drivers/net/ethernet/intel/fm10k/fm10k

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   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
   3 
   4 #ifndef _FM10K_TYPE_H_
   5 #define _FM10K_TYPE_H_
   6 
   7 /* forward declaration */
   8 struct fm10k_hw;
   9 
  10 #include <linux/types.h>
  11 #include <asm/byteorder.h>
  12 #include <linux/etherdevice.h>
  13 
  14 #include "fm10k_mbx.h"
  15 
  16 #define FM10K_DEV_ID_PF                 0x15A4
  17 #define FM10K_DEV_ID_VF                 0x15A5
  18 #define FM10K_DEV_ID_SDI_FM10420_QDA2   0x15D0
  19 #define FM10K_DEV_ID_SDI_FM10420_DA2    0x15D5
  20 
  21 #define FM10K_MAX_QUEUES                256
  22 #define FM10K_MAX_QUEUES_PF             128
  23 #define FM10K_MAX_QUEUES_POOL           16
  24 
  25 #define FM10K_48_BIT_MASK               0x0000FFFFFFFFFFFFull
  26 #define FM10K_STAT_VALID                0x80000000
  27 
  28 /* PCI Bus Info */
  29 #define FM10K_PCIE_LINK_CAP             0x7C
  30 #define FM10K_PCIE_LINK_STATUS          0x82
  31 #define FM10K_PCIE_LINK_WIDTH           0x3F0
  32 #define FM10K_PCIE_LINK_WIDTH_1         0x10
  33 #define FM10K_PCIE_LINK_WIDTH_2         0x20
  34 #define FM10K_PCIE_LINK_WIDTH_4         0x40
  35 #define FM10K_PCIE_LINK_WIDTH_8         0x80
  36 #define FM10K_PCIE_LINK_SPEED           0xF
  37 #define FM10K_PCIE_LINK_SPEED_2500      0x1
  38 #define FM10K_PCIE_LINK_SPEED_5000      0x2
  39 #define FM10K_PCIE_LINK_SPEED_8000      0x3
  40 
  41 /* PCIe payload size */
  42 #define FM10K_PCIE_DEV_CAP                      0x74
  43 #define FM10K_PCIE_DEV_CAP_PAYLOAD              0x07
  44 #define FM10K_PCIE_DEV_CAP_PAYLOAD_128          0x00
  45 #define FM10K_PCIE_DEV_CAP_PAYLOAD_256          0x01
  46 #define FM10K_PCIE_DEV_CAP_PAYLOAD_512          0x02
  47 #define FM10K_PCIE_DEV_CTRL                     0x78
  48 #define FM10K_PCIE_DEV_CTRL_PAYLOAD             0xE0
  49 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128         0x00
  50 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256         0x20
  51 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512         0x40
  52 
  53 /* PCIe MSI-X Capability info */
  54 #define FM10K_PCI_MSIX_MSG_CTRL                 0xB2
  55 #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK     0x7FF
  56 #define FM10K_MAX_MSIX_VECTORS                  256
  57 #define FM10K_MAX_VECTORS_PF                    256
  58 #define FM10K_MAX_VECTORS_POOL                  32
  59 
  60 /* PCIe SR-IOV Info */
  61 #define FM10K_PCIE_SRIOV_CTRL                   0x190
  62 #define FM10K_PCIE_SRIOV_CTRL_VFARI             0x10
  63 
  64 #define FM10K_ERR_PARAM                         -2
  65 #define FM10K_ERR_NO_RESOURCES                  -3
  66 #define FM10K_ERR_REQUESTS_PENDING              -4
  67 #define FM10K_ERR_RESET_REQUESTED               -5
  68 #define FM10K_ERR_DMA_PENDING                   -6
  69 #define FM10K_ERR_RESET_FAILED                  -7
  70 #define FM10K_ERR_INVALID_MAC_ADDR              -8
  71 #define FM10K_ERR_INVALID_VALUE                 -9
  72 #define FM10K_NOT_IMPLEMENTED                   0x7FFFFFFF
  73 
  74 /* Start of PF registers */
  75 #define FM10K_CTRL              0x0000
  76 #define FM10K_CTRL_BAR4_ALLOWED                 0x00000004
  77 
  78 #define FM10K_CTRL_EXT          0x0001
  79 #define FM10K_GCR               0x0003
  80 #define FM10K_GCR_EXT           0x0005
  81 
  82 /* Interrupt control registers */
  83 #define FM10K_EICR              0x0006
  84 #define FM10K_EICR_FAULT_MASK                   0x0000003F
  85 #define FM10K_EICR_MAILBOX                      0x00000040
  86 #define FM10K_EICR_SWITCHREADY                  0x00000080
  87 #define FM10K_EICR_SWITCHNOTREADY               0x00000100
  88 #define FM10K_EICR_SWITCHINTERRUPT              0x00000200
  89 #define FM10K_EICR_VFLR                         0x00000800
  90 #define FM10K_EICR_MAXHOLDTIME                  0x00001000
  91 #define FM10K_EIMR              0x0007
  92 #define FM10K_EIMR_PCA_FAULT                    0x00000001
  93 #define FM10K_EIMR_THI_FAULT                    0x00000010
  94 #define FM10K_EIMR_FUM_FAULT                    0x00000400
  95 #define FM10K_EIMR_MAILBOX                      0x00001000
  96 #define FM10K_EIMR_SWITCHREADY                  0x00004000
  97 #define FM10K_EIMR_SWITCHNOTREADY               0x00010000
  98 #define FM10K_EIMR_SWITCHINTERRUPT              0x00040000
  99 #define FM10K_EIMR_SRAMERROR                    0x00100000
 100 #define FM10K_EIMR_VFLR                         0x00400000
 101 #define FM10K_EIMR_MAXHOLDTIME                  0x01000000
 102 #define FM10K_EIMR_ALL                          0x55555555
 103 #define FM10K_EIMR_DISABLE(NAME)                ((FM10K_EIMR_ ## NAME) << 0)
 104 #define FM10K_EIMR_ENABLE(NAME)                 ((FM10K_EIMR_ ## NAME) << 1)
 105 #define FM10K_FAULT_ADDR_LO             0x0
 106 #define FM10K_FAULT_ADDR_HI             0x1
 107 #define FM10K_FAULT_SPECINFO            0x2
 108 #define FM10K_FAULT_FUNC                0x3
 109 #define FM10K_FAULT_SIZE                0x4
 110 #define FM10K_FAULT_FUNC_VALID                  0x00008000
 111 #define FM10K_FAULT_FUNC_PF                     0x00004000
 112 #define FM10K_FAULT_FUNC_VF_MASK                0x00003F00
 113 #define FM10K_FAULT_FUNC_VF_SHIFT               8
 114 #define FM10K_FAULT_FUNC_TYPE_MASK              0x000000FF
 115 
 116 #define FM10K_PCA_FAULT         0x0008
 117 #define FM10K_THI_FAULT         0x0010
 118 #define FM10K_FUM_FAULT         0x001C
 119 
 120 /* Rx queue timeout indicator */
 121 #define FM10K_MAXHOLDQ(_n)      ((_n) + 0x0020)
 122 
 123 /* Switch Manager info */
 124 #define FM10K_SM_AREA(_n)       ((_n) + 0x0028)
 125 
 126 /* GLORT mapping registers */
 127 #define FM10K_DGLORTMAP(_n)     ((_n) + 0x0030)
 128 #define FM10K_DGLORT_COUNT                      8
 129 #define FM10K_DGLORTMAP_MASK_SHIFT              16
 130 #define FM10K_DGLORTMAP_ANY                     0x00000000
 131 #define FM10K_DGLORTMAP_NONE                    0x0000FFFF
 132 #define FM10K_DGLORTMAP_ZERO                    0xFFFF0000
 133 #define FM10K_DGLORTDEC(_n)     ((_n) + 0x0038)
 134 #define FM10K_DGLORTDEC_VSILENGTH_SHIFT         4
 135 #define FM10K_DGLORTDEC_VSIBASE_SHIFT           7
 136 #define FM10K_DGLORTDEC_PCLENGTH_SHIFT          14
 137 #define FM10K_DGLORTDEC_QBASE_SHIFT             16
 138 #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT         24
 139 #define FM10K_DGLORTDEC_INNERRSS_ENABLE         0x08000000
 140 #define FM10K_TUNNEL_CFG        0x0040
 141 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT            16
 142 #define FM10K_TUNNEL_CFG_GENEVE 0x0041
 143 #define FM10K_SWPRI_MAP(_n)     ((_n) + 0x0050)
 144 #define FM10K_SWPRI_MAX         16
 145 #define FM10K_RSSRK(_n, _m)     (((_n) * 0x10) + (_m) + 0x0800)
 146 #define FM10K_RSSRK_SIZE        10
 147 #define FM10K_RSSRK_ENTRIES_PER_REG             4
 148 #define FM10K_RETA(_n, _m)      (((_n) * 0x20) + (_m) + 0x1000)
 149 #define FM10K_RETA_SIZE         32
 150 #define FM10K_RETA_ENTRIES_PER_REG              4
 151 #define FM10K_MAX_RSS_INDICES   128
 152 
 153 /* Rate limiting registers */
 154 #define FM10K_TC_CREDIT(_n)     ((_n) + 0x2000)
 155 #define FM10K_TC_CREDIT_CREDIT_MASK             0x001FFFFF
 156 #define FM10K_TC_MAXCREDIT(_n)  ((_n) + 0x2040)
 157 #define FM10K_TC_MAXCREDIT_64K                  0x00010000
 158 #define FM10K_TC_RATE(_n)       ((_n) + 0x2080)
 159 #define FM10K_TC_RATE_QUANTA_MASK               0x0000FFFF
 160 #define FM10K_TC_RATE_INTERVAL_4US_GEN1         0x00020000
 161 #define FM10K_TC_RATE_INTERVAL_4US_GEN2         0x00040000
 162 #define FM10K_TC_RATE_INTERVAL_4US_GEN3         0x00080000
 163 
 164 /* DMA control registers */
 165 #define FM10K_DMA_CTRL          0x20C3
 166 #define FM10K_DMA_CTRL_TX_ENABLE                0x00000001
 167 #define FM10K_DMA_CTRL_TX_ACTIVE                0x00000008
 168 #define FM10K_DMA_CTRL_RX_ENABLE                0x00000010
 169 #define FM10K_DMA_CTRL_RX_ACTIVE                0x00000080
 170 #define FM10K_DMA_CTRL_RX_DESC_SIZE             0x00000100
 171 #define FM10K_DMA_CTRL_MINMSS_64                0x00008000
 172 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3        0x04800000
 173 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2        0x04000000
 174 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1        0x03800000
 175 #define FM10K_DMA_CTRL_DATAPATH_RESET           0x20000000
 176 #define FM10K_DMA_CTRL_32_DESC                  0x00000000
 177 
 178 #define FM10K_DMA_CTRL2         0x20C4
 179 #define FM10K_DMA_CTRL2_SWITCH_READY            0x00002000
 180 
 181 /* TSO flags configuration
 182  * First packet contains all flags except for fin and psh
 183  * Middle packet contains only urg and ack
 184  * Last packet contains urg, ack, fin, and psh
 185  */
 186 #define FM10K_TSO_FLAGS_LOW             0x00300FF6
 187 #define FM10K_TSO_FLAGS_HI              0x00000039
 188 #define FM10K_DTXTCPFLGL        0x20C5
 189 #define FM10K_DTXTCPFLGH        0x20C6
 190 
 191 #define FM10K_TPH_CTRL          0x20C7
 192 #define FM10K_MRQC(_n)          ((_n) + 0x2100)
 193 #define FM10K_MRQC_TCP_IPV4                     0x00000001
 194 #define FM10K_MRQC_IPV4                         0x00000002
 195 #define FM10K_MRQC_IPV6                         0x00000010
 196 #define FM10K_MRQC_TCP_IPV6                     0x00000020
 197 #define FM10K_MRQC_UDP_IPV4                     0x00000040
 198 #define FM10K_MRQC_UDP_IPV6                     0x00000080
 199 
 200 #define FM10K_TQMAP(_n)         ((_n) + 0x2800)
 201 #define FM10K_TQMAP_TABLE_SIZE                  2048
 202 #define FM10K_RQMAP(_n)         ((_n) + 0x3000)
 203 
 204 /* Hardware Statistics */
 205 #define FM10K_STATS_TIMEOUT             0x3800
 206 #define FM10K_STATS_UR                  0x3801
 207 #define FM10K_STATS_CA                  0x3802
 208 #define FM10K_STATS_UM                  0x3803
 209 #define FM10K_STATS_XEC                 0x3804
 210 #define FM10K_STATS_VLAN_DROP           0x3805
 211 #define FM10K_STATS_LOOPBACK_DROP       0x3806
 212 #define FM10K_STATS_NODESC_DROP         0x3807
 213 
 214 /* PCIe state registers */
 215 #define FM10K_PHYADDR           0x381C
 216 
 217 /* Rx ring registers */
 218 #define FM10K_RDBAL(_n)         ((0x40 * (_n)) + 0x4000)
 219 #define FM10K_RDBAH(_n)         ((0x40 * (_n)) + 0x4001)
 220 #define FM10K_RDLEN(_n)         ((0x40 * (_n)) + 0x4002)
 221 #define FM10K_TPH_RXCTRL(_n)    ((0x40 * (_n)) + 0x4003)
 222 #define FM10K_TPH_RXCTRL_DESC_TPHEN             0x00000020
 223 #define FM10K_TPH_RXCTRL_DESC_RROEN             0x00000200
 224 #define FM10K_TPH_RXCTRL_DATA_WROEN             0x00002000
 225 #define FM10K_TPH_RXCTRL_HDR_WROEN              0x00008000
 226 #define FM10K_RDH(_n)           ((0x40 * (_n)) + 0x4004)
 227 #define FM10K_RDT(_n)           ((0x40 * (_n)) + 0x4005)
 228 #define FM10K_RXQCTL(_n)        ((0x40 * (_n)) + 0x4006)
 229 #define FM10K_RXQCTL_ENABLE                     0x00000001
 230 #define FM10K_RXQCTL_PF                         0x000000FC
 231 #define FM10K_RXQCTL_VF_SHIFT                   2
 232 #define FM10K_RXQCTL_VF                         0x00000100
 233 #define FM10K_RXQCTL_ID_MASK    (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF)
 234 #define FM10K_RXDCTL(_n)        ((0x40 * (_n)) + 0x4007)
 235 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY       0x00000001
 236 #define FM10K_RXDCTL_DROP_ON_EMPTY              0x00000200
 237 #define FM10K_RXINT(_n)         ((0x40 * (_n)) + 0x4008)
 238 #define FM10K_SRRCTL(_n)        ((0x40 * (_n)) + 0x4009)
 239 #define FM10K_SRRCTL_BSIZEPKT_SHIFT             8 /* shift _right_ */
 240 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS          0x40000000
 241 #define FM10K_SRRCTL_BUFFER_CHAINING_EN         0x80000000
 242 
 243 /* Rx Statistics */
 244 #define FM10K_QPRC(_n)          ((0x40 * (_n)) + 0x400A)
 245 #define FM10K_QPRDC(_n)         ((0x40 * (_n)) + 0x400B)
 246 #define FM10K_QBRC_L(_n)        ((0x40 * (_n)) + 0x400C)
 247 #define FM10K_QBRC_H(_n)        ((0x40 * (_n)) + 0x400D)
 248 
 249 /* Rx GLORT register */
 250 #define FM10K_RX_SGLORT(_n)             ((0x40 * (_n)) + 0x400E)
 251 
 252 /* Tx ring registers */
 253 #define FM10K_TDBAL(_n)         ((0x40 * (_n)) + 0x8000)
 254 #define FM10K_TDBAH(_n)         ((0x40 * (_n)) + 0x8001)
 255 #define FM10K_TDLEN(_n)         ((0x40 * (_n)) + 0x8002)
 256 /* When fist initialized, VFs need to know the Interrupt Throttle Rate (ITR)
 257  * scale which is based on the PCIe speed but the speed information in the PCI
 258  * configuration space may not be accurate. The PF already knows the ITR scale
 259  * but there is no defined method to pass that information from the PF to the
 260  * VF. This is accomplished during VF initialization by temporarily co-opting
 261  * the yet-to-be-used TDLEN register to have the PF store the ITR shift for
 262  * the VF to retrieve before the VF needs to use the TDLEN register for its
 263  * intended purpose, i.e. before the Tx resources are allocated.
 264  */
 265 #define FM10K_TDLEN_ITR_SCALE_SHIFT             9
 266 #define FM10K_TDLEN_ITR_SCALE_MASK              0x00000E00
 267 #define FM10K_TDLEN_ITR_SCALE_GEN1              2
 268 #define FM10K_TDLEN_ITR_SCALE_GEN2              1
 269 #define FM10K_TDLEN_ITR_SCALE_GEN3              0
 270 #define FM10K_TPH_TXCTRL(_n)    ((0x40 * (_n)) + 0x8003)
 271 #define FM10K_TPH_TXCTRL_DESC_TPHEN             0x00000020
 272 #define FM10K_TPH_TXCTRL_DESC_RROEN             0x00000200
 273 #define FM10K_TPH_TXCTRL_DESC_WROEN             0x00000800
 274 #define FM10K_TPH_TXCTRL_DATA_RROEN             0x00002000
 275 #define FM10K_TDH(_n)           ((0x40 * (_n)) + 0x8004)
 276 #define FM10K_TDT(_n)           ((0x40 * (_n)) + 0x8005)
 277 #define FM10K_TXDCTL(_n)        ((0x40 * (_n)) + 0x8006)
 278 #define FM10K_TXDCTL_ENABLE                     0x00004000
 279 #define FM10K_TXDCTL_MAX_TIME_SHIFT             16
 280 #define FM10K_TXQCTL(_n)        ((0x40 * (_n)) + 0x8007)
 281 #define FM10K_TXQCTL_PF                         0x0000003F
 282 #define FM10K_TXQCTL_VF                         0x00000040
 283 #define FM10K_TXQCTL_ID_MASK    (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF)
 284 #define FM10K_TXQCTL_PC_SHIFT                   7
 285 #define FM10K_TXQCTL_PC_MASK                    0x00000380
 286 #define FM10K_TXQCTL_TC_SHIFT                   10
 287 #define FM10K_TXQCTL_VID_SHIFT                  16
 288 #define FM10K_TXQCTL_VID_MASK                   0x0FFF0000
 289 #define FM10K_TXQCTL_UNLIMITED_BW               0x10000000
 290 #define FM10K_TXINT(_n)         ((0x40 * (_n)) + 0x8008)
 291 
 292 /* Tx Statistics */
 293 #define FM10K_QPTC(_n)          ((0x40 * (_n)) + 0x8009)
 294 #define FM10K_QBTC_L(_n)        ((0x40 * (_n)) + 0x800A)
 295 #define FM10K_QBTC_H(_n)        ((0x40 * (_n)) + 0x800B)
 296 
 297 /* Tx Push registers */
 298 #define FM10K_TQDLOC(_n)        ((0x40 * (_n)) + 0x800C)
 299 #define FM10K_TQDLOC_BASE_32_DESC               0x08
 300 #define FM10K_TQDLOC_SIZE_32_DESC               0x00050000
 301 
 302 /* Tx GLORT registers */
 303 #define FM10K_TX_SGLORT(_n)     ((0x40 * (_n)) + 0x800D)
 304 #define FM10K_PFVTCTL(_n)       ((0x40 * (_n)) + 0x800E)
 305 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE          0x00000001
 306 
 307 /* Interrupt moderation and control registers */
 308 #define FM10K_INT_MAP(_n)       ((_n) + 0x10080)
 309 #define FM10K_INT_MAP_TIMER0                    0x00000000
 310 #define FM10K_INT_MAP_TIMER1                    0x00000100
 311 #define FM10K_INT_MAP_IMMEDIATE                 0x00000200
 312 #define FM10K_INT_MAP_DISABLE                   0x00000300
 313 #define FM10K_MSIX_VECTOR_MASK(_n)      ((0x4 * (_n)) + 0x11003)
 314 #define FM10K_INT_CTRL          0x12000
 315 #define FM10K_INT_CTRL_ENABLEMODERATOR          0x00000400
 316 #define FM10K_ITR(_n)           ((_n) + 0x12400)
 317 #define FM10K_ITR_INTERVAL1_SHIFT               12
 318 #define FM10K_ITR_PENDING2                      0x10000000
 319 #define FM10K_ITR_AUTOMASK                      0x20000000
 320 #define FM10K_ITR_MASK_SET                      0x40000000
 321 #define FM10K_ITR_MASK_CLEAR                    0x80000000
 322 #define FM10K_ITR2(_n)          ((0x2 * (_n)) + 0x12800)
 323 #define FM10K_ITR_REG_COUNT                     768
 324 #define FM10K_ITR_REG_COUNT_PF                  256
 325 
 326 /* Switch manager interrupt registers */
 327 #define FM10K_IP                0x13000
 328 #define FM10K_IP_NOTINRESET                     0x00000100
 329 
 330 /* VLAN registers */
 331 #define FM10K_VLAN_TABLE(_n, _m)        ((0x80 * (_n)) + (_m) + 0x14000)
 332 #define FM10K_VLAN_TABLE_SIZE                   128
 333 
 334 /* VLAN specific message offsets */
 335 #define FM10K_VLAN_TABLE_VID_MAX                4096
 336 #define FM10K_VLAN_TABLE_VSI_MAX                64
 337 #define FM10K_VLAN_LENGTH_SHIFT                 16
 338 #define FM10K_VLAN_CLEAR                        BIT(15)
 339 #define FM10K_VLAN_OVERRIDE                     FM10K_VLAN_CLEAR
 340 #define FM10K_VLAN_ALL \
 341         ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT)
 342 
 343 /* VF FLR event notification registers */
 344 #define FM10K_PFVFLRE(_n)       ((0x1 * (_n)) + 0x18844)
 345 #define FM10K_PFVFLREC(_n)      ((0x1 * (_n)) + 0x18846)
 346 
 347 /* Defines for size of uncacheable memories */
 348 #define FM10K_UC_ADDR_START     0x000000        /* start of standard regs */
 349 #define FM10K_UC_ADDR_END       0x100000        /* end of standard regs */
 350 #define FM10K_UC_ADDR_SIZE      (FM10K_UC_ADDR_END - FM10K_UC_ADDR_START)
 351 
 352 /* Define timeouts for resets and disables */
 353 #define FM10K_QUEUE_DISABLE_TIMEOUT             100
 354 #define FM10K_RESET_TIMEOUT                     150
 355 
 356 /* Maximum supported combined inner and outer header length for encapsulation */
 357 #define FM10K_TUNNEL_HEADER_LENGTH      184
 358 
 359 /* VF registers */
 360 #define FM10K_VFCTRL            0x00000
 361 #define FM10K_VFCTRL_RST                        0x00000008
 362 #define FM10K_VFINT_MAP         0x00030
 363 #define FM10K_VFSYSTIME         0x00040
 364 #define FM10K_VFITR(_n)         ((_n) + 0x00060)
 365 
 366 enum fm10k_int_source {
 367         fm10k_int_mailbox               = 0,
 368         fm10k_int_pcie_fault            = 1,
 369         fm10k_int_switch_up_down        = 2,
 370         fm10k_int_switch_event          = 3,
 371         fm10k_int_sram                  = 4,
 372         fm10k_int_vflr                  = 5,
 373         fm10k_int_max_hold_time         = 6,
 374         fm10k_int_sources_max_pf
 375 };
 376 
 377 /* PCIe bus speeds */
 378 enum fm10k_bus_speed {
 379         fm10k_bus_speed_unknown = 0,
 380         fm10k_bus_speed_2500    = 2500,
 381         fm10k_bus_speed_5000    = 5000,
 382         fm10k_bus_speed_8000    = 8000,
 383         fm10k_bus_speed_reserved
 384 };
 385 
 386 /* PCIe bus widths */
 387 enum fm10k_bus_width {
 388         fm10k_bus_width_unknown = 0,
 389         fm10k_bus_width_pcie_x1 = 1,
 390         fm10k_bus_width_pcie_x2 = 2,
 391         fm10k_bus_width_pcie_x4 = 4,
 392         fm10k_bus_width_pcie_x8 = 8,
 393         fm10k_bus_width_reserved
 394 };
 395 
 396 /* PCIe payload sizes */
 397 enum fm10k_bus_payload {
 398         fm10k_bus_payload_unknown = 0,
 399         fm10k_bus_payload_128     = 1,
 400         fm10k_bus_payload_256     = 2,
 401         fm10k_bus_payload_512     = 3,
 402         fm10k_bus_payload_reserved
 403 };
 404 
 405 /* Bus parameters */
 406 struct fm10k_bus_info {
 407         enum fm10k_bus_speed speed;
 408         enum fm10k_bus_width width;
 409         enum fm10k_bus_payload payload;
 410 };
 411 
 412 /* Statistics related declarations */
 413 struct fm10k_hw_stat {
 414         u64 count;
 415         u32 base_l;
 416         u32 base_h;
 417 };
 418 
 419 struct fm10k_hw_stats_q {
 420         struct fm10k_hw_stat tx_bytes;
 421         struct fm10k_hw_stat tx_packets;
 422 #define tx_stats_idx    tx_packets.base_h
 423         struct fm10k_hw_stat rx_bytes;
 424         struct fm10k_hw_stat rx_packets;
 425 #define rx_stats_idx    rx_packets.base_h
 426         struct fm10k_hw_stat rx_drops;
 427 };
 428 
 429 struct fm10k_hw_stats {
 430         struct fm10k_hw_stat    timeout;
 431 #define stats_idx       timeout.base_h
 432         struct fm10k_hw_stat    ur;
 433         struct fm10k_hw_stat    ca;
 434         struct fm10k_hw_stat    um;
 435         struct fm10k_hw_stat    xec;
 436         struct fm10k_hw_stat    vlan_drop;
 437         struct fm10k_hw_stat    loopback_drop;
 438         struct fm10k_hw_stat    nodesc_drop;
 439         struct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF];
 440 };
 441 
 442 /* Establish DGLORT feature priority */
 443 enum fm10k_dglortdec_idx {
 444         fm10k_dglort_default    = 0,
 445         fm10k_dglort_vf_rsvd0   = 1,
 446         fm10k_dglort_vf_rss     = 2,
 447         fm10k_dglort_pf_rsvd0   = 3,
 448         fm10k_dglort_pf_queue   = 4,
 449         fm10k_dglort_pf_vsi     = 5,
 450         fm10k_dglort_pf_rsvd1   = 6,
 451         fm10k_dglort_pf_rss     = 7
 452 };
 453 
 454 struct fm10k_dglort_cfg {
 455         u16 glort;      /* GLORT base */
 456         u16 queue_b;    /* Base value for queue */
 457         u8  vsi_b;      /* Base value for VSI */
 458         u8  idx;        /* index of DGLORTDEC entry */
 459         u8  rss_l;      /* RSS indices */
 460         u8  pc_l;       /* Priority Class indices */
 461         u8  vsi_l;      /* Number of bits from GLORT used to determine VSI */
 462         u8  queue_l;    /* Number of bits from GLORT used to determine queue */
 463         u8  shared_l;   /* Ignored bits from GLORT resulting in shared VSI */
 464         u8  inner_rss;  /* Boolean value if inner header is used for RSS */
 465 };
 466 
 467 enum fm10k_pca_fault {
 468         PCA_NO_FAULT,
 469         PCA_UNMAPPED_ADDR,
 470         PCA_BAD_QACCESS_PF,
 471         PCA_BAD_QACCESS_VF,
 472         PCA_MALICIOUS_REQ,
 473         PCA_POISONED_TLP,
 474         PCA_TLP_ABORT,
 475         __PCA_MAX
 476 };
 477 
 478 enum fm10k_thi_fault {
 479         THI_NO_FAULT,
 480         THI_MAL_DIS_Q_FAULT,
 481         __THI_MAX
 482 };
 483 
 484 enum fm10k_fum_fault {
 485         FUM_NO_FAULT,
 486         FUM_UNMAPPED_ADDR,
 487         FUM_POISONED_TLP,
 488         FUM_BAD_VF_QACCESS,
 489         FUM_ADD_DECODE_ERR,
 490         FUM_RO_ERROR,
 491         FUM_QPRC_CRC_ERROR,
 492         FUM_CSR_TIMEOUT,
 493         FUM_INVALID_TYPE,
 494         FUM_INVALID_LENGTH,
 495         FUM_INVALID_BE,
 496         FUM_INVALID_ALIGN,
 497         __FUM_MAX
 498 };
 499 
 500 struct fm10k_fault {
 501         u64 address;    /* Address at the time fault was detected */
 502         u32 specinfo;   /* Extra info on this fault (fault dependent) */
 503         u8 type;        /* Fault value dependent on subunit */
 504         u8 func;        /* Function number of the fault */
 505 };
 506 
 507 struct fm10k_mac_ops {
 508         /* basic bring-up and tear-down */
 509         s32 (*reset_hw)(struct fm10k_hw *);
 510         s32 (*init_hw)(struct fm10k_hw *);
 511         s32 (*start_hw)(struct fm10k_hw *);
 512         s32 (*stop_hw)(struct fm10k_hw *);
 513         s32 (*get_bus_info)(struct fm10k_hw *);
 514         s32 (*get_host_state)(struct fm10k_hw *, bool *);
 515         s32 (*request_lport_map)(struct fm10k_hw *);
 516         s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool);
 517         s32 (*read_mac_addr)(struct fm10k_hw *);
 518         s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *,
 519                               u16, bool, u8);
 520         s32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool);
 521         s32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8);
 522         void (*update_int_moderator)(struct fm10k_hw *);
 523         s32  (*update_lport_state)(struct fm10k_hw *, u16, u16, bool);
 524         void (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
 525         void (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
 526         s32 (*configure_dglort_map)(struct fm10k_hw *,
 527                                     struct fm10k_dglort_cfg *);
 528         void (*set_dma_mask)(struct fm10k_hw *, u64);
 529         s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *);
 530 };
 531 
 532 enum fm10k_mac_type {
 533         fm10k_mac_unknown = 0,
 534         fm10k_mac_pf,
 535         fm10k_mac_vf,
 536         fm10k_num_macs
 537 };
 538 
 539 struct fm10k_mac_info {
 540         struct fm10k_mac_ops ops;
 541         enum fm10k_mac_type type;
 542         u8 addr[ETH_ALEN];
 543         u8 perm_addr[ETH_ALEN];
 544         u16 default_vid;
 545         u16 max_msix_vectors;
 546         u16 max_queues;
 547         bool vlan_override;
 548         bool get_host_state;
 549         bool tx_ready;
 550         u32 dglort_map;
 551         u8 itr_scale;
 552         u64 reset_while_pending;
 553 };
 554 
 555 struct fm10k_swapi_table_info {
 556         u32 used;
 557         u32 avail;
 558 };
 559 
 560 struct fm10k_swapi_info {
 561         u32 status;
 562         struct fm10k_swapi_table_info mac;
 563         struct fm10k_swapi_table_info nexthop;
 564         struct fm10k_swapi_table_info ffu;
 565 };
 566 
 567 enum fm10k_xcast_modes {
 568         FM10K_XCAST_MODE_ALLMULTI       = 0,
 569         FM10K_XCAST_MODE_MULTI          = 1,
 570         FM10K_XCAST_MODE_PROMISC        = 2,
 571         FM10K_XCAST_MODE_NONE           = 3,
 572         FM10K_XCAST_MODE_DISABLE        = 4
 573 };
 574 
 575 #define FM10K_VF_TC_MAX         100000  /* 100,000 Mb/s aka 100Gb/s */
 576 #define FM10K_VF_TC_MIN         1       /* 1 Mb/s is the slowest rate */
 577 
 578 struct fm10k_vf_info {
 579         /* mbx must be first field in struct unless all default IOV message
 580          * handlers are redone as the assumption is that vf_info starts
 581          * at the same offset as the mailbox
 582          */
 583         struct fm10k_mbx_info   mbx;            /* PF side of VF mailbox */
 584         int                     rate;           /* Tx BW cap as defined by OS */
 585         u16                     glort;          /* resource tag for this VF */
 586         u16                     sw_vid;         /* Switch API assigned VLAN */
 587         u16                     pf_vid;         /* PF assigned Default VLAN */
 588         u8                      mac[ETH_ALEN];  /* PF Default MAC address */
 589         u8                      vsi;            /* VSI identifier */
 590         u8                      vf_idx;         /* which VF this is */
 591         u8                      vf_flags;       /* flags indicating what modes
 592                                                  * are supported for the port
 593                                                  */
 594 };
 595 
 596 #define FM10K_VF_FLAG_ALLMULTI_CAPABLE  (u8)(BIT(FM10K_XCAST_MODE_ALLMULTI))
 597 #define FM10K_VF_FLAG_MULTI_CAPABLE     (u8)(BIT(FM10K_XCAST_MODE_MULTI))
 598 #define FM10K_VF_FLAG_PROMISC_CAPABLE   (u8)(BIT(FM10K_XCAST_MODE_PROMISC))
 599 #define FM10K_VF_FLAG_NONE_CAPABLE      (u8)(BIT(FM10K_XCAST_MODE_NONE))
 600 #define FM10K_VF_FLAG_CAPABLE(vf_info)  ((vf_info)->vf_flags & (u8)0xF)
 601 #define FM10K_VF_FLAG_ENABLED(vf_info)  ((vf_info)->vf_flags >> 4)
 602 #define FM10K_VF_FLAG_SET_MODE(mode)    ((u8)0x10 << (mode))
 603 #define FM10K_VF_FLAG_SET_MODE_NONE \
 604         FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE)
 605 #define FM10K_VF_FLAG_MULTI_ENABLED \
 606         (FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \
 607          FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \
 608          FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC))
 609 
 610 struct fm10k_iov_ops {
 611         /* IOV related bring-up and tear-down */
 612         s32 (*assign_resources)(struct fm10k_hw *, u16, u16);
 613         s32 (*configure_tc)(struct fm10k_hw *, u16, int);
 614         s32 (*assign_int_moderator)(struct fm10k_hw *, u16);
 615         s32 (*assign_default_mac_vlan)(struct fm10k_hw *,
 616                                        struct fm10k_vf_info *);
 617         s32 (*reset_resources)(struct fm10k_hw *,
 618                                struct fm10k_vf_info *);
 619         s32 (*set_lport)(struct fm10k_hw *, struct fm10k_vf_info *, u16, u8);
 620         void (*reset_lport)(struct fm10k_hw *, struct fm10k_vf_info *);
 621         void (*update_stats)(struct fm10k_hw *, struct fm10k_hw_stats_q *, u16);
 622 };
 623 
 624 struct fm10k_iov_info {
 625         struct fm10k_iov_ops ops;
 626         u16 total_vfs;
 627         u16 num_vfs;
 628         u16 num_pools;
 629 };
 630 
 631 enum fm10k_devices {
 632         fm10k_device_pf,
 633         fm10k_device_vf,
 634 };
 635 
 636 struct fm10k_info {
 637         enum fm10k_mac_type             mac;
 638         s32                             (*get_invariants)(struct fm10k_hw *);
 639         const struct fm10k_mac_ops      *mac_ops;
 640         const struct fm10k_iov_ops      *iov_ops;
 641 };
 642 
 643 struct fm10k_hw {
 644         u32 __iomem *hw_addr;
 645         void *back;
 646         struct fm10k_mac_info mac;
 647         struct fm10k_bus_info bus;
 648         struct fm10k_bus_info bus_caps;
 649         struct fm10k_iov_info iov;
 650         struct fm10k_mbx_info mbx;
 651         struct fm10k_swapi_info swapi;
 652         u16 device_id;
 653         u16 vendor_id;
 654         u16 subsystem_device_id;
 655         u16 subsystem_vendor_id;
 656         u8 revision_id;
 657 };
 658 
 659 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
 660 #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE        8
 661 #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE        8
 662 
 663 /* Transmit Descriptor */
 664 struct fm10k_tx_desc {
 665         __le64 buffer_addr;     /* Address of the descriptor's data buffer */
 666         __le16 buflen;          /* Length of data to be DMAed */
 667         __le16 vlan;            /* VLAN_ID and VPRI to be inserted in FTAG */
 668         __le16 mss;             /* MSS for segmentation offload */
 669         u8 hdrlen;              /* Header size for segmentation offload */
 670         u8 flags;               /* Status and offload request flags */
 671 };
 672 
 673 /* Transmit Descriptor Cache Structure */
 674 struct fm10k_tx_desc_cache {
 675         struct fm10k_tx_desc tx_desc[256];
 676 };
 677 
 678 #define FM10K_TXD_FLAG_INT      0x01
 679 #define FM10K_TXD_FLAG_TIME     0x02
 680 #define FM10K_TXD_FLAG_CSUM     0x04
 681 #define FM10K_TXD_FLAG_FTAG     0x10
 682 #define FM10K_TXD_FLAG_RS       0x20
 683 #define FM10K_TXD_FLAG_LAST     0x40
 684 #define FM10K_TXD_FLAG_DONE     0x80
 685 
 686 /* These macros are meant to enable optimal placement of the RS and INT
 687  * bits.  It will point us to the last descriptor in the cache for either the
 688  * start of the packet, or the end of the packet.  If the index is actually
 689  * at the start of the FIFO it will point to the offset for the last index
 690  * in the FIFO to prevent an unnecessary write.
 691  */
 692 #define FM10K_TXD_WB_FIFO_SIZE  4
 693 
 694 /* Receive Descriptor - 32B */
 695 union fm10k_rx_desc {
 696         struct {
 697                 __le64 pkt_addr; /* Packet buffer address */
 698                 __le64 hdr_addr; /* Header buffer address */
 699                 __le64 reserved; /* Empty space, RSS hash */
 700                 __le64 timestamp;
 701         } q; /* Read, Writeback, 64b quad-words */
 702         struct {
 703                 __le32 data; /* RSS and header data */
 704                 __le32 rss;  /* RSS Hash */
 705                 __le32 staterr;
 706                 __le32 vlan_len;
 707                 __le32 glort; /* sglort/dglort */
 708         } d; /* Writeback, 32b double-words */
 709         struct {
 710                 __le16 pkt_info; /* RSS, Pkt type */
 711                 __le16 hdr_info; /* Splithdr, hdrlen, xC */
 712                 __le16 rss_lower;
 713                 __le16 rss_upper;
 714                 __le16 status; /* status/error */
 715                 __le16 csum_err; /* checksum or extended error value */
 716                 __le16 length; /* Packet length */
 717                 __le16 vlan; /* VLAN tag */
 718                 __le16 dglort;
 719                 __le16 sglort;
 720         } w; /* Writeback, 16b words */
 721 };
 722 
 723 #define FM10K_RXD_RSSTYPE_MASK          0x000F
 724 enum fm10k_rdesc_rss_type {
 725         FM10K_RSSTYPE_NONE      = 0x0,
 726         FM10K_RSSTYPE_IPV4_TCP  = 0x1,
 727         FM10K_RSSTYPE_IPV4      = 0x2,
 728         FM10K_RSSTYPE_IPV6_TCP  = 0x3,
 729         /* Reserved 0x4 */
 730         FM10K_RSSTYPE_IPV6      = 0x5,
 731         /* Reserved 0x6 */
 732         FM10K_RSSTYPE_IPV4_UDP  = 0x7,
 733         FM10K_RSSTYPE_IPV6_UDP  = 0x8
 734         /* Reserved 0x9 - 0xF */
 735 };
 736 
 737 #define FM10K_RXD_HDR_INFO_XC_MASK      0x0006
 738 enum fm10k_rxdesc_xc {
 739         FM10K_XC_UNICAST        = 0x0,
 740         FM10K_XC_MULTICAST      = 0x4,
 741         FM10K_XC_BROADCAST      = 0x6
 742 };
 743 
 744 #define FM10K_RXD_STATUS_DD             0x0001 /* Descriptor done */
 745 #define FM10K_RXD_STATUS_EOP            0x0002 /* End of packet */
 746 #define FM10K_RXD_STATUS_L4CS           0x0010 /* Indicates an L4 csum */
 747 #define FM10K_RXD_STATUS_L4CS2          0x0040 /* Inner header L4 csum */
 748 #define FM10K_RXD_STATUS_L4E2           0x0800 /* Inner header L4 csum err */
 749 #define FM10K_RXD_STATUS_IPE2           0x1000 /* Inner header IPv4 csum err */
 750 #define FM10K_RXD_STATUS_RXE            0x2000 /* Generic Rx error */
 751 #define FM10K_RXD_STATUS_L4E            0x4000 /* L4 csum error */
 752 #define FM10K_RXD_STATUS_IPE            0x8000 /* IPv4 csum error */
 753 
 754 #define FM10K_RXD_ERR_SWITCH_ERROR      0x0001 /* Switch found bad packet */
 755 #define FM10K_RXD_ERR_NO_DESCRIPTOR     0x0002 /* No descriptor available */
 756 #define FM10K_RXD_ERR_PP_ERROR          0x0004 /* RAM error during processing */
 757 #define FM10K_RXD_ERR_SWITCH_READY      0x0008 /* Link transition mid-packet */
 758 #define FM10K_RXD_ERR_TOO_BIG           0x0010 /* Pkt too big for single buf */
 759 
 760 struct fm10k_ftag {
 761         __be16 swpri_type_user;
 762         __be16 vlan;
 763         __be16 sglort;
 764         __be16 dglort;
 765 };
 766 
 767 #endif /* _FM10K_TYPE_H */
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root/drivers/net/ethernet/intel/fm10k/fm10k_type.h

INCLUDED FROM
