This source file includes following definitions.
- __ew32_prepare
- __ew32
- e1000_regdump
- e1000e_dump_ps_pages
- e1000e_dump
- e1000_desc_unused
- e1000e_systim_to_hwtstamp
- e1000e_rx_hwtstamp
- e1000_receive_skb
- e1000_rx_checksum
- e1000e_update_rdt_wa
- e1000e_update_tdt_wa
- e1000_alloc_rx_buffers
- e1000_alloc_rx_buffers_ps
- e1000_alloc_jumbo_rx_buffers
- e1000_rx_hash
- e1000_clean_rx_irq
- e1000_put_txbuf
- e1000_print_hw_hang
- e1000e_tx_hwtstamp_work
- e1000_clean_tx_irq
- e1000_clean_rx_irq_ps
- e1000_consume_page
- e1000_clean_jumbo_rx_irq
- e1000_clean_rx_ring
- e1000e_downshift_workaround
- e1000_intr_msi
- e1000_intr
- e1000_msix_other
- e1000_intr_msix_tx
- e1000_intr_msix_rx
- e1000_configure_msix
- e1000e_reset_interrupt_capability
- e1000e_set_interrupt_capability
- e1000_request_msix
- e1000_request_irq
- e1000_free_irq
- e1000_irq_disable
- e1000_irq_enable
- e1000e_get_hw_control
- e1000e_release_hw_control
- e1000_alloc_ring_dma
- e1000e_setup_tx_resources
- e1000e_setup_rx_resources
- e1000_clean_tx_ring
- e1000e_free_tx_resources
- e1000e_free_rx_resources
- e1000_update_itr
- e1000_set_itr
- e1000e_write_itr
- e1000_alloc_queues
- e1000e_poll
- e1000_vlan_rx_add_vid
- e1000_vlan_rx_kill_vid
- e1000e_vlan_filter_disable
- e1000e_vlan_filter_enable
- e1000e_vlan_strip_disable
- e1000e_vlan_strip_enable
- e1000_update_mng_vlan
- e1000_restore_vlan
- e1000_init_manageability_pt
- e1000_configure_tx
- e1000_setup_rctl
- e1000_configure_rx
- e1000e_write_mc_addr_list
- e1000e_write_uc_addr_list
- e1000e_set_rx_mode
- e1000e_setup_rss_hash
- e1000e_get_base_timinca
- e1000e_config_hwtstamp
- e1000_configure
- e1000e_power_up_phy
- e1000_power_down_phy
- e1000_flush_tx_ring
- e1000_flush_rx_ring
- e1000_flush_desc_rings
- e1000e_systim_reset
- e1000e_reset
- e1000e_trigger_lsc
- e1000e_up
- e1000e_flush_descriptors
- e1000e_down
- e1000e_reinit_locked
- e1000e_sanitize_systim
- e1000e_read_systim
- e1000e_cyclecounter_read
- e1000_sw_init
- e1000_intr_msi_test
- e1000_test_msi_interrupt
- e1000_test_msi
- e1000e_open
- e1000e_close
- e1000_set_mac
- e1000e_update_phy_task
- e1000_update_phy_info
- e1000e_update_phy_stats
- e1000e_update_stats
- e1000_phy_read_status
- e1000_print_link_info
- e1000e_has_link
- e1000e_enable_receives
- e1000e_check_82574_phy_workaround
- e1000_watchdog
- e1000_watchdog_task
- e1000_tso
- e1000_tx_csum
- e1000_tx_map
- e1000_tx_queue
- e1000_transfer_dhcp_info
- __e1000_maybe_stop_tx
- e1000_maybe_stop_tx
- e1000_xmit_frame
- e1000_tx_timeout
- e1000_reset_task
- e1000e_get_stats64
- e1000_change_mtu
- e1000_mii_ioctl
- e1000e_hwtstamp_set
- e1000e_hwtstamp_get
- e1000_ioctl
- e1000_init_phy_wakeup
- e1000e_flush_lpic
- e1000e_pm_freeze
- __e1000_shutdown
- __e1000e_disable_aspm
- e1000e_disable_aspm
- e1000e_disable_aspm_locked
- e1000e_pm_thaw
- __e1000_resume
- e1000e_pm_suspend
- e1000e_pm_resume
- e1000e_pm_runtime_idle
- e1000e_pm_runtime_resume
- e1000e_pm_runtime_suspend
- e1000_shutdown
- e1000_intr_msix
- e1000_netpoll
- e1000_io_error_detected
- e1000_io_slot_reset
- e1000_io_resume
- e1000_print_device_info
- e1000_eeprom_checks
- e1000_fix_features
- e1000_set_features
- e1000_probe
- e1000_remove
- e1000_init_module
- e1000_exit_module
1
2
3
4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/delay.h>
13 #include <linux/netdevice.h>
14 #include <linux/interrupt.h>
15 #include <linux/tcp.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/cpu.h>
23 #include <linux/smp.h>
24 #include <linux/pm_qos.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/aer.h>
27 #include <linux/prefetch.h>
28
29 #include "e1000.h"
30
31 #define DRV_EXTRAVERSION "-k"
32
33 #define DRV_VERSION "3.2.6" DRV_EXTRAVERSION
34 char e1000e_driver_name[] = "e1000e";
35 const char e1000e_driver_version[] = DRV_VERSION;
36
37 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
38 static int debug = -1;
39 module_param(debug, int, 0);
40 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
41
42 static const struct e1000_info *e1000_info_tbl[] = {
43 [board_82571] = &e1000_82571_info,
44 [board_82572] = &e1000_82572_info,
45 [board_82573] = &e1000_82573_info,
46 [board_82574] = &e1000_82574_info,
47 [board_82583] = &e1000_82583_info,
48 [board_80003es2lan] = &e1000_es2_info,
49 [board_ich8lan] = &e1000_ich8_info,
50 [board_ich9lan] = &e1000_ich9_info,
51 [board_ich10lan] = &e1000_ich10_info,
52 [board_pchlan] = &e1000_pch_info,
53 [board_pch2lan] = &e1000_pch2_info,
54 [board_pch_lpt] = &e1000_pch_lpt_info,
55 [board_pch_spt] = &e1000_pch_spt_info,
56 [board_pch_cnp] = &e1000_pch_cnp_info,
57 };
58
59 struct e1000_reg_info {
60 u32 ofs;
61 char *name;
62 };
63
64 static const struct e1000_reg_info e1000_reg_info_tbl[] = {
65
66 {E1000_CTRL, "CTRL"},
67 {E1000_STATUS, "STATUS"},
68 {E1000_CTRL_EXT, "CTRL_EXT"},
69
70
71 {E1000_ICR, "ICR"},
72
73
74 {E1000_RCTL, "RCTL"},
75 {E1000_RDLEN(0), "RDLEN"},
76 {E1000_RDH(0), "RDH"},
77 {E1000_RDT(0), "RDT"},
78 {E1000_RDTR, "RDTR"},
79 {E1000_RXDCTL(0), "RXDCTL"},
80 {E1000_ERT, "ERT"},
81 {E1000_RDBAL(0), "RDBAL"},
82 {E1000_RDBAH(0), "RDBAH"},
83 {E1000_RDFH, "RDFH"},
84 {E1000_RDFT, "RDFT"},
85 {E1000_RDFHS, "RDFHS"},
86 {E1000_RDFTS, "RDFTS"},
87 {E1000_RDFPC, "RDFPC"},
88
89
90 {E1000_TCTL, "TCTL"},
91 {E1000_TDBAL(0), "TDBAL"},
92 {E1000_TDBAH(0), "TDBAH"},
93 {E1000_TDLEN(0), "TDLEN"},
94 {E1000_TDH(0), "TDH"},
95 {E1000_TDT(0), "TDT"},
96 {E1000_TIDV, "TIDV"},
97 {E1000_TXDCTL(0), "TXDCTL"},
98 {E1000_TADV, "TADV"},
99 {E1000_TARC(0), "TARC"},
100 {E1000_TDFH, "TDFH"},
101 {E1000_TDFT, "TDFT"},
102 {E1000_TDFHS, "TDFHS"},
103 {E1000_TDFTS, "TDFTS"},
104 {E1000_TDFPC, "TDFPC"},
105
106
107 {0, NULL}
108 };
109
110
111
112
113
114
115
116
117
118
119
120
121
122 s32 __ew32_prepare(struct e1000_hw *hw)
123 {
124 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
125
126 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
127 udelay(50);
128
129 return i;
130 }
131
132 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
133 {
134 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
135 __ew32_prepare(hw);
136
137 writel(val, hw->hw_addr + reg);
138 }
139
140
141
142
143
144
145 static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
146 {
147 int n = 0;
148 char rname[16];
149 u32 regs[8];
150
151 switch (reginfo->ofs) {
152 case E1000_RXDCTL(0):
153 for (n = 0; n < 2; n++)
154 regs[n] = __er32(hw, E1000_RXDCTL(n));
155 break;
156 case E1000_TXDCTL(0):
157 for (n = 0; n < 2; n++)
158 regs[n] = __er32(hw, E1000_TXDCTL(n));
159 break;
160 case E1000_TARC(0):
161 for (n = 0; n < 2; n++)
162 regs[n] = __er32(hw, E1000_TARC(n));
163 break;
164 default:
165 pr_info("%-15s %08x\n",
166 reginfo->name, __er32(hw, reginfo->ofs));
167 return;
168 }
169
170 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
171 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
172 }
173
174 static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
175 struct e1000_buffer *bi)
176 {
177 int i;
178 struct e1000_ps_page *ps_page;
179
180 for (i = 0; i < adapter->rx_ps_pages; i++) {
181 ps_page = &bi->ps_pages[i];
182
183 if (ps_page->page) {
184 pr_info("packet dump for ps_page %d:\n", i);
185 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
186 16, 1, page_address(ps_page->page),
187 PAGE_SIZE, true);
188 }
189 }
190 }
191
192
193
194
195
196 static void e1000e_dump(struct e1000_adapter *adapter)
197 {
198 struct net_device *netdev = adapter->netdev;
199 struct e1000_hw *hw = &adapter->hw;
200 struct e1000_reg_info *reginfo;
201 struct e1000_ring *tx_ring = adapter->tx_ring;
202 struct e1000_tx_desc *tx_desc;
203 struct my_u0 {
204 __le64 a;
205 __le64 b;
206 } *u0;
207 struct e1000_buffer *buffer_info;
208 struct e1000_ring *rx_ring = adapter->rx_ring;
209 union e1000_rx_desc_packet_split *rx_desc_ps;
210 union e1000_rx_desc_extended *rx_desc;
211 struct my_u1 {
212 __le64 a;
213 __le64 b;
214 __le64 c;
215 __le64 d;
216 } *u1;
217 u32 staterr;
218 int i = 0;
219
220 if (!netif_msg_hw(adapter))
221 return;
222
223
224 if (netdev) {
225 dev_info(&adapter->pdev->dev, "Net device Info\n");
226 pr_info("Device Name state trans_start\n");
227 pr_info("%-15s %016lX %016lX\n", netdev->name,
228 netdev->state, dev_trans_start(netdev));
229 }
230
231
232 dev_info(&adapter->pdev->dev, "Register Dump\n");
233 pr_info(" Register Name Value\n");
234 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
235 reginfo->name; reginfo++) {
236 e1000_regdump(hw, reginfo);
237 }
238
239
240 if (!netdev || !netif_running(netdev))
241 return;
242
243 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
244 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
245 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
246 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
247 0, tx_ring->next_to_use, tx_ring->next_to_clean,
248 (unsigned long long)buffer_info->dma,
249 buffer_info->length,
250 buffer_info->next_to_watch,
251 (unsigned long long)buffer_info->time_stamp);
252
253
254 if (!netif_msg_tx_done(adapter))
255 goto rx_ring_summary;
256
257 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
287 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
288 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
289 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
290 const char *next_desc;
291 tx_desc = E1000_TX_DESC(*tx_ring, i);
292 buffer_info = &tx_ring->buffer_info[i];
293 u0 = (struct my_u0 *)tx_desc;
294 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
295 next_desc = " NTC/U";
296 else if (i == tx_ring->next_to_use)
297 next_desc = " NTU";
298 else if (i == tx_ring->next_to_clean)
299 next_desc = " NTC";
300 else
301 next_desc = "";
302 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
303 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
304 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
305 i,
306 (unsigned long long)le64_to_cpu(u0->a),
307 (unsigned long long)le64_to_cpu(u0->b),
308 (unsigned long long)buffer_info->dma,
309 buffer_info->length, buffer_info->next_to_watch,
310 (unsigned long long)buffer_info->time_stamp,
311 buffer_info->skb, next_desc);
312
313 if (netif_msg_pktdata(adapter) && buffer_info->skb)
314 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
315 16, 1, buffer_info->skb->data,
316 buffer_info->skb->len, true);
317 }
318
319
320 rx_ring_summary:
321 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
322 pr_info("Queue [NTU] [NTC]\n");
323 pr_info(" %5d %5X %5X\n",
324 0, rx_ring->next_to_use, rx_ring->next_to_clean);
325
326
327 if (!netif_msg_rx_status(adapter))
328 return;
329
330 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
331 switch (adapter->rx_ps_pages) {
332 case 1:
333 case 2:
334 case 3:
335
336
337
338
339
340
341
342
343
344
345
346
347 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
348
349
350
351
352
353
354
355
356
357
358
359 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
360 for (i = 0; i < rx_ring->count; i++) {
361 const char *next_desc;
362 buffer_info = &rx_ring->buffer_info[i];
363 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
364 u1 = (struct my_u1 *)rx_desc_ps;
365 staterr =
366 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
367
368 if (i == rx_ring->next_to_use)
369 next_desc = " NTU";
370 else if (i == rx_ring->next_to_clean)
371 next_desc = " NTC";
372 else
373 next_desc = "";
374
375 if (staterr & E1000_RXD_STAT_DD) {
376
377 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
378 "RWB", i,
379 (unsigned long long)le64_to_cpu(u1->a),
380 (unsigned long long)le64_to_cpu(u1->b),
381 (unsigned long long)le64_to_cpu(u1->c),
382 (unsigned long long)le64_to_cpu(u1->d),
383 buffer_info->skb, next_desc);
384 } else {
385 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
386 "R ", i,
387 (unsigned long long)le64_to_cpu(u1->a),
388 (unsigned long long)le64_to_cpu(u1->b),
389 (unsigned long long)le64_to_cpu(u1->c),
390 (unsigned long long)le64_to_cpu(u1->d),
391 (unsigned long long)buffer_info->dma,
392 buffer_info->skb, next_desc);
393
394 if (netif_msg_pktdata(adapter))
395 e1000e_dump_ps_pages(adapter,
396 buffer_info);
397 }
398 }
399 break;
400 default:
401 case 0:
402
403
404
405
406
407
408
409
410 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
411
412
413
414
415
416
417
418
419
420
421
422
423
424 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
425
426 for (i = 0; i < rx_ring->count; i++) {
427 const char *next_desc;
428
429 buffer_info = &rx_ring->buffer_info[i];
430 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
431 u1 = (struct my_u1 *)rx_desc;
432 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
433
434 if (i == rx_ring->next_to_use)
435 next_desc = " NTU";
436 else if (i == rx_ring->next_to_clean)
437 next_desc = " NTC";
438 else
439 next_desc = "";
440
441 if (staterr & E1000_RXD_STAT_DD) {
442
443 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
444 "RWB", i,
445 (unsigned long long)le64_to_cpu(u1->a),
446 (unsigned long long)le64_to_cpu(u1->b),
447 buffer_info->skb, next_desc);
448 } else {
449 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
450 "R ", i,
451 (unsigned long long)le64_to_cpu(u1->a),
452 (unsigned long long)le64_to_cpu(u1->b),
453 (unsigned long long)buffer_info->dma,
454 buffer_info->skb, next_desc);
455
456 if (netif_msg_pktdata(adapter) &&
457 buffer_info->skb)
458 print_hex_dump(KERN_INFO, "",
459 DUMP_PREFIX_ADDRESS, 16,
460 1,
461 buffer_info->skb->data,
462 adapter->rx_buffer_len,
463 true);
464 }
465 }
466 }
467 }
468
469
470
471
472 static int e1000_desc_unused(struct e1000_ring *ring)
473 {
474 if (ring->next_to_clean > ring->next_to_use)
475 return ring->next_to_clean - ring->next_to_use - 1;
476
477 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
478 }
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494 static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
495 struct skb_shared_hwtstamps *hwtstamps,
496 u64 systim)
497 {
498 u64 ns;
499 unsigned long flags;
500
501 spin_lock_irqsave(&adapter->systim_lock, flags);
502 ns = timecounter_cyc2time(&adapter->tc, systim);
503 spin_unlock_irqrestore(&adapter->systim_lock, flags);
504
505 memset(hwtstamps, 0, sizeof(*hwtstamps));
506 hwtstamps->hwtstamp = ns_to_ktime(ns);
507 }
508
509
510
511
512
513
514
515
516
517
518
519 static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
520 struct sk_buff *skb)
521 {
522 struct e1000_hw *hw = &adapter->hw;
523 u64 rxstmp;
524
525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
526 !(status & E1000_RXDEXT_STATERR_TST) ||
527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
528 return;
529
530
531
532
533
534
535
536
537 rxstmp = (u64)er32(RXSTMPL);
538 rxstmp |= (u64)er32(RXSTMPH) << 32;
539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
540
541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
542 }
543
544
545
546
547
548
549
550
551 static void e1000_receive_skb(struct e1000_adapter *adapter,
552 struct net_device *netdev, struct sk_buff *skb,
553 u32 staterr, __le16 vlan)
554 {
555 u16 tag = le16_to_cpu(vlan);
556
557 e1000e_rx_hwtstamp(adapter, staterr, skb);
558
559 skb->protocol = eth_type_trans(skb, netdev);
560
561 if (staterr & E1000_RXD_STAT_VP)
562 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
563
564 napi_gro_receive(&adapter->napi, skb);
565 }
566
567
568
569
570
571
572
573
574 static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
575 struct sk_buff *skb)
576 {
577 u16 status = (u16)status_err;
578 u8 errors = (u8)(status_err >> 24);
579
580 skb_checksum_none_assert(skb);
581
582
583 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
584 return;
585
586
587 if (status & E1000_RXD_STAT_IXSM)
588 return;
589
590
591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
592
593 adapter->hw_csum_err++;
594 return;
595 }
596
597
598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
599 return;
600
601
602 skb->ip_summed = CHECKSUM_UNNECESSARY;
603 adapter->hw_csum_good++;
604 }
605
606 static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
607 {
608 struct e1000_adapter *adapter = rx_ring->adapter;
609 struct e1000_hw *hw = &adapter->hw;
610 s32 ret_val = __ew32_prepare(hw);
611
612 writel(i, rx_ring->tail);
613
614 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
615 u32 rctl = er32(RCTL);
616
617 ew32(RCTL, rctl & ~E1000_RCTL_EN);
618 e_err("ME firmware caused invalid RDT - resetting\n");
619 schedule_work(&adapter->reset_task);
620 }
621 }
622
623 static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
624 {
625 struct e1000_adapter *adapter = tx_ring->adapter;
626 struct e1000_hw *hw = &adapter->hw;
627 s32 ret_val = __ew32_prepare(hw);
628
629 writel(i, tx_ring->tail);
630
631 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
632 u32 tctl = er32(TCTL);
633
634 ew32(TCTL, tctl & ~E1000_TCTL_EN);
635 e_err("ME firmware caused invalid TDT - resetting\n");
636 schedule_work(&adapter->reset_task);
637 }
638 }
639
640
641
642
643
644 static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
645 int cleaned_count, gfp_t gfp)
646 {
647 struct e1000_adapter *adapter = rx_ring->adapter;
648 struct net_device *netdev = adapter->netdev;
649 struct pci_dev *pdev = adapter->pdev;
650 union e1000_rx_desc_extended *rx_desc;
651 struct e1000_buffer *buffer_info;
652 struct sk_buff *skb;
653 unsigned int i;
654 unsigned int bufsz = adapter->rx_buffer_len;
655
656 i = rx_ring->next_to_use;
657 buffer_info = &rx_ring->buffer_info[i];
658
659 while (cleaned_count--) {
660 skb = buffer_info->skb;
661 if (skb) {
662 skb_trim(skb, 0);
663 goto map_skb;
664 }
665
666 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
667 if (!skb) {
668
669 adapter->alloc_rx_buff_failed++;
670 break;
671 }
672
673 buffer_info->skb = skb;
674 map_skb:
675 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
676 adapter->rx_buffer_len,
677 DMA_FROM_DEVICE);
678 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
679 dev_err(&pdev->dev, "Rx DMA map failed\n");
680 adapter->rx_dma_failed++;
681 break;
682 }
683
684 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
685 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
686
687 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
688
689
690
691
692
693 wmb();
694 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
695 e1000e_update_rdt_wa(rx_ring, i);
696 else
697 writel(i, rx_ring->tail);
698 }
699 i++;
700 if (i == rx_ring->count)
701 i = 0;
702 buffer_info = &rx_ring->buffer_info[i];
703 }
704
705 rx_ring->next_to_use = i;
706 }
707
708
709
710
711
712 static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
713 int cleaned_count, gfp_t gfp)
714 {
715 struct e1000_adapter *adapter = rx_ring->adapter;
716 struct net_device *netdev = adapter->netdev;
717 struct pci_dev *pdev = adapter->pdev;
718 union e1000_rx_desc_packet_split *rx_desc;
719 struct e1000_buffer *buffer_info;
720 struct e1000_ps_page *ps_page;
721 struct sk_buff *skb;
722 unsigned int i, j;
723
724 i = rx_ring->next_to_use;
725 buffer_info = &rx_ring->buffer_info[i];
726
727 while (cleaned_count--) {
728 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
729
730 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
731 ps_page = &buffer_info->ps_pages[j];
732 if (j >= adapter->rx_ps_pages) {
733
734 rx_desc->read.buffer_addr[j + 1] =
735 ~cpu_to_le64(0);
736 continue;
737 }
738 if (!ps_page->page) {
739 ps_page->page = alloc_page(gfp);
740 if (!ps_page->page) {
741 adapter->alloc_rx_buff_failed++;
742 goto no_buffers;
743 }
744 ps_page->dma = dma_map_page(&pdev->dev,
745 ps_page->page,
746 0, PAGE_SIZE,
747 DMA_FROM_DEVICE);
748 if (dma_mapping_error(&pdev->dev,
749 ps_page->dma)) {
750 dev_err(&adapter->pdev->dev,
751 "Rx DMA page map failed\n");
752 adapter->rx_dma_failed++;
753 goto no_buffers;
754 }
755 }
756
757
758
759
760 rx_desc->read.buffer_addr[j + 1] =
761 cpu_to_le64(ps_page->dma);
762 }
763
764 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
765 gfp);
766
767 if (!skb) {
768 adapter->alloc_rx_buff_failed++;
769 break;
770 }
771
772 buffer_info->skb = skb;
773 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
774 adapter->rx_ps_bsize0,
775 DMA_FROM_DEVICE);
776 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
777 dev_err(&pdev->dev, "Rx DMA map failed\n");
778 adapter->rx_dma_failed++;
779
780 dev_kfree_skb_any(skb);
781 buffer_info->skb = NULL;
782 break;
783 }
784
785 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
786
787 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
788
789
790
791
792
793 wmb();
794 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
795 e1000e_update_rdt_wa(rx_ring, i << 1);
796 else
797 writel(i << 1, rx_ring->tail);
798 }
799
800 i++;
801 if (i == rx_ring->count)
802 i = 0;
803 buffer_info = &rx_ring->buffer_info[i];
804 }
805
806 no_buffers:
807 rx_ring->next_to_use = i;
808 }
809
810
811
812
813
814
815
816 static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
817 int cleaned_count, gfp_t gfp)
818 {
819 struct e1000_adapter *adapter = rx_ring->adapter;
820 struct net_device *netdev = adapter->netdev;
821 struct pci_dev *pdev = adapter->pdev;
822 union e1000_rx_desc_extended *rx_desc;
823 struct e1000_buffer *buffer_info;
824 struct sk_buff *skb;
825 unsigned int i;
826 unsigned int bufsz = 256 - 16;
827
828 i = rx_ring->next_to_use;
829 buffer_info = &rx_ring->buffer_info[i];
830
831 while (cleaned_count--) {
832 skb = buffer_info->skb;
833 if (skb) {
834 skb_trim(skb, 0);
835 goto check_page;
836 }
837
838 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
839 if (unlikely(!skb)) {
840
841 adapter->alloc_rx_buff_failed++;
842 break;
843 }
844
845 buffer_info->skb = skb;
846 check_page:
847
848 if (!buffer_info->page) {
849 buffer_info->page = alloc_page(gfp);
850 if (unlikely(!buffer_info->page)) {
851 adapter->alloc_rx_buff_failed++;
852 break;
853 }
854 }
855
856 if (!buffer_info->dma) {
857 buffer_info->dma = dma_map_page(&pdev->dev,
858 buffer_info->page, 0,
859 PAGE_SIZE,
860 DMA_FROM_DEVICE);
861 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
862 adapter->alloc_rx_buff_failed++;
863 break;
864 }
865 }
866
867 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
868 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
869
870 if (unlikely(++i == rx_ring->count))
871 i = 0;
872 buffer_info = &rx_ring->buffer_info[i];
873 }
874
875 if (likely(rx_ring->next_to_use != i)) {
876 rx_ring->next_to_use = i;
877 if (unlikely(i-- == 0))
878 i = (rx_ring->count - 1);
879
880
881
882
883
884
885 wmb();
886 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
887 e1000e_update_rdt_wa(rx_ring, i);
888 else
889 writel(i, rx_ring->tail);
890 }
891 }
892
893 static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
894 struct sk_buff *skb)
895 {
896 if (netdev->features & NETIF_F_RXHASH)
897 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
898 }
899
900
901
902
903
904
905
906
907 static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
908 int work_to_do)
909 {
910 struct e1000_adapter *adapter = rx_ring->adapter;
911 struct net_device *netdev = adapter->netdev;
912 struct pci_dev *pdev = adapter->pdev;
913 struct e1000_hw *hw = &adapter->hw;
914 union e1000_rx_desc_extended *rx_desc, *next_rxd;
915 struct e1000_buffer *buffer_info, *next_buffer;
916 u32 length, staterr;
917 unsigned int i;
918 int cleaned_count = 0;
919 bool cleaned = false;
920 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
921
922 i = rx_ring->next_to_clean;
923 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
924 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
925 buffer_info = &rx_ring->buffer_info[i];
926
927 while (staterr & E1000_RXD_STAT_DD) {
928 struct sk_buff *skb;
929
930 if (*work_done >= work_to_do)
931 break;
932 (*work_done)++;
933 dma_rmb();
934
935 skb = buffer_info->skb;
936 buffer_info->skb = NULL;
937
938 prefetch(skb->data - NET_IP_ALIGN);
939
940 i++;
941 if (i == rx_ring->count)
942 i = 0;
943 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
944 prefetch(next_rxd);
945
946 next_buffer = &rx_ring->buffer_info[i];
947
948 cleaned = true;
949 cleaned_count++;
950 dma_unmap_single(&pdev->dev, buffer_info->dma,
951 adapter->rx_buffer_len, DMA_FROM_DEVICE);
952 buffer_info->dma = 0;
953
954 length = le16_to_cpu(rx_desc->wb.upper.length);
955
956
957
958
959
960
961
962 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
963 adapter->flags2 |= FLAG2_IS_DISCARDING;
964
965 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
966
967 e_dbg("Receive packet consumed multiple buffers\n");
968
969 buffer_info->skb = skb;
970 if (staterr & E1000_RXD_STAT_EOP)
971 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
972 goto next_desc;
973 }
974
975 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
976 !(netdev->features & NETIF_F_RXALL))) {
977
978 buffer_info->skb = skb;
979 goto next_desc;
980 }
981
982
983 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
984
985
986
987
988 if (netdev->features & NETIF_F_RXFCS)
989 total_rx_bytes -= 4;
990 else
991 length -= 4;
992 }
993
994 total_rx_bytes += length;
995 total_rx_packets++;
996
997
998
999
1000
1001 if (length < copybreak) {
1002 struct sk_buff *new_skb =
1003 napi_alloc_skb(&adapter->napi, length);
1004 if (new_skb) {
1005 skb_copy_to_linear_data_offset(new_skb,
1006 -NET_IP_ALIGN,
1007 (skb->data -
1008 NET_IP_ALIGN),
1009 (length +
1010 NET_IP_ALIGN));
1011
1012 buffer_info->skb = skb;
1013 skb = new_skb;
1014 }
1015
1016 }
1017
1018 skb_put(skb, length);
1019
1020
1021 e1000_rx_checksum(adapter, staterr, skb);
1022
1023 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1024
1025 e1000_receive_skb(adapter, netdev, skb, staterr,
1026 rx_desc->wb.upper.vlan);
1027
1028 next_desc:
1029 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1030
1031
1032 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1033 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1034 GFP_ATOMIC);
1035 cleaned_count = 0;
1036 }
1037
1038
1039 rx_desc = next_rxd;
1040 buffer_info = next_buffer;
1041
1042 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1043 }
1044 rx_ring->next_to_clean = i;
1045
1046 cleaned_count = e1000_desc_unused(rx_ring);
1047 if (cleaned_count)
1048 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1049
1050 adapter->total_rx_bytes += total_rx_bytes;
1051 adapter->total_rx_packets += total_rx_packets;
1052 return cleaned;
1053 }
1054
1055 static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1056 struct e1000_buffer *buffer_info,
1057 bool drop)
1058 {
1059 struct e1000_adapter *adapter = tx_ring->adapter;
1060
1061 if (buffer_info->dma) {
1062 if (buffer_info->mapped_as_page)
1063 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1064 buffer_info->length, DMA_TO_DEVICE);
1065 else
1066 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1067 buffer_info->length, DMA_TO_DEVICE);
1068 buffer_info->dma = 0;
1069 }
1070 if (buffer_info->skb) {
1071 if (drop)
1072 dev_kfree_skb_any(buffer_info->skb);
1073 else
1074 dev_consume_skb_any(buffer_info->skb);
1075 buffer_info->skb = NULL;
1076 }
1077 buffer_info->time_stamp = 0;
1078 }
1079
1080 static void e1000_print_hw_hang(struct work_struct *work)
1081 {
1082 struct e1000_adapter *adapter = container_of(work,
1083 struct e1000_adapter,
1084 print_hang_task);
1085 struct net_device *netdev = adapter->netdev;
1086 struct e1000_ring *tx_ring = adapter->tx_ring;
1087 unsigned int i = tx_ring->next_to_clean;
1088 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1089 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1090 struct e1000_hw *hw = &adapter->hw;
1091 u16 phy_status, phy_1000t_status, phy_ext_status;
1092 u16 pci_status;
1093
1094 if (test_bit(__E1000_DOWN, &adapter->state))
1095 return;
1096
1097 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1098
1099
1100
1101 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1102
1103 e1e_flush();
1104
1105
1106
1107 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1108
1109 e1e_flush();
1110 adapter->tx_hang_recheck = true;
1111 return;
1112 }
1113 adapter->tx_hang_recheck = false;
1114
1115 if (er32(TDH(0)) == er32(TDT(0))) {
1116 e_dbg("false hang detected, ignoring\n");
1117 return;
1118 }
1119
1120
1121 netif_stop_queue(netdev);
1122
1123 e1e_rphy(hw, MII_BMSR, &phy_status);
1124 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1125 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1126
1127 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1128
1129
1130 e_err("Detected Hardware Unit Hang:\n"
1131 " TDH <%x>\n"
1132 " TDT <%x>\n"
1133 " next_to_use <%x>\n"
1134 " next_to_clean <%x>\n"
1135 "buffer_info[next_to_clean]:\n"
1136 " time_stamp <%lx>\n"
1137 " next_to_watch <%x>\n"
1138 " jiffies <%lx>\n"
1139 " next_to_watch.status <%x>\n"
1140 "MAC Status <%x>\n"
1141 "PHY Status <%x>\n"
1142 "PHY 1000BASE-T Status <%x>\n"
1143 "PHY Extended Status <%x>\n"
1144 "PCI Status <%x>\n",
1145 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1146 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1147 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1148 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1149
1150 e1000e_dump(adapter);
1151
1152
1153 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1154 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1155 }
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165 static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1166 {
1167 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1168 tx_hwtstamp_work);
1169 struct e1000_hw *hw = &adapter->hw;
1170
1171 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1172 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1173 struct skb_shared_hwtstamps shhwtstamps;
1174 u64 txstmp;
1175
1176 txstmp = er32(TXSTMPL);
1177 txstmp |= (u64)er32(TXSTMPH) << 32;
1178
1179 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1180
1181
1182
1183
1184 adapter->tx_hwtstamp_skb = NULL;
1185 wmb();
1186
1187 skb_tstamp_tx(skb, &shhwtstamps);
1188 dev_consume_skb_any(skb);
1189 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1190 + adapter->tx_timeout_factor * HZ)) {
1191 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1192 adapter->tx_hwtstamp_skb = NULL;
1193 adapter->tx_hwtstamp_timeouts++;
1194 e_warn("clearing Tx timestamp hang\n");
1195 } else {
1196
1197 schedule_work(&adapter->tx_hwtstamp_work);
1198 }
1199 }
1200
1201
1202
1203
1204
1205
1206
1207
1208 static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1209 {
1210 struct e1000_adapter *adapter = tx_ring->adapter;
1211 struct net_device *netdev = adapter->netdev;
1212 struct e1000_hw *hw = &adapter->hw;
1213 struct e1000_tx_desc *tx_desc, *eop_desc;
1214 struct e1000_buffer *buffer_info;
1215 unsigned int i, eop;
1216 unsigned int count = 0;
1217 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1218 unsigned int bytes_compl = 0, pkts_compl = 0;
1219
1220 i = tx_ring->next_to_clean;
1221 eop = tx_ring->buffer_info[i].next_to_watch;
1222 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1223
1224 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1225 (count < tx_ring->count)) {
1226 bool cleaned = false;
1227
1228 dma_rmb();
1229 for (; !cleaned; count++) {
1230 tx_desc = E1000_TX_DESC(*tx_ring, i);
1231 buffer_info = &tx_ring->buffer_info[i];
1232 cleaned = (i == eop);
1233
1234 if (cleaned) {
1235 total_tx_packets += buffer_info->segs;
1236 total_tx_bytes += buffer_info->bytecount;
1237 if (buffer_info->skb) {
1238 bytes_compl += buffer_info->skb->len;
1239 pkts_compl++;
1240 }
1241 }
1242
1243 e1000_put_txbuf(tx_ring, buffer_info, false);
1244 tx_desc->upper.data = 0;
1245
1246 i++;
1247 if (i == tx_ring->count)
1248 i = 0;
1249 }
1250
1251 if (i == tx_ring->next_to_use)
1252 break;
1253 eop = tx_ring->buffer_info[i].next_to_watch;
1254 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1255 }
1256
1257 tx_ring->next_to_clean = i;
1258
1259 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1260
1261 #define TX_WAKE_THRESHOLD 32
1262 if (count && netif_carrier_ok(netdev) &&
1263 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1264
1265
1266
1267 smp_mb();
1268
1269 if (netif_queue_stopped(netdev) &&
1270 !(test_bit(__E1000_DOWN, &adapter->state))) {
1271 netif_wake_queue(netdev);
1272 ++adapter->restart_queue;
1273 }
1274 }
1275
1276 if (adapter->detect_tx_hung) {
1277
1278
1279
1280 adapter->detect_tx_hung = false;
1281 if (tx_ring->buffer_info[i].time_stamp &&
1282 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1283 + (adapter->tx_timeout_factor * HZ)) &&
1284 !(er32(STATUS) & E1000_STATUS_TXOFF))
1285 schedule_work(&adapter->print_hang_task);
1286 else
1287 adapter->tx_hang_recheck = false;
1288 }
1289 adapter->total_tx_bytes += total_tx_bytes;
1290 adapter->total_tx_packets += total_tx_packets;
1291 return count < tx_ring->count;
1292 }
1293
1294
1295
1296
1297
1298
1299
1300
1301 static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1302 int work_to_do)
1303 {
1304 struct e1000_adapter *adapter = rx_ring->adapter;
1305 struct e1000_hw *hw = &adapter->hw;
1306 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1307 struct net_device *netdev = adapter->netdev;
1308 struct pci_dev *pdev = adapter->pdev;
1309 struct e1000_buffer *buffer_info, *next_buffer;
1310 struct e1000_ps_page *ps_page;
1311 struct sk_buff *skb;
1312 unsigned int i, j;
1313 u32 length, staterr;
1314 int cleaned_count = 0;
1315 bool cleaned = false;
1316 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1317
1318 i = rx_ring->next_to_clean;
1319 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1320 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1321 buffer_info = &rx_ring->buffer_info[i];
1322
1323 while (staterr & E1000_RXD_STAT_DD) {
1324 if (*work_done >= work_to_do)
1325 break;
1326 (*work_done)++;
1327 skb = buffer_info->skb;
1328 dma_rmb();
1329
1330
1331 prefetch(skb->data - NET_IP_ALIGN);
1332
1333 i++;
1334 if (i == rx_ring->count)
1335 i = 0;
1336 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1337 prefetch(next_rxd);
1338
1339 next_buffer = &rx_ring->buffer_info[i];
1340
1341 cleaned = true;
1342 cleaned_count++;
1343 dma_unmap_single(&pdev->dev, buffer_info->dma,
1344 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1345 buffer_info->dma = 0;
1346
1347
1348 if (!(staterr & E1000_RXD_STAT_EOP))
1349 adapter->flags2 |= FLAG2_IS_DISCARDING;
1350
1351 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1352 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1353 dev_kfree_skb_irq(skb);
1354 if (staterr & E1000_RXD_STAT_EOP)
1355 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1356 goto next_desc;
1357 }
1358
1359 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1360 !(netdev->features & NETIF_F_RXALL))) {
1361 dev_kfree_skb_irq(skb);
1362 goto next_desc;
1363 }
1364
1365 length = le16_to_cpu(rx_desc->wb.middle.length0);
1366
1367 if (!length) {
1368 e_dbg("Last part of the packet spanning multiple descriptors\n");
1369 dev_kfree_skb_irq(skb);
1370 goto next_desc;
1371 }
1372
1373
1374 skb_put(skb, length);
1375
1376 {
1377
1378
1379
1380 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1381
1382
1383
1384
1385
1386
1387 if (l1 && (l1 <= copybreak) &&
1388 ((length + l1) <= adapter->rx_ps_bsize0)) {
1389 u8 *vaddr;
1390
1391 ps_page = &buffer_info->ps_pages[0];
1392
1393
1394
1395
1396
1397 dma_sync_single_for_cpu(&pdev->dev,
1398 ps_page->dma,
1399 PAGE_SIZE,
1400 DMA_FROM_DEVICE);
1401 vaddr = kmap_atomic(ps_page->page);
1402 memcpy(skb_tail_pointer(skb), vaddr, l1);
1403 kunmap_atomic(vaddr);
1404 dma_sync_single_for_device(&pdev->dev,
1405 ps_page->dma,
1406 PAGE_SIZE,
1407 DMA_FROM_DEVICE);
1408
1409
1410 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1411 if (!(netdev->features & NETIF_F_RXFCS))
1412 l1 -= 4;
1413 }
1414
1415 skb_put(skb, l1);
1416 goto copydone;
1417 }
1418 }
1419
1420 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1421 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1422 if (!length)
1423 break;
1424
1425 ps_page = &buffer_info->ps_pages[j];
1426 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1427 DMA_FROM_DEVICE);
1428 ps_page->dma = 0;
1429 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1430 ps_page->page = NULL;
1431 skb->len += length;
1432 skb->data_len += length;
1433 skb->truesize += PAGE_SIZE;
1434 }
1435
1436
1437
1438
1439 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1440 if (!(netdev->features & NETIF_F_RXFCS))
1441 pskb_trim(skb, skb->len - 4);
1442 }
1443
1444 copydone:
1445 total_rx_bytes += skb->len;
1446 total_rx_packets++;
1447
1448 e1000_rx_checksum(adapter, staterr, skb);
1449
1450 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1451
1452 if (rx_desc->wb.upper.header_status &
1453 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1454 adapter->rx_hdr_split++;
1455
1456 e1000_receive_skb(adapter, netdev, skb, staterr,
1457 rx_desc->wb.middle.vlan);
1458
1459 next_desc:
1460 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1461 buffer_info->skb = NULL;
1462
1463
1464 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1465 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1466 GFP_ATOMIC);
1467 cleaned_count = 0;
1468 }
1469
1470
1471 rx_desc = next_rxd;
1472 buffer_info = next_buffer;
1473
1474 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1475 }
1476 rx_ring->next_to_clean = i;
1477
1478 cleaned_count = e1000_desc_unused(rx_ring);
1479 if (cleaned_count)
1480 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1481
1482 adapter->total_rx_bytes += total_rx_bytes;
1483 adapter->total_rx_packets += total_rx_packets;
1484 return cleaned;
1485 }
1486
1487
1488
1489
1490 static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1491 u16 length)
1492 {
1493 bi->page = NULL;
1494 skb->len += length;
1495 skb->data_len += length;
1496 skb->truesize += PAGE_SIZE;
1497 }
1498
1499
1500
1501
1502
1503
1504
1505
1506 static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1507 int work_to_do)
1508 {
1509 struct e1000_adapter *adapter = rx_ring->adapter;
1510 struct net_device *netdev = adapter->netdev;
1511 struct pci_dev *pdev = adapter->pdev;
1512 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1513 struct e1000_buffer *buffer_info, *next_buffer;
1514 u32 length, staterr;
1515 unsigned int i;
1516 int cleaned_count = 0;
1517 bool cleaned = false;
1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1519 struct skb_shared_info *shinfo;
1520
1521 i = rx_ring->next_to_clean;
1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1524 buffer_info = &rx_ring->buffer_info[i];
1525
1526 while (staterr & E1000_RXD_STAT_DD) {
1527 struct sk_buff *skb;
1528
1529 if (*work_done >= work_to_do)
1530 break;
1531 (*work_done)++;
1532 dma_rmb();
1533
1534 skb = buffer_info->skb;
1535 buffer_info->skb = NULL;
1536
1537 ++i;
1538 if (i == rx_ring->count)
1539 i = 0;
1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1541 prefetch(next_rxd);
1542
1543 next_buffer = &rx_ring->buffer_info[i];
1544
1545 cleaned = true;
1546 cleaned_count++;
1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1548 DMA_FROM_DEVICE);
1549 buffer_info->dma = 0;
1550
1551 length = le16_to_cpu(rx_desc->wb.upper.length);
1552
1553
1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1556 !(netdev->features & NETIF_F_RXALL)))) {
1557
1558 buffer_info->skb = skb;
1559
1560 if (rx_ring->rx_skb_top)
1561 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1562 rx_ring->rx_skb_top = NULL;
1563 goto next_desc;
1564 }
1565 #define rxtop (rx_ring->rx_skb_top)
1566 if (!(staterr & E1000_RXD_STAT_EOP)) {
1567
1568 if (!rxtop) {
1569
1570 rxtop = skb;
1571 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1572 0, length);
1573 } else {
1574
1575 shinfo = skb_shinfo(rxtop);
1576 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1577 buffer_info->page, 0,
1578 length);
1579
1580 buffer_info->skb = skb;
1581 }
1582 e1000_consume_page(buffer_info, rxtop, length);
1583 goto next_desc;
1584 } else {
1585 if (rxtop) {
1586
1587 shinfo = skb_shinfo(rxtop);
1588 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1589 buffer_info->page, 0,
1590 length);
1591
1592
1593
1594 buffer_info->skb = skb;
1595 skb = rxtop;
1596 rxtop = NULL;
1597 e1000_consume_page(buffer_info, skb, length);
1598 } else {
1599
1600
1601
1602 if (length <= copybreak &&
1603 skb_tailroom(skb) >= length) {
1604 u8 *vaddr;
1605 vaddr = kmap_atomic(buffer_info->page);
1606 memcpy(skb_tail_pointer(skb), vaddr,
1607 length);
1608 kunmap_atomic(vaddr);
1609
1610
1611
1612 skb_put(skb, length);
1613 } else {
1614 skb_fill_page_desc(skb, 0,
1615 buffer_info->page, 0,
1616 length);
1617 e1000_consume_page(buffer_info, skb,
1618 length);
1619 }
1620 }
1621 }
1622
1623
1624 e1000_rx_checksum(adapter, staterr, skb);
1625
1626 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1627
1628
1629 total_rx_bytes += skb->len;
1630 total_rx_packets++;
1631
1632
1633 if (!pskb_may_pull(skb, ETH_HLEN)) {
1634 e_err("pskb_may_pull failed.\n");
1635 dev_kfree_skb_irq(skb);
1636 goto next_desc;
1637 }
1638
1639 e1000_receive_skb(adapter, netdev, skb, staterr,
1640 rx_desc->wb.upper.vlan);
1641
1642 next_desc:
1643 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1644
1645
1646 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1647 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1648 GFP_ATOMIC);
1649 cleaned_count = 0;
1650 }
1651
1652
1653 rx_desc = next_rxd;
1654 buffer_info = next_buffer;
1655
1656 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1657 }
1658 rx_ring->next_to_clean = i;
1659
1660 cleaned_count = e1000_desc_unused(rx_ring);
1661 if (cleaned_count)
1662 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1663
1664 adapter->total_rx_bytes += total_rx_bytes;
1665 adapter->total_rx_packets += total_rx_packets;
1666 return cleaned;
1667 }
1668
1669
1670
1671
1672
1673 static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1674 {
1675 struct e1000_adapter *adapter = rx_ring->adapter;
1676 struct e1000_buffer *buffer_info;
1677 struct e1000_ps_page *ps_page;
1678 struct pci_dev *pdev = adapter->pdev;
1679 unsigned int i, j;
1680
1681
1682 for (i = 0; i < rx_ring->count; i++) {
1683 buffer_info = &rx_ring->buffer_info[i];
1684 if (buffer_info->dma) {
1685 if (adapter->clean_rx == e1000_clean_rx_irq)
1686 dma_unmap_single(&pdev->dev, buffer_info->dma,
1687 adapter->rx_buffer_len,
1688 DMA_FROM_DEVICE);
1689 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1690 dma_unmap_page(&pdev->dev, buffer_info->dma,
1691 PAGE_SIZE, DMA_FROM_DEVICE);
1692 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1693 dma_unmap_single(&pdev->dev, buffer_info->dma,
1694 adapter->rx_ps_bsize0,
1695 DMA_FROM_DEVICE);
1696 buffer_info->dma = 0;
1697 }
1698
1699 if (buffer_info->page) {
1700 put_page(buffer_info->page);
1701 buffer_info->page = NULL;
1702 }
1703
1704 if (buffer_info->skb) {
1705 dev_kfree_skb(buffer_info->skb);
1706 buffer_info->skb = NULL;
1707 }
1708
1709 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1710 ps_page = &buffer_info->ps_pages[j];
1711 if (!ps_page->page)
1712 break;
1713 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1714 DMA_FROM_DEVICE);
1715 ps_page->dma = 0;
1716 put_page(ps_page->page);
1717 ps_page->page = NULL;
1718 }
1719 }
1720
1721
1722 if (rx_ring->rx_skb_top) {
1723 dev_kfree_skb(rx_ring->rx_skb_top);
1724 rx_ring->rx_skb_top = NULL;
1725 }
1726
1727
1728 memset(rx_ring->desc, 0, rx_ring->size);
1729
1730 rx_ring->next_to_clean = 0;
1731 rx_ring->next_to_use = 0;
1732 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1733 }
1734
1735 static void e1000e_downshift_workaround(struct work_struct *work)
1736 {
1737 struct e1000_adapter *adapter = container_of(work,
1738 struct e1000_adapter,
1739 downshift_task);
1740
1741 if (test_bit(__E1000_DOWN, &adapter->state))
1742 return;
1743
1744 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1745 }
1746
1747
1748
1749
1750
1751
1752 static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1753 {
1754 struct net_device *netdev = data;
1755 struct e1000_adapter *adapter = netdev_priv(netdev);
1756 struct e1000_hw *hw = &adapter->hw;
1757 u32 icr = er32(ICR);
1758
1759
1760 if (icr & E1000_ICR_LSC) {
1761 hw->mac.get_link_status = true;
1762
1763
1764
1765 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1766 (!(er32(STATUS) & E1000_STATUS_LU)))
1767 schedule_work(&adapter->downshift_task);
1768
1769
1770
1771
1772
1773 if (netif_carrier_ok(netdev) &&
1774 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1775
1776 u32 rctl = er32(RCTL);
1777
1778 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1779 adapter->flags |= FLAG_RESTART_NOW;
1780 }
1781
1782 if (!test_bit(__E1000_DOWN, &adapter->state))
1783 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1784 }
1785
1786
1787 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1788 u32 pbeccsts = er32(PBECCSTS);
1789
1790 adapter->corr_errors +=
1791 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1792 adapter->uncorr_errors +=
1793 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1794 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1795
1796
1797 schedule_work(&adapter->reset_task);
1798
1799
1800 return IRQ_HANDLED;
1801 }
1802
1803 if (napi_schedule_prep(&adapter->napi)) {
1804 adapter->total_tx_bytes = 0;
1805 adapter->total_tx_packets = 0;
1806 adapter->total_rx_bytes = 0;
1807 adapter->total_rx_packets = 0;
1808 __napi_schedule(&adapter->napi);
1809 }
1810
1811 return IRQ_HANDLED;
1812 }
1813
1814
1815
1816
1817
1818
1819 static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1820 {
1821 struct net_device *netdev = data;
1822 struct e1000_adapter *adapter = netdev_priv(netdev);
1823 struct e1000_hw *hw = &adapter->hw;
1824 u32 rctl, icr = er32(ICR);
1825
1826 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1827 return IRQ_NONE;
1828
1829
1830
1831
1832 if (!(icr & E1000_ICR_INT_ASSERTED))
1833 return IRQ_NONE;
1834
1835
1836
1837
1838
1839
1840 if (icr & E1000_ICR_LSC) {
1841 hw->mac.get_link_status = true;
1842
1843
1844
1845 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1846 (!(er32(STATUS) & E1000_STATUS_LU)))
1847 schedule_work(&adapter->downshift_task);
1848
1849
1850
1851
1852
1853
1854 if (netif_carrier_ok(netdev) &&
1855 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1856
1857 rctl = er32(RCTL);
1858 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1859 adapter->flags |= FLAG_RESTART_NOW;
1860 }
1861
1862 if (!test_bit(__E1000_DOWN, &adapter->state))
1863 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1864 }
1865
1866
1867 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1868 u32 pbeccsts = er32(PBECCSTS);
1869
1870 adapter->corr_errors +=
1871 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1872 adapter->uncorr_errors +=
1873 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1874 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1875
1876
1877 schedule_work(&adapter->reset_task);
1878
1879
1880 return IRQ_HANDLED;
1881 }
1882
1883 if (napi_schedule_prep(&adapter->napi)) {
1884 adapter->total_tx_bytes = 0;
1885 adapter->total_tx_packets = 0;
1886 adapter->total_rx_bytes = 0;
1887 adapter->total_rx_packets = 0;
1888 __napi_schedule(&adapter->napi);
1889 }
1890
1891 return IRQ_HANDLED;
1892 }
1893
1894 static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1895 {
1896 struct net_device *netdev = data;
1897 struct e1000_adapter *adapter = netdev_priv(netdev);
1898 struct e1000_hw *hw = &adapter->hw;
1899 u32 icr = er32(ICR);
1900
1901 if (icr & adapter->eiac_mask)
1902 ew32(ICS, (icr & adapter->eiac_mask));
1903
1904 if (icr & E1000_ICR_LSC) {
1905 hw->mac.get_link_status = true;
1906
1907 if (!test_bit(__E1000_DOWN, &adapter->state))
1908 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1909 }
1910
1911 if (!test_bit(__E1000_DOWN, &adapter->state))
1912 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1913
1914 return IRQ_HANDLED;
1915 }
1916
1917 static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1918 {
1919 struct net_device *netdev = data;
1920 struct e1000_adapter *adapter = netdev_priv(netdev);
1921 struct e1000_hw *hw = &adapter->hw;
1922 struct e1000_ring *tx_ring = adapter->tx_ring;
1923
1924 adapter->total_tx_bytes = 0;
1925 adapter->total_tx_packets = 0;
1926
1927 if (!e1000_clean_tx_irq(tx_ring))
1928
1929 ew32(ICS, tx_ring->ims_val);
1930
1931 if (!test_bit(__E1000_DOWN, &adapter->state))
1932 ew32(IMS, adapter->tx_ring->ims_val);
1933
1934 return IRQ_HANDLED;
1935 }
1936
1937 static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1938 {
1939 struct net_device *netdev = data;
1940 struct e1000_adapter *adapter = netdev_priv(netdev);
1941 struct e1000_ring *rx_ring = adapter->rx_ring;
1942
1943
1944
1945
1946 if (rx_ring->set_itr) {
1947 u32 itr = rx_ring->itr_val ?
1948 1000000000 / (rx_ring->itr_val * 256) : 0;
1949
1950 writel(itr, rx_ring->itr_register);
1951 rx_ring->set_itr = 0;
1952 }
1953
1954 if (napi_schedule_prep(&adapter->napi)) {
1955 adapter->total_rx_bytes = 0;
1956 adapter->total_rx_packets = 0;
1957 __napi_schedule(&adapter->napi);
1958 }
1959 return IRQ_HANDLED;
1960 }
1961
1962
1963
1964
1965
1966
1967
1968 static void e1000_configure_msix(struct e1000_adapter *adapter)
1969 {
1970 struct e1000_hw *hw = &adapter->hw;
1971 struct e1000_ring *rx_ring = adapter->rx_ring;
1972 struct e1000_ring *tx_ring = adapter->tx_ring;
1973 int vector = 0;
1974 u32 ctrl_ext, ivar = 0;
1975
1976 adapter->eiac_mask = 0;
1977
1978
1979 if (hw->mac.type == e1000_82574) {
1980 u32 rfctl = er32(RFCTL);
1981
1982 rfctl |= E1000_RFCTL_ACK_DIS;
1983 ew32(RFCTL, rfctl);
1984 }
1985
1986
1987 rx_ring->ims_val = E1000_IMS_RXQ0;
1988 adapter->eiac_mask |= rx_ring->ims_val;
1989 if (rx_ring->itr_val)
1990 writel(1000000000 / (rx_ring->itr_val * 256),
1991 rx_ring->itr_register);
1992 else
1993 writel(1, rx_ring->itr_register);
1994 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1995
1996
1997 tx_ring->ims_val = E1000_IMS_TXQ0;
1998 vector++;
1999 if (tx_ring->itr_val)
2000 writel(1000000000 / (tx_ring->itr_val * 256),
2001 tx_ring->itr_register);
2002 else
2003 writel(1, tx_ring->itr_register);
2004 adapter->eiac_mask |= tx_ring->ims_val;
2005 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2006
2007
2008 vector++;
2009 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2010 if (rx_ring->itr_val)
2011 writel(1000000000 / (rx_ring->itr_val * 256),
2012 hw->hw_addr + E1000_EITR_82574(vector));
2013 else
2014 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2015
2016
2017 ivar |= BIT(31);
2018
2019 ew32(IVAR, ivar);
2020
2021
2022 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2023 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2024 ew32(CTRL_EXT, ctrl_ext);
2025 e1e_flush();
2026 }
2027
2028 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2029 {
2030 if (adapter->msix_entries) {
2031 pci_disable_msix(adapter->pdev);
2032 kfree(adapter->msix_entries);
2033 adapter->msix_entries = NULL;
2034 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2035 pci_disable_msi(adapter->pdev);
2036 adapter->flags &= ~FLAG_MSI_ENABLED;
2037 }
2038 }
2039
2040
2041
2042
2043
2044
2045
2046 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2047 {
2048 int err;
2049 int i;
2050
2051 switch (adapter->int_mode) {
2052 case E1000E_INT_MODE_MSIX:
2053 if (adapter->flags & FLAG_HAS_MSIX) {
2054 adapter->num_vectors = 3;
2055 adapter->msix_entries = kcalloc(adapter->num_vectors,
2056 sizeof(struct
2057 msix_entry),
2058 GFP_KERNEL);
2059 if (adapter->msix_entries) {
2060 struct e1000_adapter *a = adapter;
2061
2062 for (i = 0; i < adapter->num_vectors; i++)
2063 adapter->msix_entries[i].entry = i;
2064
2065 err = pci_enable_msix_range(a->pdev,
2066 a->msix_entries,
2067 a->num_vectors,
2068 a->num_vectors);
2069 if (err > 0)
2070 return;
2071 }
2072
2073 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2074 e1000e_reset_interrupt_capability(adapter);
2075 }
2076 adapter->int_mode = E1000E_INT_MODE_MSI;
2077
2078 case E1000E_INT_MODE_MSI:
2079 if (!pci_enable_msi(adapter->pdev)) {
2080 adapter->flags |= FLAG_MSI_ENABLED;
2081 } else {
2082 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2083 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2084 }
2085
2086 case E1000E_INT_MODE_LEGACY:
2087
2088 break;
2089 }
2090
2091
2092 adapter->num_vectors = 1;
2093 }
2094
2095
2096
2097
2098
2099
2100
2101 static int e1000_request_msix(struct e1000_adapter *adapter)
2102 {
2103 struct net_device *netdev = adapter->netdev;
2104 int err = 0, vector = 0;
2105
2106 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2107 snprintf(adapter->rx_ring->name,
2108 sizeof(adapter->rx_ring->name) - 1,
2109 "%.14s-rx-0", netdev->name);
2110 else
2111 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2112 err = request_irq(adapter->msix_entries[vector].vector,
2113 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2114 netdev);
2115 if (err)
2116 return err;
2117 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2118 E1000_EITR_82574(vector);
2119 adapter->rx_ring->itr_val = adapter->itr;
2120 vector++;
2121
2122 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2123 snprintf(adapter->tx_ring->name,
2124 sizeof(adapter->tx_ring->name) - 1,
2125 "%.14s-tx-0", netdev->name);
2126 else
2127 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2128 err = request_irq(adapter->msix_entries[vector].vector,
2129 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2130 netdev);
2131 if (err)
2132 return err;
2133 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2134 E1000_EITR_82574(vector);
2135 adapter->tx_ring->itr_val = adapter->itr;
2136 vector++;
2137
2138 err = request_irq(adapter->msix_entries[vector].vector,
2139 e1000_msix_other, 0, netdev->name, netdev);
2140 if (err)
2141 return err;
2142
2143 e1000_configure_msix(adapter);
2144
2145 return 0;
2146 }
2147
2148
2149
2150
2151
2152
2153
2154 static int e1000_request_irq(struct e1000_adapter *adapter)
2155 {
2156 struct net_device *netdev = adapter->netdev;
2157 int err;
2158
2159 if (adapter->msix_entries) {
2160 err = e1000_request_msix(adapter);
2161 if (!err)
2162 return err;
2163
2164 e1000e_reset_interrupt_capability(adapter);
2165 adapter->int_mode = E1000E_INT_MODE_MSI;
2166 e1000e_set_interrupt_capability(adapter);
2167 }
2168 if (adapter->flags & FLAG_MSI_ENABLED) {
2169 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2170 netdev->name, netdev);
2171 if (!err)
2172 return err;
2173
2174
2175 e1000e_reset_interrupt_capability(adapter);
2176 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2177 }
2178
2179 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2180 netdev->name, netdev);
2181 if (err)
2182 e_err("Unable to allocate interrupt, Error: %d\n", err);
2183
2184 return err;
2185 }
2186
2187 static void e1000_free_irq(struct e1000_adapter *adapter)
2188 {
2189 struct net_device *netdev = adapter->netdev;
2190
2191 if (adapter->msix_entries) {
2192 int vector = 0;
2193
2194 free_irq(adapter->msix_entries[vector].vector, netdev);
2195 vector++;
2196
2197 free_irq(adapter->msix_entries[vector].vector, netdev);
2198 vector++;
2199
2200
2201 free_irq(adapter->msix_entries[vector].vector, netdev);
2202 return;
2203 }
2204
2205 free_irq(adapter->pdev->irq, netdev);
2206 }
2207
2208
2209
2210
2211 static void e1000_irq_disable(struct e1000_adapter *adapter)
2212 {
2213 struct e1000_hw *hw = &adapter->hw;
2214
2215 ew32(IMC, ~0);
2216 if (adapter->msix_entries)
2217 ew32(EIAC_82574, 0);
2218 e1e_flush();
2219
2220 if (adapter->msix_entries) {
2221 int i;
2222
2223 for (i = 0; i < adapter->num_vectors; i++)
2224 synchronize_irq(adapter->msix_entries[i].vector);
2225 } else {
2226 synchronize_irq(adapter->pdev->irq);
2227 }
2228 }
2229
2230
2231
2232
2233 static void e1000_irq_enable(struct e1000_adapter *adapter)
2234 {
2235 struct e1000_hw *hw = &adapter->hw;
2236
2237 if (adapter->msix_entries) {
2238 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2239 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2240 IMS_OTHER_MASK);
2241 } else if (hw->mac.type >= e1000_pch_lpt) {
2242 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2243 } else {
2244 ew32(IMS, IMS_ENABLE_MASK);
2245 }
2246 e1e_flush();
2247 }
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258 void e1000e_get_hw_control(struct e1000_adapter *adapter)
2259 {
2260 struct e1000_hw *hw = &adapter->hw;
2261 u32 ctrl_ext;
2262 u32 swsm;
2263
2264
2265 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2266 swsm = er32(SWSM);
2267 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2268 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2269 ctrl_ext = er32(CTRL_EXT);
2270 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2271 }
2272 }
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284 void e1000e_release_hw_control(struct e1000_adapter *adapter)
2285 {
2286 struct e1000_hw *hw = &adapter->hw;
2287 u32 ctrl_ext;
2288 u32 swsm;
2289
2290
2291 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2292 swsm = er32(SWSM);
2293 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2294 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2295 ctrl_ext = er32(CTRL_EXT);
2296 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2297 }
2298 }
2299
2300
2301
2302
2303 static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2304 struct e1000_ring *ring)
2305 {
2306 struct pci_dev *pdev = adapter->pdev;
2307
2308 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2309 GFP_KERNEL);
2310 if (!ring->desc)
2311 return -ENOMEM;
2312
2313 return 0;
2314 }
2315
2316
2317
2318
2319
2320
2321
2322 int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2323 {
2324 struct e1000_adapter *adapter = tx_ring->adapter;
2325 int err = -ENOMEM, size;
2326
2327 size = sizeof(struct e1000_buffer) * tx_ring->count;
2328 tx_ring->buffer_info = vzalloc(size);
2329 if (!tx_ring->buffer_info)
2330 goto err;
2331
2332
2333 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2334 tx_ring->size = ALIGN(tx_ring->size, 4096);
2335
2336 err = e1000_alloc_ring_dma(adapter, tx_ring);
2337 if (err)
2338 goto err;
2339
2340 tx_ring->next_to_use = 0;
2341 tx_ring->next_to_clean = 0;
2342
2343 return 0;
2344 err:
2345 vfree(tx_ring->buffer_info);
2346 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2347 return err;
2348 }
2349
2350
2351
2352
2353
2354
2355
2356 int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2357 {
2358 struct e1000_adapter *adapter = rx_ring->adapter;
2359 struct e1000_buffer *buffer_info;
2360 int i, size, desc_len, err = -ENOMEM;
2361
2362 size = sizeof(struct e1000_buffer) * rx_ring->count;
2363 rx_ring->buffer_info = vzalloc(size);
2364 if (!rx_ring->buffer_info)
2365 goto err;
2366
2367 for (i = 0; i < rx_ring->count; i++) {
2368 buffer_info = &rx_ring->buffer_info[i];
2369 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2370 sizeof(struct e1000_ps_page),
2371 GFP_KERNEL);
2372 if (!buffer_info->ps_pages)
2373 goto err_pages;
2374 }
2375
2376 desc_len = sizeof(union e1000_rx_desc_packet_split);
2377
2378
2379 rx_ring->size = rx_ring->count * desc_len;
2380 rx_ring->size = ALIGN(rx_ring->size, 4096);
2381
2382 err = e1000_alloc_ring_dma(adapter, rx_ring);
2383 if (err)
2384 goto err_pages;
2385
2386 rx_ring->next_to_clean = 0;
2387 rx_ring->next_to_use = 0;
2388 rx_ring->rx_skb_top = NULL;
2389
2390 return 0;
2391
2392 err_pages:
2393 for (i = 0; i < rx_ring->count; i++) {
2394 buffer_info = &rx_ring->buffer_info[i];
2395 kfree(buffer_info->ps_pages);
2396 }
2397 err:
2398 vfree(rx_ring->buffer_info);
2399 e_err("Unable to allocate memory for the receive descriptor ring\n");
2400 return err;
2401 }
2402
2403
2404
2405
2406
2407 static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2408 {
2409 struct e1000_adapter *adapter = tx_ring->adapter;
2410 struct e1000_buffer *buffer_info;
2411 unsigned long size;
2412 unsigned int i;
2413
2414 for (i = 0; i < tx_ring->count; i++) {
2415 buffer_info = &tx_ring->buffer_info[i];
2416 e1000_put_txbuf(tx_ring, buffer_info, false);
2417 }
2418
2419 netdev_reset_queue(adapter->netdev);
2420 size = sizeof(struct e1000_buffer) * tx_ring->count;
2421 memset(tx_ring->buffer_info, 0, size);
2422
2423 memset(tx_ring->desc, 0, tx_ring->size);
2424
2425 tx_ring->next_to_use = 0;
2426 tx_ring->next_to_clean = 0;
2427 }
2428
2429
2430
2431
2432
2433
2434
2435 void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2436 {
2437 struct e1000_adapter *adapter = tx_ring->adapter;
2438 struct pci_dev *pdev = adapter->pdev;
2439
2440 e1000_clean_tx_ring(tx_ring);
2441
2442 vfree(tx_ring->buffer_info);
2443 tx_ring->buffer_info = NULL;
2444
2445 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2446 tx_ring->dma);
2447 tx_ring->desc = NULL;
2448 }
2449
2450
2451
2452
2453
2454
2455
2456 void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2457 {
2458 struct e1000_adapter *adapter = rx_ring->adapter;
2459 struct pci_dev *pdev = adapter->pdev;
2460 int i;
2461
2462 e1000_clean_rx_ring(rx_ring);
2463
2464 for (i = 0; i < rx_ring->count; i++)
2465 kfree(rx_ring->buffer_info[i].ps_pages);
2466
2467 vfree(rx_ring->buffer_info);
2468 rx_ring->buffer_info = NULL;
2469
2470 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2471 rx_ring->dma);
2472 rx_ring->desc = NULL;
2473 }
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491 static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2492 {
2493 unsigned int retval = itr_setting;
2494
2495 if (packets == 0)
2496 return itr_setting;
2497
2498 switch (itr_setting) {
2499 case lowest_latency:
2500
2501 if (bytes / packets > 8000)
2502 retval = bulk_latency;
2503 else if ((packets < 5) && (bytes > 512))
2504 retval = low_latency;
2505 break;
2506 case low_latency:
2507 if (bytes > 10000) {
2508
2509 if (bytes / packets > 8000)
2510 retval = bulk_latency;
2511 else if ((packets < 10) || ((bytes / packets) > 1200))
2512 retval = bulk_latency;
2513 else if ((packets > 35))
2514 retval = lowest_latency;
2515 } else if (bytes / packets > 2000) {
2516 retval = bulk_latency;
2517 } else if (packets <= 2 && bytes < 512) {
2518 retval = lowest_latency;
2519 }
2520 break;
2521 case bulk_latency:
2522 if (bytes > 25000) {
2523 if (packets > 35)
2524 retval = low_latency;
2525 } else if (bytes < 6000) {
2526 retval = low_latency;
2527 }
2528 break;
2529 }
2530
2531 return retval;
2532 }
2533
2534 static void e1000_set_itr(struct e1000_adapter *adapter)
2535 {
2536 u16 current_itr;
2537 u32 new_itr = adapter->itr;
2538
2539
2540 if (adapter->link_speed != SPEED_1000) {
2541 current_itr = 0;
2542 new_itr = 4000;
2543 goto set_itr_now;
2544 }
2545
2546 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2547 new_itr = 0;
2548 goto set_itr_now;
2549 }
2550
2551 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2552 adapter->total_tx_packets,
2553 adapter->total_tx_bytes);
2554
2555 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2556 adapter->tx_itr = low_latency;
2557
2558 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2559 adapter->total_rx_packets,
2560 adapter->total_rx_bytes);
2561
2562 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2563 adapter->rx_itr = low_latency;
2564
2565 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2566
2567
2568 switch (current_itr) {
2569 case lowest_latency:
2570 new_itr = 70000;
2571 break;
2572 case low_latency:
2573 new_itr = 20000;
2574 break;
2575 case bulk_latency:
2576 new_itr = 4000;
2577 break;
2578 default:
2579 break;
2580 }
2581
2582 set_itr_now:
2583 if (new_itr != adapter->itr) {
2584
2585
2586
2587
2588 new_itr = new_itr > adapter->itr ?
2589 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2590 adapter->itr = new_itr;
2591 adapter->rx_ring->itr_val = new_itr;
2592 if (adapter->msix_entries)
2593 adapter->rx_ring->set_itr = 1;
2594 else
2595 e1000e_write_itr(adapter, new_itr);
2596 }
2597 }
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2609 {
2610 struct e1000_hw *hw = &adapter->hw;
2611 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2612
2613 if (adapter->msix_entries) {
2614 int vector;
2615
2616 for (vector = 0; vector < adapter->num_vectors; vector++)
2617 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2618 } else {
2619 ew32(ITR, new_itr);
2620 }
2621 }
2622
2623
2624
2625
2626
2627 static int e1000_alloc_queues(struct e1000_adapter *adapter)
2628 {
2629 int size = sizeof(struct e1000_ring);
2630
2631 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2632 if (!adapter->tx_ring)
2633 goto err;
2634 adapter->tx_ring->count = adapter->tx_ring_count;
2635 adapter->tx_ring->adapter = adapter;
2636
2637 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2638 if (!adapter->rx_ring)
2639 goto err;
2640 adapter->rx_ring->count = adapter->rx_ring_count;
2641 adapter->rx_ring->adapter = adapter;
2642
2643 return 0;
2644 err:
2645 e_err("Unable to allocate memory for queues\n");
2646 kfree(adapter->rx_ring);
2647 kfree(adapter->tx_ring);
2648 return -ENOMEM;
2649 }
2650
2651
2652
2653
2654
2655
2656 static int e1000e_poll(struct napi_struct *napi, int budget)
2657 {
2658 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2659 napi);
2660 struct e1000_hw *hw = &adapter->hw;
2661 struct net_device *poll_dev = adapter->netdev;
2662 int tx_cleaned = 1, work_done = 0;
2663
2664 adapter = netdev_priv(poll_dev);
2665
2666 if (!adapter->msix_entries ||
2667 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2668 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2669
2670 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2671
2672 if (!tx_cleaned || work_done == budget)
2673 return budget;
2674
2675
2676
2677
2678 if (likely(napi_complete_done(napi, work_done))) {
2679 if (adapter->itr_setting & 3)
2680 e1000_set_itr(adapter);
2681 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2682 if (adapter->msix_entries)
2683 ew32(IMS, adapter->rx_ring->ims_val);
2684 else
2685 e1000_irq_enable(adapter);
2686 }
2687 }
2688
2689 return work_done;
2690 }
2691
2692 static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2693 __always_unused __be16 proto, u16 vid)
2694 {
2695 struct e1000_adapter *adapter = netdev_priv(netdev);
2696 struct e1000_hw *hw = &adapter->hw;
2697 u32 vfta, index;
2698
2699
2700 if ((adapter->hw.mng_cookie.status &
2701 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2702 (vid == adapter->mng_vlan_id))
2703 return 0;
2704
2705
2706 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2707 index = (vid >> 5) & 0x7F;
2708 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2709 vfta |= BIT((vid & 0x1F));
2710 hw->mac.ops.write_vfta(hw, index, vfta);
2711 }
2712
2713 set_bit(vid, adapter->active_vlans);
2714
2715 return 0;
2716 }
2717
2718 static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2719 __always_unused __be16 proto, u16 vid)
2720 {
2721 struct e1000_adapter *adapter = netdev_priv(netdev);
2722 struct e1000_hw *hw = &adapter->hw;
2723 u32 vfta, index;
2724
2725 if ((adapter->hw.mng_cookie.status &
2726 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2727 (vid == adapter->mng_vlan_id)) {
2728
2729 e1000e_release_hw_control(adapter);
2730 return 0;
2731 }
2732
2733
2734 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2735 index = (vid >> 5) & 0x7F;
2736 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2737 vfta &= ~BIT((vid & 0x1F));
2738 hw->mac.ops.write_vfta(hw, index, vfta);
2739 }
2740
2741 clear_bit(vid, adapter->active_vlans);
2742
2743 return 0;
2744 }
2745
2746
2747
2748
2749
2750 static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2751 {
2752 struct net_device *netdev = adapter->netdev;
2753 struct e1000_hw *hw = &adapter->hw;
2754 u32 rctl;
2755
2756 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2757
2758 rctl = er32(RCTL);
2759 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2760 ew32(RCTL, rctl);
2761
2762 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2763 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2764 adapter->mng_vlan_id);
2765 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2766 }
2767 }
2768 }
2769
2770
2771
2772
2773
2774 static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2775 {
2776 struct e1000_hw *hw = &adapter->hw;
2777 u32 rctl;
2778
2779 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2780
2781 rctl = er32(RCTL);
2782 rctl |= E1000_RCTL_VFE;
2783 rctl &= ~E1000_RCTL_CFIEN;
2784 ew32(RCTL, rctl);
2785 }
2786 }
2787
2788
2789
2790
2791
2792 static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2793 {
2794 struct e1000_hw *hw = &adapter->hw;
2795 u32 ctrl;
2796
2797
2798 ctrl = er32(CTRL);
2799 ctrl &= ~E1000_CTRL_VME;
2800 ew32(CTRL, ctrl);
2801 }
2802
2803
2804
2805
2806
2807 static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2808 {
2809 struct e1000_hw *hw = &adapter->hw;
2810 u32 ctrl;
2811
2812
2813 ctrl = er32(CTRL);
2814 ctrl |= E1000_CTRL_VME;
2815 ew32(CTRL, ctrl);
2816 }
2817
2818 static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2819 {
2820 struct net_device *netdev = adapter->netdev;
2821 u16 vid = adapter->hw.mng_cookie.vlan_id;
2822 u16 old_vid = adapter->mng_vlan_id;
2823
2824 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2825 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2826 adapter->mng_vlan_id = vid;
2827 }
2828
2829 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2830 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2831 }
2832
2833 static void e1000_restore_vlan(struct e1000_adapter *adapter)
2834 {
2835 u16 vid;
2836
2837 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2838
2839 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2840 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2841 }
2842
2843 static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2844 {
2845 struct e1000_hw *hw = &adapter->hw;
2846 u32 manc, manc2h, mdef, i, j;
2847
2848 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2849 return;
2850
2851 manc = er32(MANC);
2852
2853
2854
2855
2856
2857 manc |= E1000_MANC_EN_MNG2HOST;
2858 manc2h = er32(MANC2H);
2859
2860 switch (hw->mac.type) {
2861 default:
2862 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2863 break;
2864 case e1000_82574:
2865 case e1000_82583:
2866
2867
2868
2869 for (i = 0, j = 0; i < 8; i++) {
2870 mdef = er32(MDEF(i));
2871
2872
2873 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2874 continue;
2875
2876
2877 if (mdef)
2878 manc2h |= BIT(i);
2879
2880 j |= mdef;
2881 }
2882
2883 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2884 break;
2885
2886
2887 for (i = 0, j = 0; i < 8; i++)
2888 if (er32(MDEF(i)) == 0) {
2889 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2890 E1000_MDEF_PORT_664));
2891 manc2h |= BIT(1);
2892 j++;
2893 break;
2894 }
2895
2896 if (!j)
2897 e_warn("Unable to create IPMI pass-through filter\n");
2898 break;
2899 }
2900
2901 ew32(MANC2H, manc2h);
2902 ew32(MANC, manc);
2903 }
2904
2905
2906
2907
2908
2909
2910
2911 static void e1000_configure_tx(struct e1000_adapter *adapter)
2912 {
2913 struct e1000_hw *hw = &adapter->hw;
2914 struct e1000_ring *tx_ring = adapter->tx_ring;
2915 u64 tdba;
2916 u32 tdlen, tctl, tarc;
2917
2918
2919 tdba = tx_ring->dma;
2920 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2921 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2922 ew32(TDBAH(0), (tdba >> 32));
2923 ew32(TDLEN(0), tdlen);
2924 ew32(TDH(0), 0);
2925 ew32(TDT(0), 0);
2926 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2927 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2928
2929 writel(0, tx_ring->head);
2930 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2931 e1000e_update_tdt_wa(tx_ring, 0);
2932 else
2933 writel(0, tx_ring->tail);
2934
2935
2936 ew32(TIDV, adapter->tx_int_delay);
2937
2938 ew32(TADV, adapter->tx_abs_int_delay);
2939
2940 if (adapter->flags2 & FLAG2_DMA_BURST) {
2941 u32 txdctl = er32(TXDCTL(0));
2942
2943 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2944 E1000_TXDCTL_WTHRESH);
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2955 ew32(TXDCTL(0), txdctl);
2956 }
2957
2958 ew32(TXDCTL(1), er32(TXDCTL(0)));
2959
2960
2961 tctl = er32(TCTL);
2962 tctl &= ~E1000_TCTL_CT;
2963 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2964 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2965
2966 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2967 tarc = er32(TARC(0));
2968
2969
2970
2971 #define SPEED_MODE_BIT BIT(21)
2972 tarc |= SPEED_MODE_BIT;
2973 ew32(TARC(0), tarc);
2974 }
2975
2976
2977 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2978 tarc = er32(TARC(0));
2979 tarc |= 1;
2980 ew32(TARC(0), tarc);
2981 tarc = er32(TARC(1));
2982 tarc |= 1;
2983 ew32(TARC(1), tarc);
2984 }
2985
2986
2987 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2988
2989
2990 if (adapter->tx_int_delay)
2991 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2992
2993
2994 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2995
2996 ew32(TCTL, tctl);
2997
2998 hw->mac.ops.config_collision_dist(hw);
2999
3000
3001 if (hw->mac.type == e1000_pch_spt) {
3002 u32 reg_val;
3003
3004 reg_val = er32(IOSFPC);
3005 reg_val |= E1000_RCTL_RDMTS_HEX;
3006 ew32(IOSFPC, reg_val);
3007
3008 reg_val = er32(TARC(0));
3009
3010
3011
3012
3013 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3014 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3015 ew32(TARC(0), reg_val);
3016 }
3017 }
3018
3019
3020
3021
3022
3023 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3024 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3025 static void e1000_setup_rctl(struct e1000_adapter *adapter)
3026 {
3027 struct e1000_hw *hw = &adapter->hw;
3028 u32 rctl, rfctl;
3029 u32 pages = 0;
3030
3031
3032
3033
3034
3035 if (hw->mac.type >= e1000_pch2lan) {
3036 s32 ret_val;
3037
3038 if (adapter->netdev->mtu > ETH_DATA_LEN)
3039 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3040 else
3041 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3042
3043 if (ret_val)
3044 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3045 }
3046
3047
3048 rctl = er32(RCTL);
3049 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3050 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3051 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3052 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3053
3054
3055 rctl &= ~E1000_RCTL_SBP;
3056
3057
3058 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3059 rctl &= ~E1000_RCTL_LPE;
3060 else
3061 rctl |= E1000_RCTL_LPE;
3062
3063
3064
3065
3066
3067 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3068 rctl |= E1000_RCTL_SECRC;
3069
3070
3071 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3072 u16 phy_data;
3073
3074 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3075 phy_data &= 0xfff8;
3076 phy_data |= BIT(2);
3077 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3078
3079 e1e_rphy(hw, 22, &phy_data);
3080 phy_data &= 0x0fff;
3081 phy_data |= BIT(14);
3082 e1e_wphy(hw, 0x10, 0x2823);
3083 e1e_wphy(hw, 0x11, 0x0003);
3084 e1e_wphy(hw, 22, phy_data);
3085 }
3086
3087
3088 rctl &= ~E1000_RCTL_SZ_4096;
3089 rctl |= E1000_RCTL_BSEX;
3090 switch (adapter->rx_buffer_len) {
3091 case 2048:
3092 default:
3093 rctl |= E1000_RCTL_SZ_2048;
3094 rctl &= ~E1000_RCTL_BSEX;
3095 break;
3096 case 4096:
3097 rctl |= E1000_RCTL_SZ_4096;
3098 break;
3099 case 8192:
3100 rctl |= E1000_RCTL_SZ_8192;
3101 break;
3102 case 16384:
3103 rctl |= E1000_RCTL_SZ_16384;
3104 break;
3105 }
3106
3107
3108 rfctl = er32(RFCTL);
3109 rfctl |= E1000_RFCTL_EXTEN;
3110 ew32(RFCTL, rfctl);
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3127 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3128 adapter->rx_ps_pages = pages;
3129 else
3130 adapter->rx_ps_pages = 0;
3131
3132 if (adapter->rx_ps_pages) {
3133 u32 psrctl = 0;
3134
3135
3136 rctl |= E1000_RCTL_DTYP_PS;
3137
3138 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3139
3140 switch (adapter->rx_ps_pages) {
3141 case 3:
3142 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3143
3144 case 2:
3145 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3146
3147 case 1:
3148 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3149 break;
3150 }
3151
3152 ew32(PSRCTL, psrctl);
3153 }
3154
3155
3156 if (adapter->netdev->features & NETIF_F_RXALL) {
3157
3158
3159
3160 rctl |= (E1000_RCTL_SBP |
3161 E1000_RCTL_BAM |
3162 E1000_RCTL_PMCF);
3163
3164 rctl &= ~(E1000_RCTL_VFE |
3165 E1000_RCTL_DPF |
3166 E1000_RCTL_CFIEN);
3167
3168
3169
3170 }
3171
3172 ew32(RCTL, rctl);
3173
3174 adapter->flags &= ~FLAG_RESTART_NOW;
3175 }
3176
3177
3178
3179
3180
3181
3182
3183 static void e1000_configure_rx(struct e1000_adapter *adapter)
3184 {
3185 struct e1000_hw *hw = &adapter->hw;
3186 struct e1000_ring *rx_ring = adapter->rx_ring;
3187 u64 rdba;
3188 u32 rdlen, rctl, rxcsum, ctrl_ext;
3189
3190 if (adapter->rx_ps_pages) {
3191
3192 rdlen = rx_ring->count *
3193 sizeof(union e1000_rx_desc_packet_split);
3194 adapter->clean_rx = e1000_clean_rx_irq_ps;
3195 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3196 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3197 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3198 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3199 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3200 } else {
3201 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3202 adapter->clean_rx = e1000_clean_rx_irq;
3203 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3204 }
3205
3206
3207 rctl = er32(RCTL);
3208 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3209 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3210 e1e_flush();
3211 usleep_range(10000, 11000);
3212
3213 if (adapter->flags2 & FLAG2_DMA_BURST) {
3214
3215
3216
3217
3218
3219
3220
3221
3222 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3223 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3224 }
3225
3226
3227 ew32(RDTR, adapter->rx_int_delay);
3228
3229
3230 ew32(RADV, adapter->rx_abs_int_delay);
3231 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3232 e1000e_write_itr(adapter, adapter->itr);
3233
3234 ctrl_ext = er32(CTRL_EXT);
3235
3236 ctrl_ext |= E1000_CTRL_EXT_IAME;
3237 ew32(IAM, 0xffffffff);
3238 ew32(CTRL_EXT, ctrl_ext);
3239 e1e_flush();
3240
3241
3242
3243
3244 rdba = rx_ring->dma;
3245 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3246 ew32(RDBAH(0), (rdba >> 32));
3247 ew32(RDLEN(0), rdlen);
3248 ew32(RDH(0), 0);
3249 ew32(RDT(0), 0);
3250 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3251 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3252
3253 writel(0, rx_ring->head);
3254 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3255 e1000e_update_rdt_wa(rx_ring, 0);
3256 else
3257 writel(0, rx_ring->tail);
3258
3259
3260 rxcsum = er32(RXCSUM);
3261 if (adapter->netdev->features & NETIF_F_RXCSUM)
3262 rxcsum |= E1000_RXCSUM_TUOFL;
3263 else
3264 rxcsum &= ~E1000_RXCSUM_TUOFL;
3265 ew32(RXCSUM, rxcsum);
3266
3267
3268
3269
3270 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3271 u32 lat =
3272 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3273 adapter->max_frame_size) * 8 / 1000;
3274
3275 if (adapter->flags & FLAG_IS_ICH) {
3276 u32 rxdctl = er32(RXDCTL(0));
3277
3278 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3279 }
3280
3281 dev_info(&adapter->pdev->dev,
3282 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3283 pm_qos_update_request(&adapter->pm_qos_req, lat);
3284 } else {
3285 pm_qos_update_request(&adapter->pm_qos_req,
3286 PM_QOS_DEFAULT_VALUE);
3287 }
3288
3289
3290 ew32(RCTL, rctl);
3291 }
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302 static int e1000e_write_mc_addr_list(struct net_device *netdev)
3303 {
3304 struct e1000_adapter *adapter = netdev_priv(netdev);
3305 struct e1000_hw *hw = &adapter->hw;
3306 struct netdev_hw_addr *ha;
3307 u8 *mta_list;
3308 int i;
3309
3310 if (netdev_mc_empty(netdev)) {
3311
3312 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3313 return 0;
3314 }
3315
3316 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3317 if (!mta_list)
3318 return -ENOMEM;
3319
3320
3321 i = 0;
3322 netdev_for_each_mc_addr(ha, netdev)
3323 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3324
3325 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3326 kfree(mta_list);
3327
3328 return netdev_mc_count(netdev);
3329 }
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340 static int e1000e_write_uc_addr_list(struct net_device *netdev)
3341 {
3342 struct e1000_adapter *adapter = netdev_priv(netdev);
3343 struct e1000_hw *hw = &adapter->hw;
3344 unsigned int rar_entries;
3345 int count = 0;
3346
3347 rar_entries = hw->mac.ops.rar_get_count(hw);
3348
3349
3350 rar_entries--;
3351
3352
3353 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3354 rar_entries--;
3355
3356
3357 if (netdev_uc_count(netdev) > rar_entries)
3358 return -ENOMEM;
3359
3360 if (!netdev_uc_empty(netdev) && rar_entries) {
3361 struct netdev_hw_addr *ha;
3362
3363
3364
3365
3366 netdev_for_each_uc_addr(ha, netdev) {
3367 int ret_val;
3368
3369 if (!rar_entries)
3370 break;
3371 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3372 if (ret_val < 0)
3373 return -ENOMEM;
3374 count++;
3375 }
3376 }
3377
3378
3379 for (; rar_entries > 0; rar_entries--) {
3380 ew32(RAH(rar_entries), 0);
3381 ew32(RAL(rar_entries), 0);
3382 }
3383 e1e_flush();
3384
3385 return count;
3386 }
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397 static void e1000e_set_rx_mode(struct net_device *netdev)
3398 {
3399 struct e1000_adapter *adapter = netdev_priv(netdev);
3400 struct e1000_hw *hw = &adapter->hw;
3401 u32 rctl;
3402
3403 if (pm_runtime_suspended(netdev->dev.parent))
3404 return;
3405
3406
3407 rctl = er32(RCTL);
3408
3409
3410 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3411
3412 if (netdev->flags & IFF_PROMISC) {
3413 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3414
3415 e1000e_vlan_filter_disable(adapter);
3416 } else {
3417 int count;
3418
3419 if (netdev->flags & IFF_ALLMULTI) {
3420 rctl |= E1000_RCTL_MPE;
3421 } else {
3422
3423
3424
3425
3426 count = e1000e_write_mc_addr_list(netdev);
3427 if (count < 0)
3428 rctl |= E1000_RCTL_MPE;
3429 }
3430 e1000e_vlan_filter_enable(adapter);
3431
3432
3433
3434
3435 count = e1000e_write_uc_addr_list(netdev);
3436 if (count < 0)
3437 rctl |= E1000_RCTL_UPE;
3438 }
3439
3440 ew32(RCTL, rctl);
3441
3442 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3443 e1000e_vlan_strip_enable(adapter);
3444 else
3445 e1000e_vlan_strip_disable(adapter);
3446 }
3447
3448 static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3449 {
3450 struct e1000_hw *hw = &adapter->hw;
3451 u32 mrqc, rxcsum;
3452 u32 rss_key[10];
3453 int i;
3454
3455 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3456 for (i = 0; i < 10; i++)
3457 ew32(RSSRK(i), rss_key[i]);
3458
3459
3460 for (i = 0; i < 32; i++)
3461 ew32(RETA(i), 0);
3462
3463
3464
3465
3466 rxcsum = er32(RXCSUM);
3467 rxcsum |= E1000_RXCSUM_PCSD;
3468
3469 ew32(RXCSUM, rxcsum);
3470
3471 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3472 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3473 E1000_MRQC_RSS_FIELD_IPV6 |
3474 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3475 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3476
3477 ew32(MRQC, mrqc);
3478 }
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3489 {
3490 struct e1000_hw *hw = &adapter->hw;
3491 u32 incvalue, incperiod, shift;
3492
3493
3494
3495
3496 if ((hw->mac.type >= e1000_pch_lpt) &&
3497 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3498 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3499 u32 fextnvm7 = er32(FEXTNVM7);
3500
3501 if (!(fextnvm7 & BIT(0))) {
3502 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3503 e1e_flush();
3504 }
3505 }
3506
3507 switch (hw->mac.type) {
3508 case e1000_pch2lan:
3509
3510 incperiod = INCPERIOD_96MHZ;
3511 incvalue = INCVALUE_96MHZ;
3512 shift = INCVALUE_SHIFT_96MHZ;
3513 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3514 break;
3515 case e1000_pch_lpt:
3516 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3517
3518 incperiod = INCPERIOD_96MHZ;
3519 incvalue = INCVALUE_96MHZ;
3520 shift = INCVALUE_SHIFT_96MHZ;
3521 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3522 } else {
3523
3524 incperiod = INCPERIOD_25MHZ;
3525 incvalue = INCVALUE_25MHZ;
3526 shift = INCVALUE_SHIFT_25MHZ;
3527 adapter->cc.shift = shift;
3528 }
3529 break;
3530 case e1000_pch_spt:
3531
3532 incperiod = INCPERIOD_24MHZ;
3533 incvalue = INCVALUE_24MHZ;
3534 shift = INCVALUE_SHIFT_24MHZ;
3535 adapter->cc.shift = shift;
3536 break;
3537 case e1000_pch_cnp:
3538 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3539
3540 incperiod = INCPERIOD_24MHZ;
3541 incvalue = INCVALUE_24MHZ;
3542 shift = INCVALUE_SHIFT_24MHZ;
3543 adapter->cc.shift = shift;
3544 } else {
3545
3546 incperiod = INCPERIOD_38400KHZ;
3547 incvalue = INCVALUE_38400KHZ;
3548 shift = INCVALUE_SHIFT_38400KHZ;
3549 adapter->cc.shift = shift;
3550 }
3551 break;
3552 case e1000_82574:
3553 case e1000_82583:
3554
3555 incperiod = INCPERIOD_25MHZ;
3556 incvalue = INCVALUE_25MHZ;
3557 shift = INCVALUE_SHIFT_25MHZ;
3558 adapter->cc.shift = shift;
3559 break;
3560 default:
3561 return -EINVAL;
3562 }
3563
3564 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3565 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3566
3567 return 0;
3568 }
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585 static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3586 struct hwtstamp_config *config)
3587 {
3588 struct e1000_hw *hw = &adapter->hw;
3589 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3590 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3591 u32 rxmtrl = 0;
3592 u16 rxudp = 0;
3593 bool is_l4 = false;
3594 bool is_l2 = false;
3595 u32 regval;
3596
3597 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3598 return -EINVAL;
3599
3600
3601 if (config->flags)
3602 return -EINVAL;
3603
3604 switch (config->tx_type) {
3605 case HWTSTAMP_TX_OFF:
3606 tsync_tx_ctl = 0;
3607 break;
3608 case HWTSTAMP_TX_ON:
3609 break;
3610 default:
3611 return -ERANGE;
3612 }
3613
3614 switch (config->rx_filter) {
3615 case HWTSTAMP_FILTER_NONE:
3616 tsync_rx_ctl = 0;
3617 break;
3618 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3619 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3620 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3621 is_l4 = true;
3622 break;
3623 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3624 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3625 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3626 is_l4 = true;
3627 break;
3628 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3629
3630 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3631 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3632 is_l2 = true;
3633 break;
3634 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3635
3636 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3637 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3638 is_l2 = true;
3639 break;
3640 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3641
3642
3643
3644 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3645
3646 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3647 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3648 is_l2 = true;
3649 is_l4 = true;
3650 break;
3651 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3652
3653
3654
3655 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3656
3657 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3658 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3659 is_l2 = true;
3660 is_l4 = true;
3661 break;
3662 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3663 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3664
3665
3666
3667 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3668 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3669 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3670 is_l2 = true;
3671 is_l4 = true;
3672 break;
3673 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3674
3675
3676
3677
3678 case HWTSTAMP_FILTER_NTP_ALL:
3679 case HWTSTAMP_FILTER_ALL:
3680 is_l2 = true;
3681 is_l4 = true;
3682 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3683 config->rx_filter = HWTSTAMP_FILTER_ALL;
3684 break;
3685 default:
3686 return -ERANGE;
3687 }
3688
3689 adapter->hwtstamp_config = *config;
3690
3691
3692 regval = er32(TSYNCTXCTL);
3693 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3694 regval |= tsync_tx_ctl;
3695 ew32(TSYNCTXCTL, regval);
3696 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3697 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3698 e_err("Timesync Tx Control register not set as expected\n");
3699 return -EAGAIN;
3700 }
3701
3702
3703 regval = er32(TSYNCRXCTL);
3704 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3705 regval |= tsync_rx_ctl;
3706 ew32(TSYNCRXCTL, regval);
3707 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3708 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3709 (regval & (E1000_TSYNCRXCTL_ENABLED |
3710 E1000_TSYNCRXCTL_TYPE_MASK))) {
3711 e_err("Timesync Rx Control register not set as expected\n");
3712 return -EAGAIN;
3713 }
3714
3715
3716 if (is_l2)
3717 rxmtrl |= ETH_P_1588;
3718
3719
3720 ew32(RXMTRL, rxmtrl);
3721
3722
3723 if (is_l4) {
3724 rxudp = PTP_EV_PORT;
3725 cpu_to_be16s(&rxudp);
3726 }
3727 ew32(RXUDP, rxudp);
3728
3729 e1e_flush();
3730
3731
3732 er32(RXSTMPH);
3733 er32(TXSTMPH);
3734
3735 return 0;
3736 }
3737
3738
3739
3740
3741
3742 static void e1000_configure(struct e1000_adapter *adapter)
3743 {
3744 struct e1000_ring *rx_ring = adapter->rx_ring;
3745
3746 e1000e_set_rx_mode(adapter->netdev);
3747
3748 e1000_restore_vlan(adapter);
3749 e1000_init_manageability_pt(adapter);
3750
3751 e1000_configure_tx(adapter);
3752
3753 if (adapter->netdev->features & NETIF_F_RXHASH)
3754 e1000e_setup_rss_hash(adapter);
3755 e1000_setup_rctl(adapter);
3756 e1000_configure_rx(adapter);
3757 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3758 }
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768 void e1000e_power_up_phy(struct e1000_adapter *adapter)
3769 {
3770 if (adapter->hw.phy.ops.power_up)
3771 adapter->hw.phy.ops.power_up(&adapter->hw);
3772
3773 adapter->hw.mac.ops.setup_link(&adapter->hw);
3774 }
3775
3776
3777
3778
3779
3780
3781
3782 static void e1000_power_down_phy(struct e1000_adapter *adapter)
3783 {
3784 if (adapter->hw.phy.ops.power_down)
3785 adapter->hw.phy.ops.power_down(&adapter->hw);
3786 }
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796 static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3797 {
3798 struct e1000_hw *hw = &adapter->hw;
3799 struct e1000_ring *tx_ring = adapter->tx_ring;
3800 struct e1000_tx_desc *tx_desc = NULL;
3801 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3802 u16 size = 512;
3803
3804 tctl = er32(TCTL);
3805 ew32(TCTL, tctl | E1000_TCTL_EN);
3806 tdt = er32(TDT(0));
3807 BUG_ON(tdt != tx_ring->next_to_use);
3808 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3809 tx_desc->buffer_addr = tx_ring->dma;
3810
3811 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3812 tx_desc->upper.data = 0;
3813
3814 wmb();
3815 tx_ring->next_to_use++;
3816 if (tx_ring->next_to_use == tx_ring->count)
3817 tx_ring->next_to_use = 0;
3818 ew32(TDT(0), tx_ring->next_to_use);
3819 usleep_range(200, 250);
3820 }
3821
3822
3823
3824
3825
3826
3827 static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3828 {
3829 u32 rctl, rxdctl;
3830 struct e1000_hw *hw = &adapter->hw;
3831
3832 rctl = er32(RCTL);
3833 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3834 e1e_flush();
3835 usleep_range(100, 150);
3836
3837 rxdctl = er32(RXDCTL(0));
3838
3839 rxdctl &= 0xffffc000;
3840
3841
3842
3843
3844 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3845
3846 ew32(RXDCTL(0), rxdctl);
3847
3848 ew32(RCTL, rctl | E1000_RCTL_EN);
3849 e1e_flush();
3850 usleep_range(100, 150);
3851 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3852 }
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865 static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3866 {
3867 u16 hang_state;
3868 u32 fext_nvm11, tdlen;
3869 struct e1000_hw *hw = &adapter->hw;
3870
3871
3872 fext_nvm11 = er32(FEXTNVM11);
3873 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3874 ew32(FEXTNVM11, fext_nvm11);
3875
3876 tdlen = er32(TDLEN(0));
3877 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3878 &hang_state);
3879 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3880 return;
3881 e1000_flush_tx_ring(adapter);
3882
3883 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3884 &hang_state);
3885 if (hang_state & FLUSH_DESC_REQUIRED)
3886 e1000_flush_rx_ring(adapter);
3887 }
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898 static void e1000e_systim_reset(struct e1000_adapter *adapter)
3899 {
3900 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3901 struct e1000_hw *hw = &adapter->hw;
3902 unsigned long flags;
3903 u32 timinca;
3904 s32 ret_val;
3905
3906 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3907 return;
3908
3909 if (info->adjfreq) {
3910
3911 ret_val = info->adjfreq(info, adapter->ptp_delta);
3912 } else {
3913
3914 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3915 if (!ret_val)
3916 ew32(TIMINCA, timinca);
3917 }
3918
3919 if (ret_val) {
3920 dev_warn(&adapter->pdev->dev,
3921 "Failed to restore TIMINCA clock rate delta: %d\n",
3922 ret_val);
3923 return;
3924 }
3925
3926
3927 spin_lock_irqsave(&adapter->systim_lock, flags);
3928 timecounter_init(&adapter->tc, &adapter->cc,
3929 ktime_to_ns(ktime_get_real()));
3930 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3931
3932
3933 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3934 }
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944 void e1000e_reset(struct e1000_adapter *adapter)
3945 {
3946 struct e1000_mac_info *mac = &adapter->hw.mac;
3947 struct e1000_fc_info *fc = &adapter->hw.fc;
3948 struct e1000_hw *hw = &adapter->hw;
3949 u32 tx_space, min_tx_space, min_rx_space;
3950 u32 pba = adapter->pba;
3951 u16 hwm;
3952
3953
3954 ew32(PBA, pba);
3955
3956 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3957
3958
3959
3960
3961
3962
3963
3964 pba = er32(PBA);
3965
3966 tx_space = pba >> 16;
3967
3968 pba &= 0xffff;
3969
3970
3971
3972 min_tx_space = (adapter->max_frame_size +
3973 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3974 min_tx_space = ALIGN(min_tx_space, 1024);
3975 min_tx_space >>= 10;
3976
3977 min_rx_space = adapter->max_frame_size;
3978 min_rx_space = ALIGN(min_rx_space, 1024);
3979 min_rx_space >>= 10;
3980
3981
3982
3983
3984
3985 if ((tx_space < min_tx_space) &&
3986 ((min_tx_space - tx_space) < pba)) {
3987 pba -= min_tx_space - tx_space;
3988
3989
3990
3991
3992 if (pba < min_rx_space)
3993 pba = min_rx_space;
3994 }
3995
3996 ew32(PBA, pba);
3997 }
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4008 fc->pause_time = 0xFFFF;
4009 else
4010 fc->pause_time = E1000_FC_PAUSE_TIME;
4011 fc->send_xon = true;
4012 fc->current_mode = fc->requested_mode;
4013
4014 switch (hw->mac.type) {
4015 case e1000_ich9lan:
4016 case e1000_ich10lan:
4017 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4018 pba = 14;
4019 ew32(PBA, pba);
4020 fc->high_water = 0x2800;
4021 fc->low_water = fc->high_water - 8;
4022 break;
4023 }
4024
4025 default:
4026 hwm = min(((pba << 10) * 9 / 10),
4027 ((pba << 10) - adapter->max_frame_size));
4028
4029 fc->high_water = hwm & E1000_FCRTH_RTH;
4030 fc->low_water = fc->high_water - 8;
4031 break;
4032 case e1000_pchlan:
4033
4034
4035
4036 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4037 fc->high_water = 0x3500;
4038 fc->low_water = 0x1500;
4039 } else {
4040 fc->high_water = 0x5000;
4041 fc->low_water = 0x3000;
4042 }
4043 fc->refresh_time = 0x1000;
4044 break;
4045 case e1000_pch2lan:
4046 case e1000_pch_lpt:
4047 case e1000_pch_spt:
4048 case e1000_pch_cnp:
4049 fc->refresh_time = 0xFFFF;
4050 fc->pause_time = 0xFFFF;
4051
4052 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4053 fc->high_water = 0x05C20;
4054 fc->low_water = 0x05048;
4055 break;
4056 }
4057
4058 pba = 14;
4059 ew32(PBA, pba);
4060 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4061 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4062 break;
4063 }
4064
4065
4066
4067
4068
4069
4070 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4071 24 << 10);
4072
4073
4074
4075
4076 if (adapter->itr_setting & 0x3) {
4077 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4078 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4079 dev_info(&adapter->pdev->dev,
4080 "Interrupt Throttle Rate off\n");
4081 adapter->flags2 |= FLAG2_DISABLE_AIM;
4082 e1000e_write_itr(adapter, 0);
4083 }
4084 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4085 dev_info(&adapter->pdev->dev,
4086 "Interrupt Throttle Rate on\n");
4087 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4088 adapter->itr = 20000;
4089 e1000e_write_itr(adapter, adapter->itr);
4090 }
4091 }
4092
4093 if (hw->mac.type >= e1000_pch_spt)
4094 e1000_flush_desc_rings(adapter);
4095
4096 mac->ops.reset_hw(hw);
4097
4098
4099
4100
4101 if (adapter->flags & FLAG_HAS_AMT)
4102 e1000e_get_hw_control(adapter);
4103
4104 ew32(WUC, 0);
4105
4106 if (mac->ops.init_hw(hw))
4107 e_err("Hardware Error\n");
4108
4109 e1000_update_mng_vlan(adapter);
4110
4111
4112 ew32(VET, ETH_P_8021Q);
4113
4114 e1000e_reset_adaptive(hw);
4115
4116
4117 e1000e_systim_reset(adapter);
4118
4119
4120 if (adapter->flags2 & FLAG2_HAS_EEE) {
4121 s32 ret_val;
4122 u16 adv_addr;
4123
4124 switch (hw->phy.type) {
4125 case e1000_phy_82579:
4126 adv_addr = I82579_EEE_ADVERTISEMENT;
4127 break;
4128 case e1000_phy_i217:
4129 adv_addr = I217_EEE_ADVERTISEMENT;
4130 break;
4131 default:
4132 dev_err(&adapter->pdev->dev,
4133 "Invalid PHY type setting EEE advertisement\n");
4134 return;
4135 }
4136
4137 ret_val = hw->phy.ops.acquire(hw);
4138 if (ret_val) {
4139 dev_err(&adapter->pdev->dev,
4140 "EEE advertisement - unable to acquire PHY\n");
4141 return;
4142 }
4143
4144 e1000_write_emi_reg_locked(hw, adv_addr,
4145 hw->dev_spec.ich8lan.eee_disable ?
4146 0 : adapter->eee_advert);
4147
4148 hw->phy.ops.release(hw);
4149 }
4150
4151 if (!netif_running(adapter->netdev) &&
4152 !test_bit(__E1000_TESTING, &adapter->state))
4153 e1000_power_down_phy(adapter);
4154
4155 e1000_get_phy_info(hw);
4156
4157 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4158 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4159 u16 phy_data = 0;
4160
4161
4162
4163
4164 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4165 phy_data &= ~IGP02E1000_PM_SPD;
4166 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4167 }
4168 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4169 u32 reg;
4170
4171
4172 reg = er32(FEXTNVM7);
4173 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4174 ew32(FEXTNVM7, reg);
4175
4176 reg = er32(FEXTNVM9);
4177 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4178 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4179 ew32(FEXTNVM9, reg);
4180 }
4181
4182 }
4183
4184
4185
4186
4187
4188
4189
4190 static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4191 {
4192 struct e1000_hw *hw = &adapter->hw;
4193
4194 if (adapter->msix_entries)
4195 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4196 else
4197 ew32(ICS, E1000_ICS_LSC);
4198 }
4199
4200 void e1000e_up(struct e1000_adapter *adapter)
4201 {
4202
4203 e1000_configure(adapter);
4204
4205 clear_bit(__E1000_DOWN, &adapter->state);
4206
4207 if (adapter->msix_entries)
4208 e1000_configure_msix(adapter);
4209 e1000_irq_enable(adapter);
4210
4211
4212
4213 e1000e_trigger_lsc(adapter);
4214 }
4215
4216 static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4217 {
4218 struct e1000_hw *hw = &adapter->hw;
4219
4220 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4221 return;
4222
4223
4224 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4225 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4226
4227
4228 e1e_flush();
4229
4230
4231
4232
4233 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4234 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4235
4236
4237 e1e_flush();
4238 }
4239
4240 static void e1000e_update_stats(struct e1000_adapter *adapter);
4241
4242
4243
4244
4245
4246
4247 void e1000e_down(struct e1000_adapter *adapter, bool reset)
4248 {
4249 struct net_device *netdev = adapter->netdev;
4250 struct e1000_hw *hw = &adapter->hw;
4251 u32 tctl, rctl;
4252
4253
4254
4255
4256 set_bit(__E1000_DOWN, &adapter->state);
4257
4258 netif_carrier_off(netdev);
4259
4260
4261 rctl = er32(RCTL);
4262 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4263 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4264
4265
4266 netif_stop_queue(netdev);
4267
4268
4269 tctl = er32(TCTL);
4270 tctl &= ~E1000_TCTL_EN;
4271 ew32(TCTL, tctl);
4272
4273
4274 e1e_flush();
4275 usleep_range(10000, 11000);
4276
4277 e1000_irq_disable(adapter);
4278
4279 napi_synchronize(&adapter->napi);
4280
4281 del_timer_sync(&adapter->watchdog_timer);
4282 del_timer_sync(&adapter->phy_info_timer);
4283
4284 spin_lock(&adapter->stats64_lock);
4285 e1000e_update_stats(adapter);
4286 spin_unlock(&adapter->stats64_lock);
4287
4288 e1000e_flush_descriptors(adapter);
4289
4290 adapter->link_speed = 0;
4291 adapter->link_duplex = 0;
4292
4293
4294 if ((hw->mac.type >= e1000_pch2lan) &&
4295 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4296 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4297 e_dbg("failed to disable jumbo frame workaround mode\n");
4298
4299 if (!pci_channel_offline(adapter->pdev)) {
4300 if (reset)
4301 e1000e_reset(adapter);
4302 else if (hw->mac.type >= e1000_pch_spt)
4303 e1000_flush_desc_rings(adapter);
4304 }
4305 e1000_clean_tx_ring(adapter->tx_ring);
4306 e1000_clean_rx_ring(adapter->rx_ring);
4307 }
4308
4309 void e1000e_reinit_locked(struct e1000_adapter *adapter)
4310 {
4311 might_sleep();
4312 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4313 usleep_range(1000, 1100);
4314 e1000e_down(adapter, true);
4315 e1000e_up(adapter);
4316 clear_bit(__E1000_RESETTING, &adapter->state);
4317 }
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330 static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4331 struct ptp_system_timestamp *sts)
4332 {
4333 u64 time_delta, rem, temp;
4334 u64 systim_next;
4335 u32 incvalue;
4336 int i;
4337
4338 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4339 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4340
4341 ptp_read_system_prets(sts);
4342 systim_next = (u64)er32(SYSTIML);
4343 ptp_read_system_postts(sts);
4344 systim_next |= (u64)er32(SYSTIMH) << 32;
4345
4346 time_delta = systim_next - systim;
4347 temp = time_delta;
4348
4349 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4350
4351 systim = systim_next;
4352
4353 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4354 break;
4355 }
4356
4357 return systim;
4358 }
4359
4360
4361
4362
4363
4364
4365
4366 u64 e1000e_read_systim(struct e1000_adapter *adapter,
4367 struct ptp_system_timestamp *sts)
4368 {
4369 struct e1000_hw *hw = &adapter->hw;
4370 u32 systimel, systimel_2, systimeh;
4371 u64 systim;
4372
4373
4374
4375
4376
4377
4378 ptp_read_system_prets(sts);
4379 systimel = er32(SYSTIML);
4380 ptp_read_system_postts(sts);
4381 systimeh = er32(SYSTIMH);
4382
4383 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4384 ptp_read_system_prets(sts);
4385 systimel_2 = er32(SYSTIML);
4386 ptp_read_system_postts(sts);
4387 if (systimel > systimel_2) {
4388
4389
4390
4391 systimeh = er32(SYSTIMH);
4392 systimel = systimel_2;
4393 }
4394 }
4395 systim = (u64)systimel;
4396 systim |= (u64)systimeh << 32;
4397
4398 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4399 systim = e1000e_sanitize_systim(hw, systim, sts);
4400
4401 return systim;
4402 }
4403
4404
4405
4406
4407
4408 static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc)
4409 {
4410 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4411 cc);
4412
4413 return e1000e_read_systim(adapter, NULL);
4414 }
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424 static int e1000_sw_init(struct e1000_adapter *adapter)
4425 {
4426 struct net_device *netdev = adapter->netdev;
4427
4428 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4429 adapter->rx_ps_bsize0 = 128;
4430 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4431 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4432 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4433 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4434
4435 spin_lock_init(&adapter->stats64_lock);
4436
4437 e1000e_set_interrupt_capability(adapter);
4438
4439 if (e1000_alloc_queues(adapter))
4440 return -ENOMEM;
4441
4442
4443 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4444 adapter->cc.read = e1000e_cyclecounter_read;
4445 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4446 adapter->cc.mult = 1;
4447
4448
4449 spin_lock_init(&adapter->systim_lock);
4450 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4451 }
4452
4453
4454 e1000_irq_disable(adapter);
4455
4456 set_bit(__E1000_DOWN, &adapter->state);
4457 return 0;
4458 }
4459
4460
4461
4462
4463
4464
4465 static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4466 {
4467 struct net_device *netdev = data;
4468 struct e1000_adapter *adapter = netdev_priv(netdev);
4469 struct e1000_hw *hw = &adapter->hw;
4470 u32 icr = er32(ICR);
4471
4472 e_dbg("icr is %08X\n", icr);
4473 if (icr & E1000_ICR_RXSEQ) {
4474 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4475
4476
4477
4478 wmb();
4479 }
4480
4481 return IRQ_HANDLED;
4482 }
4483
4484
4485
4486
4487
4488
4489
4490 static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4491 {
4492 struct net_device *netdev = adapter->netdev;
4493 struct e1000_hw *hw = &adapter->hw;
4494 int err;
4495
4496
4497
4498 er32(ICR);
4499
4500
4501 e1000_free_irq(adapter);
4502 e1000e_reset_interrupt_capability(adapter);
4503
4504
4505
4506
4507 adapter->flags |= FLAG_MSI_TEST_FAILED;
4508
4509 err = pci_enable_msi(adapter->pdev);
4510 if (err)
4511 goto msi_test_failed;
4512
4513 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4514 netdev->name, netdev);
4515 if (err) {
4516 pci_disable_msi(adapter->pdev);
4517 goto msi_test_failed;
4518 }
4519
4520
4521
4522
4523 wmb();
4524
4525 e1000_irq_enable(adapter);
4526
4527
4528 ew32(ICS, E1000_ICS_RXSEQ);
4529 e1e_flush();
4530 msleep(100);
4531
4532 e1000_irq_disable(adapter);
4533
4534 rmb();
4535
4536 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4537 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4538 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4539 } else {
4540 e_dbg("MSI interrupt test succeeded!\n");
4541 }
4542
4543 free_irq(adapter->pdev->irq, netdev);
4544 pci_disable_msi(adapter->pdev);
4545
4546 msi_test_failed:
4547 e1000e_set_interrupt_capability(adapter);
4548 return e1000_request_irq(adapter);
4549 }
4550
4551
4552
4553
4554
4555
4556
4557 static int e1000_test_msi(struct e1000_adapter *adapter)
4558 {
4559 int err;
4560 u16 pci_cmd;
4561
4562 if (!(adapter->flags & FLAG_MSI_ENABLED))
4563 return 0;
4564
4565
4566 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4567 if (pci_cmd & PCI_COMMAND_SERR)
4568 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4569 pci_cmd & ~PCI_COMMAND_SERR);
4570
4571 err = e1000_test_msi_interrupt(adapter);
4572
4573
4574 if (pci_cmd & PCI_COMMAND_SERR) {
4575 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4576 pci_cmd |= PCI_COMMAND_SERR;
4577 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4578 }
4579
4580 return err;
4581 }
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595 int e1000e_open(struct net_device *netdev)
4596 {
4597 struct e1000_adapter *adapter = netdev_priv(netdev);
4598 struct e1000_hw *hw = &adapter->hw;
4599 struct pci_dev *pdev = adapter->pdev;
4600 int err;
4601
4602
4603 if (test_bit(__E1000_TESTING, &adapter->state))
4604 return -EBUSY;
4605
4606 pm_runtime_get_sync(&pdev->dev);
4607
4608 netif_carrier_off(netdev);
4609 netif_stop_queue(netdev);
4610
4611
4612 err = e1000e_setup_tx_resources(adapter->tx_ring);
4613 if (err)
4614 goto err_setup_tx;
4615
4616
4617 err = e1000e_setup_rx_resources(adapter->rx_ring);
4618 if (err)
4619 goto err_setup_rx;
4620
4621
4622
4623
4624 if (adapter->flags & FLAG_HAS_AMT) {
4625 e1000e_get_hw_control(adapter);
4626 e1000e_reset(adapter);
4627 }
4628
4629 e1000e_power_up_phy(adapter);
4630
4631 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4632 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4633 e1000_update_mng_vlan(adapter);
4634
4635
4636 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4637 PM_QOS_DEFAULT_VALUE);
4638
4639
4640
4641
4642
4643
4644 e1000_configure(adapter);
4645
4646 err = e1000_request_irq(adapter);
4647 if (err)
4648 goto err_req_irq;
4649
4650
4651
4652
4653
4654 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4655 err = e1000_test_msi(adapter);
4656 if (err) {
4657 e_err("Interrupt allocation failed\n");
4658 goto err_req_irq;
4659 }
4660 }
4661
4662
4663 clear_bit(__E1000_DOWN, &adapter->state);
4664
4665 napi_enable(&adapter->napi);
4666
4667 e1000_irq_enable(adapter);
4668
4669 adapter->tx_hang_recheck = false;
4670
4671 hw->mac.get_link_status = true;
4672 pm_runtime_put(&pdev->dev);
4673
4674 e1000e_trigger_lsc(adapter);
4675
4676 return 0;
4677
4678 err_req_irq:
4679 pm_qos_remove_request(&adapter->pm_qos_req);
4680 e1000e_release_hw_control(adapter);
4681 e1000_power_down_phy(adapter);
4682 e1000e_free_rx_resources(adapter->rx_ring);
4683 err_setup_rx:
4684 e1000e_free_tx_resources(adapter->tx_ring);
4685 err_setup_tx:
4686 e1000e_reset(adapter);
4687 pm_runtime_put_sync(&pdev->dev);
4688
4689 return err;
4690 }
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703 int e1000e_close(struct net_device *netdev)
4704 {
4705 struct e1000_adapter *adapter = netdev_priv(netdev);
4706 struct pci_dev *pdev = adapter->pdev;
4707 int count = E1000_CHECK_RESET_COUNT;
4708
4709 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4710 usleep_range(10000, 11000);
4711
4712 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4713
4714 pm_runtime_get_sync(&pdev->dev);
4715
4716 if (netif_device_present(netdev)) {
4717 e1000e_down(adapter, true);
4718 e1000_free_irq(adapter);
4719
4720
4721 pr_info("%s NIC Link is Down\n", netdev->name);
4722 }
4723
4724 napi_disable(&adapter->napi);
4725
4726 e1000e_free_tx_resources(adapter->tx_ring);
4727 e1000e_free_rx_resources(adapter->rx_ring);
4728
4729
4730
4731
4732 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4733 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4734 adapter->mng_vlan_id);
4735
4736
4737
4738
4739 if ((adapter->flags & FLAG_HAS_AMT) &&
4740 !test_bit(__E1000_TESTING, &adapter->state))
4741 e1000e_release_hw_control(adapter);
4742
4743 pm_qos_remove_request(&adapter->pm_qos_req);
4744
4745 pm_runtime_put_sync(&pdev->dev);
4746
4747 return 0;
4748 }
4749
4750
4751
4752
4753
4754
4755
4756
4757 static int e1000_set_mac(struct net_device *netdev, void *p)
4758 {
4759 struct e1000_adapter *adapter = netdev_priv(netdev);
4760 struct e1000_hw *hw = &adapter->hw;
4761 struct sockaddr *addr = p;
4762
4763 if (!is_valid_ether_addr(addr->sa_data))
4764 return -EADDRNOTAVAIL;
4765
4766 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4767 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4768
4769 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4770
4771 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4772
4773 e1000e_set_laa_state_82571(&adapter->hw, 1);
4774
4775
4776
4777
4778
4779
4780
4781
4782 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4783 adapter->hw.mac.rar_entry_count - 1);
4784 }
4785
4786 return 0;
4787 }
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797 static void e1000e_update_phy_task(struct work_struct *work)
4798 {
4799 struct e1000_adapter *adapter = container_of(work,
4800 struct e1000_adapter,
4801 update_phy_task);
4802 struct e1000_hw *hw = &adapter->hw;
4803
4804 if (test_bit(__E1000_DOWN, &adapter->state))
4805 return;
4806
4807 e1000_get_phy_info(hw);
4808
4809
4810 if (hw->phy.type >= e1000_phy_82579)
4811 e1000_set_eee_pchlan(hw);
4812 }
4813
4814
4815
4816
4817
4818
4819
4820
4821 static void e1000_update_phy_info(struct timer_list *t)
4822 {
4823 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4824
4825 if (test_bit(__E1000_DOWN, &adapter->state))
4826 return;
4827
4828 schedule_work(&adapter->update_phy_task);
4829 }
4830
4831
4832
4833
4834
4835
4836
4837 static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4838 {
4839 struct e1000_hw *hw = &adapter->hw;
4840 s32 ret_val;
4841 u16 phy_data;
4842
4843 ret_val = hw->phy.ops.acquire(hw);
4844 if (ret_val)
4845 return;
4846
4847
4848
4849
4850 hw->phy.addr = 1;
4851 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4852 &phy_data);
4853 if (ret_val)
4854 goto release;
4855 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4856 ret_val = hw->phy.ops.set_page(hw,
4857 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4858 if (ret_val)
4859 goto release;
4860 }
4861
4862
4863 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4864 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4865 if (!ret_val)
4866 adapter->stats.scc += phy_data;
4867
4868
4869 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4870 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4871 if (!ret_val)
4872 adapter->stats.ecol += phy_data;
4873
4874
4875 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4876 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4877 if (!ret_val)
4878 adapter->stats.mcc += phy_data;
4879
4880
4881 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4882 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4883 if (!ret_val)
4884 adapter->stats.latecol += phy_data;
4885
4886
4887 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4888 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4889 if (!ret_val)
4890 hw->mac.collision_delta = phy_data;
4891
4892
4893 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4894 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4895 if (!ret_val)
4896 adapter->stats.dc += phy_data;
4897
4898
4899 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4900 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4901 if (!ret_val)
4902 adapter->stats.tncrs += phy_data;
4903
4904 release:
4905 hw->phy.ops.release(hw);
4906 }
4907
4908
4909
4910
4911
4912 static void e1000e_update_stats(struct e1000_adapter *adapter)
4913 {
4914 struct net_device *netdev = adapter->netdev;
4915 struct e1000_hw *hw = &adapter->hw;
4916 struct pci_dev *pdev = adapter->pdev;
4917
4918
4919
4920
4921 if (adapter->link_speed == 0)
4922 return;
4923 if (pci_channel_offline(pdev))
4924 return;
4925
4926 adapter->stats.crcerrs += er32(CRCERRS);
4927 adapter->stats.gprc += er32(GPRC);
4928 adapter->stats.gorc += er32(GORCL);
4929 er32(GORCH);
4930 adapter->stats.bprc += er32(BPRC);
4931 adapter->stats.mprc += er32(MPRC);
4932 adapter->stats.roc += er32(ROC);
4933
4934 adapter->stats.mpc += er32(MPC);
4935
4936
4937 if (adapter->link_duplex == HALF_DUPLEX) {
4938 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4939 e1000e_update_phy_stats(adapter);
4940 } else {
4941 adapter->stats.scc += er32(SCC);
4942 adapter->stats.ecol += er32(ECOL);
4943 adapter->stats.mcc += er32(MCC);
4944 adapter->stats.latecol += er32(LATECOL);
4945 adapter->stats.dc += er32(DC);
4946
4947 hw->mac.collision_delta = er32(COLC);
4948
4949 if ((hw->mac.type != e1000_82574) &&
4950 (hw->mac.type != e1000_82583))
4951 adapter->stats.tncrs += er32(TNCRS);
4952 }
4953 adapter->stats.colc += hw->mac.collision_delta;
4954 }
4955
4956 adapter->stats.xonrxc += er32(XONRXC);
4957 adapter->stats.xontxc += er32(XONTXC);
4958 adapter->stats.xoffrxc += er32(XOFFRXC);
4959 adapter->stats.xofftxc += er32(XOFFTXC);
4960 adapter->stats.gptc += er32(GPTC);
4961 adapter->stats.gotc += er32(GOTCL);
4962 er32(GOTCH);
4963 adapter->stats.rnbc += er32(RNBC);
4964 adapter->stats.ruc += er32(RUC);
4965
4966 adapter->stats.mptc += er32(MPTC);
4967 adapter->stats.bptc += er32(BPTC);
4968
4969
4970
4971 hw->mac.tx_packet_delta = er32(TPT);
4972 adapter->stats.tpt += hw->mac.tx_packet_delta;
4973
4974 adapter->stats.algnerrc += er32(ALGNERRC);
4975 adapter->stats.rxerrc += er32(RXERRC);
4976 adapter->stats.cexterr += er32(CEXTERR);
4977 adapter->stats.tsctc += er32(TSCTC);
4978 adapter->stats.tsctfc += er32(TSCTFC);
4979
4980
4981 netdev->stats.multicast = adapter->stats.mprc;
4982 netdev->stats.collisions = adapter->stats.colc;
4983
4984
4985
4986
4987
4988
4989 netdev->stats.rx_errors = adapter->stats.rxerrc +
4990 adapter->stats.crcerrs + adapter->stats.algnerrc +
4991 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
4992 netdev->stats.rx_length_errors = adapter->stats.ruc +
4993 adapter->stats.roc;
4994 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4995 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4996 netdev->stats.rx_missed_errors = adapter->stats.mpc;
4997
4998
4999 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5000 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5001 netdev->stats.tx_window_errors = adapter->stats.latecol;
5002 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5003
5004
5005
5006
5007 adapter->stats.mgptc += er32(MGTPTC);
5008 adapter->stats.mgprc += er32(MGTPRC);
5009 adapter->stats.mgpdc += er32(MGTPDC);
5010
5011
5012 if (hw->mac.type >= e1000_pch_lpt) {
5013 u32 pbeccsts = er32(PBECCSTS);
5014
5015 adapter->corr_errors +=
5016 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5017 adapter->uncorr_errors +=
5018 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
5019 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
5020 }
5021 }
5022
5023
5024
5025
5026
5027 static void e1000_phy_read_status(struct e1000_adapter *adapter)
5028 {
5029 struct e1000_hw *hw = &adapter->hw;
5030 struct e1000_phy_regs *phy = &adapter->phy_regs;
5031
5032 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5033 (er32(STATUS) & E1000_STATUS_LU) &&
5034 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5035 int ret_val;
5036
5037 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5038 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5039 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5040 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5041 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5042 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5043 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5044 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5045 if (ret_val)
5046 e_warn("Error reading PHY register\n");
5047 } else {
5048
5049
5050
5051 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5052 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5053 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5054 BMSR_ERCAP);
5055 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5056 ADVERTISE_ALL | ADVERTISE_CSMA);
5057 phy->lpa = 0;
5058 phy->expansion = EXPANSION_ENABLENPAGE;
5059 phy->ctrl1000 = ADVERTISE_1000FULL;
5060 phy->stat1000 = 0;
5061 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5062 }
5063 }
5064
5065 static void e1000_print_link_info(struct e1000_adapter *adapter)
5066 {
5067 struct e1000_hw *hw = &adapter->hw;
5068 u32 ctrl = er32(CTRL);
5069
5070
5071 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5072 adapter->netdev->name, adapter->link_speed,
5073 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5074 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5075 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5076 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5077 }
5078
5079 static bool e1000e_has_link(struct e1000_adapter *adapter)
5080 {
5081 struct e1000_hw *hw = &adapter->hw;
5082 bool link_active = false;
5083 s32 ret_val = 0;
5084
5085
5086
5087
5088
5089
5090 switch (hw->phy.media_type) {
5091 case e1000_media_type_copper:
5092 if (hw->mac.get_link_status) {
5093 ret_val = hw->mac.ops.check_for_link(hw);
5094 link_active = !hw->mac.get_link_status;
5095 } else {
5096 link_active = true;
5097 }
5098 break;
5099 case e1000_media_type_fiber:
5100 ret_val = hw->mac.ops.check_for_link(hw);
5101 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5102 break;
5103 case e1000_media_type_internal_serdes:
5104 ret_val = hw->mac.ops.check_for_link(hw);
5105 link_active = hw->mac.serdes_has_link;
5106 break;
5107 default:
5108 case e1000_media_type_unknown:
5109 break;
5110 }
5111
5112 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5113 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5114
5115 e_info("Gigabit has been disabled, downgrading speed\n");
5116 }
5117
5118 return link_active;
5119 }
5120
5121 static void e1000e_enable_receives(struct e1000_adapter *adapter)
5122 {
5123
5124 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5125 (adapter->flags & FLAG_RESTART_NOW)) {
5126 struct e1000_hw *hw = &adapter->hw;
5127 u32 rctl = er32(RCTL);
5128
5129 ew32(RCTL, rctl | E1000_RCTL_EN);
5130 adapter->flags &= ~FLAG_RESTART_NOW;
5131 }
5132 }
5133
5134 static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5135 {
5136 struct e1000_hw *hw = &adapter->hw;
5137
5138
5139
5140
5141 if (e1000_check_phy_82574(hw))
5142 adapter->phy_hang_count++;
5143 else
5144 adapter->phy_hang_count = 0;
5145
5146 if (adapter->phy_hang_count > 1) {
5147 adapter->phy_hang_count = 0;
5148 e_dbg("PHY appears hung - resetting\n");
5149 schedule_work(&adapter->reset_task);
5150 }
5151 }
5152
5153
5154
5155
5156
5157 static void e1000_watchdog(struct timer_list *t)
5158 {
5159 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5160
5161
5162 schedule_work(&adapter->watchdog_task);
5163
5164
5165 }
5166
5167 static void e1000_watchdog_task(struct work_struct *work)
5168 {
5169 struct e1000_adapter *adapter = container_of(work,
5170 struct e1000_adapter,
5171 watchdog_task);
5172 struct net_device *netdev = adapter->netdev;
5173 struct e1000_mac_info *mac = &adapter->hw.mac;
5174 struct e1000_phy_info *phy = &adapter->hw.phy;
5175 struct e1000_ring *tx_ring = adapter->tx_ring;
5176 u32 dmoff_exit_timeout = 100, tries = 0;
5177 struct e1000_hw *hw = &adapter->hw;
5178 u32 link, tctl, pcim_state;
5179
5180 if (test_bit(__E1000_DOWN, &adapter->state))
5181 return;
5182
5183 link = e1000e_has_link(adapter);
5184 if ((netif_carrier_ok(netdev)) && link) {
5185
5186 pm_runtime_resume(netdev->dev.parent);
5187
5188 e1000e_enable_receives(adapter);
5189 goto link_up;
5190 }
5191
5192 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5193 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5194 e1000_update_mng_vlan(adapter);
5195
5196 if (link) {
5197 if (!netif_carrier_ok(netdev)) {
5198 bool txb2b = true;
5199
5200
5201 pm_runtime_resume(netdev->dev.parent);
5202
5203
5204 pcim_state = er32(STATUS);
5205 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5206 if (tries++ == dmoff_exit_timeout) {
5207 e_dbg("Error in exiting dmoff\n");
5208 break;
5209 }
5210 usleep_range(10000, 20000);
5211 pcim_state = er32(STATUS);
5212
5213
5214 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5215 e1000_phy_hw_reset(&adapter->hw);
5216 }
5217
5218
5219 e1000_phy_read_status(adapter);
5220 mac->ops.get_link_up_info(&adapter->hw,
5221 &adapter->link_speed,
5222 &adapter->link_duplex);
5223 e1000_print_link_info(adapter);
5224
5225
5226 e1000e_check_downshift(hw);
5227 if (phy->speed_downgraded)
5228 netdev_warn(netdev,
5229 "Link Speed was downgraded by SmartSpeed\n");
5230
5231
5232
5233
5234 if ((hw->phy.type == e1000_phy_igp_3 ||
5235 hw->phy.type == e1000_phy_bm) &&
5236 hw->mac.autoneg &&
5237 (adapter->link_speed == SPEED_10 ||
5238 adapter->link_speed == SPEED_100) &&
5239 (adapter->link_duplex == HALF_DUPLEX)) {
5240 u16 autoneg_exp;
5241
5242 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5243
5244 if (!(autoneg_exp & EXPANSION_NWAY))
5245 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5246 }
5247
5248
5249 adapter->tx_timeout_factor = 1;
5250 switch (adapter->link_speed) {
5251 case SPEED_10:
5252 txb2b = false;
5253 adapter->tx_timeout_factor = 16;
5254 break;
5255 case SPEED_100:
5256 txb2b = false;
5257 adapter->tx_timeout_factor = 10;
5258 break;
5259 }
5260
5261
5262
5263
5264 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5265 !txb2b) {
5266 u32 tarc0;
5267
5268 tarc0 = er32(TARC(0));
5269 tarc0 &= ~SPEED_MODE_BIT;
5270 ew32(TARC(0), tarc0);
5271 }
5272
5273
5274
5275
5276 if (!(adapter->flags & FLAG_TSO_FORCE)) {
5277 switch (adapter->link_speed) {
5278 case SPEED_10:
5279 case SPEED_100:
5280 e_info("10/100 speed: disabling TSO\n");
5281 netdev->features &= ~NETIF_F_TSO;
5282 netdev->features &= ~NETIF_F_TSO6;
5283 break;
5284 case SPEED_1000:
5285 netdev->features |= NETIF_F_TSO;
5286 netdev->features |= NETIF_F_TSO6;
5287 break;
5288 default:
5289
5290 break;
5291 }
5292 }
5293
5294
5295
5296
5297 tctl = er32(TCTL);
5298 tctl |= E1000_TCTL_EN;
5299 ew32(TCTL, tctl);
5300
5301
5302
5303
5304 if (phy->ops.cfg_on_link_up)
5305 phy->ops.cfg_on_link_up(hw);
5306
5307 netif_wake_queue(netdev);
5308 netif_carrier_on(netdev);
5309
5310 if (!test_bit(__E1000_DOWN, &adapter->state))
5311 mod_timer(&adapter->phy_info_timer,
5312 round_jiffies(jiffies + 2 * HZ));
5313 }
5314 } else {
5315 if (netif_carrier_ok(netdev)) {
5316 adapter->link_speed = 0;
5317 adapter->link_duplex = 0;
5318
5319 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
5320 netif_carrier_off(netdev);
5321 netif_stop_queue(netdev);
5322 if (!test_bit(__E1000_DOWN, &adapter->state))
5323 mod_timer(&adapter->phy_info_timer,
5324 round_jiffies(jiffies + 2 * HZ));
5325
5326
5327
5328
5329
5330 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5331 adapter->flags |= FLAG_RESTART_NOW;
5332 else
5333 pm_schedule_suspend(netdev->dev.parent,
5334 LINK_TIMEOUT);
5335 }
5336 }
5337
5338 link_up:
5339 spin_lock(&adapter->stats64_lock);
5340 e1000e_update_stats(adapter);
5341
5342 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5343 adapter->tpt_old = adapter->stats.tpt;
5344 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5345 adapter->colc_old = adapter->stats.colc;
5346
5347 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5348 adapter->gorc_old = adapter->stats.gorc;
5349 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5350 adapter->gotc_old = adapter->stats.gotc;
5351 spin_unlock(&adapter->stats64_lock);
5352
5353
5354
5355
5356
5357 if (!netif_carrier_ok(netdev) &&
5358 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5359 adapter->flags |= FLAG_RESTART_NOW;
5360
5361
5362 if (adapter->flags & FLAG_RESTART_NOW) {
5363 schedule_work(&adapter->reset_task);
5364
5365 return;
5366 }
5367
5368 e1000e_update_adaptive(&adapter->hw);
5369
5370
5371 if (adapter->itr_setting == 4) {
5372
5373
5374
5375
5376 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5377 u32 dif = (adapter->gotc > adapter->gorc ?
5378 adapter->gotc - adapter->gorc :
5379 adapter->gorc - adapter->gotc) / 10000;
5380 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5381
5382 e1000e_write_itr(adapter, itr);
5383 }
5384
5385
5386 if (adapter->msix_entries)
5387 ew32(ICS, adapter->rx_ring->ims_val);
5388 else
5389 ew32(ICS, E1000_ICS_RXDMT0);
5390
5391
5392 e1000e_flush_descriptors(adapter);
5393
5394
5395 adapter->detect_tx_hung = true;
5396
5397
5398
5399
5400 if (e1000e_get_laa_state_82571(hw))
5401 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5402
5403 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5404 e1000e_check_82574_phy_workaround(adapter);
5405
5406
5407 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5408 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5409 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5410 er32(RXSTMPH);
5411 adapter->rx_hwtstamp_cleared++;
5412 } else {
5413 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5414 }
5415 }
5416
5417
5418 if (!test_bit(__E1000_DOWN, &adapter->state))
5419 mod_timer(&adapter->watchdog_timer,
5420 round_jiffies(jiffies + 2 * HZ));
5421 }
5422
5423 #define E1000_TX_FLAGS_CSUM 0x00000001
5424 #define E1000_TX_FLAGS_VLAN 0x00000002
5425 #define E1000_TX_FLAGS_TSO 0x00000004
5426 #define E1000_TX_FLAGS_IPV4 0x00000008
5427 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5428 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5429 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5430 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5431
5432 static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5433 __be16 protocol)
5434 {
5435 struct e1000_context_desc *context_desc;
5436 struct e1000_buffer *buffer_info;
5437 unsigned int i;
5438 u32 cmd_length = 0;
5439 u16 ipcse = 0, mss;
5440 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5441 int err;
5442
5443 if (!skb_is_gso(skb))
5444 return 0;
5445
5446 err = skb_cow_head(skb, 0);
5447 if (err < 0)
5448 return err;
5449
5450 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5451 mss = skb_shinfo(skb)->gso_size;
5452 if (protocol == htons(ETH_P_IP)) {
5453 struct iphdr *iph = ip_hdr(skb);
5454 iph->tot_len = 0;
5455 iph->check = 0;
5456 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5457 0, IPPROTO_TCP, 0);
5458 cmd_length = E1000_TXD_CMD_IP;
5459 ipcse = skb_transport_offset(skb) - 1;
5460 } else if (skb_is_gso_v6(skb)) {
5461 ipv6_hdr(skb)->payload_len = 0;
5462 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5463 &ipv6_hdr(skb)->daddr,
5464 0, IPPROTO_TCP, 0);
5465 ipcse = 0;
5466 }
5467 ipcss = skb_network_offset(skb);
5468 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5469 tucss = skb_transport_offset(skb);
5470 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5471
5472 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5473 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5474
5475 i = tx_ring->next_to_use;
5476 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5477 buffer_info = &tx_ring->buffer_info[i];
5478
5479 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5480 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5481 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5482 context_desc->upper_setup.tcp_fields.tucss = tucss;
5483 context_desc->upper_setup.tcp_fields.tucso = tucso;
5484 context_desc->upper_setup.tcp_fields.tucse = 0;
5485 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5486 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5487 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5488
5489 buffer_info->time_stamp = jiffies;
5490 buffer_info->next_to_watch = i;
5491
5492 i++;
5493 if (i == tx_ring->count)
5494 i = 0;
5495 tx_ring->next_to_use = i;
5496
5497 return 1;
5498 }
5499
5500 static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5501 __be16 protocol)
5502 {
5503 struct e1000_adapter *adapter = tx_ring->adapter;
5504 struct e1000_context_desc *context_desc;
5505 struct e1000_buffer *buffer_info;
5506 unsigned int i;
5507 u8 css;
5508 u32 cmd_len = E1000_TXD_CMD_DEXT;
5509
5510 if (skb->ip_summed != CHECKSUM_PARTIAL)
5511 return false;
5512
5513 switch (protocol) {
5514 case cpu_to_be16(ETH_P_IP):
5515 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5516 cmd_len |= E1000_TXD_CMD_TCP;
5517 break;
5518 case cpu_to_be16(ETH_P_IPV6):
5519
5520 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5521 cmd_len |= E1000_TXD_CMD_TCP;
5522 break;
5523 default:
5524 if (unlikely(net_ratelimit()))
5525 e_warn("checksum_partial proto=%x!\n",
5526 be16_to_cpu(protocol));
5527 break;
5528 }
5529
5530 css = skb_checksum_start_offset(skb);
5531
5532 i = tx_ring->next_to_use;
5533 buffer_info = &tx_ring->buffer_info[i];
5534 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5535
5536 context_desc->lower_setup.ip_config = 0;
5537 context_desc->upper_setup.tcp_fields.tucss = css;
5538 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5539 context_desc->upper_setup.tcp_fields.tucse = 0;
5540 context_desc->tcp_seg_setup.data = 0;
5541 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5542
5543 buffer_info->time_stamp = jiffies;
5544 buffer_info->next_to_watch = i;
5545
5546 i++;
5547 if (i == tx_ring->count)
5548 i = 0;
5549 tx_ring->next_to_use = i;
5550
5551 return true;
5552 }
5553
5554 static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5555 unsigned int first, unsigned int max_per_txd,
5556 unsigned int nr_frags)
5557 {
5558 struct e1000_adapter *adapter = tx_ring->adapter;
5559 struct pci_dev *pdev = adapter->pdev;
5560 struct e1000_buffer *buffer_info;
5561 unsigned int len = skb_headlen(skb);
5562 unsigned int offset = 0, size, count = 0, i;
5563 unsigned int f, bytecount, segs;
5564
5565 i = tx_ring->next_to_use;
5566
5567 while (len) {
5568 buffer_info = &tx_ring->buffer_info[i];
5569 size = min(len, max_per_txd);
5570
5571 buffer_info->length = size;
5572 buffer_info->time_stamp = jiffies;
5573 buffer_info->next_to_watch = i;
5574 buffer_info->dma = dma_map_single(&pdev->dev,
5575 skb->data + offset,
5576 size, DMA_TO_DEVICE);
5577 buffer_info->mapped_as_page = false;
5578 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5579 goto dma_error;
5580
5581 len -= size;
5582 offset += size;
5583 count++;
5584
5585 if (len) {
5586 i++;
5587 if (i == tx_ring->count)
5588 i = 0;
5589 }
5590 }
5591
5592 for (f = 0; f < nr_frags; f++) {
5593 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
5594
5595 len = skb_frag_size(frag);
5596 offset = 0;
5597
5598 while (len) {
5599 i++;
5600 if (i == tx_ring->count)
5601 i = 0;
5602
5603 buffer_info = &tx_ring->buffer_info[i];
5604 size = min(len, max_per_txd);
5605
5606 buffer_info->length = size;
5607 buffer_info->time_stamp = jiffies;
5608 buffer_info->next_to_watch = i;
5609 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5610 offset, size,
5611 DMA_TO_DEVICE);
5612 buffer_info->mapped_as_page = true;
5613 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5614 goto dma_error;
5615
5616 len -= size;
5617 offset += size;
5618 count++;
5619 }
5620 }
5621
5622 segs = skb_shinfo(skb)->gso_segs ? : 1;
5623
5624 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5625
5626 tx_ring->buffer_info[i].skb = skb;
5627 tx_ring->buffer_info[i].segs = segs;
5628 tx_ring->buffer_info[i].bytecount = bytecount;
5629 tx_ring->buffer_info[first].next_to_watch = i;
5630
5631 return count;
5632
5633 dma_error:
5634 dev_err(&pdev->dev, "Tx DMA map failed\n");
5635 buffer_info->dma = 0;
5636 if (count)
5637 count--;
5638
5639 while (count--) {
5640 if (i == 0)
5641 i += tx_ring->count;
5642 i--;
5643 buffer_info = &tx_ring->buffer_info[i];
5644 e1000_put_txbuf(tx_ring, buffer_info, true);
5645 }
5646
5647 return 0;
5648 }
5649
5650 static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5651 {
5652 struct e1000_adapter *adapter = tx_ring->adapter;
5653 struct e1000_tx_desc *tx_desc = NULL;
5654 struct e1000_buffer *buffer_info;
5655 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5656 unsigned int i;
5657
5658 if (tx_flags & E1000_TX_FLAGS_TSO) {
5659 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5660 E1000_TXD_CMD_TSE;
5661 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5662
5663 if (tx_flags & E1000_TX_FLAGS_IPV4)
5664 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5665 }
5666
5667 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5668 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5669 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5670 }
5671
5672 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5673 txd_lower |= E1000_TXD_CMD_VLE;
5674 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5675 }
5676
5677 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5678 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5679
5680 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5681 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5682 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5683 }
5684
5685 i = tx_ring->next_to_use;
5686
5687 do {
5688 buffer_info = &tx_ring->buffer_info[i];
5689 tx_desc = E1000_TX_DESC(*tx_ring, i);
5690 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5691 tx_desc->lower.data = cpu_to_le32(txd_lower |
5692 buffer_info->length);
5693 tx_desc->upper.data = cpu_to_le32(txd_upper);
5694
5695 i++;
5696 if (i == tx_ring->count)
5697 i = 0;
5698 } while (--count > 0);
5699
5700 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5701
5702
5703 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5704 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5705
5706
5707
5708
5709
5710
5711 wmb();
5712
5713 tx_ring->next_to_use = i;
5714 }
5715
5716 #define MINIMUM_DHCP_PACKET_SIZE 282
5717 static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5718 struct sk_buff *skb)
5719 {
5720 struct e1000_hw *hw = &adapter->hw;
5721 u16 length, offset;
5722
5723 if (skb_vlan_tag_present(skb) &&
5724 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5725 (adapter->hw.mng_cookie.status &
5726 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5727 return 0;
5728
5729 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5730 return 0;
5731
5732 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5733 return 0;
5734
5735 {
5736 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5737 struct udphdr *udp;
5738
5739 if (ip->protocol != IPPROTO_UDP)
5740 return 0;
5741
5742 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5743 if (ntohs(udp->dest) != 67)
5744 return 0;
5745
5746 offset = (u8 *)udp + 8 - skb->data;
5747 length = skb->len - offset;
5748 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5749 }
5750
5751 return 0;
5752 }
5753
5754 static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5755 {
5756 struct e1000_adapter *adapter = tx_ring->adapter;
5757
5758 netif_stop_queue(adapter->netdev);
5759
5760
5761
5762
5763 smp_mb();
5764
5765
5766
5767
5768 if (e1000_desc_unused(tx_ring) < size)
5769 return -EBUSY;
5770
5771
5772 netif_start_queue(adapter->netdev);
5773 ++adapter->restart_queue;
5774 return 0;
5775 }
5776
5777 static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5778 {
5779 BUG_ON(size > tx_ring->count);
5780
5781 if (e1000_desc_unused(tx_ring) >= size)
5782 return 0;
5783 return __e1000_maybe_stop_tx(tx_ring, size);
5784 }
5785
5786 static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5787 struct net_device *netdev)
5788 {
5789 struct e1000_adapter *adapter = netdev_priv(netdev);
5790 struct e1000_ring *tx_ring = adapter->tx_ring;
5791 unsigned int first;
5792 unsigned int tx_flags = 0;
5793 unsigned int len = skb_headlen(skb);
5794 unsigned int nr_frags;
5795 unsigned int mss;
5796 int count = 0;
5797 int tso;
5798 unsigned int f;
5799 __be16 protocol = vlan_get_protocol(skb);
5800
5801 if (test_bit(__E1000_DOWN, &adapter->state)) {
5802 dev_kfree_skb_any(skb);
5803 return NETDEV_TX_OK;
5804 }
5805
5806 if (skb->len <= 0) {
5807 dev_kfree_skb_any(skb);
5808 return NETDEV_TX_OK;
5809 }
5810
5811
5812
5813
5814 if (skb_put_padto(skb, 17))
5815 return NETDEV_TX_OK;
5816
5817 mss = skb_shinfo(skb)->gso_size;
5818 if (mss) {
5819 u8 hdr_len;
5820
5821
5822
5823
5824
5825 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5826
5827
5828
5829 if (skb->data_len && (hdr_len == len)) {
5830 unsigned int pull_size;
5831
5832 pull_size = min_t(unsigned int, 4, skb->data_len);
5833 if (!__pskb_pull_tail(skb, pull_size)) {
5834 e_err("__pskb_pull_tail failed.\n");
5835 dev_kfree_skb_any(skb);
5836 return NETDEV_TX_OK;
5837 }
5838 len = skb_headlen(skb);
5839 }
5840 }
5841
5842
5843 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5844 count++;
5845 count++;
5846
5847 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5848
5849 nr_frags = skb_shinfo(skb)->nr_frags;
5850 for (f = 0; f < nr_frags; f++)
5851 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5852 adapter->tx_fifo_limit);
5853
5854 if (adapter->hw.mac.tx_pkt_filtering)
5855 e1000_transfer_dhcp_info(adapter, skb);
5856
5857
5858
5859
5860 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5861 return NETDEV_TX_BUSY;
5862
5863 if (skb_vlan_tag_present(skb)) {
5864 tx_flags |= E1000_TX_FLAGS_VLAN;
5865 tx_flags |= (skb_vlan_tag_get(skb) <<
5866 E1000_TX_FLAGS_VLAN_SHIFT);
5867 }
5868
5869 first = tx_ring->next_to_use;
5870
5871 tso = e1000_tso(tx_ring, skb, protocol);
5872 if (tso < 0) {
5873 dev_kfree_skb_any(skb);
5874 return NETDEV_TX_OK;
5875 }
5876
5877 if (tso)
5878 tx_flags |= E1000_TX_FLAGS_TSO;
5879 else if (e1000_tx_csum(tx_ring, skb, protocol))
5880 tx_flags |= E1000_TX_FLAGS_CSUM;
5881
5882
5883
5884
5885
5886 if (protocol == htons(ETH_P_IP))
5887 tx_flags |= E1000_TX_FLAGS_IPV4;
5888
5889 if (unlikely(skb->no_fcs))
5890 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5891
5892
5893 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5894 nr_frags);
5895 if (count) {
5896 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5897 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5898 if (!adapter->tx_hwtstamp_skb) {
5899 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5900 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5901 adapter->tx_hwtstamp_skb = skb_get(skb);
5902 adapter->tx_hwtstamp_start = jiffies;
5903 schedule_work(&adapter->tx_hwtstamp_work);
5904 } else {
5905 adapter->tx_hwtstamp_skipped++;
5906 }
5907 }
5908
5909 skb_tx_timestamp(skb);
5910
5911 netdev_sent_queue(netdev, skb->len);
5912 e1000_tx_queue(tx_ring, tx_flags, count);
5913
5914 e1000_maybe_stop_tx(tx_ring,
5915 (MAX_SKB_FRAGS *
5916 DIV_ROUND_UP(PAGE_SIZE,
5917 adapter->tx_fifo_limit) + 2));
5918
5919 if (!netdev_xmit_more() ||
5920 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5921 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5922 e1000e_update_tdt_wa(tx_ring,
5923 tx_ring->next_to_use);
5924 else
5925 writel(tx_ring->next_to_use, tx_ring->tail);
5926 }
5927 } else {
5928 dev_kfree_skb_any(skb);
5929 tx_ring->buffer_info[first].time_stamp = 0;
5930 tx_ring->next_to_use = first;
5931 }
5932
5933 return NETDEV_TX_OK;
5934 }
5935
5936
5937
5938
5939
5940 static void e1000_tx_timeout(struct net_device *netdev)
5941 {
5942 struct e1000_adapter *adapter = netdev_priv(netdev);
5943
5944
5945 adapter->tx_timeout_count++;
5946 schedule_work(&adapter->reset_task);
5947 }
5948
5949 static void e1000_reset_task(struct work_struct *work)
5950 {
5951 struct e1000_adapter *adapter;
5952 adapter = container_of(work, struct e1000_adapter, reset_task);
5953
5954
5955 if (test_bit(__E1000_DOWN, &adapter->state))
5956 return;
5957
5958 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5959 e1000e_dump(adapter);
5960 e_err("Reset adapter unexpectedly\n");
5961 }
5962 e1000e_reinit_locked(adapter);
5963 }
5964
5965
5966
5967
5968
5969
5970
5971
5972 void e1000e_get_stats64(struct net_device *netdev,
5973 struct rtnl_link_stats64 *stats)
5974 {
5975 struct e1000_adapter *adapter = netdev_priv(netdev);
5976
5977 spin_lock(&adapter->stats64_lock);
5978 e1000e_update_stats(adapter);
5979
5980 stats->rx_bytes = adapter->stats.gorc;
5981 stats->rx_packets = adapter->stats.gprc;
5982 stats->tx_bytes = adapter->stats.gotc;
5983 stats->tx_packets = adapter->stats.gptc;
5984 stats->multicast = adapter->stats.mprc;
5985 stats->collisions = adapter->stats.colc;
5986
5987
5988
5989
5990
5991
5992 stats->rx_errors = adapter->stats.rxerrc +
5993 adapter->stats.crcerrs + adapter->stats.algnerrc +
5994 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5995 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
5996 stats->rx_crc_errors = adapter->stats.crcerrs;
5997 stats->rx_frame_errors = adapter->stats.algnerrc;
5998 stats->rx_missed_errors = adapter->stats.mpc;
5999
6000
6001 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
6002 stats->tx_aborted_errors = adapter->stats.ecol;
6003 stats->tx_window_errors = adapter->stats.latecol;
6004 stats->tx_carrier_errors = adapter->stats.tncrs;
6005
6006
6007
6008 spin_unlock(&adapter->stats64_lock);
6009 }
6010
6011
6012
6013
6014
6015
6016
6017
6018 static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6019 {
6020 struct e1000_adapter *adapter = netdev_priv(netdev);
6021 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6022
6023
6024 if ((new_mtu > ETH_DATA_LEN) &&
6025 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6026 e_err("Jumbo Frames not supported.\n");
6027 return -EINVAL;
6028 }
6029
6030
6031 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6032 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6033 (new_mtu > ETH_DATA_LEN)) {
6034 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6035 return -EINVAL;
6036 }
6037
6038 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
6039 usleep_range(1000, 1100);
6040
6041 adapter->max_frame_size = max_frame;
6042 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
6043 netdev->mtu = new_mtu;
6044
6045 pm_runtime_get_sync(netdev->dev.parent);
6046
6047 if (netif_running(netdev))
6048 e1000e_down(adapter, true);
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058 if (max_frame <= 2048)
6059 adapter->rx_buffer_len = 2048;
6060 else
6061 adapter->rx_buffer_len = 4096;
6062
6063
6064 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6065 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6066
6067 if (netif_running(netdev))
6068 e1000e_up(adapter);
6069 else
6070 e1000e_reset(adapter);
6071
6072 pm_runtime_put_sync(netdev->dev.parent);
6073
6074 clear_bit(__E1000_RESETTING, &adapter->state);
6075
6076 return 0;
6077 }
6078
6079 static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6080 int cmd)
6081 {
6082 struct e1000_adapter *adapter = netdev_priv(netdev);
6083 struct mii_ioctl_data *data = if_mii(ifr);
6084
6085 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6086 return -EOPNOTSUPP;
6087
6088 switch (cmd) {
6089 case SIOCGMIIPHY:
6090 data->phy_id = adapter->hw.phy.addr;
6091 break;
6092 case SIOCGMIIREG:
6093 e1000_phy_read_status(adapter);
6094
6095 switch (data->reg_num & 0x1F) {
6096 case MII_BMCR:
6097 data->val_out = adapter->phy_regs.bmcr;
6098 break;
6099 case MII_BMSR:
6100 data->val_out = adapter->phy_regs.bmsr;
6101 break;
6102 case MII_PHYSID1:
6103 data->val_out = (adapter->hw.phy.id >> 16);
6104 break;
6105 case MII_PHYSID2:
6106 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6107 break;
6108 case MII_ADVERTISE:
6109 data->val_out = adapter->phy_regs.advertise;
6110 break;
6111 case MII_LPA:
6112 data->val_out = adapter->phy_regs.lpa;
6113 break;
6114 case MII_EXPANSION:
6115 data->val_out = adapter->phy_regs.expansion;
6116 break;
6117 case MII_CTRL1000:
6118 data->val_out = adapter->phy_regs.ctrl1000;
6119 break;
6120 case MII_STAT1000:
6121 data->val_out = adapter->phy_regs.stat1000;
6122 break;
6123 case MII_ESTATUS:
6124 data->val_out = adapter->phy_regs.estatus;
6125 break;
6126 default:
6127 return -EIO;
6128 }
6129 break;
6130 case SIOCSMIIREG:
6131 default:
6132 return -EOPNOTSUPP;
6133 }
6134 return 0;
6135 }
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146
6147
6148
6149
6150
6151
6152
6153 static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6154 {
6155 struct e1000_adapter *adapter = netdev_priv(netdev);
6156 struct hwtstamp_config config;
6157 int ret_val;
6158
6159 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6160 return -EFAULT;
6161
6162 ret_val = e1000e_config_hwtstamp(adapter, &config);
6163 if (ret_val)
6164 return ret_val;
6165
6166 switch (config.rx_filter) {
6167 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6168 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6169 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6170 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6171 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6172 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6173
6174
6175
6176
6177
6178 config.rx_filter = HWTSTAMP_FILTER_SOME;
6179 break;
6180 default:
6181 break;
6182 }
6183
6184 return copy_to_user(ifr->ifr_data, &config,
6185 sizeof(config)) ? -EFAULT : 0;
6186 }
6187
6188 static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6189 {
6190 struct e1000_adapter *adapter = netdev_priv(netdev);
6191
6192 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6193 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6194 }
6195
6196 static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6197 {
6198 switch (cmd) {
6199 case SIOCGMIIPHY:
6200 case SIOCGMIIREG:
6201 case SIOCSMIIREG:
6202 return e1000_mii_ioctl(netdev, ifr, cmd);
6203 case SIOCSHWTSTAMP:
6204 return e1000e_hwtstamp_set(netdev, ifr);
6205 case SIOCGHWTSTAMP:
6206 return e1000e_hwtstamp_get(netdev, ifr);
6207 default:
6208 return -EOPNOTSUPP;
6209 }
6210 }
6211
6212 static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6213 {
6214 struct e1000_hw *hw = &adapter->hw;
6215 u32 i, mac_reg, wuc;
6216 u16 phy_reg, wuc_enable;
6217 int retval;
6218
6219
6220 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6221
6222 retval = hw->phy.ops.acquire(hw);
6223 if (retval) {
6224 e_err("Could not acquire PHY\n");
6225 return retval;
6226 }
6227
6228
6229 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6230 if (retval)
6231 goto release;
6232
6233
6234 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6235 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6236 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6237 (u16)(mac_reg & 0xFFFF));
6238 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6239 (u16)((mac_reg >> 16) & 0xFFFF));
6240 }
6241
6242
6243 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6244 mac_reg = er32(RCTL);
6245 if (mac_reg & E1000_RCTL_UPE)
6246 phy_reg |= BM_RCTL_UPE;
6247 if (mac_reg & E1000_RCTL_MPE)
6248 phy_reg |= BM_RCTL_MPE;
6249 phy_reg &= ~(BM_RCTL_MO_MASK);
6250 if (mac_reg & E1000_RCTL_MO_3)
6251 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
6252 << BM_RCTL_MO_SHIFT);
6253 if (mac_reg & E1000_RCTL_BAM)
6254 phy_reg |= BM_RCTL_BAM;
6255 if (mac_reg & E1000_RCTL_PMCF)
6256 phy_reg |= BM_RCTL_PMCF;
6257 mac_reg = er32(CTRL);
6258 if (mac_reg & E1000_CTRL_RFCE)
6259 phy_reg |= BM_RCTL_RFCE;
6260 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6261
6262 wuc = E1000_WUC_PME_EN;
6263 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6264 wuc |= E1000_WUC_APME;
6265
6266
6267 ew32(WUFC, wufc);
6268 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6269 E1000_WUC_PME_STATUS | wuc));
6270
6271
6272 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6273 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6274
6275
6276 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6277 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6278 if (retval)
6279 e_err("Could not set PHY Host Wakeup bit\n");
6280 release:
6281 hw->phy.ops.release(hw);
6282
6283 return retval;
6284 }
6285
6286 static void e1000e_flush_lpic(struct pci_dev *pdev)
6287 {
6288 struct net_device *netdev = pci_get_drvdata(pdev);
6289 struct e1000_adapter *adapter = netdev_priv(netdev);
6290 struct e1000_hw *hw = &adapter->hw;
6291 u32 ret_val;
6292
6293 pm_runtime_get_sync(netdev->dev.parent);
6294
6295 ret_val = hw->phy.ops.acquire(hw);
6296 if (ret_val)
6297 goto fl_out;
6298
6299 pr_info("EEE TX LPI TIMER: %08X\n",
6300 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6301
6302 hw->phy.ops.release(hw);
6303
6304 fl_out:
6305 pm_runtime_put_sync(netdev->dev.parent);
6306 }
6307
6308 static int e1000e_pm_freeze(struct device *dev)
6309 {
6310 struct net_device *netdev = dev_get_drvdata(dev);
6311 struct e1000_adapter *adapter = netdev_priv(netdev);
6312 bool present;
6313
6314 rtnl_lock();
6315
6316 present = netif_device_present(netdev);
6317 netif_device_detach(netdev);
6318
6319 if (present && netif_running(netdev)) {
6320 int count = E1000_CHECK_RESET_COUNT;
6321
6322 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6323 usleep_range(10000, 11000);
6324
6325 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6326
6327
6328 e1000e_down(adapter, false);
6329 e1000_free_irq(adapter);
6330 }
6331 rtnl_unlock();
6332
6333 e1000e_reset_interrupt_capability(adapter);
6334
6335
6336 e1000e_disable_pcie_master(&adapter->hw);
6337
6338 return 0;
6339 }
6340
6341 static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6342 {
6343 struct net_device *netdev = pci_get_drvdata(pdev);
6344 struct e1000_adapter *adapter = netdev_priv(netdev);
6345 struct e1000_hw *hw = &adapter->hw;
6346 u32 ctrl, ctrl_ext, rctl, status;
6347
6348 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6349 int retval = 0;
6350
6351 status = er32(STATUS);
6352 if (status & E1000_STATUS_LU)
6353 wufc &= ~E1000_WUFC_LNKC;
6354
6355 if (wufc) {
6356 e1000_setup_rctl(adapter);
6357 e1000e_set_rx_mode(netdev);
6358
6359
6360 if (wufc & E1000_WUFC_MC) {
6361 rctl = er32(RCTL);
6362 rctl |= E1000_RCTL_MPE;
6363 ew32(RCTL, rctl);
6364 }
6365
6366 ctrl = er32(CTRL);
6367 ctrl |= E1000_CTRL_ADVD3WUC;
6368 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6369 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6370 ew32(CTRL, ctrl);
6371
6372 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6373 adapter->hw.phy.media_type ==
6374 e1000_media_type_internal_serdes) {
6375
6376 ctrl_ext = er32(CTRL_EXT);
6377 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6378 ew32(CTRL_EXT, ctrl_ext);
6379 }
6380
6381 if (!runtime)
6382 e1000e_power_up_phy(adapter);
6383
6384 if (adapter->flags & FLAG_IS_ICH)
6385 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6386
6387 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6388
6389 retval = e1000_init_phy_wakeup(adapter, wufc);
6390 if (retval)
6391 return retval;
6392 } else {
6393
6394 ew32(WUFC, wufc);
6395 ew32(WUC, E1000_WUC_PME_EN);
6396 }
6397 } else {
6398 ew32(WUC, 0);
6399 ew32(WUFC, 0);
6400
6401 e1000_power_down_phy(adapter);
6402 }
6403
6404 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6405 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6406 } else if (hw->mac.type >= e1000_pch_lpt) {
6407 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6408
6409
6410
6411 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6412
6413 if (retval)
6414 return retval;
6415 }
6416
6417
6418
6419
6420 if ((hw->phy.type >= e1000_phy_i217) &&
6421 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6422 u16 lpi_ctrl = 0;
6423
6424 retval = hw->phy.ops.acquire(hw);
6425 if (!retval) {
6426 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6427 &lpi_ctrl);
6428 if (!retval) {
6429 if (adapter->eee_advert &
6430 hw->dev_spec.ich8lan.eee_lp_ability &
6431 I82579_EEE_100_SUPPORTED)
6432 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6433 if (adapter->eee_advert &
6434 hw->dev_spec.ich8lan.eee_lp_ability &
6435 I82579_EEE_1000_SUPPORTED)
6436 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6437
6438 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6439 lpi_ctrl);
6440 }
6441 }
6442 hw->phy.ops.release(hw);
6443 }
6444
6445
6446
6447
6448 e1000e_release_hw_control(adapter);
6449
6450 pci_clear_master(pdev);
6451
6452
6453
6454
6455
6456
6457
6458
6459
6460
6461 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6462 struct pci_dev *us_dev = pdev->bus->self;
6463 u16 devctl;
6464
6465 if (!us_dev)
6466 return 0;
6467
6468 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6469 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6470 (devctl & ~PCI_EXP_DEVCTL_CERE));
6471
6472 pci_save_state(pdev);
6473 pci_prepare_to_sleep(pdev);
6474
6475 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6476 }
6477
6478 return 0;
6479 }
6480
6481
6482
6483
6484
6485
6486
6487
6488
6489 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6490 {
6491 struct pci_dev *parent = pdev->bus->self;
6492 u16 aspm_dis_mask = 0;
6493 u16 pdev_aspmc, parent_aspmc;
6494
6495 switch (state) {
6496 case PCIE_LINK_STATE_L0S:
6497 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6498 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6499
6500 case PCIE_LINK_STATE_L1:
6501 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6502 break;
6503 default:
6504 return;
6505 }
6506
6507 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6508 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6509
6510 if (parent) {
6511 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6512 &parent_aspmc);
6513 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6514 }
6515
6516
6517 if (!(pdev_aspmc & aspm_dis_mask) &&
6518 (!parent || !(parent_aspmc & aspm_dis_mask)))
6519 return;
6520
6521 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6522 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6523 "L0s" : "",
6524 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6525 "L1" : "");
6526
6527 #ifdef CONFIG_PCIEASPM
6528 if (locked)
6529 pci_disable_link_state_locked(pdev, state);
6530 else
6531 pci_disable_link_state(pdev, state);
6532
6533
6534
6535
6536
6537 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6538 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6539
6540 if (!(aspm_dis_mask & pdev_aspmc))
6541 return;
6542 #endif
6543
6544
6545
6546
6547 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6548
6549 if (parent)
6550 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6551 aspm_dis_mask);
6552 }
6553
6554
6555
6556
6557
6558
6559
6560
6561
6562 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6563 {
6564 __e1000e_disable_aspm(pdev, state, 0);
6565 }
6566
6567
6568
6569
6570
6571
6572
6573
6574
6575 static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6576 {
6577 __e1000e_disable_aspm(pdev, state, 1);
6578 }
6579
6580 static int e1000e_pm_thaw(struct device *dev)
6581 {
6582 struct net_device *netdev = dev_get_drvdata(dev);
6583 struct e1000_adapter *adapter = netdev_priv(netdev);
6584 int rc = 0;
6585
6586 e1000e_set_interrupt_capability(adapter);
6587
6588 rtnl_lock();
6589 if (netif_running(netdev)) {
6590 rc = e1000_request_irq(adapter);
6591 if (rc)
6592 goto err_irq;
6593
6594 e1000e_up(adapter);
6595 }
6596
6597 netif_device_attach(netdev);
6598 err_irq:
6599 rtnl_unlock();
6600
6601 return rc;
6602 }
6603
6604 #ifdef CONFIG_PM
6605 static int __e1000_resume(struct pci_dev *pdev)
6606 {
6607 struct net_device *netdev = pci_get_drvdata(pdev);
6608 struct e1000_adapter *adapter = netdev_priv(netdev);
6609 struct e1000_hw *hw = &adapter->hw;
6610 u16 aspm_disable_flag = 0;
6611
6612 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6613 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6614 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6615 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6616 if (aspm_disable_flag)
6617 e1000e_disable_aspm(pdev, aspm_disable_flag);
6618
6619 pci_set_master(pdev);
6620
6621 if (hw->mac.type >= e1000_pch2lan)
6622 e1000_resume_workarounds_pchlan(&adapter->hw);
6623
6624 e1000e_power_up_phy(adapter);
6625
6626
6627 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6628 u16 phy_data;
6629
6630 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6631 if (phy_data) {
6632 e_info("PHY Wakeup cause - %s\n",
6633 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6634 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6635 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6636 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6637 phy_data & E1000_WUS_LNKC ?
6638 "Link Status Change" : "other");
6639 }
6640 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6641 } else {
6642 u32 wus = er32(WUS);
6643
6644 if (wus) {
6645 e_info("MAC Wakeup cause - %s\n",
6646 wus & E1000_WUS_EX ? "Unicast Packet" :
6647 wus & E1000_WUS_MC ? "Multicast Packet" :
6648 wus & E1000_WUS_BC ? "Broadcast Packet" :
6649 wus & E1000_WUS_MAG ? "Magic Packet" :
6650 wus & E1000_WUS_LNKC ? "Link Status Change" :
6651 "other");
6652 }
6653 ew32(WUS, ~0);
6654 }
6655
6656 e1000e_reset(adapter);
6657
6658 e1000_init_manageability_pt(adapter);
6659
6660
6661
6662
6663
6664 if (!(adapter->flags & FLAG_HAS_AMT))
6665 e1000e_get_hw_control(adapter);
6666
6667 return 0;
6668 }
6669
6670 #ifdef CONFIG_PM_SLEEP
6671 static int e1000e_pm_suspend(struct device *dev)
6672 {
6673 struct pci_dev *pdev = to_pci_dev(dev);
6674 int rc;
6675
6676 e1000e_flush_lpic(pdev);
6677
6678 e1000e_pm_freeze(dev);
6679
6680 rc = __e1000_shutdown(pdev, false);
6681 if (rc)
6682 e1000e_pm_thaw(dev);
6683
6684 return rc;
6685 }
6686
6687 static int e1000e_pm_resume(struct device *dev)
6688 {
6689 struct pci_dev *pdev = to_pci_dev(dev);
6690 int rc;
6691
6692 rc = __e1000_resume(pdev);
6693 if (rc)
6694 return rc;
6695
6696 return e1000e_pm_thaw(dev);
6697 }
6698 #endif
6699
6700 static int e1000e_pm_runtime_idle(struct device *dev)
6701 {
6702 struct net_device *netdev = dev_get_drvdata(dev);
6703 struct e1000_adapter *adapter = netdev_priv(netdev);
6704 u16 eee_lp;
6705
6706 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
6707
6708 if (!e1000e_has_link(adapter)) {
6709 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
6710 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
6711 }
6712
6713 return -EBUSY;
6714 }
6715
6716 static int e1000e_pm_runtime_resume(struct device *dev)
6717 {
6718 struct pci_dev *pdev = to_pci_dev(dev);
6719 struct net_device *netdev = pci_get_drvdata(pdev);
6720 struct e1000_adapter *adapter = netdev_priv(netdev);
6721 int rc;
6722
6723 rc = __e1000_resume(pdev);
6724 if (rc)
6725 return rc;
6726
6727 if (netdev->flags & IFF_UP)
6728 e1000e_up(adapter);
6729
6730 return rc;
6731 }
6732
6733 static int e1000e_pm_runtime_suspend(struct device *dev)
6734 {
6735 struct pci_dev *pdev = to_pci_dev(dev);
6736 struct net_device *netdev = pci_get_drvdata(pdev);
6737 struct e1000_adapter *adapter = netdev_priv(netdev);
6738
6739 if (netdev->flags & IFF_UP) {
6740 int count = E1000_CHECK_RESET_COUNT;
6741
6742 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6743 usleep_range(10000, 11000);
6744
6745 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6746
6747
6748 e1000e_down(adapter, false);
6749 }
6750
6751 if (__e1000_shutdown(pdev, true)) {
6752 e1000e_pm_runtime_resume(dev);
6753 return -EBUSY;
6754 }
6755
6756 return 0;
6757 }
6758 #endif
6759
6760 static void e1000_shutdown(struct pci_dev *pdev)
6761 {
6762 e1000e_flush_lpic(pdev);
6763
6764 e1000e_pm_freeze(&pdev->dev);
6765
6766 __e1000_shutdown(pdev, false);
6767 }
6768
6769 #ifdef CONFIG_NET_POLL_CONTROLLER
6770
6771 static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
6772 {
6773 struct net_device *netdev = data;
6774 struct e1000_adapter *adapter = netdev_priv(netdev);
6775
6776 if (adapter->msix_entries) {
6777 int vector, msix_irq;
6778
6779 vector = 0;
6780 msix_irq = adapter->msix_entries[vector].vector;
6781 if (disable_hardirq(msix_irq))
6782 e1000_intr_msix_rx(msix_irq, netdev);
6783 enable_irq(msix_irq);
6784
6785 vector++;
6786 msix_irq = adapter->msix_entries[vector].vector;
6787 if (disable_hardirq(msix_irq))
6788 e1000_intr_msix_tx(msix_irq, netdev);
6789 enable_irq(msix_irq);
6790
6791 vector++;
6792 msix_irq = adapter->msix_entries[vector].vector;
6793 if (disable_hardirq(msix_irq))
6794 e1000_msix_other(msix_irq, netdev);
6795 enable_irq(msix_irq);
6796 }
6797
6798 return IRQ_HANDLED;
6799 }
6800
6801
6802
6803
6804
6805
6806
6807
6808
6809 static void e1000_netpoll(struct net_device *netdev)
6810 {
6811 struct e1000_adapter *adapter = netdev_priv(netdev);
6812
6813 switch (adapter->int_mode) {
6814 case E1000E_INT_MODE_MSIX:
6815 e1000_intr_msix(adapter->pdev->irq, netdev);
6816 break;
6817 case E1000E_INT_MODE_MSI:
6818 if (disable_hardirq(adapter->pdev->irq))
6819 e1000_intr_msi(adapter->pdev->irq, netdev);
6820 enable_irq(adapter->pdev->irq);
6821 break;
6822 default:
6823 if (disable_hardirq(adapter->pdev->irq))
6824 e1000_intr(adapter->pdev->irq, netdev);
6825 enable_irq(adapter->pdev->irq);
6826 break;
6827 }
6828 }
6829 #endif
6830
6831
6832
6833
6834
6835
6836
6837
6838
6839 static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6840 pci_channel_state_t state)
6841 {
6842 e1000e_pm_freeze(&pdev->dev);
6843
6844 if (state == pci_channel_io_perm_failure)
6845 return PCI_ERS_RESULT_DISCONNECT;
6846
6847 pci_disable_device(pdev);
6848
6849
6850 return PCI_ERS_RESULT_NEED_RESET;
6851 }
6852
6853
6854
6855
6856
6857
6858
6859
6860 static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6861 {
6862 struct net_device *netdev = pci_get_drvdata(pdev);
6863 struct e1000_adapter *adapter = netdev_priv(netdev);
6864 struct e1000_hw *hw = &adapter->hw;
6865 u16 aspm_disable_flag = 0;
6866 int err;
6867 pci_ers_result_t result;
6868
6869 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6870 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6871 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6872 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6873 if (aspm_disable_flag)
6874 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
6875
6876 err = pci_enable_device_mem(pdev);
6877 if (err) {
6878 dev_err(&pdev->dev,
6879 "Cannot re-enable PCI device after reset.\n");
6880 result = PCI_ERS_RESULT_DISCONNECT;
6881 } else {
6882 pdev->state_saved = true;
6883 pci_restore_state(pdev);
6884 pci_set_master(pdev);
6885
6886 pci_enable_wake(pdev, PCI_D3hot, 0);
6887 pci_enable_wake(pdev, PCI_D3cold, 0);
6888
6889 e1000e_reset(adapter);
6890 ew32(WUS, ~0);
6891 result = PCI_ERS_RESULT_RECOVERED;
6892 }
6893
6894 return result;
6895 }
6896
6897
6898
6899
6900
6901
6902
6903
6904
6905 static void e1000_io_resume(struct pci_dev *pdev)
6906 {
6907 struct net_device *netdev = pci_get_drvdata(pdev);
6908 struct e1000_adapter *adapter = netdev_priv(netdev);
6909
6910 e1000_init_manageability_pt(adapter);
6911
6912 e1000e_pm_thaw(&pdev->dev);
6913
6914
6915
6916
6917
6918 if (!(adapter->flags & FLAG_HAS_AMT))
6919 e1000e_get_hw_control(adapter);
6920 }
6921
6922 static void e1000_print_device_info(struct e1000_adapter *adapter)
6923 {
6924 struct e1000_hw *hw = &adapter->hw;
6925 struct net_device *netdev = adapter->netdev;
6926 u32 ret_val;
6927 u8 pba_str[E1000_PBANUM_LENGTH];
6928
6929
6930 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
6931
6932 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
6933 "Width x1"),
6934
6935 netdev->dev_addr);
6936 e_info("Intel(R) PRO/%s Network Connection\n",
6937 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
6938 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6939 E1000_PBANUM_LENGTH);
6940 if (ret_val)
6941 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
6942 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6943 hw->mac.type, hw->phy.type, pba_str);
6944 }
6945
6946 static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6947 {
6948 struct e1000_hw *hw = &adapter->hw;
6949 int ret_val;
6950 u16 buf = 0;
6951
6952 if (hw->mac.type != e1000_82573)
6953 return;
6954
6955 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
6956 le16_to_cpus(&buf);
6957 if (!ret_val && (!(buf & BIT(0)))) {
6958
6959 dev_warn(&adapter->pdev->dev,
6960 "Warning: detected DSPD enabled in EEPROM\n");
6961 }
6962 }
6963
6964 static netdev_features_t e1000_fix_features(struct net_device *netdev,
6965 netdev_features_t features)
6966 {
6967 struct e1000_adapter *adapter = netdev_priv(netdev);
6968 struct e1000_hw *hw = &adapter->hw;
6969
6970
6971 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
6972 features &= ~NETIF_F_RXFCS;
6973
6974
6975
6976
6977 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6978 features |= NETIF_F_HW_VLAN_CTAG_TX;
6979 else
6980 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
6981
6982 return features;
6983 }
6984
6985 static int e1000_set_features(struct net_device *netdev,
6986 netdev_features_t features)
6987 {
6988 struct e1000_adapter *adapter = netdev_priv(netdev);
6989 netdev_features_t changed = features ^ netdev->features;
6990
6991 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6992 adapter->flags |= FLAG_TSO_FORCE;
6993
6994 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6995 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6996 NETIF_F_RXALL)))
6997 return 0;
6998
6999 if (changed & NETIF_F_RXFCS) {
7000 if (features & NETIF_F_RXFCS) {
7001 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7002 } else {
7003
7004
7005
7006 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
7007 adapter->flags2 |= FLAG2_CRC_STRIPPING;
7008 else
7009 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7010 }
7011 }
7012
7013 netdev->features = features;
7014
7015 if (netif_running(netdev))
7016 e1000e_reinit_locked(adapter);
7017 else
7018 e1000e_reset(adapter);
7019
7020 return 1;
7021 }
7022
7023 static const struct net_device_ops e1000e_netdev_ops = {
7024 .ndo_open = e1000e_open,
7025 .ndo_stop = e1000e_close,
7026 .ndo_start_xmit = e1000_xmit_frame,
7027 .ndo_get_stats64 = e1000e_get_stats64,
7028 .ndo_set_rx_mode = e1000e_set_rx_mode,
7029 .ndo_set_mac_address = e1000_set_mac,
7030 .ndo_change_mtu = e1000_change_mtu,
7031 .ndo_do_ioctl = e1000_ioctl,
7032 .ndo_tx_timeout = e1000_tx_timeout,
7033 .ndo_validate_addr = eth_validate_addr,
7034
7035 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7036 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7037 #ifdef CONFIG_NET_POLL_CONTROLLER
7038 .ndo_poll_controller = e1000_netpoll,
7039 #endif
7040 .ndo_set_features = e1000_set_features,
7041 .ndo_fix_features = e1000_fix_features,
7042 .ndo_features_check = passthru_features_check,
7043 };
7044
7045
7046
7047
7048
7049
7050
7051
7052
7053
7054
7055
7056 static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7057 {
7058 struct net_device *netdev;
7059 struct e1000_adapter *adapter;
7060 struct e1000_hw *hw;
7061 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7062 resource_size_t mmio_start, mmio_len;
7063 resource_size_t flash_start, flash_len;
7064 static int cards_found;
7065 u16 aspm_disable_flag = 0;
7066 int bars, i, err, pci_using_dac;
7067 u16 eeprom_data = 0;
7068 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7069 s32 ret_val = 0;
7070
7071 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7072 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7073 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7074 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7075 if (aspm_disable_flag)
7076 e1000e_disable_aspm(pdev, aspm_disable_flag);
7077
7078 err = pci_enable_device_mem(pdev);
7079 if (err)
7080 return err;
7081
7082 pci_using_dac = 0;
7083 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7084 if (!err) {
7085 pci_using_dac = 1;
7086 } else {
7087 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7088 if (err) {
7089 dev_err(&pdev->dev,
7090 "No usable DMA configuration, aborting\n");
7091 goto err_dma;
7092 }
7093 }
7094
7095 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7096 err = pci_request_selected_regions_exclusive(pdev, bars,
7097 e1000e_driver_name);
7098 if (err)
7099 goto err_pci_reg;
7100
7101
7102 pci_enable_pcie_error_reporting(pdev);
7103
7104 pci_set_master(pdev);
7105
7106 err = pci_save_state(pdev);
7107 if (err)
7108 goto err_alloc_etherdev;
7109
7110 err = -ENOMEM;
7111 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7112 if (!netdev)
7113 goto err_alloc_etherdev;
7114
7115 SET_NETDEV_DEV(netdev, &pdev->dev);
7116
7117 netdev->irq = pdev->irq;
7118
7119 pci_set_drvdata(pdev, netdev);
7120 adapter = netdev_priv(netdev);
7121 hw = &adapter->hw;
7122 adapter->netdev = netdev;
7123 adapter->pdev = pdev;
7124 adapter->ei = ei;
7125 adapter->pba = ei->pba;
7126 adapter->flags = ei->flags;
7127 adapter->flags2 = ei->flags2;
7128 adapter->hw.adapter = adapter;
7129 adapter->hw.mac.type = ei->mac;
7130 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7131 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7132
7133 mmio_start = pci_resource_start(pdev, 0);
7134 mmio_len = pci_resource_len(pdev, 0);
7135
7136 err = -EIO;
7137 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7138 if (!adapter->hw.hw_addr)
7139 goto err_ioremap;
7140
7141 if ((adapter->flags & FLAG_HAS_FLASH) &&
7142 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7143 (hw->mac.type < e1000_pch_spt)) {
7144 flash_start = pci_resource_start(pdev, 1);
7145 flash_len = pci_resource_len(pdev, 1);
7146 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7147 if (!adapter->hw.flash_address)
7148 goto err_flashmap;
7149 }
7150
7151
7152 if (adapter->flags2 & FLAG2_HAS_EEE)
7153 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7154
7155
7156 netdev->netdev_ops = &e1000e_netdev_ops;
7157 e1000e_set_ethtool_ops(netdev);
7158 netdev->watchdog_timeo = 5 * HZ;
7159 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
7160 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7161
7162 netdev->mem_start = mmio_start;
7163 netdev->mem_end = mmio_start + mmio_len;
7164
7165 adapter->bd_number = cards_found++;
7166
7167 e1000e_check_options(adapter);
7168
7169
7170 err = e1000_sw_init(adapter);
7171 if (err)
7172 goto err_sw_init;
7173
7174 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7175 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7176 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7177
7178 err = ei->get_variants(adapter);
7179 if (err)
7180 goto err_hw_init;
7181
7182 if ((adapter->flags & FLAG_IS_ICH) &&
7183 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7184 (hw->mac.type < e1000_pch_spt))
7185 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7186
7187 hw->mac.ops.get_bus_info(&adapter->hw);
7188
7189 adapter->hw.phy.autoneg_wait_to_complete = 0;
7190
7191
7192 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7193 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7194 adapter->hw.phy.disable_polarity_correction = 0;
7195 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7196 }
7197
7198 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7199 dev_info(&pdev->dev,
7200 "PHY reset is blocked due to SOL/IDER session.\n");
7201
7202
7203 netdev->features = (NETIF_F_SG |
7204 NETIF_F_HW_VLAN_CTAG_RX |
7205 NETIF_F_HW_VLAN_CTAG_TX |
7206 NETIF_F_TSO |
7207 NETIF_F_TSO6 |
7208 NETIF_F_RXHASH |
7209 NETIF_F_RXCSUM |
7210 NETIF_F_HW_CSUM);
7211
7212
7213 netdev->hw_features = netdev->features;
7214 netdev->hw_features |= NETIF_F_RXFCS;
7215 netdev->priv_flags |= IFF_SUPP_NOFCS;
7216 netdev->hw_features |= NETIF_F_RXALL;
7217
7218 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7219 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7220
7221 netdev->vlan_features |= (NETIF_F_SG |
7222 NETIF_F_TSO |
7223 NETIF_F_TSO6 |
7224 NETIF_F_HW_CSUM);
7225
7226 netdev->priv_flags |= IFF_UNICAST_FLT;
7227
7228 if (pci_using_dac) {
7229 netdev->features |= NETIF_F_HIGHDMA;
7230 netdev->vlan_features |= NETIF_F_HIGHDMA;
7231 }
7232
7233
7234 netdev->min_mtu = ETH_MIN_MTU;
7235 netdev->max_mtu = adapter->max_hw_frame_size -
7236 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7237
7238 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7239 adapter->flags |= FLAG_MNG_PT_ENABLED;
7240
7241
7242
7243
7244 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7245
7246
7247
7248
7249 for (i = 0;; i++) {
7250 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7251 break;
7252 if (i == 2) {
7253 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7254 err = -EIO;
7255 goto err_eeprom;
7256 }
7257 }
7258
7259 e1000_eeprom_checks(adapter);
7260
7261
7262 if (e1000e_read_mac_addr(&adapter->hw))
7263 dev_err(&pdev->dev,
7264 "NVM Read Error while reading MAC address\n");
7265
7266 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
7267
7268 if (!is_valid_ether_addr(netdev->dev_addr)) {
7269 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7270 netdev->dev_addr);
7271 err = -EIO;
7272 goto err_eeprom;
7273 }
7274
7275 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
7276 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7277
7278 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7279 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7280 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7281 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7282 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7283
7284
7285 adapter->hw.mac.autoneg = 1;
7286 adapter->fc_autoneg = true;
7287 adapter->hw.fc.requested_mode = e1000_fc_default;
7288 adapter->hw.fc.current_mode = e1000_fc_default;
7289 adapter->hw.phy.autoneg_advertised = 0x2f;
7290
7291
7292
7293
7294 if (adapter->flags & FLAG_APME_IN_WUC) {
7295
7296 eeprom_data = er32(WUC);
7297 eeprom_apme_mask = E1000_WUC_APME;
7298 if ((hw->mac.type > e1000_ich10lan) &&
7299 (eeprom_data & E1000_WUC_PHY_WAKE))
7300 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7301 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7302 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7303 (adapter->hw.bus.func == 1))
7304 ret_val = e1000_read_nvm(&adapter->hw,
7305 NVM_INIT_CONTROL3_PORT_B,
7306 1, &eeprom_data);
7307 else
7308 ret_val = e1000_read_nvm(&adapter->hw,
7309 NVM_INIT_CONTROL3_PORT_A,
7310 1, &eeprom_data);
7311 }
7312
7313
7314 if (ret_val)
7315 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7316 else if (eeprom_data & eeprom_apme_mask)
7317 adapter->eeprom_wol |= E1000_WUFC_MAG;
7318
7319
7320
7321
7322
7323 if (!(adapter->flags & FLAG_HAS_WOL))
7324 adapter->eeprom_wol = 0;
7325
7326
7327 adapter->wol = adapter->eeprom_wol;
7328
7329
7330 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7331 (hw->mac.ops.check_mng_mode(hw)))
7332 device_wakeup_enable(&pdev->dev);
7333
7334
7335 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7336
7337 if (ret_val) {
7338 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7339 adapter->eeprom_vers = 0;
7340 }
7341
7342
7343 e1000e_ptp_init(adapter);
7344
7345
7346 e1000e_reset(adapter);
7347
7348
7349
7350
7351
7352 if (!(adapter->flags & FLAG_HAS_AMT))
7353 e1000e_get_hw_control(adapter);
7354
7355 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
7356 err = register_netdev(netdev);
7357 if (err)
7358 goto err_register;
7359
7360
7361 netif_carrier_off(netdev);
7362
7363 e1000_print_device_info(adapter);
7364
7365 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
7366
7367 if (pci_dev_run_wake(pdev) && hw->mac.type < e1000_pch_cnp)
7368 pm_runtime_put_noidle(&pdev->dev);
7369
7370 return 0;
7371
7372 err_register:
7373 if (!(adapter->flags & FLAG_HAS_AMT))
7374 e1000e_release_hw_control(adapter);
7375 err_eeprom:
7376 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7377 e1000_phy_hw_reset(&adapter->hw);
7378 err_hw_init:
7379 kfree(adapter->tx_ring);
7380 kfree(adapter->rx_ring);
7381 err_sw_init:
7382 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7383 iounmap(adapter->hw.flash_address);
7384 e1000e_reset_interrupt_capability(adapter);
7385 err_flashmap:
7386 iounmap(adapter->hw.hw_addr);
7387 err_ioremap:
7388 free_netdev(netdev);
7389 err_alloc_etherdev:
7390 pci_release_mem_regions(pdev);
7391 err_pci_reg:
7392 err_dma:
7393 pci_disable_device(pdev);
7394 return err;
7395 }
7396
7397
7398
7399
7400
7401
7402
7403
7404
7405
7406 static void e1000_remove(struct pci_dev *pdev)
7407 {
7408 struct net_device *netdev = pci_get_drvdata(pdev);
7409 struct e1000_adapter *adapter = netdev_priv(netdev);
7410
7411 e1000e_ptp_remove(adapter);
7412
7413
7414
7415
7416 set_bit(__E1000_DOWN, &adapter->state);
7417 del_timer_sync(&adapter->watchdog_timer);
7418 del_timer_sync(&adapter->phy_info_timer);
7419
7420 cancel_work_sync(&adapter->reset_task);
7421 cancel_work_sync(&adapter->watchdog_task);
7422 cancel_work_sync(&adapter->downshift_task);
7423 cancel_work_sync(&adapter->update_phy_task);
7424 cancel_work_sync(&adapter->print_hang_task);
7425
7426 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7427 cancel_work_sync(&adapter->tx_hwtstamp_work);
7428 if (adapter->tx_hwtstamp_skb) {
7429 dev_consume_skb_any(adapter->tx_hwtstamp_skb);
7430 adapter->tx_hwtstamp_skb = NULL;
7431 }
7432 }
7433
7434 unregister_netdev(netdev);
7435
7436 if (pci_dev_run_wake(pdev))
7437 pm_runtime_get_noresume(&pdev->dev);
7438
7439
7440
7441
7442 e1000e_release_hw_control(adapter);
7443
7444 e1000e_reset_interrupt_capability(adapter);
7445 kfree(adapter->tx_ring);
7446 kfree(adapter->rx_ring);
7447
7448 iounmap(adapter->hw.hw_addr);
7449 if ((adapter->hw.flash_address) &&
7450 (adapter->hw.mac.type < e1000_pch_spt))
7451 iounmap(adapter->hw.flash_address);
7452 pci_release_mem_regions(pdev);
7453
7454 free_netdev(netdev);
7455
7456
7457 pci_disable_pcie_error_reporting(pdev);
7458
7459 pci_disable_device(pdev);
7460 }
7461
7462
7463 static const struct pci_error_handlers e1000_err_handler = {
7464 .error_detected = e1000_io_error_detected,
7465 .slot_reset = e1000_io_slot_reset,
7466 .resume = e1000_io_resume,
7467 };
7468
7469 static const struct pci_device_id e1000_pci_tbl[] = {
7470 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7471 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7472 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7473 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7474 board_82571 },
7475 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7476 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7477 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7478 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7479 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7480
7481 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7482 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7483 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7484 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7485
7486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7487 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7488 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7489
7490 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7491 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7492 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7493
7494 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7495 board_80003es2lan },
7496 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7497 board_80003es2lan },
7498 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7499 board_80003es2lan },
7500 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7501 board_80003es2lan },
7502
7503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7504 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7505 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7506 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7507 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7508 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7509 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7510 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7511
7512 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7513 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7514 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7515 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7516 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7517 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7518 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7519 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7520 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7521
7522 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7523 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7524 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7525
7526 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7527 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7528 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7529
7530 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7531 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7532 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7533 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7534
7535 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7536 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7537
7538 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7539 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7540 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7541 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7542 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7543 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7544 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7545 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7546 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7547 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7548 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7549 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7550 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
7551 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7552 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7553 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7554 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
7555 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
7556 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
7557 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
7558 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
7559 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
7560 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
7561 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
7562 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
7563
7564 { 0, 0, 0, 0, 0, 0, 0 }
7565 };
7566 MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7567
7568 static const struct dev_pm_ops e1000_pm_ops = {
7569 #ifdef CONFIG_PM_SLEEP
7570 .suspend = e1000e_pm_suspend,
7571 .resume = e1000e_pm_resume,
7572 .freeze = e1000e_pm_freeze,
7573 .thaw = e1000e_pm_thaw,
7574 .poweroff = e1000e_pm_suspend,
7575 .restore = e1000e_pm_resume,
7576 #endif
7577 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7578 e1000e_pm_runtime_idle)
7579 };
7580
7581
7582 static struct pci_driver e1000_driver = {
7583 .name = e1000e_driver_name,
7584 .id_table = e1000_pci_tbl,
7585 .probe = e1000_probe,
7586 .remove = e1000_remove,
7587 .driver = {
7588 .pm = &e1000_pm_ops,
7589 },
7590 .shutdown = e1000_shutdown,
7591 .err_handler = &e1000_err_handler
7592 };
7593
7594
7595
7596
7597
7598
7599
7600 static int __init e1000_init_module(void)
7601 {
7602 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7603 e1000e_driver_version);
7604 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7605
7606 return pci_register_driver(&e1000_driver);
7607 }
7608 module_init(e1000_init_module);
7609
7610
7611
7612
7613
7614
7615
7616 static void __exit e1000_exit_module(void)
7617 {
7618 pci_unregister_driver(&e1000_driver);
7619 }
7620 module_exit(e1000_exit_module);
7621
7622 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7623 MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7624 MODULE_LICENSE("GPL v2");
7625 MODULE_VERSION(DRV_VERSION);
7626
7627