drivers/net/ethernet/intel/e1000e/phy.h

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   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3 
   4 #ifndef _E1000E_PHY_H_
   5 #define _E1000E_PHY_H_
   6 
   7 s32 e1000e_check_downshift(struct e1000_hw *hw);
   8 s32 e1000_check_polarity_m88(struct e1000_hw *hw);
   9 s32 e1000_check_polarity_igp(struct e1000_hw *hw);
  10 s32 e1000_check_polarity_ife(struct e1000_hw *hw);
  11 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
  12 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
  13 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
  14 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
  15 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
  16 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
  17 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
  18 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
  19 s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw);
  20 s32 e1000e_get_phy_id(struct e1000_hw *hw);
  21 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
  22 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
  23 s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
  24 s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
  25 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
  26 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
  27 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
  28 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
  29 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
  30 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
  31 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
  32 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
  33 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
  34 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
  35 s32 e1000e_setup_copper_link(struct e1000_hw *hw);
  36 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
  37 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
  38 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
  39 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
  40 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
  41 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
  42                                 u32 usec_interval, bool *success);
  43 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
  44 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
  45 s32 e1000e_determine_phy_address(struct e1000_hw *hw);
  46 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
  47 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
  48 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
  49 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
  50 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
  51 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
  52 void e1000_power_up_phy_copper(struct e1000_hw *hw);
  53 void e1000_power_down_phy_copper(struct e1000_hw *hw);
  54 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
  55 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
  56 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
  57 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
  58 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data);
  59 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
  60 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
  61 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data);
  62 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
  63 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
  64 s32 e1000_check_polarity_82577(struct e1000_hw *hw);
  65 s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
  66 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
  67 s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
  68 
  69 #define E1000_MAX_PHY_ADDR              8
  70 
  71 /* IGP01E1000 Specific Registers */
  72 #define IGP01E1000_PHY_PORT_CONFIG      0x10    /* Port Config */
  73 #define IGP01E1000_PHY_PORT_STATUS      0x11    /* Status */
  74 #define IGP01E1000_PHY_PORT_CTRL        0x12    /* Control */
  75 #define IGP01E1000_PHY_LINK_HEALTH      0x13    /* PHY Link Health */
  76 #define IGP02E1000_PHY_POWER_MGMT       0x19    /* Power Management */
  77 #define IGP01E1000_PHY_PAGE_SELECT      0x1F    /* Page Select */
  78 #define BM_PHY_PAGE_SELECT              22      /* Page Select for BM */
  79 #define IGP_PAGE_SHIFT                  5
  80 #define PHY_REG_MASK                    0x1F
  81 
  82 /* BM/HV Specific Registers */
  83 #define BM_PORT_CTRL_PAGE               769
  84 #define BM_WUC_PAGE                     800
  85 #define BM_WUC_ADDRESS_OPCODE           0x11
  86 #define BM_WUC_DATA_OPCODE              0x12
  87 #define BM_WUC_ENABLE_PAGE              BM_PORT_CTRL_PAGE
  88 #define BM_WUC_ENABLE_REG               17
  89 #define BM_WUC_ENABLE_BIT               BIT(2)
  90 #define BM_WUC_HOST_WU_BIT              BIT(4)
  91 #define BM_WUC_ME_WU_BIT                BIT(5)
  92 
  93 #define PHY_UPPER_SHIFT                 21
  94 #define BM_PHY_REG(page, reg) \
  95         (((reg) & MAX_PHY_REG_ADDRESS) |\
  96          (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
  97          (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
  98 #define BM_PHY_REG_PAGE(offset) \
  99         ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
 100 #define BM_PHY_REG_NUM(offset) \
 101         ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
 102          (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
 103                 ~MAX_PHY_REG_ADDRESS)))
 104 
 105 #define HV_INTC_FC_PAGE_START           768
 106 #define I82578_ADDR_REG                 29
 107 #define I82577_ADDR_REG                 16
 108 #define I82577_CFG_REG                  22
 109 #define I82577_CFG_ASSERT_CRS_ON_TX     BIT(15)
 110 #define I82577_CFG_ENABLE_DOWNSHIFT     (3u << 10)      /* auto downshift */
 111 #define I82577_CTRL_REG                 23
 112 
 113 /* 82577 specific PHY registers */
 114 #define I82577_PHY_CTRL_2               18
 115 #define I82577_PHY_LBK_CTRL             19
 116 #define I82577_PHY_STATUS_2             26
 117 #define I82577_PHY_DIAG_STATUS          31
 118 
 119 /* I82577 PHY Status 2 */
 120 #define I82577_PHY_STATUS2_REV_POLARITY         0x0400
 121 #define I82577_PHY_STATUS2_MDIX                 0x0800
 122 #define I82577_PHY_STATUS2_SPEED_MASK           0x0300
 123 #define I82577_PHY_STATUS2_SPEED_1000MBPS       0x0200
 124 
 125 /* I82577 PHY Control 2 */
 126 #define I82577_PHY_CTRL2_MANUAL_MDIX            0x0200
 127 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX          0x0400
 128 #define I82577_PHY_CTRL2_MDIX_CFG_MASK          0x0600
 129 
 130 /* I82577 PHY Diagnostics Status */
 131 #define I82577_DSTATUS_CABLE_LENGTH             0x03FC
 132 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT       2
 133 
 134 /* BM PHY Copper Specific Control 1 */
 135 #define BM_CS_CTRL1                     16
 136 
 137 /* BM PHY Copper Specific Status */
 138 #define BM_CS_STATUS                    17
 139 #define BM_CS_STATUS_LINK_UP            0x0400
 140 #define BM_CS_STATUS_RESOLVED           0x0800
 141 #define BM_CS_STATUS_SPEED_MASK         0xC000
 142 #define BM_CS_STATUS_SPEED_1000         0x8000
 143 
 144 /* 82577 Mobile Phy Status Register */
 145 #define HV_M_STATUS                     26
 146 #define HV_M_STATUS_AUTONEG_COMPLETE    0x1000
 147 #define HV_M_STATUS_SPEED_MASK          0x0300
 148 #define HV_M_STATUS_SPEED_1000          0x0200
 149 #define HV_M_STATUS_SPEED_100           0x0100
 150 #define HV_M_STATUS_LINK_UP             0x0040
 151 
 152 #define IGP01E1000_PHY_PCS_INIT_REG     0x00B4
 153 #define IGP01E1000_PHY_POLARITY_MASK    0x0078
 154 
 155 #define IGP01E1000_PSCR_AUTO_MDIX       0x1000
 156 #define IGP01E1000_PSCR_FORCE_MDI_MDIX  0x2000  /* 0=MDI, 1=MDIX */
 157 
 158 #define IGP01E1000_PSCFR_SMART_SPEED    0x0080
 159 
 160 #define IGP02E1000_PM_SPD               0x0001  /* Smart Power Down */
 161 #define IGP02E1000_PM_D0_LPLU           0x0002  /* For D0a states */
 162 #define IGP02E1000_PM_D3_LPLU           0x0004  /* For all other states */
 163 
 164 #define IGP01E1000_PLHR_SS_DOWNGRADE    0x8000
 165 
 166 #define IGP01E1000_PSSR_POLARITY_REVERSED       0x0002
 167 #define IGP01E1000_PSSR_MDIX            0x0800
 168 #define IGP01E1000_PSSR_SPEED_MASK      0xC000
 169 #define IGP01E1000_PSSR_SPEED_1000MBPS  0xC000
 170 
 171 #define IGP02E1000_PHY_CHANNEL_NUM      4
 172 #define IGP02E1000_PHY_AGC_A            0x11B1
 173 #define IGP02E1000_PHY_AGC_B            0x12B1
 174 #define IGP02E1000_PHY_AGC_C            0x14B1
 175 #define IGP02E1000_PHY_AGC_D            0x18B1
 176 
 177 #define IGP02E1000_AGC_LENGTH_SHIFT     9       /* Course=15:13, Fine=12:9 */
 178 #define IGP02E1000_AGC_LENGTH_MASK      0x7F
 179 #define IGP02E1000_AGC_RANGE            15
 180 
 181 #define E1000_CABLE_LENGTH_UNDEFINED    0xFF
 182 
 183 #define E1000_KMRNCTRLSTA_OFFSET        0x001F0000
 184 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT  16
 185 #define E1000_KMRNCTRLSTA_REN           0x00200000
 186 #define E1000_KMRNCTRLSTA_CTRL_OFFSET   0x1     /* Kumeran Control */
 187 #define E1000_KMRNCTRLSTA_DIAG_OFFSET   0x3     /* Kumeran Diagnostic */
 188 #define E1000_KMRNCTRLSTA_TIMEOUTS      0x4     /* Kumeran Timeouts */
 189 #define E1000_KMRNCTRLSTA_INBAND_PARAM  0x9     /* Kumeran InBand Parameters */
 190 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200  /* Kumeran IBIST Disable */
 191 #define E1000_KMRNCTRLSTA_DIAG_NELPBK   0x1000  /* Nearend Loopback mode */
 192 #define E1000_KMRNCTRLSTA_K1_CONFIG     0x7
 193 #define E1000_KMRNCTRLSTA_K1_ENABLE     0x0002  /* enable K1 */
 194 #define E1000_KMRNCTRLSTA_HD_CTRL       0x10    /* Kumeran HD Control */
 195 
 196 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
 197 #define IFE_PHY_SPECIAL_CONTROL         0x11    /* 100BaseTx PHY Special Ctrl */
 198 #define IFE_PHY_SPECIAL_CONTROL_LED     0x1B    /* PHY Special and LED Ctrl */
 199 #define IFE_PHY_MDIX_CONTROL            0x1C    /* MDI/MDI-X Control */
 200 
 201 /* IFE PHY Extended Status Control */
 202 #define IFE_PESC_POLARITY_REVERSED      0x0100
 203 
 204 /* IFE PHY Special Control */
 205 #define IFE_PSC_AUTO_POLARITY_DISABLE   0x0010
 206 #define IFE_PSC_FORCE_POLARITY          0x0020
 207 
 208 /* IFE PHY Special Control and LED Control */
 209 #define IFE_PSCL_PROBE_MODE             0x0020
 210 #define IFE_PSCL_PROBE_LEDS_OFF         0x0006  /* Force LEDs 0 and 2 off */
 211 #define IFE_PSCL_PROBE_LEDS_ON          0x0007  /* Force LEDs 0 and 2 on */
 212 
 213 /* IFE PHY MDIX Control */
 214 #define IFE_PMC_MDIX_STATUS             0x0020  /* 1=MDI-X, 0=MDI */
 215 #define IFE_PMC_FORCE_MDIX              0x0040  /* 1=force MDI-X, 0=force MDI */
 216 #define IFE_PMC_AUTO_MDIX               0x0080  /* 1=enable auto, 0=disable */
 217 
 218 #endif
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root/drivers/net/ethernet/intel/e1000e/phy.h

INCLUDED FROM
