root/drivers/net/ethernet/intel/e1000e/ich8lan.c

DEFINITIONS

1. __er16flash
2. __er32flash
3. __ew16flash
4. __ew32flash
5. e1000_phy_is_accessible_pchlan
6. e1000_toggle_lanphypc_pch_lpt
7. e1000_init_phy_workarounds_pchlan
8. e1000_init_phy_params_pchlan
9. e1000_init_phy_params_ich8lan
10. e1000_init_nvm_params_ich8lan
11. e1000_init_mac_params_ich8lan
12. __e1000_access_emi_reg_locked
13. e1000_read_emi_reg_locked
14. e1000_write_emi_reg_locked
15. e1000_set_eee_pchlan
16. e1000_k1_workaround_lpt_lp
17. e1000_platform_pm_pch_lpt
18. e1000_enable_ulp_lpt_lp
19. e1000_disable_ulp_lpt_lp
20. e1000_check_for_copper_link_ich8lan
21. e1000_get_variants_ich8lan
22. e1000_acquire_nvm_ich8lan
23. e1000_release_nvm_ich8lan
24. e1000_acquire_swflag_ich8lan
25. e1000_release_swflag_ich8lan
26. e1000_check_mng_mode_ich8lan
27. e1000_check_mng_mode_pchlan
28. e1000_rar_set_pch2lan
29. e1000_rar_get_count_pch_lpt
30. e1000_rar_set_pch_lpt
31. e1000_check_reset_block_ich8lan
32. e1000_write_smbus_addr
33. e1000_sw_lcd_config_ich8lan
34. e1000_k1_gig_workaround_hv
35. e1000_configure_k1_ich8lan
36. e1000_oem_bits_config_ich8lan
37. e1000_set_mdio_slow_mode_hv
38. e1000_hv_phy_workarounds_ich8lan
39. e1000_copy_rx_addrs_to_phy_ich8lan
40. e1000_lv_jumbo_workaround_ich8lan
41. e1000_lv_phy_workarounds_ich8lan
42. e1000_k1_workaround_lv
43. e1000_gate_hw_phy_config_ich8lan
44. e1000_lan_init_done_ich8lan
45. e1000_post_phy_reset_ich8lan
46. e1000_phy_hw_reset_ich8lan
47. e1000_set_lplu_state_pchlan
48. e1000_set_d0_lplu_state_ich8lan
49. e1000_set_d3_lplu_state_ich8lan
50. e1000_valid_nvm_bank_detect_ich8lan
51. e1000_read_nvm_spt
52. e1000_read_nvm_ich8lan
53. e1000_flash_cycle_init_ich8lan
54. e1000_flash_cycle_ich8lan
55. e1000_read_flash_dword_ich8lan
56. e1000_read_flash_word_ich8lan
57. e1000_read_flash_byte_ich8lan
58. e1000_read_flash_data_ich8lan
59. e1000_read_flash_data32_ich8lan
60. e1000_write_nvm_ich8lan
61. e1000_update_nvm_checksum_spt
62. e1000_update_nvm_checksum_ich8lan
63. e1000_validate_nvm_checksum_ich8lan
64. e1000e_write_protect_nvm_ich8lan
65. e1000_write_flash_data_ich8lan
66. e1000_write_flash_data32_ich8lan
67. e1000_write_flash_byte_ich8lan
68. e1000_retry_write_flash_dword_ich8lan
69. e1000_retry_write_flash_byte_ich8lan
70. e1000_erase_flash_bank_ich8lan
71. e1000_valid_led_default_ich8lan
72. e1000_id_led_init_pchlan
73. e1000_get_bus_info_ich8lan
74. e1000_reset_hw_ich8lan
75. e1000_init_hw_ich8lan
76. e1000_initialize_hw_bits_ich8lan
77. e1000_setup_link_ich8lan
78. e1000_setup_copper_link_ich8lan
79. e1000_setup_copper_link_pch_lpt
80. e1000_get_link_up_info_ich8lan
81. e1000_kmrn_lock_loss_workaround_ich8lan
82. e1000e_set_kmrn_lock_loss_workaround_ich8lan
83. e1000e_igp3_phy_powerdown_workaround_ich8lan
84. e1000e_gig_downshift_workaround_ich8lan
85. e1000_suspend_workarounds_ich8lan
86. e1000_resume_workarounds_pchlan
87. e1000_cleanup_led_ich8lan
88. e1000_led_on_ich8lan
89. e1000_led_off_ich8lan
90. e1000_setup_led_pchlan
91. e1000_cleanup_led_pchlan
92. e1000_led_on_pchlan
93. e1000_led_off_pchlan
94. e1000_get_cfg_done_ich8lan
95. e1000_power_down_phy_copper_ich8lan
96. e1000_clear_hw_cntrs_ich8lan

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3 
   4 /* 82562G 10/100 Network Connection
   5  * 82562G-2 10/100 Network Connection
   6  * 82562GT 10/100 Network Connection
   7  * 82562GT-2 10/100 Network Connection
   8  * 82562V 10/100 Network Connection
   9  * 82562V-2 10/100 Network Connection
  10  * 82566DC-2 Gigabit Network Connection
  11  * 82566DC Gigabit Network Connection
  12  * 82566DM-2 Gigabit Network Connection
  13  * 82566DM Gigabit Network Connection
  14  * 82566MC Gigabit Network Connection
  15  * 82566MM Gigabit Network Connection
  16  * 82567LM Gigabit Network Connection
  17  * 82567LF Gigabit Network Connection
  18  * 82567V Gigabit Network Connection
  19  * 82567LM-2 Gigabit Network Connection
  20  * 82567LF-2 Gigabit Network Connection
  21  * 82567V-2 Gigabit Network Connection
  22  * 82567LF-3 Gigabit Network Connection
  23  * 82567LM-3 Gigabit Network Connection
  24  * 82567LM-4 Gigabit Network Connection
  25  * 82577LM Gigabit Network Connection
  26  * 82577LC Gigabit Network Connection
  27  * 82578DM Gigabit Network Connection
  28  * 82578DC Gigabit Network Connection
  29  * 82579LM Gigabit Network Connection
  30  * 82579V Gigabit Network Connection
  31  * Ethernet Connection I217-LM
  32  * Ethernet Connection I217-V
  33  * Ethernet Connection I218-V
  34  * Ethernet Connection I218-LM
  35  * Ethernet Connection (2) I218-LM
  36  * Ethernet Connection (2) I218-V
  37  * Ethernet Connection (3) I218-LM
  38  * Ethernet Connection (3) I218-V
  39  */
  40 
  41 #include "e1000.h"
  42 
  43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  44 /* Offset 04h HSFSTS */
  45 union ich8_hws_flash_status {
  46         struct ich8_hsfsts {
  47                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  48                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  49                 u16 dael:1;     /* bit 2 Direct Access error Log */
  50                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  51                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  52                 u16 reserved1:2;        /* bit 13:6 Reserved */
  53                 u16 reserved2:6;        /* bit 13:6 Reserved */
  54                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  55                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  56         } hsf_status;
  57         u16 regval;
  58 };
  59 
  60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  61 /* Offset 06h FLCTL */
  62 union ich8_hws_flash_ctrl {
  63         struct ich8_hsflctl {
  64                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  65                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  66                 u16 reserved:5; /* 7:3 Reserved  */
  67                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  68                 u16 flockdn:6;  /* 15:10 Reserved */
  69         } hsf_ctrl;
  70         u16 regval;
  71 };
  72 
  73 /* ICH Flash Region Access Permissions */
  74 union ich8_hws_flash_regacc {
  75         struct ich8_flracc {
  76                 u32 grra:8;     /* 0:7 GbE region Read Access */
  77                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  78                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  79                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  80         } hsf_flregacc;
  81         u16 regval;
  82 };
  83 
  84 /* ICH Flash Protected Region */
  85 union ich8_flash_protected_range {
  86         struct ich8_pr {
  87                 u32 base:13;    /* 0:12 Protected Range Base */
  88                 u32 reserved1:2;        /* 13:14 Reserved */
  89                 u32 rpe:1;      /* 15 Read Protection Enable */
  90                 u32 limit:13;   /* 16:28 Protected Range Limit */
  91                 u32 reserved2:2;        /* 29:30 Reserved */
  92                 u32 wpe:1;      /* 31 Write Protection Enable */
  93         } range;
  94         u32 regval;
  95 };
  96 
  97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
  98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
  99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 101                                                 u32 offset, u8 byte);
 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 103                                          u8 *data);
 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 105                                          u16 *data);
 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 107                                          u8 size, u16 *data);
 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 109                                            u32 *data);
 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 111                                           u32 offset, u32 *data);
 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 113                                             u32 offset, u32 data);
 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 115                                                  u32 offset, u32 dword);
 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
 140 
 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 142 {
 143         return readw(hw->flash_address + reg);
 144 }
 145 
 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 147 {
 148         return readl(hw->flash_address + reg);
 149 }
 150 
 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 152 {
 153         writew(val, hw->flash_address + reg);
 154 }
 155 
 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 157 {
 158         writel(val, hw->flash_address + reg);
 159 }
 160 
 161 #define er16flash(reg)          __er16flash(hw, (reg))
 162 #define er32flash(reg)          __er32flash(hw, (reg))
 163 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 164 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 165 
 166 /**
 167  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 168  *  @hw: pointer to the HW structure
 169  *
 170  *  Test access to the PHY registers by reading the PHY ID registers.  If
 171  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 172  *  otherwise assume the read PHY ID is correct if it is valid.
 173  *
 174  *  Assumes the sw/fw/hw semaphore is already acquired.
 175  **/
 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 177 {
 178         u16 phy_reg = 0;
 179         u32 phy_id = 0;
 180         s32 ret_val = 0;
 181         u16 retry_count;
 182         u32 mac_reg = 0;
 183 
 184         for (retry_count = 0; retry_count < 2; retry_count++) {
 185                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 186                 if (ret_val || (phy_reg == 0xFFFF))
 187                         continue;
 188                 phy_id = (u32)(phy_reg << 16);
 189 
 190                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 191                 if (ret_val || (phy_reg == 0xFFFF)) {
 192                         phy_id = 0;
 193                         continue;
 194                 }
 195                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 196                 break;
 197         }
 198 
 199         if (hw->phy.id) {
 200                 if (hw->phy.id == phy_id)
 201                         goto out;
 202         } else if (phy_id) {
 203                 hw->phy.id = phy_id;
 204                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 205                 goto out;
 206         }
 207 
 208         /* In case the PHY needs to be in mdio slow mode,
 209          * set slow mode and try to get the PHY id again.
 210          */
 211         if (hw->mac.type < e1000_pch_lpt) {
 212                 hw->phy.ops.release(hw);
 213                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 214                 if (!ret_val)
 215                         ret_val = e1000e_get_phy_id(hw);
 216                 hw->phy.ops.acquire(hw);
 217         }
 218 
 219         if (ret_val)
 220                 return false;
 221 out:
 222         if (hw->mac.type >= e1000_pch_lpt) {
 223                 /* Only unforce SMBus if ME is not active */
 224                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 225                         /* Unforce SMBus mode in PHY */
 226                         e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 227                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 228                         e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 229 
 230                         /* Unforce SMBus mode in MAC */
 231                         mac_reg = er32(CTRL_EXT);
 232                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 233                         ew32(CTRL_EXT, mac_reg);
 234                 }
 235         }
 236 
 237         return true;
 238 }
 239 
 240 /**
 241  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 242  *  @hw: pointer to the HW structure
 243  *
 244  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 245  *  used to reset the PHY to a quiescent state when necessary.
 246  **/
 247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 248 {
 249         u32 mac_reg;
 250 
 251         /* Set Phy Config Counter to 50msec */
 252         mac_reg = er32(FEXTNVM3);
 253         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 254         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 255         ew32(FEXTNVM3, mac_reg);
 256 
 257         /* Toggle LANPHYPC Value bit */
 258         mac_reg = er32(CTRL);
 259         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 260         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 261         ew32(CTRL, mac_reg);
 262         e1e_flush();
 263         usleep_range(10, 20);
 264         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 265         ew32(CTRL, mac_reg);
 266         e1e_flush();
 267 
 268         if (hw->mac.type < e1000_pch_lpt) {
 269                 msleep(50);
 270         } else {
 271                 u16 count = 20;
 272 
 273                 do {
 274                         usleep_range(5000, 6000);
 275                 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
 276 
 277                 msleep(30);
 278         }
 279 }
 280 
 281 /**
 282  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 283  *  @hw: pointer to the HW structure
 284  *
 285  *  Workarounds/flow necessary for PHY initialization during driver load
 286  *  and resume paths.
 287  **/
 288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 289 {
 290         struct e1000_adapter *adapter = hw->adapter;
 291         u32 mac_reg, fwsm = er32(FWSM);
 292         s32 ret_val;
 293 
 294         /* Gate automatic PHY configuration by hardware on managed and
 295          * non-managed 82579 and newer adapters.
 296          */
 297         e1000_gate_hw_phy_config_ich8lan(hw, true);
 298 
 299         /* It is not possible to be certain of the current state of ULP
 300          * so forcibly disable it.
 301          */
 302         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 303         e1000_disable_ulp_lpt_lp(hw, true);
 304 
 305         ret_val = hw->phy.ops.acquire(hw);
 306         if (ret_val) {
 307                 e_dbg("Failed to initialize PHY flow\n");
 308                 goto out;
 309         }
 310 
 311         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 312          * inaccessible and resetting the PHY is not blocked, toggle the
 313          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 314          */
 315         switch (hw->mac.type) {
 316         case e1000_pch_lpt:
 317         case e1000_pch_spt:
 318         case e1000_pch_cnp:
 319                 if (e1000_phy_is_accessible_pchlan(hw))
 320                         break;
 321 
 322                 /* Before toggling LANPHYPC, see if PHY is accessible by
 323                  * forcing MAC to SMBus mode first.
 324                  */
 325                 mac_reg = er32(CTRL_EXT);
 326                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 327                 ew32(CTRL_EXT, mac_reg);
 328 
 329                 /* Wait 50 milliseconds for MAC to finish any retries
 330                  * that it might be trying to perform from previous
 331                  * attempts to acknowledge any phy read requests.
 332                  */
 333                 msleep(50);
 334 
 335                 /* fall-through */
 336         case e1000_pch2lan:
 337                 if (e1000_phy_is_accessible_pchlan(hw))
 338                         break;
 339 
 340                 /* fall-through */
 341         case e1000_pchlan:
 342                 if ((hw->mac.type == e1000_pchlan) &&
 343                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 344                         break;
 345 
 346                 if (hw->phy.ops.check_reset_block(hw)) {
 347                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 348                         ret_val = -E1000_ERR_PHY;
 349                         break;
 350                 }
 351 
 352                 /* Toggle LANPHYPC Value bit */
 353                 e1000_toggle_lanphypc_pch_lpt(hw);
 354                 if (hw->mac.type >= e1000_pch_lpt) {
 355                         if (e1000_phy_is_accessible_pchlan(hw))
 356                                 break;
 357 
 358                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 359                          * so ensure that the MAC is also out of SMBus mode
 360                          */
 361                         mac_reg = er32(CTRL_EXT);
 362                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 363                         ew32(CTRL_EXT, mac_reg);
 364 
 365                         if (e1000_phy_is_accessible_pchlan(hw))
 366                                 break;
 367 
 368                         ret_val = -E1000_ERR_PHY;
 369                 }
 370                 break;
 371         default:
 372                 break;
 373         }
 374 
 375         hw->phy.ops.release(hw);
 376         if (!ret_val) {
 377 
 378                 /* Check to see if able to reset PHY.  Print error if not */
 379                 if (hw->phy.ops.check_reset_block(hw)) {
 380                         e_err("Reset blocked by ME\n");
 381                         goto out;
 382                 }
 383 
 384                 /* Reset the PHY before any access to it.  Doing so, ensures
 385                  * that the PHY is in a known good state before we read/write
 386                  * PHY registers.  The generic reset is sufficient here,
 387                  * because we haven't determined the PHY type yet.
 388                  */
 389                 ret_val = e1000e_phy_hw_reset_generic(hw);
 390                 if (ret_val)
 391                         goto out;
 392 
 393                 /* On a successful reset, possibly need to wait for the PHY
 394                  * to quiesce to an accessible state before returning control
 395                  * to the calling function.  If the PHY does not quiesce, then
 396                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 397                  *  the PHY is in.
 398                  */
 399                 ret_val = hw->phy.ops.check_reset_block(hw);
 400                 if (ret_val)
 401                         e_err("ME blocked access to PHY after reset\n");
 402         }
 403 
 404 out:
 405         /* Ungate automatic PHY configuration on non-managed 82579 */
 406         if ((hw->mac.type == e1000_pch2lan) &&
 407             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 408                 usleep_range(10000, 11000);
 409                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 410         }
 411 
 412         return ret_val;
 413 }
 414 
 415 /**
 416  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 417  *  @hw: pointer to the HW structure
 418  *
 419  *  Initialize family-specific PHY parameters and function pointers.
 420  **/
 421 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 422 {
 423         struct e1000_phy_info *phy = &hw->phy;
 424         s32 ret_val;
 425 
 426         phy->addr = 1;
 427         phy->reset_delay_us = 100;
 428 
 429         phy->ops.set_page = e1000_set_page_igp;
 430         phy->ops.read_reg = e1000_read_phy_reg_hv;
 431         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 432         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 433         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 434         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 435         phy->ops.write_reg = e1000_write_phy_reg_hv;
 436         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 437         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 438         phy->ops.power_up = e1000_power_up_phy_copper;
 439         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 440         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 441 
 442         phy->id = e1000_phy_unknown;
 443 
 444         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 445         if (ret_val)
 446                 return ret_val;
 447 
 448         if (phy->id == e1000_phy_unknown)
 449                 switch (hw->mac.type) {
 450                 default:
 451                         ret_val = e1000e_get_phy_id(hw);
 452                         if (ret_val)
 453                                 return ret_val;
 454                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 455                                 break;
 456                         /* fall-through */
 457                 case e1000_pch2lan:
 458                 case e1000_pch_lpt:
 459                 case e1000_pch_spt:
 460                 case e1000_pch_cnp:
 461                         /* In case the PHY needs to be in mdio slow mode,
 462                          * set slow mode and try to get the PHY id again.
 463                          */
 464                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 465                         if (ret_val)
 466                                 return ret_val;
 467                         ret_val = e1000e_get_phy_id(hw);
 468                         if (ret_val)
 469                                 return ret_val;
 470                         break;
 471                 }
 472         phy->type = e1000e_get_phy_type_from_id(phy->id);
 473 
 474         switch (phy->type) {
 475         case e1000_phy_82577:
 476         case e1000_phy_82579:
 477         case e1000_phy_i217:
 478                 phy->ops.check_polarity = e1000_check_polarity_82577;
 479                 phy->ops.force_speed_duplex =
 480                     e1000_phy_force_speed_duplex_82577;
 481                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 482                 phy->ops.get_info = e1000_get_phy_info_82577;
 483                 phy->ops.commit = e1000e_phy_sw_reset;
 484                 break;
 485         case e1000_phy_82578:
 486                 phy->ops.check_polarity = e1000_check_polarity_m88;
 487                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 488                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 489                 phy->ops.get_info = e1000e_get_phy_info_m88;
 490                 break;
 491         default:
 492                 ret_val = -E1000_ERR_PHY;
 493                 break;
 494         }
 495 
 496         return ret_val;
 497 }
 498 
 499 /**
 500  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 501  *  @hw: pointer to the HW structure
 502  *
 503  *  Initialize family-specific PHY parameters and function pointers.
 504  **/
 505 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 506 {
 507         struct e1000_phy_info *phy = &hw->phy;
 508         s32 ret_val;
 509         u16 i = 0;
 510 
 511         phy->addr = 1;
 512         phy->reset_delay_us = 100;
 513 
 514         phy->ops.power_up = e1000_power_up_phy_copper;
 515         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 516 
 517         /* We may need to do this twice - once for IGP and if that fails,
 518          * we'll set BM func pointers and try again
 519          */
 520         ret_val = e1000e_determine_phy_address(hw);
 521         if (ret_val) {
 522                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 523                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 524                 ret_val = e1000e_determine_phy_address(hw);
 525                 if (ret_val) {
 526                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 527                         return ret_val;
 528                 }
 529         }
 530 
 531         phy->id = 0;
 532         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 533                (i++ < 100)) {
 534                 usleep_range(1000, 1100);
 535                 ret_val = e1000e_get_phy_id(hw);
 536                 if (ret_val)
 537                         return ret_val;
 538         }
 539 
 540         /* Verify phy id */
 541         switch (phy->id) {
 542         case IGP03E1000_E_PHY_ID:
 543                 phy->type = e1000_phy_igp_3;
 544                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 545                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 546                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 547                 phy->ops.get_info = e1000e_get_phy_info_igp;
 548                 phy->ops.check_polarity = e1000_check_polarity_igp;
 549                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 550                 break;
 551         case IFE_E_PHY_ID:
 552         case IFE_PLUS_E_PHY_ID:
 553         case IFE_C_E_PHY_ID:
 554                 phy->type = e1000_phy_ife;
 555                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 556                 phy->ops.get_info = e1000_get_phy_info_ife;
 557                 phy->ops.check_polarity = e1000_check_polarity_ife;
 558                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 559                 break;
 560         case BME1000_E_PHY_ID:
 561                 phy->type = e1000_phy_bm;
 562                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 563                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 564                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 565                 phy->ops.commit = e1000e_phy_sw_reset;
 566                 phy->ops.get_info = e1000e_get_phy_info_m88;
 567                 phy->ops.check_polarity = e1000_check_polarity_m88;
 568                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 569                 break;
 570         default:
 571                 return -E1000_ERR_PHY;
 572         }
 573 
 574         return 0;
 575 }
 576 
 577 /**
 578  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 579  *  @hw: pointer to the HW structure
 580  *
 581  *  Initialize family-specific NVM parameters and function
 582  *  pointers.
 583  **/
 584 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 585 {
 586         struct e1000_nvm_info *nvm = &hw->nvm;
 587         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 588         u32 gfpreg, sector_base_addr, sector_end_addr;
 589         u16 i;
 590         u32 nvm_size;
 591 
 592         nvm->type = e1000_nvm_flash_sw;
 593 
 594         if (hw->mac.type >= e1000_pch_spt) {
 595                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 596                  * STRAP register. This is because in SPT the GbE Flash region
 597                  * is no longer accessed through the flash registers. Instead,
 598                  * the mechanism has changed, and the Flash region access
 599                  * registers are now implemented in GbE memory space.
 600                  */
 601                 nvm->flash_base_addr = 0;
 602                 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
 603                     * NVM_SIZE_MULTIPLIER;
 604                 nvm->flash_bank_size = nvm_size / 2;
 605                 /* Adjust to word count */
 606                 nvm->flash_bank_size /= sizeof(u16);
 607                 /* Set the base address for flash register access */
 608                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 609         } else {
 610                 /* Can't read flash registers if register set isn't mapped. */
 611                 if (!hw->flash_address) {
 612                         e_dbg("ERROR: Flash registers not mapped\n");
 613                         return -E1000_ERR_CONFIG;
 614                 }
 615 
 616                 gfpreg = er32flash(ICH_FLASH_GFPREG);
 617 
 618                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 619                  * Add 1 to sector_end_addr since this sector is included in
 620                  * the overall size.
 621                  */
 622                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 623                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 624 
 625                 /* flash_base_addr is byte-aligned */
 626                 nvm->flash_base_addr = sector_base_addr
 627                     << FLASH_SECTOR_ADDR_SHIFT;
 628 
 629                 /* find total size of the NVM, then cut in half since the total
 630                  * size represents two separate NVM banks.
 631                  */
 632                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 633                                         << FLASH_SECTOR_ADDR_SHIFT);
 634                 nvm->flash_bank_size /= 2;
 635                 /* Adjust to word count */
 636                 nvm->flash_bank_size /= sizeof(u16);
 637         }
 638 
 639         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 640 
 641         /* Clear shadow ram */
 642         for (i = 0; i < nvm->word_size; i++) {
 643                 dev_spec->shadow_ram[i].modified = false;
 644                 dev_spec->shadow_ram[i].value = 0xFFFF;
 645         }
 646 
 647         return 0;
 648 }
 649 
 650 /**
 651  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 652  *  @hw: pointer to the HW structure
 653  *
 654  *  Initialize family-specific MAC parameters and function
 655  *  pointers.
 656  **/
 657 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 658 {
 659         struct e1000_mac_info *mac = &hw->mac;
 660 
 661         /* Set media type function pointer */
 662         hw->phy.media_type = e1000_media_type_copper;
 663 
 664         /* Set mta register count */
 665         mac->mta_reg_count = 32;
 666         /* Set rar entry count */
 667         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 668         if (mac->type == e1000_ich8lan)
 669                 mac->rar_entry_count--;
 670         /* FWSM register */
 671         mac->has_fwsm = true;
 672         /* ARC subsystem not supported */
 673         mac->arc_subsystem_valid = false;
 674         /* Adaptive IFS supported */
 675         mac->adaptive_ifs = true;
 676 
 677         /* LED and other operations */
 678         switch (mac->type) {
 679         case e1000_ich8lan:
 680         case e1000_ich9lan:
 681         case e1000_ich10lan:
 682                 /* check management mode */
 683                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 684                 /* ID LED init */
 685                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 686                 /* blink LED */
 687                 mac->ops.blink_led = e1000e_blink_led_generic;
 688                 /* setup LED */
 689                 mac->ops.setup_led = e1000e_setup_led_generic;
 690                 /* cleanup LED */
 691                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 692                 /* turn on/off LED */
 693                 mac->ops.led_on = e1000_led_on_ich8lan;
 694                 mac->ops.led_off = e1000_led_off_ich8lan;
 695                 break;
 696         case e1000_pch2lan:
 697                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 698                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 699                 /* fall-through */
 700         case e1000_pch_lpt:
 701         case e1000_pch_spt:
 702         case e1000_pch_cnp:
 703         case e1000_pchlan:
 704                 /* check management mode */
 705                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 706                 /* ID LED init */
 707                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 708                 /* setup LED */
 709                 mac->ops.setup_led = e1000_setup_led_pchlan;
 710                 /* cleanup LED */
 711                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 712                 /* turn on/off LED */
 713                 mac->ops.led_on = e1000_led_on_pchlan;
 714                 mac->ops.led_off = e1000_led_off_pchlan;
 715                 break;
 716         default:
 717                 break;
 718         }
 719 
 720         if (mac->type >= e1000_pch_lpt) {
 721                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 722                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 723                 mac->ops.setup_physical_interface =
 724                     e1000_setup_copper_link_pch_lpt;
 725                 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
 726         }
 727 
 728         /* Enable PCS Lock-loss workaround for ICH8 */
 729         if (mac->type == e1000_ich8lan)
 730                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 731 
 732         return 0;
 733 }
 734 
 735 /**
 736  *  __e1000_access_emi_reg_locked - Read/write EMI register
 737  *  @hw: pointer to the HW structure
 738  *  @addr: EMI address to program
 739  *  @data: pointer to value to read/write from/to the EMI address
 740  *  @read: boolean flag to indicate read or write
 741  *
 742  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 743  **/
 744 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 745                                          u16 *data, bool read)
 746 {
 747         s32 ret_val;
 748 
 749         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 750         if (ret_val)
 751                 return ret_val;
 752 
 753         if (read)
 754                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 755         else
 756                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 757 
 758         return ret_val;
 759 }
 760 
 761 /**
 762  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 763  *  @hw: pointer to the HW structure
 764  *  @addr: EMI address to program
 765  *  @data: value to be read from the EMI address
 766  *
 767  *  Assumes the SW/FW/HW Semaphore is already acquired.
 768  **/
 769 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 770 {
 771         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 772 }
 773 
 774 /**
 775  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 776  *  @hw: pointer to the HW structure
 777  *  @addr: EMI address to program
 778  *  @data: value to be written to the EMI address
 779  *
 780  *  Assumes the SW/FW/HW Semaphore is already acquired.
 781  **/
 782 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 783 {
 784         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 785 }
 786 
 787 /**
 788  *  e1000_set_eee_pchlan - Enable/disable EEE support
 789  *  @hw: pointer to the HW structure
 790  *
 791  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 792  *  the link and the EEE capabilities of the link partner.  The LPI Control
 793  *  register bits will remain set only if/when link is up.
 794  *
 795  *  EEE LPI must not be asserted earlier than one second after link is up.
 796  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 797  *  can be link issues with some switches.  Other devices can have EEE LPI
 798  *  enabled immediately upon link up since they have a timer in hardware which
 799  *  prevents LPI from being asserted too early.
 800  **/
 801 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 802 {
 803         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 804         s32 ret_val;
 805         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 806 
 807         switch (hw->phy.type) {
 808         case e1000_phy_82579:
 809                 lpa = I82579_EEE_LP_ABILITY;
 810                 pcs_status = I82579_EEE_PCS_STATUS;
 811                 adv_addr = I82579_EEE_ADVERTISEMENT;
 812                 break;
 813         case e1000_phy_i217:
 814                 lpa = I217_EEE_LP_ABILITY;
 815                 pcs_status = I217_EEE_PCS_STATUS;
 816                 adv_addr = I217_EEE_ADVERTISEMENT;
 817                 break;
 818         default:
 819                 return 0;
 820         }
 821 
 822         ret_val = hw->phy.ops.acquire(hw);
 823         if (ret_val)
 824                 return ret_val;
 825 
 826         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 827         if (ret_val)
 828                 goto release;
 829 
 830         /* Clear bits that enable EEE in various speeds */
 831         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 832 
 833         /* Enable EEE if not disabled by user */
 834         if (!dev_spec->eee_disable) {
 835                 /* Save off link partner's EEE ability */
 836                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 837                                                     &dev_spec->eee_lp_ability);
 838                 if (ret_val)
 839                         goto release;
 840 
 841                 /* Read EEE advertisement */
 842                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 843                 if (ret_val)
 844                         goto release;
 845 
 846                 /* Enable EEE only for speeds in which the link partner is
 847                  * EEE capable and for which we advertise EEE.
 848                  */
 849                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 850                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 851 
 852                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 853                         e1e_rphy_locked(hw, MII_LPA, &data);
 854                         if (data & LPA_100FULL)
 855                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 856                         else
 857                                 /* EEE is not supported in 100Half, so ignore
 858                                  * partner's EEE in 100 ability if full-duplex
 859                                  * is not advertised.
 860                                  */
 861                                 dev_spec->eee_lp_ability &=
 862                                     ~I82579_EEE_100_SUPPORTED;
 863                 }
 864         }
 865 
 866         if (hw->phy.type == e1000_phy_82579) {
 867                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 868                                                     &data);
 869                 if (ret_val)
 870                         goto release;
 871 
 872                 data &= ~I82579_LPI_100_PLL_SHUT;
 873                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 874                                                      data);
 875         }
 876 
 877         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 878         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 879         if (ret_val)
 880                 goto release;
 881 
 882         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 883 release:
 884         hw->phy.ops.release(hw);
 885 
 886         return ret_val;
 887 }
 888 
 889 /**
 890  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 891  *  @hw:   pointer to the HW structure
 892  *  @link: link up bool flag
 893  *
 894  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 895  *  preventing further DMA write requests.  Workaround the issue by disabling
 896  *  the de-assertion of the clock request when in 1Gpbs mode.
 897  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 898  *  speeds in order to avoid Tx hangs.
 899  **/
 900 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 901 {
 902         u32 fextnvm6 = er32(FEXTNVM6);
 903         u32 status = er32(STATUS);
 904         s32 ret_val = 0;
 905         u16 reg;
 906 
 907         if (link && (status & E1000_STATUS_SPEED_1000)) {
 908                 ret_val = hw->phy.ops.acquire(hw);
 909                 if (ret_val)
 910                         return ret_val;
 911 
 912                 ret_val =
 913                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 914                                                 &reg);
 915                 if (ret_val)
 916                         goto release;
 917 
 918                 ret_val =
 919                     e1000e_write_kmrn_reg_locked(hw,
 920                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 921                                                  reg &
 922                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 923                 if (ret_val)
 924                         goto release;
 925 
 926                 usleep_range(10, 20);
 927 
 928                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 929 
 930                 ret_val =
 931                     e1000e_write_kmrn_reg_locked(hw,
 932                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 933                                                  reg);
 934 release:
 935                 hw->phy.ops.release(hw);
 936         } else {
 937                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 938                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 939 
 940                 if ((hw->phy.revision > 5) || !link ||
 941                     ((status & E1000_STATUS_SPEED_100) &&
 942                      (status & E1000_STATUS_FD)))
 943                         goto update_fextnvm6;
 944 
 945                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 946                 if (ret_val)
 947                         return ret_val;
 948 
 949                 /* Clear link status transmit timeout */
 950                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 951 
 952                 if (status & E1000_STATUS_SPEED_100) {
 953                         /* Set inband Tx timeout to 5x10us for 100Half */
 954                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 955 
 956                         /* Do not extend the K1 entry latency for 100Half */
 957                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 958                 } else {
 959                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 960                         reg |= 50 <<
 961                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 962 
 963                         /* Extend the K1 entry latency for 10 Mbps */
 964                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 965                 }
 966 
 967                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 968                 if (ret_val)
 969                         return ret_val;
 970 
 971 update_fextnvm6:
 972                 ew32(FEXTNVM6, fextnvm6);
 973         }
 974 
 975         return ret_val;
 976 }
 977 
 978 /**
 979  *  e1000_platform_pm_pch_lpt - Set platform power management values
 980  *  @hw: pointer to the HW structure
 981  *  @link: bool indicating link status
 982  *
 983  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 984  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
 985  *  when link is up (which must not exceed the maximum latency supported
 986  *  by the platform), otherwise specify there is no LTR requirement.
 987  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
 988  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
 989  *  Capability register set, on this device LTR is set by writing the
 990  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
 991  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
 992  *  message to the PMC.
 993  **/
 994 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
 995 {
 996         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
 997             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
 998         u16 lat_enc = 0;        /* latency encoded */
 999 
1000         if (link) {
1001                 u16 speed, duplex, scale = 0;
1002                 u16 max_snoop, max_nosnoop;
1003                 u16 max_ltr_enc;        /* max LTR latency encoded */
1004                 u64 value;
1005                 u32 rxa;
1006 
1007                 if (!hw->adapter->max_frame_size) {
1008                         e_dbg("max_frame_size not set.\n");
1009                         return -E1000_ERR_CONFIG;
1010                 }
1011 
1012                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1013                 if (!speed) {
1014                         e_dbg("Speed not set.\n");
1015                         return -E1000_ERR_CONFIG;
1016                 }
1017 
1018                 /* Rx Packet Buffer Allocation size (KB) */
1019                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1020 
1021                 /* Determine the maximum latency tolerated by the device.
1022                  *
1023                  * Per the PCIe spec, the tolerated latencies are encoded as
1024                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1025                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1026                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1027                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1028                  */
1029                 rxa *= 512;
1030                 value = (rxa > hw->adapter->max_frame_size) ?
1031                         (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1032                         0;
1033 
1034                 while (value > PCI_LTR_VALUE_MASK) {
1035                         scale++;
1036                         value = DIV_ROUND_UP(value, BIT(5));
1037                 }
1038                 if (scale > E1000_LTRV_SCALE_MAX) {
1039                         e_dbg("Invalid LTR latency scale %d\n", scale);
1040                         return -E1000_ERR_CONFIG;
1041                 }
1042                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1043 
1044                 /* Determine the maximum latency tolerated by the platform */
1045                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1046                                      &max_snoop);
1047                 pci_read_config_word(hw->adapter->pdev,
1048                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1049                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1050 
1051                 if (lat_enc > max_ltr_enc)
1052                         lat_enc = max_ltr_enc;
1053         }
1054 
1055         /* Set Snoop and No-Snoop latencies the same */
1056         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1057         ew32(LTRV, reg);
1058 
1059         return 0;
1060 }
1061 
1062 /**
1063  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1064  *  @hw: pointer to the HW structure
1065  *  @to_sx: boolean indicating a system power state transition to Sx
1066  *
1067  *  When link is down, configure ULP mode to significantly reduce the power
1068  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1069  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1070  *  system, configure the ULP mode by software.
1071  */
1072 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1073 {
1074         u32 mac_reg;
1075         s32 ret_val = 0;
1076         u16 phy_reg;
1077         u16 oem_reg = 0;
1078 
1079         if ((hw->mac.type < e1000_pch_lpt) ||
1080             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1081             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1082             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1083             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1084             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1085                 return 0;
1086 
1087         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1088                 /* Request ME configure ULP mode in the PHY */
1089                 mac_reg = er32(H2ME);
1090                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1091                 ew32(H2ME, mac_reg);
1092 
1093                 goto out;
1094         }
1095 
1096         if (!to_sx) {
1097                 int i = 0;
1098 
1099                 /* Poll up to 5 seconds for Cable Disconnected indication */
1100                 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1101                         /* Bail if link is re-acquired */
1102                         if (er32(STATUS) & E1000_STATUS_LU)
1103                                 return -E1000_ERR_PHY;
1104 
1105                         if (i++ == 100)
1106                                 break;
1107 
1108                         msleep(50);
1109                 }
1110                 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1111                       (er32(FEXT) &
1112                        E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1113         }
1114 
1115         ret_val = hw->phy.ops.acquire(hw);
1116         if (ret_val)
1117                 goto out;
1118 
1119         /* Force SMBus mode in PHY */
1120         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1121         if (ret_val)
1122                 goto release;
1123         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1124         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1125 
1126         /* Force SMBus mode in MAC */
1127         mac_reg = er32(CTRL_EXT);
1128         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1129         ew32(CTRL_EXT, mac_reg);
1130 
1131         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1132          * LPLU and disable Gig speed when entering ULP
1133          */
1134         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1135                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1136                                                        &oem_reg);
1137                 if (ret_val)
1138                         goto release;
1139 
1140                 phy_reg = oem_reg;
1141                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1142 
1143                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1144                                                         phy_reg);
1145 
1146                 if (ret_val)
1147                         goto release;
1148         }
1149 
1150         /* Set Inband ULP Exit, Reset to SMBus mode and
1151          * Disable SMBus Release on PERST# in PHY
1152          */
1153         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1154         if (ret_val)
1155                 goto release;
1156         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1157                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1158         if (to_sx) {
1159                 if (er32(WUFC) & E1000_WUFC_LNKC)
1160                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1161                 else
1162                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1163 
1164                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1165                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1166         } else {
1167                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1168                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1169                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1170         }
1171         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1172 
1173         /* Set Disable SMBus Release on PERST# in MAC */
1174         mac_reg = er32(FEXTNVM7);
1175         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1176         ew32(FEXTNVM7, mac_reg);
1177 
1178         /* Commit ULP changes in PHY by starting auto ULP configuration */
1179         phy_reg |= I218_ULP_CONFIG1_START;
1180         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1181 
1182         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1183             to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1184                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1185                                                         oem_reg);
1186                 if (ret_val)
1187                         goto release;
1188         }
1189 
1190 release:
1191         hw->phy.ops.release(hw);
1192 out:
1193         if (ret_val)
1194                 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1195         else
1196                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1197 
1198         return ret_val;
1199 }
1200 
1201 /**
1202  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1203  *  @hw: pointer to the HW structure
1204  *  @force: boolean indicating whether or not to force disabling ULP
1205  *
1206  *  Un-configure ULP mode when link is up, the system is transitioned from
1207  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1208  *  system, poll for an indication from ME that ULP has been un-configured.
1209  *  If not on an ME enabled system, un-configure the ULP mode by software.
1210  *
1211  *  During nominal operation, this function is called when link is acquired
1212  *  to disable ULP mode (force=false); otherwise, for example when unloading
1213  *  the driver or during Sx->S0 transitions, this is called with force=true
1214  *  to forcibly disable ULP.
1215  */
1216 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1217 {
1218         s32 ret_val = 0;
1219         u32 mac_reg;
1220         u16 phy_reg;
1221         int i = 0;
1222 
1223         if ((hw->mac.type < e1000_pch_lpt) ||
1224             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1225             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1226             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1227             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1228             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1229                 return 0;
1230 
1231         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1232                 if (force) {
1233                         /* Request ME un-configure ULP mode in the PHY */
1234                         mac_reg = er32(H2ME);
1235                         mac_reg &= ~E1000_H2ME_ULP;
1236                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1237                         ew32(H2ME, mac_reg);
1238                 }
1239 
1240                 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1241                 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1242                         if (i++ == 30) {
1243                                 ret_val = -E1000_ERR_PHY;
1244                                 goto out;
1245                         }
1246 
1247                         usleep_range(10000, 11000);
1248                 }
1249                 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1250 
1251                 if (force) {
1252                         mac_reg = er32(H2ME);
1253                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1254                         ew32(H2ME, mac_reg);
1255                 } else {
1256                         /* Clear H2ME.ULP after ME ULP configuration */
1257                         mac_reg = er32(H2ME);
1258                         mac_reg &= ~E1000_H2ME_ULP;
1259                         ew32(H2ME, mac_reg);
1260                 }
1261 
1262                 goto out;
1263         }
1264 
1265         ret_val = hw->phy.ops.acquire(hw);
1266         if (ret_val)
1267                 goto out;
1268 
1269         if (force)
1270                 /* Toggle LANPHYPC Value bit */
1271                 e1000_toggle_lanphypc_pch_lpt(hw);
1272 
1273         /* Unforce SMBus mode in PHY */
1274         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1275         if (ret_val) {
1276                 /* The MAC might be in PCIe mode, so temporarily force to
1277                  * SMBus mode in order to access the PHY.
1278                  */
1279                 mac_reg = er32(CTRL_EXT);
1280                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1281                 ew32(CTRL_EXT, mac_reg);
1282 
1283                 msleep(50);
1284 
1285                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1286                                                        &phy_reg);
1287                 if (ret_val)
1288                         goto release;
1289         }
1290         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1291         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1292 
1293         /* Unforce SMBus mode in MAC */
1294         mac_reg = er32(CTRL_EXT);
1295         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1296         ew32(CTRL_EXT, mac_reg);
1297 
1298         /* When ULP mode was previously entered, K1 was disabled by the
1299          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1300          */
1301         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1302         if (ret_val)
1303                 goto release;
1304         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1305         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1306 
1307         /* Clear ULP enabled configuration */
1308         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1309         if (ret_val)
1310                 goto release;
1311         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1312                      I218_ULP_CONFIG1_STICKY_ULP |
1313                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1314                      I218_ULP_CONFIG1_WOL_HOST |
1315                      I218_ULP_CONFIG1_INBAND_EXIT |
1316                      I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1317                      I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1318                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1319         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1320 
1321         /* Commit ULP changes by starting auto ULP configuration */
1322         phy_reg |= I218_ULP_CONFIG1_START;
1323         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1324 
1325         /* Clear Disable SMBus Release on PERST# in MAC */
1326         mac_reg = er32(FEXTNVM7);
1327         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1328         ew32(FEXTNVM7, mac_reg);
1329 
1330 release:
1331         hw->phy.ops.release(hw);
1332         if (force) {
1333                 e1000_phy_hw_reset(hw);
1334                 msleep(50);
1335         }
1336 out:
1337         if (ret_val)
1338                 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1339         else
1340                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1341 
1342         return ret_val;
1343 }
1344 
1345 /**
1346  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1347  *  @hw: pointer to the HW structure
1348  *
1349  *  Checks to see of the link status of the hardware has changed.  If a
1350  *  change in link status has been detected, then we read the PHY registers
1351  *  to get the current speed/duplex if link exists.
1352  **/
1353 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1354 {
1355         struct e1000_mac_info *mac = &hw->mac;
1356         s32 ret_val, tipg_reg = 0;
1357         u16 emi_addr, emi_val = 0;
1358         bool link;
1359         u16 phy_reg;
1360 
1361         /* We only want to go out to the PHY registers to see if Auto-Neg
1362          * has completed and/or if our link status has changed.  The
1363          * get_link_status flag is set upon receiving a Link Status
1364          * Change or Rx Sequence Error interrupt.
1365          */
1366         if (!mac->get_link_status)
1367                 return 0;
1368         mac->get_link_status = false;
1369 
1370         /* First we want to see if the MII Status Register reports
1371          * link.  If so, then we want to get the current speed/duplex
1372          * of the PHY.
1373          */
1374         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1375         if (ret_val)
1376                 goto out;
1377 
1378         if (hw->mac.type == e1000_pchlan) {
1379                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1380                 if (ret_val)
1381                         goto out;
1382         }
1383 
1384         /* When connected at 10Mbps half-duplex, some parts are excessively
1385          * aggressive resulting in many collisions. To avoid this, increase
1386          * the IPG and reduce Rx latency in the PHY.
1387          */
1388         if ((hw->mac.type >= e1000_pch2lan) && link) {
1389                 u16 speed, duplex;
1390 
1391                 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1392                 tipg_reg = er32(TIPG);
1393                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1394 
1395                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1396                         tipg_reg |= 0xFF;
1397                         /* Reduce Rx latency in analog PHY */
1398                         emi_val = 0;
1399                 } else if (hw->mac.type >= e1000_pch_spt &&
1400                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1401                         tipg_reg |= 0xC;
1402                         emi_val = 1;
1403                 } else {
1404 
1405                         /* Roll back the default values */
1406                         tipg_reg |= 0x08;
1407                         emi_val = 1;
1408                 }
1409 
1410                 ew32(TIPG, tipg_reg);
1411 
1412                 ret_val = hw->phy.ops.acquire(hw);
1413                 if (ret_val)
1414                         goto out;
1415 
1416                 if (hw->mac.type == e1000_pch2lan)
1417                         emi_addr = I82579_RX_CONFIG;
1418                 else
1419                         emi_addr = I217_RX_CONFIG;
1420                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1421 
1422                 if (hw->mac.type >= e1000_pch_lpt) {
1423                         u16 phy_reg;
1424 
1425                         e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1426                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1427                         if (speed == SPEED_100 || speed == SPEED_10)
1428                                 phy_reg |= 0x3E8;
1429                         else
1430                                 phy_reg |= 0xFA;
1431                         e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1432 
1433                         if (speed == SPEED_1000) {
1434                                 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1435                                                             &phy_reg);
1436 
1437                                 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1438 
1439                                 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1440                                                              phy_reg);
1441                         }
1442                 }
1443                 hw->phy.ops.release(hw);
1444 
1445                 if (ret_val)
1446                         goto out;
1447 
1448                 if (hw->mac.type >= e1000_pch_spt) {
1449                         u16 data;
1450                         u16 ptr_gap;
1451 
1452                         if (speed == SPEED_1000) {
1453                                 ret_val = hw->phy.ops.acquire(hw);
1454                                 if (ret_val)
1455                                         goto out;
1456 
1457                                 ret_val = e1e_rphy_locked(hw,
1458                                                           PHY_REG(776, 20),
1459                                                           &data);
1460                                 if (ret_val) {
1461                                         hw->phy.ops.release(hw);
1462                                         goto out;
1463                                 }
1464 
1465                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1466                                 if (ptr_gap < 0x18) {
1467                                         data &= ~(0x3FF << 2);
1468                                         data |= (0x18 << 2);
1469                                         ret_val =
1470                                             e1e_wphy_locked(hw,
1471                                                             PHY_REG(776, 20),
1472                                                             data);
1473                                 }
1474                                 hw->phy.ops.release(hw);
1475                                 if (ret_val)
1476                                         goto out;
1477                         } else {
1478                                 ret_val = hw->phy.ops.acquire(hw);
1479                                 if (ret_val)
1480                                         goto out;
1481 
1482                                 ret_val = e1e_wphy_locked(hw,
1483                                                           PHY_REG(776, 20),
1484                                                           0xC023);
1485                                 hw->phy.ops.release(hw);
1486                                 if (ret_val)
1487                                         goto out;
1488 
1489                         }
1490                 }
1491         }
1492 
1493         /* I217 Packet Loss issue:
1494          * ensure that FEXTNVM4 Beacon Duration is set correctly
1495          * on power up.
1496          * Set the Beacon Duration for I217 to 8 usec
1497          */
1498         if (hw->mac.type >= e1000_pch_lpt) {
1499                 u32 mac_reg;
1500 
1501                 mac_reg = er32(FEXTNVM4);
1502                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1503                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1504                 ew32(FEXTNVM4, mac_reg);
1505         }
1506 
1507         /* Work-around I218 hang issue */
1508         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1509             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1510             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1511             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1512                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1513                 if (ret_val)
1514                         goto out;
1515         }
1516         if (hw->mac.type >= e1000_pch_lpt) {
1517                 /* Set platform power management values for
1518                  * Latency Tolerance Reporting (LTR)
1519                  */
1520                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1521                 if (ret_val)
1522                         goto out;
1523         }
1524 
1525         /* Clear link partner's EEE ability */
1526         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1527 
1528         if (hw->mac.type >= e1000_pch_lpt) {
1529                 u32 fextnvm6 = er32(FEXTNVM6);
1530 
1531                 if (hw->mac.type == e1000_pch_spt) {
1532                         /* FEXTNVM6 K1-off workaround - for SPT only */
1533                         u32 pcieanacfg = er32(PCIEANACFG);
1534 
1535                         if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1536                                 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1537                         else
1538                                 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1539                 }
1540 
1541                 ew32(FEXTNVM6, fextnvm6);
1542         }
1543 
1544         if (!link)
1545                 goto out;
1546 
1547         switch (hw->mac.type) {
1548         case e1000_pch2lan:
1549                 ret_val = e1000_k1_workaround_lv(hw);
1550                 if (ret_val)
1551                         return ret_val;
1552                 /* fall-thru */
1553         case e1000_pchlan:
1554                 if (hw->phy.type == e1000_phy_82578) {
1555                         ret_val = e1000_link_stall_workaround_hv(hw);
1556                         if (ret_val)
1557                                 return ret_val;
1558                 }
1559 
1560                 /* Workaround for PCHx parts in half-duplex:
1561                  * Set the number of preambles removed from the packet
1562                  * when it is passed from the PHY to the MAC to prevent
1563                  * the MAC from misinterpreting the packet type.
1564                  */
1565                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1566                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1567 
1568                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1569                         phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1570 
1571                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1572                 break;
1573         default:
1574                 break;
1575         }
1576 
1577         /* Check if there was DownShift, must be checked
1578          * immediately after link-up
1579          */
1580         e1000e_check_downshift(hw);
1581 
1582         /* Enable/Disable EEE after link up */
1583         if (hw->phy.type > e1000_phy_82579) {
1584                 ret_val = e1000_set_eee_pchlan(hw);
1585                 if (ret_val)
1586                         return ret_val;
1587         }
1588 
1589         /* If we are forcing speed/duplex, then we simply return since
1590          * we have already determined whether we have link or not.
1591          */
1592         if (!mac->autoneg)
1593                 return -E1000_ERR_CONFIG;
1594 
1595         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1596          * of MAC speed/duplex configuration.  So we only need to
1597          * configure Collision Distance in the MAC.
1598          */
1599         mac->ops.config_collision_dist(hw);
1600 
1601         /* Configure Flow Control now that Auto-Neg has completed.
1602          * First, we need to restore the desired flow control
1603          * settings because we may have had to re-autoneg with a
1604          * different link partner.
1605          */
1606         ret_val = e1000e_config_fc_after_link_up(hw);
1607         if (ret_val)
1608                 e_dbg("Error configuring flow control\n");
1609 
1610         return ret_val;
1611 
1612 out:
1613         mac->get_link_status = true;
1614         return ret_val;
1615 }
1616 
1617 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1618 {
1619         struct e1000_hw *hw = &adapter->hw;
1620         s32 rc;
1621 
1622         rc = e1000_init_mac_params_ich8lan(hw);
1623         if (rc)
1624                 return rc;
1625 
1626         rc = e1000_init_nvm_params_ich8lan(hw);
1627         if (rc)
1628                 return rc;
1629 
1630         switch (hw->mac.type) {
1631         case e1000_ich8lan:
1632         case e1000_ich9lan:
1633         case e1000_ich10lan:
1634                 rc = e1000_init_phy_params_ich8lan(hw);
1635                 break;
1636         case e1000_pchlan:
1637         case e1000_pch2lan:
1638         case e1000_pch_lpt:
1639         case e1000_pch_spt:
1640         case e1000_pch_cnp:
1641                 rc = e1000_init_phy_params_pchlan(hw);
1642                 break;
1643         default:
1644                 break;
1645         }
1646         if (rc)
1647                 return rc;
1648 
1649         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1650          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1651          */
1652         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1653             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1654              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1655                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1656                 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1657 
1658                 hw->mac.ops.blink_led = NULL;
1659         }
1660 
1661         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1662             (adapter->hw.phy.type != e1000_phy_ife))
1663                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1664 
1665         /* Enable workaround for 82579 w/ ME enabled */
1666         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1667             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1668                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1669 
1670         return 0;
1671 }
1672 
1673 static DEFINE_MUTEX(nvm_mutex);
1674 
1675 /**
1676  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1677  *  @hw: pointer to the HW structure
1678  *
1679  *  Acquires the mutex for performing NVM operations.
1680  **/
1681 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1682 {
1683         mutex_lock(&nvm_mutex);
1684 
1685         return 0;
1686 }
1687 
1688 /**
1689  *  e1000_release_nvm_ich8lan - Release NVM mutex
1690  *  @hw: pointer to the HW structure
1691  *
1692  *  Releases the mutex used while performing NVM operations.
1693  **/
1694 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1695 {
1696         mutex_unlock(&nvm_mutex);
1697 }
1698 
1699 /**
1700  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1701  *  @hw: pointer to the HW structure
1702  *
1703  *  Acquires the software control flag for performing PHY and select
1704  *  MAC CSR accesses.
1705  **/
1706 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1707 {
1708         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1709         s32 ret_val = 0;
1710 
1711         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1712                              &hw->adapter->state)) {
1713                 e_dbg("contention for Phy access\n");
1714                 return -E1000_ERR_PHY;
1715         }
1716 
1717         while (timeout) {
1718                 extcnf_ctrl = er32(EXTCNF_CTRL);
1719                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1720                         break;
1721 
1722                 mdelay(1);
1723                 timeout--;
1724         }
1725 
1726         if (!timeout) {
1727                 e_dbg("SW has already locked the resource.\n");
1728                 ret_val = -E1000_ERR_CONFIG;
1729                 goto out;
1730         }
1731 
1732         timeout = SW_FLAG_TIMEOUT;
1733 
1734         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1735         ew32(EXTCNF_CTRL, extcnf_ctrl);
1736 
1737         while (timeout) {
1738                 extcnf_ctrl = er32(EXTCNF_CTRL);
1739                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1740                         break;
1741 
1742                 mdelay(1);
1743                 timeout--;
1744         }
1745 
1746         if (!timeout) {
1747                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1748                       er32(FWSM), extcnf_ctrl);
1749                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1750                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1751                 ret_val = -E1000_ERR_CONFIG;
1752                 goto out;
1753         }
1754 
1755 out:
1756         if (ret_val)
1757                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1758 
1759         return ret_val;
1760 }
1761 
1762 /**
1763  *  e1000_release_swflag_ich8lan - Release software control flag
1764  *  @hw: pointer to the HW structure
1765  *
1766  *  Releases the software control flag for performing PHY and select
1767  *  MAC CSR accesses.
1768  **/
1769 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1770 {
1771         u32 extcnf_ctrl;
1772 
1773         extcnf_ctrl = er32(EXTCNF_CTRL);
1774 
1775         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1776                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1777                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1778         } else {
1779                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1780         }
1781 
1782         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1783 }
1784 
1785 /**
1786  *  e1000_check_mng_mode_ich8lan - Checks management mode
1787  *  @hw: pointer to the HW structure
1788  *
1789  *  This checks if the adapter has any manageability enabled.
1790  *  This is a function pointer entry point only called by read/write
1791  *  routines for the PHY and NVM parts.
1792  **/
1793 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1794 {
1795         u32 fwsm;
1796 
1797         fwsm = er32(FWSM);
1798         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1799                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1800                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1801 }
1802 
1803 /**
1804  *  e1000_check_mng_mode_pchlan - Checks management mode
1805  *  @hw: pointer to the HW structure
1806  *
1807  *  This checks if the adapter has iAMT enabled.
1808  *  This is a function pointer entry point only called by read/write
1809  *  routines for the PHY and NVM parts.
1810  **/
1811 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1812 {
1813         u32 fwsm;
1814 
1815         fwsm = er32(FWSM);
1816         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1817             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1818 }
1819 
1820 /**
1821  *  e1000_rar_set_pch2lan - Set receive address register
1822  *  @hw: pointer to the HW structure
1823  *  @addr: pointer to the receive address
1824  *  @index: receive address array register
1825  *
1826  *  Sets the receive address array register at index to the address passed
1827  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1828  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1829  *  Use SHRA[0-3] in place of those reserved for ME.
1830  **/
1831 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1832 {
1833         u32 rar_low, rar_high;
1834 
1835         /* HW expects these in little endian so we reverse the byte order
1836          * from network order (big endian) to little endian
1837          */
1838         rar_low = ((u32)addr[0] |
1839                    ((u32)addr[1] << 8) |
1840                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1841 
1842         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1843 
1844         /* If MAC address zero, no need to set the AV bit */
1845         if (rar_low || rar_high)
1846                 rar_high |= E1000_RAH_AV;
1847 
1848         if (index == 0) {
1849                 ew32(RAL(index), rar_low);
1850                 e1e_flush();
1851                 ew32(RAH(index), rar_high);
1852                 e1e_flush();
1853                 return 0;
1854         }
1855 
1856         /* RAR[1-6] are owned by manageability.  Skip those and program the
1857          * next address into the SHRA register array.
1858          */
1859         if (index < (u32)(hw->mac.rar_entry_count)) {
1860                 s32 ret_val;
1861 
1862                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1863                 if (ret_val)
1864                         goto out;
1865 
1866                 ew32(SHRAL(index - 1), rar_low);
1867                 e1e_flush();
1868                 ew32(SHRAH(index - 1), rar_high);
1869                 e1e_flush();
1870 
1871                 e1000_release_swflag_ich8lan(hw);
1872 
1873                 /* verify the register updates */
1874                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1875                     (er32(SHRAH(index - 1)) == rar_high))
1876                         return 0;
1877 
1878                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1879                       (index - 1), er32(FWSM));
1880         }
1881 
1882 out:
1883         e_dbg("Failed to write receive address at index %d\n", index);
1884         return -E1000_ERR_CONFIG;
1885 }
1886 
1887 /**
1888  *  e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1889  *  @hw: pointer to the HW structure
1890  *
1891  *  Get the number of available receive registers that the Host can
1892  *  program. SHRA[0-10] are the shared receive address registers
1893  *  that are shared between the Host and manageability engine (ME).
1894  *  ME can reserve any number of addresses and the host needs to be
1895  *  able to tell how many available registers it has access to.
1896  **/
1897 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1898 {
1899         u32 wlock_mac;
1900         u32 num_entries;
1901 
1902         wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1903         wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1904 
1905         switch (wlock_mac) {
1906         case 0:
1907                 /* All SHRA[0..10] and RAR[0] available */
1908                 num_entries = hw->mac.rar_entry_count;
1909                 break;
1910         case 1:
1911                 /* Only RAR[0] available */
1912                 num_entries = 1;
1913                 break;
1914         default:
1915                 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1916                 num_entries = wlock_mac + 1;
1917                 break;
1918         }
1919 
1920         return num_entries;
1921 }
1922 
1923 /**
1924  *  e1000_rar_set_pch_lpt - Set receive address registers
1925  *  @hw: pointer to the HW structure
1926  *  @addr: pointer to the receive address
1927  *  @index: receive address array register
1928  *
1929  *  Sets the receive address register array at index to the address passed
1930  *  in by addr. For LPT, RAR[0] is the base address register that is to
1931  *  contain the MAC address. SHRA[0-10] are the shared receive address
1932  *  registers that are shared between the Host and manageability engine (ME).
1933  **/
1934 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1935 {
1936         u32 rar_low, rar_high;
1937         u32 wlock_mac;
1938 
1939         /* HW expects these in little endian so we reverse the byte order
1940          * from network order (big endian) to little endian
1941          */
1942         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1943                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1944 
1945         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1946 
1947         /* If MAC address zero, no need to set the AV bit */
1948         if (rar_low || rar_high)
1949                 rar_high |= E1000_RAH_AV;
1950 
1951         if (index == 0) {
1952                 ew32(RAL(index), rar_low);
1953                 e1e_flush();
1954                 ew32(RAH(index), rar_high);
1955                 e1e_flush();
1956                 return 0;
1957         }
1958 
1959         /* The manageability engine (ME) can lock certain SHRAR registers that
1960          * it is using - those registers are unavailable for use.
1961          */
1962         if (index < hw->mac.rar_entry_count) {
1963                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1964                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1965 
1966                 /* Check if all SHRAR registers are locked */
1967                 if (wlock_mac == 1)
1968                         goto out;
1969 
1970                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1971                         s32 ret_val;
1972 
1973                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1974 
1975                         if (ret_val)
1976                                 goto out;
1977 
1978                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1979                         e1e_flush();
1980                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1981                         e1e_flush();
1982 
1983                         e1000_release_swflag_ich8lan(hw);
1984 
1985                         /* verify the register updates */
1986                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1987                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1988                                 return 0;
1989                 }
1990         }
1991 
1992 out:
1993         e_dbg("Failed to write receive address at index %d\n", index);
1994         return -E1000_ERR_CONFIG;
1995 }
1996 
1997 /**
1998  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1999  *  @hw: pointer to the HW structure
2000  *
2001  *  Checks if firmware is blocking the reset of the PHY.
2002  *  This is a function pointer entry point only called by
2003  *  reset routines.
2004  **/
2005 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2006 {
2007         bool blocked = false;
2008         int i = 0;
2009 
2010         while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2011                (i++ < 30))
2012                 usleep_range(10000, 11000);
2013         return blocked ? E1000_BLK_PHY_RESET : 0;
2014 }
2015 
2016 /**
2017  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2018  *  @hw: pointer to the HW structure
2019  *
2020  *  Assumes semaphore already acquired.
2021  *
2022  **/
2023 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2024 {
2025         u16 phy_data;
2026         u32 strap = er32(STRAP);
2027         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2028             E1000_STRAP_SMT_FREQ_SHIFT;
2029         s32 ret_val;
2030 
2031         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2032 
2033         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2034         if (ret_val)
2035                 return ret_val;
2036 
2037         phy_data &= ~HV_SMB_ADDR_MASK;
2038         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2039         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2040 
2041         if (hw->phy.type == e1000_phy_i217) {
2042                 /* Restore SMBus frequency */
2043                 if (freq--) {
2044                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2045                         phy_data |= (freq & BIT(0)) <<
2046                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
2047                         phy_data |= (freq & BIT(1)) <<
2048                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2049                 } else {
2050                         e_dbg("Unsupported SMB frequency in PHY\n");
2051                 }
2052         }
2053 
2054         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2055 }
2056 
2057 /**
2058  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2059  *  @hw:   pointer to the HW structure
2060  *
2061  *  SW should configure the LCD from the NVM extended configuration region
2062  *  as a workaround for certain parts.
2063  **/
2064 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2065 {
2066         struct e1000_phy_info *phy = &hw->phy;
2067         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2068         s32 ret_val = 0;
2069         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2070 
2071         /* Initialize the PHY from the NVM on ICH platforms.  This
2072          * is needed due to an issue where the NVM configuration is
2073          * not properly autoloaded after power transitions.
2074          * Therefore, after each PHY reset, we will load the
2075          * configuration data out of the NVM manually.
2076          */
2077         switch (hw->mac.type) {
2078         case e1000_ich8lan:
2079                 if (phy->type != e1000_phy_igp_3)
2080                         return ret_val;
2081 
2082                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2083                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2084                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2085                         break;
2086                 }
2087                 /* Fall-thru */
2088         case e1000_pchlan:
2089         case e1000_pch2lan:
2090         case e1000_pch_lpt:
2091         case e1000_pch_spt:
2092         case e1000_pch_cnp:
2093                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2094                 break;
2095         default:
2096                 return ret_val;
2097         }
2098 
2099         ret_val = hw->phy.ops.acquire(hw);
2100         if (ret_val)
2101                 return ret_val;
2102 
2103         data = er32(FEXTNVM);
2104         if (!(data & sw_cfg_mask))
2105                 goto release;
2106 
2107         /* Make sure HW does not configure LCD from PHY
2108          * extended configuration before SW configuration
2109          */
2110         data = er32(EXTCNF_CTRL);
2111         if ((hw->mac.type < e1000_pch2lan) &&
2112             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2113                 goto release;
2114 
2115         cnf_size = er32(EXTCNF_SIZE);
2116         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2117         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2118         if (!cnf_size)
2119                 goto release;
2120 
2121         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2122         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2123 
2124         if (((hw->mac.type == e1000_pchlan) &&
2125              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2126             (hw->mac.type > e1000_pchlan)) {
2127                 /* HW configures the SMBus address and LEDs when the
2128                  * OEM and LCD Write Enable bits are set in the NVM.
2129                  * When both NVM bits are cleared, SW will configure
2130                  * them instead.
2131                  */
2132                 ret_val = e1000_write_smbus_addr(hw);
2133                 if (ret_val)
2134                         goto release;
2135 
2136                 data = er32(LEDCTL);
2137                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2138                                                         (u16)data);
2139                 if (ret_val)
2140                         goto release;
2141         }
2142 
2143         /* Configure LCD from extended configuration region. */
2144 
2145         /* cnf_base_addr is in DWORD */
2146         word_addr = (u16)(cnf_base_addr << 1);
2147 
2148         for (i = 0; i < cnf_size; i++) {
2149                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2150                 if (ret_val)
2151                         goto release;
2152 
2153                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2154                                          1, &reg_addr);
2155                 if (ret_val)
2156                         goto release;
2157 
2158                 /* Save off the PHY page for future writes. */
2159                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2160                         phy_page = reg_data;
2161                         continue;
2162                 }
2163 
2164                 reg_addr &= PHY_REG_MASK;
2165                 reg_addr |= phy_page;
2166 
2167                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2168                 if (ret_val)
2169                         goto release;
2170         }
2171 
2172 release:
2173         hw->phy.ops.release(hw);
2174         return ret_val;
2175 }
2176 
2177 /**
2178  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2179  *  @hw:   pointer to the HW structure
2180  *  @link: link up bool flag
2181  *
2182  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2183  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2184  *  If link is down, the function will restore the default K1 setting located
2185  *  in the NVM.
2186  **/
2187 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2188 {
2189         s32 ret_val = 0;
2190         u16 status_reg = 0;
2191         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2192 
2193         if (hw->mac.type != e1000_pchlan)
2194                 return 0;
2195 
2196         /* Wrap the whole flow with the sw flag */
2197         ret_val = hw->phy.ops.acquire(hw);
2198         if (ret_val)
2199                 return ret_val;
2200 
2201         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2202         if (link) {
2203                 if (hw->phy.type == e1000_phy_82578) {
2204                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2205                                                   &status_reg);
2206                         if (ret_val)
2207                                 goto release;
2208 
2209                         status_reg &= (BM_CS_STATUS_LINK_UP |
2210                                        BM_CS_STATUS_RESOLVED |
2211                                        BM_CS_STATUS_SPEED_MASK);
2212 
2213                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2214                                            BM_CS_STATUS_RESOLVED |
2215                                            BM_CS_STATUS_SPEED_1000))
2216                                 k1_enable = false;
2217                 }
2218 
2219                 if (hw->phy.type == e1000_phy_82577) {
2220                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2221                         if (ret_val)
2222                                 goto release;
2223 
2224                         status_reg &= (HV_M_STATUS_LINK_UP |
2225                                        HV_M_STATUS_AUTONEG_COMPLETE |
2226                                        HV_M_STATUS_SPEED_MASK);
2227 
2228                         if (status_reg == (HV_M_STATUS_LINK_UP |
2229                                            HV_M_STATUS_AUTONEG_COMPLETE |
2230                                            HV_M_STATUS_SPEED_1000))
2231                                 k1_enable = false;
2232                 }
2233 
2234                 /* Link stall fix for link up */
2235                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2236                 if (ret_val)
2237                         goto release;
2238 
2239         } else {
2240                 /* Link stall fix for link down */
2241                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2242                 if (ret_val)
2243                         goto release;
2244         }
2245 
2246         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2247 
2248 release:
2249         hw->phy.ops.release(hw);
2250 
2251         return ret_val;
2252 }
2253 
2254 /**
2255  *  e1000_configure_k1_ich8lan - Configure K1 power state
2256  *  @hw: pointer to the HW structure
2257  *  @enable: K1 state to configure
2258  *
2259  *  Configure the K1 power state based on the provided parameter.
2260  *  Assumes semaphore already acquired.
2261  *
2262  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2263  **/
2264 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2265 {
2266         s32 ret_val;
2267         u32 ctrl_reg = 0;
2268         u32 ctrl_ext = 0;
2269         u32 reg = 0;
2270         u16 kmrn_reg = 0;
2271 
2272         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2273                                               &kmrn_reg);
2274         if (ret_val)
2275                 return ret_val;
2276 
2277         if (k1_enable)
2278                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2279         else
2280                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2281 
2282         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2283                                                kmrn_reg);
2284         if (ret_val)
2285                 return ret_val;
2286 
2287         usleep_range(20, 40);
2288         ctrl_ext = er32(CTRL_EXT);
2289         ctrl_reg = er32(CTRL);
2290 
2291         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2292         reg |= E1000_CTRL_FRCSPD;
2293         ew32(CTRL, reg);
2294 
2295         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2296         e1e_flush();
2297         usleep_range(20, 40);
2298         ew32(CTRL, ctrl_reg);
2299         ew32(CTRL_EXT, ctrl_ext);
2300         e1e_flush();
2301         usleep_range(20, 40);
2302 
2303         return 0;
2304 }
2305 
2306 /**
2307  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2308  *  @hw:       pointer to the HW structure
2309  *  @d0_state: boolean if entering d0 or d3 device state
2310  *
2311  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2312  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2313  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2314  **/
2315 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2316 {
2317         s32 ret_val = 0;
2318         u32 mac_reg;
2319         u16 oem_reg;
2320 
2321         if (hw->mac.type < e1000_pchlan)
2322                 return ret_val;
2323 
2324         ret_val = hw->phy.ops.acquire(hw);
2325         if (ret_val)
2326                 return ret_val;
2327 
2328         if (hw->mac.type == e1000_pchlan) {
2329                 mac_reg = er32(EXTCNF_CTRL);
2330                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2331                         goto release;
2332         }
2333 
2334         mac_reg = er32(FEXTNVM);
2335         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2336                 goto release;
2337 
2338         mac_reg = er32(PHY_CTRL);
2339 
2340         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2341         if (ret_val)
2342                 goto release;
2343 
2344         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2345 
2346         if (d0_state) {
2347                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2348                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2349 
2350                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2351                         oem_reg |= HV_OEM_BITS_LPLU;
2352         } else {
2353                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2354                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2355                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2356 
2357                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2358                                E1000_PHY_CTRL_NOND0A_LPLU))
2359                         oem_reg |= HV_OEM_BITS_LPLU;
2360         }
2361 
2362         /* Set Restart auto-neg to activate the bits */
2363         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2364             !hw->phy.ops.check_reset_block(hw))
2365                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2366 
2367         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2368 
2369 release:
2370         hw->phy.ops.release(hw);
2371 
2372         return ret_val;
2373 }
2374 
2375 /**
2376  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2377  *  @hw:   pointer to the HW structure
2378  **/
2379 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2380 {
2381         s32 ret_val;
2382         u16 data;
2383 
2384         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2385         if (ret_val)
2386                 return ret_val;
2387 
2388         data |= HV_KMRN_MDIO_SLOW;
2389 
2390         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2391 
2392         return ret_val;
2393 }
2394 
2395 /**
2396  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2397  *  done after every PHY reset.
2398  **/
2399 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2400 {
2401         s32 ret_val = 0;
2402         u16 phy_data;
2403 
2404         if (hw->mac.type != e1000_pchlan)
2405                 return 0;
2406 
2407         /* Set MDIO slow mode before any other MDIO access */
2408         if (hw->phy.type == e1000_phy_82577) {
2409                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2410                 if (ret_val)
2411                         return ret_val;
2412         }
2413 
2414         if (((hw->phy.type == e1000_phy_82577) &&
2415              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2416             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2417                 /* Disable generation of early preamble */
2418                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2419                 if (ret_val)
2420                         return ret_val;
2421 
2422                 /* Preamble tuning for SSC */
2423                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2424                 if (ret_val)
2425                         return ret_val;
2426         }
2427 
2428         if (hw->phy.type == e1000_phy_82578) {
2429                 /* Return registers to default by doing a soft reset then
2430                  * writing 0x3140 to the control register.
2431                  */
2432                 if (hw->phy.revision < 2) {
2433                         e1000e_phy_sw_reset(hw);
2434                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2435                         if (ret_val)
2436                                 return ret_val;
2437                 }
2438         }
2439 
2440         /* Select page 0 */
2441         ret_val = hw->phy.ops.acquire(hw);
2442         if (ret_val)
2443                 return ret_val;
2444 
2445         hw->phy.addr = 1;
2446         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2447         hw->phy.ops.release(hw);
2448         if (ret_val)
2449                 return ret_val;
2450 
2451         /* Configure the K1 Si workaround during phy reset assuming there is
2452          * link so that it disables K1 if link is in 1Gbps.
2453          */
2454         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2455         if (ret_val)
2456                 return ret_val;
2457 
2458         /* Workaround for link disconnects on a busy hub in half duplex */
2459         ret_val = hw->phy.ops.acquire(hw);
2460         if (ret_val)
2461                 return ret_val;
2462         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2463         if (ret_val)
2464                 goto release;
2465         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2466         if (ret_val)
2467                 goto release;
2468 
2469         /* set MSE higher to enable link to stay up when noise is high */
2470         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2471 release:
2472         hw->phy.ops.release(hw);
2473 
2474         return ret_val;
2475 }
2476 
2477 /**
2478  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2479  *  @hw:   pointer to the HW structure
2480  **/
2481 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2482 {
2483         u32 mac_reg;
2484         u16 i, phy_reg = 0;
2485         s32 ret_val;
2486 
2487         ret_val = hw->phy.ops.acquire(hw);
2488         if (ret_val)
2489                 return;
2490         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2491         if (ret_val)
2492                 goto release;
2493 
2494         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2495         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2496                 mac_reg = er32(RAL(i));
2497                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2498                                            (u16)(mac_reg & 0xFFFF));
2499                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2500                                            (u16)((mac_reg >> 16) & 0xFFFF));
2501 
2502                 mac_reg = er32(RAH(i));
2503                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2504                                            (u16)(mac_reg & 0xFFFF));
2505                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2506                                            (u16)((mac_reg & E1000_RAH_AV)
2507                                                  >> 16));
2508         }
2509 
2510         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2511 
2512 release:
2513         hw->phy.ops.release(hw);
2514 }
2515 
2516 /**
2517  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2518  *  with 82579 PHY
2519  *  @hw: pointer to the HW structure
2520  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2521  **/
2522 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2523 {
2524         s32 ret_val = 0;
2525         u16 phy_reg, data;
2526         u32 mac_reg;
2527         u16 i;
2528 
2529         if (hw->mac.type < e1000_pch2lan)
2530                 return 0;
2531 
2532         /* disable Rx path while enabling/disabling workaround */
2533         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2534         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2535         if (ret_val)
2536                 return ret_val;
2537 
2538         if (enable) {
2539                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2540                  * SHRAL/H) and initial CRC values to the MAC
2541                  */
2542                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2543                         u8 mac_addr[ETH_ALEN] = { 0 };
2544                         u32 addr_high, addr_low;
2545 
2546                         addr_high = er32(RAH(i));
2547                         if (!(addr_high & E1000_RAH_AV))
2548                                 continue;
2549                         addr_low = er32(RAL(i));
2550                         mac_addr[0] = (addr_low & 0xFF);
2551                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2552                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2553                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2554                         mac_addr[4] = (addr_high & 0xFF);
2555                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2556 
2557                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2558                 }
2559 
2560                 /* Write Rx addresses to the PHY */
2561                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2562 
2563                 /* Enable jumbo frame workaround in the MAC */
2564                 mac_reg = er32(FFLT_DBG);
2565                 mac_reg &= ~BIT(14);
2566                 mac_reg |= (7 << 15);
2567                 ew32(FFLT_DBG, mac_reg);
2568 
2569                 mac_reg = er32(RCTL);
2570                 mac_reg |= E1000_RCTL_SECRC;
2571                 ew32(RCTL, mac_reg);
2572 
2573                 ret_val = e1000e_read_kmrn_reg(hw,
2574                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2575                                                &data);
2576                 if (ret_val)
2577                         return ret_val;
2578                 ret_val = e1000e_write_kmrn_reg(hw,
2579                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2580                                                 data | BIT(0));
2581                 if (ret_val)
2582                         return ret_val;
2583                 ret_val = e1000e_read_kmrn_reg(hw,
2584                                                E1000_KMRNCTRLSTA_HD_CTRL,
2585                                                &data);
2586                 if (ret_val)
2587                         return ret_val;
2588                 data &= ~(0xF << 8);
2589                 data |= (0xB << 8);
2590                 ret_val = e1000e_write_kmrn_reg(hw,
2591                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2592                                                 data);
2593                 if (ret_val)
2594                         return ret_val;
2595 
2596                 /* Enable jumbo frame workaround in the PHY */
2597                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2598                 data &= ~(0x7F << 5);
2599                 data |= (0x37 << 5);
2600                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2601                 if (ret_val)
2602                         return ret_val;
2603                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2604                 data &= ~BIT(13);
2605                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2606                 if (ret_val)
2607                         return ret_val;
2608                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2609                 data &= ~(0x3FF << 2);
2610                 data |= (E1000_TX_PTR_GAP << 2);
2611                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2612                 if (ret_val)
2613                         return ret_val;
2614                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2615                 if (ret_val)
2616                         return ret_val;
2617                 e1e_rphy(hw, HV_PM_CTRL, &data);
2618                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2619                 if (ret_val)
2620                         return ret_val;
2621         } else {
2622                 /* Write MAC register values back to h/w defaults */
2623                 mac_reg = er32(FFLT_DBG);
2624                 mac_reg &= ~(0xF << 14);
2625                 ew32(FFLT_DBG, mac_reg);
2626 
2627                 mac_reg = er32(RCTL);
2628                 mac_reg &= ~E1000_RCTL_SECRC;
2629                 ew32(RCTL, mac_reg);
2630 
2631                 ret_val = e1000e_read_kmrn_reg(hw,
2632                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2633                                                &data);
2634                 if (ret_val)
2635                         return ret_val;
2636                 ret_val = e1000e_write_kmrn_reg(hw,
2637                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2638                                                 data & ~BIT(0));
2639                 if (ret_val)
2640                         return ret_val;
2641                 ret_val = e1000e_read_kmrn_reg(hw,
2642                                                E1000_KMRNCTRLSTA_HD_CTRL,
2643                                                &data);
2644                 if (ret_val)
2645                         return ret_val;
2646                 data &= ~(0xF << 8);
2647                 data |= (0xB << 8);
2648                 ret_val = e1000e_write_kmrn_reg(hw,
2649                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2650                                                 data);
2651                 if (ret_val)
2652                         return ret_val;
2653 
2654                 /* Write PHY register values back to h/w defaults */
2655                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2656                 data &= ~(0x7F << 5);
2657                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2658                 if (ret_val)
2659                         return ret_val;
2660                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2661                 data |= BIT(13);
2662                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2663                 if (ret_val)
2664                         return ret_val;
2665                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2666                 data &= ~(0x3FF << 2);
2667                 data |= (0x8 << 2);
2668                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2669                 if (ret_val)
2670                         return ret_val;
2671                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2672                 if (ret_val)
2673                         return ret_val;
2674                 e1e_rphy(hw, HV_PM_CTRL, &data);
2675                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2676                 if (ret_val)
2677                         return ret_val;
2678         }
2679 
2680         /* re-enable Rx path after enabling/disabling workaround */
2681         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2682 }
2683 
2684 /**
2685  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2686  *  done after every PHY reset.
2687  **/
2688 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2689 {
2690         s32 ret_val = 0;
2691 
2692         if (hw->mac.type != e1000_pch2lan)
2693                 return 0;
2694 
2695         /* Set MDIO slow mode before any other MDIO access */
2696         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2697         if (ret_val)
2698                 return ret_val;
2699 
2700         ret_val = hw->phy.ops.acquire(hw);
2701         if (ret_val)
2702                 return ret_val;
2703         /* set MSE higher to enable link to stay up when noise is high */
2704         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2705         if (ret_val)
2706                 goto release;
2707         /* drop link after 5 times MSE threshold was reached */
2708         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2709 release:
2710         hw->phy.ops.release(hw);
2711 
2712         return ret_val;
2713 }
2714 
2715 /**
2716  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2717  *  @hw:   pointer to the HW structure
2718  *
2719  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2720  *  Disable K1 in 1000Mbps and 100Mbps
2721  **/
2722 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2723 {
2724         s32 ret_val = 0;
2725         u16 status_reg = 0;
2726 
2727         if (hw->mac.type != e1000_pch2lan)
2728                 return 0;
2729 
2730         /* Set K1 beacon duration based on 10Mbs speed */
2731         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2732         if (ret_val)
2733                 return ret_val;
2734 
2735         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2736             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2737                 if (status_reg &
2738                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2739                         u16 pm_phy_reg;
2740 
2741                         /* LV 1G/100 Packet drop issue wa  */
2742                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2743                         if (ret_val)
2744                                 return ret_val;
2745                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2746                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2747                         if (ret_val)
2748                                 return ret_val;
2749                 } else {
2750                         u32 mac_reg;
2751 
2752                         mac_reg = er32(FEXTNVM4);
2753                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2754                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2755                         ew32(FEXTNVM4, mac_reg);
2756                 }
2757         }
2758 
2759         return ret_val;
2760 }
2761 
2762 /**
2763  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2764  *  @hw:   pointer to the HW structure
2765  *  @gate: boolean set to true to gate, false to ungate
2766  *
2767  *  Gate/ungate the automatic PHY configuration via hardware; perform
2768  *  the configuration via software instead.
2769  **/
2770 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2771 {
2772         u32 extcnf_ctrl;
2773 
2774         if (hw->mac.type < e1000_pch2lan)
2775                 return;
2776 
2777         extcnf_ctrl = er32(EXTCNF_CTRL);
2778 
2779         if (gate)
2780                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2781         else
2782                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2783 
2784         ew32(EXTCNF_CTRL, extcnf_ctrl);
2785 }
2786 
2787 /**
2788  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2789  *  @hw: pointer to the HW structure
2790  *
2791  *  Check the appropriate indication the MAC has finished configuring the
2792  *  PHY after a software reset.
2793  **/
2794 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2795 {
2796         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2797 
2798         /* Wait for basic configuration completes before proceeding */
2799         do {
2800                 data = er32(STATUS);
2801                 data &= E1000_STATUS_LAN_INIT_DONE;
2802                 usleep_range(100, 200);
2803         } while ((!data) && --loop);
2804 
2805         /* If basic configuration is incomplete before the above loop
2806          * count reaches 0, loading the configuration from NVM will
2807          * leave the PHY in a bad state possibly resulting in no link.
2808          */
2809         if (loop == 0)
2810                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2811 
2812         /* Clear the Init Done bit for the next init event */
2813         data = er32(STATUS);
2814         data &= ~E1000_STATUS_LAN_INIT_DONE;
2815         ew32(STATUS, data);
2816 }
2817 
2818 /**
2819  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2820  *  @hw: pointer to the HW structure
2821  **/
2822 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2823 {
2824         s32 ret_val = 0;
2825         u16 reg;
2826 
2827         if (hw->phy.ops.check_reset_block(hw))
2828                 return 0;
2829 
2830         /* Allow time for h/w to get to quiescent state after reset */
2831         usleep_range(10000, 11000);
2832 
2833         /* Perform any necessary post-reset workarounds */
2834         switch (hw->mac.type) {
2835         case e1000_pchlan:
2836                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2837                 if (ret_val)
2838                         return ret_val;
2839                 break;
2840         case e1000_pch2lan:
2841                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2842                 if (ret_val)
2843                         return ret_val;
2844                 break;
2845         default:
2846                 break;
2847         }
2848 
2849         /* Clear the host wakeup bit after lcd reset */
2850         if (hw->mac.type >= e1000_pchlan) {
2851                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2852                 reg &= ~BM_WUC_HOST_WU_BIT;
2853                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2854         }
2855 
2856         /* Configure the LCD with the extended configuration region in NVM */
2857         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2858         if (ret_val)
2859                 return ret_val;
2860 
2861         /* Configure the LCD with the OEM bits in NVM */
2862         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2863 
2864         if (hw->mac.type == e1000_pch2lan) {
2865                 /* Ungate automatic PHY configuration on non-managed 82579 */
2866                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2867                         usleep_range(10000, 11000);
2868                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2869                 }
2870 
2871                 /* Set EEE LPI Update Timer to 200usec */
2872                 ret_val = hw->phy.ops.acquire(hw);
2873                 if (ret_val)
2874                         return ret_val;
2875                 ret_val = e1000_write_emi_reg_locked(hw,
2876                                                      I82579_LPI_UPDATE_TIMER,
2877                                                      0x1387);
2878                 hw->phy.ops.release(hw);
2879         }
2880 
2881         return ret_val;
2882 }
2883 
2884 /**
2885  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2886  *  @hw: pointer to the HW structure
2887  *
2888  *  Resets the PHY
2889  *  This is a function pointer entry point called by drivers
2890  *  or other shared routines.
2891  **/
2892 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2893 {
2894         s32 ret_val = 0;
2895 
2896         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2897         if ((hw->mac.type == e1000_pch2lan) &&
2898             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2899                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2900 
2901         ret_val = e1000e_phy_hw_reset_generic(hw);
2902         if (ret_val)
2903                 return ret_val;
2904 
2905         return e1000_post_phy_reset_ich8lan(hw);
2906 }
2907 
2908 /**
2909  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2910  *  @hw: pointer to the HW structure
2911  *  @active: true to enable LPLU, false to disable
2912  *
2913  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2914  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2915  *  the phy speed. This function will manually set the LPLU bit and restart
2916  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2917  *  since it configures the same bit.
2918  **/
2919 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2920 {
2921         s32 ret_val;
2922         u16 oem_reg;
2923 
2924         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2925         if (ret_val)
2926                 return ret_val;
2927 
2928         if (active)
2929                 oem_reg |= HV_OEM_BITS_LPLU;
2930         else
2931                 oem_reg &= ~HV_OEM_BITS_LPLU;
2932 
2933         if (!hw->phy.ops.check_reset_block(hw))
2934                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2935 
2936         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2937 }
2938 
2939 /**
2940  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2941  *  @hw: pointer to the HW structure
2942  *  @active: true to enable LPLU, false to disable
2943  *
2944  *  Sets the LPLU D0 state according to the active flag.  When
2945  *  activating LPLU this function also disables smart speed
2946  *  and vice versa.  LPLU will not be activated unless the
2947  *  device autonegotiation advertisement meets standards of
2948  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2949  *  This is a function pointer entry point only called by
2950  *  PHY setup routines.
2951  **/
2952 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2953 {
2954         struct e1000_phy_info *phy = &hw->phy;
2955         u32 phy_ctrl;
2956         s32 ret_val = 0;
2957         u16 data;
2958 
2959         if (phy->type == e1000_phy_ife)
2960                 return 0;
2961 
2962         phy_ctrl = er32(PHY_CTRL);
2963 
2964         if (active) {
2965                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2966                 ew32(PHY_CTRL, phy_ctrl);
2967 
2968                 if (phy->type != e1000_phy_igp_3)
2969                         return 0;
2970 
2971                 /* Call gig speed drop workaround on LPLU before accessing
2972                  * any PHY registers
2973                  */
2974                 if (hw->mac.type == e1000_ich8lan)
2975                         e1000e_gig_downshift_workaround_ich8lan(hw);
2976 
2977                 /* When LPLU is enabled, we should disable SmartSpeed */
2978                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2979                 if (ret_val)
2980                         return ret_val;
2981                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2982                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2983                 if (ret_val)
2984                         return ret_val;
2985         } else {
2986                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2987                 ew32(PHY_CTRL, phy_ctrl);
2988 
2989                 if (phy->type != e1000_phy_igp_3)
2990                         return 0;
2991 
2992                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2993                  * during Dx states where the power conservation is most
2994                  * important.  During driver activity we should enable
2995                  * SmartSpeed, so performance is maintained.
2996                  */
2997                 if (phy->smart_speed == e1000_smart_speed_on) {
2998                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2999                                            &data);
3000                         if (ret_val)
3001                                 return ret_val;
3002 
3003                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3004                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3005                                            data);
3006                         if (ret_val)
3007                                 return ret_val;
3008                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3009                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3010                                            &data);
3011                         if (ret_val)
3012                                 return ret_val;
3013 
3014                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3015                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3016                                            data);
3017                         if (ret_val)
3018                                 return ret_val;
3019                 }
3020         }
3021 
3022         return 0;
3023 }
3024 
3025 /**
3026  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3027  *  @hw: pointer to the HW structure
3028  *  @active: true to enable LPLU, false to disable
3029  *
3030  *  Sets the LPLU D3 state according to the active flag.  When
3031  *  activating LPLU this function also disables smart speed
3032  *  and vice versa.  LPLU will not be activated unless the
3033  *  device autonegotiation advertisement meets standards of
3034  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3035  *  This is a function pointer entry point only called by
3036  *  PHY setup routines.
3037  **/
3038 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3039 {
3040         struct e1000_phy_info *phy = &hw->phy;
3041         u32 phy_ctrl;
3042         s32 ret_val = 0;
3043         u16 data;
3044 
3045         phy_ctrl = er32(PHY_CTRL);
3046 
3047         if (!active) {
3048                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3049                 ew32(PHY_CTRL, phy_ctrl);
3050 
3051                 if (phy->type != e1000_phy_igp_3)
3052                         return 0;
3053 
3054                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3055                  * during Dx states where the power conservation is most
3056                  * important.  During driver activity we should enable
3057                  * SmartSpeed, so performance is maintained.
3058                  */
3059                 if (phy->smart_speed == e1000_smart_speed_on) {
3060                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3061                                            &data);
3062                         if (ret_val)
3063                                 return ret_val;
3064 
3065                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3066                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3067                                            data);
3068                         if (ret_val)
3069                                 return ret_val;
3070                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3071                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3072                                            &data);
3073                         if (ret_val)
3074                                 return ret_val;
3075 
3076                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3077                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3078                                            data);
3079                         if (ret_val)
3080                                 return ret_val;
3081                 }
3082         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3083                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3084                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3085                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3086                 ew32(PHY_CTRL, phy_ctrl);
3087 
3088                 if (phy->type != e1000_phy_igp_3)
3089                         return 0;
3090 
3091                 /* Call gig speed drop workaround on LPLU before accessing
3092                  * any PHY registers
3093                  */
3094                 if (hw->mac.type == e1000_ich8lan)
3095                         e1000e_gig_downshift_workaround_ich8lan(hw);
3096 
3097                 /* When LPLU is enabled, we should disable SmartSpeed */
3098                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3099                 if (ret_val)
3100                         return ret_val;
3101 
3102                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3103                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3104         }
3105 
3106         return ret_val;
3107 }
3108 
3109 /**
3110  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3111  *  @hw: pointer to the HW structure
3112  *  @bank:  pointer to the variable that returns the active bank
3113  *
3114  *  Reads signature byte from the NVM using the flash access registers.
3115  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3116  **/
3117 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3118 {
3119         u32 eecd;
3120         struct e1000_nvm_info *nvm = &hw->nvm;
3121         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3122         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3123         u32 nvm_dword = 0;
3124         u8 sig_byte = 0;
3125         s32 ret_val;
3126 
3127         switch (hw->mac.type) {
3128         case e1000_pch_spt:
3129         case e1000_pch_cnp:
3130                 bank1_offset = nvm->flash_bank_size;
3131                 act_offset = E1000_ICH_NVM_SIG_WORD;
3132 
3133                 /* set bank to 0 in case flash read fails */
3134                 *bank = 0;
3135 
3136                 /* Check bank 0 */
3137                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3138                                                          &nvm_dword);
3139                 if (ret_val)
3140                         return ret_val;
3141                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3142                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3143                     E1000_ICH_NVM_SIG_VALUE) {
3144                         *bank = 0;
3145                         return 0;
3146                 }
3147 
3148                 /* Check bank 1 */
3149                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3150                                                          bank1_offset,
3151                                                          &nvm_dword);
3152                 if (ret_val)
3153                         return ret_val;
3154                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3155                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3156                     E1000_ICH_NVM_SIG_VALUE) {
3157                         *bank = 1;
3158                         return 0;
3159                 }
3160 
3161                 e_dbg("ERROR: No valid NVM bank present\n");
3162                 return -E1000_ERR_NVM;
3163         case e1000_ich8lan:
3164         case e1000_ich9lan:
3165                 eecd = er32(EECD);
3166                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3167                     E1000_EECD_SEC1VAL_VALID_MASK) {
3168                         if (eecd & E1000_EECD_SEC1VAL)
3169                                 *bank = 1;
3170                         else
3171                                 *bank = 0;
3172 
3173                         return 0;
3174                 }
3175                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3176                 /* fall-thru */
3177         default:
3178                 /* set bank to 0 in case flash read fails */
3179                 *bank = 0;
3180 
3181                 /* Check bank 0 */
3182                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3183                                                         &sig_byte);
3184                 if (ret_val)
3185                         return ret_val;
3186                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3187                     E1000_ICH_NVM_SIG_VALUE) {
3188                         *bank = 0;
3189                         return 0;
3190                 }
3191 
3192                 /* Check bank 1 */
3193                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3194                                                         bank1_offset,
3195                                                         &sig_byte);
3196                 if (ret_val)
3197                         return ret_val;
3198                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3199                     E1000_ICH_NVM_SIG_VALUE) {
3200                         *bank = 1;
3201                         return 0;
3202                 }
3203 
3204                 e_dbg("ERROR: No valid NVM bank present\n");
3205                 return -E1000_ERR_NVM;
3206         }
3207 }
3208 
3209 /**
3210  *  e1000_read_nvm_spt - NVM access for SPT
3211  *  @hw: pointer to the HW structure
3212  *  @offset: The offset (in bytes) of the word(s) to read.
3213  *  @words: Size of data to read in words.
3214  *  @data: pointer to the word(s) to read at offset.
3215  *
3216  *  Reads a word(s) from the NVM
3217  **/
3218 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3219                               u16 *data)
3220 {
3221         struct e1000_nvm_info *nvm = &hw->nvm;
3222         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3223         u32 act_offset;
3224         s32 ret_val = 0;
3225         u32 bank = 0;
3226         u32 dword = 0;
3227         u16 offset_to_read;
3228         u16 i;
3229 
3230         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3231             (words == 0)) {
3232                 e_dbg("nvm parameter(s) out of bounds\n");
3233                 ret_val = -E1000_ERR_NVM;
3234                 goto out;
3235         }
3236 
3237         nvm->ops.acquire(hw);
3238 
3239         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3240         if (ret_val) {
3241                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3242                 bank = 0;
3243         }
3244 
3245         act_offset = (bank) ? nvm->flash_bank_size : 0;
3246         act_offset += offset;
3247 
3248         ret_val = 0;
3249 
3250         for (i = 0; i < words; i += 2) {
3251                 if (words - i == 1) {
3252                         if (dev_spec->shadow_ram[offset + i].modified) {
3253                                 data[i] =
3254                                     dev_spec->shadow_ram[offset + i].value;
3255                         } else {
3256                                 offset_to_read = act_offset + i -
3257                                     ((act_offset + i) % 2);
3258                                 ret_val =
3259                                   e1000_read_flash_dword_ich8lan(hw,
3260                                                                  offset_to_read,
3261                                                                  &dword);
3262                                 if (ret_val)
3263                                         break;
3264                                 if ((act_offset + i) % 2 == 0)
3265                                         data[i] = (u16)(dword & 0xFFFF);
3266                                 else
3267                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3268                         }
3269                 } else {
3270                         offset_to_read = act_offset + i;
3271                         if (!(dev_spec->shadow_ram[offset + i].modified) ||
3272                             !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3273                                 ret_val =
3274                                   e1000_read_flash_dword_ich8lan(hw,
3275                                                                  offset_to_read,
3276                                                                  &dword);
3277                                 if (ret_val)
3278                                         break;
3279                         }
3280                         if (dev_spec->shadow_ram[offset + i].modified)
3281                                 data[i] =
3282                                     dev_spec->shadow_ram[offset + i].value;
3283                         else
3284                                 data[i] = (u16)(dword & 0xFFFF);
3285                         if (dev_spec->shadow_ram[offset + i].modified)
3286                                 data[i + 1] =
3287                                     dev_spec->shadow_ram[offset + i + 1].value;
3288                         else
3289                                 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3290                 }
3291         }
3292 
3293         nvm->ops.release(hw);
3294 
3295 out:
3296         if (ret_val)
3297                 e_dbg("NVM read error: %d\n", ret_val);
3298 
3299         return ret_val;
3300 }
3301 
3302 /**
3303  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3304  *  @hw: pointer to the HW structure
3305  *  @offset: The offset (in bytes) of the word(s) to read.
3306  *  @words: Size of data to read in words
3307  *  @data: Pointer to the word(s) to read at offset.
3308  *
3309  *  Reads a word(s) from the NVM using the flash access registers.
3310  **/
3311 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3312                                   u16 *data)
3313 {
3314         struct e1000_nvm_info *nvm = &hw->nvm;
3315         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3316         u32 act_offset;
3317         s32 ret_val = 0;
3318         u32 bank = 0;
3319         u16 i, word;
3320 
3321         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3322             (words == 0)) {
3323                 e_dbg("nvm parameter(s) out of bounds\n");
3324                 ret_val = -E1000_ERR_NVM;
3325                 goto out;
3326         }
3327 
3328         nvm->ops.acquire(hw);
3329 
3330         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3331         if (ret_val) {
3332                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3333                 bank = 0;
3334         }
3335 
3336         act_offset = (bank) ? nvm->flash_bank_size : 0;
3337         act_offset += offset;
3338 
3339         ret_val = 0;
3340         for (i = 0; i < words; i++) {
3341                 if (dev_spec->shadow_ram[offset + i].modified) {
3342                         data[i] = dev_spec->shadow_ram[offset + i].value;
3343                 } else {
3344                         ret_val = e1000_read_flash_word_ich8lan(hw,
3345                                                                 act_offset + i,
3346                                                                 &word);
3347                         if (ret_val)
3348                                 break;
3349                         data[i] = word;
3350                 }
3351         }
3352 
3353         nvm->ops.release(hw);
3354 
3355 out:
3356         if (ret_val)
3357                 e_dbg("NVM read error: %d\n", ret_val);
3358 
3359         return ret_val;
3360 }
3361 
3362 /**
3363  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3364  *  @hw: pointer to the HW structure
3365  *
3366  *  This function does initial flash setup so that a new read/write/erase cycle
3367  *  can be started.
3368  **/
3369 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3370 {
3371         union ich8_hws_flash_status hsfsts;
3372         s32 ret_val = -E1000_ERR_NVM;
3373 
3374         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3375 
3376         /* Check if the flash descriptor is valid */
3377         if (!hsfsts.hsf_status.fldesvalid) {
3378                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
3379                 return -E1000_ERR_NVM;
3380         }
3381 
3382         /* Clear FCERR and DAEL in hw status by writing 1 */
3383         hsfsts.hsf_status.flcerr = 1;
3384         hsfsts.hsf_status.dael = 1;
3385         if (hw->mac.type >= e1000_pch_spt)
3386                 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3387         else
3388                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3389 
3390         /* Either we should have a hardware SPI cycle in progress
3391          * bit to check against, in order to start a new cycle or
3392          * FDONE bit should be changed in the hardware so that it
3393          * is 1 after hardware reset, which can then be used as an
3394          * indication whether a cycle is in progress or has been
3395          * completed.
3396          */
3397 
3398         if (!hsfsts.hsf_status.flcinprog) {
3399                 /* There is no cycle running at present,
3400                  * so we can start a cycle.
3401                  * Begin by setting Flash Cycle Done.
3402                  */
3403                 hsfsts.hsf_status.flcdone = 1;
3404                 if (hw->mac.type >= e1000_pch_spt)
3405                         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3406                 else
3407                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3408                 ret_val = 0;
3409         } else {
3410                 s32 i;
3411 
3412                 /* Otherwise poll for sometime so the current
3413                  * cycle has a chance to end before giving up.
3414                  */
3415                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3416                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3417                         if (!hsfsts.hsf_status.flcinprog) {
3418                                 ret_val = 0;
3419                                 break;
3420                         }
3421                         udelay(1);
3422                 }
3423                 if (!ret_val) {
3424                         /* Successful in waiting for previous cycle to timeout,
3425                          * now set the Flash Cycle Done.
3426                          */
3427                         hsfsts.hsf_status.flcdone = 1;
3428                         if (hw->mac.type >= e1000_pch_spt)
3429                                 ew32flash(ICH_FLASH_HSFSTS,
3430                                           hsfsts.regval & 0xFFFF);
3431                         else
3432                                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3433                 } else {
3434                         e_dbg("Flash controller busy, cannot get access\n");
3435                 }
3436         }
3437 
3438         return ret_val;
3439 }
3440 
3441 /**
3442  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3443  *  @hw: pointer to the HW structure
3444  *  @timeout: maximum time to wait for completion
3445  *
3446  *  This function starts a flash cycle and waits for its completion.
3447  **/
3448 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3449 {
3450         union ich8_hws_flash_ctrl hsflctl;
3451         union ich8_hws_flash_status hsfsts;
3452         u32 i = 0;
3453 
3454         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3455         if (hw->mac.type >= e1000_pch_spt)
3456                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3457         else
3458                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3459         hsflctl.hsf_ctrl.flcgo = 1;
3460 
3461         if (hw->mac.type >= e1000_pch_spt)
3462                 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3463         else
3464                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3465 
3466         /* wait till FDONE bit is set to 1 */
3467         do {
3468                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3469                 if (hsfsts.hsf_status.flcdone)
3470                         break;
3471                 udelay(1);
3472         } while (i++ < timeout);
3473 
3474         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3475                 return 0;
3476 
3477         return -E1000_ERR_NVM;
3478 }
3479 
3480 /**
3481  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3482  *  @hw: pointer to the HW structure
3483  *  @offset: offset to data location
3484  *  @data: pointer to the location for storing the data
3485  *
3486  *  Reads the flash dword at offset into data.  Offset is converted
3487  *  to bytes before read.
3488  **/
3489 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3490                                           u32 *data)
3491 {
3492         /* Must convert word offset into bytes. */
3493         offset <<= 1;
3494         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3495 }
3496 
3497 /**
3498  *  e1000_read_flash_word_ich8lan - Read word from flash
3499  *  @hw: pointer to the HW structure
3500  *  @offset: offset to data location
3501  *  @data: pointer to the location for storing the data
3502  *
3503  *  Reads the flash word at offset into data.  Offset is converted
3504  *  to bytes before read.
3505  **/
3506 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3507                                          u16 *data)
3508 {
3509         /* Must convert offset into bytes. */
3510         offset <<= 1;
3511 
3512         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3513 }
3514 
3515 /**
3516  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3517  *  @hw: pointer to the HW structure
3518  *  @offset: The offset of the byte to read.
3519  *  @data: Pointer to a byte to store the value read.
3520  *
3521  *  Reads a single byte from the NVM using the flash access registers.
3522  **/
3523 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3524                                          u8 *data)
3525 {
3526         s32 ret_val;
3527         u16 word = 0;
3528 
3529         /* In SPT, only 32 bits access is supported,
3530          * so this function should not be called.
3531          */
3532         if (hw->mac.type >= e1000_pch_spt)
3533                 return -E1000_ERR_NVM;
3534         else
3535                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3536 
3537         if (ret_val)
3538                 return ret_val;
3539 
3540         *data = (u8)word;
3541 
3542         return 0;
3543 }
3544 
3545 /**
3546  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3547  *  @hw: pointer to the HW structure
3548  *  @offset: The offset (in bytes) of the byte or word to read.
3549  *  @size: Size of data to read, 1=byte 2=word
3550  *  @data: Pointer to the word to store the value read.
3551  *
3552  *  Reads a byte or word from the NVM using the flash access registers.
3553  **/
3554 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3555                                          u8 size, u16 *data)
3556 {
3557         union ich8_hws_flash_status hsfsts;
3558         union ich8_hws_flash_ctrl hsflctl;
3559         u32 flash_linear_addr;
3560         u32 flash_data = 0;
3561         s32 ret_val = -E1000_ERR_NVM;
3562         u8 count = 0;
3563 
3564         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3565                 return -E1000_ERR_NVM;
3566 
3567         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3568                              hw->nvm.flash_base_addr);
3569 
3570         do {
3571                 udelay(1);
3572                 /* Steps */
3573                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3574                 if (ret_val)
3575                         break;
3576 
3577                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3578                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3579                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3580                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3581                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3582 
3583                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3584 
3585                 ret_val =
3586                     e1000_flash_cycle_ich8lan(hw,
3587                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3588 
3589                 /* Check if FCERR is set to 1, if set to 1, clear it
3590                  * and try the whole sequence a few more times, else
3591                  * read in (shift in) the Flash Data0, the order is
3592                  * least significant byte first msb to lsb
3593                  */
3594                 if (!ret_val) {
3595                         flash_data = er32flash(ICH_FLASH_FDATA0);
3596                         if (size == 1)
3597                                 *data = (u8)(flash_data & 0x000000FF);
3598                         else if (size == 2)
3599                                 *data = (u16)(flash_data & 0x0000FFFF);
3600                         break;
3601                 } else {
3602                         /* If we've gotten here, then things are probably
3603                          * completely hosed, but if the error condition is
3604                          * detected, it won't hurt to give it another try...
3605                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3606                          */
3607                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3608                         if (hsfsts.hsf_status.flcerr) {
3609                                 /* Repeat for some time before giving up. */
3610                                 continue;
3611                         } else if (!hsfsts.hsf_status.flcdone) {
3612                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3613                                 break;
3614                         }
3615                 }
3616         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3617 
3618         return ret_val;
3619 }
3620 
3621 /**
3622  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3623  *  @hw: pointer to the HW structure
3624  *  @offset: The offset (in bytes) of the dword to read.
3625  *  @data: Pointer to the dword to store the value read.
3626  *
3627  *  Reads a byte or word from the NVM using the flash access registers.
3628  **/
3629 
3630 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3631                                            u32 *data)
3632 {
3633         union ich8_hws_flash_status hsfsts;
3634         union ich8_hws_flash_ctrl hsflctl;
3635         u32 flash_linear_addr;
3636         s32 ret_val = -E1000_ERR_NVM;
3637         u8 count = 0;
3638 
3639         if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3640                 return -E1000_ERR_NVM;
3641         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3642                              hw->nvm.flash_base_addr);
3643 
3644         do {
3645                 udelay(1);
3646                 /* Steps */
3647                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3648                 if (ret_val)
3649                         break;
3650                 /* In SPT, This register is in Lan memory space, not flash.
3651                  * Therefore, only 32 bit access is supported
3652                  */
3653                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3654 
3655                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3656                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3657                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3658                 /* In SPT, This register is in Lan memory space, not flash.
3659                  * Therefore, only 32 bit access is supported
3660                  */
3661                 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3662                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3663 
3664                 ret_val =
3665                    e1000_flash_cycle_ich8lan(hw,
3666                                              ICH_FLASH_READ_COMMAND_TIMEOUT);
3667 
3668                 /* Check if FCERR is set to 1, if set to 1, clear it
3669                  * and try the whole sequence a few more times, else
3670                  * read in (shift in) the Flash Data0, the order is
3671                  * least significant byte first msb to lsb
3672                  */
3673                 if (!ret_val) {
3674                         *data = er32flash(ICH_FLASH_FDATA0);
3675                         break;
3676                 } else {
3677                         /* If we've gotten here, then things are probably
3678                          * completely hosed, but if the error condition is
3679                          * detected, it won't hurt to give it another try...
3680                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3681                          */
3682                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3683                         if (hsfsts.hsf_status.flcerr) {
3684                                 /* Repeat for some time before giving up. */
3685                                 continue;
3686                         } else if (!hsfsts.hsf_status.flcdone) {
3687                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3688                                 break;
3689                         }
3690                 }
3691         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3692 
3693         return ret_val;
3694 }
3695 
3696 /**
3697  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3698  *  @hw: pointer to the HW structure
3699  *  @offset: The offset (in bytes) of the word(s) to write.
3700  *  @words: Size of data to write in words
3701  *  @data: Pointer to the word(s) to write at offset.
3702  *
3703  *  Writes a byte or word to the NVM using the flash access registers.
3704  **/
3705 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3706                                    u16 *data)
3707 {
3708         struct e1000_nvm_info *nvm = &hw->nvm;
3709         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3710         u16 i;
3711 
3712         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3713             (words == 0)) {
3714                 e_dbg("nvm parameter(s) out of bounds\n");
3715                 return -E1000_ERR_NVM;
3716         }
3717 
3718         nvm->ops.acquire(hw);
3719 
3720         for (i = 0; i < words; i++) {
3721                 dev_spec->shadow_ram[offset + i].modified = true;
3722                 dev_spec->shadow_ram[offset + i].value = data[i];
3723         }
3724 
3725         nvm->ops.release(hw);
3726 
3727         return 0;
3728 }
3729 
3730 /**
3731  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3732  *  @hw: pointer to the HW structure
3733  *
3734  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3735  *  which writes the checksum to the shadow ram.  The changes in the shadow
3736  *  ram are then committed to the EEPROM by processing each bank at a time
3737  *  checking for the modified bit and writing only the pending changes.
3738  *  After a successful commit, the shadow ram is cleared and is ready for
3739  *  future writes.
3740  **/
3741 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3742 {
3743         struct e1000_nvm_info *nvm = &hw->nvm;
3744         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3745         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3746         s32 ret_val;
3747         u32 dword = 0;
3748 
3749         ret_val = e1000e_update_nvm_checksum_generic(hw);
3750         if (ret_val)
3751                 goto out;
3752 
3753         if (nvm->type != e1000_nvm_flash_sw)
3754                 goto out;
3755 
3756         nvm->ops.acquire(hw);
3757 
3758         /* We're writing to the opposite bank so if we're on bank 1,
3759          * write to bank 0 etc.  We also need to erase the segment that
3760          * is going to be written
3761          */
3762         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3763         if (ret_val) {
3764                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3765                 bank = 0;
3766         }
3767 
3768         if (bank == 0) {
3769                 new_bank_offset = nvm->flash_bank_size;
3770                 old_bank_offset = 0;
3771                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3772                 if (ret_val)
3773                         goto release;
3774         } else {
3775                 old_bank_offset = nvm->flash_bank_size;
3776                 new_bank_offset = 0;
3777                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3778                 if (ret_val)
3779                         goto release;
3780         }
3781         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3782                 /* Determine whether to write the value stored
3783                  * in the other NVM bank or a modified value stored
3784                  * in the shadow RAM
3785                  */
3786                 ret_val = e1000_read_flash_dword_ich8lan(hw,
3787                                                          i + old_bank_offset,
3788                                                          &dword);
3789 
3790                 if (dev_spec->shadow_ram[i].modified) {
3791                         dword &= 0xffff0000;
3792                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3793                 }
3794                 if (dev_spec->shadow_ram[i + 1].modified) {
3795                         dword &= 0x0000ffff;
3796                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3797                                   << 16);
3798                 }
3799                 if (ret_val)
3800                         break;
3801 
3802                 /* If the word is 0x13, then make sure the signature bits
3803                  * (15:14) are 11b until the commit has completed.
3804                  * This will allow us to write 10b which indicates the
3805                  * signature is valid.  We want to do this after the write
3806                  * has completed so that we don't mark the segment valid
3807                  * while the write is still in progress
3808                  */
3809                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3810                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
3811 
3812                 /* Convert offset to bytes. */
3813                 act_offset = (i + new_bank_offset) << 1;
3814 
3815                 usleep_range(100, 200);
3816 
3817                 /* Write the data to the new bank. Offset in words */
3818                 act_offset = i + new_bank_offset;
3819                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3820                                                                 dword);
3821                 if (ret_val)
3822                         break;
3823         }
3824 
3825         /* Don't bother writing the segment valid bits if sector
3826          * programming failed.
3827          */
3828         if (ret_val) {
3829                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3830                 e_dbg("Flash commit failed.\n");
3831                 goto release;
3832         }
3833 
3834         /* Finally validate the new segment by setting bit 15:14
3835          * to 10b in word 0x13 , this can be done without an
3836          * erase as well since these bits are 11 to start with
3837          * and we need to change bit 14 to 0b
3838          */
3839         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3840 
3841         /*offset in words but we read dword */
3842         --act_offset;
3843         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3844 
3845         if (ret_val)
3846                 goto release;
3847 
3848         dword &= 0xBFFFFFFF;
3849         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3850 
3851         if (ret_val)
3852                 goto release;
3853 
3854         /* And invalidate the previously valid segment by setting
3855          * its signature word (0x13) high_byte to 0b. This can be
3856          * done without an erase because flash erase sets all bits
3857          * to 1's. We can write 1's to 0's without an erase
3858          */
3859         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3860 
3861         /* offset in words but we read dword */
3862         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3863         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3864 
3865         if (ret_val)
3866                 goto release;
3867 
3868         dword &= 0x00FFFFFF;
3869         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3870 
3871         if (ret_val)
3872                 goto release;
3873 
3874         /* Great!  Everything worked, we can now clear the cached entries. */
3875         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3876                 dev_spec->shadow_ram[i].modified = false;
3877                 dev_spec->shadow_ram[i].value = 0xFFFF;
3878         }
3879 
3880 release:
3881         nvm->ops.release(hw);
3882 
3883         /* Reload the EEPROM, or else modifications will not appear
3884          * until after the next adapter reset.
3885          */
3886         if (!ret_val) {
3887                 nvm->ops.reload(hw);
3888                 usleep_range(10000, 11000);
3889         }
3890 
3891 out:
3892         if (ret_val)
3893                 e_dbg("NVM update error: %d\n", ret_val);
3894 
3895         return ret_val;
3896 }
3897 
3898 /**
3899  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3900  *  @hw: pointer to the HW structure
3901  *
3902  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3903  *  which writes the checksum to the shadow ram.  The changes in the shadow
3904  *  ram are then committed to the EEPROM by processing each bank at a time
3905  *  checking for the modified bit and writing only the pending changes.
3906  *  After a successful commit, the shadow ram is cleared and is ready for
3907  *  future writes.
3908  **/
3909 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3910 {
3911         struct e1000_nvm_info *nvm = &hw->nvm;
3912         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3913         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3914         s32 ret_val;
3915         u16 data = 0;
3916 
3917         ret_val = e1000e_update_nvm_checksum_generic(hw);
3918         if (ret_val)
3919                 goto out;
3920 
3921         if (nvm->type != e1000_nvm_flash_sw)
3922                 goto out;
3923 
3924         nvm->ops.acquire(hw);
3925 
3926         /* We're writing to the opposite bank so if we're on bank 1,
3927          * write to bank 0 etc.  We also need to erase the segment that
3928          * is going to be written
3929          */
3930         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3931         if (ret_val) {
3932                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3933                 bank = 0;
3934         }
3935 
3936         if (bank == 0) {
3937                 new_bank_offset = nvm->flash_bank_size;
3938                 old_bank_offset = 0;
3939                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3940                 if (ret_val)
3941                         goto release;
3942         } else {
3943                 old_bank_offset = nvm->flash_bank_size;
3944                 new_bank_offset = 0;
3945                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3946                 if (ret_val)
3947                         goto release;
3948         }
3949         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3950                 if (dev_spec->shadow_ram[i].modified) {
3951                         data = dev_spec->shadow_ram[i].value;
3952                 } else {
3953                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3954                                                                 old_bank_offset,
3955                                                                 &data);
3956                         if (ret_val)
3957                                 break;
3958                 }
3959 
3960                 /* If the word is 0x13, then make sure the signature bits
3961                  * (15:14) are 11b until the commit has completed.
3962                  * This will allow us to write 10b which indicates the
3963                  * signature is valid.  We want to do this after the write
3964                  * has completed so that we don't mark the segment valid
3965                  * while the write is still in progress
3966                  */
3967                 if (i == E1000_ICH_NVM_SIG_WORD)
3968                         data |= E1000_ICH_NVM_SIG_MASK;
3969 
3970                 /* Convert offset to bytes. */
3971                 act_offset = (i + new_bank_offset) << 1;
3972 
3973                 usleep_range(100, 200);
3974                 /* Write the bytes to the new bank. */
3975                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3976                                                                act_offset,
3977                                                                (u8)data);
3978                 if (ret_val)
3979                         break;
3980 
3981                 usleep_range(100, 200);
3982                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3983                                                                act_offset + 1,
3984                                                                (u8)(data >> 8));
3985                 if (ret_val)
3986                         break;
3987         }
3988 
3989         /* Don't bother writing the segment valid bits if sector
3990          * programming failed.
3991          */
3992         if (ret_val) {
3993                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3994                 e_dbg("Flash commit failed.\n");
3995                 goto release;
3996         }
3997 
3998         /* Finally validate the new segment by setting bit 15:14
3999          * to 10b in word 0x13 , this can be done without an
4000          * erase as well since these bits are 11 to start with
4001          * and we need to change bit 14 to 0b
4002          */
4003         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4004         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4005         if (ret_val)
4006                 goto release;
4007 
4008         data &= 0xBFFF;
4009         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4010                                                        act_offset * 2 + 1,
4011                                                        (u8)(data >> 8));
4012         if (ret_val)
4013                 goto release;
4014 
4015         /* And invalidate the previously valid segment by setting
4016          * its signature word (0x13) high_byte to 0b. This can be
4017          * done without an erase because flash erase sets all bits
4018          * to 1's. We can write 1's to 0's without an erase
4019          */
4020         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4021         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4022         if (ret_val)
4023                 goto release;
4024 
4025         /* Great!  Everything worked, we can now clear the cached entries. */
4026         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4027                 dev_spec->shadow_ram[i].modified = false;
4028                 dev_spec->shadow_ram[i].value = 0xFFFF;
4029         }
4030 
4031 release:
4032         nvm->ops.release(hw);
4033 
4034         /* Reload the EEPROM, or else modifications will not appear
4035          * until after the next adapter reset.
4036          */
4037         if (!ret_val) {
4038                 nvm->ops.reload(hw);
4039                 usleep_range(10000, 11000);
4040         }
4041 
4042 out:
4043         if (ret_val)
4044                 e_dbg("NVM update error: %d\n", ret_val);
4045 
4046         return ret_val;
4047 }
4048 
4049 /**
4050  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4051  *  @hw: pointer to the HW structure
4052  *
4053  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4054  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4055  *  calculated, in which case we need to calculate the checksum and set bit 6.
4056  **/
4057 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4058 {
4059         s32 ret_val;
4060         u16 data;
4061         u16 word;
4062         u16 valid_csum_mask;
4063 
4064         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4065          * the checksum needs to be fixed.  This bit is an indication that
4066          * the NVM was prepared by OEM software and did not calculate
4067          * the checksum...a likely scenario.
4068          */
4069         switch (hw->mac.type) {
4070         case e1000_pch_lpt:
4071         case e1000_pch_spt:
4072         case e1000_pch_cnp:
4073                 word = NVM_COMPAT;
4074                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4075                 break;
4076         default:
4077                 word = NVM_FUTURE_INIT_WORD1;
4078                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4079                 break;
4080         }
4081 
4082         ret_val = e1000_read_nvm(hw, word, 1, &data);
4083         if (ret_val)
4084                 return ret_val;
4085 
4086         if (!(data & valid_csum_mask)) {
4087                 data |= valid_csum_mask;
4088                 ret_val = e1000_write_nvm(hw, word, 1, &data);
4089                 if (ret_val)
4090                         return ret_val;
4091                 ret_val = e1000e_update_nvm_checksum(hw);
4092                 if (ret_val)
4093                         return ret_val;
4094         }
4095 
4096         return e1000e_validate_nvm_checksum_generic(hw);
4097 }
4098 
4099 /**
4100  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4101  *  @hw: pointer to the HW structure
4102  *
4103  *  To prevent malicious write/erase of the NVM, set it to be read-only
4104  *  so that the hardware ignores all write/erase cycles of the NVM via
4105  *  the flash control registers.  The shadow-ram copy of the NVM will
4106  *  still be updated, however any updates to this copy will not stick
4107  *  across driver reloads.
4108  **/
4109 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4110 {
4111         struct e1000_nvm_info *nvm = &hw->nvm;
4112         union ich8_flash_protected_range pr0;
4113         union ich8_hws_flash_status hsfsts;
4114         u32 gfpreg;
4115 
4116         nvm->ops.acquire(hw);
4117 
4118         gfpreg = er32flash(ICH_FLASH_GFPREG);
4119 
4120         /* Write-protect GbE Sector of NVM */
4121         pr0.regval = er32flash(ICH_FLASH_PR0);
4122         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4123         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4124         pr0.range.wpe = true;
4125         ew32flash(ICH_FLASH_PR0, pr0.regval);
4126 
4127         /* Lock down a subset of GbE Flash Control Registers, e.g.
4128          * PR0 to prevent the write-protection from being lifted.
4129          * Once FLOCKDN is set, the registers protected by it cannot
4130          * be written until FLOCKDN is cleared by a hardware reset.
4131          */
4132         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4133         hsfsts.hsf_status.flockdn = true;
4134         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4135 
4136         nvm->ops.release(hw);
4137 }
4138 
4139 /**
4140  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4141  *  @hw: pointer to the HW structure
4142  *  @offset: The offset (in bytes) of the byte/word to read.
4143  *  @size: Size of data to read, 1=byte 2=word
4144  *  @data: The byte(s) to write to the NVM.
4145  *
4146  *  Writes one/two bytes to the NVM using the flash access registers.
4147  **/
4148 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4149                                           u8 size, u16 data)
4150 {
4151         union ich8_hws_flash_status hsfsts;
4152         union ich8_hws_flash_ctrl hsflctl;
4153         u32 flash_linear_addr;
4154         u32 flash_data = 0;
4155         s32 ret_val;
4156         u8 count = 0;
4157 
4158         if (hw->mac.type >= e1000_pch_spt) {
4159                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4160                         return -E1000_ERR_NVM;
4161         } else {
4162                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4163                         return -E1000_ERR_NVM;
4164         }
4165 
4166         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4167                              hw->nvm.flash_base_addr);
4168 
4169         do {
4170                 udelay(1);
4171                 /* Steps */
4172                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4173                 if (ret_val)
4174                         break;
4175                 /* In SPT, This register is in Lan memory space, not
4176                  * flash.  Therefore, only 32 bit access is supported
4177                  */
4178                 if (hw->mac.type >= e1000_pch_spt)
4179                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4180                 else
4181                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4182 
4183                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4184                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4185                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4186                 /* In SPT, This register is in Lan memory space,
4187                  * not flash.  Therefore, only 32 bit access is
4188                  * supported
4189                  */
4190                 if (hw->mac.type >= e1000_pch_spt)
4191                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4192                 else
4193                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4194 
4195                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4196 
4197                 if (size == 1)
4198                         flash_data = (u32)data & 0x00FF;
4199                 else
4200                         flash_data = (u32)data;
4201 
4202                 ew32flash(ICH_FLASH_FDATA0, flash_data);
4203 
4204                 /* check if FCERR is set to 1 , if set to 1, clear it
4205                  * and try the whole sequence a few more times else done
4206                  */
4207                 ret_val =
4208                     e1000_flash_cycle_ich8lan(hw,
4209                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4210                 if (!ret_val)
4211                         break;
4212 
4213                 /* If we're here, then things are most likely
4214                  * completely hosed, but if the error condition
4215                  * is detected, it won't hurt to give it another
4216                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4217                  */
4218                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4219                 if (hsfsts.hsf_status.flcerr)
4220                         /* Repeat for some time before giving up. */
4221                         continue;
4222                 if (!hsfsts.hsf_status.flcdone) {
4223                         e_dbg("Timeout error - flash cycle did not complete.\n");
4224                         break;
4225                 }
4226         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4227 
4228         return ret_val;
4229 }
4230 
4231 /**
4232 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4233 *  @hw: pointer to the HW structure
4234 *  @offset: The offset (in bytes) of the dwords to read.
4235 *  @data: The 4 bytes to write to the NVM.
4236 *
4237 *  Writes one/two/four bytes to the NVM using the flash access registers.
4238 **/
4239 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4240                                             u32 data)
4241 {
4242         union ich8_hws_flash_status hsfsts;
4243         union ich8_hws_flash_ctrl hsflctl;
4244         u32 flash_linear_addr;
4245         s32 ret_val;
4246         u8 count = 0;
4247 
4248         if (hw->mac.type >= e1000_pch_spt) {
4249                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4250                         return -E1000_ERR_NVM;
4251         }
4252         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4253                              hw->nvm.flash_base_addr);
4254         do {
4255                 udelay(1);
4256                 /* Steps */
4257                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4258                 if (ret_val)
4259                         break;
4260 
4261                 /* In SPT, This register is in Lan memory space, not
4262                  * flash.  Therefore, only 32 bit access is supported
4263                  */
4264                 if (hw->mac.type >= e1000_pch_spt)
4265                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4266                             >> 16;
4267                 else
4268                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4269 
4270                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4271                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4272 
4273                 /* In SPT, This register is in Lan memory space,
4274                  * not flash.  Therefore, only 32 bit access is
4275                  * supported
4276                  */
4277                 if (hw->mac.type >= e1000_pch_spt)
4278                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4279                 else
4280                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4281 
4282                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4283 
4284                 ew32flash(ICH_FLASH_FDATA0, data);
4285 
4286                 /* check if FCERR is set to 1 , if set to 1, clear it
4287                  * and try the whole sequence a few more times else done
4288                  */
4289                 ret_val =
4290                    e1000_flash_cycle_ich8lan(hw,
4291                                              ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4292 
4293                 if (!ret_val)
4294                         break;
4295 
4296                 /* If we're here, then things are most likely
4297                  * completely hosed, but if the error condition
4298                  * is detected, it won't hurt to give it another
4299                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4300                  */
4301                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4302 
4303                 if (hsfsts.hsf_status.flcerr)
4304                         /* Repeat for some time before giving up. */
4305                         continue;
4306                 if (!hsfsts.hsf_status.flcdone) {
4307                         e_dbg("Timeout error - flash cycle did not complete.\n");
4308                         break;
4309                 }
4310         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4311 
4312         return ret_val;
4313 }
4314 
4315 /**
4316  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4317  *  @hw: pointer to the HW structure
4318  *  @offset: The index of the byte to read.
4319  *  @data: The byte to write to the NVM.
4320  *
4321  *  Writes a single byte to the NVM using the flash access registers.
4322  **/
4323 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4324                                           u8 data)
4325 {
4326         u16 word = (u16)data;
4327 
4328         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4329 }
4330 
4331 /**
4332 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4333 *  @hw: pointer to the HW structure
4334 *  @offset: The offset of the word to write.
4335 *  @dword: The dword to write to the NVM.
4336 *
4337 *  Writes a single dword to the NVM using the flash access registers.
4338 *  Goes through a retry algorithm before giving up.
4339 **/
4340 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4341                                                  u32 offset, u32 dword)
4342 {
4343         s32 ret_val;
4344         u16 program_retries;
4345 
4346         /* Must convert word offset into bytes. */
4347         offset <<= 1;
4348         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4349 
4350         if (!ret_val)
4351                 return ret_val;
4352         for (program_retries = 0; program_retries < 100; program_retries++) {
4353                 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4354                 usleep_range(100, 200);
4355                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4356                 if (!ret_val)
4357                         break;
4358         }
4359         if (program_retries == 100)
4360                 return -E1000_ERR_NVM;
4361 
4362         return 0;
4363 }
4364 
4365 /**
4366  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4367  *  @hw: pointer to the HW structure
4368  *  @offset: The offset of the byte to write.
4369  *  @byte: The byte to write to the NVM.
4370  *
4371  *  Writes a single byte to the NVM using the flash access registers.
4372  *  Goes through a retry algorithm before giving up.
4373  **/
4374 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4375                                                 u32 offset, u8 byte)
4376 {
4377         s32 ret_val;
4378         u16 program_retries;
4379 
4380         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4381         if (!ret_val)
4382                 return ret_val;
4383 
4384         for (program_retries = 0; program_retries < 100; program_retries++) {
4385                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4386                 usleep_range(100, 200);
4387                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4388                 if (!ret_val)
4389                         break;
4390         }
4391         if (program_retries == 100)
4392                 return -E1000_ERR_NVM;
4393 
4394         return 0;
4395 }
4396 
4397 /**
4398  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4399  *  @hw: pointer to the HW structure
4400  *  @bank: 0 for first bank, 1 for second bank, etc.
4401  *
4402  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4403  *  bank N is 4096 * N + flash_reg_addr.
4404  **/
4405 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4406 {
4407         struct e1000_nvm_info *nvm = &hw->nvm;
4408         union ich8_hws_flash_status hsfsts;
4409         union ich8_hws_flash_ctrl hsflctl;
4410         u32 flash_linear_addr;
4411         /* bank size is in 16bit words - adjust to bytes */
4412         u32 flash_bank_size = nvm->flash_bank_size * 2;
4413         s32 ret_val;
4414         s32 count = 0;
4415         s32 j, iteration, sector_size;
4416 
4417         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4418 
4419         /* Determine HW Sector size: Read BERASE bits of hw flash status
4420          * register
4421          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4422          *     consecutive sectors.  The start index for the nth Hw sector
4423          *     can be calculated as = bank * 4096 + n * 256
4424          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4425          *     The start index for the nth Hw sector can be calculated
4426          *     as = bank * 4096
4427          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4428          *     (ich9 only, otherwise error condition)
4429          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4430          */
4431         switch (hsfsts.hsf_status.berasesz) {
4432         case 0:
4433                 /* Hw sector size 256 */
4434                 sector_size = ICH_FLASH_SEG_SIZE_256;
4435                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4436                 break;
4437         case 1:
4438                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4439                 iteration = 1;
4440                 break;
4441         case 2:
4442                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4443                 iteration = 1;
4444                 break;
4445         case 3:
4446                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4447                 iteration = 1;
4448                 break;
4449         default:
4450                 return -E1000_ERR_NVM;
4451         }
4452 
4453         /* Start with the base address, then add the sector offset. */
4454         flash_linear_addr = hw->nvm.flash_base_addr;
4455         flash_linear_addr += (bank) ? flash_bank_size : 0;
4456 
4457         for (j = 0; j < iteration; j++) {
4458                 do {
4459                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4460 
4461                         /* Steps */
4462                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4463                         if (ret_val)
4464                                 return ret_val;
4465 
4466                         /* Write a value 11 (block Erase) in Flash
4467                          * Cycle field in hw flash control
4468                          */
4469                         if (hw->mac.type >= e1000_pch_spt)
4470                                 hsflctl.regval =
4471                                     er32flash(ICH_FLASH_HSFSTS) >> 16;
4472                         else
4473                                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4474 
4475                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4476                         if (hw->mac.type >= e1000_pch_spt)
4477                                 ew32flash(ICH_FLASH_HSFSTS,
4478                                           hsflctl.regval << 16);
4479                         else
4480                                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4481 
4482                         /* Write the last 24 bits of an index within the
4483                          * block into Flash Linear address field in Flash
4484                          * Address.
4485                          */
4486                         flash_linear_addr += (j * sector_size);
4487                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4488 
4489                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4490                         if (!ret_val)
4491                                 break;
4492 
4493                         /* Check if FCERR is set to 1.  If 1,
4494                          * clear it and try the whole sequence
4495                          * a few more times else Done
4496                          */
4497                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4498                         if (hsfsts.hsf_status.flcerr)
4499                                 /* repeat for some time before giving up */
4500                                 continue;
4501                         else if (!hsfsts.hsf_status.flcdone)
4502                                 return ret_val;
4503                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4504         }
4505 
4506         return 0;
4507 }
4508 
4509 /**
4510  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4511  *  @hw: pointer to the HW structure
4512  *  @data: Pointer to the LED settings
4513  *
4514  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4515  *  settings is all 0's or F's, set the LED default to a valid LED default
4516  *  setting.
4517  **/
4518 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4519 {
4520         s32 ret_val;
4521 
4522         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4523         if (ret_val) {
4524                 e_dbg("NVM Read Error\n");
4525                 return ret_val;
4526         }
4527 
4528         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4529                 *data = ID_LED_DEFAULT_ICH8LAN;
4530 
4531         return 0;
4532 }
4533 
4534 /**
4535  *  e1000_id_led_init_pchlan - store LED configurations
4536  *  @hw: pointer to the HW structure
4537  *
4538  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4539  *  the PHY LED configuration register.
4540  *
4541  *  PCH also does not have an "always on" or "always off" mode which
4542  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4543  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4544  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4545  *  link based on logic in e1000_led_[on|off]_pchlan().
4546  **/
4547 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4548 {
4549         struct e1000_mac_info *mac = &hw->mac;
4550         s32 ret_val;
4551         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4552         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4553         u16 data, i, temp, shift;
4554 
4555         /* Get default ID LED modes */
4556         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4557         if (ret_val)
4558                 return ret_val;
4559 
4560         mac->ledctl_default = er32(LEDCTL);
4561         mac->ledctl_mode1 = mac->ledctl_default;
4562         mac->ledctl_mode2 = mac->ledctl_default;
4563 
4564         for (i = 0; i < 4; i++) {
4565                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4566                 shift = (i * 5);
4567                 switch (temp) {
4568                 case ID_LED_ON1_DEF2:
4569                 case ID_LED_ON1_ON2:
4570                 case ID_LED_ON1_OFF2:
4571                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4572                         mac->ledctl_mode1 |= (ledctl_on << shift);
4573                         break;
4574                 case ID_LED_OFF1_DEF2:
4575                 case ID_LED_OFF1_ON2:
4576                 case ID_LED_OFF1_OFF2:
4577                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4578                         mac->ledctl_mode1 |= (ledctl_off << shift);
4579                         break;
4580                 default:
4581                         /* Do nothing */
4582                         break;
4583                 }
4584                 switch (temp) {
4585                 case ID_LED_DEF1_ON2:
4586                 case ID_LED_ON1_ON2:
4587                 case ID_LED_OFF1_ON2:
4588                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4589                         mac->ledctl_mode2 |= (ledctl_on << shift);
4590                         break;
4591                 case ID_LED_DEF1_OFF2:
4592                 case ID_LED_ON1_OFF2:
4593                 case ID_LED_OFF1_OFF2:
4594                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4595                         mac->ledctl_mode2 |= (ledctl_off << shift);
4596                         break;
4597                 default:
4598                         /* Do nothing */
4599                         break;
4600                 }
4601         }
4602 
4603         return 0;
4604 }
4605 
4606 /**
4607  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4608  *  @hw: pointer to the HW structure
4609  *
4610  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4611  *  register, so the the bus width is hard coded.
4612  **/
4613 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4614 {
4615         struct e1000_bus_info *bus = &hw->bus;
4616         s32 ret_val;
4617 
4618         ret_val = e1000e_get_bus_info_pcie(hw);
4619 
4620         /* ICH devices are "PCI Express"-ish.  They have
4621          * a configuration space, but do not contain
4622          * PCI Express Capability registers, so bus width
4623          * must be hardcoded.
4624          */
4625         if (bus->width == e1000_bus_width_unknown)
4626                 bus->width = e1000_bus_width_pcie_x1;
4627 
4628         return ret_val;
4629 }
4630 
4631 /**
4632  *  e1000_reset_hw_ich8lan - Reset the hardware
4633  *  @hw: pointer to the HW structure
4634  *
4635  *  Does a full reset of the hardware which includes a reset of the PHY and
4636  *  MAC.
4637  **/
4638 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4639 {
4640         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4641         u16 kum_cfg;
4642         u32 ctrl, reg;
4643         s32 ret_val;
4644 
4645         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4646          * on the last TLP read/write transaction when MAC is reset.
4647          */
4648         ret_val = e1000e_disable_pcie_master(hw);
4649         if (ret_val)
4650                 e_dbg("PCI-E Master disable polling has failed.\n");
4651 
4652         e_dbg("Masking off all interrupts\n");
4653         ew32(IMC, 0xffffffff);
4654 
4655         /* Disable the Transmit and Receive units.  Then delay to allow
4656          * any pending transactions to complete before we hit the MAC
4657          * with the global reset.
4658          */
4659         ew32(RCTL, 0);
4660         ew32(TCTL, E1000_TCTL_PSP);
4661         e1e_flush();
4662 
4663         usleep_range(10000, 11000);
4664 
4665         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4666         if (hw->mac.type == e1000_ich8lan) {
4667                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4668                 ew32(PBA, E1000_PBA_8K);
4669                 /* Set Packet Buffer Size to 16k. */
4670                 ew32(PBS, E1000_PBS_16K);
4671         }
4672 
4673         if (hw->mac.type == e1000_pchlan) {
4674                 /* Save the NVM K1 bit setting */
4675                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4676                 if (ret_val)
4677                         return ret_val;
4678 
4679                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4680                         dev_spec->nvm_k1_enabled = true;
4681                 else
4682                         dev_spec->nvm_k1_enabled = false;
4683         }
4684 
4685         ctrl = er32(CTRL);
4686 
4687         if (!hw->phy.ops.check_reset_block(hw)) {
4688                 /* Full-chip reset requires MAC and PHY reset at the same
4689                  * time to make sure the interface between MAC and the
4690                  * external PHY is reset.
4691                  */
4692                 ctrl |= E1000_CTRL_PHY_RST;
4693 
4694                 /* Gate automatic PHY configuration by hardware on
4695                  * non-managed 82579
4696                  */
4697                 if ((hw->mac.type == e1000_pch2lan) &&
4698                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4699                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4700         }
4701         ret_val = e1000_acquire_swflag_ich8lan(hw);
4702         e_dbg("Issuing a global reset to ich8lan\n");
4703         ew32(CTRL, (ctrl | E1000_CTRL_RST));
4704         /* cannot issue a flush here because it hangs the hardware */
4705         msleep(20);
4706 
4707         /* Set Phy Config Counter to 50msec */
4708         if (hw->mac.type == e1000_pch2lan) {
4709                 reg = er32(FEXTNVM3);
4710                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4711                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4712                 ew32(FEXTNVM3, reg);
4713         }
4714 
4715         if (!ret_val)
4716                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4717 
4718         if (ctrl & E1000_CTRL_PHY_RST) {
4719                 ret_val = hw->phy.ops.get_cfg_done(hw);
4720                 if (ret_val)
4721                         return ret_val;
4722 
4723                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4724                 if (ret_val)
4725                         return ret_val;
4726         }
4727 
4728         /* For PCH, this write will make sure that any noise
4729          * will be detected as a CRC error and be dropped rather than show up
4730          * as a bad packet to the DMA engine.
4731          */
4732         if (hw->mac.type == e1000_pchlan)
4733                 ew32(CRC_OFFSET, 0x65656565);
4734 
4735         ew32(IMC, 0xffffffff);
4736         er32(ICR);
4737 
4738         reg = er32(KABGTXD);
4739         reg |= E1000_KABGTXD_BGSQLBIAS;
4740         ew32(KABGTXD, reg);
4741 
4742         return 0;
4743 }
4744 
4745 /**
4746  *  e1000_init_hw_ich8lan - Initialize the hardware
4747  *  @hw: pointer to the HW structure
4748  *
4749  *  Prepares the hardware for transmit and receive by doing the following:
4750  *   - initialize hardware bits
4751  *   - initialize LED identification
4752  *   - setup receive address registers
4753  *   - setup flow control
4754  *   - setup transmit descriptors
4755  *   - clear statistics
4756  **/
4757 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4758 {
4759         struct e1000_mac_info *mac = &hw->mac;
4760         u32 ctrl_ext, txdctl, snoop;
4761         s32 ret_val;
4762         u16 i;
4763 
4764         e1000_initialize_hw_bits_ich8lan(hw);
4765 
4766         /* Initialize identification LED */
4767         ret_val = mac->ops.id_led_init(hw);
4768         /* An error is not fatal and we should not stop init due to this */
4769         if (ret_val)
4770                 e_dbg("Error initializing identification LED\n");
4771 
4772         /* Setup the receive address. */
4773         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4774 
4775         /* Zero out the Multicast HASH table */
4776         e_dbg("Zeroing the MTA\n");
4777         for (i = 0; i < mac->mta_reg_count; i++)
4778                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4779 
4780         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4781          * the ME.  Disable wakeup by clearing the host wakeup bit.
4782          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4783          */
4784         if (hw->phy.type == e1000_phy_82578) {
4785                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4786                 i &= ~BM_WUC_HOST_WU_BIT;
4787                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4788                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4789                 if (ret_val)
4790                         return ret_val;
4791         }
4792 
4793         /* Setup link and flow control */
4794         ret_val = mac->ops.setup_link(hw);
4795 
4796         /* Set the transmit descriptor write-back policy for both queues */
4797         txdctl = er32(TXDCTL(0));
4798         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4799                   E1000_TXDCTL_FULL_TX_DESC_WB);
4800         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4801                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4802         ew32(TXDCTL(0), txdctl);
4803         txdctl = er32(TXDCTL(1));
4804         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4805                   E1000_TXDCTL_FULL_TX_DESC_WB);
4806         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4807                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4808         ew32(TXDCTL(1), txdctl);
4809 
4810         /* ICH8 has opposite polarity of no_snoop bits.
4811          * By default, we should use snoop behavior.
4812          */
4813         if (mac->type == e1000_ich8lan)
4814                 snoop = PCIE_ICH8_SNOOP_ALL;
4815         else
4816                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4817         e1000e_set_pcie_no_snoop(hw, snoop);
4818 
4819         ctrl_ext = er32(CTRL_EXT);
4820         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4821         ew32(CTRL_EXT, ctrl_ext);
4822 
4823         /* Clear all of the statistics registers (clear on read).  It is
4824          * important that we do this after we have tried to establish link
4825          * because the symbol error count will increment wildly if there
4826          * is no link.
4827          */
4828         e1000_clear_hw_cntrs_ich8lan(hw);
4829 
4830         return ret_val;
4831 }
4832 
4833 /**
4834  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4835  *  @hw: pointer to the HW structure
4836  *
4837  *  Sets/Clears required hardware bits necessary for correctly setting up the
4838  *  hardware for transmit and receive.
4839  **/
4840 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4841 {
4842         u32 reg;
4843 
4844         /* Extended Device Control */
4845         reg = er32(CTRL_EXT);
4846         reg |= BIT(22);
4847         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4848         if (hw->mac.type >= e1000_pchlan)
4849                 reg |= E1000_CTRL_EXT_PHYPDEN;
4850         ew32(CTRL_EXT, reg);
4851 
4852         /* Transmit Descriptor Control 0 */
4853         reg = er32(TXDCTL(0));
4854         reg |= BIT(22);
4855         ew32(TXDCTL(0), reg);
4856 
4857         /* Transmit Descriptor Control 1 */
4858         reg = er32(TXDCTL(1));
4859         reg |= BIT(22);
4860         ew32(TXDCTL(1), reg);
4861 
4862         /* Transmit Arbitration Control 0 */
4863         reg = er32(TARC(0));
4864         if (hw->mac.type == e1000_ich8lan)
4865                 reg |= BIT(28) | BIT(29);
4866         reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4867         ew32(TARC(0), reg);
4868 
4869         /* Transmit Arbitration Control 1 */
4870         reg = er32(TARC(1));
4871         if (er32(TCTL) & E1000_TCTL_MULR)
4872                 reg &= ~BIT(28);
4873         else
4874                 reg |= BIT(28);
4875         reg |= BIT(24) | BIT(26) | BIT(30);
4876         ew32(TARC(1), reg);
4877 
4878         /* Device Status */
4879         if (hw->mac.type == e1000_ich8lan) {
4880                 reg = er32(STATUS);
4881                 reg &= ~BIT(31);
4882                 ew32(STATUS, reg);
4883         }
4884 
4885         /* work-around descriptor data corruption issue during nfs v2 udp
4886          * traffic, just disable the nfs filtering capability
4887          */
4888         reg = er32(RFCTL);
4889         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4890 
4891         /* Disable IPv6 extension header parsing because some malformed
4892          * IPv6 headers can hang the Rx.
4893          */
4894         if (hw->mac.type == e1000_ich8lan)
4895                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4896         ew32(RFCTL, reg);
4897 
4898         /* Enable ECC on Lynxpoint */
4899         if (hw->mac.type >= e1000_pch_lpt) {
4900                 reg = er32(PBECCSTS);
4901                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4902                 ew32(PBECCSTS, reg);
4903 
4904                 reg = er32(CTRL);
4905                 reg |= E1000_CTRL_MEHE;
4906                 ew32(CTRL, reg);
4907         }
4908 }
4909 
4910 /**
4911  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4912  *  @hw: pointer to the HW structure
4913  *
4914  *  Determines which flow control settings to use, then configures flow
4915  *  control.  Calls the appropriate media-specific link configuration
4916  *  function.  Assuming the adapter has a valid link partner, a valid link
4917  *  should be established.  Assumes the hardware has previously been reset
4918  *  and the transmitter and receiver are not enabled.
4919  **/
4920 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4921 {
4922         s32 ret_val;
4923 
4924         if (hw->phy.ops.check_reset_block(hw))
4925                 return 0;
4926 
4927         /* ICH parts do not have a word in the NVM to determine
4928          * the default flow control setting, so we explicitly
4929          * set it to full.
4930          */
4931         if (hw->fc.requested_mode == e1000_fc_default) {
4932                 /* Workaround h/w hang when Tx flow control enabled */
4933                 if (hw->mac.type == e1000_pchlan)
4934                         hw->fc.requested_mode = e1000_fc_rx_pause;
4935                 else
4936                         hw->fc.requested_mode = e1000_fc_full;
4937         }
4938 
4939         /* Save off the requested flow control mode for use later.  Depending
4940          * on the link partner's capabilities, we may or may not use this mode.
4941          */
4942         hw->fc.current_mode = hw->fc.requested_mode;
4943 
4944         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4945 
4946         /* Continue to configure the copper link. */
4947         ret_val = hw->mac.ops.setup_physical_interface(hw);
4948         if (ret_val)
4949                 return ret_val;
4950 
4951         ew32(FCTTV, hw->fc.pause_time);
4952         if ((hw->phy.type == e1000_phy_82578) ||
4953             (hw->phy.type == e1000_phy_82579) ||
4954             (hw->phy.type == e1000_phy_i217) ||
4955             (hw->phy.type == e1000_phy_82577)) {
4956                 ew32(FCRTV_PCH, hw->fc.refresh_time);
4957 
4958                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4959                                    hw->fc.pause_time);
4960                 if (ret_val)
4961                         return ret_val;
4962         }
4963 
4964         return e1000e_set_fc_watermarks(hw);
4965 }
4966 
4967 /**
4968  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4969  *  @hw: pointer to the HW structure
4970  *
4971  *  Configures the kumeran interface to the PHY to wait the appropriate time
4972  *  when polling the PHY, then call the generic setup_copper_link to finish
4973  *  configuring the copper link.
4974  **/
4975 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4976 {
4977         u32 ctrl;
4978         s32 ret_val;
4979         u16 reg_data;
4980 
4981         ctrl = er32(CTRL);
4982         ctrl |= E1000_CTRL_SLU;
4983         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4984         ew32(CTRL, ctrl);
4985 
4986         /* Set the mac to wait the maximum time between each iteration
4987          * and increase the max iterations when polling the phy;
4988          * this fixes erroneous timeouts at 10Mbps.
4989          */
4990         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
4991         if (ret_val)
4992                 return ret_val;
4993         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4994                                        &reg_data);
4995         if (ret_val)
4996                 return ret_val;
4997         reg_data |= 0x3F;
4998         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4999                                         reg_data);
5000         if (ret_val)
5001                 return ret_val;
5002 
5003         switch (hw->phy.type) {
5004         case e1000_phy_igp_3:
5005                 ret_val = e1000e_copper_link_setup_igp(hw);
5006                 if (ret_val)
5007                         return ret_val;
5008                 break;
5009         case e1000_phy_bm:
5010         case e1000_phy_82578:
5011                 ret_val = e1000e_copper_link_setup_m88(hw);
5012                 if (ret_val)
5013                         return ret_val;
5014                 break;
5015         case e1000_phy_82577:
5016         case e1000_phy_82579:
5017                 ret_val = e1000_copper_link_setup_82577(hw);
5018                 if (ret_val)
5019                         return ret_val;
5020                 break;
5021         case e1000_phy_ife:
5022                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
5023                 if (ret_val)
5024                         return ret_val;
5025 
5026                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5027 
5028                 switch (hw->phy.mdix) {
5029                 case 1:
5030                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5031                         break;
5032                 case 2:
5033                         reg_data |= IFE_PMC_FORCE_MDIX;
5034                         break;
5035                 case 0:
5036                 default:
5037                         reg_data |= IFE_PMC_AUTO_MDIX;
5038                         break;
5039                 }
5040                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5041                 if (ret_val)
5042                         return ret_val;
5043                 break;
5044         default:
5045                 break;
5046         }
5047 
5048         return e1000e_setup_copper_link(hw);
5049 }
5050 
5051 /**
5052  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5053  *  @hw: pointer to the HW structure
5054  *
5055  *  Calls the PHY specific link setup function and then calls the
5056  *  generic setup_copper_link to finish configuring the link for
5057  *  Lynxpoint PCH devices
5058  **/
5059 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5060 {
5061         u32 ctrl;
5062         s32 ret_val;
5063 
5064         ctrl = er32(CTRL);
5065         ctrl |= E1000_CTRL_SLU;
5066         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5067         ew32(CTRL, ctrl);
5068 
5069         ret_val = e1000_copper_link_setup_82577(hw);
5070         if (ret_val)
5071                 return ret_val;
5072 
5073         return e1000e_setup_copper_link(hw);
5074 }
5075 
5076 /**
5077  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5078  *  @hw: pointer to the HW structure
5079  *  @speed: pointer to store current link speed
5080  *  @duplex: pointer to store the current link duplex
5081  *
5082  *  Calls the generic get_speed_and_duplex to retrieve the current link
5083  *  information and then calls the Kumeran lock loss workaround for links at
5084  *  gigabit speeds.
5085  **/
5086 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5087                                           u16 *duplex)
5088 {
5089         s32 ret_val;
5090 
5091         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5092         if (ret_val)
5093                 return ret_val;
5094 
5095         if ((hw->mac.type == e1000_ich8lan) &&
5096             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5097                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5098         }
5099 
5100         return ret_val;
5101 }
5102 
5103 /**
5104  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5105  *  @hw: pointer to the HW structure
5106  *
5107  *  Work-around for 82566 Kumeran PCS lock loss:
5108  *  On link status change (i.e. PCI reset, speed change) and link is up and
5109  *  speed is gigabit-
5110  *    0) if workaround is optionally disabled do nothing
5111  *    1) wait 1ms for Kumeran link to come up
5112  *    2) check Kumeran Diagnostic register PCS lock loss bit
5113  *    3) if not set the link is locked (all is good), otherwise...
5114  *    4) reset the PHY
5115  *    5) repeat up to 10 times
5116  *  Note: this is only called for IGP3 copper when speed is 1gb.
5117  **/
5118 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5119 {
5120         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5121         u32 phy_ctrl;
5122         s32 ret_val;
5123         u16 i, data;
5124         bool link;
5125 
5126         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5127                 return 0;
5128 
5129         /* Make sure link is up before proceeding.  If not just return.
5130          * Attempting this while link is negotiating fouled up link
5131          * stability
5132          */
5133         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5134         if (!link)
5135                 return 0;
5136 
5137         for (i = 0; i < 10; i++) {
5138                 /* read once to clear */
5139                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5140                 if (ret_val)
5141                         return ret_val;
5142                 /* and again to get new status */
5143                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5144                 if (ret_val)
5145                         return ret_val;
5146 
5147                 /* check for PCS lock */
5148                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5149                         return 0;
5150 
5151                 /* Issue PHY reset */
5152                 e1000_phy_hw_reset(hw);
5153                 mdelay(5);
5154         }
5155         /* Disable GigE link negotiation */
5156         phy_ctrl = er32(PHY_CTRL);
5157         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5158                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5159         ew32(PHY_CTRL, phy_ctrl);
5160 
5161         /* Call gig speed drop workaround on Gig disable before accessing
5162          * any PHY registers
5163          */
5164         e1000e_gig_downshift_workaround_ich8lan(hw);
5165 
5166         /* unable to acquire PCS lock */
5167         return -E1000_ERR_PHY;
5168 }
5169 
5170 /**
5171  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5172  *  @hw: pointer to the HW structure
5173  *  @state: boolean value used to set the current Kumeran workaround state
5174  *
5175  *  If ICH8, set the current Kumeran workaround state (enabled - true
5176  *  /disabled - false).
5177  **/
5178 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5179                                                   bool state)
5180 {
5181         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5182 
5183         if (hw->mac.type != e1000_ich8lan) {
5184                 e_dbg("Workaround applies to ICH8 only.\n");
5185                 return;
5186         }
5187 
5188         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5189 }
5190 
5191 /**
5192  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5193  *  @hw: pointer to the HW structure
5194  *
5195  *  Workaround for 82566 power-down on D3 entry:
5196  *    1) disable gigabit link
5197  *    2) write VR power-down enable
5198  *    3) read it back
5199  *  Continue if successful, else issue LCD reset and repeat
5200  **/
5201 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5202 {
5203         u32 reg;
5204         u16 data;
5205         u8 retry = 0;
5206 
5207         if (hw->phy.type != e1000_phy_igp_3)
5208                 return;
5209 
5210         /* Try the workaround twice (if needed) */
5211         do {
5212                 /* Disable link */
5213                 reg = er32(PHY_CTRL);
5214                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5215                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5216                 ew32(PHY_CTRL, reg);
5217 
5218                 /* Call gig speed drop workaround on Gig disable before
5219                  * accessing any PHY registers
5220                  */
5221                 if (hw->mac.type == e1000_ich8lan)
5222                         e1000e_gig_downshift_workaround_ich8lan(hw);
5223 
5224                 /* Write VR power-down enable */
5225                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5226                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5227                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5228 
5229                 /* Read it back and test */
5230                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5231                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5232                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5233                         break;
5234 
5235                 /* Issue PHY reset and repeat at most one more time */
5236                 reg = er32(CTRL);
5237                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5238                 retry++;
5239         } while (retry);
5240 }
5241 
5242 /**
5243  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5244  *  @hw: pointer to the HW structure
5245  *
5246  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5247  *  LPLU, Gig disable, MDIC PHY reset):
5248  *    1) Set Kumeran Near-end loopback
5249  *    2) Clear Kumeran Near-end loopback
5250  *  Should only be called for ICH8[m] devices with any 1G Phy.
5251  **/
5252 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5253 {
5254         s32 ret_val;
5255         u16 reg_data;
5256 
5257         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5258                 return;
5259 
5260         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5261                                        &reg_data);
5262         if (ret_val)
5263                 return;
5264         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5265         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5266                                         reg_data);
5267         if (ret_val)
5268                 return;
5269         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5270         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5271 }
5272 
5273 /**
5274  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5275  *  @hw: pointer to the HW structure
5276  *
5277  *  During S0 to Sx transition, it is possible the link remains at gig
5278  *  instead of negotiating to a lower speed.  Before going to Sx, set
5279  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5280  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5281  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5282  *  needs to be written.
5283  *  Parts that support (and are linked to a partner which support) EEE in
5284  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5285  *  than 10Mbps w/o EEE.
5286  **/
5287 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5288 {
5289         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5290         u32 phy_ctrl;
5291         s32 ret_val;
5292 
5293         phy_ctrl = er32(PHY_CTRL);
5294         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5295 
5296         if (hw->phy.type == e1000_phy_i217) {
5297                 u16 phy_reg, device_id = hw->adapter->pdev->device;
5298 
5299                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5300                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5301                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5302                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5303                     (hw->mac.type >= e1000_pch_spt)) {
5304                         u32 fextnvm6 = er32(FEXTNVM6);
5305 
5306                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5307                 }
5308 
5309                 ret_val = hw->phy.ops.acquire(hw);
5310                 if (ret_val)
5311                         goto out;
5312 
5313                 if (!dev_spec->eee_disable) {
5314                         u16 eee_advert;
5315 
5316                         ret_val =
5317                             e1000_read_emi_reg_locked(hw,
5318                                                       I217_EEE_ADVERTISEMENT,
5319                                                       &eee_advert);
5320                         if (ret_val)
5321                                 goto release;
5322 
5323                         /* Disable LPLU if both link partners support 100BaseT
5324                          * EEE and 100Full is advertised on both ends of the
5325                          * link, and enable Auto Enable LPI since there will
5326                          * be no driver to enable LPI while in Sx.
5327                          */
5328                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5329                             (dev_spec->eee_lp_ability &
5330                              I82579_EEE_100_SUPPORTED) &&
5331                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5332                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5333                                               E1000_PHY_CTRL_NOND0A_LPLU);
5334 
5335                                 /* Set Auto Enable LPI after link up */
5336                                 e1e_rphy_locked(hw,
5337                                                 I217_LPI_GPIO_CTRL, &phy_reg);
5338                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5339                                 e1e_wphy_locked(hw,
5340                                                 I217_LPI_GPIO_CTRL, phy_reg);
5341                         }
5342                 }
5343 
5344                 /* For i217 Intel Rapid Start Technology support,
5345                  * when the system is going into Sx and no manageability engine
5346                  * is present, the driver must configure proxy to reset only on
5347                  * power good.  LPI (Low Power Idle) state must also reset only
5348                  * on power good, as well as the MTA (Multicast table array).
5349                  * The SMBus release must also be disabled on LCD reset.
5350                  */
5351                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5352                         /* Enable proxy to reset only on power good. */
5353                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5354                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5355                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5356 
5357                         /* Set bit enable LPI (EEE) to reset only on
5358                          * power good.
5359                          */
5360                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5361                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5362                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5363 
5364                         /* Disable the SMB release on LCD reset. */
5365                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5366                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5367                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5368                 }
5369 
5370                 /* Enable MTA to reset for Intel Rapid Start Technology
5371                  * Support
5372                  */
5373                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5374                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5375                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5376 
5377 release:
5378                 hw->phy.ops.release(hw);
5379         }
5380 out:
5381         ew32(PHY_CTRL, phy_ctrl);
5382 
5383         if (hw->mac.type == e1000_ich8lan)
5384                 e1000e_gig_downshift_workaround_ich8lan(hw);
5385 
5386         if (hw->mac.type >= e1000_pchlan) {
5387                 e1000_oem_bits_config_ich8lan(hw, false);
5388 
5389                 /* Reset PHY to activate OEM bits on 82577/8 */
5390                 if (hw->mac.type == e1000_pchlan)
5391                         e1000e_phy_hw_reset_generic(hw);
5392 
5393                 ret_val = hw->phy.ops.acquire(hw);
5394                 if (ret_val)
5395                         return;
5396                 e1000_write_smbus_addr(hw);
5397                 hw->phy.ops.release(hw);
5398         }
5399 }
5400 
5401 /**
5402  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5403  *  @hw: pointer to the HW structure
5404  *
5405  *  During Sx to S0 transitions on non-managed devices or managed devices
5406  *  on which PHY resets are not blocked, if the PHY registers cannot be
5407  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5408  *  the PHY.
5409  *  On i217, setup Intel Rapid Start Technology.
5410  **/
5411 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5412 {
5413         s32 ret_val;
5414 
5415         if (hw->mac.type < e1000_pch2lan)
5416                 return;
5417 
5418         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5419         if (ret_val) {
5420                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5421                 return;
5422         }
5423 
5424         /* For i217 Intel Rapid Start Technology support when the system
5425          * is transitioning from Sx and no manageability engine is present
5426          * configure SMBus to restore on reset, disable proxy, and enable
5427          * the reset on MTA (Multicast table array).
5428          */
5429         if (hw->phy.type == e1000_phy_i217) {
5430                 u16 phy_reg;
5431 
5432                 ret_val = hw->phy.ops.acquire(hw);
5433                 if (ret_val) {
5434                         e_dbg("Failed to setup iRST\n");
5435                         return;
5436                 }
5437 
5438                 /* Clear Auto Enable LPI after link up */
5439                 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5440                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5441                 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5442 
5443                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5444                         /* Restore clear on SMB if no manageability engine
5445                          * is present
5446                          */
5447                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5448                         if (ret_val)
5449                                 goto release;
5450                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5451                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5452 
5453                         /* Disable Proxy */
5454                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5455                 }
5456                 /* Enable reset on MTA */
5457                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5458                 if (ret_val)
5459                         goto release;
5460                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5461                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5462 release:
5463                 if (ret_val)
5464                         e_dbg("Error %d in resume workarounds\n", ret_val);
5465                 hw->phy.ops.release(hw);
5466         }
5467 }
5468 
5469 /**
5470  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5471  *  @hw: pointer to the HW structure
5472  *
5473  *  Return the LED back to the default configuration.
5474  **/
5475 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5476 {
5477         if (hw->phy.type == e1000_phy_ife)
5478                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5479 
5480         ew32(LEDCTL, hw->mac.ledctl_default);
5481         return 0;
5482 }
5483 
5484 /**
5485  *  e1000_led_on_ich8lan - Turn LEDs on
5486  *  @hw: pointer to the HW structure
5487  *
5488  *  Turn on the LEDs.
5489  **/
5490 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5491 {
5492         if (hw->phy.type == e1000_phy_ife)
5493                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5494                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5495 
5496         ew32(LEDCTL, hw->mac.ledctl_mode2);
5497         return 0;
5498 }
5499 
5500 /**
5501  *  e1000_led_off_ich8lan - Turn LEDs off
5502  *  @hw: pointer to the HW structure
5503  *
5504  *  Turn off the LEDs.
5505  **/
5506 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5507 {
5508         if (hw->phy.type == e1000_phy_ife)
5509                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5510                                 (IFE_PSCL_PROBE_MODE |
5511                                  IFE_PSCL_PROBE_LEDS_OFF));
5512 
5513         ew32(LEDCTL, hw->mac.ledctl_mode1);
5514         return 0;
5515 }
5516 
5517 /**
5518  *  e1000_setup_led_pchlan - Configures SW controllable LED
5519  *  @hw: pointer to the HW structure
5520  *
5521  *  This prepares the SW controllable LED for use.
5522  **/
5523 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5524 {
5525         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5526 }
5527 
5528 /**
5529  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5530  *  @hw: pointer to the HW structure
5531  *
5532  *  Return the LED back to the default configuration.
5533  **/
5534 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5535 {
5536         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5537 }
5538 
5539 /**
5540  *  e1000_led_on_pchlan - Turn LEDs on
5541  *  @hw: pointer to the HW structure
5542  *
5543  *  Turn on the LEDs.
5544  **/
5545 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5546 {
5547         u16 data = (u16)hw->mac.ledctl_mode2;
5548         u32 i, led;
5549 
5550         /* If no link, then turn LED on by setting the invert bit
5551          * for each LED that's mode is "link_up" in ledctl_mode2.
5552          */
5553         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5554                 for (i = 0; i < 3; i++) {
5555                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5556                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5557                             E1000_LEDCTL_MODE_LINK_UP)
5558                                 continue;
5559                         if (led & E1000_PHY_LED0_IVRT)
5560                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5561                         else
5562                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5563                 }
5564         }
5565 
5566         return e1e_wphy(hw, HV_LED_CONFIG, data);
5567 }
5568 
5569 /**
5570  *  e1000_led_off_pchlan - Turn LEDs off
5571  *  @hw: pointer to the HW structure
5572  *
5573  *  Turn off the LEDs.
5574  **/
5575 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5576 {
5577         u16 data = (u16)hw->mac.ledctl_mode1;
5578         u32 i, led;
5579 
5580         /* If no link, then turn LED off by clearing the invert bit
5581          * for each LED that's mode is "link_up" in ledctl_mode1.
5582          */
5583         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5584                 for (i = 0; i < 3; i++) {
5585                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5586                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5587                             E1000_LEDCTL_MODE_LINK_UP)
5588                                 continue;
5589                         if (led & E1000_PHY_LED0_IVRT)
5590                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5591                         else
5592                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5593                 }
5594         }
5595 
5596         return e1e_wphy(hw, HV_LED_CONFIG, data);
5597 }
5598 
5599 /**
5600  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5601  *  @hw: pointer to the HW structure
5602  *
5603  *  Read appropriate register for the config done bit for completion status
5604  *  and configure the PHY through s/w for EEPROM-less parts.
5605  *
5606  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5607  *  config done bit, so only an error is logged and continues.  If we were
5608  *  to return with error, EEPROM-less silicon would not be able to be reset
5609  *  or change link.
5610  **/
5611 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5612 {
5613         s32 ret_val = 0;
5614         u32 bank = 0;
5615         u32 status;
5616 
5617         e1000e_get_cfg_done_generic(hw);
5618 
5619         /* Wait for indication from h/w that it has completed basic config */
5620         if (hw->mac.type >= e1000_ich10lan) {
5621                 e1000_lan_init_done_ich8lan(hw);
5622         } else {
5623                 ret_val = e1000e_get_auto_rd_done(hw);
5624                 if (ret_val) {
5625                         /* When auto config read does not complete, do not
5626                          * return with an error. This can happen in situations
5627                          * where there is no eeprom and prevents getting link.
5628                          */
5629                         e_dbg("Auto Read Done did not complete\n");
5630                         ret_val = 0;
5631                 }
5632         }
5633 
5634         /* Clear PHY Reset Asserted bit */
5635         status = er32(STATUS);
5636         if (status & E1000_STATUS_PHYRA)
5637                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5638         else
5639                 e_dbg("PHY Reset Asserted not set - needs delay\n");
5640 
5641         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5642         if (hw->mac.type <= e1000_ich9lan) {
5643                 if (!(er32(EECD) & E1000_EECD_PRES) &&
5644                     (hw->phy.type == e1000_phy_igp_3)) {
5645                         e1000e_phy_init_script_igp3(hw);
5646                 }
5647         } else {
5648                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5649                         /* Maybe we should do a basic PHY config */
5650                         e_dbg("EEPROM not present\n");
5651                         ret_val = -E1000_ERR_CONFIG;
5652                 }
5653         }
5654 
5655         return ret_val;
5656 }
5657 
5658 /**
5659  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5660  * @hw: pointer to the HW structure
5661  *
5662  * In the case of a PHY power down to save power, or to turn off link during a
5663  * driver unload, or wake on lan is not enabled, remove the link.
5664  **/
5665 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5666 {
5667         /* If the management interface is not enabled, then power down */
5668         if (!(hw->mac.ops.check_mng_mode(hw) ||
5669               hw->phy.ops.check_reset_block(hw)))
5670                 e1000_power_down_phy_copper(hw);
5671 }
5672 
5673 /**
5674  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5675  *  @hw: pointer to the HW structure
5676  *
5677  *  Clears hardware counters specific to the silicon family and calls
5678  *  clear_hw_cntrs_generic to clear all general purpose counters.
5679  **/
5680 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5681 {
5682         u16 phy_data;
5683         s32 ret_val;
5684 
5685         e1000e_clear_hw_cntrs_base(hw);
5686 
5687         er32(ALGNERRC);
5688         er32(RXERRC);
5689         er32(TNCRS);
5690         er32(CEXTERR);
5691         er32(TSCTC);
5692         er32(TSCTFC);
5693 
5694         er32(MGTPRC);
5695         er32(MGTPDC);
5696         er32(MGTPTC);
5697 
5698         er32(IAC);
5699         er32(ICRXOC);
5700 
5701         /* Clear PHY statistics registers */
5702         if ((hw->phy.type == e1000_phy_82578) ||
5703             (hw->phy.type == e1000_phy_82579) ||
5704             (hw->phy.type == e1000_phy_i217) ||
5705             (hw->phy.type == e1000_phy_82577)) {
5706                 ret_val = hw->phy.ops.acquire(hw);
5707                 if (ret_val)
5708                         return;
5709                 ret_val = hw->phy.ops.set_page(hw,
5710                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5711                 if (ret_val)
5712                         goto release;
5713                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5714                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5715                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5716                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5717                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5718                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5719                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5720                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5721                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5722                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5723                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5724                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5725                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5726                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5727 release:
5728                 hw->phy.ops.release(hw);
5729         }
5730 }
5731 
5732 static const struct e1000_mac_operations ich8_mac_ops = {
5733         /* check_mng_mode dependent on mac type */
5734         .check_for_link         = e1000_check_for_copper_link_ich8lan,
5735         /* cleanup_led dependent on mac type */
5736         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
5737         .get_bus_info           = e1000_get_bus_info_ich8lan,
5738         .set_lan_id             = e1000_set_lan_id_single_port,
5739         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
5740         /* led_on dependent on mac type */
5741         /* led_off dependent on mac type */
5742         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
5743         .reset_hw               = e1000_reset_hw_ich8lan,
5744         .init_hw                = e1000_init_hw_ich8lan,
5745         .setup_link             = e1000_setup_link_ich8lan,
5746         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5747         /* id_led_init dependent on mac type */
5748         .config_collision_dist  = e1000e_config_collision_dist_generic,
5749         .rar_set                = e1000e_rar_set_generic,
5750         .rar_get_count          = e1000e_rar_get_count_generic,
5751 };
5752 
5753 static const struct e1000_phy_operations ich8_phy_ops = {
5754         .acquire                = e1000_acquire_swflag_ich8lan,
5755         .check_reset_block      = e1000_check_reset_block_ich8lan,
5756         .commit                 = NULL,
5757         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
5758         .get_cable_length       = e1000e_get_cable_length_igp_2,
5759         .read_reg               = e1000e_read_phy_reg_igp,
5760         .release                = e1000_release_swflag_ich8lan,
5761         .reset                  = e1000_phy_hw_reset_ich8lan,
5762         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
5763         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
5764         .write_reg              = e1000e_write_phy_reg_igp,
5765 };
5766 
5767 static const struct e1000_nvm_operations ich8_nvm_ops = {
5768         .acquire                = e1000_acquire_nvm_ich8lan,
5769         .read                   = e1000_read_nvm_ich8lan,
5770         .release                = e1000_release_nvm_ich8lan,
5771         .reload                 = e1000e_reload_nvm_generic,
5772         .update                 = e1000_update_nvm_checksum_ich8lan,
5773         .valid_led_default      = e1000_valid_led_default_ich8lan,
5774         .validate               = e1000_validate_nvm_checksum_ich8lan,
5775         .write                  = e1000_write_nvm_ich8lan,
5776 };
5777 
5778 static const struct e1000_nvm_operations spt_nvm_ops = {
5779         .acquire                = e1000_acquire_nvm_ich8lan,
5780         .release                = e1000_release_nvm_ich8lan,
5781         .read                   = e1000_read_nvm_spt,
5782         .update                 = e1000_update_nvm_checksum_spt,
5783         .reload                 = e1000e_reload_nvm_generic,
5784         .valid_led_default      = e1000_valid_led_default_ich8lan,
5785         .validate               = e1000_validate_nvm_checksum_ich8lan,
5786         .write                  = e1000_write_nvm_ich8lan,
5787 };
5788 
5789 const struct e1000_info e1000_ich8_info = {
5790         .mac                    = e1000_ich8lan,
5791         .flags                  = FLAG_HAS_WOL
5792                                   | FLAG_IS_ICH
5793                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5794                                   | FLAG_HAS_AMT
5795                                   | FLAG_HAS_FLASH
5796                                   | FLAG_APME_IN_WUC,
5797         .pba                    = 8,
5798         .max_hw_frame_size      = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5799         .get_variants           = e1000_get_variants_ich8lan,
5800         .mac_ops                = &ich8_mac_ops,
5801         .phy_ops                = &ich8_phy_ops,
5802         .nvm_ops                = &ich8_nvm_ops,
5803 };
5804 
5805 const struct e1000_info e1000_ich9_info = {
5806         .mac                    = e1000_ich9lan,
5807         .flags                  = FLAG_HAS_JUMBO_FRAMES
5808                                   | FLAG_IS_ICH
5809                                   | FLAG_HAS_WOL
5810                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5811                                   | FLAG_HAS_AMT
5812                                   | FLAG_HAS_FLASH
5813                                   | FLAG_APME_IN_WUC,
5814         .pba                    = 18,
5815         .max_hw_frame_size      = DEFAULT_JUMBO,
5816         .get_variants           = e1000_get_variants_ich8lan,
5817         .mac_ops                = &ich8_mac_ops,
5818         .phy_ops                = &ich8_phy_ops,
5819         .nvm_ops                = &ich8_nvm_ops,
5820 };
5821 
5822 const struct e1000_info e1000_ich10_info = {
5823         .mac                    = e1000_ich10lan,
5824         .flags                  = FLAG_HAS_JUMBO_FRAMES
5825                                   | FLAG_IS_ICH
5826                                   | FLAG_HAS_WOL
5827                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5828                                   | FLAG_HAS_AMT
5829                                   | FLAG_HAS_FLASH
5830                                   | FLAG_APME_IN_WUC,
5831         .pba                    = 18,
5832         .max_hw_frame_size      = DEFAULT_JUMBO,
5833         .get_variants           = e1000_get_variants_ich8lan,
5834         .mac_ops                = &ich8_mac_ops,
5835         .phy_ops                = &ich8_phy_ops,
5836         .nvm_ops                = &ich8_nvm_ops,
5837 };
5838 
5839 const struct e1000_info e1000_pch_info = {
5840         .mac                    = e1000_pchlan,
5841         .flags                  = FLAG_IS_ICH
5842                                   | FLAG_HAS_WOL
5843                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5844                                   | FLAG_HAS_AMT
5845                                   | FLAG_HAS_FLASH
5846                                   | FLAG_HAS_JUMBO_FRAMES
5847                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5848                                   | FLAG_APME_IN_WUC,
5849         .flags2                 = FLAG2_HAS_PHY_STATS,
5850         .pba                    = 26,
5851         .max_hw_frame_size      = 4096,
5852         .get_variants           = e1000_get_variants_ich8lan,
5853         .mac_ops                = &ich8_mac_ops,
5854         .phy_ops                = &ich8_phy_ops,
5855         .nvm_ops                = &ich8_nvm_ops,
5856 };
5857 
5858 const struct e1000_info e1000_pch2_info = {
5859         .mac                    = e1000_pch2lan,
5860         .flags                  = FLAG_IS_ICH
5861                                   | FLAG_HAS_WOL
5862                                   | FLAG_HAS_HW_TIMESTAMP
5863                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5864                                   | FLAG_HAS_AMT
5865                                   | FLAG_HAS_FLASH
5866                                   | FLAG_HAS_JUMBO_FRAMES
5867                                   | FLAG_APME_IN_WUC,
5868         .flags2                 = FLAG2_HAS_PHY_STATS
5869                                   | FLAG2_HAS_EEE
5870                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5871         .pba                    = 26,
5872         .max_hw_frame_size      = 9022,
5873         .get_variants           = e1000_get_variants_ich8lan,
5874         .mac_ops                = &ich8_mac_ops,
5875         .phy_ops                = &ich8_phy_ops,
5876         .nvm_ops                = &ich8_nvm_ops,
5877 };
5878 
5879 const struct e1000_info e1000_pch_lpt_info = {
5880         .mac                    = e1000_pch_lpt,
5881         .flags                  = FLAG_IS_ICH
5882                                   | FLAG_HAS_WOL
5883                                   | FLAG_HAS_HW_TIMESTAMP
5884                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5885                                   | FLAG_HAS_AMT
5886                                   | FLAG_HAS_FLASH
5887                                   | FLAG_HAS_JUMBO_FRAMES
5888                                   | FLAG_APME_IN_WUC,
5889         .flags2                 = FLAG2_HAS_PHY_STATS
5890                                   | FLAG2_HAS_EEE
5891                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5892         .pba                    = 26,
5893         .max_hw_frame_size      = 9022,
5894         .get_variants           = e1000_get_variants_ich8lan,
5895         .mac_ops                = &ich8_mac_ops,
5896         .phy_ops                = &ich8_phy_ops,
5897         .nvm_ops                = &ich8_nvm_ops,
5898 };
5899 
5900 const struct e1000_info e1000_pch_spt_info = {
5901         .mac                    = e1000_pch_spt,
5902         .flags                  = FLAG_IS_ICH
5903                                   | FLAG_HAS_WOL
5904                                   | FLAG_HAS_HW_TIMESTAMP
5905                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5906                                   | FLAG_HAS_AMT
5907                                   | FLAG_HAS_FLASH
5908                                   | FLAG_HAS_JUMBO_FRAMES
5909                                   | FLAG_APME_IN_WUC,
5910         .flags2                 = FLAG2_HAS_PHY_STATS
5911                                   | FLAG2_HAS_EEE,
5912         .pba                    = 26,
5913         .max_hw_frame_size      = 9022,
5914         .get_variants           = e1000_get_variants_ich8lan,
5915         .mac_ops                = &ich8_mac_ops,
5916         .phy_ops                = &ich8_phy_ops,
5917         .nvm_ops                = &spt_nvm_ops,
5918 };
5919 
5920 const struct e1000_info e1000_pch_cnp_info = {
5921         .mac                    = e1000_pch_cnp,
5922         .flags                  = FLAG_IS_ICH
5923                                   | FLAG_HAS_WOL
5924                                   | FLAG_HAS_HW_TIMESTAMP
5925                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5926                                   | FLAG_HAS_AMT
5927                                   | FLAG_HAS_FLASH
5928                                   | FLAG_HAS_JUMBO_FRAMES
5929                                   | FLAG_APME_IN_WUC,
5930         .flags2                 = FLAG2_HAS_PHY_STATS
5931                                   | FLAG2_HAS_EEE,
5932         .pba                    = 26,
5933         .max_hw_frame_size      = 9022,
5934         .get_variants           = e1000_get_variants_ich8lan,
5935         .mac_ops                = &ich8_mac_ops,
5936         .phy_ops                = &ich8_phy_ops,
5937         .nvm_ops                = &spt_nvm_ops,
5938 };