This source file includes following definitions.
- e1000_set_phy_type
- e1000_phy_init_script
- e1000_set_mac_type
- e1000_set_media_type
- e1000_reset_hw
- e1000_init_hw
- e1000_adjust_serdes_amplitude
- e1000_setup_link
- e1000_setup_fiber_serdes_link
- e1000_copper_link_rtl_setup
- gbe_dhg_phy_setup
- e1000_copper_link_preconfig
- e1000_copper_link_igp_setup
- e1000_copper_link_mgp_setup
- e1000_copper_link_autoneg
- e1000_copper_link_postconfig
- e1000_setup_copper_link
- e1000_phy_setup_autoneg
- e1000_phy_force_speed_duplex
- e1000_config_collision_dist
- e1000_config_mac_to_phy
- e1000_force_mac_fc
- e1000_config_fc_after_link_up
- e1000_check_for_serdes_link_generic
- e1000_check_for_link
- e1000_get_speed_and_duplex
- e1000_wait_autoneg
- e1000_raise_mdi_clk
- e1000_lower_mdi_clk
- e1000_shift_out_mdi_bits
- e1000_shift_in_mdi_bits
- e1000_read_phy_reg
- e1000_read_phy_reg_ex
- e1000_write_phy_reg
- e1000_write_phy_reg_ex
- e1000_phy_hw_reset
- e1000_phy_reset
- e1000_detect_gig_phy
- e1000_phy_reset_dsp
- e1000_phy_igp_get_info
- e1000_phy_m88_get_info
- e1000_phy_get_info
- e1000_validate_mdi_setting
- e1000_init_eeprom_params
- e1000_raise_ee_clk
- e1000_lower_ee_clk
- e1000_shift_out_ee_bits
- e1000_shift_in_ee_bits
- e1000_acquire_eeprom
- e1000_standby_eeprom
- e1000_release_eeprom
- e1000_spi_eeprom_ready
- e1000_read_eeprom
- e1000_do_read_eeprom
- e1000_validate_eeprom_checksum
- e1000_update_eeprom_checksum
- e1000_write_eeprom
- e1000_do_write_eeprom
- e1000_write_eeprom_spi
- e1000_write_eeprom_microwire
- e1000_read_mac_addr
- e1000_init_rx_addrs
- e1000_hash_mc_addr
- e1000_rar_set
- e1000_write_vfta
- e1000_clear_vfta
- e1000_id_led_init
- e1000_setup_led
- e1000_cleanup_led
- e1000_led_on
- e1000_led_off
- e1000_clear_hw_cntrs
- e1000_reset_adaptive
- e1000_update_adaptive
- e1000_get_bus_info
- e1000_write_reg_io
- e1000_get_cable_length
- e1000_check_polarity
- e1000_check_downshift
- e1000_1000Mb_check_cable_length
- e1000_config_dsp_after_link_change
- e1000_set_phy_mode
- e1000_set_d3_lplu_state
- e1000_set_vco_speed
- e1000_enable_mng_pass_thru
- e1000_polarity_reversal_workaround
- e1000_get_auto_rd_done
- e1000_get_phy_cfg_done
1
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6
7
8 #include "e1000.h"
9
10 static s32 e1000_check_downshift(struct e1000_hw *hw);
11 static s32 e1000_check_polarity(struct e1000_hw *hw,
12 e1000_rev_polarity *polarity);
13 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
14 static void e1000_clear_vfta(struct e1000_hw *hw);
15 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
16 bool link_up);
17 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
18 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
19 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
20 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
21 u16 *max_length);
22 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
23 static s32 e1000_id_led_init(struct e1000_hw *hw);
24 static void e1000_init_rx_addrs(struct e1000_hw *hw);
25 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
26 struct e1000_phy_info *phy_info);
27 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
28 struct e1000_phy_info *phy_info);
29 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
30 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
31 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
32 static s32 e1000_set_phy_type(struct e1000_hw *hw);
33 static void e1000_phy_init_script(struct e1000_hw *hw);
34 static s32 e1000_setup_copper_link(struct e1000_hw *hw);
35 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
36 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
37 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
38 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
39 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
40 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
41 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
42 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
43 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
44 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
45 u16 words, u16 *data);
46 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
47 u16 words, u16 *data);
48 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
49 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
50 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
51 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
52 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
53 u16 phy_data);
54 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
55 u16 *phy_data);
56 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
57 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
58 static void e1000_release_eeprom(struct e1000_hw *hw);
59 static void e1000_standby_eeprom(struct e1000_hw *hw);
60 static s32 e1000_set_vco_speed(struct e1000_hw *hw);
61 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
62 static s32 e1000_set_phy_mode(struct e1000_hw *hw);
63 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
64 u16 *data);
65 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
66 u16 *data);
67
68
69 static const
70 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
71 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
72 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
73 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
74 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
75 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
76 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
77 100,
78 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
79 110, 110,
80 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
81 120, 120
82 };
83
84 static DEFINE_MUTEX(e1000_eeprom_lock);
85 static DEFINE_SPINLOCK(e1000_phy_lock);
86
87
88
89
90
91 static s32 e1000_set_phy_type(struct e1000_hw *hw)
92 {
93 if (hw->mac_type == e1000_undefined)
94 return -E1000_ERR_PHY_TYPE;
95
96 switch (hw->phy_id) {
97 case M88E1000_E_PHY_ID:
98 case M88E1000_I_PHY_ID:
99 case M88E1011_I_PHY_ID:
100 case M88E1111_I_PHY_ID:
101 case M88E1118_E_PHY_ID:
102 hw->phy_type = e1000_phy_m88;
103 break;
104 case IGP01E1000_I_PHY_ID:
105 if (hw->mac_type == e1000_82541 ||
106 hw->mac_type == e1000_82541_rev_2 ||
107 hw->mac_type == e1000_82547 ||
108 hw->mac_type == e1000_82547_rev_2)
109 hw->phy_type = e1000_phy_igp;
110 break;
111 case RTL8211B_PHY_ID:
112 hw->phy_type = e1000_phy_8211;
113 break;
114 case RTL8201N_PHY_ID:
115 hw->phy_type = e1000_phy_8201;
116 break;
117 default:
118
119 hw->phy_type = e1000_phy_undefined;
120 return -E1000_ERR_PHY_TYPE;
121 }
122
123 return E1000_SUCCESS;
124 }
125
126
127
128
129
130 static void e1000_phy_init_script(struct e1000_hw *hw)
131 {
132 u32 ret_val;
133 u16 phy_saved_data;
134
135 if (hw->phy_init_script) {
136 msleep(20);
137
138
139
140
141 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
142
143
144 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
145 msleep(20);
146
147 e1000_write_phy_reg(hw, 0x0000, 0x0140);
148 msleep(5);
149
150 switch (hw->mac_type) {
151 case e1000_82541:
152 case e1000_82547:
153 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
154 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
155 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
156 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
157 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
158 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
159 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
160 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
161 e1000_write_phy_reg(hw, 0x2010, 0x0008);
162 break;
163
164 case e1000_82541_rev_2:
165 case e1000_82547_rev_2:
166 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
167 break;
168 default:
169 break;
170 }
171
172 e1000_write_phy_reg(hw, 0x0000, 0x3300);
173 msleep(20);
174
175
176 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
177
178 if (hw->mac_type == e1000_82547) {
179 u16 fused, fine, coarse;
180
181
182 e1000_read_phy_reg(hw,
183 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
184 &fused);
185
186 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
187 e1000_read_phy_reg(hw,
188 IGP01E1000_ANALOG_FUSE_STATUS,
189 &fused);
190
191 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
192 coarse =
193 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
194
195 if (coarse >
196 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
197 coarse -=
198 IGP01E1000_ANALOG_FUSE_COARSE_10;
199 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
200 } else if (coarse ==
201 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
202 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
203
204 fused =
205 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
206 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
207 (coarse &
208 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
209
210 e1000_write_phy_reg(hw,
211 IGP01E1000_ANALOG_FUSE_CONTROL,
212 fused);
213 e1000_write_phy_reg(hw,
214 IGP01E1000_ANALOG_FUSE_BYPASS,
215 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
216 }
217 }
218 }
219 }
220
221
222
223
224
225 s32 e1000_set_mac_type(struct e1000_hw *hw)
226 {
227 switch (hw->device_id) {
228 case E1000_DEV_ID_82542:
229 switch (hw->revision_id) {
230 case E1000_82542_2_0_REV_ID:
231 hw->mac_type = e1000_82542_rev2_0;
232 break;
233 case E1000_82542_2_1_REV_ID:
234 hw->mac_type = e1000_82542_rev2_1;
235 break;
236 default:
237
238 return -E1000_ERR_MAC_TYPE;
239 }
240 break;
241 case E1000_DEV_ID_82543GC_FIBER:
242 case E1000_DEV_ID_82543GC_COPPER:
243 hw->mac_type = e1000_82543;
244 break;
245 case E1000_DEV_ID_82544EI_COPPER:
246 case E1000_DEV_ID_82544EI_FIBER:
247 case E1000_DEV_ID_82544GC_COPPER:
248 case E1000_DEV_ID_82544GC_LOM:
249 hw->mac_type = e1000_82544;
250 break;
251 case E1000_DEV_ID_82540EM:
252 case E1000_DEV_ID_82540EM_LOM:
253 case E1000_DEV_ID_82540EP:
254 case E1000_DEV_ID_82540EP_LOM:
255 case E1000_DEV_ID_82540EP_LP:
256 hw->mac_type = e1000_82540;
257 break;
258 case E1000_DEV_ID_82545EM_COPPER:
259 case E1000_DEV_ID_82545EM_FIBER:
260 hw->mac_type = e1000_82545;
261 break;
262 case E1000_DEV_ID_82545GM_COPPER:
263 case E1000_DEV_ID_82545GM_FIBER:
264 case E1000_DEV_ID_82545GM_SERDES:
265 hw->mac_type = e1000_82545_rev_3;
266 break;
267 case E1000_DEV_ID_82546EB_COPPER:
268 case E1000_DEV_ID_82546EB_FIBER:
269 case E1000_DEV_ID_82546EB_QUAD_COPPER:
270 hw->mac_type = e1000_82546;
271 break;
272 case E1000_DEV_ID_82546GB_COPPER:
273 case E1000_DEV_ID_82546GB_FIBER:
274 case E1000_DEV_ID_82546GB_SERDES:
275 case E1000_DEV_ID_82546GB_PCIE:
276 case E1000_DEV_ID_82546GB_QUAD_COPPER:
277 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
278 hw->mac_type = e1000_82546_rev_3;
279 break;
280 case E1000_DEV_ID_82541EI:
281 case E1000_DEV_ID_82541EI_MOBILE:
282 case E1000_DEV_ID_82541ER_LOM:
283 hw->mac_type = e1000_82541;
284 break;
285 case E1000_DEV_ID_82541ER:
286 case E1000_DEV_ID_82541GI:
287 case E1000_DEV_ID_82541GI_LF:
288 case E1000_DEV_ID_82541GI_MOBILE:
289 hw->mac_type = e1000_82541_rev_2;
290 break;
291 case E1000_DEV_ID_82547EI:
292 case E1000_DEV_ID_82547EI_MOBILE:
293 hw->mac_type = e1000_82547;
294 break;
295 case E1000_DEV_ID_82547GI:
296 hw->mac_type = e1000_82547_rev_2;
297 break;
298 case E1000_DEV_ID_INTEL_CE4100_GBE:
299 hw->mac_type = e1000_ce4100;
300 break;
301 default:
302
303 return -E1000_ERR_MAC_TYPE;
304 }
305
306 switch (hw->mac_type) {
307 case e1000_82541:
308 case e1000_82547:
309 case e1000_82541_rev_2:
310 case e1000_82547_rev_2:
311 hw->asf_firmware_present = true;
312 break;
313 default:
314 break;
315 }
316
317
318
319
320 if (hw->mac_type == e1000_82543)
321 hw->bad_tx_carr_stats_fd = true;
322
323 if (hw->mac_type > e1000_82544)
324 hw->has_smbus = true;
325
326 return E1000_SUCCESS;
327 }
328
329
330
331
332
333 void e1000_set_media_type(struct e1000_hw *hw)
334 {
335 u32 status;
336
337 if (hw->mac_type != e1000_82543) {
338
339 hw->tbi_compatibility_en = false;
340 }
341
342 switch (hw->device_id) {
343 case E1000_DEV_ID_82545GM_SERDES:
344 case E1000_DEV_ID_82546GB_SERDES:
345 hw->media_type = e1000_media_type_internal_serdes;
346 break;
347 default:
348 switch (hw->mac_type) {
349 case e1000_82542_rev2_0:
350 case e1000_82542_rev2_1:
351 hw->media_type = e1000_media_type_fiber;
352 break;
353 case e1000_ce4100:
354 hw->media_type = e1000_media_type_copper;
355 break;
356 default:
357 status = er32(STATUS);
358 if (status & E1000_STATUS_TBIMODE) {
359 hw->media_type = e1000_media_type_fiber;
360
361 hw->tbi_compatibility_en = false;
362 } else {
363 hw->media_type = e1000_media_type_copper;
364 }
365 break;
366 }
367 }
368 }
369
370
371
372
373
374
375
376 s32 e1000_reset_hw(struct e1000_hw *hw)
377 {
378 u32 ctrl;
379 u32 ctrl_ext;
380 u32 icr;
381 u32 manc;
382 u32 led_ctrl;
383 s32 ret_val;
384
385
386 if (hw->mac_type == e1000_82542_rev2_0) {
387 e_dbg("Disabling MWI on 82542 rev 2.0\n");
388 e1000_pci_clear_mwi(hw);
389 }
390
391
392 e_dbg("Masking off all interrupts\n");
393 ew32(IMC, 0xffffffff);
394
395
396
397
398
399 ew32(RCTL, 0);
400 ew32(TCTL, E1000_TCTL_PSP);
401 E1000_WRITE_FLUSH();
402
403
404 hw->tbi_compatibility_on = false;
405
406
407
408
409 msleep(10);
410
411 ctrl = er32(CTRL);
412
413
414 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
415 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
416 E1000_WRITE_FLUSH();
417 msleep(5);
418 }
419
420
421
422
423
424
425 e_dbg("Issuing a global reset to MAC\n");
426
427 switch (hw->mac_type) {
428 case e1000_82544:
429 case e1000_82540:
430 case e1000_82545:
431 case e1000_82546:
432 case e1000_82541:
433 case e1000_82541_rev_2:
434
435
436
437 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
438 break;
439 case e1000_82545_rev_3:
440 case e1000_82546_rev_3:
441
442 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
443 break;
444 case e1000_ce4100:
445 default:
446 ew32(CTRL, (ctrl | E1000_CTRL_RST));
447 break;
448 }
449
450
451
452
453
454 switch (hw->mac_type) {
455 case e1000_82542_rev2_0:
456 case e1000_82542_rev2_1:
457 case e1000_82543:
458 case e1000_82544:
459
460 udelay(10);
461 ctrl_ext = er32(CTRL_EXT);
462 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
463 ew32(CTRL_EXT, ctrl_ext);
464 E1000_WRITE_FLUSH();
465
466 msleep(2);
467 break;
468 case e1000_82541:
469 case e1000_82541_rev_2:
470 case e1000_82547:
471 case e1000_82547_rev_2:
472
473 msleep(20);
474 break;
475 default:
476
477 ret_val = e1000_get_auto_rd_done(hw);
478 if (ret_val)
479 return ret_val;
480 break;
481 }
482
483
484 if (hw->mac_type >= e1000_82540) {
485 manc = er32(MANC);
486 manc &= ~(E1000_MANC_ARP_EN);
487 ew32(MANC, manc);
488 }
489
490 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
491 e1000_phy_init_script(hw);
492
493
494 led_ctrl = er32(LEDCTL);
495 led_ctrl &= IGP_ACTIVITY_LED_MASK;
496 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
497 ew32(LEDCTL, led_ctrl);
498 }
499
500
501 e_dbg("Masking off all interrupts\n");
502 ew32(IMC, 0xffffffff);
503
504
505 icr = er32(ICR);
506
507
508 if (hw->mac_type == e1000_82542_rev2_0) {
509 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
510 e1000_pci_set_mwi(hw);
511 }
512
513 return E1000_SUCCESS;
514 }
515
516
517
518
519
520
521
522
523
524
525
526 s32 e1000_init_hw(struct e1000_hw *hw)
527 {
528 u32 ctrl;
529 u32 i;
530 s32 ret_val;
531 u32 mta_size;
532 u32 ctrl_ext;
533
534
535 ret_val = e1000_id_led_init(hw);
536 if (ret_val) {
537 e_dbg("Error Initializing Identification LED\n");
538 return ret_val;
539 }
540
541
542 e1000_set_media_type(hw);
543
544
545 e_dbg("Initializing the IEEE VLAN\n");
546 if (hw->mac_type < e1000_82545_rev_3)
547 ew32(VET, 0);
548 e1000_clear_vfta(hw);
549
550
551 if (hw->mac_type == e1000_82542_rev2_0) {
552 e_dbg("Disabling MWI on 82542 rev 2.0\n");
553 e1000_pci_clear_mwi(hw);
554 ew32(RCTL, E1000_RCTL_RST);
555 E1000_WRITE_FLUSH();
556 msleep(5);
557 }
558
559
560
561
562 e1000_init_rx_addrs(hw);
563
564
565 if (hw->mac_type == e1000_82542_rev2_0) {
566 ew32(RCTL, 0);
567 E1000_WRITE_FLUSH();
568 msleep(1);
569 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
570 e1000_pci_set_mwi(hw);
571 }
572
573
574 e_dbg("Zeroing the MTA\n");
575 mta_size = E1000_MC_TBL_SIZE;
576 for (i = 0; i < mta_size; i++) {
577 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
578
579
580
581 E1000_WRITE_FLUSH();
582 }
583
584
585
586
587
588
589 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
590 ctrl = er32(CTRL);
591 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
592 }
593
594 switch (hw->mac_type) {
595 case e1000_82545_rev_3:
596 case e1000_82546_rev_3:
597 break;
598 default:
599
600
601
602 if (hw->bus_type == e1000_bus_type_pcix &&
603 e1000_pcix_get_mmrbc(hw) > 2048)
604 e1000_pcix_set_mmrbc(hw, 2048);
605 break;
606 }
607
608
609 ret_val = e1000_setup_link(hw);
610
611
612 if (hw->mac_type > e1000_82544) {
613 ctrl = er32(TXDCTL);
614 ctrl =
615 (ctrl & ~E1000_TXDCTL_WTHRESH) |
616 E1000_TXDCTL_FULL_TX_DESC_WB;
617 ew32(TXDCTL, ctrl);
618 }
619
620
621
622
623
624
625 e1000_clear_hw_cntrs(hw);
626
627 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
628 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
629 ctrl_ext = er32(CTRL_EXT);
630
631
632
633 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
634 ew32(CTRL_EXT, ctrl_ext);
635 }
636
637 return ret_val;
638 }
639
640
641
642
643
644 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
645 {
646 u16 eeprom_data;
647 s32 ret_val;
648
649 if (hw->media_type != e1000_media_type_internal_serdes)
650 return E1000_SUCCESS;
651
652 switch (hw->mac_type) {
653 case e1000_82545_rev_3:
654 case e1000_82546_rev_3:
655 break;
656 default:
657 return E1000_SUCCESS;
658 }
659
660 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
661 &eeprom_data);
662 if (ret_val)
663 return ret_val;
664
665 if (eeprom_data != EEPROM_RESERVED_WORD) {
666
667 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
668 ret_val =
669 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
670 if (ret_val)
671 return ret_val;
672 }
673
674 return E1000_SUCCESS;
675 }
676
677
678
679
680
681
682
683
684
685
686
687 s32 e1000_setup_link(struct e1000_hw *hw)
688 {
689 u32 ctrl_ext;
690 s32 ret_val;
691 u16 eeprom_data;
692
693
694
695
696
697
698
699
700
701 if (hw->fc == E1000_FC_DEFAULT) {
702 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
703 1, &eeprom_data);
704 if (ret_val) {
705 e_dbg("EEPROM Read Error\n");
706 return -E1000_ERR_EEPROM;
707 }
708 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
709 hw->fc = E1000_FC_NONE;
710 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
711 EEPROM_WORD0F_ASM_DIR)
712 hw->fc = E1000_FC_TX_PAUSE;
713 else
714 hw->fc = E1000_FC_FULL;
715 }
716
717
718
719
720
721 if (hw->mac_type == e1000_82542_rev2_0)
722 hw->fc &= (~E1000_FC_TX_PAUSE);
723
724 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
725 hw->fc &= (~E1000_FC_RX_PAUSE);
726
727 hw->original_fc = hw->fc;
728
729 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);
730
731
732
733
734
735
736
737
738 if (hw->mac_type == e1000_82543) {
739 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
740 1, &eeprom_data);
741 if (ret_val) {
742 e_dbg("EEPROM Read Error\n");
743 return -E1000_ERR_EEPROM;
744 }
745 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
746 SWDPIO__EXT_SHIFT);
747 ew32(CTRL_EXT, ctrl_ext);
748 }
749
750
751 ret_val = (hw->media_type == e1000_media_type_copper) ?
752 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
753
754
755
756
757
758
759 e_dbg("Initializing the Flow Control address, type and timer regs\n");
760
761 ew32(FCT, FLOW_CONTROL_TYPE);
762 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
763 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
764
765 ew32(FCTTV, hw->fc_pause_time);
766
767
768
769
770
771
772
773 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
774 ew32(FCRTL, 0);
775 ew32(FCRTH, 0);
776 } else {
777
778
779
780
781 if (hw->fc_send_xon) {
782 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
783 ew32(FCRTH, hw->fc_high_water);
784 } else {
785 ew32(FCRTL, hw->fc_low_water);
786 ew32(FCRTH, hw->fc_high_water);
787 }
788 }
789 return ret_val;
790 }
791
792
793
794
795
796
797
798
799
800 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
801 {
802 u32 ctrl;
803 u32 status;
804 u32 txcw = 0;
805 u32 i;
806 u32 signal = 0;
807 s32 ret_val;
808
809
810
811
812
813
814
815 ctrl = er32(CTRL);
816 if (hw->media_type == e1000_media_type_fiber)
817 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
818
819 ret_val = e1000_adjust_serdes_amplitude(hw);
820 if (ret_val)
821 return ret_val;
822
823
824 ctrl &= ~(E1000_CTRL_LRST);
825
826
827 ret_val = e1000_set_vco_speed(hw);
828 if (ret_val)
829 return ret_val;
830
831 e1000_config_collision_dist(hw);
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849 switch (hw->fc) {
850 case E1000_FC_NONE:
851
852 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
853 break;
854 case E1000_FC_RX_PAUSE:
855
856
857
858
859
860
861
862 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
863 break;
864 case E1000_FC_TX_PAUSE:
865
866
867
868 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
869 break;
870 case E1000_FC_FULL:
871
872
873
874 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
875 break;
876 default:
877 e_dbg("Flow control param set incorrectly\n");
878 return -E1000_ERR_CONFIG;
879 }
880
881
882
883
884
885
886
887 e_dbg("Auto-negotiation enabled\n");
888
889 ew32(TXCW, txcw);
890 ew32(CTRL, ctrl);
891 E1000_WRITE_FLUSH();
892
893 hw->txcw = txcw;
894 msleep(1);
895
896
897
898
899
900
901
902
903 if (hw->media_type == e1000_media_type_internal_serdes ||
904 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
905 e_dbg("Looking for Link\n");
906 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
907 msleep(10);
908 status = er32(STATUS);
909 if (status & E1000_STATUS_LU)
910 break;
911 }
912 if (i == (LINK_UP_TIMEOUT / 10)) {
913 e_dbg("Never got a valid link from auto-neg!!!\n");
914 hw->autoneg_failed = 1;
915
916
917
918
919
920 ret_val = e1000_check_for_link(hw);
921 if (ret_val) {
922 e_dbg("Error while checking for link\n");
923 return ret_val;
924 }
925 hw->autoneg_failed = 0;
926 } else {
927 hw->autoneg_failed = 0;
928 e_dbg("Valid Link Found\n");
929 }
930 } else {
931 e_dbg("No Signal Detected\n");
932 }
933 return E1000_SUCCESS;
934 }
935
936
937
938
939
940
941
942 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
943 {
944 s32 ret_val;
945
946
947 ret_val = e1000_phy_reset(hw);
948 if (ret_val) {
949 e_dbg("Error Resetting the PHY\n");
950 return ret_val;
951 }
952
953 return E1000_SUCCESS;
954 }
955
956 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
957 {
958 s32 ret_val;
959 u32 ctrl_aux;
960
961 switch (hw->phy_type) {
962 case e1000_phy_8211:
963 ret_val = e1000_copper_link_rtl_setup(hw);
964 if (ret_val) {
965 e_dbg("e1000_copper_link_rtl_setup failed!\n");
966 return ret_val;
967 }
968 break;
969 case e1000_phy_8201:
970
971 ctrl_aux = er32(CTL_AUX);
972 ctrl_aux |= E1000_CTL_AUX_RMII;
973 ew32(CTL_AUX, ctrl_aux);
974 E1000_WRITE_FLUSH();
975
976
977 ctrl_aux = er32(CTL_AUX);
978 ctrl_aux |= 0x4;
979 ctrl_aux &= ~0x2;
980 ew32(CTL_AUX, ctrl_aux);
981 E1000_WRITE_FLUSH();
982 ret_val = e1000_copper_link_rtl_setup(hw);
983
984 if (ret_val) {
985 e_dbg("e1000_copper_link_rtl_setup failed!\n");
986 return ret_val;
987 }
988 break;
989 default:
990 e_dbg("Error Resetting the PHY\n");
991 return E1000_ERR_PHY_TYPE;
992 }
993
994 return E1000_SUCCESS;
995 }
996
997
998
999
1000
1001
1002
1003 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1004 {
1005 u32 ctrl;
1006 s32 ret_val;
1007 u16 phy_data;
1008
1009 ctrl = er32(CTRL);
1010
1011
1012
1013
1014 if (hw->mac_type > e1000_82543) {
1015 ctrl |= E1000_CTRL_SLU;
1016 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1017 ew32(CTRL, ctrl);
1018 } else {
1019 ctrl |=
1020 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1021 ew32(CTRL, ctrl);
1022 ret_val = e1000_phy_hw_reset(hw);
1023 if (ret_val)
1024 return ret_val;
1025 }
1026
1027
1028 ret_val = e1000_detect_gig_phy(hw);
1029 if (ret_val) {
1030 e_dbg("Error, did not detect valid phy.\n");
1031 return ret_val;
1032 }
1033 e_dbg("Phy ID = %x\n", hw->phy_id);
1034
1035
1036 ret_val = e1000_set_phy_mode(hw);
1037 if (ret_val)
1038 return ret_val;
1039
1040 if ((hw->mac_type == e1000_82545_rev_3) ||
1041 (hw->mac_type == e1000_82546_rev_3)) {
1042 ret_val =
1043 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1044 phy_data |= 0x00000008;
1045 ret_val =
1046 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1047 }
1048
1049 if (hw->mac_type <= e1000_82543 ||
1050 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1051 hw->mac_type == e1000_82541_rev_2 ||
1052 hw->mac_type == e1000_82547_rev_2)
1053 hw->phy_reset_disable = false;
1054
1055 return E1000_SUCCESS;
1056 }
1057
1058
1059
1060
1061
1062 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1063 {
1064 u32 led_ctrl;
1065 s32 ret_val;
1066 u16 phy_data;
1067
1068 if (hw->phy_reset_disable)
1069 return E1000_SUCCESS;
1070
1071 ret_val = e1000_phy_reset(hw);
1072 if (ret_val) {
1073 e_dbg("Error Resetting the PHY\n");
1074 return ret_val;
1075 }
1076
1077
1078 msleep(15);
1079
1080 led_ctrl = er32(LEDCTL);
1081 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1082 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1083 ew32(LEDCTL, led_ctrl);
1084
1085
1086 if (hw->phy_type == e1000_phy_igp) {
1087
1088 ret_val = e1000_set_d3_lplu_state(hw, false);
1089 if (ret_val) {
1090 e_dbg("Error Disabling LPLU D3\n");
1091 return ret_val;
1092 }
1093 }
1094
1095
1096 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1097 if (ret_val)
1098 return ret_val;
1099
1100 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1101 hw->dsp_config_state = e1000_dsp_config_disabled;
1102
1103 phy_data &=
1104 ~(IGP01E1000_PSCR_AUTO_MDIX |
1105 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1106 hw->mdix = 1;
1107
1108 } else {
1109 hw->dsp_config_state = e1000_dsp_config_enabled;
1110 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1111
1112 switch (hw->mdix) {
1113 case 1:
1114 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1115 break;
1116 case 2:
1117 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1118 break;
1119 case 0:
1120 default:
1121 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1122 break;
1123 }
1124 }
1125 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1126 if (ret_val)
1127 return ret_val;
1128
1129
1130 if (hw->autoneg) {
1131 e1000_ms_type phy_ms_setting = hw->master_slave;
1132
1133 if (hw->ffe_config_state == e1000_ffe_config_active)
1134 hw->ffe_config_state = e1000_ffe_config_enabled;
1135
1136 if (hw->dsp_config_state == e1000_dsp_config_activated)
1137 hw->dsp_config_state = e1000_dsp_config_enabled;
1138
1139
1140
1141
1142
1143 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1144
1145 ret_val =
1146 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1147 &phy_data);
1148 if (ret_val)
1149 return ret_val;
1150 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1151 ret_val =
1152 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1153 phy_data);
1154 if (ret_val)
1155 return ret_val;
1156
1157 ret_val =
1158 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1159 if (ret_val)
1160 return ret_val;
1161 phy_data &= ~CR_1000T_MS_ENABLE;
1162 ret_val =
1163 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1164 if (ret_val)
1165 return ret_val;
1166 }
1167
1168 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1169 if (ret_val)
1170 return ret_val;
1171
1172
1173 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1174 ((phy_data & CR_1000T_MS_VALUE) ?
1175 e1000_ms_force_master :
1176 e1000_ms_force_slave) : e1000_ms_auto;
1177
1178 switch (phy_ms_setting) {
1179 case e1000_ms_force_master:
1180 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1181 break;
1182 case e1000_ms_force_slave:
1183 phy_data |= CR_1000T_MS_ENABLE;
1184 phy_data &= ~(CR_1000T_MS_VALUE);
1185 break;
1186 case e1000_ms_auto:
1187 phy_data &= ~CR_1000T_MS_ENABLE;
1188 default:
1189 break;
1190 }
1191 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1192 if (ret_val)
1193 return ret_val;
1194 }
1195
1196 return E1000_SUCCESS;
1197 }
1198
1199
1200
1201
1202
1203 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1204 {
1205 s32 ret_val;
1206 u16 phy_data;
1207
1208 if (hw->phy_reset_disable)
1209 return E1000_SUCCESS;
1210
1211
1212 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1213 if (ret_val)
1214 return ret_val;
1215
1216 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1217
1218
1219
1220
1221
1222
1223
1224
1225 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1226
1227 switch (hw->mdix) {
1228 case 1:
1229 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1230 break;
1231 case 2:
1232 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1233 break;
1234 case 3:
1235 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1236 break;
1237 case 0:
1238 default:
1239 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1240 break;
1241 }
1242
1243
1244
1245
1246
1247
1248
1249 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1250 if (hw->disable_polarity_correction == 1)
1251 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1252 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1253 if (ret_val)
1254 return ret_val;
1255
1256 if (hw->phy_revision < M88E1011_I_REV_4) {
1257
1258
1259
1260 ret_val =
1261 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1262 &phy_data);
1263 if (ret_val)
1264 return ret_val;
1265
1266 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1267
1268 if ((hw->phy_revision == E1000_REVISION_2) &&
1269 (hw->phy_id == M88E1111_I_PHY_ID)) {
1270
1271 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1272 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1273 ret_val = e1000_write_phy_reg(hw,
1274 M88E1000_EXT_PHY_SPEC_CTRL,
1275 phy_data);
1276 if (ret_val)
1277 return ret_val;
1278 } else {
1279
1280 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1281 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1282 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1283 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1284 ret_val = e1000_write_phy_reg(hw,
1285 M88E1000_EXT_PHY_SPEC_CTRL,
1286 phy_data);
1287 if (ret_val)
1288 return ret_val;
1289 }
1290 }
1291
1292
1293 ret_val = e1000_phy_reset(hw);
1294 if (ret_val) {
1295 e_dbg("Error Resetting the PHY\n");
1296 return ret_val;
1297 }
1298
1299 return E1000_SUCCESS;
1300 }
1301
1302
1303
1304
1305
1306
1307
1308
1309 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1310 {
1311 s32 ret_val;
1312 u16 phy_data;
1313
1314
1315
1316
1317 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1318
1319
1320
1321
1322 if (hw->autoneg_advertised == 0)
1323 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1324
1325
1326 if (hw->phy_type == e1000_phy_8201)
1327 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1328
1329 e_dbg("Reconfiguring auto-neg advertisement params\n");
1330 ret_val = e1000_phy_setup_autoneg(hw);
1331 if (ret_val) {
1332 e_dbg("Error Setting up Auto-Negotiation\n");
1333 return ret_val;
1334 }
1335 e_dbg("Restarting Auto-Neg\n");
1336
1337
1338
1339
1340 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1341 if (ret_val)
1342 return ret_val;
1343
1344 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1345 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1346 if (ret_val)
1347 return ret_val;
1348
1349
1350
1351
1352 if (hw->wait_autoneg_complete) {
1353 ret_val = e1000_wait_autoneg(hw);
1354 if (ret_val) {
1355 e_dbg
1356 ("Error while waiting for autoneg to complete\n");
1357 return ret_val;
1358 }
1359 }
1360
1361 hw->get_link_status = true;
1362
1363 return E1000_SUCCESS;
1364 }
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1380 {
1381 s32 ret_val;
1382
1383 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
1384 e1000_config_collision_dist(hw);
1385 } else {
1386 ret_val = e1000_config_mac_to_phy(hw);
1387 if (ret_val) {
1388 e_dbg("Error configuring MAC to PHY settings\n");
1389 return ret_val;
1390 }
1391 }
1392 ret_val = e1000_config_fc_after_link_up(hw);
1393 if (ret_val) {
1394 e_dbg("Error Configuring Flow Control\n");
1395 return ret_val;
1396 }
1397
1398
1399 if (hw->phy_type == e1000_phy_igp) {
1400 ret_val = e1000_config_dsp_after_link_change(hw, true);
1401 if (ret_val) {
1402 e_dbg("Error Configuring DSP after link up\n");
1403 return ret_val;
1404 }
1405 }
1406
1407 return E1000_SUCCESS;
1408 }
1409
1410
1411
1412
1413
1414
1415
1416 static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1417 {
1418 s32 ret_val;
1419 u16 i;
1420 u16 phy_data;
1421
1422
1423 ret_val = e1000_copper_link_preconfig(hw);
1424 if (ret_val)
1425 return ret_val;
1426
1427 if (hw->phy_type == e1000_phy_igp) {
1428 ret_val = e1000_copper_link_igp_setup(hw);
1429 if (ret_val)
1430 return ret_val;
1431 } else if (hw->phy_type == e1000_phy_m88) {
1432 ret_val = e1000_copper_link_mgp_setup(hw);
1433 if (ret_val)
1434 return ret_val;
1435 } else {
1436 ret_val = gbe_dhg_phy_setup(hw);
1437 if (ret_val) {
1438 e_dbg("gbe_dhg_phy_setup failed!\n");
1439 return ret_val;
1440 }
1441 }
1442
1443 if (hw->autoneg) {
1444
1445
1446
1447 ret_val = e1000_copper_link_autoneg(hw);
1448 if (ret_val)
1449 return ret_val;
1450 } else {
1451
1452
1453
1454 e_dbg("Forcing speed and duplex\n");
1455 ret_val = e1000_phy_force_speed_duplex(hw);
1456 if (ret_val) {
1457 e_dbg("Error Forcing Speed and Duplex\n");
1458 return ret_val;
1459 }
1460 }
1461
1462
1463
1464
1465 for (i = 0; i < 10; i++) {
1466 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1467 if (ret_val)
1468 return ret_val;
1469 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1470 if (ret_val)
1471 return ret_val;
1472
1473 if (phy_data & MII_SR_LINK_STATUS) {
1474
1475 ret_val = e1000_copper_link_postconfig(hw);
1476 if (ret_val)
1477 return ret_val;
1478
1479 e_dbg("Valid link established!!!\n");
1480 return E1000_SUCCESS;
1481 }
1482 udelay(10);
1483 }
1484
1485 e_dbg("Unable to establish link!!!\n");
1486 return E1000_SUCCESS;
1487 }
1488
1489
1490
1491
1492
1493
1494
1495 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1496 {
1497 s32 ret_val;
1498 u16 mii_autoneg_adv_reg;
1499 u16 mii_1000t_ctrl_reg;
1500
1501
1502 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1503 if (ret_val)
1504 return ret_val;
1505
1506
1507 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1508 if (ret_val)
1509 return ret_val;
1510 else if (hw->phy_type == e1000_phy_8201)
1511 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1525 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1526
1527 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);
1528
1529
1530 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1531 e_dbg("Advertise 10mb Half duplex\n");
1532 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1533 }
1534
1535
1536 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1537 e_dbg("Advertise 10mb Full duplex\n");
1538 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1539 }
1540
1541
1542 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1543 e_dbg("Advertise 100mb Half duplex\n");
1544 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1545 }
1546
1547
1548 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1549 e_dbg("Advertise 100mb Full duplex\n");
1550 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1551 }
1552
1553
1554 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1555 e_dbg
1556 ("Advertise 1000mb Half duplex requested, request denied!\n");
1557 }
1558
1559
1560 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1561 e_dbg("Advertise 1000mb Full duplex\n");
1562 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1563 }
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582 switch (hw->fc) {
1583 case E1000_FC_NONE:
1584
1585
1586
1587 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1588 break;
1589 case E1000_FC_RX_PAUSE:
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1600 break;
1601 case E1000_FC_TX_PAUSE:
1602
1603
1604
1605 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1606 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1607 break;
1608 case E1000_FC_FULL:
1609
1610
1611
1612 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1613 break;
1614 default:
1615 e_dbg("Flow control param set incorrectly\n");
1616 return -E1000_ERR_CONFIG;
1617 }
1618
1619 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1620 if (ret_val)
1621 return ret_val;
1622
1623 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1624
1625 if (hw->phy_type == e1000_phy_8201) {
1626 mii_1000t_ctrl_reg = 0;
1627 } else {
1628 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1629 mii_1000t_ctrl_reg);
1630 if (ret_val)
1631 return ret_val;
1632 }
1633
1634 return E1000_SUCCESS;
1635 }
1636
1637
1638
1639
1640
1641
1642
1643 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1644 {
1645 u32 ctrl;
1646 s32 ret_val;
1647 u16 mii_ctrl_reg;
1648 u16 mii_status_reg;
1649 u16 phy_data;
1650 u16 i;
1651
1652
1653 hw->fc = E1000_FC_NONE;
1654
1655 e_dbg("hw->fc = %d\n", hw->fc);
1656
1657
1658 ctrl = er32(CTRL);
1659
1660
1661 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1662 ctrl &= ~(DEVICE_SPEED_MASK);
1663
1664
1665 ctrl &= ~E1000_CTRL_ASDE;
1666
1667
1668 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1669 if (ret_val)
1670 return ret_val;
1671
1672
1673
1674 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1675
1676
1677 if (hw->forced_speed_duplex == e1000_100_full ||
1678 hw->forced_speed_duplex == e1000_10_full) {
1679
1680
1681
1682 ctrl |= E1000_CTRL_FD;
1683 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1684 e_dbg("Full Duplex\n");
1685 } else {
1686
1687
1688
1689 ctrl &= ~E1000_CTRL_FD;
1690 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1691 e_dbg("Half Duplex\n");
1692 }
1693
1694
1695 if (hw->forced_speed_duplex == e1000_100_full ||
1696 hw->forced_speed_duplex == e1000_100_half) {
1697
1698 ctrl |= E1000_CTRL_SPD_100;
1699 mii_ctrl_reg |= MII_CR_SPEED_100;
1700 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1701 e_dbg("Forcing 100mb ");
1702 } else {
1703
1704 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1705 mii_ctrl_reg |= MII_CR_SPEED_10;
1706 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1707 e_dbg("Forcing 10mb ");
1708 }
1709
1710 e1000_config_collision_dist(hw);
1711
1712
1713 ew32(CTRL, ctrl);
1714
1715 if (hw->phy_type == e1000_phy_m88) {
1716 ret_val =
1717 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1718 if (ret_val)
1719 return ret_val;
1720
1721
1722
1723
1724 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1725 ret_val =
1726 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1727 if (ret_val)
1728 return ret_val;
1729
1730 e_dbg("M88E1000 PSCR: %x\n", phy_data);
1731
1732
1733 mii_ctrl_reg |= MII_CR_RESET;
1734
1735
1736 } else {
1737
1738
1739
1740 ret_val =
1741 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1742 if (ret_val)
1743 return ret_val;
1744
1745 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1746 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1747
1748 ret_val =
1749 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1750 if (ret_val)
1751 return ret_val;
1752 }
1753
1754
1755 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1756 if (ret_val)
1757 return ret_val;
1758
1759 udelay(1);
1760
1761
1762
1763
1764
1765
1766
1767
1768 if (hw->wait_autoneg_complete) {
1769
1770 e_dbg("Waiting for forced speed/duplex link.\n");
1771 mii_status_reg = 0;
1772
1773
1774 for (i = PHY_FORCE_TIME; i > 0; i--) {
1775
1776
1777
1778 ret_val =
1779 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1780 if (ret_val)
1781 return ret_val;
1782
1783 ret_val =
1784 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1785 if (ret_val)
1786 return ret_val;
1787
1788 if (mii_status_reg & MII_SR_LINK_STATUS)
1789 break;
1790 msleep(100);
1791 }
1792 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1793
1794
1795
1796 ret_val = e1000_phy_reset_dsp(hw);
1797 if (ret_val) {
1798 e_dbg("Error Resetting PHY DSP\n");
1799 return ret_val;
1800 }
1801 }
1802
1803
1804
1805 for (i = PHY_FORCE_TIME; i > 0; i--) {
1806 if (mii_status_reg & MII_SR_LINK_STATUS)
1807 break;
1808 msleep(100);
1809
1810
1811
1812 ret_val =
1813 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1814 if (ret_val)
1815 return ret_val;
1816
1817 ret_val =
1818 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1819 if (ret_val)
1820 return ret_val;
1821 }
1822 }
1823
1824 if (hw->phy_type == e1000_phy_m88) {
1825
1826
1827
1828
1829
1830 ret_val =
1831 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1832 &phy_data);
1833 if (ret_val)
1834 return ret_val;
1835
1836 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1837 ret_val =
1838 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1839 phy_data);
1840 if (ret_val)
1841 return ret_val;
1842
1843
1844
1845
1846
1847 ret_val =
1848 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1849 if (ret_val)
1850 return ret_val;
1851
1852 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1853 ret_val =
1854 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1855 if (ret_val)
1856 return ret_val;
1857
1858 if ((hw->mac_type == e1000_82544 ||
1859 hw->mac_type == e1000_82543) &&
1860 (!hw->autoneg) &&
1861 (hw->forced_speed_duplex == e1000_10_full ||
1862 hw->forced_speed_duplex == e1000_10_half)) {
1863 ret_val = e1000_polarity_reversal_workaround(hw);
1864 if (ret_val)
1865 return ret_val;
1866 }
1867 }
1868 return E1000_SUCCESS;
1869 }
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879 void e1000_config_collision_dist(struct e1000_hw *hw)
1880 {
1881 u32 tctl, coll_dist;
1882
1883 if (hw->mac_type < e1000_82543)
1884 coll_dist = E1000_COLLISION_DISTANCE_82542;
1885 else
1886 coll_dist = E1000_COLLISION_DISTANCE;
1887
1888 tctl = er32(TCTL);
1889
1890 tctl &= ~E1000_TCTL_COLD;
1891 tctl |= coll_dist << E1000_COLD_SHIFT;
1892
1893 ew32(TCTL, tctl);
1894 E1000_WRITE_FLUSH();
1895 }
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1907 {
1908 u32 ctrl;
1909 s32 ret_val;
1910 u16 phy_data;
1911
1912
1913
1914
1915 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
1916 return E1000_SUCCESS;
1917
1918
1919
1920
1921 ctrl = er32(CTRL);
1922 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1923 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1924
1925 switch (hw->phy_type) {
1926 case e1000_phy_8201:
1927 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1928 if (ret_val)
1929 return ret_val;
1930
1931 if (phy_data & RTL_PHY_CTRL_FD)
1932 ctrl |= E1000_CTRL_FD;
1933 else
1934 ctrl &= ~E1000_CTRL_FD;
1935
1936 if (phy_data & RTL_PHY_CTRL_SPD_100)
1937 ctrl |= E1000_CTRL_SPD_100;
1938 else
1939 ctrl |= E1000_CTRL_SPD_10;
1940
1941 e1000_config_collision_dist(hw);
1942 break;
1943 default:
1944
1945
1946
1947 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1948 &phy_data);
1949 if (ret_val)
1950 return ret_val;
1951
1952 if (phy_data & M88E1000_PSSR_DPLX)
1953 ctrl |= E1000_CTRL_FD;
1954 else
1955 ctrl &= ~E1000_CTRL_FD;
1956
1957 e1000_config_collision_dist(hw);
1958
1959
1960
1961
1962 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1963 ctrl |= E1000_CTRL_SPD_1000;
1964 else if ((phy_data & M88E1000_PSSR_SPEED) ==
1965 M88E1000_PSSR_100MBS)
1966 ctrl |= E1000_CTRL_SPD_100;
1967 }
1968
1969
1970 ew32(CTRL, ctrl);
1971 return E1000_SUCCESS;
1972 }
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985 s32 e1000_force_mac_fc(struct e1000_hw *hw)
1986 {
1987 u32 ctrl;
1988
1989
1990 ctrl = er32(CTRL);
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010 switch (hw->fc) {
2011 case E1000_FC_NONE:
2012 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2013 break;
2014 case E1000_FC_RX_PAUSE:
2015 ctrl &= (~E1000_CTRL_TFCE);
2016 ctrl |= E1000_CTRL_RFCE;
2017 break;
2018 case E1000_FC_TX_PAUSE:
2019 ctrl &= (~E1000_CTRL_RFCE);
2020 ctrl |= E1000_CTRL_TFCE;
2021 break;
2022 case E1000_FC_FULL:
2023 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2024 break;
2025 default:
2026 e_dbg("Flow control param set incorrectly\n");
2027 return -E1000_ERR_CONFIG;
2028 }
2029
2030
2031 if (hw->mac_type == e1000_82542_rev2_0)
2032 ctrl &= (~E1000_CTRL_TFCE);
2033
2034 ew32(CTRL, ctrl);
2035 return E1000_SUCCESS;
2036 }
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2050 {
2051 s32 ret_val;
2052 u16 mii_status_reg;
2053 u16 mii_nway_adv_reg;
2054 u16 mii_nway_lp_ability_reg;
2055 u16 speed;
2056 u16 duplex;
2057
2058
2059
2060
2061
2062 if (((hw->media_type == e1000_media_type_fiber) &&
2063 (hw->autoneg_failed)) ||
2064 ((hw->media_type == e1000_media_type_internal_serdes) &&
2065 (hw->autoneg_failed)) ||
2066 ((hw->media_type == e1000_media_type_copper) &&
2067 (!hw->autoneg))) {
2068 ret_val = e1000_force_mac_fc(hw);
2069 if (ret_val) {
2070 e_dbg("Error forcing flow control settings\n");
2071 return ret_val;
2072 }
2073 }
2074
2075
2076
2077
2078
2079
2080 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2081
2082
2083
2084
2085 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2086 if (ret_val)
2087 return ret_val;
2088 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2089 if (ret_val)
2090 return ret_val;
2091
2092 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2093
2094
2095
2096
2097
2098
2099 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2100 &mii_nway_adv_reg);
2101 if (ret_val)
2102 return ret_val;
2103 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2104 &mii_nway_lp_ability_reg);
2105 if (ret_val)
2106 return ret_val;
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2144 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2145
2146
2147
2148
2149
2150
2151
2152 if (hw->original_fc == E1000_FC_FULL) {
2153 hw->fc = E1000_FC_FULL;
2154 e_dbg("Flow Control = FULL.\n");
2155 } else {
2156 hw->fc = E1000_FC_RX_PAUSE;
2157 e_dbg
2158 ("Flow Control = RX PAUSE frames only.\n");
2159 }
2160 }
2161
2162
2163
2164
2165
2166
2167
2168
2169 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2170 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2171 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2172 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2173 hw->fc = E1000_FC_TX_PAUSE;
2174 e_dbg
2175 ("Flow Control = TX PAUSE frames only.\n");
2176 }
2177
2178
2179
2180
2181
2182
2183
2184
2185 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2186 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2187 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2188 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2189 hw->fc = E1000_FC_RX_PAUSE;
2190 e_dbg
2191 ("Flow Control = RX PAUSE frames only.\n");
2192 }
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215 else if ((hw->original_fc == E1000_FC_NONE ||
2216 hw->original_fc == E1000_FC_TX_PAUSE) ||
2217 hw->fc_strict_ieee) {
2218 hw->fc = E1000_FC_NONE;
2219 e_dbg("Flow Control = NONE.\n");
2220 } else {
2221 hw->fc = E1000_FC_RX_PAUSE;
2222 e_dbg
2223 ("Flow Control = RX PAUSE frames only.\n");
2224 }
2225
2226
2227
2228
2229
2230 ret_val =
2231 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2232 if (ret_val) {
2233 e_dbg
2234 ("Error getting link speed and duplex\n");
2235 return ret_val;
2236 }
2237
2238 if (duplex == HALF_DUPLEX)
2239 hw->fc = E1000_FC_NONE;
2240
2241
2242
2243
2244 ret_val = e1000_force_mac_fc(hw);
2245 if (ret_val) {
2246 e_dbg
2247 ("Error forcing flow control settings\n");
2248 return ret_val;
2249 }
2250 } else {
2251 e_dbg
2252 ("Copper PHY and Auto Neg has not completed.\n");
2253 }
2254 }
2255 return E1000_SUCCESS;
2256 }
2257
2258
2259
2260
2261
2262
2263
2264
2265 static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2266 {
2267 u32 rxcw;
2268 u32 ctrl;
2269 u32 status;
2270 s32 ret_val = E1000_SUCCESS;
2271
2272 ctrl = er32(CTRL);
2273 status = er32(STATUS);
2274 rxcw = er32(RXCW);
2275
2276
2277
2278
2279
2280
2281
2282
2283 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2284 if (hw->autoneg_failed == 0) {
2285 hw->autoneg_failed = 1;
2286 goto out;
2287 }
2288 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
2289
2290
2291 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2292
2293
2294 ctrl = er32(CTRL);
2295 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2296 ew32(CTRL, ctrl);
2297
2298
2299 ret_val = e1000_config_fc_after_link_up(hw);
2300 if (ret_val) {
2301 e_dbg("Error configuring flow control\n");
2302 goto out;
2303 }
2304 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2305
2306
2307
2308
2309
2310 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
2311 ew32(TXCW, hw->txcw);
2312 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2313
2314 hw->serdes_has_link = true;
2315 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2316
2317
2318
2319
2320
2321 udelay(10);
2322 rxcw = er32(RXCW);
2323 if (rxcw & E1000_RXCW_SYNCH) {
2324 if (!(rxcw & E1000_RXCW_IV)) {
2325 hw->serdes_has_link = true;
2326 e_dbg("SERDES: Link up - forced.\n");
2327 }
2328 } else {
2329 hw->serdes_has_link = false;
2330 e_dbg("SERDES: Link down - force failed.\n");
2331 }
2332 }
2333
2334 if (E1000_TXCW_ANE & er32(TXCW)) {
2335 status = er32(STATUS);
2336 if (status & E1000_STATUS_LU) {
2337
2338 udelay(10);
2339 rxcw = er32(RXCW);
2340 if (rxcw & E1000_RXCW_SYNCH) {
2341 if (!(rxcw & E1000_RXCW_IV)) {
2342 hw->serdes_has_link = true;
2343 e_dbg("SERDES: Link up - autoneg "
2344 "completed successfully.\n");
2345 } else {
2346 hw->serdes_has_link = false;
2347 e_dbg("SERDES: Link down - invalid"
2348 "codewords detected in autoneg.\n");
2349 }
2350 } else {
2351 hw->serdes_has_link = false;
2352 e_dbg("SERDES: Link down - no sync.\n");
2353 }
2354 } else {
2355 hw->serdes_has_link = false;
2356 e_dbg("SERDES: Link down - autoneg failed\n");
2357 }
2358 }
2359
2360 out:
2361 return ret_val;
2362 }
2363
2364
2365
2366
2367
2368
2369
2370
2371 s32 e1000_check_for_link(struct e1000_hw *hw)
2372 {
2373 u32 rxcw = 0;
2374 u32 ctrl;
2375 u32 status;
2376 u32 rctl;
2377 u32 icr;
2378 u32 signal = 0;
2379 s32 ret_val;
2380 u16 phy_data;
2381
2382 ctrl = er32(CTRL);
2383 status = er32(STATUS);
2384
2385
2386
2387
2388
2389 if ((hw->media_type == e1000_media_type_fiber) ||
2390 (hw->media_type == e1000_media_type_internal_serdes)) {
2391 rxcw = er32(RXCW);
2392
2393 if (hw->media_type == e1000_media_type_fiber) {
2394 signal =
2395 (hw->mac_type >
2396 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2397 if (status & E1000_STATUS_LU)
2398 hw->get_link_status = false;
2399 }
2400 }
2401
2402
2403
2404
2405
2406
2407
2408 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2409
2410
2411
2412
2413
2414 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2415 if (ret_val)
2416 return ret_val;
2417 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2418 if (ret_val)
2419 return ret_val;
2420
2421 if (phy_data & MII_SR_LINK_STATUS) {
2422 hw->get_link_status = false;
2423
2424
2425
2426 e1000_check_downshift(hw);
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437 if ((hw->mac_type == e1000_82544 ||
2438 hw->mac_type == e1000_82543) &&
2439 (!hw->autoneg) &&
2440 (hw->forced_speed_duplex == e1000_10_full ||
2441 hw->forced_speed_duplex == e1000_10_half)) {
2442 ew32(IMC, 0xffffffff);
2443 ret_val =
2444 e1000_polarity_reversal_workaround(hw);
2445 icr = er32(ICR);
2446 ew32(ICS, (icr & ~E1000_ICS_LSC));
2447 ew32(IMS, IMS_ENABLE_MASK);
2448 }
2449
2450 } else {
2451
2452 e1000_config_dsp_after_link_change(hw, false);
2453 return 0;
2454 }
2455
2456
2457
2458
2459 if (!hw->autoneg)
2460 return -E1000_ERR_CONFIG;
2461
2462
2463 e1000_config_dsp_after_link_change(hw, true);
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473 if ((hw->mac_type >= e1000_82544) &&
2474 (hw->mac_type != e1000_ce4100))
2475 e1000_config_collision_dist(hw);
2476 else {
2477 ret_val = e1000_config_mac_to_phy(hw);
2478 if (ret_val) {
2479 e_dbg
2480 ("Error configuring MAC to PHY settings\n");
2481 return ret_val;
2482 }
2483 }
2484
2485
2486
2487
2488
2489
2490 ret_val = e1000_config_fc_after_link_up(hw);
2491 if (ret_val) {
2492 e_dbg("Error configuring flow control\n");
2493 return ret_val;
2494 }
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504 if (hw->tbi_compatibility_en) {
2505 u16 speed, duplex;
2506
2507 ret_val =
2508 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2509
2510 if (ret_val) {
2511 e_dbg
2512 ("Error getting link speed and duplex\n");
2513 return ret_val;
2514 }
2515 if (speed != SPEED_1000) {
2516
2517
2518
2519 if (hw->tbi_compatibility_on) {
2520
2521
2522
2523 rctl = er32(RCTL);
2524 rctl &= ~E1000_RCTL_SBP;
2525 ew32(RCTL, rctl);
2526 hw->tbi_compatibility_on = false;
2527 }
2528 } else {
2529
2530
2531
2532
2533
2534
2535 if (!hw->tbi_compatibility_on) {
2536 hw->tbi_compatibility_on = true;
2537 rctl = er32(RCTL);
2538 rctl |= E1000_RCTL_SBP;
2539 ew32(RCTL, rctl);
2540 }
2541 }
2542 }
2543 }
2544
2545 if ((hw->media_type == e1000_media_type_fiber) ||
2546 (hw->media_type == e1000_media_type_internal_serdes))
2547 e1000_check_for_serdes_link_generic(hw);
2548
2549 return E1000_SUCCESS;
2550 }
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2561 {
2562 u32 status;
2563 s32 ret_val;
2564 u16 phy_data;
2565
2566 if (hw->mac_type >= e1000_82543) {
2567 status = er32(STATUS);
2568 if (status & E1000_STATUS_SPEED_1000) {
2569 *speed = SPEED_1000;
2570 e_dbg("1000 Mbs, ");
2571 } else if (status & E1000_STATUS_SPEED_100) {
2572 *speed = SPEED_100;
2573 e_dbg("100 Mbs, ");
2574 } else {
2575 *speed = SPEED_10;
2576 e_dbg("10 Mbs, ");
2577 }
2578
2579 if (status & E1000_STATUS_FD) {
2580 *duplex = FULL_DUPLEX;
2581 e_dbg("Full Duplex\n");
2582 } else {
2583 *duplex = HALF_DUPLEX;
2584 e_dbg(" Half Duplex\n");
2585 }
2586 } else {
2587 e_dbg("1000 Mbs, Full Duplex\n");
2588 *speed = SPEED_1000;
2589 *duplex = FULL_DUPLEX;
2590 }
2591
2592
2593
2594
2595
2596 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2597 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2598 if (ret_val)
2599 return ret_val;
2600
2601 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2602 *duplex = HALF_DUPLEX;
2603 else {
2604 ret_val =
2605 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2606 if (ret_val)
2607 return ret_val;
2608 if ((*speed == SPEED_100 &&
2609 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2610 (*speed == SPEED_10 &&
2611 !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2612 *duplex = HALF_DUPLEX;
2613 }
2614 }
2615
2616 return E1000_SUCCESS;
2617 }
2618
2619
2620
2621
2622
2623
2624
2625 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2626 {
2627 s32 ret_val;
2628 u16 i;
2629 u16 phy_data;
2630
2631 e_dbg("Waiting for Auto-Neg to complete.\n");
2632
2633
2634 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2635
2636
2637
2638 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2639 if (ret_val)
2640 return ret_val;
2641 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2642 if (ret_val)
2643 return ret_val;
2644 if (phy_data & MII_SR_AUTONEG_COMPLETE)
2645 return E1000_SUCCESS;
2646
2647 msleep(100);
2648 }
2649 return E1000_SUCCESS;
2650 }
2651
2652
2653
2654
2655
2656
2657 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2658 {
2659
2660
2661
2662 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2663 E1000_WRITE_FLUSH();
2664 udelay(10);
2665 }
2666
2667
2668
2669
2670
2671
2672 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2673 {
2674
2675
2676
2677 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2678 E1000_WRITE_FLUSH();
2679 udelay(10);
2680 }
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
2691 {
2692 u32 ctrl;
2693 u32 mask;
2694
2695
2696
2697
2698
2699 mask = 0x01;
2700 mask <<= (count - 1);
2701
2702 ctrl = er32(CTRL);
2703
2704
2705 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2706
2707 while (mask) {
2708
2709
2710
2711
2712
2713 if (data & mask)
2714 ctrl |= E1000_CTRL_MDIO;
2715 else
2716 ctrl &= ~E1000_CTRL_MDIO;
2717
2718 ew32(CTRL, ctrl);
2719 E1000_WRITE_FLUSH();
2720
2721 udelay(10);
2722
2723 e1000_raise_mdi_clk(hw, &ctrl);
2724 e1000_lower_mdi_clk(hw, &ctrl);
2725
2726 mask = mask >> 1;
2727 }
2728 }
2729
2730
2731
2732
2733
2734
2735
2736 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2737 {
2738 u32 ctrl;
2739 u16 data = 0;
2740 u8 i;
2741
2742
2743
2744
2745
2746
2747
2748
2749 ctrl = er32(CTRL);
2750
2751
2752
2753
2754 ctrl &= ~E1000_CTRL_MDIO_DIR;
2755 ctrl &= ~E1000_CTRL_MDIO;
2756
2757 ew32(CTRL, ctrl);
2758 E1000_WRITE_FLUSH();
2759
2760
2761
2762
2763
2764 e1000_raise_mdi_clk(hw, &ctrl);
2765 e1000_lower_mdi_clk(hw, &ctrl);
2766
2767 for (data = 0, i = 0; i < 16; i++) {
2768 data = data << 1;
2769 e1000_raise_mdi_clk(hw, &ctrl);
2770 ctrl = er32(CTRL);
2771
2772 if (ctrl & E1000_CTRL_MDIO)
2773 data |= 1;
2774 e1000_lower_mdi_clk(hw, &ctrl);
2775 }
2776
2777 e1000_raise_mdi_clk(hw, &ctrl);
2778 e1000_lower_mdi_clk(hw, &ctrl);
2779
2780 return data;
2781 }
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2793 {
2794 u32 ret_val;
2795 unsigned long flags;
2796
2797 spin_lock_irqsave(&e1000_phy_lock, flags);
2798
2799 if ((hw->phy_type == e1000_phy_igp) &&
2800 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2801 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2802 (u16) reg_addr);
2803 if (ret_val)
2804 goto out;
2805 }
2806
2807 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2808 phy_data);
2809 out:
2810 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2811
2812 return ret_val;
2813 }
2814
2815 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2816 u16 *phy_data)
2817 {
2818 u32 i;
2819 u32 mdic = 0;
2820 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2821
2822 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2823 e_dbg("PHY Address %d is out of range\n", reg_addr);
2824 return -E1000_ERR_PARAM;
2825 }
2826
2827 if (hw->mac_type > e1000_82543) {
2828
2829
2830
2831
2832 if (hw->mac_type == e1000_ce4100) {
2833 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2834 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2835 (INTEL_CE_GBE_MDIC_OP_READ) |
2836 (INTEL_CE_GBE_MDIC_GO));
2837
2838 writel(mdic, E1000_MDIO_CMD);
2839
2840
2841
2842
2843 for (i = 0; i < 64; i++) {
2844 udelay(50);
2845 mdic = readl(E1000_MDIO_CMD);
2846 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2847 break;
2848 }
2849
2850 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2851 e_dbg("MDI Read did not complete\n");
2852 return -E1000_ERR_PHY;
2853 }
2854
2855 mdic = readl(E1000_MDIO_STS);
2856 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
2857 e_dbg("MDI Read Error\n");
2858 return -E1000_ERR_PHY;
2859 }
2860 *phy_data = (u16)mdic;
2861 } else {
2862 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2863 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2864 (E1000_MDIC_OP_READ));
2865
2866 ew32(MDIC, mdic);
2867
2868
2869
2870
2871 for (i = 0; i < 64; i++) {
2872 udelay(50);
2873 mdic = er32(MDIC);
2874 if (mdic & E1000_MDIC_READY)
2875 break;
2876 }
2877 if (!(mdic & E1000_MDIC_READY)) {
2878 e_dbg("MDI Read did not complete\n");
2879 return -E1000_ERR_PHY;
2880 }
2881 if (mdic & E1000_MDIC_ERROR) {
2882 e_dbg("MDI Error\n");
2883 return -E1000_ERR_PHY;
2884 }
2885 *phy_data = (u16)mdic;
2886 }
2887 } else {
2888
2889
2890
2891
2892 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906 mdic = ((reg_addr) | (phy_addr << 5) |
2907 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2908
2909 e1000_shift_out_mdi_bits(hw, mdic, 14);
2910
2911
2912
2913
2914
2915 *phy_data = e1000_shift_in_mdi_bits(hw);
2916 }
2917 return E1000_SUCCESS;
2918 }
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2930 {
2931 u32 ret_val;
2932 unsigned long flags;
2933
2934 spin_lock_irqsave(&e1000_phy_lock, flags);
2935
2936 if ((hw->phy_type == e1000_phy_igp) &&
2937 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2938 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2939 (u16)reg_addr);
2940 if (ret_val) {
2941 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2942 return ret_val;
2943 }
2944 }
2945
2946 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2947 phy_data);
2948 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2949
2950 return ret_val;
2951 }
2952
2953 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2954 u16 phy_data)
2955 {
2956 u32 i;
2957 u32 mdic = 0;
2958 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2959
2960 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2961 e_dbg("PHY Address %d is out of range\n", reg_addr);
2962 return -E1000_ERR_PARAM;
2963 }
2964
2965 if (hw->mac_type > e1000_82543) {
2966
2967
2968
2969
2970
2971 if (hw->mac_type == e1000_ce4100) {
2972 mdic = (((u32)phy_data) |
2973 (reg_addr << E1000_MDIC_REG_SHIFT) |
2974 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2975 (INTEL_CE_GBE_MDIC_OP_WRITE) |
2976 (INTEL_CE_GBE_MDIC_GO));
2977
2978 writel(mdic, E1000_MDIO_CMD);
2979
2980
2981
2982
2983 for (i = 0; i < 640; i++) {
2984 udelay(5);
2985 mdic = readl(E1000_MDIO_CMD);
2986 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2987 break;
2988 }
2989 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2990 e_dbg("MDI Write did not complete\n");
2991 return -E1000_ERR_PHY;
2992 }
2993 } else {
2994 mdic = (((u32)phy_data) |
2995 (reg_addr << E1000_MDIC_REG_SHIFT) |
2996 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2997 (E1000_MDIC_OP_WRITE));
2998
2999 ew32(MDIC, mdic);
3000
3001
3002
3003
3004 for (i = 0; i < 641; i++) {
3005 udelay(5);
3006 mdic = er32(MDIC);
3007 if (mdic & E1000_MDIC_READY)
3008 break;
3009 }
3010 if (!(mdic & E1000_MDIC_READY)) {
3011 e_dbg("MDI Write did not complete\n");
3012 return -E1000_ERR_PHY;
3013 }
3014 }
3015 } else {
3016
3017
3018
3019
3020
3021 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3022
3023
3024
3025
3026
3027
3028
3029 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3030 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3031 mdic <<= 16;
3032 mdic |= (u32)phy_data;
3033
3034 e1000_shift_out_mdi_bits(hw, mdic, 32);
3035 }
3036
3037 return E1000_SUCCESS;
3038 }
3039
3040
3041
3042
3043
3044
3045
3046 s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3047 {
3048 u32 ctrl, ctrl_ext;
3049 u32 led_ctrl;
3050
3051 e_dbg("Resetting Phy...\n");
3052
3053 if (hw->mac_type > e1000_82543) {
3054
3055
3056
3057
3058
3059 ctrl = er32(CTRL);
3060 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3061 E1000_WRITE_FLUSH();
3062
3063 msleep(10);
3064
3065 ew32(CTRL, ctrl);
3066 E1000_WRITE_FLUSH();
3067
3068 } else {
3069
3070
3071
3072
3073 ctrl_ext = er32(CTRL_EXT);
3074 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3075 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3076 ew32(CTRL_EXT, ctrl_ext);
3077 E1000_WRITE_FLUSH();
3078 msleep(10);
3079 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3080 ew32(CTRL_EXT, ctrl_ext);
3081 E1000_WRITE_FLUSH();
3082 }
3083 udelay(150);
3084
3085 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3086
3087 led_ctrl = er32(LEDCTL);
3088 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3089 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3090 ew32(LEDCTL, led_ctrl);
3091 }
3092
3093
3094 return e1000_get_phy_cfg_done(hw);
3095 }
3096
3097
3098
3099
3100
3101
3102
3103
3104 s32 e1000_phy_reset(struct e1000_hw *hw)
3105 {
3106 s32 ret_val;
3107 u16 phy_data;
3108
3109 switch (hw->phy_type) {
3110 case e1000_phy_igp:
3111 ret_val = e1000_phy_hw_reset(hw);
3112 if (ret_val)
3113 return ret_val;
3114 break;
3115 default:
3116 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3117 if (ret_val)
3118 return ret_val;
3119
3120 phy_data |= MII_CR_RESET;
3121 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3122 if (ret_val)
3123 return ret_val;
3124
3125 udelay(1);
3126 break;
3127 }
3128
3129 if (hw->phy_type == e1000_phy_igp)
3130 e1000_phy_init_script(hw);
3131
3132 return E1000_SUCCESS;
3133 }
3134
3135
3136
3137
3138
3139
3140
3141 static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3142 {
3143 s32 phy_init_status, ret_val;
3144 u16 phy_id_high, phy_id_low;
3145 bool match = false;
3146
3147 if (hw->phy_id != 0)
3148 return E1000_SUCCESS;
3149
3150
3151 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3152 if (ret_val)
3153 return ret_val;
3154
3155 hw->phy_id = (u32)(phy_id_high << 16);
3156 udelay(20);
3157 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3158 if (ret_val)
3159 return ret_val;
3160
3161 hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
3162 hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
3163
3164 switch (hw->mac_type) {
3165 case e1000_82543:
3166 if (hw->phy_id == M88E1000_E_PHY_ID)
3167 match = true;
3168 break;
3169 case e1000_82544:
3170 if (hw->phy_id == M88E1000_I_PHY_ID)
3171 match = true;
3172 break;
3173 case e1000_82540:
3174 case e1000_82545:
3175 case e1000_82545_rev_3:
3176 case e1000_82546:
3177 case e1000_82546_rev_3:
3178 if (hw->phy_id == M88E1011_I_PHY_ID)
3179 match = true;
3180 break;
3181 case e1000_ce4100:
3182 if ((hw->phy_id == RTL8211B_PHY_ID) ||
3183 (hw->phy_id == RTL8201N_PHY_ID) ||
3184 (hw->phy_id == M88E1118_E_PHY_ID))
3185 match = true;
3186 break;
3187 case e1000_82541:
3188 case e1000_82541_rev_2:
3189 case e1000_82547:
3190 case e1000_82547_rev_2:
3191 if (hw->phy_id == IGP01E1000_I_PHY_ID)
3192 match = true;
3193 break;
3194 default:
3195 e_dbg("Invalid MAC type %d\n", hw->mac_type);
3196 return -E1000_ERR_CONFIG;
3197 }
3198 phy_init_status = e1000_set_phy_type(hw);
3199
3200 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3201 e_dbg("PHY ID 0x%X detected\n", hw->phy_id);
3202 return E1000_SUCCESS;
3203 }
3204 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);
3205 return -E1000_ERR_PHY;
3206 }
3207
3208
3209
3210
3211
3212
3213
3214 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3215 {
3216 s32 ret_val;
3217
3218 do {
3219 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3220 if (ret_val)
3221 break;
3222 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3223 if (ret_val)
3224 break;
3225 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3226 if (ret_val)
3227 break;
3228 ret_val = E1000_SUCCESS;
3229 } while (0);
3230
3231 return ret_val;
3232 }
3233
3234
3235
3236
3237
3238
3239
3240
3241 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3242 struct e1000_phy_info *phy_info)
3243 {
3244 s32 ret_val;
3245 u16 phy_data, min_length, max_length, average;
3246 e1000_rev_polarity polarity;
3247
3248
3249
3250
3251 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3252
3253
3254 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3255
3256
3257 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3258
3259
3260 ret_val = e1000_check_polarity(hw, &polarity);
3261 if (ret_val)
3262 return ret_val;
3263
3264 phy_info->cable_polarity = polarity;
3265
3266 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3267 if (ret_val)
3268 return ret_val;
3269
3270 phy_info->mdix_mode =
3271 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3272 IGP01E1000_PSSR_MDIX_SHIFT);
3273
3274 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3275 IGP01E1000_PSSR_SPEED_1000MBPS) {
3276
3277
3278
3279 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3280 if (ret_val)
3281 return ret_val;
3282
3283 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3284 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3285 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3286 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3287 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3288 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3289
3290
3291 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3292 if (ret_val)
3293 return ret_val;
3294
3295
3296 average = (max_length + min_length) / 2;
3297
3298 if (average <= e1000_igp_cable_length_50)
3299 phy_info->cable_length = e1000_cable_length_50;
3300 else if (average <= e1000_igp_cable_length_80)
3301 phy_info->cable_length = e1000_cable_length_50_80;
3302 else if (average <= e1000_igp_cable_length_110)
3303 phy_info->cable_length = e1000_cable_length_80_110;
3304 else if (average <= e1000_igp_cable_length_140)
3305 phy_info->cable_length = e1000_cable_length_110_140;
3306 else
3307 phy_info->cable_length = e1000_cable_length_140;
3308 }
3309
3310 return E1000_SUCCESS;
3311 }
3312
3313
3314
3315
3316
3317
3318
3319
3320 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3321 struct e1000_phy_info *phy_info)
3322 {
3323 s32 ret_val;
3324 u16 phy_data;
3325 e1000_rev_polarity polarity;
3326
3327
3328
3329
3330 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3331
3332 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3333 if (ret_val)
3334 return ret_val;
3335
3336 phy_info->extended_10bt_distance =
3337 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3338 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3339 e1000_10bt_ext_dist_enable_lower :
3340 e1000_10bt_ext_dist_enable_normal;
3341
3342 phy_info->polarity_correction =
3343 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3344 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3345 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3346
3347
3348 ret_val = e1000_check_polarity(hw, &polarity);
3349 if (ret_val)
3350 return ret_val;
3351 phy_info->cable_polarity = polarity;
3352
3353 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3354 if (ret_val)
3355 return ret_val;
3356
3357 phy_info->mdix_mode =
3358 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3359 M88E1000_PSSR_MDIX_SHIFT);
3360
3361 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3362
3363
3364
3365 phy_info->cable_length =
3366 (e1000_cable_length) ((phy_data &
3367 M88E1000_PSSR_CABLE_LENGTH) >>
3368 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3369
3370 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3371 if (ret_val)
3372 return ret_val;
3373
3374 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3375 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3376 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3377 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3378 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3379 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3380 }
3381
3382 return E1000_SUCCESS;
3383 }
3384
3385
3386
3387
3388
3389
3390
3391
3392 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3393 {
3394 s32 ret_val;
3395 u16 phy_data;
3396
3397 phy_info->cable_length = e1000_cable_length_undefined;
3398 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3399 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3400 phy_info->downshift = e1000_downshift_undefined;
3401 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3402 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3403 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3404 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3405
3406 if (hw->media_type != e1000_media_type_copper) {
3407 e_dbg("PHY info is only valid for copper media\n");
3408 return -E1000_ERR_CONFIG;
3409 }
3410
3411 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3412 if (ret_val)
3413 return ret_val;
3414
3415 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3416 if (ret_val)
3417 return ret_val;
3418
3419 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3420 e_dbg("PHY info is only valid if link is up\n");
3421 return -E1000_ERR_CONFIG;
3422 }
3423
3424 if (hw->phy_type == e1000_phy_igp)
3425 return e1000_phy_igp_get_info(hw, phy_info);
3426 else if ((hw->phy_type == e1000_phy_8211) ||
3427 (hw->phy_type == e1000_phy_8201))
3428 return E1000_SUCCESS;
3429 else
3430 return e1000_phy_m88_get_info(hw, phy_info);
3431 }
3432
3433 s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3434 {
3435 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3436 e_dbg("Invalid MDI setting detected\n");
3437 hw->mdix = 1;
3438 return -E1000_ERR_CONFIG;
3439 }
3440 return E1000_SUCCESS;
3441 }
3442
3443
3444
3445
3446
3447
3448
3449
3450 s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3451 {
3452 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3453 u32 eecd = er32(EECD);
3454 s32 ret_val = E1000_SUCCESS;
3455 u16 eeprom_size;
3456
3457 switch (hw->mac_type) {
3458 case e1000_82542_rev2_0:
3459 case e1000_82542_rev2_1:
3460 case e1000_82543:
3461 case e1000_82544:
3462 eeprom->type = e1000_eeprom_microwire;
3463 eeprom->word_size = 64;
3464 eeprom->opcode_bits = 3;
3465 eeprom->address_bits = 6;
3466 eeprom->delay_usec = 50;
3467 break;
3468 case e1000_82540:
3469 case e1000_82545:
3470 case e1000_82545_rev_3:
3471 case e1000_82546:
3472 case e1000_82546_rev_3:
3473 eeprom->type = e1000_eeprom_microwire;
3474 eeprom->opcode_bits = 3;
3475 eeprom->delay_usec = 50;
3476 if (eecd & E1000_EECD_SIZE) {
3477 eeprom->word_size = 256;
3478 eeprom->address_bits = 8;
3479 } else {
3480 eeprom->word_size = 64;
3481 eeprom->address_bits = 6;
3482 }
3483 break;
3484 case e1000_82541:
3485 case e1000_82541_rev_2:
3486 case e1000_82547:
3487 case e1000_82547_rev_2:
3488 if (eecd & E1000_EECD_TYPE) {
3489 eeprom->type = e1000_eeprom_spi;
3490 eeprom->opcode_bits = 8;
3491 eeprom->delay_usec = 1;
3492 if (eecd & E1000_EECD_ADDR_BITS) {
3493 eeprom->page_size = 32;
3494 eeprom->address_bits = 16;
3495 } else {
3496 eeprom->page_size = 8;
3497 eeprom->address_bits = 8;
3498 }
3499 } else {
3500 eeprom->type = e1000_eeprom_microwire;
3501 eeprom->opcode_bits = 3;
3502 eeprom->delay_usec = 50;
3503 if (eecd & E1000_EECD_ADDR_BITS) {
3504 eeprom->word_size = 256;
3505 eeprom->address_bits = 8;
3506 } else {
3507 eeprom->word_size = 64;
3508 eeprom->address_bits = 6;
3509 }
3510 }
3511 break;
3512 default:
3513 break;
3514 }
3515
3516 if (eeprom->type == e1000_eeprom_spi) {
3517
3518
3519
3520
3521 eeprom->word_size = 64;
3522 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3523 if (ret_val)
3524 return ret_val;
3525 eeprom_size =
3526 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3527
3528
3529
3530
3531 if (eeprom_size)
3532 eeprom_size++;
3533
3534 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3535 }
3536 return ret_val;
3537 }
3538
3539
3540
3541
3542
3543
3544 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
3545 {
3546
3547
3548
3549 *eecd = *eecd | E1000_EECD_SK;
3550 ew32(EECD, *eecd);
3551 E1000_WRITE_FLUSH();
3552 udelay(hw->eeprom.delay_usec);
3553 }
3554
3555
3556
3557
3558
3559
3560 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
3561 {
3562
3563
3564
3565 *eecd = *eecd & ~E1000_EECD_SK;
3566 ew32(EECD, *eecd);
3567 E1000_WRITE_FLUSH();
3568 udelay(hw->eeprom.delay_usec);
3569 }
3570
3571
3572
3573
3574
3575
3576
3577 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
3578 {
3579 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3580 u32 eecd;
3581 u32 mask;
3582
3583
3584
3585
3586
3587 mask = 0x01 << (count - 1);
3588 eecd = er32(EECD);
3589 if (eeprom->type == e1000_eeprom_microwire)
3590 eecd &= ~E1000_EECD_DO;
3591 else if (eeprom->type == e1000_eeprom_spi)
3592 eecd |= E1000_EECD_DO;
3593
3594 do {
3595
3596
3597
3598
3599
3600
3601 eecd &= ~E1000_EECD_DI;
3602
3603 if (data & mask)
3604 eecd |= E1000_EECD_DI;
3605
3606 ew32(EECD, eecd);
3607 E1000_WRITE_FLUSH();
3608
3609 udelay(eeprom->delay_usec);
3610
3611 e1000_raise_ee_clk(hw, &eecd);
3612 e1000_lower_ee_clk(hw, &eecd);
3613
3614 mask = mask >> 1;
3615
3616 } while (mask);
3617
3618
3619 eecd &= ~E1000_EECD_DI;
3620 ew32(EECD, eecd);
3621 }
3622
3623
3624
3625
3626
3627
3628 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
3629 {
3630 u32 eecd;
3631 u32 i;
3632 u16 data;
3633
3634
3635
3636
3637
3638
3639
3640
3641 eecd = er32(EECD);
3642
3643 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3644 data = 0;
3645
3646 for (i = 0; i < count; i++) {
3647 data = data << 1;
3648 e1000_raise_ee_clk(hw, &eecd);
3649
3650 eecd = er32(EECD);
3651
3652 eecd &= ~(E1000_EECD_DI);
3653 if (eecd & E1000_EECD_DO)
3654 data |= 1;
3655
3656 e1000_lower_ee_clk(hw, &eecd);
3657 }
3658
3659 return data;
3660 }
3661
3662
3663
3664
3665
3666
3667
3668
3669 static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3670 {
3671 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3672 u32 eecd, i = 0;
3673
3674 eecd = er32(EECD);
3675
3676
3677 if (hw->mac_type > e1000_82544) {
3678 eecd |= E1000_EECD_REQ;
3679 ew32(EECD, eecd);
3680 eecd = er32(EECD);
3681 while ((!(eecd & E1000_EECD_GNT)) &&
3682 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3683 i++;
3684 udelay(5);
3685 eecd = er32(EECD);
3686 }
3687 if (!(eecd & E1000_EECD_GNT)) {
3688 eecd &= ~E1000_EECD_REQ;
3689 ew32(EECD, eecd);
3690 e_dbg("Could not acquire EEPROM grant\n");
3691 return -E1000_ERR_EEPROM;
3692 }
3693 }
3694
3695
3696
3697 if (eeprom->type == e1000_eeprom_microwire) {
3698
3699 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3700 ew32(EECD, eecd);
3701
3702
3703 eecd |= E1000_EECD_CS;
3704 ew32(EECD, eecd);
3705 } else if (eeprom->type == e1000_eeprom_spi) {
3706
3707 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3708 ew32(EECD, eecd);
3709 E1000_WRITE_FLUSH();
3710 udelay(1);
3711 }
3712
3713 return E1000_SUCCESS;
3714 }
3715
3716
3717
3718
3719
3720 static void e1000_standby_eeprom(struct e1000_hw *hw)
3721 {
3722 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3723 u32 eecd;
3724
3725 eecd = er32(EECD);
3726
3727 if (eeprom->type == e1000_eeprom_microwire) {
3728 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3729 ew32(EECD, eecd);
3730 E1000_WRITE_FLUSH();
3731 udelay(eeprom->delay_usec);
3732
3733
3734 eecd |= E1000_EECD_SK;
3735 ew32(EECD, eecd);
3736 E1000_WRITE_FLUSH();
3737 udelay(eeprom->delay_usec);
3738
3739
3740 eecd |= E1000_EECD_CS;
3741 ew32(EECD, eecd);
3742 E1000_WRITE_FLUSH();
3743 udelay(eeprom->delay_usec);
3744
3745
3746 eecd &= ~E1000_EECD_SK;
3747 ew32(EECD, eecd);
3748 E1000_WRITE_FLUSH();
3749 udelay(eeprom->delay_usec);
3750 } else if (eeprom->type == e1000_eeprom_spi) {
3751
3752 eecd |= E1000_EECD_CS;
3753 ew32(EECD, eecd);
3754 E1000_WRITE_FLUSH();
3755 udelay(eeprom->delay_usec);
3756 eecd &= ~E1000_EECD_CS;
3757 ew32(EECD, eecd);
3758 E1000_WRITE_FLUSH();
3759 udelay(eeprom->delay_usec);
3760 }
3761 }
3762
3763
3764
3765
3766
3767
3768
3769 static void e1000_release_eeprom(struct e1000_hw *hw)
3770 {
3771 u32 eecd;
3772
3773 eecd = er32(EECD);
3774
3775 if (hw->eeprom.type == e1000_eeprom_spi) {
3776 eecd |= E1000_EECD_CS;
3777 eecd &= ~E1000_EECD_SK;
3778
3779 ew32(EECD, eecd);
3780 E1000_WRITE_FLUSH();
3781
3782 udelay(hw->eeprom.delay_usec);
3783 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3784
3785
3786
3787 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3788
3789 ew32(EECD, eecd);
3790
3791
3792 eecd |= E1000_EECD_SK;
3793 ew32(EECD, eecd);
3794 E1000_WRITE_FLUSH();
3795 udelay(hw->eeprom.delay_usec);
3796
3797
3798 eecd &= ~E1000_EECD_SK;
3799 ew32(EECD, eecd);
3800 E1000_WRITE_FLUSH();
3801 udelay(hw->eeprom.delay_usec);
3802 }
3803
3804
3805 if (hw->mac_type > e1000_82544) {
3806 eecd &= ~E1000_EECD_REQ;
3807 ew32(EECD, eecd);
3808 }
3809 }
3810
3811
3812
3813
3814
3815 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3816 {
3817 u16 retry_count = 0;
3818 u8 spi_stat_reg;
3819
3820
3821
3822
3823
3824
3825 retry_count = 0;
3826 do {
3827 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3828 hw->eeprom.opcode_bits);
3829 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
3830 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3831 break;
3832
3833 udelay(5);
3834 retry_count += 5;
3835
3836 e1000_standby_eeprom(hw);
3837 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3838
3839
3840
3841
3842 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3843 e_dbg("SPI EEPROM Status error\n");
3844 return -E1000_ERR_EEPROM;
3845 }
3846
3847 return E1000_SUCCESS;
3848 }
3849
3850
3851
3852
3853
3854
3855
3856
3857 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3858 {
3859 s32 ret;
3860
3861 mutex_lock(&e1000_eeprom_lock);
3862 ret = e1000_do_read_eeprom(hw, offset, words, data);
3863 mutex_unlock(&e1000_eeprom_lock);
3864 return ret;
3865 }
3866
3867 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3868 u16 *data)
3869 {
3870 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3871 u32 i = 0;
3872
3873 if (hw->mac_type == e1000_ce4100) {
3874 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
3875 data);
3876 return E1000_SUCCESS;
3877 }
3878
3879
3880
3881
3882 if ((offset >= eeprom->word_size) ||
3883 (words > eeprom->word_size - offset) ||
3884 (words == 0)) {
3885 e_dbg("\"words\" parameter out of bounds. Words = %d,"
3886 "size = %d\n", offset, eeprom->word_size);
3887 return -E1000_ERR_EEPROM;
3888 }
3889
3890
3891
3892
3893
3894
3895 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3896 return -E1000_ERR_EEPROM;
3897
3898
3899
3900
3901 if (eeprom->type == e1000_eeprom_spi) {
3902 u16 word_in;
3903 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3904
3905 if (e1000_spi_eeprom_ready(hw)) {
3906 e1000_release_eeprom(hw);
3907 return -E1000_ERR_EEPROM;
3908 }
3909
3910 e1000_standby_eeprom(hw);
3911
3912
3913
3914
3915 if ((eeprom->address_bits == 8) && (offset >= 128))
3916 read_opcode |= EEPROM_A8_OPCODE_SPI;
3917
3918
3919 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3920 e1000_shift_out_ee_bits(hw, (u16)(offset * 2),
3921 eeprom->address_bits);
3922
3923
3924
3925
3926
3927
3928
3929
3930 for (i = 0; i < words; i++) {
3931 word_in = e1000_shift_in_ee_bits(hw, 16);
3932 data[i] = (word_in >> 8) | (word_in << 8);
3933 }
3934 } else if (eeprom->type == e1000_eeprom_microwire) {
3935 for (i = 0; i < words; i++) {
3936
3937 e1000_shift_out_ee_bits(hw,
3938 EEPROM_READ_OPCODE_MICROWIRE,
3939 eeprom->opcode_bits);
3940 e1000_shift_out_ee_bits(hw, (u16)(offset + i),
3941 eeprom->address_bits);
3942
3943
3944
3945
3946 data[i] = e1000_shift_in_ee_bits(hw, 16);
3947 e1000_standby_eeprom(hw);
3948 cond_resched();
3949 }
3950 }
3951
3952
3953 e1000_release_eeprom(hw);
3954
3955 return E1000_SUCCESS;
3956 }
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3967 {
3968 u16 checksum = 0;
3969 u16 i, eeprom_data;
3970
3971 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3972 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3973 e_dbg("EEPROM Read Error\n");
3974 return -E1000_ERR_EEPROM;
3975 }
3976 checksum += eeprom_data;
3977 }
3978
3979 #ifdef CONFIG_PARISC
3980
3981 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6))
3982 return E1000_SUCCESS;
3983
3984 #endif
3985 if (checksum == (u16)EEPROM_SUM)
3986 return E1000_SUCCESS;
3987 else {
3988 e_dbg("EEPROM Checksum Invalid\n");
3989 return -E1000_ERR_EEPROM;
3990 }
3991 }
3992
3993
3994
3995
3996
3997
3998
3999
4000 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
4001 {
4002 u16 checksum = 0;
4003 u16 i, eeprom_data;
4004
4005 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4006 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4007 e_dbg("EEPROM Read Error\n");
4008 return -E1000_ERR_EEPROM;
4009 }
4010 checksum += eeprom_data;
4011 }
4012 checksum = (u16)EEPROM_SUM - checksum;
4013 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4014 e_dbg("EEPROM Write Error\n");
4015 return -E1000_ERR_EEPROM;
4016 }
4017 return E1000_SUCCESS;
4018 }
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4031 {
4032 s32 ret;
4033
4034 mutex_lock(&e1000_eeprom_lock);
4035 ret = e1000_do_write_eeprom(hw, offset, words, data);
4036 mutex_unlock(&e1000_eeprom_lock);
4037 return ret;
4038 }
4039
4040 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
4041 u16 *data)
4042 {
4043 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4044 s32 status = 0;
4045
4046 if (hw->mac_type == e1000_ce4100) {
4047 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
4048 data);
4049 return E1000_SUCCESS;
4050 }
4051
4052
4053
4054
4055 if ((offset >= eeprom->word_size) ||
4056 (words > eeprom->word_size - offset) ||
4057 (words == 0)) {
4058 e_dbg("\"words\" parameter out of bounds\n");
4059 return -E1000_ERR_EEPROM;
4060 }
4061
4062
4063 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4064 return -E1000_ERR_EEPROM;
4065
4066 if (eeprom->type == e1000_eeprom_microwire) {
4067 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4068 } else {
4069 status = e1000_write_eeprom_spi(hw, offset, words, data);
4070 msleep(10);
4071 }
4072
4073
4074 e1000_release_eeprom(hw);
4075
4076 return status;
4077 }
4078
4079
4080
4081
4082
4083
4084
4085
4086 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
4087 u16 *data)
4088 {
4089 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4090 u16 widx = 0;
4091
4092 while (widx < words) {
4093 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
4094
4095 if (e1000_spi_eeprom_ready(hw))
4096 return -E1000_ERR_EEPROM;
4097
4098 e1000_standby_eeprom(hw);
4099 cond_resched();
4100
4101
4102 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4103 eeprom->opcode_bits);
4104
4105 e1000_standby_eeprom(hw);
4106
4107
4108
4109
4110 if ((eeprom->address_bits == 8) && (offset >= 128))
4111 write_opcode |= EEPROM_A8_OPCODE_SPI;
4112
4113
4114 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4115
4116 e1000_shift_out_ee_bits(hw, (u16)((offset + widx) * 2),
4117 eeprom->address_bits);
4118
4119
4120
4121
4122
4123
4124 while (widx < words) {
4125 u16 word_out = data[widx];
4126
4127 word_out = (word_out >> 8) | (word_out << 8);
4128 e1000_shift_out_ee_bits(hw, word_out, 16);
4129 widx++;
4130
4131
4132
4133
4134
4135
4136 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
4137 e1000_standby_eeprom(hw);
4138 break;
4139 }
4140 }
4141 }
4142
4143 return E1000_SUCCESS;
4144 }
4145
4146
4147
4148
4149
4150
4151
4152
4153 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4154 u16 words, u16 *data)
4155 {
4156 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4157 u32 eecd;
4158 u16 words_written = 0;
4159 u16 i = 0;
4160
4161
4162
4163
4164
4165
4166
4167 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4168 (u16)(eeprom->opcode_bits + 2));
4169
4170 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
4171
4172
4173 e1000_standby_eeprom(hw);
4174
4175 while (words_written < words) {
4176
4177 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4178 eeprom->opcode_bits);
4179
4180 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
4181 eeprom->address_bits);
4182
4183
4184 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4185
4186
4187
4188
4189 e1000_standby_eeprom(hw);
4190
4191
4192
4193
4194
4195
4196 for (i = 0; i < 200; i++) {
4197 eecd = er32(EECD);
4198 if (eecd & E1000_EECD_DO)
4199 break;
4200 udelay(50);
4201 }
4202 if (i == 200) {
4203 e_dbg("EEPROM Write did not complete\n");
4204 return -E1000_ERR_EEPROM;
4205 }
4206
4207
4208 e1000_standby_eeprom(hw);
4209 cond_resched();
4210
4211 words_written++;
4212 }
4213
4214
4215
4216
4217
4218
4219
4220 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4221 (u16)(eeprom->opcode_bits + 2));
4222
4223 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
4224
4225 return E1000_SUCCESS;
4226 }
4227
4228
4229
4230
4231
4232
4233
4234
4235 s32 e1000_read_mac_addr(struct e1000_hw *hw)
4236 {
4237 u16 offset;
4238 u16 eeprom_data, i;
4239
4240 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4241 offset = i >> 1;
4242 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4243 e_dbg("EEPROM Read Error\n");
4244 return -E1000_ERR_EEPROM;
4245 }
4246 hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
4247 hw->perm_mac_addr[i + 1] = (u8)(eeprom_data >> 8);
4248 }
4249
4250 switch (hw->mac_type) {
4251 default:
4252 break;
4253 case e1000_82546:
4254 case e1000_82546_rev_3:
4255 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4256 hw->perm_mac_addr[5] ^= 0x01;
4257 break;
4258 }
4259
4260 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4261 hw->mac_addr[i] = hw->perm_mac_addr[i];
4262 return E1000_SUCCESS;
4263 }
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273 static void e1000_init_rx_addrs(struct e1000_hw *hw)
4274 {
4275 u32 i;
4276 u32 rar_num;
4277
4278
4279 e_dbg("Programming MAC Address into RAR[0]\n");
4280
4281 e1000_rar_set(hw, hw->mac_addr, 0);
4282
4283 rar_num = E1000_RAR_ENTRIES;
4284
4285
4286
4287
4288 e_dbg("Clearing RAR[1-14]\n");
4289 for (i = 1; i < rar_num; i++) {
4290 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4291 E1000_WRITE_FLUSH();
4292 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4293 E1000_WRITE_FLUSH();
4294 }
4295 }
4296
4297
4298
4299
4300
4301
4302 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
4303 {
4304 u32 hash_value = 0;
4305
4306
4307
4308
4309 switch (hw->mc_filter_type) {
4310
4311
4312
4313
4314 case 0:
4315
4316 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
4317 break;
4318 case 1:
4319
4320 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
4321 break;
4322 case 2:
4323
4324 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
4325 break;
4326 case 3:
4327
4328 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
4329 break;
4330 }
4331
4332 hash_value &= 0xFFF;
4333 return hash_value;
4334 }
4335
4336
4337
4338
4339
4340
4341
4342 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
4343 {
4344 u32 rar_low, rar_high;
4345
4346
4347
4348
4349 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
4350 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
4351 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371 switch (hw->mac_type) {
4372 default:
4373
4374 rar_high |= E1000_RAH_AV;
4375 break;
4376 }
4377
4378 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4379 E1000_WRITE_FLUSH();
4380 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4381 E1000_WRITE_FLUSH();
4382 }
4383
4384
4385
4386
4387
4388
4389
4390 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
4391 {
4392 u32 temp;
4393
4394 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4395 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4396 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4397 E1000_WRITE_FLUSH();
4398 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4399 E1000_WRITE_FLUSH();
4400 } else {
4401 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4402 E1000_WRITE_FLUSH();
4403 }
4404 }
4405
4406
4407
4408
4409
4410 static void e1000_clear_vfta(struct e1000_hw *hw)
4411 {
4412 u32 offset;
4413 u32 vfta_value = 0;
4414 u32 vfta_offset = 0;
4415 u32 vfta_bit_in_reg = 0;
4416
4417 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4418
4419
4420
4421
4422 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4423 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4424 E1000_WRITE_FLUSH();
4425 }
4426 }
4427
4428 static s32 e1000_id_led_init(struct e1000_hw *hw)
4429 {
4430 u32 ledctl;
4431 const u32 ledctl_mask = 0x000000FF;
4432 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4433 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4434 u16 eeprom_data, i, temp;
4435 const u16 led_mask = 0x0F;
4436
4437 if (hw->mac_type < e1000_82540) {
4438
4439 return E1000_SUCCESS;
4440 }
4441
4442 ledctl = er32(LEDCTL);
4443 hw->ledctl_default = ledctl;
4444 hw->ledctl_mode1 = hw->ledctl_default;
4445 hw->ledctl_mode2 = hw->ledctl_default;
4446
4447 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4448 e_dbg("EEPROM Read Error\n");
4449 return -E1000_ERR_EEPROM;
4450 }
4451
4452 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4453 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4454 eeprom_data = ID_LED_DEFAULT;
4455 }
4456
4457 for (i = 0; i < 4; i++) {
4458 temp = (eeprom_data >> (i << 2)) & led_mask;
4459 switch (temp) {
4460 case ID_LED_ON1_DEF2:
4461 case ID_LED_ON1_ON2:
4462 case ID_LED_ON1_OFF2:
4463 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4464 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4465 break;
4466 case ID_LED_OFF1_DEF2:
4467 case ID_LED_OFF1_ON2:
4468 case ID_LED_OFF1_OFF2:
4469 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4470 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4471 break;
4472 default:
4473
4474 break;
4475 }
4476 switch (temp) {
4477 case ID_LED_DEF1_ON2:
4478 case ID_LED_ON1_ON2:
4479 case ID_LED_OFF1_ON2:
4480 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4481 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4482 break;
4483 case ID_LED_DEF1_OFF2:
4484 case ID_LED_ON1_OFF2:
4485 case ID_LED_OFF1_OFF2:
4486 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4487 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4488 break;
4489 default:
4490
4491 break;
4492 }
4493 }
4494 return E1000_SUCCESS;
4495 }
4496
4497
4498
4499
4500
4501
4502
4503 s32 e1000_setup_led(struct e1000_hw *hw)
4504 {
4505 u32 ledctl;
4506 s32 ret_val = E1000_SUCCESS;
4507
4508 switch (hw->mac_type) {
4509 case e1000_82542_rev2_0:
4510 case e1000_82542_rev2_1:
4511 case e1000_82543:
4512 case e1000_82544:
4513
4514 break;
4515 case e1000_82541:
4516 case e1000_82547:
4517 case e1000_82541_rev_2:
4518 case e1000_82547_rev_2:
4519
4520 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4521 &hw->phy_spd_default);
4522 if (ret_val)
4523 return ret_val;
4524 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4525 (u16)(hw->phy_spd_default &
4526 ~IGP01E1000_GMII_SPD));
4527 if (ret_val)
4528 return ret_val;
4529
4530 default:
4531 if (hw->media_type == e1000_media_type_fiber) {
4532 ledctl = er32(LEDCTL);
4533
4534 hw->ledctl_default = ledctl;
4535
4536 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4537 E1000_LEDCTL_LED0_BLINK |
4538 E1000_LEDCTL_LED0_MODE_MASK);
4539 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4540 E1000_LEDCTL_LED0_MODE_SHIFT);
4541 ew32(LEDCTL, ledctl);
4542 } else if (hw->media_type == e1000_media_type_copper)
4543 ew32(LEDCTL, hw->ledctl_mode1);
4544 break;
4545 }
4546
4547 return E1000_SUCCESS;
4548 }
4549
4550
4551
4552
4553
4554 s32 e1000_cleanup_led(struct e1000_hw *hw)
4555 {
4556 s32 ret_val = E1000_SUCCESS;
4557
4558 switch (hw->mac_type) {
4559 case e1000_82542_rev2_0:
4560 case e1000_82542_rev2_1:
4561 case e1000_82543:
4562 case e1000_82544:
4563
4564 break;
4565 case e1000_82541:
4566 case e1000_82547:
4567 case e1000_82541_rev_2:
4568 case e1000_82547_rev_2:
4569
4570 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4571 hw->phy_spd_default);
4572 if (ret_val)
4573 return ret_val;
4574
4575 default:
4576
4577 ew32(LEDCTL, hw->ledctl_default);
4578 break;
4579 }
4580
4581 return E1000_SUCCESS;
4582 }
4583
4584
4585
4586
4587
4588 s32 e1000_led_on(struct e1000_hw *hw)
4589 {
4590 u32 ctrl = er32(CTRL);
4591
4592 switch (hw->mac_type) {
4593 case e1000_82542_rev2_0:
4594 case e1000_82542_rev2_1:
4595 case e1000_82543:
4596
4597 ctrl |= E1000_CTRL_SWDPIN0;
4598 ctrl |= E1000_CTRL_SWDPIO0;
4599 break;
4600 case e1000_82544:
4601 if (hw->media_type == e1000_media_type_fiber) {
4602
4603 ctrl |= E1000_CTRL_SWDPIN0;
4604 ctrl |= E1000_CTRL_SWDPIO0;
4605 } else {
4606
4607 ctrl &= ~E1000_CTRL_SWDPIN0;
4608 ctrl |= E1000_CTRL_SWDPIO0;
4609 }
4610 break;
4611 default:
4612 if (hw->media_type == e1000_media_type_fiber) {
4613
4614 ctrl &= ~E1000_CTRL_SWDPIN0;
4615 ctrl |= E1000_CTRL_SWDPIO0;
4616 } else if (hw->media_type == e1000_media_type_copper) {
4617 ew32(LEDCTL, hw->ledctl_mode2);
4618 return E1000_SUCCESS;
4619 }
4620 break;
4621 }
4622
4623 ew32(CTRL, ctrl);
4624
4625 return E1000_SUCCESS;
4626 }
4627
4628
4629
4630
4631
4632 s32 e1000_led_off(struct e1000_hw *hw)
4633 {
4634 u32 ctrl = er32(CTRL);
4635
4636 switch (hw->mac_type) {
4637 case e1000_82542_rev2_0:
4638 case e1000_82542_rev2_1:
4639 case e1000_82543:
4640
4641 ctrl &= ~E1000_CTRL_SWDPIN0;
4642 ctrl |= E1000_CTRL_SWDPIO0;
4643 break;
4644 case e1000_82544:
4645 if (hw->media_type == e1000_media_type_fiber) {
4646
4647 ctrl &= ~E1000_CTRL_SWDPIN0;
4648 ctrl |= E1000_CTRL_SWDPIO0;
4649 } else {
4650
4651 ctrl |= E1000_CTRL_SWDPIN0;
4652 ctrl |= E1000_CTRL_SWDPIO0;
4653 }
4654 break;
4655 default:
4656 if (hw->media_type == e1000_media_type_fiber) {
4657
4658 ctrl |= E1000_CTRL_SWDPIN0;
4659 ctrl |= E1000_CTRL_SWDPIO0;
4660 } else if (hw->media_type == e1000_media_type_copper) {
4661 ew32(LEDCTL, hw->ledctl_mode1);
4662 return E1000_SUCCESS;
4663 }
4664 break;
4665 }
4666
4667 ew32(CTRL, ctrl);
4668
4669 return E1000_SUCCESS;
4670 }
4671
4672
4673
4674
4675
4676 static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4677 {
4678 volatile u32 temp;
4679
4680 temp = er32(CRCERRS);
4681 temp = er32(SYMERRS);
4682 temp = er32(MPC);
4683 temp = er32(SCC);
4684 temp = er32(ECOL);
4685 temp = er32(MCC);
4686 temp = er32(LATECOL);
4687 temp = er32(COLC);
4688 temp = er32(DC);
4689 temp = er32(SEC);
4690 temp = er32(RLEC);
4691 temp = er32(XONRXC);
4692 temp = er32(XONTXC);
4693 temp = er32(XOFFRXC);
4694 temp = er32(XOFFTXC);
4695 temp = er32(FCRUC);
4696
4697 temp = er32(PRC64);
4698 temp = er32(PRC127);
4699 temp = er32(PRC255);
4700 temp = er32(PRC511);
4701 temp = er32(PRC1023);
4702 temp = er32(PRC1522);
4703
4704 temp = er32(GPRC);
4705 temp = er32(BPRC);
4706 temp = er32(MPRC);
4707 temp = er32(GPTC);
4708 temp = er32(GORCL);
4709 temp = er32(GORCH);
4710 temp = er32(GOTCL);
4711 temp = er32(GOTCH);
4712 temp = er32(RNBC);
4713 temp = er32(RUC);
4714 temp = er32(RFC);
4715 temp = er32(ROC);
4716 temp = er32(RJC);
4717 temp = er32(TORL);
4718 temp = er32(TORH);
4719 temp = er32(TOTL);
4720 temp = er32(TOTH);
4721 temp = er32(TPR);
4722 temp = er32(TPT);
4723
4724 temp = er32(PTC64);
4725 temp = er32(PTC127);
4726 temp = er32(PTC255);
4727 temp = er32(PTC511);
4728 temp = er32(PTC1023);
4729 temp = er32(PTC1522);
4730
4731 temp = er32(MPTC);
4732 temp = er32(BPTC);
4733
4734 if (hw->mac_type < e1000_82543)
4735 return;
4736
4737 temp = er32(ALGNERRC);
4738 temp = er32(RXERRC);
4739 temp = er32(TNCRS);
4740 temp = er32(CEXTERR);
4741 temp = er32(TSCTC);
4742 temp = er32(TSCTFC);
4743
4744 if (hw->mac_type <= e1000_82544)
4745 return;
4746
4747 temp = er32(MGTPRC);
4748 temp = er32(MGTPDC);
4749 temp = er32(MGTPTC);
4750 }
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761 void e1000_reset_adaptive(struct e1000_hw *hw)
4762 {
4763 if (hw->adaptive_ifs) {
4764 if (!hw->ifs_params_forced) {
4765 hw->current_ifs_val = 0;
4766 hw->ifs_min_val = IFS_MIN;
4767 hw->ifs_max_val = IFS_MAX;
4768 hw->ifs_step_size = IFS_STEP;
4769 hw->ifs_ratio = IFS_RATIO;
4770 }
4771 hw->in_ifs_mode = false;
4772 ew32(AIT, 0);
4773 } else {
4774 e_dbg("Not in Adaptive IFS mode!\n");
4775 }
4776 }
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787 void e1000_update_adaptive(struct e1000_hw *hw)
4788 {
4789 if (hw->adaptive_ifs) {
4790 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4791 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4792 hw->in_ifs_mode = true;
4793 if (hw->current_ifs_val < hw->ifs_max_val) {
4794 if (hw->current_ifs_val == 0)
4795 hw->current_ifs_val =
4796 hw->ifs_min_val;
4797 else
4798 hw->current_ifs_val +=
4799 hw->ifs_step_size;
4800 ew32(AIT, hw->current_ifs_val);
4801 }
4802 }
4803 } else {
4804 if (hw->in_ifs_mode &&
4805 (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4806 hw->current_ifs_val = 0;
4807 hw->in_ifs_mode = false;
4808 ew32(AIT, 0);
4809 }
4810 }
4811 } else {
4812 e_dbg("Not in Adaptive IFS mode!\n");
4813 }
4814 }
4815
4816
4817
4818
4819
4820
4821
4822 void e1000_get_bus_info(struct e1000_hw *hw)
4823 {
4824 u32 status;
4825
4826 switch (hw->mac_type) {
4827 case e1000_82542_rev2_0:
4828 case e1000_82542_rev2_1:
4829 hw->bus_type = e1000_bus_type_pci;
4830 hw->bus_speed = e1000_bus_speed_unknown;
4831 hw->bus_width = e1000_bus_width_unknown;
4832 break;
4833 default:
4834 status = er32(STATUS);
4835 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4836 e1000_bus_type_pcix : e1000_bus_type_pci;
4837
4838 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4839 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4840 e1000_bus_speed_66 : e1000_bus_speed_120;
4841 } else if (hw->bus_type == e1000_bus_type_pci) {
4842 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4843 e1000_bus_speed_66 : e1000_bus_speed_33;
4844 } else {
4845 switch (status & E1000_STATUS_PCIX_SPEED) {
4846 case E1000_STATUS_PCIX_SPEED_66:
4847 hw->bus_speed = e1000_bus_speed_66;
4848 break;
4849 case E1000_STATUS_PCIX_SPEED_100:
4850 hw->bus_speed = e1000_bus_speed_100;
4851 break;
4852 case E1000_STATUS_PCIX_SPEED_133:
4853 hw->bus_speed = e1000_bus_speed_133;
4854 break;
4855 default:
4856 hw->bus_speed = e1000_bus_speed_reserved;
4857 break;
4858 }
4859 }
4860 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4861 e1000_bus_width_64 : e1000_bus_width_32;
4862 break;
4863 }
4864 }
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
4876 {
4877 unsigned long io_addr = hw->io_base;
4878 unsigned long io_data = hw->io_base + 4;
4879
4880 e1000_io_write(hw, io_addr, offset);
4881 e1000_io_write(hw, io_data, value);
4882 }
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
4899 u16 *max_length)
4900 {
4901 s32 ret_val;
4902 u16 agc_value = 0;
4903 u16 i, phy_data;
4904 u16 cable_length;
4905
4906 *min_length = *max_length = 0;
4907
4908
4909 if (hw->phy_type == e1000_phy_m88) {
4910 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4911 &phy_data);
4912 if (ret_val)
4913 return ret_val;
4914 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4915 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
4916
4917
4918 switch (cable_length) {
4919 case e1000_cable_length_50:
4920 *min_length = 0;
4921 *max_length = e1000_igp_cable_length_50;
4922 break;
4923 case e1000_cable_length_50_80:
4924 *min_length = e1000_igp_cable_length_50;
4925 *max_length = e1000_igp_cable_length_80;
4926 break;
4927 case e1000_cable_length_80_110:
4928 *min_length = e1000_igp_cable_length_80;
4929 *max_length = e1000_igp_cable_length_110;
4930 break;
4931 case e1000_cable_length_110_140:
4932 *min_length = e1000_igp_cable_length_110;
4933 *max_length = e1000_igp_cable_length_140;
4934 break;
4935 case e1000_cable_length_140:
4936 *min_length = e1000_igp_cable_length_140;
4937 *max_length = e1000_igp_cable_length_170;
4938 break;
4939 default:
4940 return -E1000_ERR_PHY;
4941 }
4942 } else if (hw->phy_type == e1000_phy_igp) {
4943 u16 cur_agc_value;
4944 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4945 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
4946 IGP01E1000_PHY_AGC_A,
4947 IGP01E1000_PHY_AGC_B,
4948 IGP01E1000_PHY_AGC_C,
4949 IGP01E1000_PHY_AGC_D
4950 };
4951
4952 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4953 ret_val =
4954 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4955 if (ret_val)
4956 return ret_val;
4957
4958 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4959
4960
4961 if ((cur_agc_value >=
4962 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4963 (cur_agc_value == 0))
4964 return -E1000_ERR_PHY;
4965
4966 agc_value += cur_agc_value;
4967
4968
4969 if (min_agc_value > cur_agc_value)
4970 min_agc_value = cur_agc_value;
4971 }
4972
4973
4974 if (agc_value <
4975 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4976 agc_value -= min_agc_value;
4977
4978
4979 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4980 } else {
4981
4982 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4983 }
4984
4985
4986 *min_length = ((e1000_igp_cable_length_table[agc_value] -
4987 IGP01E1000_AGC_RANGE) > 0) ?
4988 (e1000_igp_cable_length_table[agc_value] -
4989 IGP01E1000_AGC_RANGE) : 0;
4990 *max_length = e1000_igp_cable_length_table[agc_value] +
4991 IGP01E1000_AGC_RANGE;
4992 }
4993
4994 return E1000_SUCCESS;
4995 }
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012 static s32 e1000_check_polarity(struct e1000_hw *hw,
5013 e1000_rev_polarity *polarity)
5014 {
5015 s32 ret_val;
5016 u16 phy_data;
5017
5018 if (hw->phy_type == e1000_phy_m88) {
5019
5020 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5021 &phy_data);
5022 if (ret_val)
5023 return ret_val;
5024 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
5025 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
5026 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
5027
5028 } else if (hw->phy_type == e1000_phy_igp) {
5029
5030 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5031 &phy_data);
5032 if (ret_val)
5033 return ret_val;
5034
5035
5036
5037
5038 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5039 IGP01E1000_PSSR_SPEED_1000MBPS) {
5040
5041 ret_val =
5042 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5043 &phy_data);
5044 if (ret_val)
5045 return ret_val;
5046
5047
5048 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5049 e1000_rev_polarity_reversed :
5050 e1000_rev_polarity_normal;
5051 } else {
5052
5053
5054
5055 *polarity =
5056 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5057 e1000_rev_polarity_reversed :
5058 e1000_rev_polarity_normal;
5059 }
5060 }
5061 return E1000_SUCCESS;
5062 }
5063
5064
5065
5066
5067
5068
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078 static s32 e1000_check_downshift(struct e1000_hw *hw)
5079 {
5080 s32 ret_val;
5081 u16 phy_data;
5082
5083 if (hw->phy_type == e1000_phy_igp) {
5084 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5085 &phy_data);
5086 if (ret_val)
5087 return ret_val;
5088
5089 hw->speed_downgraded =
5090 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5091 } else if (hw->phy_type == e1000_phy_m88) {
5092 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5093 &phy_data);
5094 if (ret_val)
5095 return ret_val;
5096
5097 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5098 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5099 }
5100
5101 return E1000_SUCCESS;
5102 }
5103
5104 static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5105 IGP01E1000_PHY_AGC_PARAM_A,
5106 IGP01E1000_PHY_AGC_PARAM_B,
5107 IGP01E1000_PHY_AGC_PARAM_C,
5108 IGP01E1000_PHY_AGC_PARAM_D
5109 };
5110
5111 static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw)
5112 {
5113 u16 min_length, max_length;
5114 u16 phy_data, i;
5115 s32 ret_val;
5116
5117 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
5118 if (ret_val)
5119 return ret_val;
5120
5121 if (hw->dsp_config_state != e1000_dsp_config_enabled)
5122 return 0;
5123
5124 if (min_length >= e1000_igp_cable_length_50) {
5125 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5126 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
5127 &phy_data);
5128 if (ret_val)
5129 return ret_val;
5130
5131 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5132
5133 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
5134 phy_data);
5135 if (ret_val)
5136 return ret_val;
5137 }
5138 hw->dsp_config_state = e1000_dsp_config_activated;
5139 } else {
5140 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5141 u32 idle_errs = 0;
5142
5143
5144 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
5145 if (ret_val)
5146 return ret_val;
5147
5148 for (i = 0; i < ffe_idle_err_timeout; i++) {
5149 udelay(1000);
5150 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5151 &phy_data);
5152 if (ret_val)
5153 return ret_val;
5154
5155 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
5156 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
5157 hw->ffe_config_state = e1000_ffe_config_active;
5158
5159 ret_val = e1000_write_phy_reg(hw,
5160 IGP01E1000_PHY_DSP_FFE,
5161 IGP01E1000_PHY_DSP_FFE_CM_CP);
5162 if (ret_val)
5163 return ret_val;
5164 break;
5165 }
5166
5167 if (idle_errs)
5168 ffe_idle_err_timeout =
5169 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5170 }
5171 }
5172
5173 return 0;
5174 }
5175
5176
5177
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187
5188 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5189 {
5190 s32 ret_val;
5191 u16 phy_data, phy_saved_data, speed, duplex, i;
5192
5193 if (hw->phy_type != e1000_phy_igp)
5194 return E1000_SUCCESS;
5195
5196 if (link_up) {
5197 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5198 if (ret_val) {
5199 e_dbg("Error getting link speed and duplex\n");
5200 return ret_val;
5201 }
5202
5203 if (speed == SPEED_1000) {
5204 ret_val = e1000_1000Mb_check_cable_length(hw);
5205 if (ret_val)
5206 return ret_val;
5207 }
5208 } else {
5209 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5210
5211
5212
5213 ret_val =
5214 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5215
5216 if (ret_val)
5217 return ret_val;
5218
5219
5220 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5221
5222 if (ret_val)
5223 return ret_val;
5224
5225 msleep(20);
5226
5227 ret_val = e1000_write_phy_reg(hw, 0x0000,
5228 IGP01E1000_IEEE_FORCE_GIGA);
5229 if (ret_val)
5230 return ret_val;
5231 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5232 ret_val =
5233 e1000_read_phy_reg(hw, dsp_reg_array[i],
5234 &phy_data);
5235 if (ret_val)
5236 return ret_val;
5237
5238 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5239 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5240
5241 ret_val =
5242 e1000_write_phy_reg(hw, dsp_reg_array[i],
5243 phy_data);
5244 if (ret_val)
5245 return ret_val;
5246 }
5247
5248 ret_val = e1000_write_phy_reg(hw, 0x0000,
5249 IGP01E1000_IEEE_RESTART_AUTONEG);
5250 if (ret_val)
5251 return ret_val;
5252
5253 msleep(20);
5254
5255
5256 ret_val =
5257 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5258
5259 if (ret_val)
5260 return ret_val;
5261
5262 hw->dsp_config_state = e1000_dsp_config_enabled;
5263 }
5264
5265 if (hw->ffe_config_state == e1000_ffe_config_active) {
5266
5267
5268
5269 ret_val =
5270 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5271
5272 if (ret_val)
5273 return ret_val;
5274
5275
5276 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5277
5278 if (ret_val)
5279 return ret_val;
5280
5281 msleep(20);
5282
5283 ret_val = e1000_write_phy_reg(hw, 0x0000,
5284 IGP01E1000_IEEE_FORCE_GIGA);
5285 if (ret_val)
5286 return ret_val;
5287 ret_val =
5288 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5289 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5290 if (ret_val)
5291 return ret_val;
5292
5293 ret_val = e1000_write_phy_reg(hw, 0x0000,
5294 IGP01E1000_IEEE_RESTART_AUTONEG);
5295 if (ret_val)
5296 return ret_val;
5297
5298 msleep(20);
5299
5300
5301 ret_val =
5302 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5303
5304 if (ret_val)
5305 return ret_val;
5306
5307 hw->ffe_config_state = e1000_ffe_config_enabled;
5308 }
5309 }
5310 return E1000_SUCCESS;
5311 }
5312
5313
5314
5315
5316
5317
5318
5319
5320
5321 static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5322 {
5323 s32 ret_val;
5324 u16 eeprom_data;
5325
5326 if ((hw->mac_type == e1000_82545_rev_3) &&
5327 (hw->media_type == e1000_media_type_copper)) {
5328 ret_val =
5329 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5330 &eeprom_data);
5331 if (ret_val)
5332 return ret_val;
5333
5334 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5335 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5336 ret_val =
5337 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5338 0x000B);
5339 if (ret_val)
5340 return ret_val;
5341 ret_val =
5342 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5343 0x8104);
5344 if (ret_val)
5345 return ret_val;
5346
5347 hw->phy_reset_disable = false;
5348 }
5349 }
5350
5351 return E1000_SUCCESS;
5352 }
5353
5354
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5368 {
5369 s32 ret_val;
5370 u16 phy_data;
5371
5372 if (hw->phy_type != e1000_phy_igp)
5373 return E1000_SUCCESS;
5374
5375
5376
5377
5378
5379 if (hw->mac_type == e1000_82541_rev_2 ||
5380 hw->mac_type == e1000_82547_rev_2) {
5381 ret_val =
5382 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5383 if (ret_val)
5384 return ret_val;
5385 }
5386
5387 if (!active) {
5388 if (hw->mac_type == e1000_82541_rev_2 ||
5389 hw->mac_type == e1000_82547_rev_2) {
5390 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5391 ret_val =
5392 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5393 phy_data);
5394 if (ret_val)
5395 return ret_val;
5396 }
5397
5398
5399
5400
5401
5402
5403 if (hw->smart_speed == e1000_smart_speed_on) {
5404 ret_val =
5405 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5406 &phy_data);
5407 if (ret_val)
5408 return ret_val;
5409
5410 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5411 ret_val =
5412 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5413 phy_data);
5414 if (ret_val)
5415 return ret_val;
5416 } else if (hw->smart_speed == e1000_smart_speed_off) {
5417 ret_val =
5418 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5419 &phy_data);
5420 if (ret_val)
5421 return ret_val;
5422
5423 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5424 ret_val =
5425 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5426 phy_data);
5427 if (ret_val)
5428 return ret_val;
5429 }
5430 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5431 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
5432 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5433 if (hw->mac_type == e1000_82541_rev_2 ||
5434 hw->mac_type == e1000_82547_rev_2) {
5435 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5436 ret_val =
5437 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5438 phy_data);
5439 if (ret_val)
5440 return ret_val;
5441 }
5442
5443
5444 ret_val =
5445 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5446 &phy_data);
5447 if (ret_val)
5448 return ret_val;
5449
5450 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5451 ret_val =
5452 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5453 phy_data);
5454 if (ret_val)
5455 return ret_val;
5456 }
5457 return E1000_SUCCESS;
5458 }
5459
5460
5461
5462
5463
5464
5465
5466 static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5467 {
5468 s32 ret_val;
5469 u16 default_page = 0;
5470 u16 phy_data;
5471
5472 switch (hw->mac_type) {
5473 case e1000_82545_rev_3:
5474 case e1000_82546_rev_3:
5475 break;
5476 default:
5477 return E1000_SUCCESS;
5478 }
5479
5480
5481
5482 ret_val =
5483 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5484 if (ret_val)
5485 return ret_val;
5486
5487 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5488 if (ret_val)
5489 return ret_val;
5490
5491 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5492 if (ret_val)
5493 return ret_val;
5494
5495 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5496 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5497 if (ret_val)
5498 return ret_val;
5499
5500
5501
5502 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5503 if (ret_val)
5504 return ret_val;
5505
5506 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5507 if (ret_val)
5508 return ret_val;
5509
5510 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5511 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5512 if (ret_val)
5513 return ret_val;
5514
5515 ret_val =
5516 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5517 if (ret_val)
5518 return ret_val;
5519
5520 return E1000_SUCCESS;
5521 }
5522
5523
5524
5525
5526
5527
5528
5529
5530 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
5531 {
5532 u32 manc;
5533
5534 if (hw->asf_firmware_present) {
5535 manc = er32(MANC);
5536
5537 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5538 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5539 return false;
5540 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5541 return true;
5542 }
5543 return false;
5544 }
5545
5546 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5547 {
5548 s32 ret_val;
5549 u16 mii_status_reg;
5550 u16 i;
5551
5552
5553
5554
5555
5556 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5557 if (ret_val)
5558 return ret_val;
5559 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5560 if (ret_val)
5561 return ret_val;
5562
5563 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5564 if (ret_val)
5565 return ret_val;
5566
5567
5568 for (i = PHY_FORCE_TIME; i > 0; i--) {
5569
5570
5571
5572
5573 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5574 if (ret_val)
5575 return ret_val;
5576
5577 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5578 if (ret_val)
5579 return ret_val;
5580
5581 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5582 break;
5583 msleep(100);
5584 }
5585
5586
5587 msleep(1000);
5588
5589
5590
5591 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5592 if (ret_val)
5593 return ret_val;
5594 msleep(50);
5595 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5596 if (ret_val)
5597 return ret_val;
5598 msleep(50);
5599 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5600 if (ret_val)
5601 return ret_val;
5602 msleep(50);
5603 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5604 if (ret_val)
5605 return ret_val;
5606
5607 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5608 if (ret_val)
5609 return ret_val;
5610
5611
5612 for (i = PHY_FORCE_TIME; i > 0; i--) {
5613
5614
5615
5616
5617 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5618 if (ret_val)
5619 return ret_val;
5620
5621 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5622 if (ret_val)
5623 return ret_val;
5624
5625 if (mii_status_reg & MII_SR_LINK_STATUS)
5626 break;
5627 msleep(100);
5628 }
5629 return E1000_SUCCESS;
5630 }
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5641 {
5642 msleep(5);
5643 return E1000_SUCCESS;
5644 }
5645
5646
5647
5648
5649
5650
5651
5652
5653
5654 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5655 {
5656 msleep(10);
5657 return E1000_SUCCESS;
5658 }