1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
3
4 /* e1000_hw.c
5 * Shared functions for accessing and configuring the MAC
6 */
7
8 #include "e1000.h"
9
10 static s32 e1000_check_downshift(struct e1000_hw *hw);
11 static s32 e1000_check_polarity(struct e1000_hw *hw,
12 e1000_rev_polarity *polarity);
13 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
14 static void e1000_clear_vfta(struct e1000_hw *hw);
15 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
16 bool link_up);
17 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
18 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
19 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
20 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
21 u16 *max_length);
22 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
23 static s32 e1000_id_led_init(struct e1000_hw *hw);
24 static void e1000_init_rx_addrs(struct e1000_hw *hw);
25 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
26 struct e1000_phy_info *phy_info);
27 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
28 struct e1000_phy_info *phy_info);
29 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
30 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
31 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
32 static s32 e1000_set_phy_type(struct e1000_hw *hw);
33 static void e1000_phy_init_script(struct e1000_hw *hw);
34 static s32 e1000_setup_copper_link(struct e1000_hw *hw);
35 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
36 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
37 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
38 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
39 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
40 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
41 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
42 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
43 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
44 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
45 u16 words, u16 *data);
46 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
47 u16 words, u16 *data);
48 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
49 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
50 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
51 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
52 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
53 u16 phy_data);
54 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
55 u16 *phy_data);
56 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
57 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
58 static void e1000_release_eeprom(struct e1000_hw *hw);
59 static void e1000_standby_eeprom(struct e1000_hw *hw);
60 static s32 e1000_set_vco_speed(struct e1000_hw *hw);
61 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
62 static s32 e1000_set_phy_mode(struct e1000_hw *hw);
63 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
64 u16 *data);
65 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
66 u16 *data);
67
68 /* IGP cable length table */
69 static const
70 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
71 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
72 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
73 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
74 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
75 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
76 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
77 100,
78 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
79 110, 110,
80 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
81 120, 120
82 };
83
84 static DEFINE_MUTEX(e1000_eeprom_lock);
85 static DEFINE_SPINLOCK(e1000_phy_lock);
86
87 /**
88 * e1000_set_phy_type - Set the phy type member in the hw struct.
89 * @hw: Struct containing variables accessed by shared code
90 */
91 static s32 e1000_set_phy_type(struct e1000_hw *hw)
92 {
93 if (hw->mac_type == e1000_undefined)
94 return -E1000_ERR_PHY_TYPE;
95
96 switch (hw->phy_id) {
97 case M88E1000_E_PHY_ID:
98 case M88E1000_I_PHY_ID:
99 case M88E1011_I_PHY_ID:
100 case M88E1111_I_PHY_ID:
101 case M88E1118_E_PHY_ID:
102 hw->phy_type = e1000_phy_m88;
103 break;
104 case IGP01E1000_I_PHY_ID:
105 if (hw->mac_type == e1000_82541 ||
106 hw->mac_type == e1000_82541_rev_2 ||
107 hw->mac_type == e1000_82547 ||
108 hw->mac_type == e1000_82547_rev_2)
109 hw->phy_type = e1000_phy_igp;
110 break;
111 case RTL8211B_PHY_ID:
112 hw->phy_type = e1000_phy_8211;
113 break;
114 case RTL8201N_PHY_ID:
115 hw->phy_type = e1000_phy_8201;
116 break;
117 default:
118 /* Should never have loaded on this device */
119 hw->phy_type = e1000_phy_undefined;
120 return -E1000_ERR_PHY_TYPE;
121 }
122
123 return E1000_SUCCESS;
124 }
125
126 /**
127 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
128 * @hw: Struct containing variables accessed by shared code
129 */
130 static void e1000_phy_init_script(struct e1000_hw *hw)
131 {
132 u32 ret_val;
133 u16 phy_saved_data;
134
135 if (hw->phy_init_script) {
136 msleep(20);
137
138 /* Save off the current value of register 0x2F5B to be restored
139 * at the end of this routine.
140 */
141 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
142
143 /* Disabled the PHY transmitter */
144 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
145 msleep(20);
146
147 e1000_write_phy_reg(hw, 0x0000, 0x0140);
148 msleep(5);
149
150 switch (hw->mac_type) {
151 case e1000_82541:
152 case e1000_82547:
153 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
154 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
155 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
156 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
157 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
158 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
159 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
160 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
161 e1000_write_phy_reg(hw, 0x2010, 0x0008);
162 break;
163
164 case e1000_82541_rev_2:
165 case e1000_82547_rev_2:
166 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
167 break;
168 default:
169 break;
170 }
171
172 e1000_write_phy_reg(hw, 0x0000, 0x3300);
173 msleep(20);
174
175 /* Now enable the transmitter */
176 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
177
178 if (hw->mac_type == e1000_82547) {
179 u16 fused, fine, coarse;
180
181 /* Move to analog registers page */
182 e1000_read_phy_reg(hw,
183 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
184 &fused);
185
186 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
187 e1000_read_phy_reg(hw,
188 IGP01E1000_ANALOG_FUSE_STATUS,
189 &fused);
190
191 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
192 coarse =
193 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
194
195 if (coarse >
196 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
197 coarse -=
198 IGP01E1000_ANALOG_FUSE_COARSE_10;
199 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
200 } else if (coarse ==
201 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
202 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
203
204 fused =
205 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
206 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
207 (coarse &
208 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
209
210 e1000_write_phy_reg(hw,
211 IGP01E1000_ANALOG_FUSE_CONTROL,
212 fused);
213 e1000_write_phy_reg(hw,
214 IGP01E1000_ANALOG_FUSE_BYPASS,
215 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
216 }
217 }
218 }
219 }
220
221 /**
222 * e1000_set_mac_type - Set the mac type member in the hw struct.
223 * @hw: Struct containing variables accessed by shared code
224 */
225 s32 e1000_set_mac_type(struct e1000_hw *hw)
226 {
227 switch (hw->device_id) {
228 case E1000_DEV_ID_82542:
229 switch (hw->revision_id) {
230 case E1000_82542_2_0_REV_ID:
231 hw->mac_type = e1000_82542_rev2_0;
232 break;
233 case E1000_82542_2_1_REV_ID:
234 hw->mac_type = e1000_82542_rev2_1;
235 break;
236 default:
237 /* Invalid 82542 revision ID */
238 return -E1000_ERR_MAC_TYPE;
239 }
240 break;
241 case E1000_DEV_ID_82543GC_FIBER:
242 case E1000_DEV_ID_82543GC_COPPER:
243 hw->mac_type = e1000_82543;
244 break;
245 case E1000_DEV_ID_82544EI_COPPER:
246 case E1000_DEV_ID_82544EI_FIBER:
247 case E1000_DEV_ID_82544GC_COPPER:
248 case E1000_DEV_ID_82544GC_LOM:
249 hw->mac_type = e1000_82544;
250 break;
251 case E1000_DEV_ID_82540EM:
252 case E1000_DEV_ID_82540EM_LOM:
253 case E1000_DEV_ID_82540EP:
254 case E1000_DEV_ID_82540EP_LOM:
255 case E1000_DEV_ID_82540EP_LP:
256 hw->mac_type = e1000_82540;
257 break;
258 case E1000_DEV_ID_82545EM_COPPER:
259 case E1000_DEV_ID_82545EM_FIBER:
260 hw->mac_type = e1000_82545;
261 break;
262 case E1000_DEV_ID_82545GM_COPPER:
263 case E1000_DEV_ID_82545GM_FIBER:
264 case E1000_DEV_ID_82545GM_SERDES:
265 hw->mac_type = e1000_82545_rev_3;
266 break;
267 case E1000_DEV_ID_82546EB_COPPER:
268 case E1000_DEV_ID_82546EB_FIBER:
269 case E1000_DEV_ID_82546EB_QUAD_COPPER:
270 hw->mac_type = e1000_82546;
271 break;
272 case E1000_DEV_ID_82546GB_COPPER:
273 case E1000_DEV_ID_82546GB_FIBER:
274 case E1000_DEV_ID_82546GB_SERDES:
275 case E1000_DEV_ID_82546GB_PCIE:
276 case E1000_DEV_ID_82546GB_QUAD_COPPER:
277 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
278 hw->mac_type = e1000_82546_rev_3;
279 break;
280 case E1000_DEV_ID_82541EI:
281 case E1000_DEV_ID_82541EI_MOBILE:
282 case E1000_DEV_ID_82541ER_LOM:
283 hw->mac_type = e1000_82541;
284 break;
285 case E1000_DEV_ID_82541ER:
286 case E1000_DEV_ID_82541GI:
287 case E1000_DEV_ID_82541GI_LF:
288 case E1000_DEV_ID_82541GI_MOBILE:
289 hw->mac_type = e1000_82541_rev_2;
290 break;
291 case E1000_DEV_ID_82547EI:
292 case E1000_DEV_ID_82547EI_MOBILE:
293 hw->mac_type = e1000_82547;
294 break;
295 case E1000_DEV_ID_82547GI:
296 hw->mac_type = e1000_82547_rev_2;
297 break;
298 case E1000_DEV_ID_INTEL_CE4100_GBE:
299 hw->mac_type = e1000_ce4100;
300 break;
301 default:
302 /* Should never have loaded on this device */
303 return -E1000_ERR_MAC_TYPE;
304 }
305
306 switch (hw->mac_type) {
307 case e1000_82541:
308 case e1000_82547:
309 case e1000_82541_rev_2:
310 case e1000_82547_rev_2:
311 hw->asf_firmware_present = true;
312 break;
313 default:
314 break;
315 }
316
317 /* The 82543 chip does not count tx_carrier_errors properly in
318 * FD mode
319 */
320 if (hw->mac_type == e1000_82543)
321 hw->bad_tx_carr_stats_fd = true;
322
323 if (hw->mac_type > e1000_82544)
324 hw->has_smbus = true;
325
326 return E1000_SUCCESS;
327 }
328
329 /**
330 * e1000_set_media_type - Set media type and TBI compatibility.
331 * @hw: Struct containing variables accessed by shared code
332 */
333 void e1000_set_media_type(struct e1000_hw *hw)
334 {
335 u32 status;
336
337 if (hw->mac_type != e1000_82543) {
338 /* tbi_compatibility is only valid on 82543 */
339 hw->tbi_compatibility_en = false;
340 }
341
342 switch (hw->device_id) {
343 case E1000_DEV_ID_82545GM_SERDES:
344 case E1000_DEV_ID_82546GB_SERDES:
345 hw->media_type = e1000_media_type_internal_serdes;
346 break;
347 default:
348 switch (hw->mac_type) {
349 case e1000_82542_rev2_0:
350 case e1000_82542_rev2_1:
351 hw->media_type = e1000_media_type_fiber;
352 break;
353 case e1000_ce4100:
354 hw->media_type = e1000_media_type_copper;
355 break;
356 default:
357 status = er32(STATUS);
358 if (status & E1000_STATUS_TBIMODE) {
359 hw->media_type = e1000_media_type_fiber;
360 /* tbi_compatibility not valid on fiber */
361 hw->tbi_compatibility_en = false;
362 } else {
363 hw->media_type = e1000_media_type_copper;
364 }
365 break;
366 }
367 }
368 }
369
370 /**
371 * e1000_reset_hw - reset the hardware completely
372 * @hw: Struct containing variables accessed by shared code
373 *
374 * Reset the transmit and receive units; mask and clear all interrupts.
375 */
376 s32 e1000_reset_hw(struct e1000_hw *hw)
377 {
378 u32 ctrl;
379 u32 ctrl_ext;
380 u32 icr;
381 u32 manc;
382 u32 led_ctrl;
383 s32 ret_val;
384
385 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
386 if (hw->mac_type == e1000_82542_rev2_0) {
387 e_dbg("Disabling MWI on 82542 rev 2.0\n");
388 e1000_pci_clear_mwi(hw);
389 }
390
391 /* Clear interrupt mask to stop board from generating interrupts */
392 e_dbg("Masking off all interrupts\n");
393 ew32(IMC, 0xffffffff);
394
395 /* Disable the Transmit and Receive units. Then delay to allow
396 * any pending transactions to complete before we hit the MAC with
397 * the global reset.
398 */
399 ew32(RCTL, 0);
400 ew32(TCTL, E1000_TCTL_PSP);
401 E1000_WRITE_FLUSH();
402
403 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
404 hw->tbi_compatibility_on = false;
405
406 /* Delay to allow any outstanding PCI transactions to complete before
407 * resetting the device
408 */
409 msleep(10);
410
411 ctrl = er32(CTRL);
412
413 /* Must reset the PHY before resetting the MAC */
414 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
415 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
416 E1000_WRITE_FLUSH();
417 msleep(5);
418 }
419
420 /* Issue a global reset to the MAC. This will reset the chip's
421 * transmit, receive, DMA, and link units. It will not effect
422 * the current PCI configuration. The global reset bit is self-
423 * clearing, and should clear within a microsecond.
424 */
425 e_dbg("Issuing a global reset to MAC\n");
426
427 switch (hw->mac_type) {
428 case e1000_82544:
429 case e1000_82540:
430 case e1000_82545:
431 case e1000_82546:
432 case e1000_82541:
433 case e1000_82541_rev_2:
434 /* These controllers can't ack the 64-bit write when issuing the
435 * reset, so use IO-mapping as a workaround to issue the reset
436 */
437 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
438 break;
439 case e1000_82545_rev_3:
440 case e1000_82546_rev_3:
441 /* Reset is performed on a shadow of the control register */
442 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
443 break;
444 case e1000_ce4100:
445 default:
446 ew32(CTRL, (ctrl | E1000_CTRL_RST));
447 break;
448 }
449
450 /* After MAC reset, force reload of EEPROM to restore power-on settings
451 * to device. Later controllers reload the EEPROM automatically, so
452 * just wait for reload to complete.
453 */
454 switch (hw->mac_type) {
455 case e1000_82542_rev2_0:
456 case e1000_82542_rev2_1:
457 case e1000_82543:
458 case e1000_82544:
459 /* Wait for reset to complete */
460 udelay(10);
461 ctrl_ext = er32(CTRL_EXT);
462 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
463 ew32(CTRL_EXT, ctrl_ext);
464 E1000_WRITE_FLUSH();
465 /* Wait for EEPROM reload */
466 msleep(2);
467 break;
468 case e1000_82541:
469 case e1000_82541_rev_2:
470 case e1000_82547:
471 case e1000_82547_rev_2:
472 /* Wait for EEPROM reload */
473 msleep(20);
474 break;
475 default:
476 /* Auto read done will delay 5ms or poll based on mac type */
477 ret_val = e1000_get_auto_rd_done(hw);
478 if (ret_val)
479 return ret_val;
480 break;
481 }
482
483 /* Disable HW ARPs on ASF enabled adapters */
484 if (hw->mac_type >= e1000_82540) {
485 manc = er32(MANC);
486 manc &= ~(E1000_MANC_ARP_EN);
487 ew32(MANC, manc);
488 }
489
490 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
491 e1000_phy_init_script(hw);
492
493 /* Configure activity LED after PHY reset */
494 led_ctrl = er32(LEDCTL);
495 led_ctrl &= IGP_ACTIVITY_LED_MASK;
496 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
497 ew32(LEDCTL, led_ctrl);
498 }
499
500 /* Clear interrupt mask to stop board from generating interrupts */
501 e_dbg("Masking off all interrupts\n");
502 ew32(IMC, 0xffffffff);
503
504 /* Clear any pending interrupt events. */
505 icr = er32(ICR);
506
507 /* If MWI was previously enabled, reenable it. */
508 if (hw->mac_type == e1000_82542_rev2_0) {
509 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
510 e1000_pci_set_mwi(hw);
511 }
512
513 return E1000_SUCCESS;
514 }
515
516 /**
517 * e1000_init_hw - Performs basic configuration of the adapter.
518 * @hw: Struct containing variables accessed by shared code
519 *
520 * Assumes that the controller has previously been reset and is in a
521 * post-reset uninitialized state. Initializes the receive address registers,
522 * multicast table, and VLAN filter table. Calls routines to setup link
523 * configuration and flow control settings. Clears all on-chip counters. Leaves
524 * the transmit and receive units disabled and uninitialized.
525 */
526 s32 e1000_init_hw(struct e1000_hw *hw)
527 {
528 u32 ctrl;
529 u32 i;
530 s32 ret_val;
531 u32 mta_size;
532 u32 ctrl_ext;
533
534 /* Initialize Identification LED */
535 ret_val = e1000_id_led_init(hw);
536 if (ret_val) {
537 e_dbg("Error Initializing Identification LED\n");
538 return ret_val;
539 }
540
541 /* Set the media type and TBI compatibility */
542 e1000_set_media_type(hw);
543
544 /* Disabling VLAN filtering. */
545 e_dbg("Initializing the IEEE VLAN\n");
546 if (hw->mac_type < e1000_82545_rev_3)
547 ew32(VET, 0);
548 e1000_clear_vfta(hw);
549
550 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
551 if (hw->mac_type == e1000_82542_rev2_0) {
552 e_dbg("Disabling MWI on 82542 rev 2.0\n");
553 e1000_pci_clear_mwi(hw);
554 ew32(RCTL, E1000_RCTL_RST);
555 E1000_WRITE_FLUSH();
556 msleep(5);
557 }
558
559 /* Setup the receive address. This involves initializing all of the
560 * Receive Address Registers (RARs 0 - 15).
561 */
562 e1000_init_rx_addrs(hw);
563
564 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
565 if (hw->mac_type == e1000_82542_rev2_0) {
566 ew32(RCTL, 0);
567 E1000_WRITE_FLUSH();
568 msleep(1);
569 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
570 e1000_pci_set_mwi(hw);
571 }
572
573 /* Zero out the Multicast HASH table */
574 e_dbg("Zeroing the MTA\n");
575 mta_size = E1000_MC_TBL_SIZE;
576 for (i = 0; i < mta_size; i++) {
577 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
578 /* use write flush to prevent Memory Write Block (MWB) from
579 * occurring when accessing our register space
580 */
581 E1000_WRITE_FLUSH();
582 }
583
584 /* Set the PCI priority bit correctly in the CTRL register. This
585 * determines if the adapter gives priority to receives, or if it
586 * gives equal priority to transmits and receives. Valid only on
587 * 82542 and 82543 silicon.
588 */
589 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
590 ctrl = er32(CTRL);
591 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
592 }
593
594 switch (hw->mac_type) {
595 case e1000_82545_rev_3:
596 case e1000_82546_rev_3:
597 break;
598 default:
599 /* Workaround for PCI-X problem when BIOS sets MMRBC
600 * incorrectly.
601 */
602 if (hw->bus_type == e1000_bus_type_pcix &&
603 e1000_pcix_get_mmrbc(hw) > 2048)
604 e1000_pcix_set_mmrbc(hw, 2048);
605 break;
606 }
607
608 /* Call a subroutine to configure the link and setup flow control. */
609 ret_val = e1000_setup_link(hw);
610
611 /* Set the transmit descriptor write-back policy */
612 if (hw->mac_type > e1000_82544) {
613 ctrl = er32(TXDCTL);
614 ctrl =
615 (ctrl & ~E1000_TXDCTL_WTHRESH) |
616 E1000_TXDCTL_FULL_TX_DESC_WB;
617 ew32(TXDCTL, ctrl);
618 }
619
620 /* Clear all of the statistics registers (clear on read). It is
621 * important that we do this after we have tried to establish link
622 * because the symbol error count will increment wildly if there
623 * is no link.
624 */
625 e1000_clear_hw_cntrs(hw);
626
627 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
628 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
629 ctrl_ext = er32(CTRL_EXT);
630 /* Relaxed ordering must be disabled to avoid a parity
631 * error crash in a PCI slot.
632 */
633 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
634 ew32(CTRL_EXT, ctrl_ext);
635 }
636
637 return ret_val;
638 }
639
640 /**
641 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
642 * @hw: Struct containing variables accessed by shared code.
643 */
644 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
645 {
646 u16 eeprom_data;
647 s32 ret_val;
648
649 if (hw->media_type != e1000_media_type_internal_serdes)
650 return E1000_SUCCESS;
651
652 switch (hw->mac_type) {
653 case e1000_82545_rev_3:
654 case e1000_82546_rev_3:
655 break;
656 default:
657 return E1000_SUCCESS;
658 }
659
660 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
661 &eeprom_data);
662 if (ret_val)
663 return ret_val;
664
665 if (eeprom_data != EEPROM_RESERVED_WORD) {
666 /* Adjust SERDES output amplitude only. */
667 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
668 ret_val =
669 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
670 if (ret_val)
671 return ret_val;
672 }
673
674 return E1000_SUCCESS;
675 }
676
677 /**
678 * e1000_setup_link - Configures flow control and link settings.
679 * @hw: Struct containing variables accessed by shared code
680 *
681 * Determines which flow control settings to use. Calls the appropriate media-
682 * specific link configuration function. Configures the flow control settings.
683 * Assuming the adapter has a valid link partner, a valid link should be
684 * established. Assumes the hardware has previously been reset and the
685 * transmitter and receiver are not enabled.
686 */
687 s32 e1000_setup_link(struct e1000_hw *hw)
688 {
689 u32 ctrl_ext;
690 s32 ret_val;
691 u16 eeprom_data;
692
693 /* Read and store word 0x0F of the EEPROM. This word contains bits
694 * that determine the hardware's default PAUSE (flow control) mode,
695 * a bit that determines whether the HW defaults to enabling or
696 * disabling auto-negotiation, and the direction of the
697 * SW defined pins. If there is no SW over-ride of the flow
698 * control setting, then the variable hw->fc will
699 * be initialized based on a value in the EEPROM.
700 */
701 if (hw->fc == E1000_FC_DEFAULT) {
702 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
703 1, &eeprom_data);
704 if (ret_val) {
705 e_dbg("EEPROM Read Error\n");
706 return -E1000_ERR_EEPROM;
707 }
708 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
709 hw->fc = E1000_FC_NONE;
710 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
711 EEPROM_WORD0F_ASM_DIR)
712 hw->fc = E1000_FC_TX_PAUSE;
713 else
714 hw->fc = E1000_FC_FULL;
715 }
716
717 /* We want to save off the original Flow Control configuration just
718 * in case we get disconnected and then reconnected into a different
719 * hub or switch with different Flow Control capabilities.
720 */
721 if (hw->mac_type == e1000_82542_rev2_0)
722 hw->fc &= (~E1000_FC_TX_PAUSE);
723
724 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
725 hw->fc &= (~E1000_FC_RX_PAUSE);
726
727 hw->original_fc = hw->fc;
728
729 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);
730
731 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
732 * polarity value for the SW controlled pins, and setup the
733 * Extended Device Control reg with that info.
734 * This is needed because one of the SW controlled pins is used for
735 * signal detection. So this should be done before e1000_setup_pcs_link()
736 * or e1000_phy_setup() is called.
737 */
738 if (hw->mac_type == e1000_82543) {
739 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
740 1, &eeprom_data);
741 if (ret_val) {
742 e_dbg("EEPROM Read Error\n");
743 return -E1000_ERR_EEPROM;
744 }
745 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
746 SWDPIO__EXT_SHIFT);
747 ew32(CTRL_EXT, ctrl_ext);
748 }
749
750 /* Call the necessary subroutine to configure the link. */
751 ret_val = (hw->media_type == e1000_media_type_copper) ?
752 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
753
754 /* Initialize the flow control address, type, and PAUSE timer
755 * registers to their default values. This is done even if flow
756 * control is disabled, because it does not hurt anything to
757 * initialize these registers.
758 */
759 e_dbg("Initializing the Flow Control address, type and timer regs\n");
760
761 ew32(FCT, FLOW_CONTROL_TYPE);
762 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
763 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
764
765 ew32(FCTTV, hw->fc_pause_time);
766
767 /* Set the flow control receive threshold registers. Normally,
768 * these registers will be set to a default threshold that may be
769 * adjusted later by the driver's runtime code. However, if the
770 * ability to transmit pause frames in not enabled, then these
771 * registers will be set to 0.
772 */
773 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
774 ew32(FCRTL, 0);
775 ew32(FCRTH, 0);
776 } else {
777 /* We need to set up the Receive Threshold high and low water
778 * marks as well as (optionally) enabling the transmission of
779 * XON frames.
780 */
781 if (hw->fc_send_xon) {
782 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
783 ew32(FCRTH, hw->fc_high_water);
784 } else {
785 ew32(FCRTL, hw->fc_low_water);
786 ew32(FCRTH, hw->fc_high_water);
787 }
788 }
789 return ret_val;
790 }
791
792 /**
793 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
794 * @hw: Struct containing variables accessed by shared code
795 *
796 * Manipulates Physical Coding Sublayer functions in order to configure
797 * link. Assumes the hardware has been previously reset and the transmitter
798 * and receiver are not enabled.
799 */
800 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
801 {
802 u32 ctrl;
803 u32 status;
804 u32 txcw = 0;
805 u32 i;
806 u32 signal = 0;
807 s32 ret_val;
808
809 /* On adapters with a MAC newer than 82544, SWDP 1 will be
810 * set when the optics detect a signal. On older adapters, it will be
811 * cleared when there is a signal. This applies to fiber media only.
812 * If we're on serdes media, adjust the output amplitude to value
813 * set in the EEPROM.
814 */
815 ctrl = er32(CTRL);
816 if (hw->media_type == e1000_media_type_fiber)
817 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
818
819 ret_val = e1000_adjust_serdes_amplitude(hw);
820 if (ret_val)
821 return ret_val;
822
823 /* Take the link out of reset */
824 ctrl &= ~(E1000_CTRL_LRST);
825
826 /* Adjust VCO speed to improve BER performance */
827 ret_val = e1000_set_vco_speed(hw);
828 if (ret_val)
829 return ret_val;
830
831 e1000_config_collision_dist(hw);
832
833 /* Check for a software override of the flow control settings, and setup
834 * the device accordingly. If auto-negotiation is enabled, then
835 * software will have to set the "PAUSE" bits to the correct value in
836 * the Tranmsit Config Word Register (TXCW) and re-start
837 * auto-negotiation. However, if auto-negotiation is disabled, then
838 * software will have to manually configure the two flow control enable
839 * bits in the CTRL register.
840 *
841 * The possible values of the "fc" parameter are:
842 * 0: Flow control is completely disabled
843 * 1: Rx flow control is enabled (we can receive pause frames, but
844 * not send pause frames).
845 * 2: Tx flow control is enabled (we can send pause frames but we do
846 * not support receiving pause frames).
847 * 3: Both Rx and TX flow control (symmetric) are enabled.
848 */
849 switch (hw->fc) {
850 case E1000_FC_NONE:
851 /* Flow ctrl is completely disabled by a software over-ride */
852 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
853 break;
854 case E1000_FC_RX_PAUSE:
855 /* Rx Flow control is enabled and Tx Flow control is disabled by
856 * a software over-ride. Since there really isn't a way to
857 * advertise that we are capable of Rx Pause ONLY, we will
858 * advertise that we support both symmetric and asymmetric Rx
859 * PAUSE. Later, we will disable the adapter's ability to send
860 * PAUSE frames.
861 */
862 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
863 break;
864 case E1000_FC_TX_PAUSE:
865 /* Tx Flow control is enabled, and Rx Flow control is disabled,
866 * by a software over-ride.
867 */
868 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
869 break;
870 case E1000_FC_FULL:
871 /* Flow control (both Rx and Tx) is enabled by a software
872 * over-ride.
873 */
874 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
875 break;
876 default:
877 e_dbg("Flow control param set incorrectly\n");
878 return -E1000_ERR_CONFIG;
879 }
880
881 /* Since auto-negotiation is enabled, take the link out of reset (the
882 * link will be in reset, because we previously reset the chip). This
883 * will restart auto-negotiation. If auto-negotiation is successful
884 * then the link-up status bit will be set and the flow control enable
885 * bits (RFCE and TFCE) will be set according to their negotiated value.
886 */
887 e_dbg("Auto-negotiation enabled\n");
888
889 ew32(TXCW, txcw);
890 ew32(CTRL, ctrl);
891 E1000_WRITE_FLUSH();
892
893 hw->txcw = txcw;
894 msleep(1);
895
896 /* If we have a signal (the cable is plugged in) then poll for a
897 * "Link-Up" indication in the Device Status Register. Time-out if a
898 * link isn't seen in 500 milliseconds seconds (Auto-negotiation should
899 * complete in less than 500 milliseconds even if the other end is doing
900 * it in SW). For internal serdes, we just assume a signal is present,
901 * then poll.
902 */
903 if (hw->media_type == e1000_media_type_internal_serdes ||
904 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
905 e_dbg("Looking for Link\n");
906 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
907 msleep(10);
908 status = er32(STATUS);
909 if (status & E1000_STATUS_LU)
910 break;
911 }
912 if (i == (LINK_UP_TIMEOUT / 10)) {
913 e_dbg("Never got a valid link from auto-neg!!!\n");
914 hw->autoneg_failed = 1;
915 /* AutoNeg failed to achieve a link, so we'll call
916 * e1000_check_for_link. This routine will force the
917 * link up if we detect a signal. This will allow us to
918 * communicate with non-autonegotiating link partners.
919 */
920 ret_val = e1000_check_for_link(hw);
921 if (ret_val) {
922 e_dbg("Error while checking for link\n");
923 return ret_val;
924 }
925 hw->autoneg_failed = 0;
926 } else {
927 hw->autoneg_failed = 0;
928 e_dbg("Valid Link Found\n");
929 }
930 } else {
931 e_dbg("No Signal Detected\n");
932 }
933 return E1000_SUCCESS;
934 }
935
936 /**
937 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.
938 * @hw: Struct containing variables accessed by shared code
939 *
940 * Commits changes to PHY configuration by calling e1000_phy_reset().
941 */
942 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
943 {
944 s32 ret_val;
945
946 /* SW reset the PHY so all changes take effect */
947 ret_val = e1000_phy_reset(hw);
948 if (ret_val) {
949 e_dbg("Error Resetting the PHY\n");
950 return ret_val;
951 }
952
953 return E1000_SUCCESS;
954 }
955
956 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
957 {
958 s32 ret_val;
959 u32 ctrl_aux;
960
961 switch (hw->phy_type) {
962 case e1000_phy_8211:
963 ret_val = e1000_copper_link_rtl_setup(hw);
964 if (ret_val) {
965 e_dbg("e1000_copper_link_rtl_setup failed!\n");
966 return ret_val;
967 }
968 break;
969 case e1000_phy_8201:
970 /* Set RMII mode */
971 ctrl_aux = er32(CTL_AUX);
972 ctrl_aux |= E1000_CTL_AUX_RMII;
973 ew32(CTL_AUX, ctrl_aux);
974 E1000_WRITE_FLUSH();
975
976 /* Disable the J/K bits required for receive */
977 ctrl_aux = er32(CTL_AUX);
978 ctrl_aux |= 0x4;
979 ctrl_aux &= ~0x2;
980 ew32(CTL_AUX, ctrl_aux);
981 E1000_WRITE_FLUSH();
982 ret_val = e1000_copper_link_rtl_setup(hw);
983
984 if (ret_val) {
985 e_dbg("e1000_copper_link_rtl_setup failed!\n");
986 return ret_val;
987 }
988 break;
989 default:
990 e_dbg("Error Resetting the PHY\n");
991 return E1000_ERR_PHY_TYPE;
992 }
993
994 return E1000_SUCCESS;
995 }
996
997 /**
998 * e1000_copper_link_preconfig - early configuration for copper
999 * @hw: Struct containing variables accessed by shared code
1000 *
1001 * Make sure we have a valid PHY and change PHY mode before link setup.
1002 */
1003 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1004 {
1005 u32 ctrl;
1006 s32 ret_val;
1007 u16 phy_data;
1008
1009 ctrl = er32(CTRL);
1010 /* With 82543, we need to force speed and duplex on the MAC equal to
1011 * what the PHY speed and duplex configuration is. In addition, we need
1012 * to perform a hardware reset on the PHY to take it out of reset.
1013 */
1014 if (hw->mac_type > e1000_82543) {
1015 ctrl |= E1000_CTRL_SLU;
1016 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1017 ew32(CTRL, ctrl);
1018 } else {
1019 ctrl |=
1020 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1021 ew32(CTRL, ctrl);
1022 ret_val = e1000_phy_hw_reset(hw);
1023 if (ret_val)
1024 return ret_val;
1025 }
1026
1027 /* Make sure we have a valid PHY */
1028 ret_val = e1000_detect_gig_phy(hw);
1029 if (ret_val) {
1030 e_dbg("Error, did not detect valid phy.\n");
1031 return ret_val;
1032 }
1033 e_dbg("Phy ID = %x\n", hw->phy_id);
1034
1035 /* Set PHY to class A mode (if necessary) */
1036 ret_val = e1000_set_phy_mode(hw);
1037 if (ret_val)
1038 return ret_val;
1039
1040 if ((hw->mac_type == e1000_82545_rev_3) ||
1041 (hw->mac_type == e1000_82546_rev_3)) {
1042 ret_val =
1043 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1044 phy_data |= 0x00000008;
1045 ret_val =
1046 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1047 }
1048
1049 if (hw->mac_type <= e1000_82543 ||
1050 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1051 hw->mac_type == e1000_82541_rev_2 ||
1052 hw->mac_type == e1000_82547_rev_2)
1053 hw->phy_reset_disable = false;
1054
1055 return E1000_SUCCESS;
1056 }
1057
1058 /**
1059 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
1060 * @hw: Struct containing variables accessed by shared code
1061 */
1062 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1063 {
1064 u32 led_ctrl;
1065 s32 ret_val;
1066 u16 phy_data;
1067
1068 if (hw->phy_reset_disable)
1069 return E1000_SUCCESS;
1070
1071 ret_val = e1000_phy_reset(hw);
1072 if (ret_val) {
1073 e_dbg("Error Resetting the PHY\n");
1074 return ret_val;
1075 }
1076
1077 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1078 msleep(15);
1079 /* Configure activity LED after PHY reset */
1080 led_ctrl = er32(LEDCTL);
1081 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1082 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1083 ew32(LEDCTL, led_ctrl);
1084
1085 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1086 if (hw->phy_type == e1000_phy_igp) {
1087 /* disable lplu d3 during driver init */
1088 ret_val = e1000_set_d3_lplu_state(hw, false);
1089 if (ret_val) {
1090 e_dbg("Error Disabling LPLU D3\n");
1091 return ret_val;
1092 }
1093 }
1094
1095 /* Configure mdi-mdix settings */
1096 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1097 if (ret_val)
1098 return ret_val;
1099
1100 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1101 hw->dsp_config_state = e1000_dsp_config_disabled;
1102 /* Force MDI for earlier revs of the IGP PHY */
1103 phy_data &=
1104 ~(IGP01E1000_PSCR_AUTO_MDIX |
1105 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1106 hw->mdix = 1;
1107
1108 } else {
1109 hw->dsp_config_state = e1000_dsp_config_enabled;
1110 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1111
1112 switch (hw->mdix) {
1113 case 1:
1114 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1115 break;
1116 case 2:
1117 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1118 break;
1119 case 0:
1120 default:
1121 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1122 break;
1123 }
1124 }
1125 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1126 if (ret_val)
1127 return ret_val;
1128
1129 /* set auto-master slave resolution settings */
1130 if (hw->autoneg) {
1131 e1000_ms_type phy_ms_setting = hw->master_slave;
1132
1133 if (hw->ffe_config_state == e1000_ffe_config_active)
1134 hw->ffe_config_state = e1000_ffe_config_enabled;
1135
1136 if (hw->dsp_config_state == e1000_dsp_config_activated)
1137 hw->dsp_config_state = e1000_dsp_config_enabled;
1138
1139 /* when autonegotiation advertisement is only 1000Mbps then we
1140 * should disable SmartSpeed and enable Auto MasterSlave
1141 * resolution as hardware default.
1142 */
1143 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1144 /* Disable SmartSpeed */
1145 ret_val =
1146 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1147 &phy_data);
1148 if (ret_val)
1149 return ret_val;
1150 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1151 ret_val =
1152 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1153 phy_data);
1154 if (ret_val)
1155 return ret_val;
1156 /* Set auto Master/Slave resolution process */
1157 ret_val =
1158 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1159 if (ret_val)
1160 return ret_val;
1161 phy_data &= ~CR_1000T_MS_ENABLE;
1162 ret_val =
1163 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1164 if (ret_val)
1165 return ret_val;
1166 }
1167
1168 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1169 if (ret_val)
1170 return ret_val;
1171
1172 /* load defaults for future use */
1173 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1174 ((phy_data & CR_1000T_MS_VALUE) ?
1175 e1000_ms_force_master :
1176 e1000_ms_force_slave) : e1000_ms_auto;
1177
1178 switch (phy_ms_setting) {
1179 case e1000_ms_force_master:
1180 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1181 break;
1182 case e1000_ms_force_slave:
1183 phy_data |= CR_1000T_MS_ENABLE;
1184 phy_data &= ~(CR_1000T_MS_VALUE);
1185 break;
1186 case e1000_ms_auto:
1187 phy_data &= ~CR_1000T_MS_ENABLE;
1188 default:
1189 break;
1190 }
1191 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1192 if (ret_val)
1193 return ret_val;
1194 }
1195
1196 return E1000_SUCCESS;
1197 }
1198
1199 /**
1200 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
1201 * @hw: Struct containing variables accessed by shared code
1202 */
1203 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1204 {
1205 s32 ret_val;
1206 u16 phy_data;
1207
1208 if (hw->phy_reset_disable)
1209 return E1000_SUCCESS;
1210
1211 /* Enable CRS on TX. This must be set for half-duplex operation. */
1212 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1213 if (ret_val)
1214 return ret_val;
1215
1216 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1217
1218 /* Options:
1219 * MDI/MDI-X = 0 (default)
1220 * 0 - Auto for all speeds
1221 * 1 - MDI mode
1222 * 2 - MDI-X mode
1223 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1224 */
1225 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1226
1227 switch (hw->mdix) {
1228 case 1:
1229 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1230 break;
1231 case 2:
1232 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1233 break;
1234 case 3:
1235 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1236 break;
1237 case 0:
1238 default:
1239 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1240 break;
1241 }
1242
1243 /* Options:
1244 * disable_polarity_correction = 0 (default)
1245 * Automatic Correction for Reversed Cable Polarity
1246 * 0 - Disabled
1247 * 1 - Enabled
1248 */
1249 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1250 if (hw->disable_polarity_correction == 1)
1251 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1252 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1253 if (ret_val)
1254 return ret_val;
1255
1256 if (hw->phy_revision < M88E1011_I_REV_4) {
1257 /* Force TX_CLK in the Extended PHY Specific Control Register
1258 * to 25MHz clock.
1259 */
1260 ret_val =
1261 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1262 &phy_data);
1263 if (ret_val)
1264 return ret_val;
1265
1266 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1267
1268 if ((hw->phy_revision == E1000_REVISION_2) &&
1269 (hw->phy_id == M88E1111_I_PHY_ID)) {
1270 /* Vidalia Phy, set the downshift counter to 5x */
1271 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1272 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1273 ret_val = e1000_write_phy_reg(hw,
1274 M88E1000_EXT_PHY_SPEC_CTRL,
1275 phy_data);
1276 if (ret_val)
1277 return ret_val;
1278 } else {
1279 /* Configure Master and Slave downshift values */
1280 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1281 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1282 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1283 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1284 ret_val = e1000_write_phy_reg(hw,
1285 M88E1000_EXT_PHY_SPEC_CTRL,
1286 phy_data);
1287 if (ret_val)
1288 return ret_val;
1289 }
1290 }
1291
1292 /* SW Reset the PHY so all changes take effect */
1293 ret_val = e1000_phy_reset(hw);
1294 if (ret_val) {
1295 e_dbg("Error Resetting the PHY\n");
1296 return ret_val;
1297 }
1298
1299 return E1000_SUCCESS;
1300 }
1301
1302 /**
1303 * e1000_copper_link_autoneg - setup auto-neg
1304 * @hw: Struct containing variables accessed by shared code
1305 *
1306 * Setup auto-negotiation and flow control advertisements,
1307 * and then perform auto-negotiation.
1308 */
1309 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1310 {
1311 s32 ret_val;
1312 u16 phy_data;
1313
1314 /* Perform some bounds checking on the hw->autoneg_advertised
1315 * parameter. If this variable is zero, then set it to the default.
1316 */
1317 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1318
1319 /* If autoneg_advertised is zero, we assume it was not defaulted
1320 * by the calling code so we set to advertise full capability.
1321 */
1322 if (hw->autoneg_advertised == 0)
1323 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1324
1325 /* IFE/RTL8201N PHY only supports 10/100 */
1326 if (hw->phy_type == e1000_phy_8201)
1327 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1328
1329 e_dbg("Reconfiguring auto-neg advertisement params\n");
1330 ret_val = e1000_phy_setup_autoneg(hw);
1331 if (ret_val) {
1332 e_dbg("Error Setting up Auto-Negotiation\n");
1333 return ret_val;
1334 }
1335 e_dbg("Restarting Auto-Neg\n");
1336
1337 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1338 * the Auto Neg Restart bit in the PHY control register.
1339 */
1340 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1341 if (ret_val)
1342 return ret_val;
1343
1344 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1345 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1346 if (ret_val)
1347 return ret_val;
1348
1349 /* Does the user want to wait for Auto-Neg to complete here, or
1350 * check at a later time (for example, callback routine).
1351 */
1352 if (hw->wait_autoneg_complete) {
1353 ret_val = e1000_wait_autoneg(hw);
1354 if (ret_val) {
1355 e_dbg
1356 ("Error while waiting for autoneg to complete\n");
1357 return ret_val;
1358 }
1359 }
1360
1361 hw->get_link_status = true;
1362
1363 return E1000_SUCCESS;
1364 }
1365
1366 /**
1367 * e1000_copper_link_postconfig - post link setup
1368 * @hw: Struct containing variables accessed by shared code
1369 *
1370 * Config the MAC and the PHY after link is up.
1371 * 1) Set up the MAC to the current PHY speed/duplex
1372 * if we are on 82543. If we
1373 * are on newer silicon, we only need to configure
1374 * collision distance in the Transmit Control Register.
1375 * 2) Set up flow control on the MAC to that established with
1376 * the link partner.
1377 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1378 */
1379 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1380 {
1381 s32 ret_val;
1382
1383 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
1384 e1000_config_collision_dist(hw);
1385 } else {
1386 ret_val = e1000_config_mac_to_phy(hw);
1387 if (ret_val) {
1388 e_dbg("Error configuring MAC to PHY settings\n");
1389 return ret_val;
1390 }
1391 }
1392 ret_val = e1000_config_fc_after_link_up(hw);
1393 if (ret_val) {
1394 e_dbg("Error Configuring Flow Control\n");
1395 return ret_val;
1396 }
1397
1398 /* Config DSP to improve Giga link quality */
1399 if (hw->phy_type == e1000_phy_igp) {
1400 ret_val = e1000_config_dsp_after_link_change(hw, true);
1401 if (ret_val) {
1402 e_dbg("Error Configuring DSP after link up\n");
1403 return ret_val;
1404 }
1405 }
1406
1407 return E1000_SUCCESS;
1408 }
1409
1410 /**
1411 * e1000_setup_copper_link - phy/speed/duplex setting
1412 * @hw: Struct containing variables accessed by shared code
1413 *
1414 * Detects which PHY is present and sets up the speed and duplex
1415 */
1416 static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1417 {
1418 s32 ret_val;
1419 u16 i;
1420 u16 phy_data;
1421
1422 /* Check if it is a valid PHY and set PHY mode if necessary. */
1423 ret_val = e1000_copper_link_preconfig(hw);
1424 if (ret_val)
1425 return ret_val;
1426
1427 if (hw->phy_type == e1000_phy_igp) {
1428 ret_val = e1000_copper_link_igp_setup(hw);
1429 if (ret_val)
1430 return ret_val;
1431 } else if (hw->phy_type == e1000_phy_m88) {
1432 ret_val = e1000_copper_link_mgp_setup(hw);
1433 if (ret_val)
1434 return ret_val;
1435 } else {
1436 ret_val = gbe_dhg_phy_setup(hw);
1437 if (ret_val) {
1438 e_dbg("gbe_dhg_phy_setup failed!\n");
1439 return ret_val;
1440 }
1441 }
1442
1443 if (hw->autoneg) {
1444 /* Setup autoneg and flow control advertisement
1445 * and perform autonegotiation
1446 */
1447 ret_val = e1000_copper_link_autoneg(hw);
1448 if (ret_val)
1449 return ret_val;
1450 } else {
1451 /* PHY will be set to 10H, 10F, 100H,or 100F
1452 * depending on value from forced_speed_duplex.
1453 */
1454 e_dbg("Forcing speed and duplex\n");
1455 ret_val = e1000_phy_force_speed_duplex(hw);
1456 if (ret_val) {
1457 e_dbg("Error Forcing Speed and Duplex\n");
1458 return ret_val;
1459 }
1460 }
1461
1462 /* Check link status. Wait up to 100 microseconds for link to become
1463 * valid.
1464 */
1465 for (i = 0; i < 10; i++) {
1466 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1467 if (ret_val)
1468 return ret_val;
1469 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1470 if (ret_val)
1471 return ret_val;
1472
1473 if (phy_data & MII_SR_LINK_STATUS) {
1474 /* Config the MAC and PHY after link is up */
1475 ret_val = e1000_copper_link_postconfig(hw);
1476 if (ret_val)
1477 return ret_val;
1478
1479 e_dbg("Valid link established!!!\n");
1480 return E1000_SUCCESS;
1481 }
1482 udelay(10);
1483 }
1484
1485 e_dbg("Unable to establish link!!!\n");
1486 return E1000_SUCCESS;
1487 }
1488
1489 /**
1490 * e1000_phy_setup_autoneg - phy settings
1491 * @hw: Struct containing variables accessed by shared code
1492 *
1493 * Configures PHY autoneg and flow control advertisement settings
1494 */
1495 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1496 {
1497 s32 ret_val;
1498 u16 mii_autoneg_adv_reg;
1499 u16 mii_1000t_ctrl_reg;
1500
1501 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1502 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1503 if (ret_val)
1504 return ret_val;
1505
1506 /* Read the MII 1000Base-T Control Register (Address 9). */
1507 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1508 if (ret_val)
1509 return ret_val;
1510 else if (hw->phy_type == e1000_phy_8201)
1511 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1512
1513 /* Need to parse both autoneg_advertised and fc and set up
1514 * the appropriate PHY registers. First we will parse for
1515 * autoneg_advertised software override. Since we can advertise
1516 * a plethora of combinations, we need to check each bit
1517 * individually.
1518 */
1519
1520 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1521 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1522 * the 1000Base-T Control Register (Address 9).
1523 */
1524 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1525 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1526
1527 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);
1528
1529 /* Do we want to advertise 10 Mb Half Duplex? */
1530 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1531 e_dbg("Advertise 10mb Half duplex\n");
1532 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1533 }
1534
1535 /* Do we want to advertise 10 Mb Full Duplex? */
1536 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1537 e_dbg("Advertise 10mb Full duplex\n");
1538 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1539 }
1540
1541 /* Do we want to advertise 100 Mb Half Duplex? */
1542 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1543 e_dbg("Advertise 100mb Half duplex\n");
1544 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1545 }
1546
1547 /* Do we want to advertise 100 Mb Full Duplex? */
1548 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1549 e_dbg("Advertise 100mb Full duplex\n");
1550 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1551 }
1552
1553 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1554 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1555 e_dbg
1556 ("Advertise 1000mb Half duplex requested, request denied!\n");
1557 }
1558
1559 /* Do we want to advertise 1000 Mb Full Duplex? */
1560 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1561 e_dbg("Advertise 1000mb Full duplex\n");
1562 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1563 }
1564
1565 /* Check for a software override of the flow control settings, and
1566 * setup the PHY advertisement registers accordingly. If
1567 * auto-negotiation is enabled, then software will have to set the
1568 * "PAUSE" bits to the correct value in the Auto-Negotiation
1569 * Advertisement Register (PHY_AUTONEG_ADV) and re-start
1570 * auto-negotiation.
1571 *
1572 * The possible values of the "fc" parameter are:
1573 * 0: Flow control is completely disabled
1574 * 1: Rx flow control is enabled (we can receive pause frames
1575 * but not send pause frames).
1576 * 2: Tx flow control is enabled (we can send pause frames
1577 * but we do not support receiving pause frames).
1578 * 3: Both Rx and TX flow control (symmetric) are enabled.
1579 * other: No software override. The flow control configuration
1580 * in the EEPROM is used.
1581 */
1582 switch (hw->fc) {
1583 case E1000_FC_NONE: /* 0 */
1584 /* Flow control (RX & TX) is completely disabled by a
1585 * software over-ride.
1586 */
1587 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1588 break;
1589 case E1000_FC_RX_PAUSE: /* 1 */
1590 /* RX Flow control is enabled, and TX Flow control is
1591 * disabled, by a software over-ride.
1592 */
1593 /* Since there really isn't a way to advertise that we are
1594 * capable of RX Pause ONLY, we will advertise that we
1595 * support both symmetric and asymmetric RX PAUSE. Later
1596 * (in e1000_config_fc_after_link_up) we will disable the
1597 * hw's ability to send PAUSE frames.
1598 */
1599 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1600 break;
1601 case E1000_FC_TX_PAUSE: /* 2 */
1602 /* TX Flow control is enabled, and RX Flow control is
1603 * disabled, by a software over-ride.
1604 */
1605 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1606 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1607 break;
1608 case E1000_FC_FULL: /* 3 */
1609 /* Flow control (both RX and TX) is enabled by a software
1610 * over-ride.
1611 */
1612 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1613 break;
1614 default:
1615 e_dbg("Flow control param set incorrectly\n");
1616 return -E1000_ERR_CONFIG;
1617 }
1618
1619 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1620 if (ret_val)
1621 return ret_val;
1622
1623 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1624
1625 if (hw->phy_type == e1000_phy_8201) {
1626 mii_1000t_ctrl_reg = 0;
1627 } else {
1628 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1629 mii_1000t_ctrl_reg);
1630 if (ret_val)
1631 return ret_val;
1632 }
1633
1634 return E1000_SUCCESS;
1635 }
1636
1637 /**
1638 * e1000_phy_force_speed_duplex - force link settings
1639 * @hw: Struct containing variables accessed by shared code
1640 *
1641 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1642 */
1643 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1644 {
1645 u32 ctrl;
1646 s32 ret_val;
1647 u16 mii_ctrl_reg;
1648 u16 mii_status_reg;
1649 u16 phy_data;
1650 u16 i;
1651
1652 /* Turn off Flow control if we are forcing speed and duplex. */
1653 hw->fc = E1000_FC_NONE;
1654
1655 e_dbg("hw->fc = %d\n", hw->fc);
1656
1657 /* Read the Device Control Register. */
1658 ctrl = er32(CTRL);
1659
1660 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1661 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1662 ctrl &= ~(DEVICE_SPEED_MASK);
1663
1664 /* Clear the Auto Speed Detect Enable bit. */
1665 ctrl &= ~E1000_CTRL_ASDE;
1666
1667 /* Read the MII Control Register. */
1668 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1669 if (ret_val)
1670 return ret_val;
1671
1672 /* We need to disable autoneg in order to force link and duplex. */
1673
1674 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1675
1676 /* Are we forcing Full or Half Duplex? */
1677 if (hw->forced_speed_duplex == e1000_100_full ||
1678 hw->forced_speed_duplex == e1000_10_full) {
1679 /* We want to force full duplex so we SET the full duplex bits
1680 * in the Device and MII Control Registers.
1681 */
1682 ctrl |= E1000_CTRL_FD;
1683 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1684 e_dbg("Full Duplex\n");
1685 } else {
1686 /* We want to force half duplex so we CLEAR the full duplex bits
1687 * in the Device and MII Control Registers.
1688 */
1689 ctrl &= ~E1000_CTRL_FD;
1690 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1691 e_dbg("Half Duplex\n");
1692 }
1693
1694 /* Are we forcing 100Mbps??? */
1695 if (hw->forced_speed_duplex == e1000_100_full ||
1696 hw->forced_speed_duplex == e1000_100_half) {
1697 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1698 ctrl |= E1000_CTRL_SPD_100;
1699 mii_ctrl_reg |= MII_CR_SPEED_100;
1700 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1701 e_dbg("Forcing 100mb ");
1702 } else {
1703 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1704 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1705 mii_ctrl_reg |= MII_CR_SPEED_10;
1706 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1707 e_dbg("Forcing 10mb ");
1708 }
1709
1710 e1000_config_collision_dist(hw);
1711
1712 /* Write the configured values back to the Device Control Reg. */
1713 ew32(CTRL, ctrl);
1714
1715 if (hw->phy_type == e1000_phy_m88) {
1716 ret_val =
1717 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1718 if (ret_val)
1719 return ret_val;
1720
1721 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires
1722 * MDI forced whenever speed are duplex are forced.
1723 */
1724 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1725 ret_val =
1726 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1727 if (ret_val)
1728 return ret_val;
1729
1730 e_dbg("M88E1000 PSCR: %x\n", phy_data);
1731
1732 /* Need to reset the PHY or these changes will be ignored */
1733 mii_ctrl_reg |= MII_CR_RESET;
1734
1735 /* Disable MDI-X support for 10/100 */
1736 } else {
1737 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1738 * forced whenever speed or duplex are forced.
1739 */
1740 ret_val =
1741 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1742 if (ret_val)
1743 return ret_val;
1744
1745 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1746 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1747
1748 ret_val =
1749 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1750 if (ret_val)
1751 return ret_val;
1752 }
1753
1754 /* Write back the modified PHY MII control register. */
1755 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1756 if (ret_val)
1757 return ret_val;
1758
1759 udelay(1);
1760
1761 /* The wait_autoneg_complete flag may be a little misleading here.
1762 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1763 * But we do want to delay for a period while forcing only so we
1764 * don't generate false No Link messages. So we will wait here
1765 * only if the user has set wait_autoneg_complete to 1, which is
1766 * the default.
1767 */
1768 if (hw->wait_autoneg_complete) {
1769 /* We will wait for autoneg to complete. */
1770 e_dbg("Waiting for forced speed/duplex link.\n");
1771 mii_status_reg = 0;
1772
1773 /* Wait for autoneg to complete or 4.5 seconds to expire */
1774 for (i = PHY_FORCE_TIME; i > 0; i--) {
1775 /* Read the MII Status Register and wait for Auto-Neg
1776 * Complete bit to be set.
1777 */
1778 ret_val =
1779 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1780 if (ret_val)
1781 return ret_val;
1782
1783 ret_val =
1784 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1785 if (ret_val)
1786 return ret_val;
1787
1788 if (mii_status_reg & MII_SR_LINK_STATUS)
1789 break;
1790 msleep(100);
1791 }
1792 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1793 /* We didn't get link. Reset the DSP and wait again
1794 * for link.
1795 */
1796 ret_val = e1000_phy_reset_dsp(hw);
1797 if (ret_val) {
1798 e_dbg("Error Resetting PHY DSP\n");
1799 return ret_val;
1800 }
1801 }
1802 /* This loop will early-out if the link condition has been
1803 * met
1804 */
1805 for (i = PHY_FORCE_TIME; i > 0; i--) {
1806 if (mii_status_reg & MII_SR_LINK_STATUS)
1807 break;
1808 msleep(100);
1809 /* Read the MII Status Register and wait for Auto-Neg
1810 * Complete bit to be set.
1811 */
1812 ret_val =
1813 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1814 if (ret_val)
1815 return ret_val;
1816
1817 ret_val =
1818 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1819 if (ret_val)
1820 return ret_val;
1821 }
1822 }
1823
1824 if (hw->phy_type == e1000_phy_m88) {
1825 /* Because we reset the PHY above, we need to re-force TX_CLK in
1826 * the Extended PHY Specific Control Register to 25MHz clock.
1827 * This value defaults back to a 2.5MHz clock when the PHY is
1828 * reset.
1829 */
1830 ret_val =
1831 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1832 &phy_data);
1833 if (ret_val)
1834 return ret_val;
1835
1836 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1837 ret_val =
1838 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1839 phy_data);
1840 if (ret_val)
1841 return ret_val;
1842
1843 /* In addition, because of the s/w reset above, we need to
1844 * enable CRS on Tx. This must be set for both full and half
1845 * duplex operation.
1846 */
1847 ret_val =
1848 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1849 if (ret_val)
1850 return ret_val;
1851
1852 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1853 ret_val =
1854 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1855 if (ret_val)
1856 return ret_val;
1857
1858 if ((hw->mac_type == e1000_82544 ||
1859 hw->mac_type == e1000_82543) &&
1860 (!hw->autoneg) &&
1861 (hw->forced_speed_duplex == e1000_10_full ||
1862 hw->forced_speed_duplex == e1000_10_half)) {
1863 ret_val = e1000_polarity_reversal_workaround(hw);
1864 if (ret_val)
1865 return ret_val;
1866 }
1867 }
1868 return E1000_SUCCESS;
1869 }
1870
1871 /**
1872 * e1000_config_collision_dist - set collision distance register
1873 * @hw: Struct containing variables accessed by shared code
1874 *
1875 * Sets the collision distance in the Transmit Control register.
1876 * Link should have been established previously. Reads the speed and duplex
1877 * information from the Device Status register.
1878 */
1879 void e1000_config_collision_dist(struct e1000_hw *hw)
1880 {
1881 u32 tctl, coll_dist;
1882
1883 if (hw->mac_type < e1000_82543)
1884 coll_dist = E1000_COLLISION_DISTANCE_82542;
1885 else
1886 coll_dist = E1000_COLLISION_DISTANCE;
1887
1888 tctl = er32(TCTL);
1889
1890 tctl &= ~E1000_TCTL_COLD;
1891 tctl |= coll_dist << E1000_COLD_SHIFT;
1892
1893 ew32(TCTL, tctl);
1894 E1000_WRITE_FLUSH();
1895 }
1896
1897 /**
1898 * e1000_config_mac_to_phy - sync phy and mac settings
1899 * @hw: Struct containing variables accessed by shared code
1900 * @mii_reg: data to write to the MII control register
1901 *
1902 * Sets MAC speed and duplex settings to reflect the those in the PHY
1903 * The contents of the PHY register containing the needed information need to
1904 * be passed in.
1905 */
1906 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1907 {
1908 u32 ctrl;
1909 s32 ret_val;
1910 u16 phy_data;
1911
1912 /* 82544 or newer MAC, Auto Speed Detection takes care of
1913 * MAC speed/duplex configuration.
1914 */
1915 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
1916 return E1000_SUCCESS;
1917
1918 /* Read the Device Control Register and set the bits to Force Speed
1919 * and Duplex.
1920 */
1921 ctrl = er32(CTRL);
1922 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1923 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1924
1925 switch (hw->phy_type) {
1926 case e1000_phy_8201:
1927 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1928 if (ret_val)
1929 return ret_val;
1930
1931 if (phy_data & RTL_PHY_CTRL_FD)
1932 ctrl |= E1000_CTRL_FD;
1933 else
1934 ctrl &= ~E1000_CTRL_FD;
1935
1936 if (phy_data & RTL_PHY_CTRL_SPD_100)
1937 ctrl |= E1000_CTRL_SPD_100;
1938 else
1939 ctrl |= E1000_CTRL_SPD_10;
1940
1941 e1000_config_collision_dist(hw);
1942 break;
1943 default:
1944 /* Set up duplex in the Device Control and Transmit Control
1945 * registers depending on negotiated values.
1946 */
1947 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1948 &phy_data);
1949 if (ret_val)
1950 return ret_val;
1951
1952 if (phy_data & M88E1000_PSSR_DPLX)
1953 ctrl |= E1000_CTRL_FD;
1954 else
1955 ctrl &= ~E1000_CTRL_FD;
1956
1957 e1000_config_collision_dist(hw);
1958
1959 /* Set up speed in the Device Control register depending on
1960 * negotiated values.
1961 */
1962 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1963 ctrl |= E1000_CTRL_SPD_1000;
1964 else if ((phy_data & M88E1000_PSSR_SPEED) ==
1965 M88E1000_PSSR_100MBS)
1966 ctrl |= E1000_CTRL_SPD_100;
1967 }
1968
1969 /* Write the configured values back to the Device Control Reg. */
1970 ew32(CTRL, ctrl);
1971 return E1000_SUCCESS;
1972 }
1973
1974 /**
1975 * e1000_force_mac_fc - force flow control settings
1976 * @hw: Struct containing variables accessed by shared code
1977 *
1978 * Forces the MAC's flow control settings.
1979 * Sets the TFCE and RFCE bits in the device control register to reflect
1980 * the adapter settings. TFCE and RFCE need to be explicitly set by
1981 * software when a Copper PHY is used because autonegotiation is managed
1982 * by the PHY rather than the MAC. Software must also configure these
1983 * bits when link is forced on a fiber connection.
1984 */
1985 s32 e1000_force_mac_fc(struct e1000_hw *hw)
1986 {
1987 u32 ctrl;
1988
1989 /* Get the current configuration of the Device Control Register */
1990 ctrl = er32(CTRL);
1991
1992 /* Because we didn't get link via the internal auto-negotiation
1993 * mechanism (we either forced link or we got link via PHY
1994 * auto-neg), we have to manually enable/disable transmit an
1995 * receive flow control.
1996 *
1997 * The "Case" statement below enables/disable flow control
1998 * according to the "hw->fc" parameter.
1999 *
2000 * The possible values of the "fc" parameter are:
2001 * 0: Flow control is completely disabled
2002 * 1: Rx flow control is enabled (we can receive pause
2003 * frames but not send pause frames).
2004 * 2: Tx flow control is enabled (we can send pause frames
2005 * frames but we do not receive pause frames).
2006 * 3: Both Rx and TX flow control (symmetric) is enabled.
2007 * other: No other values should be possible at this point.
2008 */
2009
2010 switch (hw->fc) {
2011 case E1000_FC_NONE:
2012 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2013 break;
2014 case E1000_FC_RX_PAUSE:
2015 ctrl &= (~E1000_CTRL_TFCE);
2016 ctrl |= E1000_CTRL_RFCE;
2017 break;
2018 case E1000_FC_TX_PAUSE:
2019 ctrl &= (~E1000_CTRL_RFCE);
2020 ctrl |= E1000_CTRL_TFCE;
2021 break;
2022 case E1000_FC_FULL:
2023 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2024 break;
2025 default:
2026 e_dbg("Flow control param set incorrectly\n");
2027 return -E1000_ERR_CONFIG;
2028 }
2029
2030 /* Disable TX Flow Control for 82542 (rev 2.0) */
2031 if (hw->mac_type == e1000_82542_rev2_0)
2032 ctrl &= (~E1000_CTRL_TFCE);
2033
2034 ew32(CTRL, ctrl);
2035 return E1000_SUCCESS;
2036 }
2037
2038 /**
2039 * e1000_config_fc_after_link_up - configure flow control after autoneg
2040 * @hw: Struct containing variables accessed by shared code
2041 *
2042 * Configures flow control settings after link is established
2043 * Should be called immediately after a valid link has been established.
2044 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2045 * and autonegotiation is enabled, the MAC flow control settings will be set
2046 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2047 * and RFCE bits will be automatically set to the negotiated flow control mode.
2048 */
2049 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2050 {
2051 s32 ret_val;
2052 u16 mii_status_reg;
2053 u16 mii_nway_adv_reg;
2054 u16 mii_nway_lp_ability_reg;
2055 u16 speed;
2056 u16 duplex;
2057
2058 /* Check for the case where we have fiber media and auto-neg failed
2059 * so we had to force link. In this case, we need to force the
2060 * configuration of the MAC to match the "fc" parameter.
2061 */
2062 if (((hw->media_type == e1000_media_type_fiber) &&
2063 (hw->autoneg_failed)) ||
2064 ((hw->media_type == e1000_media_type_internal_serdes) &&
2065 (hw->autoneg_failed)) ||
2066 ((hw->media_type == e1000_media_type_copper) &&
2067 (!hw->autoneg))) {
2068 ret_val = e1000_force_mac_fc(hw);
2069 if (ret_val) {
2070 e_dbg("Error forcing flow control settings\n");
2071 return ret_val;
2072 }
2073 }
2074
2075 /* Check for the case where we have copper media and auto-neg is
2076 * enabled. In this case, we need to check and see if Auto-Neg
2077 * has completed, and if so, how the PHY and link partner has
2078 * flow control configured.
2079 */
2080 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2081 /* Read the MII Status Register and check to see if AutoNeg
2082 * has completed. We read this twice because this reg has
2083 * some "sticky" (latched) bits.
2084 */
2085 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2086 if (ret_val)
2087 return ret_val;
2088 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2089 if (ret_val)
2090 return ret_val;
2091
2092 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2093 /* The AutoNeg process has completed, so we now need to
2094 * read both the Auto Negotiation Advertisement Register
2095 * (Address 4) and the Auto_Negotiation Base Page
2096 * Ability Register (Address 5) to determine how flow
2097 * control was negotiated.
2098 */
2099 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2100 &mii_nway_adv_reg);
2101 if (ret_val)
2102 return ret_val;
2103 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2104 &mii_nway_lp_ability_reg);
2105 if (ret_val)
2106 return ret_val;
2107
2108 /* Two bits in the Auto Negotiation Advertisement
2109 * Register (Address 4) and two bits in the Auto
2110 * Negotiation Base Page Ability Register (Address 5)
2111 * determine flow control for both the PHY and the link
2112 * partner. The following table, taken out of the IEEE
2113 * 802.3ab/D6.0 dated March 25, 1999, describes these
2114 * PAUSE resolution bits and how flow control is
2115 * determined based upon these settings.
2116 * NOTE: DC = Don't Care
2117 *
2118 * LOCAL DEVICE | LINK PARTNER
2119 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2120 *-------|---------|-------|---------|------------------
2121 * 0 | 0 | DC | DC | E1000_FC_NONE
2122 * 0 | 1 | 0 | DC | E1000_FC_NONE
2123 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2124 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2125 * 1 | 0 | 0 | DC | E1000_FC_NONE
2126 * 1 | DC | 1 | DC | E1000_FC_FULL
2127 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2128 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2129 *
2130 */
2131 /* Are both PAUSE bits set to 1? If so, this implies
2132 * Symmetric Flow Control is enabled at both ends. The
2133 * ASM_DIR bits are irrelevant per the spec.
2134 *
2135 * For Symmetric Flow Control:
2136 *
2137 * LOCAL DEVICE | LINK PARTNER
2138 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2139 *-------|---------|-------|---------|------------------
2140 * 1 | DC | 1 | DC | E1000_FC_FULL
2141 *
2142 */
2143 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2144 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2145 /* Now we need to check if the user selected Rx
2146 * ONLY of pause frames. In this case, we had
2147 * to advertise FULL flow control because we
2148 * could not advertise Rx ONLY. Hence, we must
2149 * now check to see if we need to turn OFF the
2150 * TRANSMISSION of PAUSE frames.
2151 */
2152 if (hw->original_fc == E1000_FC_FULL) {
2153 hw->fc = E1000_FC_FULL;
2154 e_dbg("Flow Control = FULL.\n");
2155 } else {
2156 hw->fc = E1000_FC_RX_PAUSE;
2157 e_dbg
2158 ("Flow Control = RX PAUSE frames only.\n");
2159 }
2160 }
2161 /* For receiving PAUSE frames ONLY.
2162 *
2163 * LOCAL DEVICE | LINK PARTNER
2164 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2165 *-------|---------|-------|---------|------------------
2166 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2167 *
2168 */
2169 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2170 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2171 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2172 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2173 hw->fc = E1000_FC_TX_PAUSE;
2174 e_dbg
2175 ("Flow Control = TX PAUSE frames only.\n");
2176 }
2177 /* For transmitting PAUSE frames ONLY.
2178 *
2179 * LOCAL DEVICE | LINK PARTNER
2180 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2181 *-------|---------|-------|---------|------------------
2182 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2183 *
2184 */
2185 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2186 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2187 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2188 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2189 hw->fc = E1000_FC_RX_PAUSE;
2190 e_dbg
2191 ("Flow Control = RX PAUSE frames only.\n");
2192 }
2193 /* Per the IEEE spec, at this point flow control should
2194 * be disabled. However, we want to consider that we
2195 * could be connected to a legacy switch that doesn't
2196 * advertise desired flow control, but can be forced on
2197 * the link partner. So if we advertised no flow
2198 * control, that is what we will resolve to. If we
2199 * advertised some kind of receive capability (Rx Pause
2200 * Only or Full Flow Control) and the link partner
2201 * advertised none, we will configure ourselves to
2202 * enable Rx Flow Control only. We can do this safely
2203 * for two reasons: If the link partner really
2204 * didn't want flow control enabled, and we enable Rx,
2205 * no harm done since we won't be receiving any PAUSE
2206 * frames anyway. If the intent on the link partner was
2207 * to have flow control enabled, then by us enabling Rx
2208 * only, we can at least receive pause frames and
2209 * process them. This is a good idea because in most
2210 * cases, since we are predominantly a server NIC, more
2211 * times than not we will be asked to delay transmission
2212 * of packets than asking our link partner to pause
2213 * transmission of frames.
2214 */
2215 else if ((hw->original_fc == E1000_FC_NONE ||
2216 hw->original_fc == E1000_FC_TX_PAUSE) ||
2217 hw->fc_strict_ieee) {
2218 hw->fc = E1000_FC_NONE;
2219 e_dbg("Flow Control = NONE.\n");
2220 } else {
2221 hw->fc = E1000_FC_RX_PAUSE;
2222 e_dbg
2223 ("Flow Control = RX PAUSE frames only.\n");
2224 }
2225
2226 /* Now we need to do one last check... If we auto-
2227 * negotiated to HALF DUPLEX, flow control should not be
2228 * enabled per IEEE 802.3 spec.
2229 */
2230 ret_val =
2231 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2232 if (ret_val) {
2233 e_dbg
2234 ("Error getting link speed and duplex\n");
2235 return ret_val;
2236 }
2237
2238 if (duplex == HALF_DUPLEX)
2239 hw->fc = E1000_FC_NONE;
2240
2241 /* Now we call a subroutine to actually force the MAC
2242 * controller to use the correct flow control settings.
2243 */
2244 ret_val = e1000_force_mac_fc(hw);
2245 if (ret_val) {
2246 e_dbg
2247 ("Error forcing flow control settings\n");
2248 return ret_val;
2249 }
2250 } else {
2251 e_dbg
2252 ("Copper PHY and Auto Neg has not completed.\n");
2253 }
2254 }
2255 return E1000_SUCCESS;
2256 }
2257
2258 /**
2259 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
2260 * @hw: pointer to the HW structure
2261 *
2262 * Checks for link up on the hardware. If link is not up and we have
2263 * a signal, then we need to force link up.
2264 */
2265 static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2266 {
2267 u32 rxcw;
2268 u32 ctrl;
2269 u32 status;
2270 s32 ret_val = E1000_SUCCESS;
2271
2272 ctrl = er32(CTRL);
2273 status = er32(STATUS);
2274 rxcw = er32(RXCW);
2275
2276 /* If we don't have link (auto-negotiation failed or link partner
2277 * cannot auto-negotiate), and our link partner is not trying to
2278 * auto-negotiate with us (we are receiving idles or data),
2279 * we need to force link up. We also need to give auto-negotiation
2280 * time to complete.
2281 */
2282 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
2283 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2284 if (hw->autoneg_failed == 0) {
2285 hw->autoneg_failed = 1;
2286 goto out;
2287 }
2288 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
2289
2290 /* Disable auto-negotiation in the TXCW register */
2291 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2292
2293 /* Force link-up and also force full-duplex. */
2294 ctrl = er32(CTRL);
2295 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2296 ew32(CTRL, ctrl);
2297
2298 /* Configure Flow Control after forcing link up. */
2299 ret_val = e1000_config_fc_after_link_up(hw);
2300 if (ret_val) {
2301 e_dbg("Error configuring flow control\n");
2302 goto out;
2303 }
2304 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2305 /* If we are forcing link and we are receiving /C/ ordered
2306 * sets, re-enable auto-negotiation in the TXCW register
2307 * and disable forced link in the Device Control register
2308 * in an attempt to auto-negotiate with our link partner.
2309 */
2310 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
2311 ew32(TXCW, hw->txcw);
2312 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2313
2314 hw->serdes_has_link = true;
2315 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2316 /* If we force link for non-auto-negotiation switch, check
2317 * link status based on MAC synchronization for internal
2318 * serdes media type.
2319 */
2320 /* SYNCH bit and IV bit are sticky. */
2321 udelay(10);
2322 rxcw = er32(RXCW);
2323 if (rxcw & E1000_RXCW_SYNCH) {
2324 if (!(rxcw & E1000_RXCW_IV)) {
2325 hw->serdes_has_link = true;
2326 e_dbg("SERDES: Link up - forced.\n");
2327 }
2328 } else {
2329 hw->serdes_has_link = false;
2330 e_dbg("SERDES: Link down - force failed.\n");
2331 }
2332 }
2333
2334 if (E1000_TXCW_ANE & er32(TXCW)) {
2335 status = er32(STATUS);
2336 if (status & E1000_STATUS_LU) {
2337 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
2338 udelay(10);
2339 rxcw = er32(RXCW);
2340 if (rxcw & E1000_RXCW_SYNCH) {
2341 if (!(rxcw & E1000_RXCW_IV)) {
2342 hw->serdes_has_link = true;
2343 e_dbg("SERDES: Link up - autoneg "
2344 "completed successfully.\n");
2345 } else {
2346 hw->serdes_has_link = false;
2347 e_dbg("SERDES: Link down - invalid"
2348 "codewords detected in autoneg.\n");
2349 }
2350 } else {
2351 hw->serdes_has_link = false;
2352 e_dbg("SERDES: Link down - no sync.\n");
2353 }
2354 } else {
2355 hw->serdes_has_link = false;
2356 e_dbg("SERDES: Link down - autoneg failed\n");
2357 }
2358 }
2359
2360 out:
2361 return ret_val;
2362 }
2363
2364 /**
2365 * e1000_check_for_link
2366 * @hw: Struct containing variables accessed by shared code
2367 *
2368 * Checks to see if the link status of the hardware has changed.
2369 * Called by any function that needs to check the link status of the adapter.
2370 */
2371 s32 e1000_check_for_link(struct e1000_hw *hw)
2372 {
2373 u32 rxcw = 0;
2374 u32 ctrl;
2375 u32 status;
2376 u32 rctl;
2377 u32 icr;
2378 u32 signal = 0;
2379 s32 ret_val;
2380 u16 phy_data;
2381
2382 ctrl = er32(CTRL);
2383 status = er32(STATUS);
2384
2385 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
2386 * set when the optics detect a signal. On older adapters, it will be
2387 * cleared when there is a signal. This applies to fiber media only.
2388 */
2389 if ((hw->media_type == e1000_media_type_fiber) ||
2390 (hw->media_type == e1000_media_type_internal_serdes)) {
2391 rxcw = er32(RXCW);
2392
2393 if (hw->media_type == e1000_media_type_fiber) {
2394 signal =
2395 (hw->mac_type >
2396 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2397 if (status & E1000_STATUS_LU)
2398 hw->get_link_status = false;
2399 }
2400 }
2401
2402 /* If we have a copper PHY then we only want to go out to the PHY
2403 * registers to see if Auto-Neg has completed and/or if our link
2404 * status has changed. The get_link_status flag will be set if we
2405 * receive a Link Status Change interrupt or we have Rx Sequence
2406 * Errors.
2407 */
2408 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2409 /* First we want to see if the MII Status Register reports
2410 * link. If so, then we want to get the current speed/duplex
2411 * of the PHY.
2412 * Read the register twice since the link bit is sticky.
2413 */
2414 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2415 if (ret_val)
2416 return ret_val;
2417 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2418 if (ret_val)
2419 return ret_val;
2420
2421 if (phy_data & MII_SR_LINK_STATUS) {
2422 hw->get_link_status = false;
2423 /* Check if there was DownShift, must be checked
2424 * immediately after link-up
2425 */
2426 e1000_check_downshift(hw);
2427
2428 /* If we are on 82544 or 82543 silicon and speed/duplex
2429 * are forced to 10H or 10F, then we will implement the
2430 * polarity reversal workaround. We disable interrupts
2431 * first, and upon returning, place the devices
2432 * interrupt state to its previous value except for the
2433 * link status change interrupt which will
2434 * happen due to the execution of this workaround.
2435 */
2436
2437 if ((hw->mac_type == e1000_82544 ||
2438 hw->mac_type == e1000_82543) &&
2439 (!hw->autoneg) &&
2440 (hw->forced_speed_duplex == e1000_10_full ||
2441 hw->forced_speed_duplex == e1000_10_half)) {
2442 ew32(IMC, 0xffffffff);
2443 ret_val =
2444 e1000_polarity_reversal_workaround(hw);
2445 icr = er32(ICR);
2446 ew32(ICS, (icr & ~E1000_ICS_LSC));
2447 ew32(IMS, IMS_ENABLE_MASK);
2448 }
2449
2450 } else {
2451 /* No link detected */
2452 e1000_config_dsp_after_link_change(hw, false);
2453 return 0;
2454 }
2455
2456 /* If we are forcing speed/duplex, then we simply return since
2457 * we have already determined whether we have link or not.
2458 */
2459 if (!hw->autoneg)
2460 return -E1000_ERR_CONFIG;
2461
2462 /* optimize the dsp settings for the igp phy */
2463 e1000_config_dsp_after_link_change(hw, true);
2464
2465 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2466 * have Si on board that is 82544 or newer, Auto
2467 * Speed Detection takes care of MAC speed/duplex
2468 * configuration. So we only need to configure Collision
2469 * Distance in the MAC. Otherwise, we need to force
2470 * speed/duplex on the MAC to the current PHY speed/duplex
2471 * settings.
2472 */
2473 if ((hw->mac_type >= e1000_82544) &&
2474 (hw->mac_type != e1000_ce4100))
2475 e1000_config_collision_dist(hw);
2476 else {
2477 ret_val = e1000_config_mac_to_phy(hw);
2478 if (ret_val) {
2479 e_dbg
2480 ("Error configuring MAC to PHY settings\n");
2481 return ret_val;
2482 }
2483 }
2484
2485 /* Configure Flow Control now that Auto-Neg has completed.
2486 * First, we need to restore the desired flow control settings
2487 * because we may have had to re-autoneg with a different link
2488 * partner.
2489 */
2490 ret_val = e1000_config_fc_after_link_up(hw);
2491 if (ret_val) {
2492 e_dbg("Error configuring flow control\n");
2493 return ret_val;
2494 }
2495
2496 /* At this point we know that we are on copper and we have
2497 * auto-negotiated link. These are conditions for checking the
2498 * link partner capability register. We use the link speed to
2499 * determine if TBI compatibility needs to be turned on or off.
2500 * If the link is not at gigabit speed, then TBI compatibility
2501 * is not needed. If we are at gigabit speed, we turn on TBI
2502 * compatibility.
2503 */
2504 if (hw->tbi_compatibility_en) {
2505 u16 speed, duplex;
2506
2507 ret_val =
2508 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2509
2510 if (ret_val) {
2511 e_dbg
2512 ("Error getting link speed and duplex\n");
2513 return ret_val;
2514 }
2515 if (speed != SPEED_1000) {
2516 /* If link speed is not set to gigabit speed, we
2517 * do not need to enable TBI compatibility.
2518 */
2519 if (hw->tbi_compatibility_on) {
2520 /* If we previously were in the mode,
2521 * turn it off.
2522 */
2523 rctl = er32(RCTL);
2524 rctl &= ~E1000_RCTL_SBP;
2525 ew32(RCTL, rctl);
2526 hw->tbi_compatibility_on = false;
2527 }
2528 } else {
2529 /* If TBI compatibility is was previously off,
2530 * turn it on. For compatibility with a TBI link
2531 * partner, we will store bad packets. Some
2532 * frames have an additional byte on the end and
2533 * will look like CRC errors to to the hardware.
2534 */
2535 if (!hw->tbi_compatibility_on) {
2536 hw->tbi_compatibility_on = true;
2537 rctl = er32(RCTL);
2538 rctl |= E1000_RCTL_SBP;
2539 ew32(RCTL, rctl);
2540 }
2541 }
2542 }
2543 }
2544
2545 if ((hw->media_type == e1000_media_type_fiber) ||
2546 (hw->media_type == e1000_media_type_internal_serdes))
2547 e1000_check_for_serdes_link_generic(hw);
2548
2549 return E1000_SUCCESS;
2550 }
2551
2552 /**
2553 * e1000_get_speed_and_duplex
2554 * @hw: Struct containing variables accessed by shared code
2555 * @speed: Speed of the connection
2556 * @duplex: Duplex setting of the connection
2557 *
2558 * Detects the current speed and duplex settings of the hardware.
2559 */
2560 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2561 {
2562 u32 status;
2563 s32 ret_val;
2564 u16 phy_data;
2565
2566 if (hw->mac_type >= e1000_82543) {
2567 status = er32(STATUS);
2568 if (status & E1000_STATUS_SPEED_1000) {
2569 *speed = SPEED_1000;
2570 e_dbg("1000 Mbs, ");
2571 } else if (status & E1000_STATUS_SPEED_100) {
2572 *speed = SPEED_100;
2573 e_dbg("100 Mbs, ");
2574 } else {
2575 *speed = SPEED_10;
2576 e_dbg("10 Mbs, ");
2577 }
2578
2579 if (status & E1000_STATUS_FD) {
2580 *duplex = FULL_DUPLEX;
2581 e_dbg("Full Duplex\n");
2582 } else {
2583 *duplex = HALF_DUPLEX;
2584 e_dbg(" Half Duplex\n");
2585 }
2586 } else {
2587 e_dbg("1000 Mbs, Full Duplex\n");
2588 *speed = SPEED_1000;
2589 *duplex = FULL_DUPLEX;
2590 }
2591
2592 /* IGP01 PHY may advertise full duplex operation after speed downgrade
2593 * even if it is operating at half duplex. Here we set the duplex
2594 * settings to match the duplex in the link partner's capabilities.
2595 */
2596 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2597 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2598 if (ret_val)
2599 return ret_val;
2600
2601 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2602 *duplex = HALF_DUPLEX;
2603 else {
2604 ret_val =
2605 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2606 if (ret_val)
2607 return ret_val;
2608 if ((*speed == SPEED_100 &&
2609 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2610 (*speed == SPEED_10 &&
2611 !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2612 *duplex = HALF_DUPLEX;
2613 }
2614 }
2615
2616 return E1000_SUCCESS;
2617 }
2618
2619 /**
2620 * e1000_wait_autoneg
2621 * @hw: Struct containing variables accessed by shared code
2622 *
2623 * Blocks until autoneg completes or times out (~4.5 seconds)
2624 */
2625 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2626 {
2627 s32 ret_val;
2628 u16 i;
2629 u16 phy_data;
2630
2631 e_dbg("Waiting for Auto-Neg to complete.\n");
2632
2633 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2634 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2635 /* Read the MII Status Register and wait for Auto-Neg
2636 * Complete bit to be set.
2637 */
2638 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2639 if (ret_val)
2640 return ret_val;
2641 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2642 if (ret_val)
2643 return ret_val;
2644 if (phy_data & MII_SR_AUTONEG_COMPLETE)
2645 return E1000_SUCCESS;
2646
2647 msleep(100);
2648 }
2649 return E1000_SUCCESS;
2650 }
2651
2652 /**
2653 * e1000_raise_mdi_clk - Raises the Management Data Clock
2654 * @hw: Struct containing variables accessed by shared code
2655 * @ctrl: Device control register's current value
2656 */
2657 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2658 {
2659 /* Raise the clock input to the Management Data Clock (by setting the
2660 * MDC bit), and then delay 10 microseconds.
2661 */
2662 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2663 E1000_WRITE_FLUSH();
2664 udelay(10);
2665 }
2666
2667 /**
2668 * e1000_lower_mdi_clk - Lowers the Management Data Clock
2669 * @hw: Struct containing variables accessed by shared code
2670 * @ctrl: Device control register's current value
2671 */
2672 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2673 {
2674 /* Lower the clock input to the Management Data Clock (by clearing the
2675 * MDC bit), and then delay 10 microseconds.
2676 */
2677 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2678 E1000_WRITE_FLUSH();
2679 udelay(10);
2680 }
2681
2682 /**
2683 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
2684 * @hw: Struct containing variables accessed by shared code
2685 * @data: Data to send out to the PHY
2686 * @count: Number of bits to shift out
2687 *
2688 * Bits are shifted out in MSB to LSB order.
2689 */
2690 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
2691 {
2692 u32 ctrl;
2693 u32 mask;
2694
2695 /* We need to shift "count" number of bits out to the PHY. So, the value
2696 * in the "data" parameter will be shifted out to the PHY one bit at a
2697 * time. In order to do this, "data" must be broken down into bits.
2698 */
2699 mask = 0x01;
2700 mask <<= (count - 1);
2701
2702 ctrl = er32(CTRL);
2703
2704 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2705 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2706
2707 while (mask) {
2708 /* A "1" is shifted out to the PHY by setting the MDIO bit to
2709 * "1" and then raising and lowering the Management Data Clock.
2710 * A "0" is shifted out to the PHY by setting the MDIO bit to
2711 * "0" and then raising and lowering the clock.
2712 */
2713 if (data & mask)
2714 ctrl |= E1000_CTRL_MDIO;
2715 else
2716 ctrl &= ~E1000_CTRL_MDIO;
2717
2718 ew32(CTRL, ctrl);
2719 E1000_WRITE_FLUSH();
2720
2721 udelay(10);
2722
2723 e1000_raise_mdi_clk(hw, &ctrl);
2724 e1000_lower_mdi_clk(hw, &ctrl);
2725
2726 mask = mask >> 1;
2727 }
2728 }
2729
2730 /**
2731 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
2732 * @hw: Struct containing variables accessed by shared code
2733 *
2734 * Bits are shifted in in MSB to LSB order.
2735 */
2736 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2737 {
2738 u32 ctrl;
2739 u16 data = 0;
2740 u8 i;
2741
2742 /* In order to read a register from the PHY, we need to shift in a total
2743 * of 18 bits from the PHY. The first two bit (turnaround) times are
2744 * used to avoid contention on the MDIO pin when a read operation is
2745 * performed. These two bits are ignored by us and thrown away. Bits are
2746 * "shifted in" by raising the input to the Management Data Clock
2747 * (setting the MDC bit), and then reading the value of the MDIO bit.
2748 */
2749 ctrl = er32(CTRL);
2750
2751 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
2752 * input.
2753 */
2754 ctrl &= ~E1000_CTRL_MDIO_DIR;
2755 ctrl &= ~E1000_CTRL_MDIO;
2756
2757 ew32(CTRL, ctrl);
2758 E1000_WRITE_FLUSH();
2759
2760 /* Raise and Lower the clock before reading in the data. This accounts
2761 * for the turnaround bits. The first clock occurred when we clocked out
2762 * the last bit of the Register Address.
2763 */
2764 e1000_raise_mdi_clk(hw, &ctrl);
2765 e1000_lower_mdi_clk(hw, &ctrl);
2766
2767 for (data = 0, i = 0; i < 16; i++) {
2768 data = data << 1;
2769 e1000_raise_mdi_clk(hw, &ctrl);
2770 ctrl = er32(CTRL);
2771 /* Check to see if we shifted in a "1". */
2772 if (ctrl & E1000_CTRL_MDIO)
2773 data |= 1;
2774 e1000_lower_mdi_clk(hw, &ctrl);
2775 }
2776
2777 e1000_raise_mdi_clk(hw, &ctrl);
2778 e1000_lower_mdi_clk(hw, &ctrl);
2779
2780 return data;
2781 }
2782
2783 /**
2784 * e1000_read_phy_reg - read a phy register
2785 * @hw: Struct containing variables accessed by shared code
2786 * @reg_addr: address of the PHY register to read
2787 * @phy_data: pointer to the value on the PHY register
2788 *
2789 * Reads the value from a PHY register, if the value is on a specific non zero
2790 * page, sets the page first.
2791 */
2792 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2793 {
2794 u32 ret_val;
2795 unsigned long flags;
2796
2797 spin_lock_irqsave(&e1000_phy_lock, flags);
2798
2799 if ((hw->phy_type == e1000_phy_igp) &&
2800 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2801 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2802 (u16) reg_addr);
2803 if (ret_val)
2804 goto out;
2805 }
2806
2807 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2808 phy_data);
2809 out:
2810 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2811
2812 return ret_val;
2813 }
2814
2815 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2816 u16 *phy_data)
2817 {
2818 u32 i;
2819 u32 mdic = 0;
2820 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2821
2822 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2823 e_dbg("PHY Address %d is out of range\n", reg_addr);
2824 return -E1000_ERR_PARAM;
2825 }
2826
2827 if (hw->mac_type > e1000_82543) {
2828 /* Set up Op-code, Phy Address, and register address in the MDI
2829 * Control register. The MAC will take care of interfacing with
2830 * the PHY to retrieve the desired data.
2831 */
2832 if (hw->mac_type == e1000_ce4100) {
2833 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2834 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2835 (INTEL_CE_GBE_MDIC_OP_READ) |
2836 (INTEL_CE_GBE_MDIC_GO));
2837
2838 writel(mdic, E1000_MDIO_CMD);
2839
2840 /* Poll the ready bit to see if the MDI read
2841 * completed
2842 */
2843 for (i = 0; i < 64; i++) {
2844 udelay(50);
2845 mdic = readl(E1000_MDIO_CMD);
2846 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2847 break;
2848 }
2849
2850 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2851 e_dbg("MDI Read did not complete\n");
2852 return -E1000_ERR_PHY;
2853 }
2854
2855 mdic = readl(E1000_MDIO_STS);
2856 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
2857 e_dbg("MDI Read Error\n");
2858 return -E1000_ERR_PHY;
2859 }
2860 *phy_data = (u16)mdic;
2861 } else {
2862 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2863 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2864 (E1000_MDIC_OP_READ));
2865
2866 ew32(MDIC, mdic);
2867
2868 /* Poll the ready bit to see if the MDI read
2869 * completed
2870 */
2871 for (i = 0; i < 64; i++) {
2872 udelay(50);
2873 mdic = er32(MDIC);
2874 if (mdic & E1000_MDIC_READY)
2875 break;
2876 }
2877 if (!(mdic & E1000_MDIC_READY)) {
2878 e_dbg("MDI Read did not complete\n");
2879 return -E1000_ERR_PHY;
2880 }
2881 if (mdic & E1000_MDIC_ERROR) {
2882 e_dbg("MDI Error\n");
2883 return -E1000_ERR_PHY;
2884 }
2885 *phy_data = (u16)mdic;
2886 }
2887 } else {
2888 /* We must first send a preamble through the MDIO pin to signal
2889 * the beginning of an MII instruction. This is done by sending
2890 * 32 consecutive "1" bits.
2891 */
2892 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2893
2894 /* Now combine the next few fields that are required for a read
2895 * operation. We use this method instead of calling the
2896 * e1000_shift_out_mdi_bits routine five different times. The
2897 * format of a MII read instruction consists of a shift out of
2898 * 14 bits and is defined as follows:
2899 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2900 * followed by a shift in of 18 bits. This first two bits
2901 * shifted in are TurnAround bits used to avoid contention on
2902 * the MDIO pin when a READ operation is performed. These two
2903 * bits are thrown away followed by a shift in of 16 bits which
2904 * contains the desired data.
2905 */
2906 mdic = ((reg_addr) | (phy_addr << 5) |
2907 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2908
2909 e1000_shift_out_mdi_bits(hw, mdic, 14);
2910
2911 /* Now that we've shifted out the read command to the MII, we
2912 * need to "shift in" the 16-bit value (18 total bits) of the
2913 * requested PHY register address.
2914 */
2915 *phy_data = e1000_shift_in_mdi_bits(hw);
2916 }
2917 return E1000_SUCCESS;
2918 }
2919
2920 /**
2921 * e1000_write_phy_reg - write a phy register
2922 *
2923 * @hw: Struct containing variables accessed by shared code
2924 * @reg_addr: address of the PHY register to write
2925 * @data: data to write to the PHY
2926 *
2927 * Writes a value to a PHY register
2928 */
2929 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2930 {
2931 u32 ret_val;
2932 unsigned long flags;
2933
2934 spin_lock_irqsave(&e1000_phy_lock, flags);
2935
2936 if ((hw->phy_type == e1000_phy_igp) &&
2937 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2938 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2939 (u16)reg_addr);
2940 if (ret_val) {
2941 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2942 return ret_val;
2943 }
2944 }
2945
2946 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2947 phy_data);
2948 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2949
2950 return ret_val;
2951 }
2952
2953 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2954 u16 phy_data)
2955 {
2956 u32 i;
2957 u32 mdic = 0;
2958 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2959
2960 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2961 e_dbg("PHY Address %d is out of range\n", reg_addr);
2962 return -E1000_ERR_PARAM;
2963 }
2964
2965 if (hw->mac_type > e1000_82543) {
2966 /* Set up Op-code, Phy Address, register address, and data
2967 * intended for the PHY register in the MDI Control register.
2968 * The MAC will take care of interfacing with the PHY to send
2969 * the desired data.
2970 */
2971 if (hw->mac_type == e1000_ce4100) {
2972 mdic = (((u32)phy_data) |
2973 (reg_addr << E1000_MDIC_REG_SHIFT) |
2974 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2975 (INTEL_CE_GBE_MDIC_OP_WRITE) |
2976 (INTEL_CE_GBE_MDIC_GO));
2977
2978 writel(mdic, E1000_MDIO_CMD);
2979
2980 /* Poll the ready bit to see if the MDI read
2981 * completed
2982 */
2983 for (i = 0; i < 640; i++) {
2984 udelay(5);
2985 mdic = readl(E1000_MDIO_CMD);
2986 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2987 break;
2988 }
2989 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2990 e_dbg("MDI Write did not complete\n");
2991 return -E1000_ERR_PHY;
2992 }
2993 } else {
2994 mdic = (((u32)phy_data) |
2995 (reg_addr << E1000_MDIC_REG_SHIFT) |
2996 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2997 (E1000_MDIC_OP_WRITE));
2998
2999 ew32(MDIC, mdic);
3000
3001 /* Poll the ready bit to see if the MDI read
3002 * completed
3003 */
3004 for (i = 0; i < 641; i++) {
3005 udelay(5);
3006 mdic = er32(MDIC);
3007 if (mdic & E1000_MDIC_READY)
3008 break;
3009 }
3010 if (!(mdic & E1000_MDIC_READY)) {
3011 e_dbg("MDI Write did not complete\n");
3012 return -E1000_ERR_PHY;
3013 }
3014 }
3015 } else {
3016 /* We'll need to use the SW defined pins to shift the write
3017 * command out to the PHY. We first send a preamble to the PHY
3018 * to signal the beginning of the MII instruction. This is done
3019 * by sending 32 consecutive "1" bits.
3020 */
3021 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3022
3023 /* Now combine the remaining required fields that will indicate
3024 * a write operation. We use this method instead of calling the
3025 * e1000_shift_out_mdi_bits routine for each field in the
3026 * command. The format of a MII write instruction is as follows:
3027 * <Preamble><SOF><OpCode><PhyAddr><RegAddr><Turnaround><Data>.
3028 */
3029 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3030 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3031 mdic <<= 16;
3032 mdic |= (u32)phy_data;
3033
3034 e1000_shift_out_mdi_bits(hw, mdic, 32);
3035 }
3036
3037 return E1000_SUCCESS;
3038 }
3039
3040 /**
3041 * e1000_phy_hw_reset - reset the phy, hardware style
3042 * @hw: Struct containing variables accessed by shared code
3043 *
3044 * Returns the PHY to the power-on reset state
3045 */
3046 s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3047 {
3048 u32 ctrl, ctrl_ext;
3049 u32 led_ctrl;
3050
3051 e_dbg("Resetting Phy...\n");
3052
3053 if (hw->mac_type > e1000_82543) {
3054 /* Read the device control register and assert the
3055 * E1000_CTRL_PHY_RST bit. Then, take it out of reset.
3056 * For e1000 hardware, we delay for 10ms between the assert
3057 * and de-assert.
3058 */
3059 ctrl = er32(CTRL);
3060 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3061 E1000_WRITE_FLUSH();
3062
3063 msleep(10);
3064
3065 ew32(CTRL, ctrl);
3066 E1000_WRITE_FLUSH();
3067
3068 } else {
3069 /* Read the Extended Device Control Register, assert the
3070 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it
3071 * out of reset.
3072 */
3073 ctrl_ext = er32(CTRL_EXT);
3074 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3075 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3076 ew32(CTRL_EXT, ctrl_ext);
3077 E1000_WRITE_FLUSH();
3078 msleep(10);
3079 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3080 ew32(CTRL_EXT, ctrl_ext);
3081 E1000_WRITE_FLUSH();
3082 }
3083 udelay(150);
3084
3085 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3086 /* Configure activity LED after PHY reset */
3087 led_ctrl = er32(LEDCTL);
3088 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3089 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3090 ew32(LEDCTL, led_ctrl);
3091 }
3092
3093 /* Wait for FW to finish PHY configuration. */
3094 return e1000_get_phy_cfg_done(hw);
3095 }
3096
3097 /**
3098 * e1000_phy_reset - reset the phy to commit settings
3099 * @hw: Struct containing variables accessed by shared code
3100 *
3101 * Resets the PHY
3102 * Sets bit 15 of the MII Control register
3103 */
3104 s32 e1000_phy_reset(struct e1000_hw *hw)
3105 {
3106 s32 ret_val;
3107 u16 phy_data;
3108
3109 switch (hw->phy_type) {
3110 case e1000_phy_igp:
3111 ret_val = e1000_phy_hw_reset(hw);
3112 if (ret_val)
3113 return ret_val;
3114 break;
3115 default:
3116 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3117 if (ret_val)
3118 return ret_val;
3119
3120 phy_data |= MII_CR_RESET;
3121 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3122 if (ret_val)
3123 return ret_val;
3124
3125 udelay(1);
3126 break;
3127 }
3128
3129 if (hw->phy_type == e1000_phy_igp)
3130 e1000_phy_init_script(hw);
3131
3132 return E1000_SUCCESS;
3133 }
3134
3135 /**
3136 * e1000_detect_gig_phy - check the phy type
3137 * @hw: Struct containing variables accessed by shared code
3138 *
3139 * Probes the expected PHY address for known PHY IDs
3140 */
3141 static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3142 {
3143 s32 phy_init_status, ret_val;
3144 u16 phy_id_high, phy_id_low;
3145 bool match = false;
3146
3147 if (hw->phy_id != 0)
3148 return E1000_SUCCESS;
3149
3150 /* Read the PHY ID Registers to identify which PHY is onboard. */
3151 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3152 if (ret_val)
3153 return ret_val;
3154
3155 hw->phy_id = (u32)(phy_id_high << 16);
3156 udelay(20);
3157 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3158 if (ret_val)
3159 return ret_val;
3160
3161 hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
3162 hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
3163
3164 switch (hw->mac_type) {
3165 case e1000_82543:
3166 if (hw->phy_id == M88E1000_E_PHY_ID)
3167 match = true;
3168 break;
3169 case e1000_82544:
3170 if (hw->phy_id == M88E1000_I_PHY_ID)
3171 match = true;
3172 break;
3173 case e1000_82540:
3174 case e1000_82545:
3175 case e1000_82545_rev_3:
3176 case e1000_82546:
3177 case e1000_82546_rev_3:
3178 if (hw->phy_id == M88E1011_I_PHY_ID)
3179 match = true;
3180 break;
3181 case e1000_ce4100:
3182 if ((hw->phy_id == RTL8211B_PHY_ID) ||
3183 (hw->phy_id == RTL8201N_PHY_ID) ||
3184 (hw->phy_id == M88E1118_E_PHY_ID))
3185 match = true;
3186 break;
3187 case e1000_82541:
3188 case e1000_82541_rev_2:
3189 case e1000_82547:
3190 case e1000_82547_rev_2:
3191 if (hw->phy_id == IGP01E1000_I_PHY_ID)
3192 match = true;
3193 break;
3194 default:
3195 e_dbg("Invalid MAC type %d\n", hw->mac_type);
3196 return -E1000_ERR_CONFIG;
3197 }
3198 phy_init_status = e1000_set_phy_type(hw);
3199
3200 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3201 e_dbg("PHY ID 0x%X detected\n", hw->phy_id);
3202 return E1000_SUCCESS;
3203 }
3204 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);
3205 return -E1000_ERR_PHY;
3206 }
3207
3208 /**
3209 * e1000_phy_reset_dsp - reset DSP
3210 * @hw: Struct containing variables accessed by shared code
3211 *
3212 * Resets the PHY's DSP
3213 */
3214 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3215 {
3216 s32 ret_val;
3217
3218 do {
3219 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3220 if (ret_val)
3221 break;
3222 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3223 if (ret_val)
3224 break;
3225 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3226 if (ret_val)
3227 break;
3228 ret_val = E1000_SUCCESS;
3229 } while (0);
3230
3231 return ret_val;
3232 }
3233
3234 /**
3235 * e1000_phy_igp_get_info - get igp specific registers
3236 * @hw: Struct containing variables accessed by shared code
3237 * @phy_info: PHY information structure
3238 *
3239 * Get PHY information from various PHY registers for igp PHY only.
3240 */
3241 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3242 struct e1000_phy_info *phy_info)
3243 {
3244 s32 ret_val;
3245 u16 phy_data, min_length, max_length, average;
3246 e1000_rev_polarity polarity;
3247
3248 /* The downshift status is checked only once, after link is established,
3249 * and it stored in the hw->speed_downgraded parameter.
3250 */
3251 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3252
3253 /* IGP01E1000 does not need to support it. */
3254 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3255
3256 /* IGP01E1000 always correct polarity reversal */
3257 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3258
3259 /* Check polarity status */
3260 ret_val = e1000_check_polarity(hw, &polarity);
3261 if (ret_val)
3262 return ret_val;
3263
3264 phy_info->cable_polarity = polarity;
3265
3266 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3267 if (ret_val)
3268 return ret_val;
3269
3270 phy_info->mdix_mode =
3271 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3272 IGP01E1000_PSSR_MDIX_SHIFT);
3273
3274 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3275 IGP01E1000_PSSR_SPEED_1000MBPS) {
3276 /* Local/Remote Receiver Information are only valid @ 1000
3277 * Mbps
3278 */
3279 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3280 if (ret_val)
3281 return ret_val;
3282
3283 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3284 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3285 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3286 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3287 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3288 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3289
3290 /* Get cable length */
3291 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3292 if (ret_val)
3293 return ret_val;
3294
3295 /* Translate to old method */
3296 average = (max_length + min_length) / 2;
3297
3298 if (average <= e1000_igp_cable_length_50)
3299 phy_info->cable_length = e1000_cable_length_50;
3300 else if (average <= e1000_igp_cable_length_80)
3301 phy_info->cable_length = e1000_cable_length_50_80;
3302 else if (average <= e1000_igp_cable_length_110)
3303 phy_info->cable_length = e1000_cable_length_80_110;
3304 else if (average <= e1000_igp_cable_length_140)
3305 phy_info->cable_length = e1000_cable_length_110_140;
3306 else
3307 phy_info->cable_length = e1000_cable_length_140;
3308 }
3309
3310 return E1000_SUCCESS;
3311 }
3312
3313 /**
3314 * e1000_phy_m88_get_info - get m88 specific registers
3315 * @hw: Struct containing variables accessed by shared code
3316 * @phy_info: PHY information structure
3317 *
3318 * Get PHY information from various PHY registers for m88 PHY only.
3319 */
3320 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3321 struct e1000_phy_info *phy_info)
3322 {
3323 s32 ret_val;
3324 u16 phy_data;
3325 e1000_rev_polarity polarity;
3326
3327 /* The downshift status is checked only once, after link is established,
3328 * and it stored in the hw->speed_downgraded parameter.
3329 */
3330 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3331
3332 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3333 if (ret_val)
3334 return ret_val;
3335
3336 phy_info->extended_10bt_distance =
3337 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3338 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3339 e1000_10bt_ext_dist_enable_lower :
3340 e1000_10bt_ext_dist_enable_normal;
3341
3342 phy_info->polarity_correction =
3343 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3344 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3345 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3346
3347 /* Check polarity status */
3348 ret_val = e1000_check_polarity(hw, &polarity);
3349 if (ret_val)
3350 return ret_val;
3351 phy_info->cable_polarity = polarity;
3352
3353 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3354 if (ret_val)
3355 return ret_val;
3356
3357 phy_info->mdix_mode =
3358 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3359 M88E1000_PSSR_MDIX_SHIFT);
3360
3361 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3362 /* Cable Length Estimation and Local/Remote Receiver Information
3363 * are only valid at 1000 Mbps.
3364 */
3365 phy_info->cable_length =
3366 (e1000_cable_length) ((phy_data &
3367 M88E1000_PSSR_CABLE_LENGTH) >>
3368 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3369
3370 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3371 if (ret_val)
3372 return ret_val;
3373
3374 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3375 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3376 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3377 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3378 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3379 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3380 }
3381
3382 return E1000_SUCCESS;
3383 }
3384
3385 /**
3386 * e1000_phy_get_info - request phy info
3387 * @hw: Struct containing variables accessed by shared code
3388 * @phy_info: PHY information structure
3389 *
3390 * Get PHY information from various PHY registers
3391 */
3392 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3393 {
3394 s32 ret_val;
3395 u16 phy_data;
3396
3397 phy_info->cable_length = e1000_cable_length_undefined;
3398 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3399 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3400 phy_info->downshift = e1000_downshift_undefined;
3401 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3402 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3403 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3404 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3405
3406 if (hw->media_type != e1000_media_type_copper) {
3407 e_dbg("PHY info is only valid for copper media\n");
3408 return -E1000_ERR_CONFIG;
3409 }
3410
3411 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3412 if (ret_val)
3413 return ret_val;
3414
3415 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3416 if (ret_val)
3417 return ret_val;
3418
3419 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3420 e_dbg("PHY info is only valid if link is up\n");
3421 return -E1000_ERR_CONFIG;
3422 }
3423
3424 if (hw->phy_type == e1000_phy_igp)
3425 return e1000_phy_igp_get_info(hw, phy_info);
3426 else if ((hw->phy_type == e1000_phy_8211) ||
3427 (hw->phy_type == e1000_phy_8201))
3428 return E1000_SUCCESS;
3429 else
3430 return e1000_phy_m88_get_info(hw, phy_info);
3431 }
3432
3433 s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3434 {
3435 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3436 e_dbg("Invalid MDI setting detected\n");
3437 hw->mdix = 1;
3438 return -E1000_ERR_CONFIG;
3439 }
3440 return E1000_SUCCESS;
3441 }
3442
3443 /**
3444 * e1000_init_eeprom_params - initialize sw eeprom vars
3445 * @hw: Struct containing variables accessed by shared code
3446 *
3447 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3448 * is configured.
3449 */
3450 s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3451 {
3452 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3453 u32 eecd = er32(EECD);
3454 s32 ret_val = E1000_SUCCESS;
3455 u16 eeprom_size;
3456
3457 switch (hw->mac_type) {
3458 case e1000_82542_rev2_0:
3459 case e1000_82542_rev2_1:
3460 case e1000_82543:
3461 case e1000_82544:
3462 eeprom->type = e1000_eeprom_microwire;
3463 eeprom->word_size = 64;
3464 eeprom->opcode_bits = 3;
3465 eeprom->address_bits = 6;
3466 eeprom->delay_usec = 50;
3467 break;
3468 case e1000_82540:
3469 case e1000_82545:
3470 case e1000_82545_rev_3:
3471 case e1000_82546:
3472 case e1000_82546_rev_3:
3473 eeprom->type = e1000_eeprom_microwire;
3474 eeprom->opcode_bits = 3;
3475 eeprom->delay_usec = 50;
3476 if (eecd & E1000_EECD_SIZE) {
3477 eeprom->word_size = 256;
3478 eeprom->address_bits = 8;
3479 } else {
3480 eeprom->word_size = 64;
3481 eeprom->address_bits = 6;
3482 }
3483 break;
3484 case e1000_82541:
3485 case e1000_82541_rev_2:
3486 case e1000_82547:
3487 case e1000_82547_rev_2:
3488 if (eecd & E1000_EECD_TYPE) {
3489 eeprom->type = e1000_eeprom_spi;
3490 eeprom->opcode_bits = 8;
3491 eeprom->delay_usec = 1;
3492 if (eecd & E1000_EECD_ADDR_BITS) {
3493 eeprom->page_size = 32;
3494 eeprom->address_bits = 16;
3495 } else {
3496 eeprom->page_size = 8;
3497 eeprom->address_bits = 8;
3498 }
3499 } else {
3500 eeprom->type = e1000_eeprom_microwire;
3501 eeprom->opcode_bits = 3;
3502 eeprom->delay_usec = 50;
3503 if (eecd & E1000_EECD_ADDR_BITS) {
3504 eeprom->word_size = 256;
3505 eeprom->address_bits = 8;
3506 } else {
3507 eeprom->word_size = 64;
3508 eeprom->address_bits = 6;
3509 }
3510 }
3511 break;
3512 default:
3513 break;
3514 }
3515
3516 if (eeprom->type == e1000_eeprom_spi) {
3517 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes
3518 * 128B to 32KB (incremented by powers of 2).
3519 */
3520 /* Set to default value for initial eeprom read. */
3521 eeprom->word_size = 64;
3522 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3523 if (ret_val)
3524 return ret_val;
3525 eeprom_size =
3526 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3527 /* 256B eeprom size was not supported in earlier hardware, so we
3528 * bump eeprom_size up one to ensure that "1" (which maps to
3529 * 256B) is never the result used in the shifting logic below.
3530 */
3531 if (eeprom_size)
3532 eeprom_size++;
3533
3534 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3535 }
3536 return ret_val;
3537 }
3538
3539 /**
3540 * e1000_raise_ee_clk - Raises the EEPROM's clock input.
3541 * @hw: Struct containing variables accessed by shared code
3542 * @eecd: EECD's current value
3543 */
3544 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
3545 {
3546 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3547 * wait <delay> microseconds.
3548 */
3549 *eecd = *eecd | E1000_EECD_SK;
3550 ew32(EECD, *eecd);
3551 E1000_WRITE_FLUSH();
3552 udelay(hw->eeprom.delay_usec);
3553 }
3554
3555 /**
3556 * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
3557 * @hw: Struct containing variables accessed by shared code
3558 * @eecd: EECD's current value
3559 */
3560 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
3561 {
3562 /* Lower the clock input to the EEPROM (by clearing the SK bit), and
3563 * then wait 50 microseconds.
3564 */
3565 *eecd = *eecd & ~E1000_EECD_SK;
3566 ew32(EECD, *eecd);
3567 E1000_WRITE_FLUSH();
3568 udelay(hw->eeprom.delay_usec);
3569 }
3570
3571 /**
3572 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
3573 * @hw: Struct containing variables accessed by shared code
3574 * @data: data to send to the EEPROM
3575 * @count: number of bits to shift out
3576 */
3577 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
3578 {
3579 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3580 u32 eecd;
3581 u32 mask;
3582
3583 /* We need to shift "count" bits out to the EEPROM. So, value in the
3584 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3585 * In order to do this, "data" must be broken down into bits.
3586 */
3587 mask = 0x01 << (count - 1);
3588 eecd = er32(EECD);
3589 if (eeprom->type == e1000_eeprom_microwire)
3590 eecd &= ~E1000_EECD_DO;
3591 else if (eeprom->type == e1000_eeprom_spi)
3592 eecd |= E1000_EECD_DO;
3593
3594 do {
3595 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a
3596 * "1", and then raising and then lowering the clock (the SK bit
3597 * controls the clock input to the EEPROM). A "0" is shifted
3598 * out to the EEPROM by setting "DI" to "0" and then raising and
3599 * then lowering the clock.
3600 */
3601 eecd &= ~E1000_EECD_DI;
3602
3603 if (data & mask)
3604 eecd |= E1000_EECD_DI;
3605
3606 ew32(EECD, eecd);
3607 E1000_WRITE_FLUSH();
3608
3609 udelay(eeprom->delay_usec);
3610
3611 e1000_raise_ee_clk(hw, &eecd);
3612 e1000_lower_ee_clk(hw, &eecd);
3613
3614 mask = mask >> 1;
3615
3616 } while (mask);
3617
3618 /* We leave the "DI" bit set to "0" when we leave this routine. */
3619 eecd &= ~E1000_EECD_DI;
3620 ew32(EECD, eecd);
3621 }
3622
3623 /**
3624 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
3625 * @hw: Struct containing variables accessed by shared code
3626 * @count: number of bits to shift in
3627 */
3628 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
3629 {
3630 u32 eecd;
3631 u32 i;
3632 u16 data;
3633
3634 /* In order to read a register from the EEPROM, we need to shift 'count'
3635 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3636 * input to the EEPROM (setting the SK bit), and then reading the value
3637 * of the "DO" bit. During this "shifting in" process the "DI" bit
3638 * should always be clear.
3639 */
3640
3641 eecd = er32(EECD);
3642
3643 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3644 data = 0;
3645
3646 for (i = 0; i < count; i++) {
3647 data = data << 1;
3648 e1000_raise_ee_clk(hw, &eecd);
3649
3650 eecd = er32(EECD);
3651
3652 eecd &= ~(E1000_EECD_DI);
3653 if (eecd & E1000_EECD_DO)
3654 data |= 1;
3655
3656 e1000_lower_ee_clk(hw, &eecd);
3657 }
3658
3659 return data;
3660 }
3661
3662 /**
3663 * e1000_acquire_eeprom - Prepares EEPROM for access
3664 * @hw: Struct containing variables accessed by shared code
3665 *
3666 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3667 * function should be called before issuing a command to the EEPROM.
3668 */
3669 static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3670 {
3671 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3672 u32 eecd, i = 0;
3673
3674 eecd = er32(EECD);
3675
3676 /* Request EEPROM Access */
3677 if (hw->mac_type > e1000_82544) {
3678 eecd |= E1000_EECD_REQ;
3679 ew32(EECD, eecd);
3680 eecd = er32(EECD);
3681 while ((!(eecd & E1000_EECD_GNT)) &&
3682 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3683 i++;
3684 udelay(5);
3685 eecd = er32(EECD);
3686 }
3687 if (!(eecd & E1000_EECD_GNT)) {
3688 eecd &= ~E1000_EECD_REQ;
3689 ew32(EECD, eecd);
3690 e_dbg("Could not acquire EEPROM grant\n");
3691 return -E1000_ERR_EEPROM;
3692 }
3693 }
3694
3695 /* Setup EEPROM for Read/Write */
3696
3697 if (eeprom->type == e1000_eeprom_microwire) {
3698 /* Clear SK and DI */
3699 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3700 ew32(EECD, eecd);
3701
3702 /* Set CS */
3703 eecd |= E1000_EECD_CS;
3704 ew32(EECD, eecd);
3705 } else if (eeprom->type == e1000_eeprom_spi) {
3706 /* Clear SK and CS */
3707 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3708 ew32(EECD, eecd);
3709 E1000_WRITE_FLUSH();
3710 udelay(1);
3711 }
3712
3713 return E1000_SUCCESS;
3714 }
3715
3716 /**
3717 * e1000_standby_eeprom - Returns EEPROM to a "standby" state
3718 * @hw: Struct containing variables accessed by shared code
3719 */
3720 static void e1000_standby_eeprom(struct e1000_hw *hw)
3721 {
3722 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3723 u32 eecd;
3724
3725 eecd = er32(EECD);
3726
3727 if (eeprom->type == e1000_eeprom_microwire) {
3728 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3729 ew32(EECD, eecd);
3730 E1000_WRITE_FLUSH();
3731 udelay(eeprom->delay_usec);
3732
3733 /* Clock high */
3734 eecd |= E1000_EECD_SK;
3735 ew32(EECD, eecd);
3736 E1000_WRITE_FLUSH();
3737 udelay(eeprom->delay_usec);
3738
3739 /* Select EEPROM */
3740 eecd |= E1000_EECD_CS;
3741 ew32(EECD, eecd);
3742 E1000_WRITE_FLUSH();
3743 udelay(eeprom->delay_usec);
3744
3745 /* Clock low */
3746 eecd &= ~E1000_EECD_SK;
3747 ew32(EECD, eecd);
3748 E1000_WRITE_FLUSH();
3749 udelay(eeprom->delay_usec);
3750 } else if (eeprom->type == e1000_eeprom_spi) {
3751 /* Toggle CS to flush commands */
3752 eecd |= E1000_EECD_CS;
3753 ew32(EECD, eecd);
3754 E1000_WRITE_FLUSH();
3755 udelay(eeprom->delay_usec);
3756 eecd &= ~E1000_EECD_CS;
3757 ew32(EECD, eecd);
3758 E1000_WRITE_FLUSH();
3759 udelay(eeprom->delay_usec);
3760 }
3761 }
3762
3763 /**
3764 * e1000_release_eeprom - drop chip select
3765 * @hw: Struct containing variables accessed by shared code
3766 *
3767 * Terminates a command by inverting the EEPROM's chip select pin
3768 */
3769 static void e1000_release_eeprom(struct e1000_hw *hw)
3770 {
3771 u32 eecd;
3772
3773 eecd = er32(EECD);
3774
3775 if (hw->eeprom.type == e1000_eeprom_spi) {
3776 eecd |= E1000_EECD_CS; /* Pull CS high */
3777 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3778
3779 ew32(EECD, eecd);
3780 E1000_WRITE_FLUSH();
3781
3782 udelay(hw->eeprom.delay_usec);
3783 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3784 /* cleanup eeprom */
3785
3786 /* CS on Microwire is active-high */
3787 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3788
3789 ew32(EECD, eecd);
3790
3791 /* Rising edge of clock */
3792 eecd |= E1000_EECD_SK;
3793 ew32(EECD, eecd);
3794 E1000_WRITE_FLUSH();
3795 udelay(hw->eeprom.delay_usec);
3796
3797 /* Falling edge of clock */
3798 eecd &= ~E1000_EECD_SK;
3799 ew32(EECD, eecd);
3800 E1000_WRITE_FLUSH();
3801 udelay(hw->eeprom.delay_usec);
3802 }
3803
3804 /* Stop requesting EEPROM access */
3805 if (hw->mac_type > e1000_82544) {
3806 eecd &= ~E1000_EECD_REQ;
3807 ew32(EECD, eecd);
3808 }
3809 }
3810
3811 /**
3812 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
3813 * @hw: Struct containing variables accessed by shared code
3814 */
3815 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3816 {
3817 u16 retry_count = 0;
3818 u8 spi_stat_reg;
3819
3820 /* Read "Status Register" repeatedly until the LSB is cleared. The
3821 * EEPROM will signal that the command has been completed by clearing
3822 * bit 0 of the internal status register. If it's not cleared within
3823 * 5 milliseconds, then error out.
3824 */
3825 retry_count = 0;
3826 do {
3827 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3828 hw->eeprom.opcode_bits);
3829 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
3830 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3831 break;
3832
3833 udelay(5);
3834 retry_count += 5;
3835
3836 e1000_standby_eeprom(hw);
3837 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3838
3839 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3840 * only 0-5mSec on 5V devices)
3841 */
3842 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3843 e_dbg("SPI EEPROM Status error\n");
3844 return -E1000_ERR_EEPROM;
3845 }
3846
3847 return E1000_SUCCESS;
3848 }
3849
3850 /**
3851 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
3852 * @hw: Struct containing variables accessed by shared code
3853 * @offset: offset of word in the EEPROM to read
3854 * @data: word read from the EEPROM
3855 * @words: number of words to read
3856 */
3857 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3858 {
3859 s32 ret;
3860
3861 mutex_lock(&e1000_eeprom_lock);
3862 ret = e1000_do_read_eeprom(hw, offset, words, data);
3863 mutex_unlock(&e1000_eeprom_lock);
3864 return ret;
3865 }
3866
3867 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3868 u16 *data)
3869 {
3870 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3871 u32 i = 0;
3872
3873 if (hw->mac_type == e1000_ce4100) {
3874 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
3875 data);
3876 return E1000_SUCCESS;
3877 }
3878
3879 /* A check for invalid values: offset too large, too many words, and
3880 * not enough words.
3881 */
3882 if ((offset >= eeprom->word_size) ||
3883 (words > eeprom->word_size - offset) ||
3884 (words == 0)) {
3885 e_dbg("\"words\" parameter out of bounds. Words = %d,"
3886 "size = %d\n", offset, eeprom->word_size);
3887 return -E1000_ERR_EEPROM;
3888 }
3889
3890 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
3891 * directly. In this case, we need to acquire the EEPROM so that
3892 * FW or other port software does not interrupt.
3893 */
3894 /* Prepare the EEPROM for bit-bang reading */
3895 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3896 return -E1000_ERR_EEPROM;
3897
3898 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
3899 * acquired the EEPROM at this point, so any returns should release it
3900 */
3901 if (eeprom->type == e1000_eeprom_spi) {
3902 u16 word_in;
3903 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3904
3905 if (e1000_spi_eeprom_ready(hw)) {
3906 e1000_release_eeprom(hw);
3907 return -E1000_ERR_EEPROM;
3908 }
3909
3910 e1000_standby_eeprom(hw);
3911
3912 /* Some SPI eeproms use the 8th address bit embedded in the
3913 * opcode
3914 */
3915 if ((eeprom->address_bits == 8) && (offset >= 128))
3916 read_opcode |= EEPROM_A8_OPCODE_SPI;
3917
3918 /* Send the READ command (opcode + addr) */
3919 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3920 e1000_shift_out_ee_bits(hw, (u16)(offset * 2),
3921 eeprom->address_bits);
3922
3923 /* Read the data. The address of the eeprom internally
3924 * increments with each byte (spi) being read, saving on the
3925 * overhead of eeprom setup and tear-down. The address counter
3926 * will roll over if reading beyond the size of the eeprom, thus
3927 * allowing the entire memory to be read starting from any
3928 * offset.
3929 */
3930 for (i = 0; i < words; i++) {
3931 word_in = e1000_shift_in_ee_bits(hw, 16);
3932 data[i] = (word_in >> 8) | (word_in << 8);
3933 }
3934 } else if (eeprom->type == e1000_eeprom_microwire) {
3935 for (i = 0; i < words; i++) {
3936 /* Send the READ command (opcode + addr) */
3937 e1000_shift_out_ee_bits(hw,
3938 EEPROM_READ_OPCODE_MICROWIRE,
3939 eeprom->opcode_bits);
3940 e1000_shift_out_ee_bits(hw, (u16)(offset + i),
3941 eeprom->address_bits);
3942
3943 /* Read the data. For microwire, each word requires the
3944 * overhead of eeprom setup and tear-down.
3945 */
3946 data[i] = e1000_shift_in_ee_bits(hw, 16);
3947 e1000_standby_eeprom(hw);
3948 cond_resched();
3949 }
3950 }
3951
3952 /* End this read operation */
3953 e1000_release_eeprom(hw);
3954
3955 return E1000_SUCCESS;
3956 }
3957
3958 /**
3959 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
3960 * @hw: Struct containing variables accessed by shared code
3961 *
3962 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3963 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3964 * valid.
3965 */
3966 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3967 {
3968 u16 checksum = 0;
3969 u16 i, eeprom_data;
3970
3971 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3972 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3973 e_dbg("EEPROM Read Error\n");
3974 return -E1000_ERR_EEPROM;
3975 }
3976 checksum += eeprom_data;
3977 }
3978
3979 #ifdef CONFIG_PARISC
3980 /* This is a signature and not a checksum on HP c8000 */
3981 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6))
3982 return E1000_SUCCESS;
3983
3984 #endif
3985 if (checksum == (u16)EEPROM_SUM)
3986 return E1000_SUCCESS;
3987 else {
3988 e_dbg("EEPROM Checksum Invalid\n");
3989 return -E1000_ERR_EEPROM;
3990 }
3991 }
3992
3993 /**
3994 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
3995 * @hw: Struct containing variables accessed by shared code
3996 *
3997 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3998 * Writes the difference to word offset 63 of the EEPROM.
3999 */
4000 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
4001 {
4002 u16 checksum = 0;
4003 u16 i, eeprom_data;
4004
4005 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4006 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4007 e_dbg("EEPROM Read Error\n");
4008 return -E1000_ERR_EEPROM;
4009 }
4010 checksum += eeprom_data;
4011 }
4012 checksum = (u16)EEPROM_SUM - checksum;
4013 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4014 e_dbg("EEPROM Write Error\n");
4015 return -E1000_ERR_EEPROM;
4016 }
4017 return E1000_SUCCESS;
4018 }
4019
4020 /**
4021 * e1000_write_eeprom - write words to the different EEPROM types.
4022 * @hw: Struct containing variables accessed by shared code
4023 * @offset: offset within the EEPROM to be written to
4024 * @words: number of words to write
4025 * @data: 16 bit word to be written to the EEPROM
4026 *
4027 * If e1000_update_eeprom_checksum is not called after this function, the
4028 * EEPROM will most likely contain an invalid checksum.
4029 */
4030 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4031 {
4032 s32 ret;
4033
4034 mutex_lock(&e1000_eeprom_lock);
4035 ret = e1000_do_write_eeprom(hw, offset, words, data);
4036 mutex_unlock(&e1000_eeprom_lock);
4037 return ret;
4038 }
4039
4040 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
4041 u16 *data)
4042 {
4043 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4044 s32 status = 0;
4045
4046 if (hw->mac_type == e1000_ce4100) {
4047 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
4048 data);
4049 return E1000_SUCCESS;
4050 }
4051
4052 /* A check for invalid values: offset too large, too many words, and
4053 * not enough words.
4054 */
4055 if ((offset >= eeprom->word_size) ||
4056 (words > eeprom->word_size - offset) ||
4057 (words == 0)) {
4058 e_dbg("\"words\" parameter out of bounds\n");
4059 return -E1000_ERR_EEPROM;
4060 }
4061
4062 /* Prepare the EEPROM for writing */
4063 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4064 return -E1000_ERR_EEPROM;
4065
4066 if (eeprom->type == e1000_eeprom_microwire) {
4067 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4068 } else {
4069 status = e1000_write_eeprom_spi(hw, offset, words, data);
4070 msleep(10);
4071 }
4072
4073 /* Done with writing */
4074 e1000_release_eeprom(hw);
4075
4076 return status;
4077 }
4078
4079 /**
4080 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
4081 * @hw: Struct containing variables accessed by shared code
4082 * @offset: offset within the EEPROM to be written to
4083 * @words: number of words to write
4084 * @data: pointer to array of 8 bit words to be written to the EEPROM
4085 */
4086 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
4087 u16 *data)
4088 {
4089 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4090 u16 widx = 0;
4091
4092 while (widx < words) {
4093 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
4094
4095 if (e1000_spi_eeprom_ready(hw))
4096 return -E1000_ERR_EEPROM;
4097
4098 e1000_standby_eeprom(hw);
4099 cond_resched();
4100
4101 /* Send the WRITE ENABLE command (8 bit opcode ) */
4102 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4103 eeprom->opcode_bits);
4104
4105 e1000_standby_eeprom(hw);
4106
4107 /* Some SPI eeproms use the 8th address bit embedded in the
4108 * opcode
4109 */
4110 if ((eeprom->address_bits == 8) && (offset >= 128))
4111 write_opcode |= EEPROM_A8_OPCODE_SPI;
4112
4113 /* Send the Write command (8-bit opcode + addr) */
4114 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4115
4116 e1000_shift_out_ee_bits(hw, (u16)((offset + widx) * 2),
4117 eeprom->address_bits);
4118
4119 /* Send the data */
4120
4121 /* Loop to allow for up to whole page write (32 bytes) of
4122 * eeprom
4123 */
4124 while (widx < words) {
4125 u16 word_out = data[widx];
4126
4127 word_out = (word_out >> 8) | (word_out << 8);
4128 e1000_shift_out_ee_bits(hw, word_out, 16);
4129 widx++;
4130
4131 /* Some larger eeprom sizes are capable of a 32-byte
4132 * PAGE WRITE operation, while the smaller eeproms are
4133 * capable of an 8-byte PAGE WRITE operation. Break the
4134 * inner loop to pass new address
4135 */
4136 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
4137 e1000_standby_eeprom(hw);
4138 break;
4139 }
4140 }
4141 }
4142
4143 return E1000_SUCCESS;
4144 }
4145
4146 /**
4147 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
4148 * @hw: Struct containing variables accessed by shared code
4149 * @offset: offset within the EEPROM to be written to
4150 * @words: number of words to write
4151 * @data: pointer to array of 8 bit words to be written to the EEPROM
4152 */
4153 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4154 u16 words, u16 *data)
4155 {
4156 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4157 u32 eecd;
4158 u16 words_written = 0;
4159 u16 i = 0;
4160
4161 /* Send the write enable command to the EEPROM (3-bit opcode plus
4162 * 6/8-bit dummy address beginning with 11). It's less work to include
4163 * the 11 of the dummy address as part of the opcode than it is to shift
4164 * it over the correct number of bits for the address. This puts the
4165 * EEPROM into write/erase mode.
4166 */
4167 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4168 (u16)(eeprom->opcode_bits + 2));
4169
4170 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
4171
4172 /* Prepare the EEPROM */
4173 e1000_standby_eeprom(hw);
4174
4175 while (words_written < words) {
4176 /* Send the Write command (3-bit opcode + addr) */
4177 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4178 eeprom->opcode_bits);
4179
4180 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
4181 eeprom->address_bits);
4182
4183 /* Send the data */
4184 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4185
4186 /* Toggle the CS line. This in effect tells the EEPROM to
4187 * execute the previous command.
4188 */
4189 e1000_standby_eeprom(hw);
4190
4191 /* Read DO repeatedly until it is high (equal to '1'). The
4192 * EEPROM will signal that the command has been completed by
4193 * raising the DO signal. If DO does not go high in 10
4194 * milliseconds, then error out.
4195 */
4196 for (i = 0; i < 200; i++) {
4197 eecd = er32(EECD);
4198 if (eecd & E1000_EECD_DO)
4199 break;
4200 udelay(50);
4201 }
4202 if (i == 200) {
4203 e_dbg("EEPROM Write did not complete\n");
4204 return -E1000_ERR_EEPROM;
4205 }
4206
4207 /* Recover from write */
4208 e1000_standby_eeprom(hw);
4209 cond_resched();
4210
4211 words_written++;
4212 }
4213
4214 /* Send the write disable command to the EEPROM (3-bit opcode plus
4215 * 6/8-bit dummy address beginning with 10). It's less work to include
4216 * the 10 of the dummy address as part of the opcode than it is to shift
4217 * it over the correct number of bits for the address. This takes the
4218 * EEPROM out of write/erase mode.
4219 */
4220 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4221 (u16)(eeprom->opcode_bits + 2));
4222
4223 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
4224
4225 return E1000_SUCCESS;
4226 }
4227
4228 /**
4229 * e1000_read_mac_addr - read the adapters MAC from eeprom
4230 * @hw: Struct containing variables accessed by shared code
4231 *
4232 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4233 * second function of dual function devices
4234 */
4235 s32 e1000_read_mac_addr(struct e1000_hw *hw)
4236 {
4237 u16 offset;
4238 u16 eeprom_data, i;
4239
4240 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4241 offset = i >> 1;
4242 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4243 e_dbg("EEPROM Read Error\n");
4244 return -E1000_ERR_EEPROM;
4245 }
4246 hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
4247 hw->perm_mac_addr[i + 1] = (u8)(eeprom_data >> 8);
4248 }
4249
4250 switch (hw->mac_type) {
4251 default:
4252 break;
4253 case e1000_82546:
4254 case e1000_82546_rev_3:
4255 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4256 hw->perm_mac_addr[5] ^= 0x01;
4257 break;
4258 }
4259
4260 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4261 hw->mac_addr[i] = hw->perm_mac_addr[i];
4262 return E1000_SUCCESS;
4263 }
4264
4265 /**
4266 * e1000_init_rx_addrs - Initializes receive address filters.
4267 * @hw: Struct containing variables accessed by shared code
4268 *
4269 * Places the MAC address in receive address register 0 and clears the rest
4270 * of the receive address registers. Clears the multicast table. Assumes
4271 * the receiver is in reset when the routine is called.
4272 */
4273 static void e1000_init_rx_addrs(struct e1000_hw *hw)
4274 {
4275 u32 i;
4276 u32 rar_num;
4277
4278 /* Setup the receive address. */
4279 e_dbg("Programming MAC Address into RAR[0]\n");
4280
4281 e1000_rar_set(hw, hw->mac_addr, 0);
4282
4283 rar_num = E1000_RAR_ENTRIES;
4284
4285 /* Zero out the following 14 receive addresses. RAR[15] is for
4286 * manageability
4287 */
4288 e_dbg("Clearing RAR[1-14]\n");
4289 for (i = 1; i < rar_num; i++) {
4290 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4291 E1000_WRITE_FLUSH();
4292 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4293 E1000_WRITE_FLUSH();
4294 }
4295 }
4296
4297 /**
4298 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
4299 * @hw: Struct containing variables accessed by shared code
4300 * @mc_addr: the multicast address to hash
4301 */
4302 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
4303 {
4304 u32 hash_value = 0;
4305
4306 /* The portion of the address that is used for the hash table is
4307 * determined by the mc_filter_type setting.
4308 */
4309 switch (hw->mc_filter_type) {
4310 /* [0] [1] [2] [3] [4] [5]
4311 * 01 AA 00 12 34 56
4312 * LSB MSB
4313 */
4314 case 0:
4315 /* [47:36] i.e. 0x563 for above example address */
4316 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
4317 break;
4318 case 1:
4319 /* [46:35] i.e. 0xAC6 for above example address */
4320 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
4321 break;
4322 case 2:
4323 /* [45:34] i.e. 0x5D8 for above example address */
4324 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
4325 break;
4326 case 3:
4327 /* [43:32] i.e. 0x634 for above example address */
4328 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
4329 break;
4330 }
4331
4332 hash_value &= 0xFFF;
4333 return hash_value;
4334 }
4335
4336 /**
4337 * e1000_rar_set - Puts an ethernet address into a receive address register.
4338 * @hw: Struct containing variables accessed by shared code
4339 * @addr: Address to put into receive address register
4340 * @index: Receive address register to write
4341 */
4342 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
4343 {
4344 u32 rar_low, rar_high;
4345
4346 /* HW expects these in little endian so we reverse the byte order
4347 * from network order (big endian) to little endian
4348 */
4349 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
4350 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
4351 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
4352
4353 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
4354 * unit hang.
4355 *
4356 * Description:
4357 * If there are any Rx frames queued up or otherwise present in the HW
4358 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
4359 * hang. To work around this issue, we have to disable receives and
4360 * flush out all Rx frames before we enable RSS. To do so, we modify we
4361 * redirect all Rx traffic to manageability and then reset the HW.
4362 * This flushes away Rx frames, and (since the redirections to
4363 * manageability persists across resets) keeps new ones from coming in
4364 * while we work. Then, we clear the Address Valid AV bit for all MAC
4365 * addresses and undo the re-direction to manageability.
4366 * Now, frames are coming in again, but the MAC won't accept them, so
4367 * far so good. We now proceed to initialize RSS (if necessary) and
4368 * configure the Rx unit. Last, we re-enable the AV bits and continue
4369 * on our merry way.
4370 */
4371 switch (hw->mac_type) {
4372 default:
4373 /* Indicate to hardware the Address is Valid. */
4374 rar_high |= E1000_RAH_AV;
4375 break;
4376 }
4377
4378 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4379 E1000_WRITE_FLUSH();
4380 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4381 E1000_WRITE_FLUSH();
4382 }
4383
4384 /**
4385 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
4386 * @hw: Struct containing variables accessed by shared code
4387 * @offset: Offset in VLAN filer table to write
4388 * @value: Value to write into VLAN filter table
4389 */
4390 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
4391 {
4392 u32 temp;
4393
4394 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4395 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4396 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4397 E1000_WRITE_FLUSH();
4398 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4399 E1000_WRITE_FLUSH();
4400 } else {
4401 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4402 E1000_WRITE_FLUSH();
4403 }
4404 }
4405
4406 /**
4407 * e1000_clear_vfta - Clears the VLAN filer table
4408 * @hw: Struct containing variables accessed by shared code
4409 */
4410 static void e1000_clear_vfta(struct e1000_hw *hw)
4411 {
4412 u32 offset;
4413 u32 vfta_value = 0;
4414 u32 vfta_offset = 0;
4415 u32 vfta_bit_in_reg = 0;
4416
4417 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4418 /* If the offset we want to clear is the same offset of the
4419 * manageability VLAN ID, then clear all bits except that of the
4420 * manageability unit
4421 */
4422 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4423 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4424 E1000_WRITE_FLUSH();
4425 }
4426 }
4427
4428 static s32 e1000_id_led_init(struct e1000_hw *hw)
4429 {
4430 u32 ledctl;
4431 const u32 ledctl_mask = 0x000000FF;
4432 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4433 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4434 u16 eeprom_data, i, temp;
4435 const u16 led_mask = 0x0F;
4436
4437 if (hw->mac_type < e1000_82540) {
4438 /* Nothing to do */
4439 return E1000_SUCCESS;
4440 }
4441
4442 ledctl = er32(LEDCTL);
4443 hw->ledctl_default = ledctl;
4444 hw->ledctl_mode1 = hw->ledctl_default;
4445 hw->ledctl_mode2 = hw->ledctl_default;
4446
4447 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4448 e_dbg("EEPROM Read Error\n");
4449 return -E1000_ERR_EEPROM;
4450 }
4451
4452 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4453 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4454 eeprom_data = ID_LED_DEFAULT;
4455 }
4456
4457 for (i = 0; i < 4; i++) {
4458 temp = (eeprom_data >> (i << 2)) & led_mask;
4459 switch (temp) {
4460 case ID_LED_ON1_DEF2:
4461 case ID_LED_ON1_ON2:
4462 case ID_LED_ON1_OFF2:
4463 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4464 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4465 break;
4466 case ID_LED_OFF1_DEF2:
4467 case ID_LED_OFF1_ON2:
4468 case ID_LED_OFF1_OFF2:
4469 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4470 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4471 break;
4472 default:
4473 /* Do nothing */
4474 break;
4475 }
4476 switch (temp) {
4477 case ID_LED_DEF1_ON2:
4478 case ID_LED_ON1_ON2:
4479 case ID_LED_OFF1_ON2:
4480 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4481 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4482 break;
4483 case ID_LED_DEF1_OFF2:
4484 case ID_LED_ON1_OFF2:
4485 case ID_LED_OFF1_OFF2:
4486 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4487 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4488 break;
4489 default:
4490 /* Do nothing */
4491 break;
4492 }
4493 }
4494 return E1000_SUCCESS;
4495 }
4496
4497 /**
4498 * e1000_setup_led
4499 * @hw: Struct containing variables accessed by shared code
4500 *
4501 * Prepares SW controlable LED for use and saves the current state of the LED.
4502 */
4503 s32 e1000_setup_led(struct e1000_hw *hw)
4504 {
4505 u32 ledctl;
4506 s32 ret_val = E1000_SUCCESS;
4507
4508 switch (hw->mac_type) {
4509 case e1000_82542_rev2_0:
4510 case e1000_82542_rev2_1:
4511 case e1000_82543:
4512 case e1000_82544:
4513 /* No setup necessary */
4514 break;
4515 case e1000_82541:
4516 case e1000_82547:
4517 case e1000_82541_rev_2:
4518 case e1000_82547_rev_2:
4519 /* Turn off PHY Smart Power Down (if enabled) */
4520 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4521 &hw->phy_spd_default);
4522 if (ret_val)
4523 return ret_val;
4524 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4525 (u16)(hw->phy_spd_default &
4526 ~IGP01E1000_GMII_SPD));
4527 if (ret_val)
4528 return ret_val;
4529 /* Fall Through */
4530 default:
4531 if (hw->media_type == e1000_media_type_fiber) {
4532 ledctl = er32(LEDCTL);
4533 /* Save current LEDCTL settings */
4534 hw->ledctl_default = ledctl;
4535 /* Turn off LED0 */
4536 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4537 E1000_LEDCTL_LED0_BLINK |
4538 E1000_LEDCTL_LED0_MODE_MASK);
4539 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4540 E1000_LEDCTL_LED0_MODE_SHIFT);
4541 ew32(LEDCTL, ledctl);
4542 } else if (hw->media_type == e1000_media_type_copper)
4543 ew32(LEDCTL, hw->ledctl_mode1);
4544 break;
4545 }
4546
4547 return E1000_SUCCESS;
4548 }
4549
4550 /**
4551 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
4552 * @hw: Struct containing variables accessed by shared code
4553 */
4554 s32 e1000_cleanup_led(struct e1000_hw *hw)
4555 {
4556 s32 ret_val = E1000_SUCCESS;
4557
4558 switch (hw->mac_type) {
4559 case e1000_82542_rev2_0:
4560 case e1000_82542_rev2_1:
4561 case e1000_82543:
4562 case e1000_82544:
4563 /* No cleanup necessary */
4564 break;
4565 case e1000_82541:
4566 case e1000_82547:
4567 case e1000_82541_rev_2:
4568 case e1000_82547_rev_2:
4569 /* Turn on PHY Smart Power Down (if previously enabled) */
4570 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4571 hw->phy_spd_default);
4572 if (ret_val)
4573 return ret_val;
4574 /* Fall Through */
4575 default:
4576 /* Restore LEDCTL settings */
4577 ew32(LEDCTL, hw->ledctl_default);
4578 break;
4579 }
4580
4581 return E1000_SUCCESS;
4582 }
4583
4584 /**
4585 * e1000_led_on - Turns on the software controllable LED
4586 * @hw: Struct containing variables accessed by shared code
4587 */
4588 s32 e1000_led_on(struct e1000_hw *hw)
4589 {
4590 u32 ctrl = er32(CTRL);
4591
4592 switch (hw->mac_type) {
4593 case e1000_82542_rev2_0:
4594 case e1000_82542_rev2_1:
4595 case e1000_82543:
4596 /* Set SW Defineable Pin 0 to turn on the LED */
4597 ctrl |= E1000_CTRL_SWDPIN0;
4598 ctrl |= E1000_CTRL_SWDPIO0;
4599 break;
4600 case e1000_82544:
4601 if (hw->media_type == e1000_media_type_fiber) {
4602 /* Set SW Defineable Pin 0 to turn on the LED */
4603 ctrl |= E1000_CTRL_SWDPIN0;
4604 ctrl |= E1000_CTRL_SWDPIO0;
4605 } else {
4606 /* Clear SW Defineable Pin 0 to turn on the LED */
4607 ctrl &= ~E1000_CTRL_SWDPIN0;
4608 ctrl |= E1000_CTRL_SWDPIO0;
4609 }
4610 break;
4611 default:
4612 if (hw->media_type == e1000_media_type_fiber) {
4613 /* Clear SW Defineable Pin 0 to turn on the LED */
4614 ctrl &= ~E1000_CTRL_SWDPIN0;
4615 ctrl |= E1000_CTRL_SWDPIO0;
4616 } else if (hw->media_type == e1000_media_type_copper) {
4617 ew32(LEDCTL, hw->ledctl_mode2);
4618 return E1000_SUCCESS;
4619 }
4620 break;
4621 }
4622
4623 ew32(CTRL, ctrl);
4624
4625 return E1000_SUCCESS;
4626 }
4627
4628 /**
4629 * e1000_led_off - Turns off the software controllable LED
4630 * @hw: Struct containing variables accessed by shared code
4631 */
4632 s32 e1000_led_off(struct e1000_hw *hw)
4633 {
4634 u32 ctrl = er32(CTRL);
4635
4636 switch (hw->mac_type) {
4637 case e1000_82542_rev2_0:
4638 case e1000_82542_rev2_1:
4639 case e1000_82543:
4640 /* Clear SW Defineable Pin 0 to turn off the LED */
4641 ctrl &= ~E1000_CTRL_SWDPIN0;
4642 ctrl |= E1000_CTRL_SWDPIO0;
4643 break;
4644 case e1000_82544:
4645 if (hw->media_type == e1000_media_type_fiber) {
4646 /* Clear SW Defineable Pin 0 to turn off the LED */
4647 ctrl &= ~E1000_CTRL_SWDPIN0;
4648 ctrl |= E1000_CTRL_SWDPIO0;
4649 } else {
4650 /* Set SW Defineable Pin 0 to turn off the LED */
4651 ctrl |= E1000_CTRL_SWDPIN0;
4652 ctrl |= E1000_CTRL_SWDPIO0;
4653 }
4654 break;
4655 default:
4656 if (hw->media_type == e1000_media_type_fiber) {
4657 /* Set SW Defineable Pin 0 to turn off the LED */
4658 ctrl |= E1000_CTRL_SWDPIN0;
4659 ctrl |= E1000_CTRL_SWDPIO0;
4660 } else if (hw->media_type == e1000_media_type_copper) {
4661 ew32(LEDCTL, hw->ledctl_mode1);
4662 return E1000_SUCCESS;
4663 }
4664 break;
4665 }
4666
4667 ew32(CTRL, ctrl);
4668
4669 return E1000_SUCCESS;
4670 }
4671
4672 /**
4673 * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
4674 * @hw: Struct containing variables accessed by shared code
4675 */
4676 static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4677 {
4678 volatile u32 temp;
4679
4680 temp = er32(CRCERRS);
4681 temp = er32(SYMERRS);
4682 temp = er32(MPC);
4683 temp = er32(SCC);
4684 temp = er32(ECOL);
4685 temp = er32(MCC);
4686 temp = er32(LATECOL);
4687 temp = er32(COLC);
4688 temp = er32(DC);
4689 temp = er32(SEC);
4690 temp = er32(RLEC);
4691 temp = er32(XONRXC);
4692 temp = er32(XONTXC);
4693 temp = er32(XOFFRXC);
4694 temp = er32(XOFFTXC);
4695 temp = er32(FCRUC);
4696
4697 temp = er32(PRC64);
4698 temp = er32(PRC127);
4699 temp = er32(PRC255);
4700 temp = er32(PRC511);
4701 temp = er32(PRC1023);
4702 temp = er32(PRC1522);
4703
4704 temp = er32(GPRC);
4705 temp = er32(BPRC);
4706 temp = er32(MPRC);
4707 temp = er32(GPTC);
4708 temp = er32(GORCL);
4709 temp = er32(GORCH);
4710 temp = er32(GOTCL);
4711 temp = er32(GOTCH);
4712 temp = er32(RNBC);
4713 temp = er32(RUC);
4714 temp = er32(RFC);
4715 temp = er32(ROC);
4716 temp = er32(RJC);
4717 temp = er32(TORL);
4718 temp = er32(TORH);
4719 temp = er32(TOTL);
4720 temp = er32(TOTH);
4721 temp = er32(TPR);
4722 temp = er32(TPT);
4723
4724 temp = er32(PTC64);
4725 temp = er32(PTC127);
4726 temp = er32(PTC255);
4727 temp = er32(PTC511);
4728 temp = er32(PTC1023);
4729 temp = er32(PTC1522);
4730
4731 temp = er32(MPTC);
4732 temp = er32(BPTC);
4733
4734 if (hw->mac_type < e1000_82543)
4735 return;
4736
4737 temp = er32(ALGNERRC);
4738 temp = er32(RXERRC);
4739 temp = er32(TNCRS);
4740 temp = er32(CEXTERR);
4741 temp = er32(TSCTC);
4742 temp = er32(TSCTFC);
4743
4744 if (hw->mac_type <= e1000_82544)
4745 return;
4746
4747 temp = er32(MGTPRC);
4748 temp = er32(MGTPDC);
4749 temp = er32(MGTPTC);
4750 }
4751
4752 /**
4753 * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
4754 * @hw: Struct containing variables accessed by shared code
4755 *
4756 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4757 * hw->ifs_params_forced to true. However, you must initialize hw->
4758 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4759 * before calling this function.
4760 */
4761 void e1000_reset_adaptive(struct e1000_hw *hw)
4762 {
4763 if (hw->adaptive_ifs) {
4764 if (!hw->ifs_params_forced) {
4765 hw->current_ifs_val = 0;
4766 hw->ifs_min_val = IFS_MIN;
4767 hw->ifs_max_val = IFS_MAX;
4768 hw->ifs_step_size = IFS_STEP;
4769 hw->ifs_ratio = IFS_RATIO;
4770 }
4771 hw->in_ifs_mode = false;
4772 ew32(AIT, 0);
4773 } else {
4774 e_dbg("Not in Adaptive IFS mode!\n");
4775 }
4776 }
4777
4778 /**
4779 * e1000_update_adaptive - update adaptive IFS
4780 * @hw: Struct containing variables accessed by shared code
4781 * @tx_packets: Number of transmits since last callback
4782 * @total_collisions: Number of collisions since last callback
4783 *
4784 * Called during the callback/watchdog routine to update IFS value based on
4785 * the ratio of transmits to collisions.
4786 */
4787 void e1000_update_adaptive(struct e1000_hw *hw)
4788 {
4789 if (hw->adaptive_ifs) {
4790 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4791 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4792 hw->in_ifs_mode = true;
4793 if (hw->current_ifs_val < hw->ifs_max_val) {
4794 if (hw->current_ifs_val == 0)
4795 hw->current_ifs_val =
4796 hw->ifs_min_val;
4797 else
4798 hw->current_ifs_val +=
4799 hw->ifs_step_size;
4800 ew32(AIT, hw->current_ifs_val);
4801 }
4802 }
4803 } else {
4804 if (hw->in_ifs_mode &&
4805 (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4806 hw->current_ifs_val = 0;
4807 hw->in_ifs_mode = false;
4808 ew32(AIT, 0);
4809 }
4810 }
4811 } else {
4812 e_dbg("Not in Adaptive IFS mode!\n");
4813 }
4814 }
4815
4816 /**
4817 * e1000_get_bus_info
4818 * @hw: Struct containing variables accessed by shared code
4819 *
4820 * Gets the current PCI bus type, speed, and width of the hardware
4821 */
4822 void e1000_get_bus_info(struct e1000_hw *hw)
4823 {
4824 u32 status;
4825
4826 switch (hw->mac_type) {
4827 case e1000_82542_rev2_0:
4828 case e1000_82542_rev2_1:
4829 hw->bus_type = e1000_bus_type_pci;
4830 hw->bus_speed = e1000_bus_speed_unknown;
4831 hw->bus_width = e1000_bus_width_unknown;
4832 break;
4833 default:
4834 status = er32(STATUS);
4835 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4836 e1000_bus_type_pcix : e1000_bus_type_pci;
4837
4838 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4839 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4840 e1000_bus_speed_66 : e1000_bus_speed_120;
4841 } else if (hw->bus_type == e1000_bus_type_pci) {
4842 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4843 e1000_bus_speed_66 : e1000_bus_speed_33;
4844 } else {
4845 switch (status & E1000_STATUS_PCIX_SPEED) {
4846 case E1000_STATUS_PCIX_SPEED_66:
4847 hw->bus_speed = e1000_bus_speed_66;
4848 break;
4849 case E1000_STATUS_PCIX_SPEED_100:
4850 hw->bus_speed = e1000_bus_speed_100;
4851 break;
4852 case E1000_STATUS_PCIX_SPEED_133:
4853 hw->bus_speed = e1000_bus_speed_133;
4854 break;
4855 default:
4856 hw->bus_speed = e1000_bus_speed_reserved;
4857 break;
4858 }
4859 }
4860 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4861 e1000_bus_width_64 : e1000_bus_width_32;
4862 break;
4863 }
4864 }
4865
4866 /**
4867 * e1000_write_reg_io
4868 * @hw: Struct containing variables accessed by shared code
4869 * @offset: offset to write to
4870 * @value: value to write
4871 *
4872 * Writes a value to one of the devices registers using port I/O (as opposed to
4873 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4874 */
4875 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
4876 {
4877 unsigned long io_addr = hw->io_base;
4878 unsigned long io_data = hw->io_base + 4;
4879
4880 e1000_io_write(hw, io_addr, offset);
4881 e1000_io_write(hw, io_data, value);
4882 }
4883
4884 /**
4885 * e1000_get_cable_length - Estimates the cable length.
4886 * @hw: Struct containing variables accessed by shared code
4887 * @min_length: The estimated minimum length
4888 * @max_length: The estimated maximum length
4889 *
4890 * returns: - E1000_ERR_XXX
4891 * E1000_SUCCESS
4892 *
4893 * This function always returns a ranged length (minimum & maximum).
4894 * So for M88 phy's, this function interprets the one value returned from the
4895 * register to the minimum and maximum range.
4896 * For IGP phy's, the function calculates the range by the AGC registers.
4897 */
4898 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
4899 u16 *max_length)
4900 {
4901 s32 ret_val;
4902 u16 agc_value = 0;
4903 u16 i, phy_data;
4904 u16 cable_length;
4905
4906 *min_length = *max_length = 0;
4907
4908 /* Use old method for Phy older than IGP */
4909 if (hw->phy_type == e1000_phy_m88) {
4910 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4911 &phy_data);
4912 if (ret_val)
4913 return ret_val;
4914 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4915 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
4916
4917 /* Convert the enum value to ranged values */
4918 switch (cable_length) {
4919 case e1000_cable_length_50:
4920 *min_length = 0;
4921 *max_length = e1000_igp_cable_length_50;
4922 break;
4923 case e1000_cable_length_50_80:
4924 *min_length = e1000_igp_cable_length_50;
4925 *max_length = e1000_igp_cable_length_80;
4926 break;
4927 case e1000_cable_length_80_110:
4928 *min_length = e1000_igp_cable_length_80;
4929 *max_length = e1000_igp_cable_length_110;
4930 break;
4931 case e1000_cable_length_110_140:
4932 *min_length = e1000_igp_cable_length_110;
4933 *max_length = e1000_igp_cable_length_140;
4934 break;
4935 case e1000_cable_length_140:
4936 *min_length = e1000_igp_cable_length_140;
4937 *max_length = e1000_igp_cable_length_170;
4938 break;
4939 default:
4940 return -E1000_ERR_PHY;
4941 }
4942 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
4943 u16 cur_agc_value;
4944 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4945 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
4946 IGP01E1000_PHY_AGC_A,
4947 IGP01E1000_PHY_AGC_B,
4948 IGP01E1000_PHY_AGC_C,
4949 IGP01E1000_PHY_AGC_D
4950 };
4951 /* Read the AGC registers for all channels */
4952 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4953 ret_val =
4954 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4955 if (ret_val)
4956 return ret_val;
4957
4958 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4959
4960 /* Value bound check. */
4961 if ((cur_agc_value >=
4962 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4963 (cur_agc_value == 0))
4964 return -E1000_ERR_PHY;
4965
4966 agc_value += cur_agc_value;
4967
4968 /* Update minimal AGC value. */
4969 if (min_agc_value > cur_agc_value)
4970 min_agc_value = cur_agc_value;
4971 }
4972
4973 /* Remove the minimal AGC result for length < 50m */
4974 if (agc_value <
4975 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4976 agc_value -= min_agc_value;
4977
4978 /* Get the average length of the remaining 3 channels */
4979 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4980 } else {
4981 /* Get the average length of all the 4 channels. */
4982 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4983 }
4984
4985 /* Set the range of the calculated length. */
4986 *min_length = ((e1000_igp_cable_length_table[agc_value] -
4987 IGP01E1000_AGC_RANGE) > 0) ?
4988 (e1000_igp_cable_length_table[agc_value] -
4989 IGP01E1000_AGC_RANGE) : 0;
4990 *max_length = e1000_igp_cable_length_table[agc_value] +
4991 IGP01E1000_AGC_RANGE;
4992 }
4993
4994 return E1000_SUCCESS;
4995 }
4996
4997 /**
4998 * e1000_check_polarity - Check the cable polarity
4999 * @hw: Struct containing variables accessed by shared code
5000 * @polarity: output parameter : 0 - Polarity is not reversed
5001 * 1 - Polarity is reversed.
5002 *
5003 * returns: - E1000_ERR_XXX
5004 * E1000_SUCCESS
5005 *
5006 * For phy's older than IGP, this function simply reads the polarity bit in the
5007 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
5008 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
5009 * return 0. If the link speed is 1000 Mbps the polarity status is in the
5010 * IGP01E1000_PHY_PCS_INIT_REG.
5011 */
5012 static s32 e1000_check_polarity(struct e1000_hw *hw,
5013 e1000_rev_polarity *polarity)
5014 {
5015 s32 ret_val;
5016 u16 phy_data;
5017
5018 if (hw->phy_type == e1000_phy_m88) {
5019 /* return the Polarity bit in the Status register. */
5020 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5021 &phy_data);
5022 if (ret_val)
5023 return ret_val;
5024 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
5025 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
5026 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
5027
5028 } else if (hw->phy_type == e1000_phy_igp) {
5029 /* Read the Status register to check the speed */
5030 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5031 &phy_data);
5032 if (ret_val)
5033 return ret_val;
5034
5035 /* If speed is 1000 Mbps, must read the
5036 * IGP01E1000_PHY_PCS_INIT_REG to find the polarity status
5037 */
5038 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5039 IGP01E1000_PSSR_SPEED_1000MBPS) {
5040 /* Read the GIG initialization PCS register (0x00B4) */
5041 ret_val =
5042 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5043 &phy_data);
5044 if (ret_val)
5045 return ret_val;
5046
5047 /* Check the polarity bits */
5048 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5049 e1000_rev_polarity_reversed :
5050 e1000_rev_polarity_normal;
5051 } else {
5052 /* For 10 Mbps, read the polarity bit in the status
5053 * register. (for 100 Mbps this bit is always 0)
5054 */
5055 *polarity =
5056 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5057 e1000_rev_polarity_reversed :
5058 e1000_rev_polarity_normal;
5059 }
5060 }
5061 return E1000_SUCCESS;
5062 }
5063
5064 /**
5065 * e1000_check_downshift - Check if Downshift occurred
5066 * @hw: Struct containing variables accessed by shared code
5067 * @downshift: output parameter : 0 - No Downshift occurred.
5068 * 1 - Downshift occurred.
5069 *
5070 * returns: - E1000_ERR_XXX
5071 * E1000_SUCCESS
5072 *
5073 * For phy's older than IGP, this function reads the Downshift bit in the Phy
5074 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5075 * Link Health register. In IGP this bit is latched high, so the driver must
5076 * read it immediately after link is established.
5077 */
5078 static s32 e1000_check_downshift(struct e1000_hw *hw)
5079 {
5080 s32 ret_val;
5081 u16 phy_data;
5082
5083 if (hw->phy_type == e1000_phy_igp) {
5084 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5085 &phy_data);
5086 if (ret_val)
5087 return ret_val;
5088
5089 hw->speed_downgraded =
5090 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5091 } else if (hw->phy_type == e1000_phy_m88) {
5092 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5093 &phy_data);
5094 if (ret_val)
5095 return ret_val;
5096
5097 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5098 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5099 }
5100
5101 return E1000_SUCCESS;
5102 }
5103
5104 static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5105 IGP01E1000_PHY_AGC_PARAM_A,
5106 IGP01E1000_PHY_AGC_PARAM_B,
5107 IGP01E1000_PHY_AGC_PARAM_C,
5108 IGP01E1000_PHY_AGC_PARAM_D
5109 };
5110
5111 static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw)
5112 {
5113 u16 min_length, max_length;
5114 u16 phy_data, i;
5115 s32 ret_val;
5116
5117 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
5118 if (ret_val)
5119 return ret_val;
5120
5121 if (hw->dsp_config_state != e1000_dsp_config_enabled)
5122 return 0;
5123
5124 if (min_length >= e1000_igp_cable_length_50) {
5125 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5126 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
5127 &phy_data);
5128 if (ret_val)
5129 return ret_val;
5130
5131 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5132
5133 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
5134 phy_data);
5135 if (ret_val)
5136 return ret_val;
5137 }
5138 hw->dsp_config_state = e1000_dsp_config_activated;
5139 } else {
5140 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5141 u32 idle_errs = 0;
5142
5143 /* clear previous idle error counts */
5144 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
5145 if (ret_val)
5146 return ret_val;
5147
5148 for (i = 0; i < ffe_idle_err_timeout; i++) {
5149 udelay(1000);
5150 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5151 &phy_data);
5152 if (ret_val)
5153 return ret_val;
5154
5155 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
5156 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
5157 hw->ffe_config_state = e1000_ffe_config_active;
5158
5159 ret_val = e1000_write_phy_reg(hw,
5160 IGP01E1000_PHY_DSP_FFE,
5161 IGP01E1000_PHY_DSP_FFE_CM_CP);
5162 if (ret_val)
5163 return ret_val;
5164 break;
5165 }
5166
5167 if (idle_errs)
5168 ffe_idle_err_timeout =
5169 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5170 }
5171 }
5172
5173 return 0;
5174 }
5175
5176 /**
5177 * e1000_config_dsp_after_link_change
5178 * @hw: Struct containing variables accessed by shared code
5179 * @link_up: was link up at the time this was called
5180 *
5181 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5182 * E1000_SUCCESS at any other case.
5183 *
5184 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5185 * gigabit link is achieved to improve link quality.
5186 */
5187
5188 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5189 {
5190 s32 ret_val;
5191 u16 phy_data, phy_saved_data, speed, duplex, i;
5192
5193 if (hw->phy_type != e1000_phy_igp)
5194 return E1000_SUCCESS;
5195
5196 if (link_up) {
5197 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5198 if (ret_val) {
5199 e_dbg("Error getting link speed and duplex\n");
5200 return ret_val;
5201 }
5202
5203 if (speed == SPEED_1000) {
5204 ret_val = e1000_1000Mb_check_cable_length(hw);
5205 if (ret_val)
5206 return ret_val;
5207 }
5208 } else {
5209 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5210 /* Save off the current value of register 0x2F5B to be
5211 * restored at the end of the routines.
5212 */
5213 ret_val =
5214 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5215
5216 if (ret_val)
5217 return ret_val;
5218
5219 /* Disable the PHY transmitter */
5220 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5221
5222 if (ret_val)
5223 return ret_val;
5224
5225 msleep(20);
5226
5227 ret_val = e1000_write_phy_reg(hw, 0x0000,
5228 IGP01E1000_IEEE_FORCE_GIGA);
5229 if (ret_val)
5230 return ret_val;
5231 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5232 ret_val =
5233 e1000_read_phy_reg(hw, dsp_reg_array[i],
5234 &phy_data);
5235 if (ret_val)
5236 return ret_val;
5237
5238 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5239 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5240
5241 ret_val =
5242 e1000_write_phy_reg(hw, dsp_reg_array[i],
5243 phy_data);
5244 if (ret_val)
5245 return ret_val;
5246 }
5247
5248 ret_val = e1000_write_phy_reg(hw, 0x0000,
5249 IGP01E1000_IEEE_RESTART_AUTONEG);
5250 if (ret_val)
5251 return ret_val;
5252
5253 msleep(20);
5254
5255 /* Now enable the transmitter */
5256 ret_val =
5257 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5258
5259 if (ret_val)
5260 return ret_val;
5261
5262 hw->dsp_config_state = e1000_dsp_config_enabled;
5263 }
5264
5265 if (hw->ffe_config_state == e1000_ffe_config_active) {
5266 /* Save off the current value of register 0x2F5B to be
5267 * restored at the end of the routines.
5268 */
5269 ret_val =
5270 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5271
5272 if (ret_val)
5273 return ret_val;
5274
5275 /* Disable the PHY transmitter */
5276 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5277
5278 if (ret_val)
5279 return ret_val;
5280
5281 msleep(20);
5282
5283 ret_val = e1000_write_phy_reg(hw, 0x0000,
5284 IGP01E1000_IEEE_FORCE_GIGA);
5285 if (ret_val)
5286 return ret_val;
5287 ret_val =
5288 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5289 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5290 if (ret_val)
5291 return ret_val;
5292
5293 ret_val = e1000_write_phy_reg(hw, 0x0000,
5294 IGP01E1000_IEEE_RESTART_AUTONEG);
5295 if (ret_val)
5296 return ret_val;
5297
5298 msleep(20);
5299
5300 /* Now enable the transmitter */
5301 ret_val =
5302 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5303
5304 if (ret_val)
5305 return ret_val;
5306
5307 hw->ffe_config_state = e1000_ffe_config_enabled;
5308 }
5309 }
5310 return E1000_SUCCESS;
5311 }
5312
5313 /**
5314 * e1000_set_phy_mode - Set PHY to class A mode
5315 * @hw: Struct containing variables accessed by shared code
5316 *
5317 * Assumes the following operations will follow to enable the new class mode.
5318 * 1. Do a PHY soft reset
5319 * 2. Restart auto-negotiation or force link.
5320 */
5321 static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5322 {
5323 s32 ret_val;
5324 u16 eeprom_data;
5325
5326 if ((hw->mac_type == e1000_82545_rev_3) &&
5327 (hw->media_type == e1000_media_type_copper)) {
5328 ret_val =
5329 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5330 &eeprom_data);
5331 if (ret_val)
5332 return ret_val;
5333
5334 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5335 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5336 ret_val =
5337 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5338 0x000B);
5339 if (ret_val)
5340 return ret_val;
5341 ret_val =
5342 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5343 0x8104);
5344 if (ret_val)
5345 return ret_val;
5346
5347 hw->phy_reset_disable = false;
5348 }
5349 }
5350
5351 return E1000_SUCCESS;
5352 }
5353
5354 /**
5355 * e1000_set_d3_lplu_state - set d3 link power state
5356 * @hw: Struct containing variables accessed by shared code
5357 * @active: true to enable lplu false to disable lplu.
5358 *
5359 * This function sets the lplu state according to the active flag. When
5360 * activating lplu this function also disables smart speed and vise versa.
5361 * lplu will not be activated unless the device autonegotiation advertisement
5362 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5363 *
5364 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5365 * E1000_SUCCESS at any other case.
5366 */
5367 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5368 {
5369 s32 ret_val;
5370 u16 phy_data;
5371
5372 if (hw->phy_type != e1000_phy_igp)
5373 return E1000_SUCCESS;
5374
5375 /* During driver activity LPLU should not be used or it will attain link
5376 * from the lowest speeds starting from 10Mbps. The capability is used
5377 * for Dx transitions and states
5378 */
5379 if (hw->mac_type == e1000_82541_rev_2 ||
5380 hw->mac_type == e1000_82547_rev_2) {
5381 ret_val =
5382 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5383 if (ret_val)
5384 return ret_val;
5385 }
5386
5387 if (!active) {
5388 if (hw->mac_type == e1000_82541_rev_2 ||
5389 hw->mac_type == e1000_82547_rev_2) {
5390 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5391 ret_val =
5392 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5393 phy_data);
5394 if (ret_val)
5395 return ret_val;
5396 }
5397
5398 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
5399 * during Dx states where the power conservation is most
5400 * important. During driver activity we should enable
5401 * SmartSpeed, so performance is maintained.
5402 */
5403 if (hw->smart_speed == e1000_smart_speed_on) {
5404 ret_val =
5405 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5406 &phy_data);
5407 if (ret_val)
5408 return ret_val;
5409
5410 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5411 ret_val =
5412 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5413 phy_data);
5414 if (ret_val)
5415 return ret_val;
5416 } else if (hw->smart_speed == e1000_smart_speed_off) {
5417 ret_val =
5418 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5419 &phy_data);
5420 if (ret_val)
5421 return ret_val;
5422
5423 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5424 ret_val =
5425 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5426 phy_data);
5427 if (ret_val)
5428 return ret_val;
5429 }
5430 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5431 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
5432 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5433 if (hw->mac_type == e1000_82541_rev_2 ||
5434 hw->mac_type == e1000_82547_rev_2) {
5435 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5436 ret_val =
5437 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5438 phy_data);
5439 if (ret_val)
5440 return ret_val;
5441 }
5442
5443 /* When LPLU is enabled we should disable SmartSpeed */
5444 ret_val =
5445 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5446 &phy_data);
5447 if (ret_val)
5448 return ret_val;
5449
5450 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5451 ret_val =
5452 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5453 phy_data);
5454 if (ret_val)
5455 return ret_val;
5456 }
5457 return E1000_SUCCESS;
5458 }
5459
5460 /**
5461 * e1000_set_vco_speed
5462 * @hw: Struct containing variables accessed by shared code
5463 *
5464 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5465 */
5466 static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5467 {
5468 s32 ret_val;
5469 u16 default_page = 0;
5470 u16 phy_data;
5471
5472 switch (hw->mac_type) {
5473 case e1000_82545_rev_3:
5474 case e1000_82546_rev_3:
5475 break;
5476 default:
5477 return E1000_SUCCESS;
5478 }
5479
5480 /* Set PHY register 30, page 5, bit 8 to 0 */
5481
5482 ret_val =
5483 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5484 if (ret_val)
5485 return ret_val;
5486
5487 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5488 if (ret_val)
5489 return ret_val;
5490
5491 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5492 if (ret_val)
5493 return ret_val;
5494
5495 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5496 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5497 if (ret_val)
5498 return ret_val;
5499
5500 /* Set PHY register 30, page 4, bit 11 to 1 */
5501
5502 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5503 if (ret_val)
5504 return ret_val;
5505
5506 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5507 if (ret_val)
5508 return ret_val;
5509
5510 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5511 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5512 if (ret_val)
5513 return ret_val;
5514
5515 ret_val =
5516 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5517 if (ret_val)
5518 return ret_val;
5519
5520 return E1000_SUCCESS;
5521 }
5522
5523 /**
5524 * e1000_enable_mng_pass_thru - check for bmc pass through
5525 * @hw: Struct containing variables accessed by shared code
5526 *
5527 * Verifies the hardware needs to allow ARPs to be processed by the host
5528 * returns: - true/false
5529 */
5530 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
5531 {
5532 u32 manc;
5533
5534 if (hw->asf_firmware_present) {
5535 manc = er32(MANC);
5536
5537 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5538 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5539 return false;
5540 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5541 return true;
5542 }
5543 return false;
5544 }
5545
5546 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5547 {
5548 s32 ret_val;
5549 u16 mii_status_reg;
5550 u16 i;
5551
5552 /* Polarity reversal workaround for forced 10F/10H links. */
5553
5554 /* Disable the transmitter on the PHY */
5555
5556 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5557 if (ret_val)
5558 return ret_val;
5559 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5560 if (ret_val)
5561 return ret_val;
5562
5563 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5564 if (ret_val)
5565 return ret_val;
5566
5567 /* This loop will early-out if the NO link condition has been met. */
5568 for (i = PHY_FORCE_TIME; i > 0; i--) {
5569 /* Read the MII Status Register and wait for Link Status bit
5570 * to be clear.
5571 */
5572
5573 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5574 if (ret_val)
5575 return ret_val;
5576
5577 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5578 if (ret_val)
5579 return ret_val;
5580
5581 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5582 break;
5583 msleep(100);
5584 }
5585
5586 /* Recommended delay time after link has been lost */
5587 msleep(1000);
5588
5589 /* Now we will re-enable th transmitter on the PHY */
5590
5591 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5592 if (ret_val)
5593 return ret_val;
5594 msleep(50);
5595 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5596 if (ret_val)
5597 return ret_val;
5598 msleep(50);
5599 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5600 if (ret_val)
5601 return ret_val;
5602 msleep(50);
5603 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5604 if (ret_val)
5605 return ret_val;
5606
5607 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5608 if (ret_val)
5609 return ret_val;
5610
5611 /* This loop will early-out if the link condition has been met. */
5612 for (i = PHY_FORCE_TIME; i > 0; i--) {
5613 /* Read the MII Status Register and wait for Link Status bit
5614 * to be set.
5615 */
5616
5617 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5618 if (ret_val)
5619 return ret_val;
5620
5621 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5622 if (ret_val)
5623 return ret_val;
5624
5625 if (mii_status_reg & MII_SR_LINK_STATUS)
5626 break;
5627 msleep(100);
5628 }
5629 return E1000_SUCCESS;
5630 }
5631
5632 /**
5633 * e1000_get_auto_rd_done
5634 * @hw: Struct containing variables accessed by shared code
5635 *
5636 * Check for EEPROM Auto Read bit done.
5637 * returns: - E1000_ERR_RESET if fail to reset MAC
5638 * E1000_SUCCESS at any other case.
5639 */
5640 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5641 {
5642 msleep(5);
5643 return E1000_SUCCESS;
5644 }
5645
5646 /**
5647 * e1000_get_phy_cfg_done
5648 * @hw: Struct containing variables accessed by shared code
5649 *
5650 * Checks if the PHY configuration is done
5651 * returns: - E1000_ERR_RESET if fail to reset MAC
5652 * E1000_SUCCESS at any other case.
5653 */
5654 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5655 {
5656 msleep(10);
5657 return E1000_SUCCESS;
5658 }