root/drivers/net/ethernet/intel/igb/e1000_i210.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
   3 
   4 #ifndef _E1000_I210_H_
   5 #define _E1000_I210_H_
   6 
   7 s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
   8 void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
   9 s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data);
  10 s32 igb_read_invm_version(struct e1000_hw *hw,
  11                           struct e1000_fw_version *invm_ver);
  12 s32 igb_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data);
  13 s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data);
  14 s32 igb_init_nvm_params_i210(struct e1000_hw *hw);
  15 bool igb_get_flash_presence_i210(struct e1000_hw *hw);
  16 s32 igb_pll_workaround_i210(struct e1000_hw *hw);
  17 s32 igb_get_cfg_done_i210(struct e1000_hw *hw);
  18 
  19 #define E1000_STM_OPCODE                0xDB00
  20 #define E1000_EEPROM_FLASH_SIZE_WORD    0x11
  21 
  22 #define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \
  23         (u8)((invm_dword) & 0x7)
  24 #define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \
  25         (u8)(((invm_dword) & 0x0000FE00) >> 9)
  26 #define INVM_DWORD_TO_WORD_DATA(invm_dword) \
  27         (u16)(((invm_dword) & 0xFFFF0000) >> 16)
  28 
  29 enum E1000_INVM_STRUCTURE_TYPE {
  30         E1000_INVM_UNINITIALIZED_STRUCTURE              = 0x00,
  31         E1000_INVM_WORD_AUTOLOAD_STRUCTURE              = 0x01,
  32         E1000_INVM_CSR_AUTOLOAD_STRUCTURE               = 0x02,
  33         E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE      = 0x03,
  34         E1000_INVM_RSA_KEY_SHA256_STRUCTURE             = 0x04,
  35         E1000_INVM_INVALIDATED_STRUCTURE                = 0x0F,
  36 };
  37 
  38 #define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS   8
  39 #define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS     1
  40 #define E1000_INVM_ULT_BYTES_SIZE                       8
  41 #define E1000_INVM_RECORD_SIZE_IN_BYTES                 4
  42 #define E1000_INVM_VER_FIELD_ONE                        0x1FF8
  43 #define E1000_INVM_VER_FIELD_TWO                        0x7FE000
  44 #define E1000_INVM_IMGTYPE_FIELD                        0x1F800000
  45 
  46 #define E1000_INVM_MAJOR_MASK           0x3F0
  47 #define E1000_INVM_MINOR_MASK           0xF
  48 #define E1000_INVM_MAJOR_SHIFT          4
  49 
  50 #define ID_LED_DEFAULT_I210             ((ID_LED_OFF1_ON2  << 8) | \
  51                                          (ID_LED_DEF1_DEF2 <<  4) | \
  52                                          (ID_LED_OFF1_OFF2))
  53 #define ID_LED_DEFAULT_I210_SERDES      ((ID_LED_DEF1_DEF2 << 8) | \
  54                                          (ID_LED_DEF1_DEF2 <<  4) | \
  55                                          (ID_LED_OFF1_ON2))
  56 
  57 /* NVM offset defaults for i211 device */
  58 #define NVM_INIT_CTRL_2_DEFAULT_I211    0X7243
  59 #define NVM_INIT_CTRL_4_DEFAULT_I211    0x00C1
  60 #define NVM_LED_1_CFG_DEFAULT_I211      0x0184
  61 #define NVM_LED_0_2_CFG_DEFAULT_I211    0x200C
  62 
  63 /* PLL Defines */
  64 #define E1000_PCI_PMCSR                 0x44
  65 #define E1000_PCI_PMCSR_D3              0x03
  66 #define E1000_MAX_PLL_TRIES             5
  67 #define E1000_PHY_PLL_UNCONF            0xFF
  68 #define E1000_PHY_PLL_FREQ_PAGE         0xFC
  69 #define E1000_PHY_PLL_FREQ_REG          0x000E
  70 #define E1000_INVM_DEFAULT_AL           0x202F
  71 #define E1000_INVM_AUTOLOAD             0x0A
  72 #define E1000_INVM_PLL_WO_VAL           0x0010
  73 
  74 #endif