drivers/net/ethernet/intel/igb/e1000

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This source file includes following definitions.
igb_write_vfta_i350
igb_sgmii_uses_mdio_82575
igb_check_for_link_media_swap
igb_init_phy_params_82575
igb_init_nvm_params_82575
igb_init_mac_params_82575
igb_set_sfp_media_type_82575
igb_get_invariants_82575
igb_acquire_phy_82575
igb_release_phy_82575
igb_read_phy_reg_sgmii_82575
igb_write_phy_reg_sgmii_82575
igb_get_phy_id_82575
igb_phy_hw_reset_sgmii_82575
igb_set_d0_lplu_state_82575
igb_set_d0_lplu_state_82580
igb_set_d3_lplu_state_82580
igb_acquire_nvm_82575
igb_release_nvm_82575
igb_acquire_swfw_sync_82575
igb_release_swfw_sync_82575
igb_get_cfg_done_82575
igb_get_link_up_info_82575
igb_check_for_link_82575
igb_power_up_serdes_link_82575
igb_get_pcs_speed_and_duplex_82575
igb_shutdown_serdes_link_82575
igb_reset_hw_82575
igb_init_hw_82575
igb_setup_copper_link_82575
igb_setup_serdes_link_82575
igb_sgmii_active_82575
igb_reset_init_script_82575
igb_read_mac_addr_82575
igb_power_down_phy_copper_82575
igb_clear_hw_cntrs_82575
igb_rx_fifo_flush_82575
igb_set_pcie_completion_timeout
igb_vmdq_set_anti_spoofing_pf
igb_vmdq_set_loopback_pf
igb_vmdq_set_replication_pf
igb_read_phy_reg_82580
igb_write_phy_reg_82580
igb_reset_mdicnfg_82580
igb_reset_hw_82580
igb_rxpbs_adjust_82580
igb_validate_nvm_checksum_with_offset
igb_update_nvm_checksum_with_offset
igb_validate_nvm_checksum_82580
igb_update_nvm_checksum_82580
igb_validate_nvm_checksum_i350
igb_update_nvm_checksum_i350
__igb_access_emi_reg
igb_read_emi_reg
igb_set_eee_i350
igb_set_eee_i354
igb_get_eee_status_i354
igb_get_thermal_sensor_data_generic
igb_init_thermal_sensor_thresh_generic
   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
   3 
   4 /* e1000_82575
   5  * e1000_82576
   6  */
   7 
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9 
  10 #include <linux/types.h>
  11 #include <linux/if_ether.h>
  12 #include <linux/i2c.h>
  13 
  14 #include "e1000_mac.h"
  15 #include "e1000_82575.h"
  16 #include "e1000_i210.h"
  17 #include "igb.h"
  18 
  19 static s32  igb_get_invariants_82575(struct e1000_hw *);
  20 static s32  igb_acquire_phy_82575(struct e1000_hw *);
  21 static void igb_release_phy_82575(struct e1000_hw *);
  22 static s32  igb_acquire_nvm_82575(struct e1000_hw *);
  23 static void igb_release_nvm_82575(struct e1000_hw *);
  24 static s32  igb_check_for_link_82575(struct e1000_hw *);
  25 static s32  igb_get_cfg_done_82575(struct e1000_hw *);
  26 static s32  igb_init_hw_82575(struct e1000_hw *);
  27 static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
  28 static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
  29 static s32  igb_reset_hw_82575(struct e1000_hw *);
  30 static s32  igb_reset_hw_82580(struct e1000_hw *);
  31 static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
  32 static s32  igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
  33 static s32  igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
  34 static s32  igb_setup_copper_link_82575(struct e1000_hw *);
  35 static s32  igb_setup_serdes_link_82575(struct e1000_hw *);
  36 static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
  37 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
  38 static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
  39 static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
  40                                                  u16 *);
  41 static s32  igb_get_phy_id_82575(struct e1000_hw *);
  42 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
  43 static bool igb_sgmii_active_82575(struct e1000_hw *);
  44 static s32  igb_reset_init_script_82575(struct e1000_hw *);
  45 static s32  igb_read_mac_addr_82575(struct e1000_hw *);
  46 static s32  igb_set_pcie_completion_timeout(struct e1000_hw *hw);
  47 static s32  igb_reset_mdicnfg_82580(struct e1000_hw *hw);
  48 static s32  igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
  49 static s32  igb_update_nvm_checksum_82580(struct e1000_hw *hw);
  50 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
  51 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
  52 static const u16 e1000_82580_rxpbs_table[] = {
  53         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
  54 
  55 /* Due to a hw errata, if the host tries to  configure the VFTA register
  56  * while performing queries from the BMC or DMA, then the VFTA in some
  57  * cases won't be written.
  58  */
  59 
  60 /**
  61  *  igb_write_vfta_i350 - Write value to VLAN filter table
  62  *  @hw: pointer to the HW structure
  63  *  @offset: register offset in VLAN filter table
  64  *  @value: register value written to VLAN filter table
  65  *
  66  *  Writes value at the given offset in the register array which stores
  67  *  the VLAN filter table.
  68  **/
  69 static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
  70 {
  71         struct igb_adapter *adapter = hw->back;
  72         int i;
  73 
  74         for (i = 10; i--;)
  75                 array_wr32(E1000_VFTA, offset, value);
  76 
  77         wrfl();
  78         adapter->shadow_vfta[offset] = value;
  79 }
  80 
  81 /**
  82  *  igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
  83  *  @hw: pointer to the HW structure
  84  *
  85  *  Called to determine if the I2C pins are being used for I2C or as an
  86  *  external MDIO interface since the two options are mutually exclusive.
  87  **/
  88 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
  89 {
  90         u32 reg = 0;
  91         bool ext_mdio = false;
  92 
  93         switch (hw->mac.type) {
  94         case e1000_82575:
  95         case e1000_82576:
  96                 reg = rd32(E1000_MDIC);
  97                 ext_mdio = !!(reg & E1000_MDIC_DEST);
  98                 break;
  99         case e1000_82580:
 100         case e1000_i350:
 101         case e1000_i354:
 102         case e1000_i210:
 103         case e1000_i211:
 104                 reg = rd32(E1000_MDICNFG);
 105                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 106                 break;
 107         default:
 108                 break;
 109         }
 110         return ext_mdio;
 111 }
 112 
 113 /**
 114  *  igb_check_for_link_media_swap - Check which M88E1112 interface linked
 115  *  @hw: pointer to the HW structure
 116  *
 117  *  Poll the M88E1112 interfaces to see which interface achieved link.
 118  */
 119 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
 120 {
 121         struct e1000_phy_info *phy = &hw->phy;
 122         s32 ret_val;
 123         u16 data;
 124         u8 port = 0;
 125 
 126         /* Check the copper medium. */
 127         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 128         if (ret_val)
 129                 return ret_val;
 130 
 131         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
 132         if (ret_val)
 133                 return ret_val;
 134 
 135         if (data & E1000_M88E1112_STATUS_LINK)
 136                 port = E1000_MEDIA_PORT_COPPER;
 137 
 138         /* Check the other medium. */
 139         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
 140         if (ret_val)
 141                 return ret_val;
 142 
 143         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
 144         if (ret_val)
 145                 return ret_val;
 146 
 147 
 148         if (data & E1000_M88E1112_STATUS_LINK)
 149                 port = E1000_MEDIA_PORT_OTHER;
 150 
 151         /* Determine if a swap needs to happen. */
 152         if (port && (hw->dev_spec._82575.media_port != port)) {
 153                 hw->dev_spec._82575.media_port = port;
 154                 hw->dev_spec._82575.media_changed = true;
 155         }
 156 
 157         if (port == E1000_MEDIA_PORT_COPPER) {
 158                 /* reset page to 0 */
 159                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 160                 if (ret_val)
 161                         return ret_val;
 162                 igb_check_for_link_82575(hw);
 163         } else {
 164                 igb_check_for_link_82575(hw);
 165                 /* reset page to 0 */
 166                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 167                 if (ret_val)
 168                         return ret_val;
 169         }
 170 
 171         return 0;
 172 }
 173 
 174 /**
 175  *  igb_init_phy_params_82575 - Init PHY func ptrs.
 176  *  @hw: pointer to the HW structure
 177  **/
 178 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
 179 {
 180         struct e1000_phy_info *phy = &hw->phy;
 181         s32 ret_val = 0;
 182         u32 ctrl_ext;
 183 
 184         if (hw->phy.media_type != e1000_media_type_copper) {
 185                 phy->type = e1000_phy_none;
 186                 goto out;
 187         }
 188 
 189         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 190         phy->reset_delay_us     = 100;
 191 
 192         ctrl_ext = rd32(E1000_CTRL_EXT);
 193 
 194         if (igb_sgmii_active_82575(hw)) {
 195                 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
 196                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 197         } else {
 198                 phy->ops.reset = igb_phy_hw_reset;
 199                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 200         }
 201 
 202         wr32(E1000_CTRL_EXT, ctrl_ext);
 203         igb_reset_mdicnfg_82580(hw);
 204 
 205         if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
 206                 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
 207                 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
 208         } else {
 209                 switch (hw->mac.type) {
 210                 case e1000_82580:
 211                 case e1000_i350:
 212                 case e1000_i354:
 213                 case e1000_i210:
 214                 case e1000_i211:
 215                         phy->ops.read_reg = igb_read_phy_reg_82580;
 216                         phy->ops.write_reg = igb_write_phy_reg_82580;
 217                         break;
 218                 default:
 219                         phy->ops.read_reg = igb_read_phy_reg_igp;
 220                         phy->ops.write_reg = igb_write_phy_reg_igp;
 221                 }
 222         }
 223 
 224         /* set lan id */
 225         hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
 226                         E1000_STATUS_FUNC_SHIFT;
 227 
 228         /* Set phy->phy_addr and phy->id. */
 229         ret_val = igb_get_phy_id_82575(hw);
 230         if (ret_val)
 231                 return ret_val;
 232 
 233         /* Verify phy id and set remaining function pointers */
 234         switch (phy->id) {
 235         case M88E1543_E_PHY_ID:
 236         case M88E1512_E_PHY_ID:
 237         case I347AT4_E_PHY_ID:
 238         case M88E1112_E_PHY_ID:
 239         case M88E1111_I_PHY_ID:
 240                 phy->type               = e1000_phy_m88;
 241                 phy->ops.check_polarity = igb_check_polarity_m88;
 242                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 243                 if (phy->id != M88E1111_I_PHY_ID)
 244                         phy->ops.get_cable_length =
 245                                          igb_get_cable_length_m88_gen2;
 246                 else
 247                         phy->ops.get_cable_length = igb_get_cable_length_m88;
 248                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 249                 /* Check if this PHY is configured for media swap. */
 250                 if (phy->id == M88E1112_E_PHY_ID) {
 251                         u16 data;
 252 
 253                         ret_val = phy->ops.write_reg(hw,
 254                                                      E1000_M88E1112_PAGE_ADDR,
 255                                                      2);
 256                         if (ret_val)
 257                                 goto out;
 258 
 259                         ret_val = phy->ops.read_reg(hw,
 260                                                     E1000_M88E1112_MAC_CTRL_1,
 261                                                     &data);
 262                         if (ret_val)
 263                                 goto out;
 264 
 265                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 266                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 267                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 268                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 269                                 hw->mac.ops.check_for_link =
 270                                                 igb_check_for_link_media_swap;
 271                 }
 272                 if (phy->id == M88E1512_E_PHY_ID) {
 273                         ret_val = igb_initialize_M88E1512_phy(hw);
 274                         if (ret_val)
 275                                 goto out;
 276                 }
 277                 if (phy->id == M88E1543_E_PHY_ID) {
 278                         ret_val = igb_initialize_M88E1543_phy(hw);
 279                         if (ret_val)
 280                                 goto out;
 281                 }
 282                 break;
 283         case IGP03E1000_E_PHY_ID:
 284                 phy->type = e1000_phy_igp_3;
 285                 phy->ops.get_phy_info = igb_get_phy_info_igp;
 286                 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
 287                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
 288                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
 289                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
 290                 break;
 291         case I82580_I_PHY_ID:
 292         case I350_I_PHY_ID:
 293                 phy->type = e1000_phy_82580;
 294                 phy->ops.force_speed_duplex =
 295                                          igb_phy_force_speed_duplex_82580;
 296                 phy->ops.get_cable_length = igb_get_cable_length_82580;
 297                 phy->ops.get_phy_info = igb_get_phy_info_82580;
 298                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 299                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 300                 break;
 301         case I210_I_PHY_ID:
 302                 phy->type               = e1000_phy_i210;
 303                 phy->ops.check_polarity = igb_check_polarity_m88;
 304                 phy->ops.get_cfg_done   = igb_get_cfg_done_i210;
 305                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 306                 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
 307                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 308                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 309                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 310                 break;
 311         case BCM54616_E_PHY_ID:
 312                 phy->type = e1000_phy_bcm54616;
 313                 break;
 314         default:
 315                 ret_val = -E1000_ERR_PHY;
 316                 goto out;
 317         }
 318 
 319 out:
 320         return ret_val;
 321 }
 322 
 323 /**
 324  *  igb_init_nvm_params_82575 - Init NVM func ptrs.
 325  *  @hw: pointer to the HW structure
 326  **/
 327 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
 328 {
 329         struct e1000_nvm_info *nvm = &hw->nvm;
 330         u32 eecd = rd32(E1000_EECD);
 331         u16 size;
 332 
 333         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 334                      E1000_EECD_SIZE_EX_SHIFT);
 335 
 336         /* Added to a constant, "size" becomes the left-shift value
 337          * for setting word_size.
 338          */
 339         size += NVM_WORD_SIZE_BASE_SHIFT;
 340 
 341         /* Just in case size is out of range, cap it to the largest
 342          * EEPROM size supported
 343          */
 344         if (size > 15)
 345                 size = 15;
 346 
 347         nvm->word_size = BIT(size);
 348         nvm->opcode_bits = 8;
 349         nvm->delay_usec = 1;
 350 
 351         switch (nvm->override) {
 352         case e1000_nvm_override_spi_large:
 353                 nvm->page_size = 32;
 354                 nvm->address_bits = 16;
 355                 break;
 356         case e1000_nvm_override_spi_small:
 357                 nvm->page_size = 8;
 358                 nvm->address_bits = 8;
 359                 break;
 360         default:
 361                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 362                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 363                                     16 : 8;
 364                 break;
 365         }
 366         if (nvm->word_size == BIT(15))
 367                 nvm->page_size = 128;
 368 
 369         nvm->type = e1000_nvm_eeprom_spi;
 370 
 371         /* NVM Function Pointers */
 372         nvm->ops.acquire = igb_acquire_nvm_82575;
 373         nvm->ops.release = igb_release_nvm_82575;
 374         nvm->ops.write = igb_write_nvm_spi;
 375         nvm->ops.validate = igb_validate_nvm_checksum;
 376         nvm->ops.update = igb_update_nvm_checksum;
 377         if (nvm->word_size < BIT(15))
 378                 nvm->ops.read = igb_read_nvm_eerd;
 379         else
 380                 nvm->ops.read = igb_read_nvm_spi;
 381 
 382         /* override generic family function pointers for specific descendants */
 383         switch (hw->mac.type) {
 384         case e1000_82580:
 385                 nvm->ops.validate = igb_validate_nvm_checksum_82580;
 386                 nvm->ops.update = igb_update_nvm_checksum_82580;
 387                 break;
 388         case e1000_i354:
 389         case e1000_i350:
 390                 nvm->ops.validate = igb_validate_nvm_checksum_i350;
 391                 nvm->ops.update = igb_update_nvm_checksum_i350;
 392                 break;
 393         default:
 394                 break;
 395         }
 396 
 397         return 0;
 398 }
 399 
 400 /**
 401  *  igb_init_mac_params_82575 - Init MAC func ptrs.
 402  *  @hw: pointer to the HW structure
 403  **/
 404 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
 405 {
 406         struct e1000_mac_info *mac = &hw->mac;
 407         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 408 
 409         /* Set mta register count */
 410         mac->mta_reg_count = 128;
 411         /* Set uta register count */
 412         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 413         /* Set rar entry count */
 414         switch (mac->type) {
 415         case e1000_82576:
 416                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 417                 break;
 418         case e1000_82580:
 419                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 420                 break;
 421         case e1000_i350:
 422         case e1000_i354:
 423                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 424                 break;
 425         default:
 426                 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 427                 break;
 428         }
 429         /* reset */
 430         if (mac->type >= e1000_82580)
 431                 mac->ops.reset_hw = igb_reset_hw_82580;
 432         else
 433                 mac->ops.reset_hw = igb_reset_hw_82575;
 434 
 435         if (mac->type >= e1000_i210) {
 436                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
 437                 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
 438 
 439         } else {
 440                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
 441                 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
 442         }
 443 
 444         if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
 445                 mac->ops.write_vfta = igb_write_vfta_i350;
 446         else
 447                 mac->ops.write_vfta = igb_write_vfta;
 448 
 449         /* Set if part includes ASF firmware */
 450         mac->asf_firmware_present = true;
 451         /* Set if manageability features are enabled. */
 452         mac->arc_subsystem_valid =
 453                 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
 454                         ? true : false;
 455         /* enable EEE on i350 parts and later parts */
 456         if (mac->type >= e1000_i350)
 457                 dev_spec->eee_disable = false;
 458         else
 459                 dev_spec->eee_disable = true;
 460         /* Allow a single clear of the SW semaphore on I210 and newer */
 461         if (mac->type >= e1000_i210)
 462                 dev_spec->clear_semaphore_once = true;
 463         /* physical interface link setup */
 464         mac->ops.setup_physical_interface =
 465                 (hw->phy.media_type == e1000_media_type_copper)
 466                         ? igb_setup_copper_link_82575
 467                         : igb_setup_serdes_link_82575;
 468 
 469         if (mac->type == e1000_82580 || mac->type == e1000_i350) {
 470                 switch (hw->device_id) {
 471                 /* feature not supported on these id's */
 472                 case E1000_DEV_ID_DH89XXCC_SGMII:
 473                 case E1000_DEV_ID_DH89XXCC_SERDES:
 474                 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 475                 case E1000_DEV_ID_DH89XXCC_SFP:
 476                         break;
 477                 default:
 478                         hw->dev_spec._82575.mas_capable = true;
 479                         break;
 480                 }
 481         }
 482         return 0;
 483 }
 484 
 485 /**
 486  *  igb_set_sfp_media_type_82575 - derives SFP module media type.
 487  *  @hw: pointer to the HW structure
 488  *
 489  *  The media type is chosen based on SFP module.
 490  *  compatibility flags retrieved from SFP ID EEPROM.
 491  **/
 492 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
 493 {
 494         s32 ret_val = E1000_ERR_CONFIG;
 495         u32 ctrl_ext = 0;
 496         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 497         struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
 498         u8 tranceiver_type = 0;
 499         s32 timeout = 3;
 500 
 501         /* Turn I2C interface ON and power on sfp cage */
 502         ctrl_ext = rd32(E1000_CTRL_EXT);
 503         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
 504         wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
 505 
 506         wrfl();
 507 
 508         /* Read SFP module data */
 509         while (timeout) {
 510                 ret_val = igb_read_sfp_data_byte(hw,
 511                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
 512                         &tranceiver_type);
 513                 if (ret_val == 0)
 514                         break;
 515                 msleep(100);
 516                 timeout--;
 517         }
 518         if (ret_val != 0)
 519                 goto out;
 520 
 521         ret_val = igb_read_sfp_data_byte(hw,
 522                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
 523                         (u8 *)eth_flags);
 524         if (ret_val != 0)
 525                 goto out;
 526 
 527         /* Check if there is some SFP module plugged and powered */
 528         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
 529             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
 530                 dev_spec->module_plugged = true;
 531                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
 532                         hw->phy.media_type = e1000_media_type_internal_serdes;
 533                 } else if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) {
 534                         dev_spec->sgmii_active = true;
 535                         hw->phy.media_type = e1000_media_type_internal_serdes;
 536                 } else if (eth_flags->e1000_base_t) {
 537                         dev_spec->sgmii_active = true;
 538                         hw->phy.media_type = e1000_media_type_copper;
 539                 } else {
 540                         hw->phy.media_type = e1000_media_type_unknown;
 541                         hw_dbg("PHY module has not been recognized\n");
 542                         goto out;
 543                 }
 544         } else {
 545                 hw->phy.media_type = e1000_media_type_unknown;
 546         }
 547         ret_val = 0;
 548 out:
 549         /* Restore I2C interface setting */
 550         wr32(E1000_CTRL_EXT, ctrl_ext);
 551         return ret_val;
 552 }
 553 
 554 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
 555 {
 556         struct e1000_mac_info *mac = &hw->mac;
 557         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 558         s32 ret_val;
 559         u32 ctrl_ext = 0;
 560         u32 link_mode = 0;
 561 
 562         switch (hw->device_id) {
 563         case E1000_DEV_ID_82575EB_COPPER:
 564         case E1000_DEV_ID_82575EB_FIBER_SERDES:
 565         case E1000_DEV_ID_82575GB_QUAD_COPPER:
 566                 mac->type = e1000_82575;
 567                 break;
 568         case E1000_DEV_ID_82576:
 569         case E1000_DEV_ID_82576_NS:
 570         case E1000_DEV_ID_82576_NS_SERDES:
 571         case E1000_DEV_ID_82576_FIBER:
 572         case E1000_DEV_ID_82576_SERDES:
 573         case E1000_DEV_ID_82576_QUAD_COPPER:
 574         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
 575         case E1000_DEV_ID_82576_SERDES_QUAD:
 576                 mac->type = e1000_82576;
 577                 break;
 578         case E1000_DEV_ID_82580_COPPER:
 579         case E1000_DEV_ID_82580_FIBER:
 580         case E1000_DEV_ID_82580_QUAD_FIBER:
 581         case E1000_DEV_ID_82580_SERDES:
 582         case E1000_DEV_ID_82580_SGMII:
 583         case E1000_DEV_ID_82580_COPPER_DUAL:
 584         case E1000_DEV_ID_DH89XXCC_SGMII:
 585         case E1000_DEV_ID_DH89XXCC_SERDES:
 586         case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 587         case E1000_DEV_ID_DH89XXCC_SFP:
 588                 mac->type = e1000_82580;
 589                 break;
 590         case E1000_DEV_ID_I350_COPPER:
 591         case E1000_DEV_ID_I350_FIBER:
 592         case E1000_DEV_ID_I350_SERDES:
 593         case E1000_DEV_ID_I350_SGMII:
 594                 mac->type = e1000_i350;
 595                 break;
 596         case E1000_DEV_ID_I210_COPPER:
 597         case E1000_DEV_ID_I210_FIBER:
 598         case E1000_DEV_ID_I210_SERDES:
 599         case E1000_DEV_ID_I210_SGMII:
 600         case E1000_DEV_ID_I210_COPPER_FLASHLESS:
 601         case E1000_DEV_ID_I210_SERDES_FLASHLESS:
 602                 mac->type = e1000_i210;
 603                 break;
 604         case E1000_DEV_ID_I211_COPPER:
 605                 mac->type = e1000_i211;
 606                 break;
 607         case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
 608         case E1000_DEV_ID_I354_SGMII:
 609         case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
 610                 mac->type = e1000_i354;
 611                 break;
 612         default:
 613                 return -E1000_ERR_MAC_INIT;
 614         }
 615 
 616         /* Set media type */
 617         /* The 82575 uses bits 22:23 for link mode. The mode can be changed
 618          * based on the EEPROM. We cannot rely upon device ID. There
 619          * is no distinguishable difference between fiber and internal
 620          * SerDes mode on the 82575. There can be an external PHY attached
 621          * on the SGMII interface. For this, we'll set sgmii_active to true.
 622          */
 623         hw->phy.media_type = e1000_media_type_copper;
 624         dev_spec->sgmii_active = false;
 625         dev_spec->module_plugged = false;
 626 
 627         ctrl_ext = rd32(E1000_CTRL_EXT);
 628 
 629         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
 630         switch (link_mode) {
 631         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
 632                 hw->phy.media_type = e1000_media_type_internal_serdes;
 633                 break;
 634         case E1000_CTRL_EXT_LINK_MODE_SGMII:
 635                 /* Get phy control interface type set (MDIO vs. I2C)*/
 636                 if (igb_sgmii_uses_mdio_82575(hw)) {
 637                         hw->phy.media_type = e1000_media_type_copper;
 638                         dev_spec->sgmii_active = true;
 639                         break;
 640                 }
 641                 /* fall through - for I2C based SGMII */
 642         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
 643                 /* read media type from SFP EEPROM */
 644                 ret_val = igb_set_sfp_media_type_82575(hw);
 645                 if ((ret_val != 0) ||
 646                     (hw->phy.media_type == e1000_media_type_unknown)) {
 647                         /* If media type was not identified then return media
 648                          * type defined by the CTRL_EXT settings.
 649                          */
 650                         hw->phy.media_type = e1000_media_type_internal_serdes;
 651 
 652                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
 653                                 hw->phy.media_type = e1000_media_type_copper;
 654                                 dev_spec->sgmii_active = true;
 655                         }
 656 
 657                         break;
 658                 }
 659 
 660                 /* change current link mode setting */
 661                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
 662 
 663                 if (dev_spec->sgmii_active)
 664                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
 665                 else
 666                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
 667 
 668                 wr32(E1000_CTRL_EXT, ctrl_ext);
 669 
 670                 break;
 671         default:
 672                 break;
 673         }
 674 
 675         /* mac initialization and operations */
 676         ret_val = igb_init_mac_params_82575(hw);
 677         if (ret_val)
 678                 goto out;
 679 
 680         /* NVM initialization */
 681         ret_val = igb_init_nvm_params_82575(hw);
 682         switch (hw->mac.type) {
 683         case e1000_i210:
 684         case e1000_i211:
 685                 ret_val = igb_init_nvm_params_i210(hw);
 686                 break;
 687         default:
 688                 break;
 689         }
 690 
 691         if (ret_val)
 692                 goto out;
 693 
 694         /* if part supports SR-IOV then initialize mailbox parameters */
 695         switch (mac->type) {
 696         case e1000_82576:
 697         case e1000_i350:
 698                 igb_init_mbx_params_pf(hw);
 699                 break;
 700         default:
 701                 break;
 702         }
 703 
 704         /* setup PHY parameters */
 705         ret_val = igb_init_phy_params_82575(hw);
 706 
 707 out:
 708         return ret_val;
 709 }
 710 
 711 /**
 712  *  igb_acquire_phy_82575 - Acquire rights to access PHY
 713  *  @hw: pointer to the HW structure
 714  *
 715  *  Acquire access rights to the correct PHY.  This is a
 716  *  function pointer entry point called by the api module.
 717  **/
 718 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
 719 {
 720         u16 mask = E1000_SWFW_PHY0_SM;
 721 
 722         if (hw->bus.func == E1000_FUNC_1)
 723                 mask = E1000_SWFW_PHY1_SM;
 724         else if (hw->bus.func == E1000_FUNC_2)
 725                 mask = E1000_SWFW_PHY2_SM;
 726         else if (hw->bus.func == E1000_FUNC_3)
 727                 mask = E1000_SWFW_PHY3_SM;
 728 
 729         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 730 }
 731 
 732 /**
 733  *  igb_release_phy_82575 - Release rights to access PHY
 734  *  @hw: pointer to the HW structure
 735  *
 736  *  A wrapper to release access rights to the correct PHY.  This is a
 737  *  function pointer entry point called by the api module.
 738  **/
 739 static void igb_release_phy_82575(struct e1000_hw *hw)
 740 {
 741         u16 mask = E1000_SWFW_PHY0_SM;
 742 
 743         if (hw->bus.func == E1000_FUNC_1)
 744                 mask = E1000_SWFW_PHY1_SM;
 745         else if (hw->bus.func == E1000_FUNC_2)
 746                 mask = E1000_SWFW_PHY2_SM;
 747         else if (hw->bus.func == E1000_FUNC_3)
 748                 mask = E1000_SWFW_PHY3_SM;
 749 
 750         hw->mac.ops.release_swfw_sync(hw, mask);
 751 }
 752 
 753 /**
 754  *  igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 755  *  @hw: pointer to the HW structure
 756  *  @offset: register offset to be read
 757  *  @data: pointer to the read data
 758  *
 759  *  Reads the PHY register at offset using the serial gigabit media independent
 760  *  interface and stores the retrieved information in data.
 761  **/
 762 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 763                                           u16 *data)
 764 {
 765         s32 ret_val = -E1000_ERR_PARAM;
 766 
 767         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 768                 hw_dbg("PHY Address %u is out of range\n", offset);
 769                 goto out;
 770         }
 771 
 772         ret_val = hw->phy.ops.acquire(hw);
 773         if (ret_val)
 774                 goto out;
 775 
 776         ret_val = igb_read_phy_reg_i2c(hw, offset, data);
 777 
 778         hw->phy.ops.release(hw);
 779 
 780 out:
 781         return ret_val;
 782 }
 783 
 784 /**
 785  *  igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 786  *  @hw: pointer to the HW structure
 787  *  @offset: register offset to write to
 788  *  @data: data to write at register offset
 789  *
 790  *  Writes the data to PHY register at the offset using the serial gigabit
 791  *  media independent interface.
 792  **/
 793 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 794                                            u16 data)
 795 {
 796         s32 ret_val = -E1000_ERR_PARAM;
 797 
 798 
 799         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 800                 hw_dbg("PHY Address %d is out of range\n", offset);
 801                 goto out;
 802         }
 803 
 804         ret_val = hw->phy.ops.acquire(hw);
 805         if (ret_val)
 806                 goto out;
 807 
 808         ret_val = igb_write_phy_reg_i2c(hw, offset, data);
 809 
 810         hw->phy.ops.release(hw);
 811 
 812 out:
 813         return ret_val;
 814 }
 815 
 816 /**
 817  *  igb_get_phy_id_82575 - Retrieve PHY addr and id
 818  *  @hw: pointer to the HW structure
 819  *
 820  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 821  *  sgmi interface.
 822  **/
 823 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
 824 {
 825         struct e1000_phy_info *phy = &hw->phy;
 826         s32  ret_val = 0;
 827         u16 phy_id;
 828         u32 ctrl_ext;
 829         u32 mdic;
 830 
 831         /* Extra read required for some PHY's on i354 */
 832         if (hw->mac.type == e1000_i354)
 833                 igb_get_phy_id(hw);
 834 
 835         /* For SGMII PHYs, we try the list of possible addresses until
 836          * we find one that works.  For non-SGMII PHYs
 837          * (e.g. integrated copper PHYs), an address of 1 should
 838          * work.  The result of this function should mean phy->phy_addr
 839          * and phy->id are set correctly.
 840          */
 841         if (!(igb_sgmii_active_82575(hw))) {
 842                 phy->addr = 1;
 843                 ret_val = igb_get_phy_id(hw);
 844                 goto out;
 845         }
 846 
 847         if (igb_sgmii_uses_mdio_82575(hw)) {
 848                 switch (hw->mac.type) {
 849                 case e1000_82575:
 850                 case e1000_82576:
 851                         mdic = rd32(E1000_MDIC);
 852                         mdic &= E1000_MDIC_PHY_MASK;
 853                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 854                         break;
 855                 case e1000_82580:
 856                 case e1000_i350:
 857                 case e1000_i354:
 858                 case e1000_i210:
 859                 case e1000_i211:
 860                         mdic = rd32(E1000_MDICNFG);
 861                         mdic &= E1000_MDICNFG_PHY_MASK;
 862                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 863                         break;
 864                 default:
 865                         ret_val = -E1000_ERR_PHY;
 866                         goto out;
 867                 }
 868                 ret_val = igb_get_phy_id(hw);
 869                 goto out;
 870         }
 871 
 872         /* Power on sgmii phy if it is disabled */
 873         ctrl_ext = rd32(E1000_CTRL_EXT);
 874         wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 875         wrfl();
 876         msleep(300);
 877 
 878         /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
 879          * Therefore, we need to test 1-7
 880          */
 881         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 882                 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 883                 if (ret_val == 0) {
 884                         hw_dbg("Vendor ID 0x%08X read at address %u\n",
 885                                phy_id, phy->addr);
 886                         /* At the time of this writing, The M88 part is
 887                          * the only supported SGMII PHY product.
 888                          */
 889                         if (phy_id == M88_VENDOR)
 890                                 break;
 891                 } else {
 892                         hw_dbg("PHY address %u was unreadable\n", phy->addr);
 893                 }
 894         }
 895 
 896         /* A valid PHY type couldn't be found. */
 897         if (phy->addr == 8) {
 898                 phy->addr = 0;
 899                 ret_val = -E1000_ERR_PHY;
 900                 goto out;
 901         } else {
 902                 ret_val = igb_get_phy_id(hw);
 903         }
 904 
 905         /* restore previous sfp cage power state */
 906         wr32(E1000_CTRL_EXT, ctrl_ext);
 907 
 908 out:
 909         return ret_val;
 910 }
 911 
 912 /**
 913  *  igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 914  *  @hw: pointer to the HW structure
 915  *
 916  *  Resets the PHY using the serial gigabit media independent interface.
 917  **/
 918 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 919 {
 920         struct e1000_phy_info *phy = &hw->phy;
 921         s32 ret_val;
 922 
 923         /* This isn't a true "hard" reset, but is the only reset
 924          * available to us at this time.
 925          */
 926 
 927         hw_dbg("Soft resetting SGMII attached PHY...\n");
 928 
 929         /* SFP documentation requires the following to configure the SPF module
 930          * to work on SGMII.  No further documentation is given.
 931          */
 932         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 933         if (ret_val)
 934                 goto out;
 935 
 936         ret_val = igb_phy_sw_reset(hw);
 937         if (ret_val)
 938                 goto out;
 939 
 940         if (phy->id == M88E1512_E_PHY_ID)
 941                 ret_val = igb_initialize_M88E1512_phy(hw);
 942         if (phy->id == M88E1543_E_PHY_ID)
 943                 ret_val = igb_initialize_M88E1543_phy(hw);
 944 out:
 945         return ret_val;
 946 }
 947 
 948 /**
 949  *  igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 950  *  @hw: pointer to the HW structure
 951  *  @active: true to enable LPLU, false to disable
 952  *
 953  *  Sets the LPLU D0 state according to the active flag.  When
 954  *  activating LPLU this function also disables smart speed
 955  *  and vice versa.  LPLU will not be activated unless the
 956  *  device autonegotiation advertisement meets standards of
 957  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 958  *  This is a function pointer entry point only called by
 959  *  PHY setup routines.
 960  **/
 961 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 962 {
 963         struct e1000_phy_info *phy = &hw->phy;
 964         s32 ret_val;
 965         u16 data;
 966 
 967         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 968         if (ret_val)
 969                 goto out;
 970 
 971         if (active) {
 972                 data |= IGP02E1000_PM_D0_LPLU;
 973                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 974                                                  data);
 975                 if (ret_val)
 976                         goto out;
 977 
 978                 /* When LPLU is enabled, we should disable SmartSpeed */
 979                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 980                                                 &data);
 981                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 982                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 983                                                  data);
 984                 if (ret_val)
 985                         goto out;
 986         } else {
 987                 data &= ~IGP02E1000_PM_D0_LPLU;
 988                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 989                                                  data);
 990                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 991                  * during Dx states where the power conservation is most
 992                  * important.  During driver activity we should enable
 993                  * SmartSpeed, so performance is maintained.
 994                  */
 995                 if (phy->smart_speed == e1000_smart_speed_on) {
 996                         ret_val = phy->ops.read_reg(hw,
 997                                         IGP01E1000_PHY_PORT_CONFIG, &data);
 998                         if (ret_val)
 999                                 goto out;
1000 
1001                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1002                         ret_val = phy->ops.write_reg(hw,
1003                                         IGP01E1000_PHY_PORT_CONFIG, data);
1004                         if (ret_val)
1005                                 goto out;
1006                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1007                         ret_val = phy->ops.read_reg(hw,
1008                                         IGP01E1000_PHY_PORT_CONFIG, &data);
1009                         if (ret_val)
1010                                 goto out;
1011 
1012                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1013                         ret_val = phy->ops.write_reg(hw,
1014                                         IGP01E1000_PHY_PORT_CONFIG, data);
1015                         if (ret_val)
1016                                 goto out;
1017                 }
1018         }
1019 
1020 out:
1021         return ret_val;
1022 }
1023 
1024 /**
1025  *  igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
1026  *  @hw: pointer to the HW structure
1027  *  @active: true to enable LPLU, false to disable
1028  *
1029  *  Sets the LPLU D0 state according to the active flag.  When
1030  *  activating LPLU this function also disables smart speed
1031  *  and vice versa.  LPLU will not be activated unless the
1032  *  device autonegotiation advertisement meets standards of
1033  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1034  *  This is a function pointer entry point only called by
1035  *  PHY setup routines.
1036  **/
1037 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1038 {
1039         struct e1000_phy_info *phy = &hw->phy;
1040         u16 data;
1041 
1042         data = rd32(E1000_82580_PHY_POWER_MGMT);
1043 
1044         if (active) {
1045                 data |= E1000_82580_PM_D0_LPLU;
1046 
1047                 /* When LPLU is enabled, we should disable SmartSpeed */
1048                 data &= ~E1000_82580_PM_SPD;
1049         } else {
1050                 data &= ~E1000_82580_PM_D0_LPLU;
1051 
1052                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1053                  * during Dx states where the power conservation is most
1054                  * important.  During driver activity we should enable
1055                  * SmartSpeed, so performance is maintained.
1056                  */
1057                 if (phy->smart_speed == e1000_smart_speed_on)
1058                         data |= E1000_82580_PM_SPD;
1059                 else if (phy->smart_speed == e1000_smart_speed_off)
1060                         data &= ~E1000_82580_PM_SPD; }
1061 
1062         wr32(E1000_82580_PHY_POWER_MGMT, data);
1063         return 0;
1064 }
1065 
1066 /**
1067  *  igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1068  *  @hw: pointer to the HW structure
1069  *  @active: boolean used to enable/disable lplu
1070  *
1071  *  Success returns 0, Failure returns 1
1072  *
1073  *  The low power link up (lplu) state is set to the power management level D3
1074  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
1075  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
1076  *  is used during Dx states where the power conservation is most important.
1077  *  During driver activity, SmartSpeed should be enabled so performance is
1078  *  maintained.
1079  **/
1080 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1081 {
1082         struct e1000_phy_info *phy = &hw->phy;
1083         u16 data;
1084 
1085         data = rd32(E1000_82580_PHY_POWER_MGMT);
1086 
1087         if (!active) {
1088                 data &= ~E1000_82580_PM_D3_LPLU;
1089                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1090                  * during Dx states where the power conservation is most
1091                  * important.  During driver activity we should enable
1092                  * SmartSpeed, so performance is maintained.
1093                  */
1094                 if (phy->smart_speed == e1000_smart_speed_on)
1095                         data |= E1000_82580_PM_SPD;
1096                 else if (phy->smart_speed == e1000_smart_speed_off)
1097                         data &= ~E1000_82580_PM_SPD;
1098         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1099                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1100                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1101                 data |= E1000_82580_PM_D3_LPLU;
1102                 /* When LPLU is enabled, we should disable SmartSpeed */
1103                 data &= ~E1000_82580_PM_SPD;
1104         }
1105 
1106         wr32(E1000_82580_PHY_POWER_MGMT, data);
1107         return 0;
1108 }
1109 
1110 /**
1111  *  igb_acquire_nvm_82575 - Request for access to EEPROM
1112  *  @hw: pointer to the HW structure
1113  *
1114  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
1115  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
1116  *  Return successful if access grant bit set, else clear the request for
1117  *  EEPROM access and return -E1000_ERR_NVM (-1).
1118  **/
1119 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1120 {
1121         s32 ret_val;
1122 
1123         ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1124         if (ret_val)
1125                 goto out;
1126 
1127         ret_val = igb_acquire_nvm(hw);
1128 
1129         if (ret_val)
1130                 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1131 
1132 out:
1133         return ret_val;
1134 }
1135 
1136 /**
1137  *  igb_release_nvm_82575 - Release exclusive access to EEPROM
1138  *  @hw: pointer to the HW structure
1139  *
1140  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1141  *  then release the semaphores acquired.
1142  **/
1143 static void igb_release_nvm_82575(struct e1000_hw *hw)
1144 {
1145         igb_release_nvm(hw);
1146         hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1147 }
1148 
1149 /**
1150  *  igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1151  *  @hw: pointer to the HW structure
1152  *  @mask: specifies which semaphore to acquire
1153  *
1154  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1155  *  will also specify which port we're acquiring the lock for.
1156  **/
1157 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1158 {
1159         u32 swfw_sync;
1160         u32 swmask = mask;
1161         u32 fwmask = mask << 16;
1162         s32 ret_val = 0;
1163         s32 i = 0, timeout = 200;
1164 
1165         while (i < timeout) {
1166                 if (igb_get_hw_semaphore(hw)) {
1167                         ret_val = -E1000_ERR_SWFW_SYNC;
1168                         goto out;
1169                 }
1170 
1171                 swfw_sync = rd32(E1000_SW_FW_SYNC);
1172                 if (!(swfw_sync & (fwmask | swmask)))
1173                         break;
1174 
1175                 /* Firmware currently using resource (fwmask)
1176                  * or other software thread using resource (swmask)
1177                  */
1178                 igb_put_hw_semaphore(hw);
1179                 mdelay(5);
1180                 i++;
1181         }
1182 
1183         if (i == timeout) {
1184                 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1185                 ret_val = -E1000_ERR_SWFW_SYNC;
1186                 goto out;
1187         }
1188 
1189         swfw_sync |= swmask;
1190         wr32(E1000_SW_FW_SYNC, swfw_sync);
1191 
1192         igb_put_hw_semaphore(hw);
1193 
1194 out:
1195         return ret_val;
1196 }
1197 
1198 /**
1199  *  igb_release_swfw_sync_82575 - Release SW/FW semaphore
1200  *  @hw: pointer to the HW structure
1201  *  @mask: specifies which semaphore to acquire
1202  *
1203  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1204  *  will also specify which port we're releasing the lock for.
1205  **/
1206 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1207 {
1208         u32 swfw_sync;
1209 
1210         while (igb_get_hw_semaphore(hw) != 0)
1211                 ; /* Empty */
1212 
1213         swfw_sync = rd32(E1000_SW_FW_SYNC);
1214         swfw_sync &= ~mask;
1215         wr32(E1000_SW_FW_SYNC, swfw_sync);
1216 
1217         igb_put_hw_semaphore(hw);
1218 }
1219 
1220 /**
1221  *  igb_get_cfg_done_82575 - Read config done bit
1222  *  @hw: pointer to the HW structure
1223  *
1224  *  Read the management control register for the config done bit for
1225  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1226  *  to read the config done bit, so an error is *ONLY* logged and returns
1227  *  0.  If we were to return with error, EEPROM-less silicon
1228  *  would not be able to be reset or change link.
1229  **/
1230 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1231 {
1232         s32 timeout = PHY_CFG_TIMEOUT;
1233         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1234 
1235         if (hw->bus.func == 1)
1236                 mask = E1000_NVM_CFG_DONE_PORT_1;
1237         else if (hw->bus.func == E1000_FUNC_2)
1238                 mask = E1000_NVM_CFG_DONE_PORT_2;
1239         else if (hw->bus.func == E1000_FUNC_3)
1240                 mask = E1000_NVM_CFG_DONE_PORT_3;
1241 
1242         while (timeout) {
1243                 if (rd32(E1000_EEMNGCTL) & mask)
1244                         break;
1245                 usleep_range(1000, 2000);
1246                 timeout--;
1247         }
1248         if (!timeout)
1249                 hw_dbg("MNG configuration cycle has not completed.\n");
1250 
1251         /* If EEPROM is not marked present, init the PHY manually */
1252         if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1253             (hw->phy.type == e1000_phy_igp_3))
1254                 igb_phy_init_script_igp3(hw);
1255 
1256         return 0;
1257 }
1258 
1259 /**
1260  *  igb_get_link_up_info_82575 - Get link speed/duplex info
1261  *  @hw: pointer to the HW structure
1262  *  @speed: stores the current speed
1263  *  @duplex: stores the current duplex
1264  *
1265  *  This is a wrapper function, if using the serial gigabit media independent
1266  *  interface, use PCS to retrieve the link speed and duplex information.
1267  *  Otherwise, use the generic function to get the link speed and duplex info.
1268  **/
1269 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1270                                         u16 *duplex)
1271 {
1272         s32 ret_val;
1273 
1274         if (hw->phy.media_type != e1000_media_type_copper)
1275                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1276                                                                duplex);
1277         else
1278                 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1279                                                                     duplex);
1280 
1281         return ret_val;
1282 }
1283 
1284 /**
1285  *  igb_check_for_link_82575 - Check for link
1286  *  @hw: pointer to the HW structure
1287  *
1288  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1289  *  use the generic interface for determining link.
1290  **/
1291 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1292 {
1293         s32 ret_val;
1294         u16 speed, duplex;
1295 
1296         if (hw->phy.media_type != e1000_media_type_copper) {
1297                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1298                                                              &duplex);
1299                 /* Use this flag to determine if link needs to be checked or
1300                  * not.  If  we have link clear the flag so that we do not
1301                  * continue to check for link.
1302                  */
1303                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1304 
1305                 /* Configure Flow Control now that Auto-Neg has completed.
1306                  * First, we need to restore the desired flow control
1307                  * settings because we may have had to re-autoneg with a
1308                  * different link partner.
1309                  */
1310                 ret_val = igb_config_fc_after_link_up(hw);
1311                 if (ret_val)
1312                         hw_dbg("Error configuring flow control\n");
1313         } else {
1314                 ret_val = igb_check_for_copper_link(hw);
1315         }
1316 
1317         return ret_val;
1318 }
1319 
1320 /**
1321  *  igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1322  *  @hw: pointer to the HW structure
1323  **/
1324 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1325 {
1326         u32 reg;
1327 
1328 
1329         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1330             !igb_sgmii_active_82575(hw))
1331                 return;
1332 
1333         /* Enable PCS to turn on link */
1334         reg = rd32(E1000_PCS_CFG0);
1335         reg |= E1000_PCS_CFG_PCS_EN;
1336         wr32(E1000_PCS_CFG0, reg);
1337 
1338         /* Power up the laser */
1339         reg = rd32(E1000_CTRL_EXT);
1340         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1341         wr32(E1000_CTRL_EXT, reg);
1342 
1343         /* flush the write to verify completion */
1344         wrfl();
1345         usleep_range(1000, 2000);
1346 }
1347 
1348 /**
1349  *  igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1350  *  @hw: pointer to the HW structure
1351  *  @speed: stores the current speed
1352  *  @duplex: stores the current duplex
1353  *
1354  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1355  *  duplex, then store the values in the pointers provided.
1356  **/
1357 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1358                                                 u16 *duplex)
1359 {
1360         struct e1000_mac_info *mac = &hw->mac;
1361         u32 pcs, status;
1362 
1363         /* Set up defaults for the return values of this function */
1364         mac->serdes_has_link = false;
1365         *speed = 0;
1366         *duplex = 0;
1367 
1368         /* Read the PCS Status register for link state. For non-copper mode,
1369          * the status register is not accurate. The PCS status register is
1370          * used instead.
1371          */
1372         pcs = rd32(E1000_PCS_LSTAT);
1373 
1374         /* The link up bit determines when link is up on autoneg. The sync ok
1375          * gets set once both sides sync up and agree upon link. Stable link
1376          * can be determined by checking for both link up and link sync ok
1377          */
1378         if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1379                 mac->serdes_has_link = true;
1380 
1381                 /* Detect and store PCS speed */
1382                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1383                         *speed = SPEED_1000;
1384                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1385                         *speed = SPEED_100;
1386                 else
1387                         *speed = SPEED_10;
1388 
1389                 /* Detect and store PCS duplex */
1390                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1391                         *duplex = FULL_DUPLEX;
1392                 else
1393                         *duplex = HALF_DUPLEX;
1394 
1395         /* Check if it is an I354 2.5Gb backplane connection. */
1396                 if (mac->type == e1000_i354) {
1397                         status = rd32(E1000_STATUS);
1398                         if ((status & E1000_STATUS_2P5_SKU) &&
1399                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1400                                 *speed = SPEED_2500;
1401                                 *duplex = FULL_DUPLEX;
1402                                 hw_dbg("2500 Mbs, ");
1403                                 hw_dbg("Full Duplex\n");
1404                         }
1405                 }
1406 
1407         }
1408 
1409         return 0;
1410 }
1411 
1412 /**
1413  *  igb_shutdown_serdes_link_82575 - Remove link during power down
1414  *  @hw: pointer to the HW structure
1415  *
1416  *  In the case of fiber serdes, shut down optics and PCS on driver unload
1417  *  when management pass thru is not enabled.
1418  **/
1419 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1420 {
1421         u32 reg;
1422 
1423         if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1424             igb_sgmii_active_82575(hw))
1425                 return;
1426 
1427         if (!igb_enable_mng_pass_thru(hw)) {
1428                 /* Disable PCS to turn off link */
1429                 reg = rd32(E1000_PCS_CFG0);
1430                 reg &= ~E1000_PCS_CFG_PCS_EN;
1431                 wr32(E1000_PCS_CFG0, reg);
1432 
1433                 /* shutdown the laser */
1434                 reg = rd32(E1000_CTRL_EXT);
1435                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1436                 wr32(E1000_CTRL_EXT, reg);
1437 
1438                 /* flush the write to verify completion */
1439                 wrfl();
1440                 usleep_range(1000, 2000);
1441         }
1442 }
1443 
1444 /**
1445  *  igb_reset_hw_82575 - Reset hardware
1446  *  @hw: pointer to the HW structure
1447  *
1448  *  This resets the hardware into a known state.  This is a
1449  *  function pointer entry point called by the api module.
1450  **/
1451 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1452 {
1453         u32 ctrl;
1454         s32 ret_val;
1455 
1456         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1457          * on the last TLP read/write transaction when MAC is reset.
1458          */
1459         ret_val = igb_disable_pcie_master(hw);
1460         if (ret_val)
1461                 hw_dbg("PCI-E Master disable polling has failed.\n");
1462 
1463         /* set the completion timeout for interface */
1464         ret_val = igb_set_pcie_completion_timeout(hw);
1465         if (ret_val)
1466                 hw_dbg("PCI-E Set completion timeout has failed.\n");
1467 
1468         hw_dbg("Masking off all interrupts\n");
1469         wr32(E1000_IMC, 0xffffffff);
1470 
1471         wr32(E1000_RCTL, 0);
1472         wr32(E1000_TCTL, E1000_TCTL_PSP);
1473         wrfl();
1474 
1475         usleep_range(10000, 20000);
1476 
1477         ctrl = rd32(E1000_CTRL);
1478 
1479         hw_dbg("Issuing a global reset to MAC\n");
1480         wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1481 
1482         ret_val = igb_get_auto_rd_done(hw);
1483         if (ret_val) {
1484                 /* When auto config read does not complete, do not
1485                  * return with an error. This can happen in situations
1486                  * where there is no eeprom and prevents getting link.
1487                  */
1488                 hw_dbg("Auto Read Done did not complete\n");
1489         }
1490 
1491         /* If EEPROM is not present, run manual init scripts */
1492         if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1493                 igb_reset_init_script_82575(hw);
1494 
1495         /* Clear any pending interrupt events. */
1496         wr32(E1000_IMC, 0xffffffff);
1497         rd32(E1000_ICR);
1498 
1499         /* Install any alternate MAC address into RAR0 */
1500         ret_val = igb_check_alt_mac_addr(hw);
1501 
1502         return ret_val;
1503 }
1504 
1505 /**
1506  *  igb_init_hw_82575 - Initialize hardware
1507  *  @hw: pointer to the HW structure
1508  *
1509  *  This inits the hardware readying it for operation.
1510  **/
1511 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1512 {
1513         struct e1000_mac_info *mac = &hw->mac;
1514         s32 ret_val;
1515         u16 i, rar_count = mac->rar_entry_count;
1516 
1517         if ((hw->mac.type >= e1000_i210) &&
1518             !(igb_get_flash_presence_i210(hw))) {
1519                 ret_val = igb_pll_workaround_i210(hw);
1520                 if (ret_val)
1521                         return ret_val;
1522         }
1523 
1524         /* Initialize identification LED */
1525         ret_val = igb_id_led_init(hw);
1526         if (ret_val) {
1527                 hw_dbg("Error initializing identification LED\n");
1528                 /* This is not fatal and we should not stop init due to this */
1529         }
1530 
1531         /* Disabling VLAN filtering */
1532         hw_dbg("Initializing the IEEE VLAN\n");
1533         igb_clear_vfta(hw);
1534 
1535         /* Setup the receive address */
1536         igb_init_rx_addrs(hw, rar_count);
1537 
1538         /* Zero out the Multicast HASH table */
1539         hw_dbg("Zeroing the MTA\n");
1540         for (i = 0; i < mac->mta_reg_count; i++)
1541                 array_wr32(E1000_MTA, i, 0);
1542 
1543         /* Zero out the Unicast HASH table */
1544         hw_dbg("Zeroing the UTA\n");
1545         for (i = 0; i < mac->uta_reg_count; i++)
1546                 array_wr32(E1000_UTA, i, 0);
1547 
1548         /* Setup link and flow control */
1549         ret_val = igb_setup_link(hw);
1550 
1551         /* Clear all of the statistics registers (clear on read).  It is
1552          * important that we do this after we have tried to establish link
1553          * because the symbol error count will increment wildly if there
1554          * is no link.
1555          */
1556         igb_clear_hw_cntrs_82575(hw);
1557         return ret_val;
1558 }
1559 
1560 /**
1561  *  igb_setup_copper_link_82575 - Configure copper link settings
1562  *  @hw: pointer to the HW structure
1563  *
1564  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1565  *  for link, once link is established calls to configure collision distance
1566  *  and flow control are called.
1567  **/
1568 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1569 {
1570         u32 ctrl;
1571         s32  ret_val;
1572         u32 phpm_reg;
1573 
1574         ctrl = rd32(E1000_CTRL);
1575         ctrl |= E1000_CTRL_SLU;
1576         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1577         wr32(E1000_CTRL, ctrl);
1578 
1579         /* Clear Go Link Disconnect bit on supported devices */
1580         switch (hw->mac.type) {
1581         case e1000_82580:
1582         case e1000_i350:
1583         case e1000_i210:
1584         case e1000_i211:
1585                 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1586                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1587                 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1588                 break;
1589         default:
1590                 break;
1591         }
1592 
1593         ret_val = igb_setup_serdes_link_82575(hw);
1594         if (ret_val)
1595                 goto out;
1596 
1597         if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1598                 /* allow time for SFP cage time to power up phy */
1599                 msleep(300);
1600 
1601                 ret_val = hw->phy.ops.reset(hw);
1602                 if (ret_val) {
1603                         hw_dbg("Error resetting the PHY.\n");
1604                         goto out;
1605                 }
1606         }
1607         switch (hw->phy.type) {
1608         case e1000_phy_i210:
1609         case e1000_phy_m88:
1610                 switch (hw->phy.id) {
1611                 case I347AT4_E_PHY_ID:
1612                 case M88E1112_E_PHY_ID:
1613                 case M88E1543_E_PHY_ID:
1614                 case M88E1512_E_PHY_ID:
1615                 case I210_I_PHY_ID:
1616                         ret_val = igb_copper_link_setup_m88_gen2(hw);
1617                         break;
1618                 default:
1619                         ret_val = igb_copper_link_setup_m88(hw);
1620                         break;
1621                 }
1622                 break;
1623         case e1000_phy_igp_3:
1624                 ret_val = igb_copper_link_setup_igp(hw);
1625                 break;
1626         case e1000_phy_82580:
1627                 ret_val = igb_copper_link_setup_82580(hw);
1628                 break;
1629         case e1000_phy_bcm54616:
1630                 ret_val = 0;
1631                 break;
1632         default:
1633                 ret_val = -E1000_ERR_PHY;
1634                 break;
1635         }
1636 
1637         if (ret_val)
1638                 goto out;
1639 
1640         ret_val = igb_setup_copper_link(hw);
1641 out:
1642         return ret_val;
1643 }
1644 
1645 /**
1646  *  igb_setup_serdes_link_82575 - Setup link for serdes
1647  *  @hw: pointer to the HW structure
1648  *
1649  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1650  *  used on copper connections where the serialized gigabit media independent
1651  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1652  *  for auto-negotiation or forces speed/duplex.
1653  **/
1654 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1655 {
1656         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1657         bool pcs_autoneg;
1658         s32 ret_val = 0;
1659         u16 data;
1660 
1661         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1662             !igb_sgmii_active_82575(hw))
1663                 return ret_val;
1664 
1665 
1666         /* On the 82575, SerDes loopback mode persists until it is
1667          * explicitly turned off or a power cycle is performed.  A read to
1668          * the register does not indicate its status.  Therefore, we ensure
1669          * loopback mode is disabled during initialization.
1670          */
1671         wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1672 
1673         /* power on the sfp cage if present and turn on I2C */
1674         ctrl_ext = rd32(E1000_CTRL_EXT);
1675         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1676         ctrl_ext |= E1000_CTRL_I2C_ENA;
1677         wr32(E1000_CTRL_EXT, ctrl_ext);
1678 
1679         ctrl_reg = rd32(E1000_CTRL);
1680         ctrl_reg |= E1000_CTRL_SLU;
1681 
1682         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1683                 /* set both sw defined pins */
1684                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1685 
1686                 /* Set switch control to serdes energy detect */
1687                 reg = rd32(E1000_CONNSW);
1688                 reg |= E1000_CONNSW_ENRGSRC;
1689                 wr32(E1000_CONNSW, reg);
1690         }
1691 
1692         reg = rd32(E1000_PCS_LCTL);
1693 
1694         /* default pcs_autoneg to the same setting as mac autoneg */
1695         pcs_autoneg = hw->mac.autoneg;
1696 
1697         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1698         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1699                 /* sgmii mode lets the phy handle forcing speed/duplex */
1700                 pcs_autoneg = true;
1701                 /* autoneg time out should be disabled for SGMII mode */
1702                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1703                 break;
1704         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1705                 /* disable PCS autoneg and support parallel detect only */
1706                 pcs_autoneg = false;
1707                 /* fall through */
1708         default:
1709                 if (hw->mac.type == e1000_82575 ||
1710                     hw->mac.type == e1000_82576) {
1711                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1712                         if (ret_val) {
1713                                 hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
1714                                 return ret_val;
1715                         }
1716 
1717                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1718                                 pcs_autoneg = false;
1719                 }
1720 
1721                 /* non-SGMII modes only supports a speed of 1000/Full for the
1722                  * link so it is best to just force the MAC and let the pcs
1723                  * link either autoneg or be forced to 1000/Full
1724                  */
1725                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1726                                 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1727 
1728                 /* set speed of 1000/Full if speed/duplex is forced */
1729                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1730                 break;
1731         }
1732 
1733         wr32(E1000_CTRL, ctrl_reg);
1734 
1735         /* New SerDes mode allows for forcing speed or autonegotiating speed
1736          * at 1gb. Autoneg should be default set by most drivers. This is the
1737          * mode that will be compatible with older link partners and switches.
1738          * However, both are supported by the hardware and some drivers/tools.
1739          */
1740         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1741                 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1742 
1743         if (pcs_autoneg) {
1744                 /* Set PCS register for autoneg */
1745                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1746                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1747 
1748                 /* Disable force flow control for autoneg */
1749                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1750 
1751                 /* Configure flow control advertisement for autoneg */
1752                 anadv_reg = rd32(E1000_PCS_ANADV);
1753                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1754                 switch (hw->fc.requested_mode) {
1755                 case e1000_fc_full:
1756                 case e1000_fc_rx_pause:
1757                         anadv_reg |= E1000_TXCW_ASM_DIR;
1758                         anadv_reg |= E1000_TXCW_PAUSE;
1759                         break;
1760                 case e1000_fc_tx_pause:
1761                         anadv_reg |= E1000_TXCW_ASM_DIR;
1762                         break;
1763                 default:
1764                         break;
1765                 }
1766                 wr32(E1000_PCS_ANADV, anadv_reg);
1767 
1768                 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1769         } else {
1770                 /* Set PCS register for forced link */
1771                 reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
1772 
1773                 /* Force flow control for forced link */
1774                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1775 
1776                 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1777         }
1778 
1779         wr32(E1000_PCS_LCTL, reg);
1780 
1781         if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1782                 igb_force_mac_fc(hw);
1783 
1784         return ret_val;
1785 }
1786 
1787 /**
1788  *  igb_sgmii_active_82575 - Return sgmii state
1789  *  @hw: pointer to the HW structure
1790  *
1791  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1792  *  which can be enabled for use in the embedded applications.  Simply
1793  *  return the current state of the sgmii interface.
1794  **/
1795 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1796 {
1797         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1798         return dev_spec->sgmii_active;
1799 }
1800 
1801 /**
1802  *  igb_reset_init_script_82575 - Inits HW defaults after reset
1803  *  @hw: pointer to the HW structure
1804  *
1805  *  Inits recommended HW defaults after a reset when there is no EEPROM
1806  *  detected. This is only for the 82575.
1807  **/
1808 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1809 {
1810         if (hw->mac.type == e1000_82575) {
1811                 hw_dbg("Running reset init script for 82575\n");
1812                 /* SerDes configuration via SERDESCTRL */
1813                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1814                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1815                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1816                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1817 
1818                 /* CCM configuration via CCMCTL register */
1819                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1820                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1821 
1822                 /* PCIe lanes configuration */
1823                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1824                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1825                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1826                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1827 
1828                 /* PCIe PLL Configuration */
1829                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1830                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1831                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1832         }
1833 
1834         return 0;
1835 }
1836 
1837 /**
1838  *  igb_read_mac_addr_82575 - Read device MAC address
1839  *  @hw: pointer to the HW structure
1840  **/
1841 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1842 {
1843         s32 ret_val = 0;
1844 
1845         /* If there's an alternate MAC address place it in RAR0
1846          * so that it will override the Si installed default perm
1847          * address.
1848          */
1849         ret_val = igb_check_alt_mac_addr(hw);
1850         if (ret_val)
1851                 goto out;
1852 
1853         ret_val = igb_read_mac_addr(hw);
1854 
1855 out:
1856         return ret_val;
1857 }
1858 
1859 /**
1860  * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1861  * @hw: pointer to the HW structure
1862  *
1863  * In the case of a PHY power down to save power, or to turn off link during a
1864  * driver unload, or wake on lan is not enabled, remove the link.
1865  **/
1866 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1867 {
1868         /* If the management interface is not enabled, then power down */
1869         if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1870                 igb_power_down_phy_copper(hw);
1871 }
1872 
1873 /**
1874  *  igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1875  *  @hw: pointer to the HW structure
1876  *
1877  *  Clears the hardware counters by reading the counter registers.
1878  **/
1879 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1880 {
1881         igb_clear_hw_cntrs_base(hw);
1882 
1883         rd32(E1000_PRC64);
1884         rd32(E1000_PRC127);
1885         rd32(E1000_PRC255);
1886         rd32(E1000_PRC511);
1887         rd32(E1000_PRC1023);
1888         rd32(E1000_PRC1522);
1889         rd32(E1000_PTC64);
1890         rd32(E1000_PTC127);
1891         rd32(E1000_PTC255);
1892         rd32(E1000_PTC511);
1893         rd32(E1000_PTC1023);
1894         rd32(E1000_PTC1522);
1895 
1896         rd32(E1000_ALGNERRC);
1897         rd32(E1000_RXERRC);
1898         rd32(E1000_TNCRS);
1899         rd32(E1000_CEXTERR);
1900         rd32(E1000_TSCTC);
1901         rd32(E1000_TSCTFC);
1902 
1903         rd32(E1000_MGTPRC);
1904         rd32(E1000_MGTPDC);
1905         rd32(E1000_MGTPTC);
1906 
1907         rd32(E1000_IAC);
1908         rd32(E1000_ICRXOC);
1909 
1910         rd32(E1000_ICRXPTC);
1911         rd32(E1000_ICRXATC);
1912         rd32(E1000_ICTXPTC);
1913         rd32(E1000_ICTXATC);
1914         rd32(E1000_ICTXQEC);
1915         rd32(E1000_ICTXQMTC);
1916         rd32(E1000_ICRXDMTC);
1917 
1918         rd32(E1000_CBTMPC);
1919         rd32(E1000_HTDPMC);
1920         rd32(E1000_CBRMPC);
1921         rd32(E1000_RPTHC);
1922         rd32(E1000_HGPTC);
1923         rd32(E1000_HTCBDPC);
1924         rd32(E1000_HGORCL);
1925         rd32(E1000_HGORCH);
1926         rd32(E1000_HGOTCL);
1927         rd32(E1000_HGOTCH);
1928         rd32(E1000_LENERRS);
1929 
1930         /* This register should not be read in copper configurations */
1931         if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1932             igb_sgmii_active_82575(hw))
1933                 rd32(E1000_SCVPC);
1934 }
1935 
1936 /**
1937  *  igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1938  *  @hw: pointer to the HW structure
1939  *
1940  *  After rx enable if manageability is enabled then there is likely some
1941  *  bad data at the start of the fifo and possibly in the DMA fifo. This
1942  *  function clears the fifos and flushes any packets that came in as rx was
1943  *  being enabled.
1944  **/
1945 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1946 {
1947         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1948         int i, ms_wait;
1949 
1950         /* disable IPv6 options as per hardware errata */
1951         rfctl = rd32(E1000_RFCTL);
1952         rfctl |= E1000_RFCTL_IPV6_EX_DIS;
1953         wr32(E1000_RFCTL, rfctl);
1954 
1955         if (hw->mac.type != e1000_82575 ||
1956             !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1957                 return;
1958 
1959         /* Disable all RX queues */
1960         for (i = 0; i < 4; i++) {
1961                 rxdctl[i] = rd32(E1000_RXDCTL(i));
1962                 wr32(E1000_RXDCTL(i),
1963                      rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1964         }
1965         /* Poll all queues to verify they have shut down */
1966         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1967                 usleep_range(1000, 2000);
1968                 rx_enabled = 0;
1969                 for (i = 0; i < 4; i++)
1970                         rx_enabled |= rd32(E1000_RXDCTL(i));
1971                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1972                         break;
1973         }
1974 
1975         if (ms_wait == 10)
1976                 hw_dbg("Queue disable timed out after 10ms\n");
1977 
1978         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1979          * incoming packets are rejected.  Set enable and wait 2ms so that
1980          * any packet that was coming in as RCTL.EN was set is flushed
1981          */
1982         wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1983 
1984         rlpml = rd32(E1000_RLPML);
1985         wr32(E1000_RLPML, 0);
1986 
1987         rctl = rd32(E1000_RCTL);
1988         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1989         temp_rctl |= E1000_RCTL_LPE;
1990 
1991         wr32(E1000_RCTL, temp_rctl);
1992         wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1993         wrfl();
1994         usleep_range(2000, 3000);
1995 
1996         /* Enable RX queues that were previously enabled and restore our
1997          * previous state
1998          */
1999         for (i = 0; i < 4; i++)
2000                 wr32(E1000_RXDCTL(i), rxdctl[i]);
2001         wr32(E1000_RCTL, rctl);
2002         wrfl();
2003 
2004         wr32(E1000_RLPML, rlpml);
2005         wr32(E1000_RFCTL, rfctl);
2006 
2007         /* Flush receive errors generated by workaround */
2008         rd32(E1000_ROC);
2009         rd32(E1000_RNBC);
2010         rd32(E1000_MPC);
2011 }
2012 
2013 /**
2014  *  igb_set_pcie_completion_timeout - set pci-e completion timeout
2015  *  @hw: pointer to the HW structure
2016  *
2017  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2018  *  however the hardware default for these parts is 500us to 1ms which is less
2019  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2020  *  increase the value to either 10ms to 200ms for capability version 1 config,
2021  *  or 16ms to 55ms for version 2.
2022  **/
2023 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
2024 {
2025         u32 gcr = rd32(E1000_GCR);
2026         s32 ret_val = 0;
2027         u16 pcie_devctl2;
2028 
2029         /* only take action if timeout value is defaulted to 0 */
2030         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2031                 goto out;
2032 
2033         /* if capabilities version is type 1 we can write the
2034          * timeout of 10ms to 200ms through the GCR register
2035          */
2036         if (!(gcr & E1000_GCR_CAP_VER2)) {
2037                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2038                 goto out;
2039         }
2040 
2041         /* for version 2 capabilities we need to write the config space
2042          * directly in order to set the completion timeout value for
2043          * 16ms to 55ms
2044          */
2045         ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2046                                         &pcie_devctl2);
2047         if (ret_val)
2048                 goto out;
2049 
2050         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2051 
2052         ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2053                                          &pcie_devctl2);
2054 out:
2055         /* disable completion timeout resend */
2056         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2057 
2058         wr32(E1000_GCR, gcr);
2059         return ret_val;
2060 }
2061 
2062 /**
2063  *  igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2064  *  @hw: pointer to the hardware struct
2065  *  @enable: state to enter, either enabled or disabled
2066  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2067  *
2068  *  enables/disables L2 switch anti-spoofing functionality.
2069  **/
2070 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2071 {
2072         u32 reg_val, reg_offset;
2073 
2074         switch (hw->mac.type) {
2075         case e1000_82576:
2076                 reg_offset = E1000_DTXSWC;
2077                 break;
2078         case e1000_i350:
2079         case e1000_i354:
2080                 reg_offset = E1000_TXSWC;
2081                 break;
2082         default:
2083                 return;
2084         }
2085 
2086         reg_val = rd32(reg_offset);
2087         if (enable) {
2088                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2089                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2090                 /* The PF can spoof - it has to in order to
2091                  * support emulation mode NICs
2092                  */
2093                 reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS));
2094         } else {
2095                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2096                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2097         }
2098         wr32(reg_offset, reg_val);
2099 }
2100 
2101 /**
2102  *  igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2103  *  @hw: pointer to the hardware struct
2104  *  @enable: state to enter, either enabled or disabled
2105  *
2106  *  enables/disables L2 switch loopback functionality.
2107  **/
2108 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2109 {
2110         u32 dtxswc;
2111 
2112         switch (hw->mac.type) {
2113         case e1000_82576:
2114                 dtxswc = rd32(E1000_DTXSWC);
2115                 if (enable)
2116                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2117                 else
2118                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2119                 wr32(E1000_DTXSWC, dtxswc);
2120                 break;
2121         case e1000_i354:
2122         case e1000_i350:
2123                 dtxswc = rd32(E1000_TXSWC);
2124                 if (enable)
2125                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2126                 else
2127                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2128                 wr32(E1000_TXSWC, dtxswc);
2129                 break;
2130         default:
2131                 /* Currently no other hardware supports loopback */
2132                 break;
2133         }
2134 
2135 }
2136 
2137 /**
2138  *  igb_vmdq_set_replication_pf - enable or disable vmdq replication
2139  *  @hw: pointer to the hardware struct
2140  *  @enable: state to enter, either enabled or disabled
2141  *
2142  *  enables/disables replication of packets across multiple pools.
2143  **/
2144 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2145 {
2146         u32 vt_ctl = rd32(E1000_VT_CTL);
2147 
2148         if (enable)
2149                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2150         else
2151                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2152 
2153         wr32(E1000_VT_CTL, vt_ctl);
2154 }
2155 
2156 /**
2157  *  igb_read_phy_reg_82580 - Read 82580 MDI control register
2158  *  @hw: pointer to the HW structure
2159  *  @offset: register offset to be read
2160  *  @data: pointer to the read data
2161  *
2162  *  Reads the MDI control register in the PHY at offset and stores the
2163  *  information read to data.
2164  **/
2165 s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2166 {
2167         s32 ret_val;
2168 
2169         ret_val = hw->phy.ops.acquire(hw);
2170         if (ret_val)
2171                 goto out;
2172 
2173         ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2174 
2175         hw->phy.ops.release(hw);
2176 
2177 out:
2178         return ret_val;
2179 }
2180 
2181 /**
2182  *  igb_write_phy_reg_82580 - Write 82580 MDI control register
2183  *  @hw: pointer to the HW structure
2184  *  @offset: register offset to write to
2185  *  @data: data to write to register at offset
2186  *
2187  *  Writes data to MDI control register in the PHY at offset.
2188  **/
2189 s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2190 {
2191         s32 ret_val;
2192 
2193 
2194         ret_val = hw->phy.ops.acquire(hw);
2195         if (ret_val)
2196                 goto out;
2197 
2198         ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2199 
2200         hw->phy.ops.release(hw);
2201 
2202 out:
2203         return ret_val;
2204 }
2205 
2206 /**
2207  *  igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2208  *  @hw: pointer to the HW structure
2209  *
2210  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2211  *  the values found in the EEPROM.  This addresses an issue in which these
2212  *  bits are not restored from EEPROM after reset.
2213  **/
2214 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2215 {
2216         s32 ret_val = 0;
2217         u32 mdicnfg;
2218         u16 nvm_data = 0;
2219 
2220         if (hw->mac.type != e1000_82580)
2221                 goto out;
2222         if (!igb_sgmii_active_82575(hw))
2223                 goto out;
2224 
2225         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2226                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2227                                    &nvm_data);
2228         if (ret_val) {
2229                 hw_dbg("NVM Read Error\n");
2230                 goto out;
2231         }
2232 
2233         mdicnfg = rd32(E1000_MDICNFG);
2234         if (nvm_data & NVM_WORD24_EXT_MDIO)
2235                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2236         if (nvm_data & NVM_WORD24_COM_MDIO)
2237                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2238         wr32(E1000_MDICNFG, mdicnfg);
2239 out:
2240         return ret_val;
2241 }
2242 
2243 /**
2244  *  igb_reset_hw_82580 - Reset hardware
2245  *  @hw: pointer to the HW structure
2246  *
2247  *  This resets function or entire device (all ports, etc.)
2248  *  to a known state.
2249  **/
2250 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2251 {
2252         s32 ret_val = 0;
2253         /* BH SW mailbox bit in SW_FW_SYNC */
2254         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2255         u32 ctrl;
2256         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2257 
2258         hw->dev_spec._82575.global_device_reset = false;
2259 
2260         /* due to hw errata, global device reset doesn't always
2261          * work on 82580
2262          */
2263         if (hw->mac.type == e1000_82580)
2264                 global_device_reset = false;
2265 
2266         /* Get current control state. */
2267         ctrl = rd32(E1000_CTRL);
2268 
2269         /* Prevent the PCI-E bus from sticking if there is no TLP connection
2270          * on the last TLP read/write transaction when MAC is reset.
2271          */
2272         ret_val = igb_disable_pcie_master(hw);
2273         if (ret_val)
2274                 hw_dbg("PCI-E Master disable polling has failed.\n");
2275 
2276         hw_dbg("Masking off all interrupts\n");
2277         wr32(E1000_IMC, 0xffffffff);
2278         wr32(E1000_RCTL, 0);
2279         wr32(E1000_TCTL, E1000_TCTL_PSP);
2280         wrfl();
2281 
2282         usleep_range(10000, 11000);
2283 
2284         /* Determine whether or not a global dev reset is requested */
2285         if (global_device_reset &&
2286                 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2287                         global_device_reset = false;
2288 
2289         if (global_device_reset &&
2290                 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2291                 ctrl |= E1000_CTRL_DEV_RST;
2292         else
2293                 ctrl |= E1000_CTRL_RST;
2294 
2295         wr32(E1000_CTRL, ctrl);
2296         wrfl();
2297 
2298         /* Add delay to insure DEV_RST has time to complete */
2299         if (global_device_reset)
2300                 usleep_range(5000, 6000);
2301 
2302         ret_val = igb_get_auto_rd_done(hw);
2303         if (ret_val) {
2304                 /* When auto config read does not complete, do not
2305                  * return with an error. This can happen in situations
2306                  * where there is no eeprom and prevents getting link.
2307                  */
2308                 hw_dbg("Auto Read Done did not complete\n");
2309         }
2310 
2311         /* clear global device reset status bit */
2312         wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2313 
2314         /* Clear any pending interrupt events. */
2315         wr32(E1000_IMC, 0xffffffff);
2316         rd32(E1000_ICR);
2317 
2318         ret_val = igb_reset_mdicnfg_82580(hw);
2319         if (ret_val)
2320                 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2321 
2322         /* Install any alternate MAC address into RAR0 */
2323         ret_val = igb_check_alt_mac_addr(hw);
2324 
2325         /* Release semaphore */
2326         if (global_device_reset)
2327                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2328 
2329         return ret_val;
2330 }
2331 
2332 /**
2333  *  igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2334  *  @data: data received by reading RXPBS register
2335  *
2336  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2337  *  This function converts the retrieved value into the correct table value
2338  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2339  *  0x0 36  72 144   1   2   4   8  16
2340  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2341  */
2342 u16 igb_rxpbs_adjust_82580(u32 data)
2343 {
2344         u16 ret_val = 0;
2345 
2346         if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
2347                 ret_val = e1000_82580_rxpbs_table[data];
2348 
2349         return ret_val;
2350 }
2351 
2352 /**
2353  *  igb_validate_nvm_checksum_with_offset - Validate EEPROM
2354  *  checksum
2355  *  @hw: pointer to the HW structure
2356  *  @offset: offset in words of the checksum protected region
2357  *
2358  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2359  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2360  **/
2361 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2362                                                  u16 offset)
2363 {
2364         s32 ret_val = 0;
2365         u16 checksum = 0;
2366         u16 i, nvm_data;
2367 
2368         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2369                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2370                 if (ret_val) {
2371                         hw_dbg("NVM Read Error\n");
2372                         goto out;
2373                 }
2374                 checksum += nvm_data;
2375         }
2376 
2377         if (checksum != (u16) NVM_SUM) {
2378                 hw_dbg("NVM Checksum Invalid\n");
2379                 ret_val = -E1000_ERR_NVM;
2380                 goto out;
2381         }
2382 
2383 out:
2384         return ret_val;
2385 }
2386 
2387 /**
2388  *  igb_update_nvm_checksum_with_offset - Update EEPROM
2389  *  checksum
2390  *  @hw: pointer to the HW structure
2391  *  @offset: offset in words of the checksum protected region
2392  *
2393  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2394  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2395  *  value to the EEPROM.
2396  **/
2397 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2398 {
2399         s32 ret_val;
2400         u16 checksum = 0;
2401         u16 i, nvm_data;
2402 
2403         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2404                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2405                 if (ret_val) {
2406                         hw_dbg("NVM Read Error while updating checksum.\n");
2407                         goto out;
2408                 }
2409                 checksum += nvm_data;
2410         }
2411         checksum = (u16) NVM_SUM - checksum;
2412         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2413                                 &checksum);
2414         if (ret_val)
2415                 hw_dbg("NVM Write Error while updating checksum.\n");
2416 
2417 out:
2418         return ret_val;
2419 }
2420 
2421 /**
2422  *  igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2423  *  @hw: pointer to the HW structure
2424  *
2425  *  Calculates the EEPROM section checksum by reading/adding each word of
2426  *  the EEPROM and then verifies that the sum of the EEPROM is
2427  *  equal to 0xBABA.
2428  **/
2429 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2430 {
2431         s32 ret_val = 0;
2432         u16 eeprom_regions_count = 1;
2433         u16 j, nvm_data;
2434         u16 nvm_offset;
2435 
2436         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2437         if (ret_val) {
2438                 hw_dbg("NVM Read Error\n");
2439                 goto out;
2440         }
2441 
2442         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2443                 /* if checksums compatibility bit is set validate checksums
2444                  * for all 4 ports.
2445                  */
2446                 eeprom_regions_count = 4;
2447         }
2448 
2449         for (j = 0; j < eeprom_regions_count; j++) {
2450                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2451                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2452                                                                 nvm_offset);
2453                 if (ret_val != 0)
2454                         goto out;
2455         }
2456 
2457 out:
2458         return ret_val;
2459 }
2460 
2461 /**
2462  *  igb_update_nvm_checksum_82580 - Update EEPROM checksum
2463  *  @hw: pointer to the HW structure
2464  *
2465  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2466  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2467  *  checksum and writes the value to the EEPROM.
2468  **/
2469 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2470 {
2471         s32 ret_val;
2472         u16 j, nvm_data;
2473         u16 nvm_offset;
2474 
2475         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2476         if (ret_val) {
2477                 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
2478                 goto out;
2479         }
2480 
2481         if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2482                 /* set compatibility bit to validate checksums appropriately */
2483                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2484                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2485                                         &nvm_data);
2486                 if (ret_val) {
2487                         hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
2488                         goto out;
2489                 }
2490         }
2491 
2492         for (j = 0; j < 4; j++) {
2493                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2494                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2495                 if (ret_val)
2496                         goto out;
2497         }
2498 
2499 out:
2500         return ret_val;
2501 }
2502 
2503 /**
2504  *  igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2505  *  @hw: pointer to the HW structure
2506  *
2507  *  Calculates the EEPROM section checksum by reading/adding each word of
2508  *  the EEPROM and then verifies that the sum of the EEPROM is
2509  *  equal to 0xBABA.
2510  **/
2511 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2512 {
2513         s32 ret_val = 0;
2514         u16 j;
2515         u16 nvm_offset;
2516 
2517         for (j = 0; j < 4; j++) {
2518                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2519                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2520                                                                 nvm_offset);
2521                 if (ret_val != 0)
2522                         goto out;
2523         }
2524 
2525 out:
2526         return ret_val;
2527 }
2528 
2529 /**
2530  *  igb_update_nvm_checksum_i350 - Update EEPROM checksum
2531  *  @hw: pointer to the HW structure
2532  *
2533  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2534  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2535  *  checksum and writes the value to the EEPROM.
2536  **/
2537 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2538 {
2539         s32 ret_val = 0;
2540         u16 j;
2541         u16 nvm_offset;
2542 
2543         for (j = 0; j < 4; j++) {
2544                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2545                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2546                 if (ret_val != 0)
2547                         goto out;
2548         }
2549 
2550 out:
2551         return ret_val;
2552 }
2553 
2554 /**
2555  *  __igb_access_emi_reg - Read/write EMI register
2556  *  @hw: pointer to the HW structure
2557  *  @addr: EMI address to program
2558  *  @data: pointer to value to read/write from/to the EMI address
2559  *  @read: boolean flag to indicate read or write
2560  **/
2561 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2562                                   u16 *data, bool read)
2563 {
2564         s32 ret_val = 0;
2565 
2566         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2567         if (ret_val)
2568                 return ret_val;
2569 
2570         if (read)
2571                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2572         else
2573                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2574 
2575         return ret_val;
2576 }
2577 
2578 /**
2579  *  igb_read_emi_reg - Read Extended Management Interface register
2580  *  @hw: pointer to the HW structure
2581  *  @addr: EMI address to program
2582  *  @data: value to be read from the EMI address
2583  **/
2584 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2585 {
2586         return __igb_access_emi_reg(hw, addr, data, true);
2587 }
2588 
2589 /**
2590  *  igb_set_eee_i350 - Enable/disable EEE support
2591  *  @hw: pointer to the HW structure
2592  *  @adv1G: boolean flag enabling 1G EEE advertisement
2593  *  @adv100m: boolean flag enabling 100M EEE advertisement
2594  *
2595  *  Enable/disable EEE based on setting in dev_spec structure.
2596  *
2597  **/
2598 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2599 {
2600         u32 ipcnfg, eeer;
2601 
2602         if ((hw->mac.type < e1000_i350) ||
2603             (hw->phy.media_type != e1000_media_type_copper))
2604                 goto out;
2605         ipcnfg = rd32(E1000_IPCNFG);
2606         eeer = rd32(E1000_EEER);
2607 
2608         /* enable or disable per user setting */
2609         if (!(hw->dev_spec._82575.eee_disable)) {
2610                 u32 eee_su = rd32(E1000_EEE_SU);
2611 
2612                 if (adv100M)
2613                         ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2614                 else
2615                         ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2616 
2617                 if (adv1G)
2618                         ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2619                 else
2620                         ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2621 
2622                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2623                         E1000_EEER_LPI_FC);
2624 
2625                 /* This bit should not be set in normal operation. */
2626                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2627                         hw_dbg("LPI Clock Stop Bit should not be set!\n");
2628 
2629         } else {
2630                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2631                         E1000_IPCNFG_EEE_100M_AN);
2632                 eeer &= ~(E1000_EEER_TX_LPI_EN |
2633                         E1000_EEER_RX_LPI_EN |
2634                         E1000_EEER_LPI_FC);
2635         }
2636         wr32(E1000_IPCNFG, ipcnfg);
2637         wr32(E1000_EEER, eeer);
2638         rd32(E1000_IPCNFG);
2639         rd32(E1000_EEER);
2640 out:
2641 
2642         return 0;
2643 }
2644 
2645 /**
2646  *  igb_set_eee_i354 - Enable/disable EEE support
2647  *  @hw: pointer to the HW structure
2648  *  @adv1G: boolean flag enabling 1G EEE advertisement
2649  *  @adv100m: boolean flag enabling 100M EEE advertisement
2650  *
2651  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2652  *
2653  **/
2654 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2655 {
2656         struct e1000_phy_info *phy = &hw->phy;
2657         s32 ret_val = 0;
2658         u16 phy_data;
2659 
2660         if ((hw->phy.media_type != e1000_media_type_copper) ||
2661             ((phy->id != M88E1543_E_PHY_ID) &&
2662              (phy->id != M88E1512_E_PHY_ID)))
2663                 goto out;
2664 
2665         if (!hw->dev_spec._82575.eee_disable) {
2666                 /* Switch to PHY page 18. */
2667                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2668                 if (ret_val)
2669                         goto out;
2670 
2671                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2672                                             &phy_data);
2673                 if (ret_val)
2674                         goto out;
2675 
2676                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2677                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2678                                              phy_data);
2679                 if (ret_val)
2680                         goto out;
2681 
2682                 /* Return the PHY to page 0. */
2683                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2684                 if (ret_val)
2685                         goto out;
2686 
2687                 /* Turn on EEE advertisement. */
2688                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2689                                              E1000_EEE_ADV_DEV_I354,
2690                                              &phy_data);
2691                 if (ret_val)
2692                         goto out;
2693 
2694                 if (adv100M)
2695                         phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2696                 else
2697                         phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2698 
2699                 if (adv1G)
2700                         phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2701                 else
2702                         phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2703 
2704                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2705                                                 E1000_EEE_ADV_DEV_I354,
2706                                                 phy_data);
2707         } else {
2708                 /* Turn off EEE advertisement. */
2709                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2710                                              E1000_EEE_ADV_DEV_I354,
2711                                              &phy_data);
2712                 if (ret_val)
2713                         goto out;
2714 
2715                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2716                               E1000_EEE_ADV_1000_SUPPORTED);
2717                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2718                                               E1000_EEE_ADV_DEV_I354,
2719                                               phy_data);
2720         }
2721 
2722 out:
2723         return ret_val;
2724 }
2725 
2726 /**
2727  *  igb_get_eee_status_i354 - Get EEE status
2728  *  @hw: pointer to the HW structure
2729  *  @status: EEE status
2730  *
2731  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
2732  *  been received.
2733  **/
2734 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2735 {
2736         struct e1000_phy_info *phy = &hw->phy;
2737         s32 ret_val = 0;
2738         u16 phy_data;
2739 
2740         /* Check if EEE is supported on this device. */
2741         if ((hw->phy.media_type != e1000_media_type_copper) ||
2742             ((phy->id != M88E1543_E_PHY_ID) &&
2743              (phy->id != M88E1512_E_PHY_ID)))
2744                 goto out;
2745 
2746         ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2747                                      E1000_PCS_STATUS_DEV_I354,
2748                                      &phy_data);
2749         if (ret_val)
2750                 goto out;
2751 
2752         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2753                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2754 
2755 out:
2756         return ret_val;
2757 }
2758 
2759 static const u8 e1000_emc_temp_data[4] = {
2760         E1000_EMC_INTERNAL_DATA,
2761         E1000_EMC_DIODE1_DATA,
2762         E1000_EMC_DIODE2_DATA,
2763         E1000_EMC_DIODE3_DATA
2764 };
2765 static const u8 e1000_emc_therm_limit[4] = {
2766         E1000_EMC_INTERNAL_THERM_LIMIT,
2767         E1000_EMC_DIODE1_THERM_LIMIT,
2768         E1000_EMC_DIODE2_THERM_LIMIT,
2769         E1000_EMC_DIODE3_THERM_LIMIT
2770 };
2771 
2772 #ifdef CONFIG_IGB_HWMON
2773 /**
2774  *  igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2775  *  @hw: pointer to hardware structure
2776  *
2777  *  Updates the temperatures in mac.thermal_sensor_data
2778  **/
2779 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2780 {
2781         u16 ets_offset;
2782         u16 ets_cfg;
2783         u16 ets_sensor;
2784         u8  num_sensors;
2785         u8  sensor_index;
2786         u8  sensor_location;
2787         u8  i;
2788         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2789 
2790         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2791                 return E1000_NOT_IMPLEMENTED;
2792 
2793         data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2794 
2795         /* Return the internal sensor only if ETS is unsupported */
2796         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2797         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2798                 return 0;
2799 
2800         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2801         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2802             != NVM_ETS_TYPE_EMC)
2803                 return E1000_NOT_IMPLEMENTED;
2804 
2805         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2806         if (num_sensors > E1000_MAX_SENSORS)
2807                 num_sensors = E1000_MAX_SENSORS;
2808 
2809         for (i = 1; i < num_sensors; i++) {
2810                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2811                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2812                                 NVM_ETS_DATA_INDEX_SHIFT);
2813                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2814                                    NVM_ETS_DATA_LOC_SHIFT);
2815 
2816                 if (sensor_location != 0)
2817                         hw->phy.ops.read_i2c_byte(hw,
2818                                         e1000_emc_temp_data[sensor_index],
2819                                         E1000_I2C_THERMAL_SENSOR_ADDR,
2820                                         &data->sensor[i].temp);
2821         }
2822         return 0;
2823 }
2824 
2825 /**
2826  *  igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2827  *  @hw: pointer to hardware structure
2828  *
2829  *  Sets the thermal sensor thresholds according to the NVM map
2830  *  and save off the threshold and location values into mac.thermal_sensor_data
2831  **/
2832 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2833 {
2834         u16 ets_offset;
2835         u16 ets_cfg;
2836         u16 ets_sensor;
2837         u8  low_thresh_delta;
2838         u8  num_sensors;
2839         u8  sensor_index;
2840         u8  sensor_location;
2841         u8  therm_limit;
2842         u8  i;
2843         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2844 
2845         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2846                 return E1000_NOT_IMPLEMENTED;
2847 
2848         memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2849 
2850         data->sensor[0].location = 0x1;
2851         data->sensor[0].caution_thresh =
2852                 (rd32(E1000_THHIGHTC) & 0xFF);
2853         data->sensor[0].max_op_thresh =
2854                 (rd32(E1000_THLOWTC) & 0xFF);
2855 
2856         /* Return the internal sensor only if ETS is unsupported */
2857         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2858         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2859                 return 0;
2860 
2861         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2862         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2863             != NVM_ETS_TYPE_EMC)
2864                 return E1000_NOT_IMPLEMENTED;
2865 
2866         low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2867                             NVM_ETS_LTHRES_DELTA_SHIFT);
2868         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2869 
2870         for (i = 1; i <= num_sensors; i++) {
2871                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2872                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2873                                 NVM_ETS_DATA_INDEX_SHIFT);
2874                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2875                                    NVM_ETS_DATA_LOC_SHIFT);
2876                 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2877 
2878                 hw->phy.ops.write_i2c_byte(hw,
2879                         e1000_emc_therm_limit[sensor_index],
2880                         E1000_I2C_THERMAL_SENSOR_ADDR,
2881                         therm_limit);
2882 
2883                 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2884                         data->sensor[i].location = sensor_location;
2885                         data->sensor[i].caution_thresh = therm_limit;
2886                         data->sensor[i].max_op_thresh = therm_limit -
2887                                                         low_thresh_delta;
2888                 }
2889         }
2890         return 0;
2891 }
2892 
2893 #endif
2894 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2895         .init_hw              = igb_init_hw_82575,
2896         .check_for_link       = igb_check_for_link_82575,
2897         .rar_set              = igb_rar_set,
2898         .read_mac_addr        = igb_read_mac_addr_82575,
2899         .get_speed_and_duplex = igb_get_link_up_info_82575,
2900 #ifdef CONFIG_IGB_HWMON
2901         .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2902         .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2903 #endif
2904 };
2905 
2906 static const struct e1000_phy_operations e1000_phy_ops_82575 = {
2907         .acquire              = igb_acquire_phy_82575,
2908         .get_cfg_done         = igb_get_cfg_done_82575,
2909         .release              = igb_release_phy_82575,
2910         .write_i2c_byte       = igb_write_i2c_byte,
2911         .read_i2c_byte        = igb_read_i2c_byte,
2912 };
2913 
2914 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2915         .acquire              = igb_acquire_nvm_82575,
2916         .read                 = igb_read_nvm_eerd,
2917         .release              = igb_release_nvm_82575,
2918         .write                = igb_write_nvm_spi,
2919 };
2920 
2921 const struct e1000_info e1000_82575_info = {
2922         .get_invariants = igb_get_invariants_82575,
2923         .mac_ops = &e1000_mac_ops_82575,
2924         .phy_ops = &e1000_phy_ops_82575,
2925         .nvm_ops = &e1000_nvm_ops_82575,
2926 };
2927
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/intel/igb/e1000_82575.c

DEFINITIONS
