1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018 Intel Corporation */
3
4 #include <linux/pci.h>
5 #include <linux/delay.h>
6
7 #include "igc_mac.h"
8 #include "igc_hw.h"
9
10 /**
11 * igc_disable_pcie_master - Disables PCI-express master access
12 * @hw: pointer to the HW structure
13 *
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
16 * the master requests to be disabled.
17 *
18 * Disables PCI-Express master access and verifies there are no pending
19 * requests.
20 */
21 s32 igc_disable_pcie_master(struct igc_hw *hw)
22 {
23 s32 timeout = MASTER_DISABLE_TIMEOUT;
24 s32 ret_val = 0;
25 u32 ctrl;
26
27 ctrl = rd32(IGC_CTRL);
28 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
29 wr32(IGC_CTRL, ctrl);
30
31 while (timeout) {
32 if (!(rd32(IGC_STATUS) &
33 IGC_STATUS_GIO_MASTER_ENABLE))
34 break;
35 usleep_range(2000, 3000);
36 timeout--;
37 }
38
39 if (!timeout) {
40 hw_dbg("Master requests are pending.\n");
41 ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING;
42 goto out;
43 }
44
45 out:
46 return ret_val;
47 }
48
49 /**
50 * igc_init_rx_addrs - Initialize receive addresses
51 * @hw: pointer to the HW structure
52 * @rar_count: receive address registers
53 *
54 * Setup the receive address registers by setting the base receive address
55 * register to the devices MAC address and clearing all the other receive
56 * address registers to 0.
57 */
58 void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count)
59 {
60 u8 mac_addr[ETH_ALEN] = {0};
61 u32 i;
62
63 /* Setup the receive address */
64 hw_dbg("Programming MAC Address into RAR[0]\n");
65
66 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
67
68 /* Zero out the other (rar_entry_count - 1) receive addresses */
69 hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
70 for (i = 1; i < rar_count; i++)
71 hw->mac.ops.rar_set(hw, mac_addr, i);
72 }
73
74 /**
75 * igc_set_fc_watermarks - Set flow control high/low watermarks
76 * @hw: pointer to the HW structure
77 *
78 * Sets the flow control high/low threshold (watermark) registers. If
79 * flow control XON frame transmission is enabled, then set XON frame
80 * transmission as well.
81 */
82 static s32 igc_set_fc_watermarks(struct igc_hw *hw)
83 {
84 u32 fcrtl = 0, fcrth = 0;
85
86 /* Set the flow control receive threshold registers. Normally,
87 * these registers will be set to a default threshold that may be
88 * adjusted later by the driver's runtime code. However, if the
89 * ability to transmit pause frames is not enabled, then these
90 * registers will be set to 0.
91 */
92 if (hw->fc.current_mode & igc_fc_tx_pause) {
93 /* We need to set up the Receive Threshold high and low water
94 * marks as well as (optionally) enabling the transmission of
95 * XON frames.
96 */
97 fcrtl = hw->fc.low_water;
98 if (hw->fc.send_xon)
99 fcrtl |= IGC_FCRTL_XONE;
100
101 fcrth = hw->fc.high_water;
102 }
103 wr32(IGC_FCRTL, fcrtl);
104 wr32(IGC_FCRTH, fcrth);
105
106 return 0;
107 }
108
109 /**
110 * igc_setup_link - Setup flow control and link settings
111 * @hw: pointer to the HW structure
112 *
113 * Determines which flow control settings to use, then configures flow
114 * control. Calls the appropriate media-specific link configuration
115 * function. Assuming the adapter has a valid link partner, a valid link
116 * should be established. Assumes the hardware has previously been reset
117 * and the transmitter and receiver are not enabled.
118 */
119 s32 igc_setup_link(struct igc_hw *hw)
120 {
121 s32 ret_val = 0;
122
123 /* In the case of the phy reset being blocked, we already have a link.
124 * We do not need to set it up again.
125 */
126 if (igc_check_reset_block(hw))
127 goto out;
128
129 /* If requested flow control is set to default, set flow control
130 * to the both 'rx' and 'tx' pause frames.
131 */
132 if (hw->fc.requested_mode == igc_fc_default)
133 hw->fc.requested_mode = igc_fc_full;
134
135 /* We want to save off the original Flow Control configuration just
136 * in case we get disconnected and then reconnected into a different
137 * hub or switch with different Flow Control capabilities.
138 */
139 hw->fc.current_mode = hw->fc.requested_mode;
140
141 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
142
143 /* Call the necessary media_type subroutine to configure the link. */
144 ret_val = hw->mac.ops.setup_physical_interface(hw);
145 if (ret_val)
146 goto out;
147
148 /* Initialize the flow control address, type, and PAUSE timer
149 * registers to their default values. This is done even if flow
150 * control is disabled, because it does not hurt anything to
151 * initialize these registers.
152 */
153 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
154 wr32(IGC_FCT, FLOW_CONTROL_TYPE);
155 wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
156 wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
157
158 wr32(IGC_FCTTV, hw->fc.pause_time);
159
160 ret_val = igc_set_fc_watermarks(hw);
161
162 out:
163 return ret_val;
164 }
165
166 /**
167 * igc_force_mac_fc - Force the MAC's flow control settings
168 * @hw: pointer to the HW structure
169 *
170 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
171 * device control register to reflect the adapter settings. TFCE and RFCE
172 * need to be explicitly set by software when a copper PHY is used because
173 * autonegotiation is managed by the PHY rather than the MAC. Software must
174 * also configure these bits when link is forced on a fiber connection.
175 */
176 s32 igc_force_mac_fc(struct igc_hw *hw)
177 {
178 s32 ret_val = 0;
179 u32 ctrl;
180
181 ctrl = rd32(IGC_CTRL);
182
183 /* Because we didn't get link via the internal auto-negotiation
184 * mechanism (we either forced link or we got link via PHY
185 * auto-neg), we have to manually enable/disable transmit an
186 * receive flow control.
187 *
188 * The "Case" statement below enables/disable flow control
189 * according to the "hw->fc.current_mode" parameter.
190 *
191 * The possible values of the "fc" parameter are:
192 * 0: Flow control is completely disabled
193 * 1: Rx flow control is enabled (we can receive pause
194 * frames but not send pause frames).
195 * 2: Tx flow control is enabled (we can send pause frames
196 * frames but we do not receive pause frames).
197 * 3: Both Rx and TX flow control (symmetric) is enabled.
198 * other: No other values should be possible at this point.
199 */
200 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
201
202 switch (hw->fc.current_mode) {
203 case igc_fc_none:
204 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
205 break;
206 case igc_fc_rx_pause:
207 ctrl &= (~IGC_CTRL_TFCE);
208 ctrl |= IGC_CTRL_RFCE;
209 break;
210 case igc_fc_tx_pause:
211 ctrl &= (~IGC_CTRL_RFCE);
212 ctrl |= IGC_CTRL_TFCE;
213 break;
214 case igc_fc_full:
215 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
216 break;
217 default:
218 hw_dbg("Flow control param set incorrectly\n");
219 ret_val = -IGC_ERR_CONFIG;
220 goto out;
221 }
222
223 wr32(IGC_CTRL, ctrl);
224
225 out:
226 return ret_val;
227 }
228
229 /**
230 * igc_clear_hw_cntrs_base - Clear base hardware counters
231 * @hw: pointer to the HW structure
232 *
233 * Clears the base hardware counters by reading the counter registers.
234 */
235 void igc_clear_hw_cntrs_base(struct igc_hw *hw)
236 {
237 rd32(IGC_CRCERRS);
238 rd32(IGC_SYMERRS);
239 rd32(IGC_MPC);
240 rd32(IGC_SCC);
241 rd32(IGC_ECOL);
242 rd32(IGC_MCC);
243 rd32(IGC_LATECOL);
244 rd32(IGC_COLC);
245 rd32(IGC_DC);
246 rd32(IGC_SEC);
247 rd32(IGC_RLEC);
248 rd32(IGC_XONRXC);
249 rd32(IGC_XONTXC);
250 rd32(IGC_XOFFRXC);
251 rd32(IGC_XOFFTXC);
252 rd32(IGC_FCRUC);
253 rd32(IGC_GPRC);
254 rd32(IGC_BPRC);
255 rd32(IGC_MPRC);
256 rd32(IGC_GPTC);
257 rd32(IGC_GORCL);
258 rd32(IGC_GORCH);
259 rd32(IGC_GOTCL);
260 rd32(IGC_GOTCH);
261 rd32(IGC_RNBC);
262 rd32(IGC_RUC);
263 rd32(IGC_RFC);
264 rd32(IGC_ROC);
265 rd32(IGC_RJC);
266 rd32(IGC_TORL);
267 rd32(IGC_TORH);
268 rd32(IGC_TOTL);
269 rd32(IGC_TOTH);
270 rd32(IGC_TPR);
271 rd32(IGC_TPT);
272 rd32(IGC_MPTC);
273 rd32(IGC_BPTC);
274
275 rd32(IGC_PRC64);
276 rd32(IGC_PRC127);
277 rd32(IGC_PRC255);
278 rd32(IGC_PRC511);
279 rd32(IGC_PRC1023);
280 rd32(IGC_PRC1522);
281 rd32(IGC_PTC64);
282 rd32(IGC_PTC127);
283 rd32(IGC_PTC255);
284 rd32(IGC_PTC511);
285 rd32(IGC_PTC1023);
286 rd32(IGC_PTC1522);
287
288 rd32(IGC_ALGNERRC);
289 rd32(IGC_RXERRC);
290 rd32(IGC_TNCRS);
291 rd32(IGC_CEXTERR);
292 rd32(IGC_TSCTC);
293 rd32(IGC_TSCTFC);
294
295 rd32(IGC_MGTPRC);
296 rd32(IGC_MGTPDC);
297 rd32(IGC_MGTPTC);
298
299 rd32(IGC_IAC);
300 rd32(IGC_ICRXOC);
301
302 rd32(IGC_ICRXPTC);
303 rd32(IGC_ICRXATC);
304 rd32(IGC_ICTXPTC);
305 rd32(IGC_ICTXATC);
306 rd32(IGC_ICTXQEC);
307 rd32(IGC_ICTXQMTC);
308 rd32(IGC_ICRXDMTC);
309
310 rd32(IGC_CBTMPC);
311 rd32(IGC_HTDPMC);
312 rd32(IGC_CBRMPC);
313 rd32(IGC_RPTHC);
314 rd32(IGC_HGPTC);
315 rd32(IGC_HTCBDPC);
316 rd32(IGC_HGORCL);
317 rd32(IGC_HGORCH);
318 rd32(IGC_HGOTCL);
319 rd32(IGC_HGOTCH);
320 rd32(IGC_LENERRS);
321 }
322
323 /**
324 * igc_rar_set - Set receive address register
325 * @hw: pointer to the HW structure
326 * @addr: pointer to the receive address
327 * @index: receive address array register
328 *
329 * Sets the receive address array register at index to the address passed
330 * in by addr.
331 */
332 void igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index)
333 {
334 u32 rar_low, rar_high;
335
336 /* HW expects these in little endian so we reverse the byte order
337 * from network order (big endian) to little endian
338 */
339 rar_low = ((u32)addr[0] |
340 ((u32)addr[1] << 8) |
341 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
342
343 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
344
345 /* If MAC address zero, no need to set the AV bit */
346 if (rar_low || rar_high)
347 rar_high |= IGC_RAH_AV;
348
349 /* Some bridges will combine consecutive 32-bit writes into
350 * a single burst write, which will malfunction on some parts.
351 * The flushes avoid this.
352 */
353 wr32(IGC_RAL(index), rar_low);
354 wrfl();
355 wr32(IGC_RAH(index), rar_high);
356 wrfl();
357 }
358
359 /**
360 * igc_check_for_copper_link - Check for link (Copper)
361 * @hw: pointer to the HW structure
362 *
363 * Checks to see of the link status of the hardware has changed. If a
364 * change in link status has been detected, then we read the PHY registers
365 * to get the current speed/duplex if link exists.
366 */
367 s32 igc_check_for_copper_link(struct igc_hw *hw)
368 {
369 struct igc_mac_info *mac = &hw->mac;
370 s32 ret_val;
371 bool link;
372
373 /* We only want to go out to the PHY registers to see if Auto-Neg
374 * has completed and/or if our link status has changed. The
375 * get_link_status flag is set upon receiving a Link Status
376 * Change or Rx Sequence Error interrupt.
377 */
378 if (!mac->get_link_status) {
379 ret_val = 0;
380 goto out;
381 }
382
383 /* First we want to see if the MII Status Register reports
384 * link. If so, then we want to get the current speed/duplex
385 * of the PHY.
386 */
387 ret_val = igc_phy_has_link(hw, 1, 0, &link);
388 if (ret_val)
389 goto out;
390
391 if (!link)
392 goto out; /* No link detected */
393
394 mac->get_link_status = false;
395
396 /* Check if there was DownShift, must be checked
397 * immediately after link-up
398 */
399 igc_check_downshift(hw);
400
401 /* If we are forcing speed/duplex, then we simply return since
402 * we have already determined whether we have link or not.
403 */
404 if (!mac->autoneg) {
405 ret_val = -IGC_ERR_CONFIG;
406 goto out;
407 }
408
409 /* Auto-Neg is enabled. Auto Speed Detection takes care
410 * of MAC speed/duplex configuration. So we only need to
411 * configure Collision Distance in the MAC.
412 */
413 igc_config_collision_dist(hw);
414
415 /* Configure Flow Control now that Auto-Neg has completed.
416 * First, we need to restore the desired flow control
417 * settings because we may have had to re-autoneg with a
418 * different link partner.
419 */
420 ret_val = igc_config_fc_after_link_up(hw);
421 if (ret_val)
422 hw_dbg("Error configuring flow control\n");
423
424 out:
425 return ret_val;
426 }
427
428 /**
429 * igc_config_collision_dist - Configure collision distance
430 * @hw: pointer to the HW structure
431 *
432 * Configures the collision distance to the default value and is used
433 * during link setup. Currently no func pointer exists and all
434 * implementations are handled in the generic version of this function.
435 */
436 void igc_config_collision_dist(struct igc_hw *hw)
437 {
438 u32 tctl;
439
440 tctl = rd32(IGC_TCTL);
441
442 tctl &= ~IGC_TCTL_COLD;
443 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;
444
445 wr32(IGC_TCTL, tctl);
446 wrfl();
447 }
448
449 /**
450 * igc_config_fc_after_link_up - Configures flow control after link
451 * @hw: pointer to the HW structure
452 *
453 * Checks the status of auto-negotiation after link up to ensure that the
454 * speed and duplex were not forced. If the link needed to be forced, then
455 * flow control needs to be forced also. If auto-negotiation is enabled
456 * and did not fail, then we configure flow control based on our link
457 * partner.
458 */
459 s32 igc_config_fc_after_link_up(struct igc_hw *hw)
460 {
461 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
462 struct igc_mac_info *mac = &hw->mac;
463 u16 speed, duplex;
464 s32 ret_val = 0;
465
466 /* Check for the case where we have fiber media and auto-neg failed
467 * so we had to force link. In this case, we need to force the
468 * configuration of the MAC to match the "fc" parameter.
469 */
470 if (mac->autoneg_failed) {
471 if (hw->phy.media_type == igc_media_type_copper)
472 ret_val = igc_force_mac_fc(hw);
473 }
474
475 if (ret_val) {
476 hw_dbg("Error forcing flow control settings\n");
477 goto out;
478 }
479
480 /* Check for the case where we have copper media and auto-neg is
481 * enabled. In this case, we need to check and see if Auto-Neg
482 * has completed, and if so, how the PHY and link partner has
483 * flow control configured.
484 */
485 if (hw->phy.media_type == igc_media_type_copper && mac->autoneg) {
486 /* Read the MII Status Register and check to see if AutoNeg
487 * has completed. We read this twice because this reg has
488 * some "sticky" (latched) bits.
489 */
490 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
491 &mii_status_reg);
492 if (ret_val)
493 goto out;
494 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
495 &mii_status_reg);
496 if (ret_val)
497 goto out;
498
499 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
500 hw_dbg("Copper PHY and Auto Neg has not completed.\n");
501 goto out;
502 }
503
504 /* The AutoNeg process has completed, so we now need to
505 * read both the Auto Negotiation Advertisement
506 * Register (Address 4) and the Auto_Negotiation Base
507 * Page Ability Register (Address 5) to determine how
508 * flow control was negotiated.
509 */
510 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
511 &mii_nway_adv_reg);
512 if (ret_val)
513 goto out;
514 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
515 &mii_nway_lp_ability_reg);
516 if (ret_val)
517 goto out;
518 /* Two bits in the Auto Negotiation Advertisement Register
519 * (Address 4) and two bits in the Auto Negotiation Base
520 * Page Ability Register (Address 5) determine flow control
521 * for both the PHY and the link partner. The following
522 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
523 * 1999, describes these PAUSE resolution bits and how flow
524 * control is determined based upon these settings.
525 * NOTE: DC = Don't Care
526 *
527 * LOCAL DEVICE | LINK PARTNER
528 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
529 *-------|---------|-------|---------|--------------------
530 * 0 | 0 | DC | DC | igc_fc_none
531 * 0 | 1 | 0 | DC | igc_fc_none
532 * 0 | 1 | 1 | 0 | igc_fc_none
533 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
534 * 1 | 0 | 0 | DC | igc_fc_none
535 * 1 | DC | 1 | DC | igc_fc_full
536 * 1 | 1 | 0 | 0 | igc_fc_none
537 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
538 *
539 * Are both PAUSE bits set to 1? If so, this implies
540 * Symmetric Flow Control is enabled at both ends. The
541 * ASM_DIR bits are irrelevant per the spec.
542 *
543 * For Symmetric Flow Control:
544 *
545 * LOCAL DEVICE | LINK PARTNER
546 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
547 *-------|---------|-------|---------|--------------------
548 * 1 | DC | 1 | DC | IGC_fc_full
549 *
550 */
551 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
552 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
553 /* Now we need to check if the user selected RX ONLY
554 * of pause frames. In this case, we had to advertise
555 * FULL flow control because we could not advertise RX
556 * ONLY. Hence, we must now check to see if we need to
557 * turn OFF the TRANSMISSION of PAUSE frames.
558 */
559 if (hw->fc.requested_mode == igc_fc_full) {
560 hw->fc.current_mode = igc_fc_full;
561 hw_dbg("Flow Control = FULL.\n");
562 } else {
563 hw->fc.current_mode = igc_fc_rx_pause;
564 hw_dbg("Flow Control = RX PAUSE frames only.\n");
565 }
566 }
567
568 /* For receiving PAUSE frames ONLY.
569 *
570 * LOCAL DEVICE | LINK PARTNER
571 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
572 *-------|---------|-------|---------|--------------------
573 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
574 */
575 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
576 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
577 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
578 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
579 hw->fc.current_mode = igc_fc_tx_pause;
580 hw_dbg("Flow Control = TX PAUSE frames only.\n");
581 }
582 /* For transmitting PAUSE frames ONLY.
583 *
584 * LOCAL DEVICE | LINK PARTNER
585 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
586 *-------|---------|-------|---------|--------------------
587 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
588 */
589 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
590 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
591 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
592 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
593 hw->fc.current_mode = igc_fc_rx_pause;
594 hw_dbg("Flow Control = RX PAUSE frames only.\n");
595 }
596 /* Per the IEEE spec, at this point flow control should be
597 * disabled. However, we want to consider that we could
598 * be connected to a legacy switch that doesn't advertise
599 * desired flow control, but can be forced on the link
600 * partner. So if we advertised no flow control, that is
601 * what we will resolve to. If we advertised some kind of
602 * receive capability (Rx Pause Only or Full Flow Control)
603 * and the link partner advertised none, we will configure
604 * ourselves to enable Rx Flow Control only. We can do
605 * this safely for two reasons: If the link partner really
606 * didn't want flow control enabled, and we enable Rx, no
607 * harm done since we won't be receiving any PAUSE frames
608 * anyway. If the intent on the link partner was to have
609 * flow control enabled, then by us enabling RX only, we
610 * can at least receive pause frames and process them.
611 * This is a good idea because in most cases, since we are
612 * predominantly a server NIC, more times than not we will
613 * be asked to delay transmission of packets than asking
614 * our link partner to pause transmission of frames.
615 */
616 else if ((hw->fc.requested_mode == igc_fc_none) ||
617 (hw->fc.requested_mode == igc_fc_tx_pause) ||
618 (hw->fc.strict_ieee)) {
619 hw->fc.current_mode = igc_fc_none;
620 hw_dbg("Flow Control = NONE.\n");
621 } else {
622 hw->fc.current_mode = igc_fc_rx_pause;
623 hw_dbg("Flow Control = RX PAUSE frames only.\n");
624 }
625
626 /* Now we need to do one last check... If we auto-
627 * negotiated to HALF DUPLEX, flow control should not be
628 * enabled per IEEE 802.3 spec.
629 */
630 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
631 if (ret_val) {
632 hw_dbg("Error getting link speed and duplex\n");
633 goto out;
634 }
635
636 if (duplex == HALF_DUPLEX)
637 hw->fc.current_mode = igc_fc_none;
638
639 /* Now we call a subroutine to actually force the MAC
640 * controller to use the correct flow control settings.
641 */
642 ret_val = igc_force_mac_fc(hw);
643 if (ret_val) {
644 hw_dbg("Error forcing flow control settings\n");
645 goto out;
646 }
647 }
648
649 out:
650 return 0;
651 }
652
653 /**
654 * igc_get_auto_rd_done - Check for auto read completion
655 * @hw: pointer to the HW structure
656 *
657 * Check EEPROM for Auto Read done bit.
658 */
659 s32 igc_get_auto_rd_done(struct igc_hw *hw)
660 {
661 s32 ret_val = 0;
662 s32 i = 0;
663
664 while (i < AUTO_READ_DONE_TIMEOUT) {
665 if (rd32(IGC_EECD) & IGC_EECD_AUTO_RD)
666 break;
667 usleep_range(1000, 2000);
668 i++;
669 }
670
671 if (i == AUTO_READ_DONE_TIMEOUT) {
672 hw_dbg("Auto read by HW from NVM has not completed.\n");
673 ret_val = -IGC_ERR_RESET;
674 goto out;
675 }
676
677 out:
678 return ret_val;
679 }
680
681 /**
682 * igc_get_speed_and_duplex_copper - Retrieve current speed/duplex
683 * @hw: pointer to the HW structure
684 * @speed: stores the current speed
685 * @duplex: stores the current duplex
686 *
687 * Read the status register for the current speed/duplex and store the current
688 * speed and duplex for copper connections.
689 */
690 s32 igc_get_speed_and_duplex_copper(struct igc_hw *hw, u16 *speed,
691 u16 *duplex)
692 {
693 u32 status;
694
695 status = rd32(IGC_STATUS);
696 if (status & IGC_STATUS_SPEED_1000) {
697 /* For I225, STATUS will indicate 1G speed in both 1 Gbps
698 * and 2.5 Gbps link modes. An additional bit is used
699 * to differentiate between 1 Gbps and 2.5 Gbps.
700 */
701 if (hw->mac.type == igc_i225 &&
702 (status & IGC_STATUS_SPEED_2500)) {
703 *speed = SPEED_2500;
704 hw_dbg("2500 Mbs, ");
705 } else {
706 *speed = SPEED_1000;
707 hw_dbg("1000 Mbs, ");
708 }
709 } else if (status & IGC_STATUS_SPEED_100) {
710 *speed = SPEED_100;
711 hw_dbg("100 Mbs, ");
712 } else {
713 *speed = SPEED_10;
714 hw_dbg("10 Mbs, ");
715 }
716
717 if (status & IGC_STATUS_FD) {
718 *duplex = FULL_DUPLEX;
719 hw_dbg("Full Duplex\n");
720 } else {
721 *duplex = HALF_DUPLEX;
722 hw_dbg("Half Duplex\n");
723 }
724
725 return 0;
726 }
727
728 /**
729 * igc_put_hw_semaphore - Release hardware semaphore
730 * @hw: pointer to the HW structure
731 *
732 * Release hardware semaphore used to access the PHY or NVM
733 */
734 void igc_put_hw_semaphore(struct igc_hw *hw)
735 {
736 u32 swsm;
737
738 swsm = rd32(IGC_SWSM);
739
740 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
741
742 wr32(IGC_SWSM, swsm);
743 }
744
745 /**
746 * igc_enable_mng_pass_thru - Enable processing of ARP's
747 * @hw: pointer to the HW structure
748 *
749 * Verifies the hardware needs to leave interface enabled so that frames can
750 * be directed to and from the management interface.
751 */
752 bool igc_enable_mng_pass_thru(struct igc_hw *hw)
753 {
754 bool ret_val = false;
755 u32 fwsm, factps;
756 u32 manc;
757
758 if (!hw->mac.asf_firmware_present)
759 goto out;
760
761 manc = rd32(IGC_MANC);
762
763 if (!(manc & IGC_MANC_RCV_TCO_EN))
764 goto out;
765
766 if (hw->mac.arc_subsystem_valid) {
767 fwsm = rd32(IGC_FWSM);
768 factps = rd32(IGC_FACTPS);
769
770 if (!(factps & IGC_FACTPS_MNGCG) &&
771 ((fwsm & IGC_FWSM_MODE_MASK) ==
772 (igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT))) {
773 ret_val = true;
774 goto out;
775 }
776 } else {
777 if ((manc & IGC_MANC_SMBUS_EN) &&
778 !(manc & IGC_MANC_ASF_EN)) {
779 ret_val = true;
780 goto out;
781 }
782 }
783
784 out:
785 return ret_val;
786 }