drivers/net/ethernet/intel/igc/igc

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   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c)  2018 Intel Corporation */
   3 
   4 #ifndef _IGC_DEFINES_H_
   5 #define _IGC_DEFINES_H_
   6 
   7 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
   8 #define REQ_TX_DESCRIPTOR_MULTIPLE      8
   9 #define REQ_RX_DESCRIPTOR_MULTIPLE      8
  10 
  11 #define IGC_CTRL_EXT_DRV_LOAD   0x10000000 /* Drv loaded bit for FW */
  12 
  13 /* Physical Func Reset Done Indication */
  14 #define IGC_CTRL_EXT_LINK_MODE_MASK     0x00C00000
  15 
  16 /* Loop limit on how long we wait for auto-negotiation to complete */
  17 #define COPPER_LINK_UP_LIMIT            10
  18 #define PHY_AUTO_NEG_LIMIT              45
  19 #define PHY_FORCE_LIMIT                 20
  20 
  21 /* Number of 100 microseconds we wait for PCI Express master disable */
  22 #define MASTER_DISABLE_TIMEOUT          800
  23 /*Blocks new Master requests */
  24 #define IGC_CTRL_GIO_MASTER_DISABLE     0x00000004
  25 /* Status of Master requests. */
  26 #define IGC_STATUS_GIO_MASTER_ENABLE    0x00080000
  27 
  28 /* Receive Address
  29  * Number of high/low register pairs in the RAR. The RAR (Receive Address
  30  * Registers) holds the directed and multicast addresses that we monitor.
  31  * Technically, we have 16 spots.  However, we reserve one of these spots
  32  * (RAR[15]) for our directed address used by controllers with
  33  * manageability enabled, allowing us room for 15 multicast addresses.
  34  */
  35 #define IGC_RAH_AV              0x80000000 /* Receive descriptor valid */
  36 #define IGC_RAH_POOL_1          0x00040000
  37 #define IGC_RAL_MAC_ADDR_LEN    4
  38 #define IGC_RAH_MAC_ADDR_LEN    2
  39 
  40 /* Error Codes */
  41 #define IGC_SUCCESS                     0
  42 #define IGC_ERR_NVM                     1
  43 #define IGC_ERR_PHY                     2
  44 #define IGC_ERR_CONFIG                  3
  45 #define IGC_ERR_PARAM                   4
  46 #define IGC_ERR_MAC_INIT                5
  47 #define IGC_ERR_RESET                   9
  48 #define IGC_ERR_MASTER_REQUESTS_PENDING 10
  49 #define IGC_ERR_BLK_PHY_RESET           12
  50 #define IGC_ERR_SWFW_SYNC               13
  51 
  52 /* Device Control */
  53 #define IGC_CTRL_DEV_RST        0x20000000  /* Device reset */
  54 
  55 #define IGC_CTRL_PHY_RST        0x80000000  /* PHY Reset */
  56 #define IGC_CTRL_SLU            0x00000040  /* Set link up (Force Link) */
  57 #define IGC_CTRL_FRCSPD         0x00000800  /* Force Speed */
  58 #define IGC_CTRL_FRCDPX         0x00001000  /* Force Duplex */
  59 
  60 #define IGC_CTRL_RFCE           0x08000000  /* Receive Flow Control enable */
  61 #define IGC_CTRL_TFCE           0x10000000  /* Transmit flow control enable */
  62 
  63 #define IGC_CONNSW_AUTOSENSE_EN 0x1
  64 
  65 /* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
  66 #define MAX_JUMBO_FRAME_SIZE    0x2600
  67 
  68 /* PBA constants */
  69 #define IGC_PBA_34K             0x0022
  70 
  71 /* SW Semaphore Register */
  72 #define IGC_SWSM_SMBI           0x00000001 /* Driver Semaphore bit */
  73 #define IGC_SWSM_SWESMBI        0x00000002 /* FW Semaphore bit */
  74 
  75 /* SWFW_SYNC Definitions */
  76 #define IGC_SWFW_EEP_SM         0x1
  77 #define IGC_SWFW_PHY0_SM        0x2
  78 
  79 /* Autoneg Advertisement Register */
  80 #define NWAY_AR_10T_HD_CAPS     0x0020   /* 10T   Half Duplex Capable */
  81 #define NWAY_AR_10T_FD_CAPS     0x0040   /* 10T   Full Duplex Capable */
  82 #define NWAY_AR_100TX_HD_CAPS   0x0080   /* 100TX Half Duplex Capable */
  83 #define NWAY_AR_100TX_FD_CAPS   0x0100   /* 100TX Full Duplex Capable */
  84 #define NWAY_AR_PAUSE           0x0400   /* Pause operation desired */
  85 #define NWAY_AR_ASM_DIR         0x0800   /* Asymmetric Pause Direction bit */
  86 
  87 /* Link Partner Ability Register (Base Page) */
  88 #define NWAY_LPAR_PAUSE         0x0400 /* LP Pause operation desired */
  89 #define NWAY_LPAR_ASM_DIR       0x0800 /* LP Asymmetric Pause Direction bit */
  90 
  91 /* 1000BASE-T Control Register */
  92 #define CR_1000T_ASYM_PAUSE     0x0080 /* Advertise asymmetric pause bit */
  93 #define CR_1000T_HD_CAPS        0x0100 /* Advertise 1000T HD capability */
  94 #define CR_1000T_FD_CAPS        0x0200 /* Advertise 1000T FD capability  */
  95 
  96 /* 1000BASE-T Status Register */
  97 #define SR_1000T_REMOTE_RX_STATUS       0x1000 /* Remote receiver OK */
  98 #define SR_1000T_LOCAL_RX_STATUS        0x2000 /* Local receiver OK */
  99 
 100 /* PHY GPY 211 registers */
 101 #define STANDARD_AN_REG_MASK    0x0007 /* MMD */
 102 #define ANEG_MULTIGBT_AN_CTRL   0x0020 /* MULTI GBT AN Control Register */
 103 #define MMD_DEVADDR_SHIFT       16     /* Shift MMD to higher bits */
 104 #define CR_2500T_FD_CAPS        0x0080 /* Advertise 2500T FD capability */
 105 
 106 /* NVM Control */
 107 /* Number of milliseconds for NVM auto read done after MAC reset. */
 108 #define AUTO_READ_DONE_TIMEOUT          10
 109 #define IGC_EECD_AUTO_RD                0x00000200  /* NVM Auto Read done */
 110 #define IGC_EECD_REQ            0x00000040 /* NVM Access Request */
 111 #define IGC_EECD_GNT            0x00000080 /* NVM Access Grant */
 112 /* NVM Addressing bits based on type 0=small, 1=large */
 113 #define IGC_EECD_ADDR_BITS              0x00000400
 114 #define IGC_NVM_GRANT_ATTEMPTS          1000 /* NVM # attempts to gain grant */
 115 #define IGC_EECD_SIZE_EX_MASK           0x00007800  /* NVM Size */
 116 #define IGC_EECD_SIZE_EX_SHIFT          11
 117 #define IGC_EECD_FLUPD_I225             0x00800000 /* Update FLASH */
 118 #define IGC_EECD_FLUDONE_I225           0x04000000 /* Update FLASH done*/
 119 #define IGC_EECD_FLASH_DETECTED_I225    0x00080000 /* FLASH detected */
 120 #define IGC_FLUDONE_ATTEMPTS            20000
 121 #define IGC_EERD_EEWR_MAX_COUNT         512 /* buffered EEPROM words rw */
 122 
 123 /* Offset to data in NVM read/write registers */
 124 #define IGC_NVM_RW_REG_DATA     16
 125 #define IGC_NVM_RW_REG_DONE     2    /* Offset to READ/WRITE done bit */
 126 #define IGC_NVM_RW_REG_START    1    /* Start operation */
 127 #define IGC_NVM_RW_ADDR_SHIFT   2    /* Shift to the address bits */
 128 #define IGC_NVM_POLL_READ       0    /* Flag for polling for read complete */
 129 
 130 /* NVM Word Offsets */
 131 #define NVM_CHECKSUM_REG                0x003F
 132 
 133 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
 134 #define NVM_SUM                         0xBABA
 135 
 136 #define NVM_PBA_OFFSET_0                8
 137 #define NVM_PBA_OFFSET_1                9
 138 #define NVM_RESERVED_WORD               0xFFFF
 139 #define NVM_PBA_PTR_GUARD               0xFAFA
 140 #define NVM_WORD_SIZE_BASE_SHIFT        6
 141 
 142 /* Collision related configuration parameters */
 143 #define IGC_COLLISION_THRESHOLD         15
 144 #define IGC_CT_SHIFT                    4
 145 #define IGC_COLLISION_DISTANCE          63
 146 #define IGC_COLD_SHIFT                  12
 147 
 148 /* Device Status */
 149 #define IGC_STATUS_FD           0x00000001      /* Full duplex.0=half,1=full */
 150 #define IGC_STATUS_LU           0x00000002      /* Link up.0=no,1=link */
 151 #define IGC_STATUS_FUNC_MASK    0x0000000C      /* PCI Function Mask */
 152 #define IGC_STATUS_FUNC_SHIFT   2
 153 #define IGC_STATUS_FUNC_1       0x00000004      /* Function 1 */
 154 #define IGC_STATUS_TXOFF        0x00000010      /* transmission paused */
 155 #define IGC_STATUS_SPEED_100    0x00000040      /* Speed 100Mb/s */
 156 #define IGC_STATUS_SPEED_1000   0x00000080      /* Speed 1000Mb/s */
 157 #define IGC_STATUS_SPEED_2500   0x00400000      /* Speed 2.5Gb/s */
 158 
 159 #define SPEED_10                10
 160 #define SPEED_100               100
 161 #define SPEED_1000              1000
 162 #define SPEED_2500              2500
 163 #define HALF_DUPLEX             1
 164 #define FULL_DUPLEX             2
 165 
 166 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
 167 #define ADVERTISE_10_HALF               0x0001
 168 #define ADVERTISE_10_FULL               0x0002
 169 #define ADVERTISE_100_HALF              0x0004
 170 #define ADVERTISE_100_FULL              0x0008
 171 #define ADVERTISE_1000_HALF             0x0010 /* Not used, just FYI */
 172 #define ADVERTISE_1000_FULL             0x0020
 173 #define ADVERTISE_2500_HALF             0x0040 /* Not used, just FYI */
 174 #define ADVERTISE_2500_FULL             0x0080
 175 
 176 #define IGC_ALL_SPEED_DUPLEX_2500 ( \
 177         ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
 178         ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL)
 179 
 180 #define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500    IGC_ALL_SPEED_DUPLEX_2500
 181 
 182 /* Interrupt Cause Read */
 183 #define IGC_ICR_TXDW            BIT(0)  /* Transmit desc written back */
 184 #define IGC_ICR_TXQE            BIT(1)  /* Transmit Queue empty */
 185 #define IGC_ICR_LSC             BIT(2)  /* Link Status Change */
 186 #define IGC_ICR_RXSEQ           BIT(3)  /* Rx sequence error */
 187 #define IGC_ICR_RXDMT0          BIT(4)  /* Rx desc min. threshold (0) */
 188 #define IGC_ICR_RXO             BIT(6)  /* Rx overrun */
 189 #define IGC_ICR_RXT0            BIT(7)  /* Rx timer intr (ring 0) */
 190 #define IGC_ICR_DRSTA           BIT(30) /* Device Reset Asserted */
 191 
 192 /* If this bit asserted, the driver should claim the interrupt */
 193 #define IGC_ICR_INT_ASSERTED    BIT(31)
 194 
 195 #define IGC_ICS_RXT0            IGC_ICR_RXT0 /* Rx timer intr */
 196 
 197 #define IMS_ENABLE_MASK ( \
 198         IGC_IMS_RXT0   |    \
 199         IGC_IMS_TXDW   |    \
 200         IGC_IMS_RXDMT0 |    \
 201         IGC_IMS_RXSEQ  |    \
 202         IGC_IMS_LSC)
 203 
 204 /* Interrupt Mask Set */
 205 #define IGC_IMS_TXDW            IGC_ICR_TXDW    /* Tx desc written back */
 206 #define IGC_IMS_RXSEQ           IGC_ICR_RXSEQ   /* Rx sequence error */
 207 #define IGC_IMS_LSC             IGC_ICR_LSC     /* Link Status Change */
 208 #define IGC_IMS_DOUTSYNC        IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
 209 #define IGC_IMS_DRSTA           IGC_ICR_DRSTA   /* Device Reset Asserted */
 210 #define IGC_IMS_RXT0            IGC_ICR_RXT0    /* Rx timer intr */
 211 #define IGC_IMS_RXDMT0          IGC_ICR_RXDMT0  /* Rx desc min. threshold */
 212 
 213 #define IGC_QVECTOR_MASK        0x7FFC          /* Q-vector mask */
 214 #define IGC_ITR_VAL_MASK        0x04            /* ITR value mask */
 215 
 216 /* Interrupt Cause Set */
 217 #define IGC_ICS_LSC             IGC_ICR_LSC       /* Link Status Change */
 218 #define IGC_ICS_RXDMT0          IGC_ICR_RXDMT0    /* rx desc min. threshold */
 219 #define IGC_ICS_DRSTA           IGC_ICR_DRSTA     /* Device Reset Aserted */
 220 
 221 #define IGC_ICR_DOUTSYNC        0x10000000 /* NIC DMA out of sync */
 222 #define IGC_EITR_CNT_IGNR       0x80000000 /* Don't reset counters on write */
 223 #define IGC_IVAR_VALID          0x80
 224 #define IGC_GPIE_NSICR          0x00000001
 225 #define IGC_GPIE_MSIX_MODE      0x00000010
 226 #define IGC_GPIE_EIAME          0x40000000
 227 #define IGC_GPIE_PBA            0x80000000
 228 
 229 /* Transmit Descriptor bit definitions */
 230 #define IGC_TXD_DTYP_D          0x00100000 /* Data Descriptor */
 231 #define IGC_TXD_DTYP_C          0x00000000 /* Context Descriptor */
 232 #define IGC_TXD_POPTS_IXSM      0x01       /* Insert IP checksum */
 233 #define IGC_TXD_POPTS_TXSM      0x02       /* Insert TCP/UDP checksum */
 234 #define IGC_TXD_CMD_EOP         0x01000000 /* End of Packet */
 235 #define IGC_TXD_CMD_IFCS        0x02000000 /* Insert FCS (Ethernet CRC) */
 236 #define IGC_TXD_CMD_IC          0x04000000 /* Insert Checksum */
 237 #define IGC_TXD_CMD_RS          0x08000000 /* Report Status */
 238 #define IGC_TXD_CMD_RPS         0x10000000 /* Report Packet Sent */
 239 #define IGC_TXD_CMD_DEXT        0x20000000 /* Desc extension (0 = legacy) */
 240 #define IGC_TXD_CMD_VLE         0x40000000 /* Add VLAN tag */
 241 #define IGC_TXD_CMD_IDE         0x80000000 /* Enable Tidv register */
 242 #define IGC_TXD_STAT_DD         0x00000001 /* Descriptor Done */
 243 #define IGC_TXD_STAT_EC         0x00000002 /* Excess Collisions */
 244 #define IGC_TXD_STAT_LC         0x00000004 /* Late Collisions */
 245 #define IGC_TXD_STAT_TU         0x00000008 /* Transmit underrun */
 246 #define IGC_TXD_CMD_TCP         0x01000000 /* TCP packet */
 247 #define IGC_TXD_CMD_IP          0x02000000 /* IP packet */
 248 #define IGC_TXD_CMD_TSE         0x04000000 /* TCP Seg enable */
 249 #define IGC_TXD_STAT_TC         0x00000004 /* Tx Underrun */
 250 #define IGC_TXD_EXTCMD_TSTAMP   0x00000010 /* IEEE1588 Timestamp packet */
 251 
 252 /* Transmit Control */
 253 #define IGC_TCTL_EN             0x00000002 /* enable Tx */
 254 #define IGC_TCTL_PSP            0x00000008 /* pad short packets */
 255 #define IGC_TCTL_CT             0x00000ff0 /* collision threshold */
 256 #define IGC_TCTL_COLD           0x003ff000 /* collision distance */
 257 #define IGC_TCTL_RTLC           0x01000000 /* Re-transmit on late collision */
 258 #define IGC_TCTL_MULR           0x10000000 /* Multiple request support */
 259 
 260 /* Flow Control Constants */
 261 #define FLOW_CONTROL_ADDRESS_LOW        0x00C28001
 262 #define FLOW_CONTROL_ADDRESS_HIGH       0x00000100
 263 #define FLOW_CONTROL_TYPE               0x8808
 264 /* Enable XON frame transmission */
 265 #define IGC_FCRTL_XONE                  0x80000000
 266 
 267 /* Management Control */
 268 #define IGC_MANC_RCV_TCO_EN     0x00020000 /* Receive TCO Packets Enabled */
 269 #define IGC_MANC_BLK_PHY_RST_ON_IDE     0x00040000 /* Block phy resets */
 270 
 271 /* Receive Control */
 272 #define IGC_RCTL_RST            0x00000001 /* Software reset */
 273 #define IGC_RCTL_EN             0x00000002 /* enable */
 274 #define IGC_RCTL_SBP            0x00000004 /* store bad packet */
 275 #define IGC_RCTL_UPE            0x00000008 /* unicast promisc enable */
 276 #define IGC_RCTL_MPE            0x00000010 /* multicast promisc enable */
 277 #define IGC_RCTL_LPE            0x00000020 /* long packet enable */
 278 #define IGC_RCTL_LBM_MAC        0x00000040 /* MAC loopback mode */
 279 #define IGC_RCTL_LBM_TCVR       0x000000C0 /* tcvr loopback mode */
 280 
 281 #define IGC_RCTL_RDMTS_HALF     0x00000000 /* Rx desc min thresh size */
 282 #define IGC_RCTL_BAM            0x00008000 /* broadcast enable */
 283 
 284 /* Receive Descriptor bit definitions */
 285 #define IGC_RXD_STAT_EOP        0x02    /* End of Packet */
 286 
 287 #define IGC_RXDEXT_STATERR_CE           0x01000000
 288 #define IGC_RXDEXT_STATERR_SE           0x02000000
 289 #define IGC_RXDEXT_STATERR_SEQ          0x04000000
 290 #define IGC_RXDEXT_STATERR_CXE          0x10000000
 291 #define IGC_RXDEXT_STATERR_TCPE         0x20000000
 292 #define IGC_RXDEXT_STATERR_IPE          0x40000000
 293 #define IGC_RXDEXT_STATERR_RXE          0x80000000
 294 
 295 /* Same mask, but for extended and packet split descriptors */
 296 #define IGC_RXDEXT_ERR_FRAME_ERR_MASK ( \
 297         IGC_RXDEXT_STATERR_CE  |        \
 298         IGC_RXDEXT_STATERR_SE  |        \
 299         IGC_RXDEXT_STATERR_SEQ |        \
 300         IGC_RXDEXT_STATERR_CXE |        \
 301         IGC_RXDEXT_STATERR_RXE)
 302 
 303 #define IGC_MRQC_RSS_FIELD_IPV4_TCP     0x00010000
 304 #define IGC_MRQC_RSS_FIELD_IPV4         0x00020000
 305 #define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX  0x00040000
 306 #define IGC_MRQC_RSS_FIELD_IPV6         0x00100000
 307 #define IGC_MRQC_RSS_FIELD_IPV6_TCP     0x00200000
 308 
 309 /* Header split receive */
 310 #define IGC_RFCTL_IPV6_EX_DIS   0x00010000
 311 #define IGC_RFCTL_LEF           0x00040000
 312 
 313 #define IGC_RCTL_SZ_256         0x00030000 /* Rx buffer size 256 */
 314 
 315 #define IGC_RCTL_MO_SHIFT       12 /* multicast offset shift */
 316 #define IGC_RCTL_CFIEN          0x00080000 /* canonical form enable */
 317 #define IGC_RCTL_DPF            0x00400000 /* discard pause frames */
 318 #define IGC_RCTL_PMCF           0x00800000 /* pass MAC control frames */
 319 #define IGC_RCTL_SECRC          0x04000000 /* Strip Ethernet CRC */
 320 
 321 #define I225_RXPBSIZE_DEFAULT   0x000000A2 /* RXPBSIZE default */
 322 #define I225_TXPBSIZE_DEFAULT   0x04000014 /* TXPBSIZE default */
 323 
 324 /* Receive Checksum Control */
 325 #define IGC_RXCSUM_CRCOFL       0x00000800   /* CRC32 offload enable */
 326 #define IGC_RXCSUM_PCSD         0x00002000   /* packet checksum disabled */
 327 
 328 /* GPY211 - I225 defines */
 329 #define GPY_MMD_MASK            0xFFFF0000
 330 #define GPY_MMD_SHIFT           16
 331 #define GPY_REG_MASK            0x0000FFFF
 332 
 333 #define IGC_MMDAC_FUNC_DATA     0x4000 /* Data, no post increment */
 334 
 335 /* MAC definitions */
 336 #define IGC_FACTPS_MNGCG        0x20000000
 337 #define IGC_FWSM_MODE_MASK      0xE
 338 #define IGC_FWSM_MODE_SHIFT     1
 339 
 340 /* Management Control */
 341 #define IGC_MANC_SMBUS_EN       0x00000001 /* SMBus Enabled - RO */
 342 #define IGC_MANC_ASF_EN         0x00000002 /* ASF Enabled - RO */
 343 
 344 /* PHY */
 345 #define PHY_REVISION_MASK       0xFFFFFFF0
 346 #define MAX_PHY_REG_ADDRESS     0x1F  /* 5 bit address bus (0-0x1F) */
 347 #define IGC_GEN_POLL_TIMEOUT    1920
 348 
 349 /* PHY Control Register */
 350 #define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
 351 #define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
 352 #define MII_CR_POWER_DOWN       0x0800  /* Power down */
 353 #define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
 354 #define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
 355 #define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
 356 #define MII_CR_SPEED_1000       0x0040
 357 #define MII_CR_SPEED_100        0x2000
 358 #define MII_CR_SPEED_10         0x0000
 359 
 360 /* PHY Status Register */
 361 #define MII_SR_LINK_STATUS      0x0004 /* Link Status 1 = link */
 362 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
 363 
 364 /* PHY 1000 MII Register/Bit Definitions */
 365 /* PHY Registers defined by IEEE */
 366 #define PHY_CONTROL             0x00 /* Control Register */
 367 #define PHY_STATUS              0x01 /* Status Register */
 368 #define PHY_ID1                 0x02 /* Phy Id Reg (word 1) */
 369 #define PHY_ID2                 0x03 /* Phy Id Reg (word 2) */
 370 #define PHY_AUTONEG_ADV         0x04 /* Autoneg Advertisement */
 371 #define PHY_LP_ABILITY          0x05 /* Link Partner Ability (Base Page) */
 372 #define PHY_1000T_CTRL          0x09 /* 1000Base-T Control Reg */
 373 #define PHY_1000T_STATUS        0x0A /* 1000Base-T Status Reg */
 374 
 375 /* Bit definitions for valid PHY IDs. I = Integrated E = External */
 376 #define I225_I_PHY_ID           0x67C9DC00
 377 
 378 /* MDI Control */
 379 #define IGC_MDIC_DATA_MASK      0x0000FFFF
 380 #define IGC_MDIC_REG_MASK       0x001F0000
 381 #define IGC_MDIC_REG_SHIFT      16
 382 #define IGC_MDIC_PHY_MASK       0x03E00000
 383 #define IGC_MDIC_PHY_SHIFT      21
 384 #define IGC_MDIC_OP_WRITE       0x04000000
 385 #define IGC_MDIC_OP_READ        0x08000000
 386 #define IGC_MDIC_READY          0x10000000
 387 #define IGC_MDIC_INT_EN         0x20000000
 388 #define IGC_MDIC_ERROR          0x40000000
 389 #define IGC_MDIC_DEST           0x80000000
 390 
 391 #define IGC_N0_QUEUE            -1
 392 
 393 #define IGC_MAX_MAC_HDR_LEN     127
 394 #define IGC_MAX_NETWORK_HDR_LEN 511
 395 
 396 #define IGC_VLAPQF_QUEUE_SEL(_n, q_idx) ((q_idx) << ((_n) * 4))
 397 #define IGC_VLAPQF_P_VALID(_n)  (0x1 << (3 + (_n) * 4))
 398 #define IGC_VLAPQF_QUEUE_MASK   0x03
 399 
 400 #define IGC_ADVTXD_MACLEN_SHIFT         9  /* Adv ctxt desc mac len shift */
 401 #define IGC_ADVTXD_TUCMD_IPV4           0x00000400  /* IP Packet Type:1=IPv4 */
 402 #define IGC_ADVTXD_TUCMD_L4T_TCP        0x00000800  /* L4 Packet Type of TCP */
 403 #define IGC_ADVTXD_TUCMD_L4T_SCTP       0x00001000 /* L4 packet TYPE of SCTP */
 404 
 405 #endif /* _IGC_DEFINES_H_ */
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root/drivers/net/ethernet/intel/igc/igc_defines.h

INCLUDED FROM
