This source file includes following definitions.
- IXGBE_MVALS_INIT
1
2
3
4 #ifndef _IXGBE_TYPE_H_
5 #define _IXGBE_TYPE_H_
6
7 #include <linux/types.h>
8 #include <linux/mdio.h>
9 #include <linux/netdevice.h>
10
11
12 #define IXGBE_DEV_ID_82598 0x10B6
13 #define IXGBE_DEV_ID_82598_BX 0x1508
14 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
15 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
16 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
17 #define IXGBE_DEV_ID_82598AT 0x10C8
18 #define IXGBE_DEV_ID_82598AT2 0x150B
19 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
20 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
21 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
22 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
23 #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
24 #define IXGBE_DEV_ID_82599_KX4 0x10F7
25 #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
26 #define IXGBE_DEV_ID_82599_KR 0x1517
27 #define IXGBE_DEV_ID_82599_T3_LOM 0x151C
28 #define IXGBE_DEV_ID_82599_CX4 0x10F9
29 #define IXGBE_DEV_ID_82599_SFP 0x10FB
30 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a
31 #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
32 #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
33 #define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071
34 #define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72
35 #define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
36 #define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B
37 #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6 0x2159
38 #define IXGBE_SUBDEV_ID_82599_SFP_1OCP 0x000D
39 #define IXGBE_SUBDEV_ID_82599_SFP_2OCP 0x0008
40 #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1 0x8976
41 #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2 0x06EE
42 #define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470
43 #define IXGBE_DEV_ID_82599_SFP_EM 0x1507
44 #define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
45 #define IXGBE_DEV_ID_82599EN_SFP 0x1557
46 #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001
47 #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
48 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
49 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
50 #define IXGBE_DEV_ID_82599_LS 0x154F
51 #define IXGBE_DEV_ID_X540T 0x1528
52 #define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A
53 #define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558
54 #define IXGBE_DEV_ID_X540T1 0x1560
55
56 #define IXGBE_DEV_ID_X550T 0x1563
57 #define IXGBE_DEV_ID_X550T1 0x15D1
58 #define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA
59 #define IXGBE_DEV_ID_X550EM_X_KR 0x15AB
60 #define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
61 #define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
62 #define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE
63 #define IXGBE_DEV_ID_X550EM_X_XFI 0x15B0
64 #define IXGBE_DEV_ID_X550EM_A_KR 0x15C2
65 #define IXGBE_DEV_ID_X550EM_A_KR_L 0x15C3
66 #define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4
67 #define IXGBE_DEV_ID_X550EM_A_SGMII 0x15C6
68 #define IXGBE_DEV_ID_X550EM_A_SGMII_L 0x15C7
69 #define IXGBE_DEV_ID_X550EM_A_10G_T 0x15C8
70 #define IXGBE_DEV_ID_X550EM_A_SFP 0x15CE
71 #define IXGBE_DEV_ID_X550EM_A_1G_T 0x15E4
72 #define IXGBE_DEV_ID_X550EM_A_1G_T_L 0x15E5
73
74
75 #define IXGBE_DEV_ID_82599_VF 0x10ED
76 #define IXGBE_DEV_ID_X540_VF 0x1515
77 #define IXGBE_DEV_ID_X550_VF 0x1565
78 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
79 #define IXGBE_DEV_ID_X550EM_A_VF 0x15C5
80
81 #define IXGBE_CAT(r, m) IXGBE_##r##_##m
82
83 #define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, IDX)])
84
85
86 #define IXGBE_CTRL 0x00000
87 #define IXGBE_STATUS 0x00008
88 #define IXGBE_CTRL_EXT 0x00018
89 #define IXGBE_ESDP 0x00020
90 #define IXGBE_EODSDP 0x00028
91
92 #define IXGBE_I2CCTL_8259X 0x00028
93 #define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_8259X
94 #define IXGBE_I2CCTL_X550 0x15F5C
95 #define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550
96 #define IXGBE_I2CCTL_X550EM_a IXGBE_I2CCTL_X550
97 #define IXGBE_I2CCTL(_hw) IXGBE_BY_MAC((_hw), I2CCTL)
98
99 #define IXGBE_LEDCTL 0x00200
100 #define IXGBE_FRTIMER 0x00048
101 #define IXGBE_TCPTIMER 0x0004C
102 #define IXGBE_CORESPARE 0x00600
103 #define IXGBE_EXVET 0x05078
104
105
106 #define IXGBE_EEC_8259X 0x10010
107 #define IXGBE_EEC_X540 IXGBE_EEC_8259X
108 #define IXGBE_EEC_X550 IXGBE_EEC_8259X
109 #define IXGBE_EEC_X550EM_x IXGBE_EEC_8259X
110 #define IXGBE_EEC_X550EM_a 0x15FF8
111 #define IXGBE_EEC(_hw) IXGBE_BY_MAC((_hw), EEC)
112 #define IXGBE_EERD 0x10014
113 #define IXGBE_EEWR 0x10018
114 #define IXGBE_FLA_8259X 0x1001C
115 #define IXGBE_FLA_X540 IXGBE_FLA_8259X
116 #define IXGBE_FLA_X550 IXGBE_FLA_8259X
117 #define IXGBE_FLA_X550EM_x IXGBE_FLA_8259X
118 #define IXGBE_FLA_X550EM_a 0x15F68
119 #define IXGBE_FLA(_hw) IXGBE_BY_MAC((_hw), FLA)
120 #define IXGBE_EEMNGCTL 0x10110
121 #define IXGBE_EEMNGDATA 0x10114
122 #define IXGBE_FLMNGCTL 0x10118
123 #define IXGBE_FLMNGDATA 0x1011C
124 #define IXGBE_FLMNGCNT 0x10120
125 #define IXGBE_FLOP 0x1013C
126 #define IXGBE_GRC_8259X 0x10200
127 #define IXGBE_GRC_X540 IXGBE_GRC_8259X
128 #define IXGBE_GRC_X550 IXGBE_GRC_8259X
129 #define IXGBE_GRC_X550EM_x IXGBE_GRC_8259X
130 #define IXGBE_GRC_X550EM_a 0x15F64
131 #define IXGBE_GRC(_hw) IXGBE_BY_MAC((_hw), GRC)
132
133
134 #define IXGBE_GRC_MNG 0x00000001
135 #define IXGBE_GRC_APME 0x00000002
136
137 #define IXGBE_VPDDIAG0 0x10204
138 #define IXGBE_VPDDIAG1 0x10208
139
140
141 #define IXGBE_I2C_CLK_IN_8259X 0x00000001
142 #define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN_8259X
143 #define IXGBE_I2C_CLK_IN_X550 0x00004000
144 #define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550
145 #define IXGBE_I2C_CLK_IN_X550EM_a IXGBE_I2C_CLK_IN_X550
146 #define IXGBE_I2C_CLK_IN(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN)
147
148 #define IXGBE_I2C_CLK_OUT_8259X 0x00000002
149 #define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT_8259X
150 #define IXGBE_I2C_CLK_OUT_X550 0x00000200
151 #define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550
152 #define IXGBE_I2C_CLK_OUT_X550EM_a IXGBE_I2C_CLK_OUT_X550
153 #define IXGBE_I2C_CLK_OUT(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
154
155 #define IXGBE_I2C_DATA_IN_8259X 0x00000004
156 #define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN_8259X
157 #define IXGBE_I2C_DATA_IN_X550 0x00001000
158 #define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550
159 #define IXGBE_I2C_DATA_IN_X550EM_a IXGBE_I2C_DATA_IN_X550
160 #define IXGBE_I2C_DATA_IN(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN)
161
162 #define IXGBE_I2C_DATA_OUT_8259X 0x00000008
163 #define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT_8259X
164 #define IXGBE_I2C_DATA_OUT_X550 0x00000400
165 #define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550
166 #define IXGBE_I2C_DATA_OUT_X550EM_a IXGBE_I2C_DATA_OUT_X550
167 #define IXGBE_I2C_DATA_OUT(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
168
169 #define IXGBE_I2C_DATA_OE_N_EN_8259X 0
170 #define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN_8259X
171 #define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800
172 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550
173 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550
174 #define IXGBE_I2C_DATA_OE_N_EN(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
175
176 #define IXGBE_I2C_BB_EN_8259X 0
177 #define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN_8259X
178 #define IXGBE_I2C_BB_EN_X550 0x00000100
179 #define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550
180 #define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550
181 #define IXGBE_I2C_BB_EN(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN)
182
183 #define IXGBE_I2C_CLK_OE_N_EN_8259X 0
184 #define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN_8259X
185 #define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000
186 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550
187 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550
188 #define IXGBE_I2C_CLK_OE_N_EN(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
189
190 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
191
192 #define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
193 #define IXGBE_EMC_INTERNAL_DATA 0x00
194 #define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
195 #define IXGBE_EMC_DIODE1_DATA 0x01
196 #define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19
197 #define IXGBE_EMC_DIODE2_DATA 0x23
198 #define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
199
200 #define IXGBE_MAX_SENSORS 3
201
202 struct ixgbe_thermal_diode_data {
203 u8 location;
204 u8 temp;
205 u8 caution_thresh;
206 u8 max_op_thresh;
207 };
208
209 struct ixgbe_thermal_sensor_data {
210 struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];
211 };
212
213 #define NVM_OROM_OFFSET 0x17
214 #define NVM_OROM_BLK_LOW 0x83
215 #define NVM_OROM_BLK_HI 0x84
216 #define NVM_OROM_PATCH_MASK 0xFF
217 #define NVM_OROM_SHIFT 8
218
219 #define NVM_VER_MASK 0x00FF
220 #define NVM_VER_SHIFT 8
221 #define NVM_OEM_PROD_VER_PTR 0x1B
222 #define NVM_OEM_PROD_VER_CAP_OFF 0x1
223 #define NVM_OEM_PROD_VER_OFF_L 0x2
224 #define NVM_OEM_PROD_VER_OFF_H 0x3
225 #define NVM_OEM_PROD_VER_CAP_MASK 0xF
226 #define NVM_OEM_PROD_VER_MOD_LEN 0x3
227 #define NVM_ETK_OFF_LOW 0x2D
228 #define NVM_ETK_OFF_HI 0x2E
229 #define NVM_ETK_SHIFT 16
230 #define NVM_VER_INVALID 0xFFFF
231 #define NVM_ETK_VALID 0x8000
232 #define NVM_INVALID_PTR 0xFFFF
233 #define NVM_VER_SIZE 32
234
235 struct ixgbe_nvm_version {
236 u32 etk_id;
237 u8 nvm_major;
238 u16 nvm_minor;
239 u8 nvm_id;
240
241 bool oem_valid;
242 u8 oem_major;
243 u8 oem_minor;
244 u16 oem_release;
245
246 bool or_valid;
247 u8 or_major;
248 u16 or_build;
249 u8 or_patch;
250 };
251
252
253 #define IXGBE_EICR 0x00800
254 #define IXGBE_EICS 0x00808
255 #define IXGBE_EIMS 0x00880
256 #define IXGBE_EIMC 0x00888
257 #define IXGBE_EIAC 0x00810
258 #define IXGBE_EIAM 0x00890
259 #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
260 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
261 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
262 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
263
264
265
266
267
268 #define IXGBE_MAX_INT_RATE 488281
269 #define IXGBE_MIN_INT_RATE 956
270 #define IXGBE_MAX_EITR 0x00000FF8
271 #define IXGBE_MIN_EITR 8
272 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
273 (0x012300 + (((_i) - 24) * 4)))
274 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
275 #define IXGBE_EITR_LLI_MOD 0x00008000
276 #define IXGBE_EITR_CNT_WDIS 0x80000000
277 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4))
278 #define IXGBE_IVAR_MISC 0x00A00
279 #define IXGBE_EITRSEL 0x00894
280 #define IXGBE_MSIXT 0x00000
281 #define IXGBE_MSIXPBA 0x02000
282 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
283 #define IXGBE_GPIE 0x00898
284
285
286 #define IXGBE_FCADBUL 0x03210
287 #define IXGBE_FCADBUH 0x03214
288 #define IXGBE_FCAMACL 0x04328
289 #define IXGBE_FCAMACH 0x0432C
290 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4))
291 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4))
292 #define IXGBE_PFCTOP 0x03008
293 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4))
294 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8))
295 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8))
296 #define IXGBE_FCRTV 0x032A0
297 #define IXGBE_FCCFG 0x03D00
298 #define IXGBE_TFCS 0x0CE00
299
300
301 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
302 (0x0D000 + (((_i) - 64) * 0x40)))
303 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
304 (0x0D004 + (((_i) - 64) * 0x40)))
305 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
306 (0x0D008 + (((_i) - 64) * 0x40)))
307 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
308 (0x0D010 + (((_i) - 64) * 0x40)))
309 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
310 (0x0D018 + (((_i) - 64) * 0x40)))
311 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
312 (0x0D028 + (((_i) - 64) * 0x40)))
313 #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
314 (0x0D02C + (((_i) - 64) * 0x40)))
315 #define IXGBE_RSCDBU 0x03028
316 #define IXGBE_RDDCC 0x02F20
317 #define IXGBE_RXMEMWRAP 0x03190
318 #define IXGBE_STARCTRL 0x03024
319
320
321
322
323
324
325 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
326 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
327 (0x0D014 + (((_i) - 64) * 0x40))))
328
329
330
331
332
333
334 #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
335 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
336 (0x0D00C + (((_i) - 64) * 0x40))))
337 #define IXGBE_RDRXCTL 0x02F00
338 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
339
340 #define IXGBE_RXCTRL 0x03000
341 #define IXGBE_DROPEN 0x03D04
342 #define IXGBE_RXPBSIZE_SHIFT 10
343
344
345 #define IXGBE_RXCSUM 0x05000
346 #define IXGBE_RFCTL 0x05008
347 #define IXGBE_DRECCCTL 0x02F08
348 #define IXGBE_DRECCCTL_DISABLE 0
349
350 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
351 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
352 (0x0A200 + ((_i) * 8)))
353 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
354 (0x0A204 + ((_i) * 8)))
355 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
356 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
357
358 #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
359 (0x0EA00 + ((_i) * 4)))
360
361 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
362
363 #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
364 #define IXGBE_FCTRL 0x05080
365 #define IXGBE_VLNCTRL 0x05088
366 #define IXGBE_MCSTCTRL 0x05090
367 #define IXGBE_MRQC 0x05818
368 #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4))
369 #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4))
370 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4))
371 #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4))
372 #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4))
373 #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4))
374 #define IXGBE_SYNQF 0x0EC30
375 #define IXGBE_RQTC 0x0EC70
376 #define IXGBE_MTQC 0x08120
377 #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4))
378 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))
379 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))
380 #define IXGBE_PFFLPL 0x050B0
381 #define IXGBE_PFFLPH 0x050B4
382 #define IXGBE_VT_CTL 0x051B0
383 #define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i)))
384 #define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i)))
385 #define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i)))
386 #define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i)))
387 #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
388 #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
389 #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
390 #define IXGBE_QDE 0x2F04
391 #define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4))
392 #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4))
393 #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
394 #define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
395 #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
396 #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
397 #define IXGBE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4))
398 #define IXGBE_WQBR_TX(_i) (0x8130 + ((_i) * 4))
399 #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4))
400 #define IXGBE_RXFECCERR0 0x051B8
401 #define IXGBE_LLITHRESH 0x0EC90
402 #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4))
403 #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4))
404 #define IXGBE_IMIRVP 0x05AC0
405 #define IXGBE_VMD_CTL 0x0581C
406 #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4))
407 #define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4))
408 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4))
409
410
411
412
413
414 #define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4))
415 #define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40))
416 #define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40))
417
418
419 #define IXGBE_FDIRCTRL 0x0EE00
420 #define IXGBE_FDIRHKEY 0x0EE68
421 #define IXGBE_FDIRSKEY 0x0EE6C
422 #define IXGBE_FDIRDIP4M 0x0EE3C
423 #define IXGBE_FDIRSIP4M 0x0EE40
424 #define IXGBE_FDIRTCPM 0x0EE44
425 #define IXGBE_FDIRUDPM 0x0EE48
426 #define IXGBE_FDIRSCTPM 0x0EE78
427 #define IXGBE_FDIRIP6M 0x0EE74
428 #define IXGBE_FDIRM 0x0EE70
429
430
431 #define IXGBE_FDIRFREE 0x0EE38
432 #define IXGBE_FDIRLEN 0x0EE4C
433 #define IXGBE_FDIRUSTAT 0x0EE50
434 #define IXGBE_FDIRFSTAT 0x0EE54
435 #define IXGBE_FDIRMATCH 0x0EE58
436 #define IXGBE_FDIRMISS 0x0EE5C
437
438
439 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4))
440 #define IXGBE_FDIRIPSA 0x0EE18
441 #define IXGBE_FDIRIPDA 0x0EE1C
442 #define IXGBE_FDIRPORT 0x0EE20
443 #define IXGBE_FDIRVLAN 0x0EE24
444 #define IXGBE_FDIRHASH 0x0EE28
445 #define IXGBE_FDIRCMD 0x0EE2C
446
447
448 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40))
449 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
450 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
451 #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
452 #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
453 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
454 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
455 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
456 #define IXGBE_DTXCTL 0x07E00
457
458 #define IXGBE_DMATXCTL 0x04A80
459 #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4))
460 #define IXGBE_PFDTXGSWC 0x08220
461 #define IXGBE_DTXMXSZRQ 0x08100
462 #define IXGBE_DTXTCPFLGL 0x04A88
463 #define IXGBE_DTXTCPFLGH 0x04A8C
464 #define IXGBE_LBDRPEN 0x0CA00
465 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4))
466
467 #define IXGBE_DMATXCTL_TE 0x1
468 #define IXGBE_DMATXCTL_NS 0x2
469 #define IXGBE_DMATXCTL_GDV 0x8
470 #define IXGBE_DMATXCTL_MDP_EN 0x20
471 #define IXGBE_DMATXCTL_MBINTEN 0x40
472 #define IXGBE_DMATXCTL_VT_SHIFT 16
473
474 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1
475
476
477 #define IXGBE_SPOOF_MACAS_MASK 0xFF
478 #define IXGBE_SPOOF_VLANAS_MASK 0xFF00
479 #define IXGBE_SPOOF_VLANAS_SHIFT 8
480 #define IXGBE_SPOOF_ETHERTYPEAS 0xFF000000
481 #define IXGBE_SPOOF_ETHERTYPEAS_SHIFT 16
482 #define IXGBE_PFVFSPOOF_REG_COUNT 8
483
484 #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4))
485
486 #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
487 #define IXGBE_TIPG 0x0CB00
488 #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4))
489 #define IXGBE_MNGTXMAP 0x0CD10
490 #define IXGBE_TIPG_FIBER_DEFAULT 3
491 #define IXGBE_TXPBSIZE_SHIFT 10
492
493
494 #define IXGBE_WUC 0x05800
495 #define IXGBE_WUFC 0x05808
496 #define IXGBE_WUS 0x05810
497 #define IXGBE_IPAV 0x05838
498 #define IXGBE_IP4AT 0x05840
499 #define IXGBE_IP6AT 0x05880
500
501 #define IXGBE_WUPL 0x05900
502 #define IXGBE_WUPM 0x05A00
503 #define IXGBE_VXLANCTRL 0x0000507C
504 #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100))
505 #define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100))
506
507
508
509 #define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff
510 #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000
511 #define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff
512
513 #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16
514
515 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
516 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
517
518
519 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
520 #define IXGBE_FHFT_LENGTH_OFFSET 0xFC
521 #define IXGBE_FHFT_LENGTH_MASK 0x0FF
522
523
524
525 #define IXGBE_WUC_PME_EN 0x00000002
526 #define IXGBE_WUC_PME_STATUS 0x00000004
527 #define IXGBE_WUC_WKEN 0x00000010
528
529
530 #define IXGBE_WUFC_LNKC 0x00000001
531 #define IXGBE_WUFC_MAG 0x00000002
532 #define IXGBE_WUFC_EX 0x00000004
533 #define IXGBE_WUFC_MC 0x00000008
534 #define IXGBE_WUFC_BC 0x00000010
535 #define IXGBE_WUFC_ARP 0x00000020
536 #define IXGBE_WUFC_IPV4 0x00000040
537 #define IXGBE_WUFC_IPV6 0x00000080
538 #define IXGBE_WUFC_MNG 0x00000100
539
540 #define IXGBE_WUFC_IGNORE_TCO 0x00008000
541 #define IXGBE_WUFC_FLX0 0x00010000
542 #define IXGBE_WUFC_FLX1 0x00020000
543 #define IXGBE_WUFC_FLX2 0x00040000
544 #define IXGBE_WUFC_FLX3 0x00080000
545 #define IXGBE_WUFC_FLX4 0x00100000
546 #define IXGBE_WUFC_FLX5 0x00200000
547 #define IXGBE_WUFC_FLX_FILTERS 0x000F0000
548 #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000
549 #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF
550 #define IXGBE_WUFC_FLX_OFFSET 16
551
552
553 #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
554 #define IXGBE_WUS_MAG IXGBE_WUFC_MAG
555 #define IXGBE_WUS_EX IXGBE_WUFC_EX
556 #define IXGBE_WUS_MC IXGBE_WUFC_MC
557 #define IXGBE_WUS_BC IXGBE_WUFC_BC
558 #define IXGBE_WUS_ARP IXGBE_WUFC_ARP
559 #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
560 #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
561 #define IXGBE_WUS_MNG IXGBE_WUFC_MNG
562 #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
563 #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
564 #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
565 #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
566 #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
567 #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
568 #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
569
570
571 #define IXGBE_WUPL_LENGTH_MASK 0xFFFF
572
573
574 #define MAX_TRAFFIC_CLASS 8
575 #define X540_TRAFFIC_CLASS 4
576 #define DEF_TRAFFIC_CLASS 1
577 #define IXGBE_RMCS 0x03D00
578 #define IXGBE_DPMCS 0x07F40
579 #define IXGBE_PDPMCS 0x0CD00
580 #define IXGBE_RUPPBMR 0x050A0
581 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4))
582 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4))
583 #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40))
584 #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40))
585 #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4))
586 #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4))
587
588
589 #define IXGBE_SECTXCTRL 0x08800
590 #define IXGBE_SECTXSTAT 0x08804
591 #define IXGBE_SECTXBUFFAF 0x08808
592 #define IXGBE_SECTXMINIFG 0x08810
593 #define IXGBE_SECRXCTRL 0x08D00
594 #define IXGBE_SECRXSTAT 0x08D04
595
596
597 #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
598 #define IXGBE_SECTXCTRL_TX_DIS 0x00000002
599 #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
600
601 #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
602 #define IXGBE_SECTXSTAT_SECTX_OFF_DIS 0x00000002
603 #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000004
604
605 #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
606 #define IXGBE_SECRXCTRL_RX_DIS 0x00000002
607
608 #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
609 #define IXGBE_SECRXSTAT_SECRX_OFF_DIS 0x00000002
610 #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000004
611
612
613 #define IXGBE_LSECTXCAP 0x08A00
614 #define IXGBE_LSECRXCAP 0x08F00
615 #define IXGBE_LSECTXCTRL 0x08A04
616 #define IXGBE_LSECTXSCL 0x08A08
617 #define IXGBE_LSECTXSCH 0x08A0C
618 #define IXGBE_LSECTXSA 0x08A10
619 #define IXGBE_LSECTXPN0 0x08A14
620 #define IXGBE_LSECTXPN1 0x08A18
621 #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n)))
622 #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n)))
623 #define IXGBE_LSECRXCTRL 0x08F04
624 #define IXGBE_LSECRXSCL 0x08F08
625 #define IXGBE_LSECRXSCH 0x08F0C
626 #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i)))
627 #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i)))
628 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
629 #define IXGBE_LSECTXUT 0x08A3C
630 #define IXGBE_LSECTXPKTE 0x08A40
631 #define IXGBE_LSECTXPKTP 0x08A44
632 #define IXGBE_LSECTXOCTE 0x08A48
633 #define IXGBE_LSECTXOCTP 0x08A4C
634 #define IXGBE_LSECRXUT 0x08F40
635 #define IXGBE_LSECRXOCTD 0x08F44
636 #define IXGBE_LSECRXOCTV 0x08F48
637 #define IXGBE_LSECRXBAD 0x08F4C
638 #define IXGBE_LSECRXNOSCI 0x08F50
639 #define IXGBE_LSECRXUNSCI 0x08F54
640 #define IXGBE_LSECRXUNCH 0x08F58
641 #define IXGBE_LSECRXDELAY 0x08F5C
642 #define IXGBE_LSECRXLATE 0x08F60
643 #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n)))
644 #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n)))
645 #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n)))
646 #define IXGBE_LSECRXUNSA 0x08F7C
647 #define IXGBE_LSECRXNUSA 0x08F80
648
649
650 #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
651 #define IXGBE_LSECTXCAP_SUM_SHIFT 16
652 #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
653 #define IXGBE_LSECRXCAP_SUM_SHIFT 16
654
655 #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
656 #define IXGBE_LSECTXCTRL_DISABLE 0x0
657 #define IXGBE_LSECTXCTRL_AUTH 0x1
658 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
659 #define IXGBE_LSECTXCTRL_AISCI 0x00000020
660 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
661 #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
662
663 #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
664 #define IXGBE_LSECRXCTRL_EN_SHIFT 2
665 #define IXGBE_LSECRXCTRL_DISABLE 0x0
666 #define IXGBE_LSECRXCTRL_CHECK 0x1
667 #define IXGBE_LSECRXCTRL_STRICT 0x2
668 #define IXGBE_LSECRXCTRL_DROP 0x3
669 #define IXGBE_LSECRXCTRL_PLSH 0x00000040
670 #define IXGBE_LSECRXCTRL_RP 0x00000080
671 #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
672
673
674 #define IXGBE_IPSTXIDX 0x08900
675 #define IXGBE_IPSTXSALT 0x08904
676 #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i)))
677 #define IXGBE_IPSRXIDX 0x08E00
678 #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i)))
679 #define IXGBE_IPSRXSPI 0x08E14
680 #define IXGBE_IPSRXIPIDX 0x08E18
681 #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i)))
682 #define IXGBE_IPSRXSALT 0x08E2C
683 #define IXGBE_IPSRXMOD 0x08E30
684
685 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
686
687
688 #define IXGBE_RTRPCS 0x02430
689 #define IXGBE_RTTDCS 0x04900
690 #define IXGBE_RTTDCS_ARBDIS 0x00000040
691 #define IXGBE_RTTPCS 0x0CD00
692 #define IXGBE_RTRUP2TC 0x03020
693 #define IXGBE_RTTUP2TC 0x0C800
694 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4))
695 #define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4))
696 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4))
697 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4))
698 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4))
699 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4))
700 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4))
701 #define IXGBE_RTTDQSEL 0x04904
702 #define IXGBE_RTTDT1C 0x04908
703 #define IXGBE_RTTDT1S 0x0490C
704 #define IXGBE_RTTQCNCR 0x08B00
705 #define IXGBE_RTTQCNTG 0x04A90
706 #define IXGBE_RTTBCNRD 0x0498C
707 #define IXGBE_RTTQCNRR 0x0498C
708 #define IXGBE_RTTDTECC 0x04990
709 #define IXGBE_RTTDTECC_NO_BCN 0x00000100
710 #define IXGBE_RTTBCNRC 0x04984
711 #define IXGBE_RTTBCNRC_RS_ENA 0x80000000
712 #define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
713 #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
714 #define IXGBE_RTTBCNRC_RF_INT_MASK \
715 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
716 #define IXGBE_RTTBCNRM 0x04980
717 #define IXGBE_RTTQCNRM 0x04980
718
719
720 #define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
721
722 #define IXGBE_FCPTRL 0x02410
723 #define IXGBE_FCPTRH 0x02414
724 #define IXGBE_FCBUFF 0x02418
725 #define IXGBE_FCDMARW 0x02420
726 #define IXGBE_FCINVST0 0x03FC0
727 #define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
728 #define IXGBE_FCBUFF_VALID BIT(0)
729 #define IXGBE_FCBUFF_BUFFSIZE (3u << 3)
730 #define IXGBE_FCBUFF_WRCONTX BIT(7)
731 #define IXGBE_FCBUFF_BUFFCNT 0x0000ff00
732 #define IXGBE_FCBUFF_OFFSET 0xffff0000
733 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
734 #define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
735 #define IXGBE_FCBUFF_OFFSET_SHIFT 16
736 #define IXGBE_FCDMARW_WE BIT(14)
737 #define IXGBE_FCDMARW_RE BIT(15)
738 #define IXGBE_FCDMARW_FCOESEL 0x000001ff
739 #define IXGBE_FCDMARW_LASTSIZE 0xffff0000
740 #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
741
742
743 #define IXGBE_TEOFF 0x04A94
744 #define IXGBE_TSOFF 0x04A98
745 #define IXGBE_REOFF 0x05158
746 #define IXGBE_RSOFF 0x051F8
747
748 #define IXGBE_FCDFC(_i, _j) (0x28000 + ((_i) * 0x4) + ((_j) * 0x10))
749 #define IXGBE_FCDFCD(_i) (0x30000 + ((_i) * 0x4))
750
751 #define IXGBE_FCFLT 0x05108
752 #define IXGBE_FCFLTRW 0x05110
753 #define IXGBE_FCPARAM 0x051d8
754 #define IXGBE_FCFLT_VALID BIT(0)
755 #define IXGBE_FCFLT_FIRST BIT(1)
756 #define IXGBE_FCFLT_SEQID 0x00ff0000
757 #define IXGBE_FCFLT_SEQCNT 0xff000000
758 #define IXGBE_FCFLTRW_RVALDT BIT(13)
759 #define IXGBE_FCFLTRW_WE BIT(14)
760 #define IXGBE_FCFLTRW_RE BIT(15)
761
762 #define IXGBE_FCRXCTRL 0x05100
763 #define IXGBE_FCRXCTRL_FCOELLI BIT(0)
764 #define IXGBE_FCRXCTRL_SAVBAD BIT(1)
765 #define IXGBE_FCRXCTRL_FRSTRDH BIT(2)
766 #define IXGBE_FCRXCTRL_LASTSEQH BIT(3)
767 #define IXGBE_FCRXCTRL_ALLH BIT(4)
768 #define IXGBE_FCRXCTRL_FRSTSEQH BIT(5)
769 #define IXGBE_FCRXCTRL_ICRC BIT(6)
770 #define IXGBE_FCRXCTRL_FCCRCBO BIT(7)
771 #define IXGBE_FCRXCTRL_FCOEVER 0x00000f00
772 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
773
774 #define IXGBE_FCRECTL 0x0ED00
775 #define IXGBE_FCRETA0 0x0ED10
776 #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4))
777 #define IXGBE_FCRECTL_ENA 0x1
778 #define IXGBE_FCRETA_SIZE 8
779 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f
780 #define IXGBE_FCRETA_SIZE_X550 32
781
782 #define IXGBE_FCRETA_ENTRY_HIGH_MASK 0x007F0000
783 #define IXGBE_FCRETA_ENTRY_HIGH_SHIFT 16
784
785
786 #define IXGBE_CRCERRS 0x04000
787 #define IXGBE_ILLERRC 0x04004
788 #define IXGBE_ERRBC 0x04008
789 #define IXGBE_MSPDC 0x04010
790 #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4))
791 #define IXGBE_MLFC 0x04034
792 #define IXGBE_MRFC 0x04038
793 #define IXGBE_RLEC 0x04040
794 #define IXGBE_LXONTXC 0x03F60
795 #define IXGBE_LXONRXC 0x0CF60
796 #define IXGBE_LXOFFTXC 0x03F68
797 #define IXGBE_LXOFFRXC 0x0CF68
798 #define IXGBE_LXONRXCNT 0x041A4
799 #define IXGBE_LXOFFRXCNT 0x041A8
800 #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4))
801 #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4))
802 #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4))
803 #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4))
804 #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4))
805 #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4))
806 #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4))
807 #define IXGBE_PRC64 0x0405C
808 #define IXGBE_PRC127 0x04060
809 #define IXGBE_PRC255 0x04064
810 #define IXGBE_PRC511 0x04068
811 #define IXGBE_PRC1023 0x0406C
812 #define IXGBE_PRC1522 0x04070
813 #define IXGBE_GPRC 0x04074
814 #define IXGBE_BPRC 0x04078
815 #define IXGBE_MPRC 0x0407C
816 #define IXGBE_GPTC 0x04080
817 #define IXGBE_GORCL 0x04088
818 #define IXGBE_GORCH 0x0408C
819 #define IXGBE_GOTCL 0x04090
820 #define IXGBE_GOTCH 0x04094
821 #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4))
822 #define IXGBE_RUC 0x040A4
823 #define IXGBE_RFC 0x040A8
824 #define IXGBE_ROC 0x040AC
825 #define IXGBE_RJC 0x040B0
826 #define IXGBE_MNGPRC 0x040B4
827 #define IXGBE_MNGPDC 0x040B8
828 #define IXGBE_MNGPTC 0x0CF90
829 #define IXGBE_TORL 0x040C0
830 #define IXGBE_TORH 0x040C4
831 #define IXGBE_TPR 0x040D0
832 #define IXGBE_TPT 0x040D4
833 #define IXGBE_PTC64 0x040D8
834 #define IXGBE_PTC127 0x040DC
835 #define IXGBE_PTC255 0x040E0
836 #define IXGBE_PTC511 0x040E4
837 #define IXGBE_PTC1023 0x040E8
838 #define IXGBE_PTC1522 0x040EC
839 #define IXGBE_MPTC 0x040F0
840 #define IXGBE_BPTC 0x040F4
841 #define IXGBE_XEC 0x04120
842 #define IXGBE_SSVPC 0x08780
843
844 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
845 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
846 (0x08600 + ((_i) * 4)))
847 #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
848
849 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40))
850 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40))
851 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40))
852 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40))
853 #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40))
854 #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40))
855 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40))
856 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8))
857 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8))
858 #define IXGBE_FCCRC 0x05118
859 #define IXGBE_FCOERPDC 0x0241C
860 #define IXGBE_FCLAST 0x02424
861 #define IXGBE_FCOEPRC 0x02428
862 #define IXGBE_FCOEDWRC 0x0242C
863 #define IXGBE_FCOEPTC 0x08784
864 #define IXGBE_FCOEDWTC 0x08788
865 #define IXGBE_O2BGPTC 0x041C4
866 #define IXGBE_O2BSPC 0x087B0
867 #define IXGBE_B2OSPC 0x041C0
868 #define IXGBE_B2OGPRC 0x02F90
869 #define IXGBE_PCRC8ECL 0x0E810
870 #define IXGBE_PCRC8ECH 0x0E811
871 #define IXGBE_PCRC8ECH_MASK 0x1F
872 #define IXGBE_LDPCECL 0x0E820
873 #define IXGBE_LDPCECH 0x0E821
874
875
876 #define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
877
878 #define IXGBE_MDIO_XENPAK_LASI_STATUS 0x9005
879 #define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1
880
881 #define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4
882
883 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7
884 #define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK 0x6
885 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0
886 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1
887 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2
888 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3
889 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4
890 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5
891 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6
892 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7
893 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB 0x4
894 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB 0x6
895
896 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400
897 #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17
898 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000
899 #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000
900 #define IXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400
901 #define IXGBE_MII_5GBASE_T_ADVERTISE 0x0800
902 #define IXGBE_MII_RESTART 0x200
903 #define IXGBE_MII_AUTONEG_LINK_UP 0x04
904 #define IXGBE_MII_AUTONEG_REG 0x0
905
906
907 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4))
908 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4))
909 #define IXGBE_MANC 0x05820
910 #define IXGBE_MFVAL 0x05824
911 #define IXGBE_MANC2H 0x05860
912 #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4))
913 #define IXGBE_MIPAF 0x058B0
914 #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8))
915 #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8))
916 #define IXGBE_FTFT 0x09400
917 #define IXGBE_METF(_i) (0x05190 + ((_i) * 4))
918 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4))
919 #define IXGBE_LSWFW 0x15014
920
921
922 #define IXGBE_MANC_RCV_TCO_EN 0x00020000
923
924
925 #define IXGBE_FWSM_MODE_MASK 0xE
926 #define IXGBE_FWSM_FW_MODE_PT 0x4
927 #define IXGBE_FWSM_FW_NVM_RECOVERY_MODE BIT(5)
928 #define IXGBE_FWSM_EXT_ERR_IND_MASK 0x01F80000
929 #define IXGBE_FWSM_FW_VAL_BIT BIT(15)
930
931
932 #define IXGBE_HICR 0x15F00
933 #define IXGBE_FWSTS 0x15F0C
934 #define IXGBE_HSMC0R 0x15F04
935 #define IXGBE_HSMC1R 0x15F08
936 #define IXGBE_SWSR 0x15F10
937 #define IXGBE_HFDR 0x15FE8
938 #define IXGBE_FLEX_MNG 0x15800
939
940 #define IXGBE_HICR_EN 0x01
941
942 #define IXGBE_HICR_C 0x02
943 #define IXGBE_HICR_SV 0x04
944 #define IXGBE_HICR_FW_RESET_ENABLE 0x40
945 #define IXGBE_HICR_FW_RESET 0x80
946
947
948 #define IXGBE_GCR 0x11000
949 #define IXGBE_GTV 0x11004
950 #define IXGBE_FUNCTAG 0x11008
951 #define IXGBE_GLT 0x1100C
952 #define IXGBE_GSCL_1 0x11010
953 #define IXGBE_GSCL_2 0x11014
954 #define IXGBE_GSCL_3 0x11018
955 #define IXGBE_GSCL_4 0x1101C
956 #define IXGBE_GSCN_0 0x11020
957 #define IXGBE_GSCN_1 0x11024
958 #define IXGBE_GSCN_2 0x11028
959 #define IXGBE_GSCN_3 0x1102C
960 #define IXGBE_FACTPS_8259X 0x10150
961 #define IXGBE_FACTPS_X540 IXGBE_FACTPS_8259X
962 #define IXGBE_FACTPS_X550 IXGBE_FACTPS_8259X
963 #define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS_8259X
964 #define IXGBE_FACTPS_X550EM_a 0x15FEC
965 #define IXGBE_FACTPS(_hw) IXGBE_BY_MAC((_hw), FACTPS)
966
967 #define IXGBE_PCIEANACTL 0x11040
968 #define IXGBE_SWSM_8259X 0x10140
969 #define IXGBE_SWSM_X540 IXGBE_SWSM_8259X
970 #define IXGBE_SWSM_X550 IXGBE_SWSM_8259X
971 #define IXGBE_SWSM_X550EM_x IXGBE_SWSM_8259X
972 #define IXGBE_SWSM_X550EM_a 0x15F70
973 #define IXGBE_SWSM(_hw) IXGBE_BY_MAC((_hw), SWSM)
974 #define IXGBE_FWSM_8259X 0x10148
975 #define IXGBE_FWSM_X540 IXGBE_FWSM_8259X
976 #define IXGBE_FWSM_X550 IXGBE_FWSM_8259X
977 #define IXGBE_FWSM_X550EM_x IXGBE_FWSM_8259X
978 #define IXGBE_FWSM_X550EM_a 0x15F74
979 #define IXGBE_FWSM(_hw) IXGBE_BY_MAC((_hw), FWSM)
980 #define IXGBE_GSSR 0x10160
981 #define IXGBE_MREVID 0x11064
982 #define IXGBE_DCA_ID 0x11070
983 #define IXGBE_DCA_CTRL 0x11074
984 #define IXGBE_SWFW_SYNC_8259X IXGBE_GSSR
985 #define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC_8259X
986 #define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC_8259X
987 #define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC_8259X
988 #define IXGBE_SWFW_SYNC_X550EM_a 0x15F78
989 #define IXGBE_SWFW_SYNC(_hw) IXGBE_BY_MAC((_hw), SWFW_SYNC)
990
991
992 #define IXGBE_GCR_EXT 0x11050
993 #define IXGBE_GSCL_5_82599 0x11030
994 #define IXGBE_GSCL_6_82599 0x11034
995 #define IXGBE_GSCL_7_82599 0x11038
996 #define IXGBE_GSCL_8_82599 0x1103C
997 #define IXGBE_PHYADR_82599 0x11040
998 #define IXGBE_PHYDAT_82599 0x11044
999 #define IXGBE_PHYCTL_82599 0x11048
1000 #define IXGBE_PBACLR_82599 0x11068
1001
1002 #define IXGBE_CIAA_8259X 0x11088
1003 #define IXGBE_CIAA_X540 IXGBE_CIAA_8259X
1004 #define IXGBE_CIAA_X550 0x11508
1005 #define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550
1006 #define IXGBE_CIAA_X550EM_a IXGBE_CIAA_X550
1007 #define IXGBE_CIAA(_hw) IXGBE_BY_MAC((_hw), CIAA)
1008
1009 #define IXGBE_CIAD_8259X 0x1108C
1010 #define IXGBE_CIAD_X540 IXGBE_CIAD_8259X
1011 #define IXGBE_CIAD_X550 0x11510
1012 #define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550
1013 #define IXGBE_CIAD_X550EM_a IXGBE_CIAD_X550
1014 #define IXGBE_CIAD(_hw) IXGBE_BY_MAC((_hw), CIAD)
1015
1016 #define IXGBE_PICAUSE 0x110B0
1017 #define IXGBE_PIENA 0x110B8
1018 #define IXGBE_CDQ_MBR_82599 0x110B4
1019 #define IXGBE_PCIESPARE 0x110BC
1020 #define IXGBE_MISC_REG_82599 0x110F0
1021 #define IXGBE_ECC_CTRL_0_82599 0x11100
1022 #define IXGBE_ECC_CTRL_1_82599 0x11104
1023 #define IXGBE_ECC_STATUS_82599 0x110E0
1024 #define IXGBE_BAR_CTRL_82599 0x110F4
1025
1026
1027 #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
1028 #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
1029 #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
1030 #define IXGBE_GCR_CAP_VER2 0x00040000
1031
1032 #define IXGBE_GCR_EXT_MSIX_EN 0x80000000
1033 #define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000
1034 #define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
1035 #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
1036 #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
1037 #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
1038 IXGBE_GCR_EXT_VT_MODE_64)
1039
1040
1041 #define IXGBE_TSYNCRXCTL 0x05188
1042 #define IXGBE_TSYNCTXCTL 0x08C00
1043 #define IXGBE_RXSTMPL 0x051E8
1044 #define IXGBE_RXSTMPH 0x051A4
1045 #define IXGBE_RXSATRL 0x051A0
1046 #define IXGBE_RXSATRH 0x051A8
1047 #define IXGBE_RXMTRL 0x05120
1048 #define IXGBE_TXSTMPL 0x08C04
1049 #define IXGBE_TXSTMPH 0x08C08
1050 #define IXGBE_SYSTIML 0x08C0C
1051 #define IXGBE_SYSTIMH 0x08C10
1052 #define IXGBE_SYSTIMR 0x08C58
1053 #define IXGBE_TIMINCA 0x08C14
1054 #define IXGBE_TIMADJL 0x08C18
1055 #define IXGBE_TIMADJH 0x08C1C
1056 #define IXGBE_TSAUXC 0x08C20
1057 #define IXGBE_TRGTTIML0 0x08C24
1058 #define IXGBE_TRGTTIMH0 0x08C28
1059 #define IXGBE_TRGTTIML1 0x08C2C
1060 #define IXGBE_TRGTTIMH1 0x08C30
1061 #define IXGBE_CLKTIML 0x08C34
1062 #define IXGBE_CLKTIMH 0x08C38
1063 #define IXGBE_FREQOUT0 0x08C34
1064 #define IXGBE_FREQOUT1 0x08C38
1065 #define IXGBE_AUXSTMPL0 0x08C3C
1066 #define IXGBE_AUXSTMPH0 0x08C40
1067 #define IXGBE_AUXSTMPL1 0x08C44
1068 #define IXGBE_AUXSTMPH1 0x08C48
1069 #define IXGBE_TSIM 0x08C68
1070 #define IXGBE_TSSDP 0x0003C
1071
1072
1073 #define IXGBE_RDSTATCTL 0x02C20
1074 #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4))
1075 #define IXGBE_RDHMPN 0x02F08
1076 #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
1077 #define IXGBE_RDPROBE 0x02F20
1078 #define IXGBE_RDMAM 0x02F30
1079 #define IXGBE_RDMAD 0x02F34
1080 #define IXGBE_TDSTATCTL 0x07C20
1081 #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4))
1082 #define IXGBE_TDHMPN 0x07F08
1083 #define IXGBE_TDHMPN2 0x082FC
1084 #define IXGBE_TXDESCIC 0x082CC
1085 #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
1086 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
1087 #define IXGBE_TDPROBE 0x07F20
1088 #define IXGBE_TXBUFCTRL 0x0C600
1089 #define IXGBE_TXBUFDATA(_i) (0x0C610 + ((_i) * 4))
1090 #define IXGBE_RXBUFCTRL 0x03600
1091 #define IXGBE_RXBUFDATA(_i) (0x03610 + ((_i) * 4))
1092 #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4))
1093 #define IXGBE_RFVAL 0x050A4
1094 #define IXGBE_MDFTC1 0x042B8
1095 #define IXGBE_MDFTC2 0x042C0
1096 #define IXGBE_MDFTFIFO1 0x042C4
1097 #define IXGBE_MDFTFIFO2 0x042C8
1098 #define IXGBE_MDFTS 0x042CC
1099 #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4))
1100 #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4))
1101 #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4))
1102 #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4))
1103 #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4))
1104 #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4))
1105 #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4))
1106 #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4))
1107 #define IXGBE_PCIEECCCTL 0x1106C
1108 #define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4))
1109 #define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4))
1110 #define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4))
1111 #define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4))
1112 #define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4))
1113 #define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4))
1114 #define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4))
1115 #define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4))
1116 #define IXGBE_PCIEECCCTL0 0x11100
1117 #define IXGBE_PCIEECCCTL1 0x11104
1118 #define IXGBE_RXDBUECC 0x03F70
1119 #define IXGBE_TXDBUECC 0x0CF70
1120 #define IXGBE_RXDBUEST 0x03F74
1121 #define IXGBE_TXDBUEST 0x0CF74
1122 #define IXGBE_PBTXECC 0x0C300
1123 #define IXGBE_PBRXECC 0x03300
1124 #define IXGBE_GHECCR 0x110B0
1125
1126
1127 #define IXGBE_PCS1GCFIG 0x04200
1128 #define IXGBE_PCS1GLCTL 0x04208
1129 #define IXGBE_PCS1GLSTA 0x0420C
1130 #define IXGBE_PCS1GDBG0 0x04210
1131 #define IXGBE_PCS1GDBG1 0x04214
1132 #define IXGBE_PCS1GANA 0x04218
1133 #define IXGBE_PCS1GANLP 0x0421C
1134 #define IXGBE_PCS1GANNP 0x04220
1135 #define IXGBE_PCS1GANLPNP 0x04224
1136 #define IXGBE_HLREG0 0x04240
1137 #define IXGBE_HLREG1 0x04244
1138 #define IXGBE_PAP 0x04248
1139 #define IXGBE_MACA 0x0424C
1140 #define IXGBE_APAE 0x04250
1141 #define IXGBE_ARD 0x04254
1142 #define IXGBE_AIS 0x04258
1143 #define IXGBE_MSCA 0x0425C
1144 #define IXGBE_MSRWD 0x04260
1145 #define IXGBE_MLADD 0x04264
1146 #define IXGBE_MHADD 0x04268
1147 #define IXGBE_MAXFRS 0x04268
1148 #define IXGBE_TREG 0x0426C
1149 #define IXGBE_PCSS1 0x04288
1150 #define IXGBE_PCSS2 0x0428C
1151 #define IXGBE_XPCSS 0x04290
1152 #define IXGBE_MFLCN 0x04294
1153 #define IXGBE_SERDESC 0x04298
1154 #define IXGBE_MAC_SGMII_BUSY 0x04298
1155 #define IXGBE_MACS 0x0429C
1156 #define IXGBE_AUTOC 0x042A0
1157 #define IXGBE_LINKS 0x042A4
1158 #define IXGBE_LINKS2 0x04324
1159 #define IXGBE_AUTOC2 0x042A8
1160 #define IXGBE_AUTOC3 0x042AC
1161 #define IXGBE_ANLP1 0x042B0
1162 #define IXGBE_ANLP2 0x042B4
1163 #define IXGBE_MACC 0x04330
1164 #define IXGBE_ATLASCTL 0x04800
1165 #define IXGBE_MMNGC 0x042D0
1166 #define IXGBE_ANLPNP1 0x042D4
1167 #define IXGBE_ANLPNP2 0x042D8
1168 #define IXGBE_KRPCSFC 0x042E0
1169 #define IXGBE_KRPCSS 0x042E4
1170 #define IXGBE_FECS1 0x042E8
1171 #define IXGBE_FECS2 0x042EC
1172 #define IXGBE_SMADARCTL 0x14F10
1173 #define IXGBE_MPVC 0x04318
1174 #define IXGBE_SGMIIC 0x04314
1175
1176
1177 #define IXGBE_RXNFGPC 0x041B0
1178 #define IXGBE_RXNFGBCL 0x041B4
1179 #define IXGBE_RXNFGBCH 0x041B8
1180 #define IXGBE_RXDGPC 0x02F50
1181 #define IXGBE_RXDGBCL 0x02F54
1182 #define IXGBE_RXDGBCH 0x02F58
1183 #define IXGBE_RXDDGPC 0x02F5C
1184 #define IXGBE_RXDDGBCL 0x02F60
1185 #define IXGBE_RXDDGBCH 0x02F64
1186 #define IXGBE_RXLPBKGPC 0x02F68
1187 #define IXGBE_RXLPBKGBCL 0x02F6C
1188 #define IXGBE_RXLPBKGBCH 0x02F70
1189 #define IXGBE_RXDLPBKGPC 0x02F74
1190 #define IXGBE_RXDLPBKGBCL 0x02F78
1191 #define IXGBE_RXDLPBKGBCH 0x02F7C
1192 #define IXGBE_TXDGPC 0x087A0
1193 #define IXGBE_TXDGBCL 0x087A4
1194 #define IXGBE_TXDGBCH 0x087A8
1195
1196 #define IXGBE_RXDSTATCTRL 0x02F40
1197
1198
1199 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
1200
1201
1202 #define IXGBE_CORECTL 0x014F00
1203
1204 #define IXGBE_BARCTRL 0x110F4
1205 #define IXGBE_BARCTRL_FLSIZE 0x0700
1206 #define IXGBE_BARCTRL_FLSIZE_SHIFT 8
1207 #define IXGBE_BARCTRL_CSRSIZE 0x2000
1208
1209
1210 #define IXGBE_RSCCTL_RSCEN 0x01
1211 #define IXGBE_RSCCTL_MAXDESC_1 0x00
1212 #define IXGBE_RSCCTL_MAXDESC_4 0x04
1213 #define IXGBE_RSCCTL_MAXDESC_8 0x08
1214 #define IXGBE_RSCCTL_MAXDESC_16 0x0C
1215
1216
1217 #define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
1218 #define IXGBE_RSCDBU_RSCACKDIS 0x00000080
1219
1220
1221 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000
1222 #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002
1223 #define IXGBE_RDRXCTL_PSP 0x00000004
1224 #define IXGBE_RDRXCTL_MVMEN 0x00000020
1225 #define IXGBE_RDRXCTL_DMAIDONE 0x00000008
1226 #define IXGBE_RDRXCTL_AGGDIS 0x00010000
1227 #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000
1228 #define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000
1229 #define IXGBE_RDRXCTL_RSCACKC 0x02000000
1230 #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000
1231 #define IXGBE_RDRXCTL_MBINTEN 0x10000000
1232 #define IXGBE_RDRXCTL_MDP_EN 0x20000000
1233
1234
1235 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1236 #define IXGBE_RQTC_TC0_MASK (0x7 << 0)
1237 #define IXGBE_RQTC_TC1_MASK (0x7 << 4)
1238 #define IXGBE_RQTC_TC2_MASK (0x7 << 8)
1239 #define IXGBE_RQTC_TC3_MASK (0x7 << 12)
1240 #define IXGBE_RQTC_TC4_MASK (0x7 << 16)
1241 #define IXGBE_RQTC_TC5_MASK (0x7 << 20)
1242 #define IXGBE_RQTC_TC6_MASK (0x7 << 24)
1243 #define IXGBE_RQTC_TC7_MASK (0x7 << 28)
1244
1245
1246 #define IXGBE_PSRTYPE_RQPL_MASK 0x7
1247 #define IXGBE_PSRTYPE_RQPL_SHIFT 29
1248
1249
1250 #define IXGBE_CTRL_GIO_DIS 0x00000004
1251 #define IXGBE_CTRL_LNK_RST 0x00000008
1252 #define IXGBE_CTRL_RST 0x04000000
1253 #define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1254
1255
1256 #define IXGBE_FACTPS_MNGCG 0x20000000
1257 #define IXGBE_FACTPS_LFS 0x40000000
1258
1259
1260 #define IXGBE_MHADD_MFS_MASK 0xFFFF0000
1261 #define IXGBE_MHADD_MFS_SHIFT 16
1262
1263
1264 #define IXGBE_CTRL_EXT_PFRSTD 0x00004000
1265 #define IXGBE_CTRL_EXT_NS_DIS 0x00010000
1266 #define IXGBE_CTRL_EXT_RO_DIS 0x00020000
1267 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000
1268
1269
1270 #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000
1271 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001
1272
1273 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00
1274 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02
1275
1276 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F
1277 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000
1278 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24
1279 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5)
1280 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6)
1281 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7)
1282 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9)
1283 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13)
1284 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15)
1285
1286 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F
1287 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000
1288 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24
1289 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5)
1290 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9)
1291 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11)
1292 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13)
1293 #define IXGBE_DCA_MAX_QUEUES_82598 16
1294
1295
1296 #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF
1297 #define IXGBE_MSCA_NP_ADDR_SHIFT 0
1298 #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000
1299 #define IXGBE_MSCA_DEV_TYPE_SHIFT 16
1300 #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000
1301 #define IXGBE_MSCA_PHY_ADDR_SHIFT 21
1302 #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000
1303 #define IXGBE_MSCA_OP_CODE_SHIFT 26
1304 #define IXGBE_MSCA_ADDR_CYCLE 0x00000000
1305 #define IXGBE_MSCA_WRITE 0x04000000
1306 #define IXGBE_MSCA_READ 0x0C000000
1307 #define IXGBE_MSCA_READ_AUTOINC 0x08000000
1308 #define IXGBE_MSCA_ST_CODE_MASK 0x30000000
1309 #define IXGBE_MSCA_ST_CODE_SHIFT 28
1310 #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000
1311 #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000
1312 #define IXGBE_MSCA_MDI_COMMAND 0x40000000
1313 #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000
1314
1315
1316 #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
1317 #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
1318 #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
1319 #define IXGBE_MSRWD_READ_DATA_SHIFT 16
1320
1321
1322 #define IXGBE_ATLAS_PDN_LPBK 0x24
1323 #define IXGBE_ATLAS_PDN_10G 0xB
1324 #define IXGBE_ATLAS_PDN_1G 0xC
1325 #define IXGBE_ATLAS_PDN_AN 0xD
1326
1327
1328 #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
1329 #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
1330 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
1331 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
1332 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
1333
1334
1335 #define IXGBE_CORECTL_WRITE_CMD 0x00010000
1336
1337
1338
1339 #define IXGBE_MDIO_ZERO_DEV_TYPE 0x0
1340 #define IXGBE_MDIO_PCS_DEV_TYPE 0x3
1341 #define IXGBE_TWINAX_DEV 1
1342
1343 #define IXGBE_MDIO_COMMAND_TIMEOUT 100
1344
1345 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008
1346 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010
1347 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
1348 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
1349
1350 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800
1351 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00
1352 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01
1353 #define IXGBE_MDIO_AUTO_NEG_VEN_LSC 0x1
1354 #define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C
1355
1356 #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800
1357 #define IXGBE_AUTO_NEG_LP_STATUS 0xE820
1358 #define IXGBE_AUTO_NEG_LP_1000BASE_CAP 0x8000
1359 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02
1360 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3
1361 #define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479
1362 #define IXGBE_MDIO_POWER_UP_STALL 0x8000
1363 #define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK 0xFF00
1364 #define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG 0xFC00
1365 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK 0xFF01
1366 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG 0xFC01
1367 #define IXGBE_MDIO_GLOBAL_ALARM_1 0xCC00
1368 #define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT 0x0010
1369 #define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL 0x4000
1370 #define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850
1371 #define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007
1372 #define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400
1373
1374 #define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000
1375 #define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4
1376 #define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1
1377 #define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200
1378 #define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000
1379 #define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010
1380
1381 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A
1382 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B
1383 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C
1384 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401
1385 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1
1386 #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9
1387 #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001
1388
1389
1390 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400
1391 #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17
1392 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000
1393 #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000
1394 #define IXGBE_MII_AUTONEG_REG 0x0
1395
1396 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1397 #define IXGBE_MAX_PHY_ADDR 32
1398
1399
1400 #define TN1010_PHY_ID 0x00A19410
1401 #define TNX_FW_REV 0xB
1402 #define X540_PHY_ID 0x01540200
1403 #define X550_PHY_ID2 0x01540223
1404 #define X550_PHY_ID3 0x01540221
1405 #define X557_PHY_ID 0x01540240
1406 #define X557_PHY_ID2 0x01540250
1407 #define QT2022_PHY_ID 0x0043A400
1408 #define ATH_PHY_ID 0x03429050
1409 #define AQ_FW_REV 0x20
1410
1411
1412 #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1413 #define IXGBE_PHY_INIT_END_NL 0xFFFF
1414 #define IXGBE_CONTROL_MASK_NL 0xF000
1415 #define IXGBE_DATA_MASK_NL 0x0FFF
1416 #define IXGBE_CONTROL_SHIFT_NL 12
1417 #define IXGBE_DELAY_NL 0
1418 #define IXGBE_DATA_NL 1
1419 #define IXGBE_CONTROL_NL 0x000F
1420 #define IXGBE_CONTROL_EOL_NL 0x0FFF
1421 #define IXGBE_CONTROL_SOL_NL 0x0000
1422
1423
1424 #define IXGBE_SDP0_GPIEN_8259X 0x00000001
1425 #define IXGBE_SDP1_GPIEN_8259X 0x00000002
1426 #define IXGBE_SDP2_GPIEN_8259X 0x00000004
1427 #define IXGBE_SDP0_GPIEN_X540 0x00000002
1428 #define IXGBE_SDP1_GPIEN_X540 0x00000004
1429 #define IXGBE_SDP2_GPIEN_X540 0x00000008
1430 #define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540
1431 #define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540
1432 #define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540
1433 #define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540
1434 #define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540
1435 #define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540
1436 #define IXGBE_SDP0_GPIEN_X550EM_a IXGBE_SDP0_GPIEN_X540
1437 #define IXGBE_SDP1_GPIEN_X550EM_a IXGBE_SDP1_GPIEN_X540
1438 #define IXGBE_SDP2_GPIEN_X550EM_a IXGBE_SDP2_GPIEN_X540
1439 #define IXGBE_SDP0_GPIEN(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN)
1440 #define IXGBE_SDP1_GPIEN(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN)
1441 #define IXGBE_SDP2_GPIEN(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN)
1442
1443 #define IXGBE_GPIE_MSIX_MODE 0x00000010
1444 #define IXGBE_GPIE_OCD 0x00000020
1445 #define IXGBE_GPIE_EIMEN 0x00000040
1446 #define IXGBE_GPIE_EIAME 0x40000000
1447 #define IXGBE_GPIE_PBA_SUPPORT 0x80000000
1448 #define IXGBE_GPIE_RSC_DELAY_SHIFT 11
1449 #define IXGBE_GPIE_VTMODE_MASK 0x0000C000
1450 #define IXGBE_GPIE_VTMODE_16 0x00004000
1451 #define IXGBE_GPIE_VTMODE_32 0x00008000
1452 #define IXGBE_GPIE_VTMODE_64 0x0000C000
1453
1454
1455 #define IXGBE_TXPBSIZE_20KB 0x00005000
1456 #define IXGBE_TXPBSIZE_40KB 0x0000A000
1457 #define IXGBE_RXPBSIZE_48KB 0x0000C000
1458 #define IXGBE_RXPBSIZE_64KB 0x00010000
1459 #define IXGBE_RXPBSIZE_80KB 0x00014000
1460 #define IXGBE_RXPBSIZE_128KB 0x00020000
1461 #define IXGBE_RXPBSIZE_MAX 0x00080000
1462 #define IXGBE_TXPBSIZE_MAX 0x00028000
1463
1464 #define IXGBE_TXPKT_SIZE_MAX 0xA
1465 #define IXGBE_MAX_PB 8
1466
1467
1468 enum {
1469 PBA_STRATEGY_EQUAL = 0,
1470 #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL
1471 PBA_STRATEGY_WEIGHTED = 1,
1472 #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED
1473 };
1474
1475
1476 #define IXGBE_TFCS_TXOFF 0x00000001
1477 #define IXGBE_TFCS_TXOFF0 0x00000100
1478 #define IXGBE_TFCS_TXOFF1 0x00000200
1479 #define IXGBE_TFCS_TXOFF2 0x00000400
1480 #define IXGBE_TFCS_TXOFF3 0x00000800
1481 #define IXGBE_TFCS_TXOFF4 0x00001000
1482 #define IXGBE_TFCS_TXOFF5 0x00002000
1483 #define IXGBE_TFCS_TXOFF6 0x00004000
1484 #define IXGBE_TFCS_TXOFF7 0x00008000
1485
1486
1487 #define IXGBE_TCPTIMER_KS 0x00000100
1488 #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
1489 #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
1490 #define IXGBE_TCPTIMER_LOOP 0x00000800
1491 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1492
1493
1494 #define IXGBE_HLREG0_TXCRCEN 0x00000001
1495 #define IXGBE_HLREG0_RXCRCSTRP 0x00000002
1496 #define IXGBE_HLREG0_JUMBOEN 0x00000004
1497 #define IXGBE_HLREG0_TXPADEN 0x00000400
1498 #define IXGBE_HLREG0_TXPAUSEEN 0x00001000
1499 #define IXGBE_HLREG0_RXPAUSEEN 0x00004000
1500 #define IXGBE_HLREG0_LPBK 0x00008000
1501 #define IXGBE_HLREG0_MDCSPD 0x00010000
1502 #define IXGBE_HLREG0_CONTMDC 0x00020000
1503 #define IXGBE_HLREG0_CTRLFLTR 0x00040000
1504 #define IXGBE_HLREG0_PREPEND 0x00F00000
1505 #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000
1506 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000
1507 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000
1508 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000
1509
1510
1511 #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
1512 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1513
1514
1515 #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000
1516 #define IXGBE_VT_CTL_REPLEN 0x40000000
1517 #define IXGBE_VT_CTL_VT_ENABLE 0x00000001
1518 #define IXGBE_VT_CTL_POOL_SHIFT 7
1519 #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1520
1521
1522 #define IXGBE_VMOLR_UPE 0x00400000
1523 #define IXGBE_VMOLR_VPE 0x00800000
1524 #define IXGBE_VMOLR_AUPE 0x01000000
1525 #define IXGBE_VMOLR_ROMPE 0x02000000
1526 #define IXGBE_VMOLR_ROPE 0x04000000
1527 #define IXGBE_VMOLR_BAM 0x08000000
1528 #define IXGBE_VMOLR_MPE 0x10000000
1529
1530
1531 #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
1532
1533 #define IXGBE_VF_INIT_TIMEOUT 200
1534
1535
1536 #define IXGBE_RDHMPN_RDICADDR 0x007FF800
1537 #define IXGBE_RDHMPN_RDICRDREQ 0x00800000
1538 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1539 #define IXGBE_TDHMPN_TDICADDR 0x003FF800
1540 #define IXGBE_TDHMPN_TDICRDREQ 0x00800000
1541 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1542
1543 #define IXGBE_RDMAM_MEM_SEL_SHIFT 13
1544 #define IXGBE_RDMAM_DWORD_SHIFT 9
1545 #define IXGBE_RDMAM_DESC_COMP_FIFO 1
1546 #define IXGBE_RDMAM_DFC_CMD_FIFO 2
1547 #define IXGBE_RDMAM_TCN_STATUS_RAM 4
1548 #define IXGBE_RDMAM_WB_COLL_FIFO 5
1549 #define IXGBE_RDMAM_QSC_CNT_RAM 6
1550 #define IXGBE_RDMAM_QSC_QUEUE_CNT 8
1551 #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
1552 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
1553 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
1554 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
1555 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
1556 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
1557 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
1558 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
1559 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
1560 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
1561 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
1562 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1563 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1564 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1565 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1566
1567 #define IXGBE_TXDESCIC_READY 0x80000000
1568
1569
1570 #define IXGBE_RXCSUM_IPPCSE 0x00001000
1571 #define IXGBE_RXCSUM_PCSD 0x00002000
1572
1573
1574 #define IXGBE_FCRTL_XONE 0x80000000
1575 #define IXGBE_FCRTH_FCEN 0x80000000
1576
1577
1578 #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF
1579
1580
1581 #define IXGBE_RMCS_RRM 0x00000002
1582
1583 #define IXGBE_RMCS_RAC 0x00000004
1584 #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC
1585 #define IXGBE_RMCS_TFCE_802_3X 0x00000008
1586 #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010
1587 #define IXGBE_RMCS_ARBDIS 0x00000040
1588
1589
1590 #define IXGBE_FCCFG_TFCE_802_3X 0x00000008
1591 #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010
1592
1593
1594
1595
1596 #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF
1597 #define IXGBE_EICR_FLOW_DIR 0x00010000
1598 #define IXGBE_EICR_RX_MISS 0x00020000
1599 #define IXGBE_EICR_PCI 0x00040000
1600 #define IXGBE_EICR_MAILBOX 0x00080000
1601 #define IXGBE_EICR_LSC 0x00100000
1602 #define IXGBE_EICR_LINKSEC 0x00200000
1603 #define IXGBE_EICR_MNG 0x00400000
1604 #define IXGBE_EICR_TS 0x00800000
1605 #define IXGBE_EICR_TIMESYNC 0x01000000
1606 #define IXGBE_EICR_GPI_SDP0_8259X 0x01000000
1607 #define IXGBE_EICR_GPI_SDP1_8259X 0x02000000
1608 #define IXGBE_EICR_GPI_SDP2_8259X 0x04000000
1609 #define IXGBE_EICR_GPI_SDP0_X540 0x02000000
1610 #define IXGBE_EICR_GPI_SDP1_X540 0x04000000
1611 #define IXGBE_EICR_GPI_SDP2_X540 0x08000000
1612 #define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540
1613 #define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540
1614 #define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540
1615 #define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540
1616 #define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540
1617 #define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540
1618 #define IXGBE_EICR_GPI_SDP0_X550EM_a IXGBE_EICR_GPI_SDP0_X540
1619 #define IXGBE_EICR_GPI_SDP1_X550EM_a IXGBE_EICR_GPI_SDP1_X540
1620 #define IXGBE_EICR_GPI_SDP2_X550EM_a IXGBE_EICR_GPI_SDP2_X540
1621 #define IXGBE_EICR_GPI_SDP0(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
1622 #define IXGBE_EICR_GPI_SDP1(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
1623 #define IXGBE_EICR_GPI_SDP2(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
1624
1625 #define IXGBE_EICR_ECC 0x10000000
1626 #define IXGBE_EICR_PBUR 0x10000000
1627 #define IXGBE_EICR_DHER 0x20000000
1628 #define IXGBE_EICR_TCP_TIMER 0x40000000
1629 #define IXGBE_EICR_OTHER 0x80000000
1630
1631
1632 #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE
1633 #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR
1634 #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS
1635 #define IXGBE_EICS_PCI IXGBE_EICR_PCI
1636 #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX
1637 #define IXGBE_EICS_LSC IXGBE_EICR_LSC
1638 #define IXGBE_EICS_MNG IXGBE_EICR_MNG
1639 #define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC
1640 #define IXGBE_EICS_GPI_SDP0(_hw) IXGBE_EICR_GPI_SDP0(_hw)
1641 #define IXGBE_EICS_GPI_SDP1(_hw) IXGBE_EICR_GPI_SDP1(_hw)
1642 #define IXGBE_EICS_GPI_SDP2(_hw) IXGBE_EICR_GPI_SDP2(_hw)
1643 #define IXGBE_EICS_ECC IXGBE_EICR_ECC
1644 #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR
1645 #define IXGBE_EICS_DHER IXGBE_EICR_DHER
1646 #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER
1647 #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER
1648
1649
1650 #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE
1651 #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR
1652 #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS
1653 #define IXGBE_EIMS_PCI IXGBE_EICR_PCI
1654 #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX
1655 #define IXGBE_EIMS_LSC IXGBE_EICR_LSC
1656 #define IXGBE_EIMS_MNG IXGBE_EICR_MNG
1657 #define IXGBE_EIMS_TS IXGBE_EICR_TS
1658 #define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC
1659 #define IXGBE_EIMS_GPI_SDP0(_hw) IXGBE_EICR_GPI_SDP0(_hw)
1660 #define IXGBE_EIMS_GPI_SDP1(_hw) IXGBE_EICR_GPI_SDP1(_hw)
1661 #define IXGBE_EIMS_GPI_SDP2(_hw) IXGBE_EICR_GPI_SDP2(_hw)
1662 #define IXGBE_EIMS_ECC IXGBE_EICR_ECC
1663 #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR
1664 #define IXGBE_EIMS_DHER IXGBE_EICR_DHER
1665 #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER
1666 #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER
1667
1668
1669 #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE
1670 #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR
1671 #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS
1672 #define IXGBE_EIMC_PCI IXGBE_EICR_PCI
1673 #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX
1674 #define IXGBE_EIMC_LSC IXGBE_EICR_LSC
1675 #define IXGBE_EIMC_MNG IXGBE_EICR_MNG
1676 #define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC
1677 #define IXGBE_EIMC_GPI_SDP0(_hw) IXGBE_EICR_GPI_SDP0(_hw)
1678 #define IXGBE_EIMC_GPI_SDP1(_hw) IXGBE_EICR_GPI_SDP1(_hw)
1679 #define IXGBE_EIMC_GPI_SDP2(_hw) IXGBE_EICR_GPI_SDP2(_hw)
1680 #define IXGBE_EIMC_ECC IXGBE_EICR_ECC
1681 #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR
1682 #define IXGBE_EIMC_DHER IXGBE_EICR_DHER
1683 #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER
1684 #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER
1685
1686 #define IXGBE_EIMS_ENABLE_MASK ( \
1687 IXGBE_EIMS_RTX_QUEUE | \
1688 IXGBE_EIMS_LSC | \
1689 IXGBE_EIMS_TCP_TIMER | \
1690 IXGBE_EIMS_OTHER)
1691
1692
1693 #define IXGBE_IMIR_PORT_IM_EN 0x00010000
1694 #define IXGBE_IMIR_PORT_BP 0x00020000
1695 #define IXGBE_IMIREXT_SIZE_BP 0x00001000
1696 #define IXGBE_IMIREXT_CTRL_URG 0x00002000
1697 #define IXGBE_IMIREXT_CTRL_ACK 0x00004000
1698 #define IXGBE_IMIREXT_CTRL_PSH 0x00008000
1699 #define IXGBE_IMIREXT_CTRL_RST 0x00010000
1700 #define IXGBE_IMIREXT_CTRL_SYN 0x00020000
1701 #define IXGBE_IMIREXT_CTRL_FIN 0x00040000
1702 #define IXGBE_IMIREXT_CTRL_BP 0x00080000
1703 #define IXGBE_IMIR_SIZE_BP_82599 0x00001000
1704 #define IXGBE_IMIR_CTRL_URG_82599 0x00002000
1705 #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000
1706 #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000
1707 #define IXGBE_IMIR_CTRL_RST_82599 0x00010000
1708 #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000
1709 #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000
1710 #define IXGBE_IMIR_CTRL_BP_82599 0x00080000
1711 #define IXGBE_IMIR_LLI_EN_82599 0x00100000
1712 #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F
1713 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21
1714 #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007
1715 #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008
1716
1717 #define IXGBE_MAX_FTQF_FILTERS 128
1718 #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1719 #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1720 #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1721 #define IXGBE_FTQF_PROTOCOL_SCTP 2
1722 #define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1723 #define IXGBE_FTQF_PRIORITY_SHIFT 2
1724 #define IXGBE_FTQF_POOL_MASK 0x0000003F
1725 #define IXGBE_FTQF_POOL_SHIFT 8
1726 #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1727 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
1728 #define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
1729 #define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
1730 #define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
1731 #define IXGBE_FTQF_DEST_PORT_MASK 0x17
1732 #define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
1733 #define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1734 #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
1735
1736
1737 #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
1738
1739
1740 #define IXGBE_IVAR_REG_NUM 25
1741 #define IXGBE_IVAR_REG_NUM_82599 64
1742 #define IXGBE_IVAR_TXRX_ENTRY 96
1743 #define IXGBE_IVAR_RX_ENTRY 64
1744 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
1745 #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
1746 #define IXGBE_IVAR_TX_ENTRY 32
1747
1748 #define IXGBE_IVAR_TCP_TIMER_INDEX 96
1749 #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97
1750
1751 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
1752
1753 #define IXGBE_IVAR_ALLOC_VAL 0x80
1754
1755
1756 #define IXGBE_MAX_ETQF_FILTERS 8
1757 #define IXGBE_ETQF_FCOE 0x08000000
1758 #define IXGBE_ETQF_BCN 0x10000000
1759 #define IXGBE_ETQF_TX_ANTISPOOF 0x20000000
1760 #define IXGBE_ETQF_1588 0x40000000
1761 #define IXGBE_ETQF_FILTER_EN 0x80000000
1762 #define IXGBE_ETQF_POOL_ENABLE BIT(26)
1763 #define IXGBE_ETQF_POOL_SHIFT 20
1764
1765 #define IXGBE_ETQS_RX_QUEUE 0x007F0000
1766 #define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1767 #define IXGBE_ETQS_LLI 0x20000000
1768 #define IXGBE_ETQS_QUEUE_EN 0x80000000
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784 #define IXGBE_ETQF_FILTER_EAPOL 0
1785 #define IXGBE_ETQF_FILTER_FCOE 2
1786 #define IXGBE_ETQF_FILTER_1588 3
1787 #define IXGBE_ETQF_FILTER_FIP 4
1788 #define IXGBE_ETQF_FILTER_LLDP 5
1789 #define IXGBE_ETQF_FILTER_LACP 6
1790 #define IXGBE_ETQF_FILTER_FC 7
1791
1792
1793 #define IXGBE_VLNCTRL_VET 0x0000FFFF
1794 #define IXGBE_VLNCTRL_CFI 0x10000000
1795 #define IXGBE_VLNCTRL_CFIEN 0x20000000
1796 #define IXGBE_VLNCTRL_VFE 0x40000000
1797 #define IXGBE_VLNCTRL_VME 0x80000000
1798
1799
1800 #define IXGBE_VLVF_VIEN 0x80000000
1801 #define IXGBE_VLVF_ENTRIES 64
1802 #define IXGBE_VLVF_VLANID_MASK 0x00000FFF
1803
1804
1805 #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000
1806 #define IXGBE_VMVIR_VLANA_NEVER 0x80000000
1807
1808 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100
1809
1810
1811 #define IXGBE_STATUS_LAN_ID 0x0000000C
1812 #define IXGBE_STATUS_LAN_ID_SHIFT 2
1813 #define IXGBE_STATUS_GIO 0x00080000
1814
1815 #define IXGBE_STATUS_LAN_ID_0 0x00000000
1816 #define IXGBE_STATUS_LAN_ID_1 0x00000004
1817
1818
1819 #define IXGBE_ESDP_SDP0 0x00000001
1820 #define IXGBE_ESDP_SDP1 0x00000002
1821 #define IXGBE_ESDP_SDP2 0x00000004
1822 #define IXGBE_ESDP_SDP3 0x00000008
1823 #define IXGBE_ESDP_SDP4 0x00000010
1824 #define IXGBE_ESDP_SDP5 0x00000020
1825 #define IXGBE_ESDP_SDP6 0x00000040
1826 #define IXGBE_ESDP_SDP0_DIR 0x00000100
1827 #define IXGBE_ESDP_SDP1_DIR 0x00000200
1828 #define IXGBE_ESDP_SDP4_DIR 0x00000004
1829 #define IXGBE_ESDP_SDP5_DIR 0x00002000
1830 #define IXGBE_ESDP_SDP0_NATIVE 0x00010000
1831 #define IXGBE_ESDP_SDP1_NATIVE 0x00020000
1832
1833
1834 #define IXGBE_LED_IVRT_BASE 0x00000040
1835 #define IXGBE_LED_BLINK_BASE 0x00000080
1836 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1837 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1838 #define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i))
1839 #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1840 #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1841 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1842 #define IXGBE_X557_LED_MANUAL_SET_MASK BIT(8)
1843 #define IXGBE_X557_MAX_LED_INDEX 3
1844 #define IXGBE_X557_LED_PROVISIONING 0xC430
1845
1846
1847 #define IXGBE_LED_LINK_UP 0x0
1848 #define IXGBE_LED_LINK_10G 0x1
1849 #define IXGBE_LED_MAC 0x2
1850 #define IXGBE_LED_FILTER 0x3
1851 #define IXGBE_LED_LINK_ACTIVE 0x4
1852 #define IXGBE_LED_LINK_1G 0x5
1853 #define IXGBE_LED_ON 0xE
1854 #define IXGBE_LED_OFF 0xF
1855
1856
1857 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1858 #define IXGBE_AUTOC_KX4_SUPP 0x80000000
1859 #define IXGBE_AUTOC_KX_SUPP 0x40000000
1860 #define IXGBE_AUTOC_PAUSE 0x30000000
1861 #define IXGBE_AUTOC_ASM_PAUSE 0x20000000
1862 #define IXGBE_AUTOC_SYM_PAUSE 0x10000000
1863 #define IXGBE_AUTOC_RF 0x08000000
1864 #define IXGBE_AUTOC_PD_TMR 0x06000000
1865 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1866 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1867 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1868 #define IXGBE_AUTOC_FECA 0x00040000
1869 #define IXGBE_AUTOC_FECR 0x00020000
1870 #define IXGBE_AUTOC_KR_SUPP 0x00010000
1871 #define IXGBE_AUTOC_AN_RESTART 0x00001000
1872 #define IXGBE_AUTOC_FLU 0x00000001
1873 #define IXGBE_AUTOC_LMS_SHIFT 13
1874 #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1875 #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1876 #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1877 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1878 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1879 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1880 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1881 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1882 #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1883 #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1884 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1885 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1886
1887 #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
1888 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
1889 #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
1890 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
1891 #define IXGBE_AUTOC_10G_XAUI (0u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1892 #define IXGBE_AUTOC_10G_KX4 (1u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1893 #define IXGBE_AUTOC_10G_CX4 (2u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1894 #define IXGBE_AUTOC_1G_BX (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1895 #define IXGBE_AUTOC_1G_KX (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1896 #define IXGBE_AUTOC_1G_SFI (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1897 #define IXGBE_AUTOC_1G_KX_BX (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1898
1899 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1900 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1901 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1902 #define IXGBE_AUTOC2_10G_KR (0u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1903 #define IXGBE_AUTOC2_10G_XFI (1u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1904 #define IXGBE_AUTOC2_10G_SFI (2u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1905 #define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000
1906 #define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000
1907
1908 #define IXGBE_MACC_FLU 0x00000001
1909 #define IXGBE_MACC_FSV_10G 0x00030000
1910 #define IXGBE_MACC_FS 0x00040000
1911 #define IXGBE_MAC_RX2TX_LPBK 0x00000002
1912
1913
1914 #define IXGBE_MMNGC_MNG_VETO 0x00000001
1915
1916
1917 #define IXGBE_LINKS_KX_AN_COMP 0x80000000
1918 #define IXGBE_LINKS_UP 0x40000000
1919 #define IXGBE_LINKS_SPEED 0x20000000
1920 #define IXGBE_LINKS_MODE 0x18000000
1921 #define IXGBE_LINKS_RX_MODE 0x06000000
1922 #define IXGBE_LINKS_TX_MODE 0x01800000
1923 #define IXGBE_LINKS_XGXS_EN 0x00400000
1924 #define IXGBE_LINKS_SGMII_EN 0x02000000
1925 #define IXGBE_LINKS_PCS_1G_EN 0x00200000
1926 #define IXGBE_LINKS_1G_AN_EN 0x00100000
1927 #define IXGBE_LINKS_KX_AN_IDLE 0x00080000
1928 #define IXGBE_LINKS_1G_SYNC 0x00040000
1929 #define IXGBE_LINKS_10G_ALIGN 0x00020000
1930 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1931 #define IXGBE_LINKS_TL_FAULT 0x00001000
1932 #define IXGBE_LINKS_SIGNAL 0x00000F00
1933
1934 #define IXGBE_LINKS_SPEED_NON_STD 0x08000000
1935 #define IXGBE_LINKS_SPEED_82599 0x30000000
1936 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1937 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000
1938 #define IXGBE_LINKS_SPEED_100_82599 0x10000000
1939 #define IXGBE_LINKS_SPEED_10_X550EM_A 0
1940 #define IXGBE_LINK_UP_TIME 90
1941 #define IXGBE_AUTO_NEG_TIME 45
1942
1943 #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
1944
1945
1946 #define IXGBE_PCS1GLSTA_LINK_OK 1
1947 #define IXGBE_PCS1GLSTA_SYNK_OK 0x10
1948 #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
1949 #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
1950 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
1951 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1952 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
1953
1954 #define IXGBE_PCS1GANA_SYM_PAUSE 0x80
1955 #define IXGBE_PCS1GANA_ASM_PAUSE 0x100
1956
1957
1958 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000
1959 #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
1960 #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
1961 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1962 #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1963 #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1964
1965
1966 #define IXGBE_ANLP1_PAUSE 0x0C00
1967 #define IXGBE_ANLP1_SYM_PAUSE 0x0400
1968 #define IXGBE_ANLP1_ASM_PAUSE 0x0800
1969 #define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
1970
1971
1972 #define IXGBE_SWSM_SMBI 0x00000001
1973 #define IXGBE_SWSM_SWESMBI 0x00000002
1974 #define IXGBE_SWSM_WMNG 0x00000004
1975 #define IXGBE_SWFW_REGSMP 0x80000000
1976
1977
1978 #define IXGBE_GSSR_EEP_SM 0x0001
1979 #define IXGBE_GSSR_PHY0_SM 0x0002
1980 #define IXGBE_GSSR_PHY1_SM 0x0004
1981 #define IXGBE_GSSR_MAC_CSR_SM 0x0008
1982 #define IXGBE_GSSR_FLASH_SM 0x0010
1983 #define IXGBE_GSSR_NVM_UPDATE_SM 0x0200
1984 #define IXGBE_GSSR_SW_MNG_SM 0x0400
1985 #define IXGBE_GSSR_TOKEN_SM 0x40000000
1986 #define IXGBE_GSSR_SHARED_I2C_SM 0x1806
1987 #define IXGBE_GSSR_I2C_MASK 0x1800
1988 #define IXGBE_GSSR_NVM_PHY_MASK 0xF
1989
1990
1991 #define IXGBE_FWSTS_FWRI 0x00000200
1992
1993
1994 #define IXGBE_EEC_SK 0x00000001
1995 #define IXGBE_EEC_CS 0x00000002
1996 #define IXGBE_EEC_DI 0x00000004
1997 #define IXGBE_EEC_DO 0x00000008
1998 #define IXGBE_EEC_FWE_MASK 0x00000030
1999 #define IXGBE_EEC_FWE_DIS 0x00000010
2000 #define IXGBE_EEC_FWE_EN 0x00000020
2001 #define IXGBE_EEC_FWE_SHIFT 4
2002 #define IXGBE_EEC_REQ 0x00000040
2003 #define IXGBE_EEC_GNT 0x00000080
2004 #define IXGBE_EEC_PRES 0x00000100
2005 #define IXGBE_EEC_ARD 0x00000200
2006 #define IXGBE_EEC_FLUP 0x00800000
2007 #define IXGBE_EEC_SEC1VAL 0x02000000
2008 #define IXGBE_EEC_FLUDONE 0x04000000
2009
2010 #define IXGBE_EEC_ADDR_SIZE 0x00000400
2011 #define IXGBE_EEC_SIZE 0x00007800
2012 #define IXGBE_EERD_MAX_ADDR 0x00003FFF
2013
2014 #define IXGBE_EEC_SIZE_SHIFT 11
2015 #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
2016 #define IXGBE_EEPROM_OPCODE_BITS 8
2017
2018
2019 #define IXGBE_PBANUM_LENGTH 11
2020
2021
2022 #define IXGBE_PBANUM_PTR_GUARD 0xFAFA
2023 #define IXGBE_EEPROM_CHECKSUM 0x3F
2024 #define IXGBE_EEPROM_SUM 0xBABA
2025 #define IXGBE_EEPROM_CTRL_4 0x45
2026 #define IXGBE_EE_CTRL_4_INST_ID 0x10
2027 #define IXGBE_EE_CTRL_4_INST_ID_SHIFT 4
2028 #define IXGBE_PCIE_ANALOG_PTR 0x03
2029 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
2030 #define IXGBE_PHY_PTR 0x04
2031 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
2032 #define IXGBE_OPTION_ROM_PTR 0x05
2033 #define IXGBE_PCIE_GENERAL_PTR 0x06
2034 #define IXGBE_PCIE_CONFIG0_PTR 0x07
2035 #define IXGBE_PCIE_CONFIG1_PTR 0x08
2036 #define IXGBE_CORE0_PTR 0x09
2037 #define IXGBE_CORE1_PTR 0x0A
2038 #define IXGBE_MAC0_PTR 0x0B
2039 #define IXGBE_MAC1_PTR 0x0C
2040 #define IXGBE_CSR0_CONFIG_PTR 0x0D
2041 #define IXGBE_CSR1_CONFIG_PTR 0x0E
2042 #define IXGBE_PCIE_ANALOG_PTR_X550 0x02
2043 #define IXGBE_SHADOW_RAM_SIZE_X550 0x4000
2044 #define IXGBE_IXGBE_PCIE_GENERAL_SIZE 0x24
2045 #define IXGBE_PCIE_CONFIG_SIZE 0x08
2046 #define IXGBE_EEPROM_LAST_WORD 0x41
2047 #define IXGBE_FW_PTR 0x0F
2048 #define IXGBE_PBANUM0_PTR 0x15
2049 #define IXGBE_PBANUM1_PTR 0x16
2050 #define IXGBE_FREE_SPACE_PTR 0X3E
2051
2052
2053 #define IXGBE_ETS_CFG 0x26
2054 #define IXGBE_ETS_LTHRES_DELTA_MASK 0x07C0
2055 #define IXGBE_ETS_LTHRES_DELTA_SHIFT 6
2056 #define IXGBE_ETS_TYPE_MASK 0x0038
2057 #define IXGBE_ETS_TYPE_SHIFT 3
2058 #define IXGBE_ETS_TYPE_EMC 0x000
2059 #define IXGBE_ETS_TYPE_EMC_SHIFTED 0x000
2060 #define IXGBE_ETS_NUM_SENSORS_MASK 0x0007
2061 #define IXGBE_ETS_DATA_LOC_MASK 0x3C00
2062 #define IXGBE_ETS_DATA_LOC_SHIFT 10
2063 #define IXGBE_ETS_DATA_INDEX_MASK 0x0300
2064 #define IXGBE_ETS_DATA_INDEX_SHIFT 8
2065 #define IXGBE_ETS_DATA_HTHRESH_MASK 0x00FF
2066
2067 #define IXGBE_SAN_MAC_ADDR_PTR 0x28
2068 #define IXGBE_DEVICE_CAPS 0x2C
2069 #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
2070 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72
2071 #define IXGBE_MAX_MSIX_VECTORS_82599 0x40
2072 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62
2073 #define IXGBE_MAX_MSIX_VECTORS_82598 0x13
2074
2075
2076 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
2077
2078
2079 #define IXGBE_ISCSI_BOOT_CAPS 0x0033
2080 #define IXGBE_ISCSI_SETUP_PORT_0 0x0030
2081 #define IXGBE_ISCSI_SETUP_PORT_1 0x0034
2082
2083
2084 #define IXGBE_EEPROM_MAX_RETRY_SPI 5000
2085 #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
2086 #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03
2087 #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02
2088 #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08
2089 #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06
2090
2091 #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
2092 #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05
2093 #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01
2094 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20
2095 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8
2096 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB
2097
2098
2099 #define IXGBE_EEPROM_RW_REG_DATA 16
2100 #define IXGBE_EEPROM_RW_REG_DONE 2
2101 #define IXGBE_EEPROM_RW_REG_START 1
2102 #define IXGBE_EEPROM_RW_ADDR_SHIFT 2
2103 #define IXGBE_NVM_POLL_WRITE 1
2104 #define IXGBE_NVM_POLL_READ 0
2105
2106 #define NVM_INIT_CTRL_3 0x38
2107 #define NVM_INIT_CTRL_3_LPLU 0x8
2108 #define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40
2109 #define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100
2110
2111 #define IXGBE_EEPROM_PAGE_SIZE_MAX 128
2112 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512
2113 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256
2114
2115 #define IXGBE_EEPROM_CTRL_2 1
2116 #define IXGBE_EEPROM_CCD_BIT 2
2117
2118 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
2119 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000
2120 #endif
2121
2122 #ifndef IXGBE_EERD_EEWR_ATTEMPTS
2123
2124
2125 #define IXGBE_EERD_EEWR_ATTEMPTS 100000
2126 #endif
2127
2128 #ifndef IXGBE_FLUDONE_ATTEMPTS
2129
2130 #define IXGBE_FLUDONE_ATTEMPTS 20000
2131 #endif
2132
2133 #define IXGBE_PCIE_CTRL2 0x5
2134 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8
2135 #define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2
2136 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1
2137
2138 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
2139 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
2140 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
2141 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
2142 #define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR BIT(7)
2143 #define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
2144 #define IXGBE_FW_LESM_STATE_1 0x1
2145 #define IXGBE_FW_LESM_STATE_ENABLED 0x8000
2146 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
2147 #define IXGBE_FW_PATCH_VERSION_4 0x7
2148 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33
2149 #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20
2150 #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17
2151 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0
2152 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1
2153 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27
2154 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0
2155 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1
2156 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4
2157 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7
2158 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8
2159 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0
2160 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1
2161
2162 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4
2163 #define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8
2164 #define IXGBE_DEVICE_CAPS_WOL_MASK 0xC
2165
2166
2167 #define IXGBE_PCI_DEVICE_STATUS 0xAA
2168 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
2169 #define IXGBE_PCI_LINK_STATUS 0xB2
2170 #define IXGBE_PCI_DEVICE_CONTROL2 0xC8
2171 #define IXGBE_PCI_LINK_WIDTH 0x3F0
2172 #define IXGBE_PCI_LINK_WIDTH_1 0x10
2173 #define IXGBE_PCI_LINK_WIDTH_2 0x20
2174 #define IXGBE_PCI_LINK_WIDTH_4 0x40
2175 #define IXGBE_PCI_LINK_WIDTH_8 0x80
2176 #define IXGBE_PCI_LINK_SPEED 0xF
2177 #define IXGBE_PCI_LINK_SPEED_2500 0x1
2178 #define IXGBE_PCI_LINK_SPEED_5000 0x2
2179 #define IXGBE_PCI_LINK_SPEED_8000 0x3
2180 #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
2181 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
2182 #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
2183
2184 #define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf
2185 #define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0
2186 #define IXGBE_PCIDEVCTRL2_50_100us 0x1
2187 #define IXGBE_PCIDEVCTRL2_1_2ms 0x2
2188 #define IXGBE_PCIDEVCTRL2_16_32ms 0x5
2189 #define IXGBE_PCIDEVCTRL2_65_130ms 0x6
2190 #define IXGBE_PCIDEVCTRL2_260_520ms 0x9
2191 #define IXGBE_PCIDEVCTRL2_1_2s 0xa
2192 #define IXGBE_PCIDEVCTRL2_4_8s 0xd
2193 #define IXGBE_PCIDEVCTRL2_17_34s 0xe
2194
2195
2196 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
2197
2198
2199 #define IXGBE_RAH_VIND_MASK 0x003C0000
2200 #define IXGBE_RAH_VIND_SHIFT 18
2201 #define IXGBE_RAH_AV 0x80000000
2202 #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
2203
2204
2205 #define IXGBE_RFCTL_ISCSI_DIS 0x00000001
2206 #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
2207 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
2208 #define IXGBE_RFCTL_RSC_DIS 0x00000020
2209 #define IXGBE_RFCTL_NFSW_DIS 0x00000040
2210 #define IXGBE_RFCTL_NFSR_DIS 0x00000080
2211 #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
2212 #define IXGBE_RFCTL_NFS_VER_SHIFT 8
2213 #define IXGBE_RFCTL_NFS_VER_2 0
2214 #define IXGBE_RFCTL_NFS_VER_3 1
2215 #define IXGBE_RFCTL_NFS_VER_4 2
2216 #define IXGBE_RFCTL_IPV6_DIS 0x00000400
2217 #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
2218 #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
2219 #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
2220 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
2221
2222
2223 #define IXGBE_TXDCTL_ENABLE 0x02000000
2224 #define IXGBE_TXDCTL_SWFLSH 0x04000000
2225 #define IXGBE_TXDCTL_WTHRESH_SHIFT 16
2226
2227 #define IXGBE_TX_PAD_ENABLE 0x00000400
2228 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004
2229
2230 #define IXGBE_MAX_FRAME_SZ 0x40040000
2231
2232 #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1
2233 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2
2234
2235
2236 #define IXGBE_RXCTRL_RXEN 0x00000001
2237 #define IXGBE_RXCTRL_DMBYPS 0x00000002
2238 #define IXGBE_RXDCTL_ENABLE 0x02000000
2239 #define IXGBE_RXDCTL_SWFLSH 0x04000000
2240 #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF
2241 #define IXGBE_RXDCTL_RLPML_EN 0x00008000
2242 #define IXGBE_RXDCTL_VME 0x40000000
2243
2244 #define IXGBE_TSAUXC_EN_CLK 0x00000004
2245 #define IXGBE_TSAUXC_SYNCLK 0x00000008
2246 #define IXGBE_TSAUXC_SDP0_INT 0x00000040
2247 #define IXGBE_TSAUXC_EN_TT0 0x00000001
2248 #define IXGBE_TSAUXC_EN_TT1 0x00000002
2249 #define IXGBE_TSAUXC_ST0 0x00000010
2250 #define IXGBE_TSAUXC_DISABLE_SYSTIME 0x80000000
2251
2252 #define IXGBE_TSSDP_TS_SDP0_SEL_MASK 0x000000C0
2253 #define IXGBE_TSSDP_TS_SDP0_CLK0 0x00000080
2254 #define IXGBE_TSSDP_TS_SDP0_EN 0x00000100
2255
2256 #define IXGBE_TSYNCTXCTL_VALID 0x00000001
2257 #define IXGBE_TSYNCTXCTL_ENABLED 0x00000010
2258
2259 #define IXGBE_TSYNCRXCTL_VALID 0x00000001
2260 #define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E
2261 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00
2262 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02
2263 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
2264 #define IXGBE_TSYNCRXCTL_TYPE_ALL 0x08
2265 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
2266 #define IXGBE_TSYNCRXCTL_ENABLED 0x00000010
2267 #define IXGBE_TSYNCRXCTL_TSIP_UT_EN 0x00800000
2268
2269 #define IXGBE_TSIM_TXTS 0x00000002
2270
2271 #define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF
2272 #define IXGBE_RXMTRL_V1_SYNC_MSG 0x00
2273 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01
2274 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02
2275 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03
2276 #define IXGBE_RXMTRL_V1_MGMT_MSG 0x04
2277
2278 #define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00
2279 #define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000
2280 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100
2281 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200
2282 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
2283 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800
2284 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900
2285 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
2286 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00
2287 #define IXGBE_RXMTRL_V2_SIGNALING_MSG 0x0C00
2288 #define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00
2289
2290 #define IXGBE_FCTRL_SBP 0x00000002
2291 #define IXGBE_FCTRL_MPE 0x00000100
2292 #define IXGBE_FCTRL_UPE 0x00000200
2293 #define IXGBE_FCTRL_BAM 0x00000400
2294 #define IXGBE_FCTRL_PMCF 0x00001000
2295 #define IXGBE_FCTRL_DPF 0x00002000
2296
2297 #define IXGBE_FCTRL_RPFCE 0x00004000
2298 #define IXGBE_FCTRL_RFCE 0x00008000
2299 #define IXGBE_MFLCN_PMCF 0x00000001
2300 #define IXGBE_MFLCN_DPF 0x00000002
2301 #define IXGBE_MFLCN_RPFCE 0x00000004
2302 #define IXGBE_MFLCN_RFCE 0x00000008
2303 #define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4
2304
2305 #define IXGBE_MFLCN_RPFCE_SHIFT 4
2306
2307
2308 #define IXGBE_MRQC_RSSEN 0x00000001
2309 #define IXGBE_MRQC_MRQE_MASK 0xF
2310 #define IXGBE_MRQC_RT8TCEN 0x00000002
2311 #define IXGBE_MRQC_RT4TCEN 0x00000003
2312 #define IXGBE_MRQC_RTRSS8TCEN 0x00000004
2313 #define IXGBE_MRQC_RTRSS4TCEN 0x00000005
2314 #define IXGBE_MRQC_VMDQEN 0x00000008
2315 #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A
2316 #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B
2317 #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C
2318 #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D
2319 #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
2320 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
2321 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
2322 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2323 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
2324 #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
2325 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
2326 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
2327 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
2328 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
2329 #define IXGBE_MRQC_MULTIPLE_RSS 0x00002000
2330 #define IXGBE_MRQC_L3L4TXSWEN 0x00008000
2331
2332 #define IXGBE_FWSM_TS_ENABLED 0x1
2333
2334
2335 #define IXGBE_QDE_ENABLE 0x00000001
2336 #define IXGBE_QDE_HIDE_VLAN 0x00000002
2337 #define IXGBE_QDE_IDX_MASK 0x00007F00
2338 #define IXGBE_QDE_IDX_SHIFT 8
2339 #define IXGBE_QDE_WRITE 0x00010000
2340
2341 #define IXGBE_TXD_POPTS_IXSM 0x01
2342 #define IXGBE_TXD_POPTS_TXSM 0x02
2343 #define IXGBE_TXD_CMD_EOP 0x01000000
2344 #define IXGBE_TXD_CMD_IFCS 0x02000000
2345 #define IXGBE_TXD_CMD_IC 0x04000000
2346 #define IXGBE_TXD_CMD_RS 0x08000000
2347 #define IXGBE_TXD_CMD_DEXT 0x20000000
2348 #define IXGBE_TXD_CMD_VLE 0x40000000
2349 #define IXGBE_TXD_STAT_DD 0x00000001
2350
2351
2352 #define IXGBE_MTQC_RT_ENA 0x1
2353 #define IXGBE_MTQC_VT_ENA 0x2
2354 #define IXGBE_MTQC_64Q_1PB 0x0
2355 #define IXGBE_MTQC_32VF 0x8
2356 #define IXGBE_MTQC_64VF 0x4
2357 #define IXGBE_MTQC_8TC_8TQ 0xC
2358 #define IXGBE_MTQC_4TC_4TQ 0x8
2359
2360
2361 #define IXGBE_RXD_STAT_DD 0x01
2362 #define IXGBE_RXD_STAT_EOP 0x02
2363 #define IXGBE_RXD_STAT_FLM 0x04
2364 #define IXGBE_RXD_STAT_VP 0x08
2365 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0
2366 #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
2367 #define IXGBE_RXD_STAT_UDPCS 0x10
2368 #define IXGBE_RXD_STAT_L4CS 0x20
2369 #define IXGBE_RXD_STAT_IPCS 0x40
2370 #define IXGBE_RXD_STAT_PIF 0x80
2371 #define IXGBE_RXD_STAT_CRCV 0x100
2372 #define IXGBE_RXD_STAT_OUTERIPCS 0x100
2373 #define IXGBE_RXD_STAT_VEXT 0x200
2374 #define IXGBE_RXD_STAT_UDPV 0x400
2375 #define IXGBE_RXD_STAT_DYNINT 0x800
2376 #define IXGBE_RXD_STAT_LLINT 0x800
2377 #define IXGBE_RXD_STAT_TSIP 0x08000
2378 #define IXGBE_RXD_STAT_TS 0x10000
2379 #define IXGBE_RXD_STAT_SECP 0x20000
2380 #define IXGBE_RXD_STAT_LB 0x40000
2381 #define IXGBE_RXD_STAT_ACK 0x8000
2382 #define IXGBE_RXD_ERR_CE 0x01
2383 #define IXGBE_RXD_ERR_LE 0x02
2384 #define IXGBE_RXD_ERR_PE 0x08
2385 #define IXGBE_RXD_ERR_OSE 0x10
2386 #define IXGBE_RXD_ERR_USE 0x20
2387 #define IXGBE_RXD_ERR_TCPE 0x40
2388 #define IXGBE_RXD_ERR_IPE 0x80
2389 #define IXGBE_RXDADV_ERR_MASK 0xfff00000
2390 #define IXGBE_RXDADV_ERR_SHIFT 20
2391 #define IXGBE_RXDADV_ERR_OUTERIPER 0x04000000
2392 #define IXGBE_RXDADV_ERR_FCEOFE 0x80000000
2393 #define IXGBE_RXDADV_ERR_FCERR 0x00700000
2394 #define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000
2395 #define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000
2396 #define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000
2397 #define IXGBE_RXDADV_ERR_HBO 0x00800000
2398 #define IXGBE_RXDADV_ERR_CE 0x01000000
2399 #define IXGBE_RXDADV_ERR_LE 0x02000000
2400 #define IXGBE_RXDADV_ERR_PE 0x08000000
2401 #define IXGBE_RXDADV_ERR_OSE 0x10000000
2402 #define IXGBE_RXDADV_ERR_IPSEC_INV_PROTOCOL 0x08000000
2403 #define IXGBE_RXDADV_ERR_IPSEC_INV_LENGTH 0x10000000
2404 #define IXGBE_RXDADV_ERR_IPSEC_AUTH_FAILED 0x18000000
2405 #define IXGBE_RXDADV_ERR_USE 0x20000000
2406 #define IXGBE_RXDADV_ERR_TCPE 0x40000000
2407 #define IXGBE_RXDADV_ERR_IPE 0x80000000
2408 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF
2409 #define IXGBE_RXD_PRI_MASK 0xE000
2410 #define IXGBE_RXD_PRI_SHIFT 13
2411 #define IXGBE_RXD_CFI_MASK 0x1000
2412 #define IXGBE_RXD_CFI_SHIFT 12
2413
2414 #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD
2415 #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP
2416 #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM
2417 #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP
2418 #define IXGBE_RXDADV_STAT_MASK 0x000fffff
2419 #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040
2420 #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030
2421 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000
2422 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010
2423 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020
2424 #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030
2425 #define IXGBE_RXDADV_STAT_TS 0x00010000
2426 #define IXGBE_RXDADV_STAT_SECP 0x00020000
2427
2428
2429 #define IXGBE_PSRTYPE_TCPHDR 0x00000010
2430 #define IXGBE_PSRTYPE_UDPHDR 0x00000020
2431 #define IXGBE_PSRTYPE_IPV4HDR 0x00000100
2432 #define IXGBE_PSRTYPE_IPV6HDR 0x00000200
2433 #define IXGBE_PSRTYPE_L2HDR 0x00001000
2434
2435
2436 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10
2437 #define IXGBE_SRRCTL_RDMTS_SHIFT 22
2438 #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
2439 #define IXGBE_SRRCTL_DROP_EN 0x10000000
2440 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
2441 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
2442 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
2443 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2444 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
2445 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2446 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2447 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
2448
2449 #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
2450 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2451
2452 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
2453 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
2454 #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
2455 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
2456 #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
2457 #define IXGBE_RXDADV_RSCCNT_SHIFT 17
2458 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
2459 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
2460 #define IXGBE_RXDADV_SPH 0x8000
2461
2462
2463 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
2464 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
2465 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
2466 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
2467 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
2468 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
2469 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2470 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
2471 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
2472 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2473
2474
2475 #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
2476 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010
2477 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020
2478 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040
2479 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080
2480 #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100
2481 #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200
2482 #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400
2483 #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800
2484 #define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800
2485 #define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000
2486 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000
2487 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000
2488 #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000
2489 #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000
2490 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070
2491 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4
2492
2493
2494 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2495 IXGBE_RXD_ERR_CE | \
2496 IXGBE_RXD_ERR_LE | \
2497 IXGBE_RXD_ERR_PE | \
2498 IXGBE_RXD_ERR_OSE | \
2499 IXGBE_RXD_ERR_USE)
2500
2501 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2502 IXGBE_RXDADV_ERR_CE | \
2503 IXGBE_RXDADV_ERR_LE | \
2504 IXGBE_RXDADV_ERR_PE | \
2505 IXGBE_RXDADV_ERR_OSE | \
2506 IXGBE_RXDADV_ERR_IPSEC_INV_PROTOCOL | \
2507 IXGBE_RXDADV_ERR_IPSEC_INV_LENGTH | \
2508 IXGBE_RXDADV_ERR_USE)
2509
2510
2511 #define IXGBE_MCSTCTRL_MFE 0x4
2512
2513
2514 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
2515 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
2516 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
2517
2518
2519 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF
2520 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000
2521 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D
2522 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2523
2524
2525 #define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
2526 #define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4))
2527 #define IXGBE_VFLRE(_i) ((((_i) & 1) ? 0x001C0 : 0x00600))
2528 #define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4))
2529
2530 #define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P)))
2531 #define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P)))
2532 #define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P)))
2533 #define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P)))
2534 #define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P)))
2535
2536 #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
2537 (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
2538 #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
2539 (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
2540
2541 #define IXGBE_PVFTDHN(q_per_pool, vf_number, vf_q_index) \
2542 (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
2543 #define IXGBE_PVFTDTN(q_per_pool, vf_number, vf_q_index) \
2544 (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
2545
2546 enum ixgbe_fdir_pballoc_type {
2547 IXGBE_FDIR_PBALLOC_NONE = 0,
2548 IXGBE_FDIR_PBALLOC_64K = 1,
2549 IXGBE_FDIR_PBALLOC_128K = 2,
2550 IXGBE_FDIR_PBALLOC_256K = 3,
2551 };
2552 #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16
2553
2554
2555 #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
2556 #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
2557 #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
2558 #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
2559 #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
2560 #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
2561 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
2562 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
2563 #define IXGBE_FDIRCTRL_FLEX_SHIFT 16
2564 #define IXGBE_FDIRCTRL_DROP_NO_MATCH 0x00008000
2565 #define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21
2566 #define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001
2567 #define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002
2568 #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
2569 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
2570 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
2571 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
2572
2573 #define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
2574 #define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
2575 #define IXGBE_FDIRIP6M_DIPM_SHIFT 16
2576 #define IXGBE_FDIRM_VLANID 0x00000001
2577 #define IXGBE_FDIRM_VLANP 0x00000002
2578 #define IXGBE_FDIRM_POOL 0x00000004
2579 #define IXGBE_FDIRM_L4P 0x00000008
2580 #define IXGBE_FDIRM_FLEX 0x00000010
2581 #define IXGBE_FDIRM_DIPv6 0x00000020
2582
2583 #define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
2584 #define IXGBE_FDIRFREE_FREE_SHIFT 0
2585 #define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
2586 #define IXGBE_FDIRFREE_COLL_SHIFT 16
2587 #define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
2588 #define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
2589 #define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
2590 #define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
2591 #define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
2592 #define IXGBE_FDIRUSTAT_ADD_SHIFT 0
2593 #define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
2594 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
2595 #define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
2596 #define IXGBE_FDIRFSTAT_FADD_SHIFT 0
2597 #define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
2598 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
2599 #define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
2600 #define IXGBE_FDIRVLAN_FLEX_SHIFT 16
2601 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
2602 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
2603
2604 #define IXGBE_FDIRCMD_CMD_MASK 0x00000003
2605 #define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
2606 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
2607 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
2608 #define IXGBE_FDIRCMD_FILTER_VALID 0x00000004
2609 #define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
2610 #define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
2611 #define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
2612 #define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
2613 #define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
2614 #define IXGBE_FDIRCMD_IPV6 0x00000080
2615 #define IXGBE_FDIRCMD_CLEARHT 0x00000100
2616 #define IXGBE_FDIRCMD_DROP 0x00000200
2617 #define IXGBE_FDIRCMD_INT 0x00000400
2618 #define IXGBE_FDIRCMD_LAST 0x00000800
2619 #define IXGBE_FDIRCMD_COLLISION 0x00001000
2620 #define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
2621 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
2622 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
2623 #define IXGBE_FDIRCMD_RX_TUNNEL_FILTER_SHIFT 23
2624 #define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
2625 #define IXGBE_FDIR_INIT_DONE_POLL 10
2626 #define IXGBE_FDIRCMD_CMD_POLL 10
2627 #define IXGBE_FDIRCMD_TUNNEL_FILTER 0x00800000
2628
2629 #define IXGBE_FDIR_DROP_QUEUE 127
2630
2631
2632 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792
2633 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448
2634 #define IXGBE_HI_COMMAND_TIMEOUT 500
2635 #define IXGBE_HI_FLASH_ERASE_TIMEOUT 1000
2636 #define IXGBE_HI_FLASH_UPDATE_TIMEOUT 5000
2637 #define IXGBE_HI_FLASH_APPLY_TIMEOUT 0
2638
2639
2640 #define FW_CEM_HDR_LEN 0x4
2641 #define FW_CEM_CMD_DRIVER_INFO 0xDD
2642 #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
2643 #define FW_CEM_CMD_RESERVED 0x0
2644 #define FW_CEM_UNUSED_VER 0x0
2645 #define FW_CEM_MAX_RETRIES 3
2646 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
2647 #define FW_CEM_DRIVER_VERSION_SIZE 39
2648 #define FW_READ_SHADOW_RAM_CMD 0x31
2649 #define FW_READ_SHADOW_RAM_LEN 0x6
2650 #define FW_WRITE_SHADOW_RAM_CMD 0x33
2651 #define FW_WRITE_SHADOW_RAM_LEN 0xA
2652 #define FW_SHADOW_RAM_DUMP_CMD 0x36
2653 #define FW_SHADOW_RAM_DUMP_LEN 0
2654 #define FW_DEFAULT_CHECKSUM 0xFF
2655 #define FW_NVM_DATA_OFFSET 3
2656 #define FW_MAX_READ_BUFFER_SIZE 1024
2657 #define FW_DISABLE_RXEN_CMD 0xDE
2658 #define FW_DISABLE_RXEN_LEN 0x1
2659 #define FW_PHY_MGMT_REQ_CMD 0x20
2660 #define FW_PHY_TOKEN_REQ_CMD 0x0A
2661 #define FW_PHY_TOKEN_REQ_LEN 2
2662 #define FW_PHY_TOKEN_REQ 0
2663 #define FW_PHY_TOKEN_REL 1
2664 #define FW_PHY_TOKEN_OK 1
2665 #define FW_PHY_TOKEN_RETRY 0x80
2666 #define FW_PHY_TOKEN_DELAY 5
2667 #define FW_PHY_TOKEN_WAIT 5
2668 #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)
2669 #define FW_INT_PHY_REQ_CMD 0xB
2670 #define FW_INT_PHY_REQ_LEN 10
2671 #define FW_INT_PHY_REQ_READ 0
2672 #define FW_INT_PHY_REQ_WRITE 1
2673 #define FW_PHY_ACT_REQ_CMD 5
2674 #define FW_PHY_ACT_DATA_COUNT 4
2675 #define FW_PHY_ACT_REQ_LEN (4 + 4 * FW_PHY_ACT_DATA_COUNT)
2676 #define FW_PHY_ACT_INIT_PHY 1
2677 #define FW_PHY_ACT_SETUP_LINK 2
2678 #define FW_PHY_ACT_LINK_SPEED_10 BIT(0)
2679 #define FW_PHY_ACT_LINK_SPEED_100 BIT(1)
2680 #define FW_PHY_ACT_LINK_SPEED_1G BIT(2)
2681 #define FW_PHY_ACT_LINK_SPEED_2_5G BIT(3)
2682 #define FW_PHY_ACT_LINK_SPEED_5G BIT(4)
2683 #define FW_PHY_ACT_LINK_SPEED_10G BIT(5)
2684 #define FW_PHY_ACT_LINK_SPEED_20G BIT(6)
2685 #define FW_PHY_ACT_LINK_SPEED_25G BIT(7)
2686 #define FW_PHY_ACT_LINK_SPEED_40G BIT(8)
2687 #define FW_PHY_ACT_LINK_SPEED_50G BIT(9)
2688 #define FW_PHY_ACT_LINK_SPEED_100G BIT(10)
2689 #define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16
2690 #define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3 << \
2691 HW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT)
2692 #define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u
2693 #define FW_PHY_ACT_SETUP_LINK_PAUSE_TX 1u
2694 #define FW_PHY_ACT_SETUP_LINK_PAUSE_RX 2u
2695 #define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u
2696 #define FW_PHY_ACT_SETUP_LINK_LP BIT(18)
2697 #define FW_PHY_ACT_SETUP_LINK_HP BIT(19)
2698 #define FW_PHY_ACT_SETUP_LINK_EEE BIT(20)
2699 #define FW_PHY_ACT_SETUP_LINK_AN BIT(22)
2700 #define FW_PHY_ACT_SETUP_LINK_RSP_DOWN BIT(0)
2701 #define FW_PHY_ACT_GET_LINK_INFO 3
2702 #define FW_PHY_ACT_GET_LINK_INFO_EEE BIT(19)
2703 #define FW_PHY_ACT_GET_LINK_INFO_FC_TX BIT(20)
2704 #define FW_PHY_ACT_GET_LINK_INFO_FC_RX BIT(21)
2705 #define FW_PHY_ACT_GET_LINK_INFO_POWER BIT(22)
2706 #define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE BIT(24)
2707 #define FW_PHY_ACT_GET_LINK_INFO_TEMP BIT(25)
2708 #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX BIT(28)
2709 #define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX BIT(29)
2710 #define FW_PHY_ACT_FORCE_LINK_DOWN 4
2711 #define FW_PHY_ACT_FORCE_LINK_DOWN_OFF BIT(0)
2712 #define FW_PHY_ACT_PHY_SW_RESET 5
2713 #define FW_PHY_ACT_PHY_HW_RESET 6
2714 #define FW_PHY_ACT_GET_PHY_INFO 7
2715 #define FW_PHY_ACT_UD_2 0x1002
2716 #define FW_PHY_ACT_UD_2_10G_KR_EEE BIT(6)
2717 #define FW_PHY_ACT_UD_2_10G_KX4_EEE BIT(5)
2718 #define FW_PHY_ACT_UD_2_1G_KX_EEE BIT(4)
2719 #define FW_PHY_ACT_UD_2_10G_T_EEE BIT(3)
2720 #define FW_PHY_ACT_UD_2_1G_T_EEE BIT(2)
2721 #define FW_PHY_ACT_UD_2_100M_TX_EEE BIT(1)
2722 #define FW_PHY_ACT_RETRIES 50
2723 #define FW_PHY_INFO_SPEED_MASK 0xFFFu
2724 #define FW_PHY_INFO_ID_HI_MASK 0xFFFF0000u
2725 #define FW_PHY_INFO_ID_LO_MASK 0x0000FFFFu
2726
2727
2728 struct ixgbe_hic_hdr {
2729 u8 cmd;
2730 u8 buf_len;
2731 union {
2732 u8 cmd_resv;
2733 u8 ret_status;
2734 } cmd_or_resp;
2735 u8 checksum;
2736 };
2737
2738 struct ixgbe_hic_hdr2_req {
2739 u8 cmd;
2740 u8 buf_lenh;
2741 u8 buf_lenl;
2742 u8 checksum;
2743 };
2744
2745 struct ixgbe_hic_hdr2_rsp {
2746 u8 cmd;
2747 u8 buf_lenl;
2748 u8 buf_lenh_status;
2749 u8 checksum;
2750 };
2751
2752 union ixgbe_hic_hdr2 {
2753 struct ixgbe_hic_hdr2_req req;
2754 struct ixgbe_hic_hdr2_rsp rsp;
2755 };
2756
2757 struct ixgbe_hic_drv_info {
2758 struct ixgbe_hic_hdr hdr;
2759 u8 port_num;
2760 u8 ver_sub;
2761 u8 ver_build;
2762 u8 ver_min;
2763 u8 ver_maj;
2764 u8 pad;
2765 u16 pad2;
2766 };
2767
2768 struct ixgbe_hic_drv_info2 {
2769 struct ixgbe_hic_hdr hdr;
2770 u8 port_num;
2771 u8 ver_sub;
2772 u8 ver_build;
2773 u8 ver_min;
2774 u8 ver_maj;
2775 char driver_string[FW_CEM_DRIVER_VERSION_SIZE];
2776 };
2777
2778
2779 struct ixgbe_hic_read_shadow_ram {
2780 union ixgbe_hic_hdr2 hdr;
2781 u32 address;
2782 u16 length;
2783 u16 pad2;
2784 u16 data;
2785 u16 pad3;
2786 };
2787
2788 struct ixgbe_hic_write_shadow_ram {
2789 union ixgbe_hic_hdr2 hdr;
2790 __be32 address;
2791 __be16 length;
2792 u16 pad2;
2793 u16 data;
2794 u16 pad3;
2795 };
2796
2797 struct ixgbe_hic_disable_rxen {
2798 struct ixgbe_hic_hdr hdr;
2799 u8 port_number;
2800 u8 pad2;
2801 u16 pad3;
2802 };
2803
2804 struct ixgbe_hic_phy_token_req {
2805 struct ixgbe_hic_hdr hdr;
2806 u8 port_number;
2807 u8 command_type;
2808 u16 pad;
2809 };
2810
2811 struct ixgbe_hic_internal_phy_req {
2812 struct ixgbe_hic_hdr hdr;
2813 u8 port_number;
2814 u8 command_type;
2815 __be16 address;
2816 u16 rsv1;
2817 __be32 write_data;
2818 u16 pad;
2819 } __packed;
2820
2821 struct ixgbe_hic_internal_phy_resp {
2822 struct ixgbe_hic_hdr hdr;
2823 __be32 read_data;
2824 };
2825
2826 struct ixgbe_hic_phy_activity_req {
2827 struct ixgbe_hic_hdr hdr;
2828 u8 port_number;
2829 u8 pad;
2830 __le16 activity_id;
2831 __be32 data[FW_PHY_ACT_DATA_COUNT];
2832 };
2833
2834 struct ixgbe_hic_phy_activity_resp {
2835 struct ixgbe_hic_hdr hdr;
2836 __be32 data[FW_PHY_ACT_DATA_COUNT];
2837 };
2838
2839
2840 union ixgbe_adv_tx_desc {
2841 struct {
2842 __le64 buffer_addr;
2843 __le32 cmd_type_len;
2844 __le32 olinfo_status;
2845 } read;
2846 struct {
2847 __le64 rsvd;
2848 __le32 nxtseq_seed;
2849 __le32 status;
2850 } wb;
2851 };
2852
2853
2854 union ixgbe_adv_rx_desc {
2855 struct {
2856 __le64 pkt_addr;
2857 __le64 hdr_addr;
2858 } read;
2859 struct {
2860 struct {
2861 union {
2862 __le32 data;
2863 struct {
2864 __le16 pkt_info;
2865 __le16 hdr_info;
2866 } hs_rss;
2867 } lo_dword;
2868 union {
2869 __le32 rss;
2870 struct {
2871 __le16 ip_id;
2872 __le16 csum;
2873 } csum_ip;
2874 } hi_dword;
2875 } lower;
2876 struct {
2877 __le32 status_error;
2878 __le16 length;
2879 __le16 vlan;
2880 } upper;
2881 } wb;
2882 };
2883
2884
2885 struct ixgbe_adv_tx_context_desc {
2886 __le32 vlan_macip_lens;
2887 __le32 fceof_saidx;
2888 __le32 type_tucmd_mlhl;
2889 __le32 mss_l4len_idx;
2890 };
2891
2892
2893 #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF
2894 #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000
2895 #define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000
2896 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF
2897 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF
2898 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000
2899 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000
2900 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000
2901 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP
2902 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS
2903 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS
2904 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000
2905 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT
2906 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE
2907 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000
2908 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD
2909 #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002
2910 #define IXGBE_ADVTXD_STAT_RSV 0x0000000C
2911 #define IXGBE_ADVTXD_IDX_SHIFT 4
2912 #define IXGBE_ADVTXD_CC 0x00000080
2913 #define IXGBE_ADVTXD_POPTS_SHIFT 8
2914 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
2915 IXGBE_ADVTXD_POPTS_SHIFT)
2916 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
2917 IXGBE_ADVTXD_POPTS_SHIFT)
2918 #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400
2919 #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000
2920 #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800
2921 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000
2922 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800
2923 #define IXGBE_ADVTXD_POPTS_RSV 0x00002000
2924 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14
2925 #define IXGBE_ADVTXD_MACLEN_SHIFT 9
2926 #define IXGBE_ADVTXD_VLAN_SHIFT 16
2927 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400
2928 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000
2929 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000
2930 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800
2931 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000
2932 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800
2933 #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000
2934 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000
2935 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000
2936 #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000
2937 #define IXGBE_ADVTXD_FCOEF_SOF (BIT(2) << 10)
2938 #define IXGBE_ADVTXD_FCOEF_PARINC (BIT(3) << 10)
2939 #define IXGBE_ADVTXD_FCOEF_ORIE (BIT(4) << 10)
2940 #define IXGBE_ADVTXD_FCOEF_ORIS (BIT(5) << 10)
2941 #define IXGBE_ADVTXD_FCOEF_EOF_N (0u << 10)
2942 #define IXGBE_ADVTXD_FCOEF_EOF_T (1u << 10)
2943 #define IXGBE_ADVTXD_FCOEF_EOF_NI (2u << 10)
2944 #define IXGBE_ADVTXD_FCOEF_EOF_A (3u << 10)
2945 #define IXGBE_ADVTXD_FCOEF_EOF_MASK (3u << 10)
2946 #define IXGBE_ADVTXD_L4LEN_SHIFT 8
2947 #define IXGBE_ADVTXD_MSS_SHIFT 16
2948
2949
2950 typedef u32 ixgbe_autoneg_advertised;
2951
2952 typedef u32 ixgbe_link_speed;
2953 #define IXGBE_LINK_SPEED_UNKNOWN 0
2954 #define IXGBE_LINK_SPEED_10_FULL 0x0002
2955 #define IXGBE_LINK_SPEED_100_FULL 0x0008
2956 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020
2957 #define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400
2958 #define IXGBE_LINK_SPEED_5GB_FULL 0x0800
2959 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080
2960 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2961 IXGBE_LINK_SPEED_10GB_FULL)
2962 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2963 IXGBE_LINK_SPEED_1GB_FULL | \
2964 IXGBE_LINK_SPEED_10GB_FULL)
2965
2966
2967
2968
2969
2970
2971 #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
2972 #define IXGBE_B2BT(BT) (BT * 8)
2973
2974
2975 #define IXGBE_PFC_D 672
2976
2977
2978 #define IXGBE_CABLE_DC 5556
2979 #define IXGBE_CABLE_DO 5000
2980
2981
2982 #define IXGBE_PHY_DC 25600
2983 #define IXGBE_MAC_DC 8192
2984 #define IXGBE_XAUI_DC (2 * 2048)
2985
2986 #define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
2987
2988
2989 #define IXGBE_PHY_D 12800
2990 #define IXGBE_MAC_D 4096
2991 #define IXGBE_XAUI_D (2 * 1024)
2992
2993 #define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
2994
2995
2996 #define IXGBE_HD 6144
2997
2998
2999 #define IXGBE_PCI_DELAY 10000
3000
3001
3002 #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
3003 ((36 * \
3004 (IXGBE_B2BT(_max_frame_link) + \
3005 IXGBE_PFC_D + \
3006 (2 * IXGBE_CABLE_DC) + \
3007 (2 * IXGBE_ID_X540) + \
3008 IXGBE_HD) / 25 + 1) + \
3009 2 * IXGBE_B2BT(_max_frame_tc))
3010
3011
3012 #define IXGBE_DV(_max_frame_link, _max_frame_tc) \
3013 ((36 * \
3014 (IXGBE_B2BT(_max_frame_link) + \
3015 IXGBE_PFC_D + \
3016 (2 * IXGBE_CABLE_DC) + \
3017 (2 * IXGBE_ID) + \
3018 IXGBE_HD) / 25 + 1) + \
3019 2 * IXGBE_B2BT(_max_frame_tc))
3020
3021
3022 #define IXGBE_LOW_DV_X540(_max_frame_tc) \
3023 (2 * IXGBE_B2BT(_max_frame_tc) + \
3024 (36 * IXGBE_PCI_DELAY / 25) + 1)
3025 #define IXGBE_LOW_DV(_max_frame_tc) \
3026 (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
3027
3028
3029 #define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
3030 #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
3031
3032
3033 #define IXGBE_ATR_HASH_MASK 0x7fff
3034 #define IXGBE_ATR_L4TYPE_MASK 0x3
3035 #define IXGBE_ATR_L4TYPE_UDP 0x1
3036 #define IXGBE_ATR_L4TYPE_TCP 0x2
3037 #define IXGBE_ATR_L4TYPE_SCTP 0x3
3038 #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
3039 #define IXGBE_ATR_L4TYPE_TUNNEL_MASK 0x10
3040 enum ixgbe_atr_flow_type {
3041 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
3042 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
3043 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
3044 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
3045 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
3046 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
3047 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
3048 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
3049 };
3050
3051
3052 union ixgbe_atr_input {
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066 struct {
3067 u8 vm_pool;
3068 u8 flow_type;
3069 __be16 vlan_id;
3070 __be32 dst_ip[4];
3071 __be32 src_ip[4];
3072 __be16 src_port;
3073 __be16 dst_port;
3074 __be16 flex_bytes;
3075 __be16 bkt_hash;
3076 } formatted;
3077 __be32 dword_stream[11];
3078 };
3079
3080
3081 union ixgbe_atr_hash_dword {
3082 struct {
3083 u8 vm_pool;
3084 u8 flow_type;
3085 __be16 vlan_id;
3086 } formatted;
3087 __be32 ip;
3088 struct {
3089 __be16 src;
3090 __be16 dst;
3091 } port;
3092 __be16 flex_bytes;
3093 __be32 dword;
3094 };
3095
3096 #define IXGBE_MVALS_INIT(m) \
3097 IXGBE_CAT(EEC, m), \
3098 IXGBE_CAT(FLA, m), \
3099 IXGBE_CAT(GRC, m), \
3100 IXGBE_CAT(FACTPS, m), \
3101 IXGBE_CAT(SWSM, m), \
3102 IXGBE_CAT(SWFW_SYNC, m), \
3103 IXGBE_CAT(FWSM, m), \
3104 IXGBE_CAT(SDP0_GPIEN, m), \
3105 IXGBE_CAT(SDP1_GPIEN, m), \
3106 IXGBE_CAT(SDP2_GPIEN, m), \
3107 IXGBE_CAT(EICR_GPI_SDP0, m), \
3108 IXGBE_CAT(EICR_GPI_SDP1, m), \
3109 IXGBE_CAT(EICR_GPI_SDP2, m), \
3110 IXGBE_CAT(CIAA, m), \
3111 IXGBE_CAT(CIAD, m), \
3112 IXGBE_CAT(I2C_CLK_IN, m), \
3113 IXGBE_CAT(I2C_CLK_OUT, m), \
3114 IXGBE_CAT(I2C_DATA_IN, m), \
3115 IXGBE_CAT(I2C_DATA_OUT, m), \
3116 IXGBE_CAT(I2C_DATA_OE_N_EN, m), \
3117 IXGBE_CAT(I2C_BB_EN, m), \
3118 IXGBE_CAT(I2C_CLK_OE_N_EN, m), \
3119 IXGBE_CAT(I2CCTL, m)
3120
3121 enum ixgbe_mvals {
3122 IXGBE_MVALS_INIT(IDX),
3123 IXGBE_MVALS_IDX_LIMIT
3124 };
3125
3126 enum ixgbe_eeprom_type {
3127 ixgbe_eeprom_uninitialized = 0,
3128 ixgbe_eeprom_spi,
3129 ixgbe_flash,
3130 ixgbe_eeprom_none
3131 };
3132
3133 enum ixgbe_mac_type {
3134 ixgbe_mac_unknown = 0,
3135 ixgbe_mac_82598EB,
3136 ixgbe_mac_82599EB,
3137 ixgbe_mac_X540,
3138 ixgbe_mac_X550,
3139 ixgbe_mac_X550EM_x,
3140 ixgbe_mac_x550em_a,
3141 ixgbe_num_macs
3142 };
3143
3144 enum ixgbe_phy_type {
3145 ixgbe_phy_unknown = 0,
3146 ixgbe_phy_none,
3147 ixgbe_phy_tn,
3148 ixgbe_phy_aq,
3149 ixgbe_phy_x550em_kr,
3150 ixgbe_phy_x550em_kx4,
3151 ixgbe_phy_x550em_xfi,
3152 ixgbe_phy_x550em_ext_t,
3153 ixgbe_phy_ext_1g_t,
3154 ixgbe_phy_cu_unknown,
3155 ixgbe_phy_qt,
3156 ixgbe_phy_xaui,
3157 ixgbe_phy_nl,
3158 ixgbe_phy_sfp_passive_tyco,
3159 ixgbe_phy_sfp_passive_unknown,
3160 ixgbe_phy_sfp_active_unknown,
3161 ixgbe_phy_sfp_avago,
3162 ixgbe_phy_sfp_ftl,
3163 ixgbe_phy_sfp_ftl_active,
3164 ixgbe_phy_sfp_unknown,
3165 ixgbe_phy_sfp_intel,
3166 ixgbe_phy_qsfp_passive_unknown,
3167 ixgbe_phy_qsfp_active_unknown,
3168 ixgbe_phy_qsfp_intel,
3169 ixgbe_phy_qsfp_unknown,
3170 ixgbe_phy_sfp_unsupported,
3171 ixgbe_phy_sgmii,
3172 ixgbe_phy_fw,
3173 ixgbe_phy_generic
3174 };
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189 enum ixgbe_sfp_type {
3190 ixgbe_sfp_type_da_cu = 0,
3191 ixgbe_sfp_type_sr = 1,
3192 ixgbe_sfp_type_lr = 2,
3193 ixgbe_sfp_type_da_cu_core0 = 3,
3194 ixgbe_sfp_type_da_cu_core1 = 4,
3195 ixgbe_sfp_type_srlr_core0 = 5,
3196 ixgbe_sfp_type_srlr_core1 = 6,
3197 ixgbe_sfp_type_da_act_lmt_core0 = 7,
3198 ixgbe_sfp_type_da_act_lmt_core1 = 8,
3199 ixgbe_sfp_type_1g_cu_core0 = 9,
3200 ixgbe_sfp_type_1g_cu_core1 = 10,
3201 ixgbe_sfp_type_1g_sx_core0 = 11,
3202 ixgbe_sfp_type_1g_sx_core1 = 12,
3203 ixgbe_sfp_type_1g_lx_core0 = 13,
3204 ixgbe_sfp_type_1g_lx_core1 = 14,
3205 ixgbe_sfp_type_not_present = 0xFFFE,
3206 ixgbe_sfp_type_unknown = 0xFFFF
3207 };
3208
3209 enum ixgbe_media_type {
3210 ixgbe_media_type_unknown = 0,
3211 ixgbe_media_type_fiber,
3212 ixgbe_media_type_fiber_qsfp,
3213 ixgbe_media_type_fiber_lco,
3214 ixgbe_media_type_copper,
3215 ixgbe_media_type_backplane,
3216 ixgbe_media_type_cx4,
3217 ixgbe_media_type_virtual
3218 };
3219
3220
3221 enum ixgbe_fc_mode {
3222 ixgbe_fc_none = 0,
3223 ixgbe_fc_rx_pause,
3224 ixgbe_fc_tx_pause,
3225 ixgbe_fc_full,
3226 ixgbe_fc_default
3227 };
3228
3229
3230 #define IXGBE_SMARTSPEED_MAX_RETRIES 3
3231 enum ixgbe_smart_speed {
3232 ixgbe_smart_speed_auto = 0,
3233 ixgbe_smart_speed_on,
3234 ixgbe_smart_speed_off
3235 };
3236
3237
3238 enum ixgbe_bus_type {
3239 ixgbe_bus_type_unknown = 0,
3240 ixgbe_bus_type_pci_express,
3241 ixgbe_bus_type_internal,
3242 ixgbe_bus_type_reserved
3243 };
3244
3245
3246 enum ixgbe_bus_speed {
3247 ixgbe_bus_speed_unknown = 0,
3248 ixgbe_bus_speed_33 = 33,
3249 ixgbe_bus_speed_66 = 66,
3250 ixgbe_bus_speed_100 = 100,
3251 ixgbe_bus_speed_120 = 120,
3252 ixgbe_bus_speed_133 = 133,
3253 ixgbe_bus_speed_2500 = 2500,
3254 ixgbe_bus_speed_5000 = 5000,
3255 ixgbe_bus_speed_8000 = 8000,
3256 ixgbe_bus_speed_reserved
3257 };
3258
3259
3260 enum ixgbe_bus_width {
3261 ixgbe_bus_width_unknown = 0,
3262 ixgbe_bus_width_pcie_x1 = 1,
3263 ixgbe_bus_width_pcie_x2 = 2,
3264 ixgbe_bus_width_pcie_x4 = 4,
3265 ixgbe_bus_width_pcie_x8 = 8,
3266 ixgbe_bus_width_32 = 32,
3267 ixgbe_bus_width_64 = 64,
3268 ixgbe_bus_width_reserved
3269 };
3270
3271 struct ixgbe_addr_filter_info {
3272 u32 num_mc_addrs;
3273 u32 rar_used_count;
3274 u32 mta_in_use;
3275 u32 overflow_promisc;
3276 bool uc_set_promisc;
3277 bool user_set_promisc;
3278 };
3279
3280
3281 struct ixgbe_bus_info {
3282 enum ixgbe_bus_speed speed;
3283 enum ixgbe_bus_width width;
3284 enum ixgbe_bus_type type;
3285
3286 u8 func;
3287 u8 lan_id;
3288 u8 instance_id;
3289 };
3290
3291
3292 struct ixgbe_fc_info {
3293 u32 high_water[MAX_TRAFFIC_CLASS];
3294 u32 low_water[MAX_TRAFFIC_CLASS];
3295 u16 pause_time;
3296 bool send_xon;
3297 bool strict_ieee;
3298 bool disable_fc_autoneg;
3299 bool fc_was_autonegged;
3300 enum ixgbe_fc_mode current_mode;
3301 enum ixgbe_fc_mode requested_mode;
3302 };
3303
3304
3305 struct ixgbe_hw_stats {
3306 u64 crcerrs;
3307 u64 illerrc;
3308 u64 errbc;
3309 u64 mspdc;
3310 u64 mpctotal;
3311 u64 mpc[8];
3312 u64 mlfc;
3313 u64 mrfc;
3314 u64 rlec;
3315 u64 lxontxc;
3316 u64 lxonrxc;
3317 u64 lxofftxc;
3318 u64 lxoffrxc;
3319 u64 pxontxc[8];
3320 u64 pxonrxc[8];
3321 u64 pxofftxc[8];
3322 u64 pxoffrxc[8];
3323 u64 prc64;
3324 u64 prc127;
3325 u64 prc255;
3326 u64 prc511;
3327 u64 prc1023;
3328 u64 prc1522;
3329 u64 gprc;
3330 u64 bprc;
3331 u64 mprc;
3332 u64 gptc;
3333 u64 gorc;
3334 u64 gotc;
3335 u64 rnbc[8];
3336 u64 ruc;
3337 u64 rfc;
3338 u64 roc;
3339 u64 rjc;
3340 u64 mngprc;
3341 u64 mngpdc;
3342 u64 mngptc;
3343 u64 tor;
3344 u64 tpr;
3345 u64 tpt;
3346 u64 ptc64;
3347 u64 ptc127;
3348 u64 ptc255;
3349 u64 ptc511;
3350 u64 ptc1023;
3351 u64 ptc1522;
3352 u64 mptc;
3353 u64 bptc;
3354 u64 xec;
3355 u64 rqsmr[16];
3356 u64 tqsmr[8];
3357 u64 qprc[16];
3358 u64 qptc[16];
3359 u64 qbrc[16];
3360 u64 qbtc[16];
3361 u64 qprdc[16];
3362 u64 pxon2offc[8];
3363 u64 fdirustat_add;
3364 u64 fdirustat_remove;
3365 u64 fdirfstat_fadd;
3366 u64 fdirfstat_fremove;
3367 u64 fdirmatch;
3368 u64 fdirmiss;
3369 u64 fccrc;
3370 u64 fcoerpdc;
3371 u64 fcoeprc;
3372 u64 fcoeptc;
3373 u64 fcoedwrc;
3374 u64 fcoedwtc;
3375 u64 fcoe_noddp;
3376 u64 fcoe_noddp_ext_buff;
3377 u64 b2ospc;
3378 u64 b2ogprc;
3379 u64 o2bgptc;
3380 u64 o2bspc;
3381 };
3382
3383
3384 struct ixgbe_hw;
3385
3386
3387 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
3388 u32 *vmdq);
3389
3390
3391 struct ixgbe_eeprom_operations {
3392 s32 (*init_params)(struct ixgbe_hw *);
3393 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
3394 s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3395 s32 (*write)(struct ixgbe_hw *, u16, u16);
3396 s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3397 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
3398 s32 (*update_checksum)(struct ixgbe_hw *);
3399 s32 (*calc_checksum)(struct ixgbe_hw *);
3400 };
3401
3402 struct ixgbe_mac_operations {
3403 s32 (*init_hw)(struct ixgbe_hw *);
3404 s32 (*reset_hw)(struct ixgbe_hw *);
3405 s32 (*start_hw)(struct ixgbe_hw *);
3406 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
3407 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
3408 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
3409 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
3410 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
3411 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
3412 s32 (*stop_adapter)(struct ixgbe_hw *);
3413 s32 (*get_bus_info)(struct ixgbe_hw *);
3414 void (*set_lan_id)(struct ixgbe_hw *);
3415 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
3416 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
3417 s32 (*setup_sfp)(struct ixgbe_hw *);
3418 s32 (*disable_rx_buff)(struct ixgbe_hw *);
3419 s32 (*enable_rx_buff)(struct ixgbe_hw *);
3420 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
3421 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
3422 void (*release_swfw_sync)(struct ixgbe_hw *, u32);
3423 void (*init_swfw_sync)(struct ixgbe_hw *);
3424 s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
3425 s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
3426
3427
3428 void (*disable_tx_laser)(struct ixgbe_hw *);
3429 void (*enable_tx_laser)(struct ixgbe_hw *);
3430 void (*flap_tx_laser)(struct ixgbe_hw *);
3431 void (*stop_link_on_d3)(struct ixgbe_hw *);
3432 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3433 s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3434 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
3435 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
3436 bool *);
3437 void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed);
3438
3439
3440 void (*set_rxpba)(struct ixgbe_hw *, int, u32, int);
3441
3442
3443 s32 (*led_on)(struct ixgbe_hw *, u32);
3444 s32 (*led_off)(struct ixgbe_hw *, u32);
3445 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
3446 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
3447 s32 (*init_led_link_act)(struct ixgbe_hw *);
3448
3449
3450 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
3451 s32 (*clear_rar)(struct ixgbe_hw *, u32);
3452 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
3453 s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
3454 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3455 s32 (*init_rx_addrs)(struct ixgbe_hw *);
3456 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
3457 s32 (*enable_mc)(struct ixgbe_hw *);
3458 s32 (*disable_mc)(struct ixgbe_hw *);
3459 s32 (*clear_vfta)(struct ixgbe_hw *);
3460 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool);
3461 s32 (*init_uta_tables)(struct ixgbe_hw *);
3462 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3463 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3464
3465
3466 s32 (*fc_enable)(struct ixgbe_hw *);
3467 s32 (*setup_fc)(struct ixgbe_hw *);
3468 void (*fc_autoneg)(struct ixgbe_hw *);
3469
3470
3471 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16,
3472 const char *);
3473 s32 (*get_thermal_sensor_data)(struct ixgbe_hw *);
3474 s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);
3475 bool (*fw_recovery_mode)(struct ixgbe_hw *hw);
3476 void (*disable_rx)(struct ixgbe_hw *hw);
3477 void (*enable_rx)(struct ixgbe_hw *hw);
3478 void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
3479 unsigned int);
3480 void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);
3481
3482
3483 s32 (*dmac_config)(struct ixgbe_hw *hw);
3484 s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
3485 s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);
3486 s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *);
3487 s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32);
3488 };
3489
3490 struct ixgbe_phy_operations {
3491 s32 (*identify)(struct ixgbe_hw *);
3492 s32 (*identify_sfp)(struct ixgbe_hw *);
3493 s32 (*init)(struct ixgbe_hw *);
3494 s32 (*reset)(struct ixgbe_hw *);
3495 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
3496 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3497 s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
3498 s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
3499 s32 (*setup_link)(struct ixgbe_hw *);
3500 s32 (*setup_internal_link)(struct ixgbe_hw *);
3501 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3502 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3503 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3504 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
3505 s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
3506 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
3507 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3508 s32 (*check_overtemp)(struct ixgbe_hw *);
3509 s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
3510 s32 (*enter_lplu)(struct ixgbe_hw *);
3511 s32 (*handle_lasi)(struct ixgbe_hw *hw);
3512 s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3513 u8 *value);
3514 s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,
3515 u8 value);
3516 };
3517
3518 struct ixgbe_link_operations {
3519 s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
3520 s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3521 u16 *val);
3522 s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
3523 s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3524 u16 val);
3525 };
3526
3527 struct ixgbe_link_info {
3528 struct ixgbe_link_operations ops;
3529 u8 addr;
3530 };
3531
3532 struct ixgbe_eeprom_info {
3533 struct ixgbe_eeprom_operations ops;
3534 enum ixgbe_eeprom_type type;
3535 u32 semaphore_delay;
3536 u16 word_size;
3537 u16 address_bits;
3538 u16 word_page_size;
3539 u16 ctrl_word_3;
3540 };
3541
3542 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
3543 struct ixgbe_mac_info {
3544 struct ixgbe_mac_operations ops;
3545 enum ixgbe_mac_type type;
3546 u8 addr[ETH_ALEN];
3547 u8 perm_addr[ETH_ALEN];
3548 u8 san_addr[ETH_ALEN];
3549
3550 u16 wwnn_prefix;
3551
3552 u16 wwpn_prefix;
3553 u16 max_msix_vectors;
3554 #define IXGBE_MAX_MTA 128
3555 u32 mta_shadow[IXGBE_MAX_MTA];
3556 s32 mc_filter_type;
3557 u32 mcft_size;
3558 u32 vft_size;
3559 u32 num_rar_entries;
3560 u32 rar_highwater;
3561 u32 rx_pb_size;
3562 u32 max_tx_queues;
3563 u32 max_rx_queues;
3564 u32 orig_autoc;
3565 u32 orig_autoc2;
3566 bool orig_link_settings_stored;
3567 bool autotry_restart;
3568 u8 flags;
3569 u8 san_mac_rar_index;
3570 struct ixgbe_thermal_sensor_data thermal_sensor_data;
3571 bool set_lben;
3572 u8 led_link_act;
3573 };
3574
3575 struct ixgbe_phy_info {
3576 struct ixgbe_phy_operations ops;
3577 struct mdio_if_info mdio;
3578 enum ixgbe_phy_type type;
3579 u32 id;
3580 enum ixgbe_sfp_type sfp_type;
3581 bool sfp_setup_needed;
3582 u32 revision;
3583 enum ixgbe_media_type media_type;
3584 u32 phy_semaphore_mask;
3585 bool reset_disable;
3586 ixgbe_autoneg_advertised autoneg_advertised;
3587 ixgbe_link_speed speeds_supported;
3588 ixgbe_link_speed eee_speeds_supported;
3589 ixgbe_link_speed eee_speeds_advertised;
3590 enum ixgbe_smart_speed smart_speed;
3591 bool smart_speed_active;
3592 bool multispeed_fiber;
3593 bool reset_if_overtemp;
3594 bool qsfp_shared_i2c_bus;
3595 u32 nw_mng_if_sel;
3596 };
3597
3598 #include "ixgbe_mbx.h"
3599
3600 struct ixgbe_mbx_operations {
3601 s32 (*init_params)(struct ixgbe_hw *hw);
3602 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
3603 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
3604 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3605 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3606 s32 (*check_for_msg)(struct ixgbe_hw *, u16);
3607 s32 (*check_for_ack)(struct ixgbe_hw *, u16);
3608 s32 (*check_for_rst)(struct ixgbe_hw *, u16);
3609 };
3610
3611 struct ixgbe_mbx_stats {
3612 u32 msgs_tx;
3613 u32 msgs_rx;
3614
3615 u32 acks;
3616 u32 reqs;
3617 u32 rsts;
3618 };
3619
3620 struct ixgbe_mbx_info {
3621 const struct ixgbe_mbx_operations *ops;
3622 struct ixgbe_mbx_stats stats;
3623 u32 timeout;
3624 u32 usec_delay;
3625 u32 v2p_mailbox;
3626 u16 size;
3627 };
3628
3629 struct ixgbe_hw {
3630 u8 __iomem *hw_addr;
3631 void *back;
3632 struct ixgbe_mac_info mac;
3633 struct ixgbe_addr_filter_info addr_ctrl;
3634 struct ixgbe_fc_info fc;
3635 struct ixgbe_phy_info phy;
3636 struct ixgbe_link_info link;
3637 struct ixgbe_eeprom_info eeprom;
3638 struct ixgbe_bus_info bus;
3639 struct ixgbe_mbx_info mbx;
3640 const u32 *mvals;
3641 u16 device_id;
3642 u16 vendor_id;
3643 u16 subsystem_device_id;
3644 u16 subsystem_vendor_id;
3645 u8 revision_id;
3646 bool adapter_stopped;
3647 bool force_full_reset;
3648 bool allow_unsupported_sfp;
3649 bool wol_enabled;
3650 bool need_crosstalk_fix;
3651 };
3652
3653 struct ixgbe_info {
3654 enum ixgbe_mac_type mac;
3655 s32 (*get_invariants)(struct ixgbe_hw *);
3656 const struct ixgbe_mac_operations *mac_ops;
3657 const struct ixgbe_eeprom_operations *eeprom_ops;
3658 const struct ixgbe_phy_operations *phy_ops;
3659 const struct ixgbe_mbx_operations *mbx_ops;
3660 const struct ixgbe_link_operations *link_ops;
3661 const u32 *mvals;
3662 };
3663
3664
3665
3666 #define IXGBE_ERR_EEPROM -1
3667 #define IXGBE_ERR_EEPROM_CHECKSUM -2
3668 #define IXGBE_ERR_PHY -3
3669 #define IXGBE_ERR_CONFIG -4
3670 #define IXGBE_ERR_PARAM -5
3671 #define IXGBE_ERR_MAC_TYPE -6
3672 #define IXGBE_ERR_UNKNOWN_PHY -7
3673 #define IXGBE_ERR_LINK_SETUP -8
3674 #define IXGBE_ERR_ADAPTER_STOPPED -9
3675 #define IXGBE_ERR_INVALID_MAC_ADDR -10
3676 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
3677 #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
3678 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13
3679 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
3680 #define IXGBE_ERR_RESET_FAILED -15
3681 #define IXGBE_ERR_SWFW_SYNC -16
3682 #define IXGBE_ERR_PHY_ADDR_INVALID -17
3683 #define IXGBE_ERR_I2C -18
3684 #define IXGBE_ERR_SFP_NOT_SUPPORTED -19
3685 #define IXGBE_ERR_SFP_NOT_PRESENT -20
3686 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
3687 #define IXGBE_ERR_NO_SAN_ADDR_PTR -22
3688 #define IXGBE_ERR_FDIR_REINIT_FAILED -23
3689 #define IXGBE_ERR_EEPROM_VERSION -24
3690 #define IXGBE_ERR_NO_SPACE -25
3691 #define IXGBE_ERR_OVERTEMP -26
3692 #define IXGBE_ERR_FC_NOT_NEGOTIATED -27
3693 #define IXGBE_ERR_FC_NOT_SUPPORTED -28
3694 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
3695 #define IXGBE_ERR_PBA_SECTION -31
3696 #define IXGBE_ERR_INVALID_ARGUMENT -32
3697 #define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
3698 #define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38
3699 #define IXGBE_ERR_FW_RESP_INVALID -39
3700 #define IXGBE_ERR_TOKEN_RETRY -40
3701 #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
3702
3703 #define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
3704 #define IXGBE_FUSES0_300MHZ BIT(5)
3705 #define IXGBE_FUSES0_REV_MASK (3u << 6)
3706
3707 #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
3708 #define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200)
3709 #define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
3710 #define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C)
3711 #define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248)
3712 #define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0)
3713 #define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C)
3714 #define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
3715 #define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
3716 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
3717 #define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00)
3718 #define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054)
3719 #define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)
3720 #define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)
3721
3722 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA ~(0x3 << 20)
3723 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR BIT(20)
3724 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR (0x2 << 20)
3725 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN BIT(25)
3726 #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN BIT(26)
3727 #define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN BIT(27)
3728 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M ~(0x7 << 28)
3729 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M BIT(28)
3730 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G (0x2 << 28)
3731 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G (0x3 << 28)
3732 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN (0x4 << 28)
3733 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G (0x7 << 28)
3734 #define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK (0x7 << 28)
3735 #define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART BIT(31)
3736
3737 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B BIT(9)
3738 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS BIT(11)
3739
3740 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (7u << 8)
3741 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2u << 8)
3742 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4u << 8)
3743 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN BIT(12)
3744 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN BIT(13)
3745 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ BIT(14)
3746 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC BIT(15)
3747 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX BIT(16)
3748 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR BIT(18)
3749 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX BIT(24)
3750 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR BIT(26)
3751 #define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE BIT(28)
3752 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE BIT(29)
3753 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART BIT(31)
3754
3755 #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE BIT(28)
3756 #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE BIT(29)
3757
3758 #define IXGBE_KRM_AN_CNTL_8_LINEAR BIT(0)
3759 #define IXGBE_KRM_AN_CNTL_8_LIMITING BIT(1)
3760
3761 #define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE BIT(10)
3762 #define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE BIT(11)
3763 #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D BIT(12)
3764 #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D BIT(19)
3765
3766 #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN BIT(6)
3767 #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN BIT(15)
3768 #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN BIT(16)
3769
3770 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL BIT(4)
3771 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS BIT(2)
3772
3773 #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (3u << 16)
3774
3775 #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN BIT(1)
3776 #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN BIT(2)
3777 #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN BIT(3)
3778 #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN BIT(31)
3779
3780 #define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144
3781 #define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148
3782
3783 #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0
3784 #define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF
3785 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18
3786 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \
3787 (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
3788 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20
3789 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \
3790 (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
3791 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28
3792 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7
3793 #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31
3794 #define IXGBE_SB_IOSF_CTRL_BUSY BIT(IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
3795 #define IXGBE_SB_IOSF_TARGET_KR_PHY 0
3796
3797 #define IXGBE_NW_MNG_IF_SEL 0x00011178
3798 #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT BIT(1)
3799 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M BIT(17)
3800 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M BIT(18)
3801 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G BIT(19)
3802 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G BIT(20)
3803 #define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G BIT(21)
3804 #define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE BIT(25)
3805 #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE BIT(24)
3806 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3
3807 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \
3808 (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
3809 #endif