drivers/net/ethernet/toshiba/tc35815.c

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This source file includes following definitions.
fd_virt_to_bus
fd_bus_to_virt
alloc_rxbuf_skb
free_rxbuf_skb
tc_mdio_read
tc_mdio_write
tc_handle_link_change
tc_mii_probe
tc_mii_init
tc35815_mac_match
tc35815_read_plat_dev_addr
tc35815_read_plat_dev_addr
tc35815_init_dev_addr
tc35815_init_one
tc35815_remove_one
tc35815_init_queues
tc35815_clear_queues
tc35815_free_queues
dump_txfd
dump_rxfd
dump_frfd
panic_queues
print_eth
tc35815_tx_full
tc35815_restart
tc35815_restart_work
tc35815_schedule_restart
tc35815_tx_timeout
tc35815_open
tc35815_send_packet
tc35815_fatal_error_interrupt
tc35815_do_interrupt
tc35815_interrupt
tc35815_poll_controller
tc35815_rx
tc35815_poll
tc35815_check_tx_stat
tc35815_txdone
tc35815_close
tc35815_get_stats
tc35815_set_cam_entry
tc35815_set_multicast_list
tc35815_get_drvinfo
tc35815_get_msglevel
tc35815_set_msglevel
tc35815_get_sset_count
tc35815_get_ethtool_stats
tc35815_get_strings
tc35815_ioctl
tc35815_chip_reset
tc35815_chip_init
tc35815_suspend
tc35815_resume
   1 /*
   2  * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
   3  *
   4  * Based on skelton.c by Donald Becker.
   5  *
   6  * This driver is a replacement of older and less maintained version.
   7  * This is a header of the older version:
   8  *      -----<snip>-----
   9  *      Copyright 2001 MontaVista Software Inc.
  10  *      Author: MontaVista Software, Inc.
  11  *              ahennessy@mvista.com
  12  *      Copyright (C) 2000-2001 Toshiba Corporation
  13  *      static const char *version =
  14  *              "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
  15  *      -----<snip>-----
  16  *
  17  * This file is subject to the terms and conditions of the GNU General Public
  18  * License.  See the file "COPYING" in the main directory of this archive
  19  * for more details.
  20  *
  21  * (C) Copyright TOSHIBA CORPORATION 2004-2005
  22  * All Rights Reserved.
  23  */
  24 
  25 #define DRV_VERSION     "1.39"
  26 static const char version[] = "tc35815.c:v" DRV_VERSION "\n";
  27 #define MODNAME                 "tc35815"
  28 
  29 #include <linux/module.h>
  30 #include <linux/kernel.h>
  31 #include <linux/types.h>
  32 #include <linux/fcntl.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ioport.h>
  35 #include <linux/in.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/slab.h>
  38 #include <linux/string.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/errno.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/skbuff.h>
  44 #include <linux/delay.h>
  45 #include <linux/pci.h>
  46 #include <linux/phy.h>
  47 #include <linux/workqueue.h>
  48 #include <linux/platform_device.h>
  49 #include <linux/prefetch.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 
  53 enum tc35815_chiptype {
  54         TC35815CF = 0,
  55         TC35815_NWU,
  56         TC35815_TX4939,
  57 };
  58 
  59 /* indexed by tc35815_chiptype, above */
  60 static const struct {
  61         const char *name;
  62 } chip_info[] = {
  63         { "TOSHIBA TC35815CF 10/100BaseTX" },
  64         { "TOSHIBA TC35815 with Wake on LAN" },
  65         { "TOSHIBA TC35815/TX4939" },
  66 };
  67 
  68 static const struct pci_device_id tc35815_pci_tbl[] = {
  69         {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
  70         {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
  71         {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
  72         {0,}
  73 };
  74 MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
  75 
  76 /* see MODULE_PARM_DESC */
  77 static struct tc35815_options {
  78         int speed;
  79         int duplex;
  80 } options;
  81 
  82 /*
  83  * Registers
  84  */
  85 struct tc35815_regs {
  86         __u32 DMA_Ctl;          /* 0x00 */
  87         __u32 TxFrmPtr;
  88         __u32 TxThrsh;
  89         __u32 TxPollCtr;
  90         __u32 BLFrmPtr;
  91         __u32 RxFragSize;
  92         __u32 Int_En;
  93         __u32 FDA_Bas;
  94         __u32 FDA_Lim;          /* 0x20 */
  95         __u32 Int_Src;
  96         __u32 unused0[2];
  97         __u32 PauseCnt;
  98         __u32 RemPauCnt;
  99         __u32 TxCtlFrmStat;
 100         __u32 unused1;
 101         __u32 MAC_Ctl;          /* 0x40 */
 102         __u32 CAM_Ctl;
 103         __u32 Tx_Ctl;
 104         __u32 Tx_Stat;
 105         __u32 Rx_Ctl;
 106         __u32 Rx_Stat;
 107         __u32 MD_Data;
 108         __u32 MD_CA;
 109         __u32 CAM_Adr;          /* 0x60 */
 110         __u32 CAM_Data;
 111         __u32 CAM_Ena;
 112         __u32 PROM_Ctl;
 113         __u32 PROM_Data;
 114         __u32 Algn_Cnt;
 115         __u32 CRC_Cnt;
 116         __u32 Miss_Cnt;
 117 };
 118 
 119 /*
 120  * Bit assignments
 121  */
 122 /* DMA_Ctl bit assign ------------------------------------------------------- */
 123 #define DMA_RxAlign            0x00c00000 /* 1:Reception Alignment           */
 124 #define DMA_RxAlign_1          0x00400000
 125 #define DMA_RxAlign_2          0x00800000
 126 #define DMA_RxAlign_3          0x00c00000
 127 #define DMA_M66EnStat          0x00080000 /* 1:66MHz Enable State            */
 128 #define DMA_IntMask            0x00040000 /* 1:Interrupt mask                */
 129 #define DMA_SWIntReq           0x00020000 /* 1:Software Interrupt request    */
 130 #define DMA_TxWakeUp           0x00010000 /* 1:Transmit Wake Up              */
 131 #define DMA_RxBigE             0x00008000 /* 1:Receive Big Endian            */
 132 #define DMA_TxBigE             0x00004000 /* 1:Transmit Big Endian           */
 133 #define DMA_TestMode           0x00002000 /* 1:Test Mode                     */
 134 #define DMA_PowrMgmnt          0x00001000 /* 1:Power Management              */
 135 #define DMA_DmBurst_Mask       0x000001fc /* DMA Burst size                  */
 136 
 137 /* RxFragSize bit assign ---------------------------------------------------- */
 138 #define RxFrag_EnPack          0x00008000 /* 1:Enable Packing                */
 139 #define RxFrag_MinFragMask     0x00000ffc /* Minimum Fragment                */
 140 
 141 /* MAC_Ctl bit assign ------------------------------------------------------- */
 142 #define MAC_Link10             0x00008000 /* 1:Link Status 10Mbits           */
 143 #define MAC_EnMissRoll         0x00002000 /* 1:Enable Missed Roll            */
 144 #define MAC_MissRoll           0x00000400 /* 1:Missed Roll                   */
 145 #define MAC_Loop10             0x00000080 /* 1:Loop 10 Mbps                  */
 146 #define MAC_Conn_Auto          0x00000000 /*00:Connection mode (Automatic)   */
 147 #define MAC_Conn_10M           0x00000020 /*01:                (10Mbps endec)*/
 148 #define MAC_Conn_Mll           0x00000040 /*10:                (Mll clock)   */
 149 #define MAC_MacLoop            0x00000010 /* 1:MAC Loopback                  */
 150 #define MAC_FullDup            0x00000008 /* 1:Full Duplex 0:Half Duplex     */
 151 #define MAC_Reset              0x00000004 /* 1:Software Reset                */
 152 #define MAC_HaltImm            0x00000002 /* 1:Halt Immediate                */
 153 #define MAC_HaltReq            0x00000001 /* 1:Halt request                  */
 154 
 155 /* PROM_Ctl bit assign ------------------------------------------------------ */
 156 #define PROM_Busy              0x00008000 /* 1:Busy (Start Operation)        */
 157 #define PROM_Read              0x00004000 /*10:Read operation                */
 158 #define PROM_Write             0x00002000 /*01:Write operation               */
 159 #define PROM_Erase             0x00006000 /*11:Erase operation               */
 160                                           /*00:Enable or Disable Writting,   */
 161                                           /*      as specified in PROM_Addr. */
 162 #define PROM_Addr_Ena          0x00000030 /*11xxxx:PROM Write enable         */
 163                                           /*00xxxx:           disable        */
 164 
 165 /* CAM_Ctl bit assign ------------------------------------------------------- */
 166 #define CAM_CompEn             0x00000010 /* 1:CAM Compare Enable            */
 167 #define CAM_NegCAM             0x00000008 /* 1:Reject packets CAM recognizes,*/
 168                                           /*                    accept other */
 169 #define CAM_BroadAcc           0x00000004 /* 1:Broadcast assept              */
 170 #define CAM_GroupAcc           0x00000002 /* 1:Multicast assept              */
 171 #define CAM_StationAcc         0x00000001 /* 1:unicast accept                */
 172 
 173 /* CAM_Ena bit assign ------------------------------------------------------- */
 174 #define CAM_ENTRY_MAX                  21   /* CAM Data entry max count      */
 175 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits)  */
 176 #define CAM_Ena_Bit(index)      (1 << (index))
 177 #define CAM_ENTRY_DESTINATION   0
 178 #define CAM_ENTRY_SOURCE        1
 179 #define CAM_ENTRY_MACCTL        20
 180 
 181 /* Tx_Ctl bit assign -------------------------------------------------------- */
 182 #define Tx_En                  0x00000001 /* 1:Transmit enable               */
 183 #define Tx_TxHalt              0x00000002 /* 1:Transmit Halt Request         */
 184 #define Tx_NoPad               0x00000004 /* 1:Suppress Padding              */
 185 #define Tx_NoCRC               0x00000008 /* 1:Suppress Padding              */
 186 #define Tx_FBack               0x00000010 /* 1:Fast Back-off                 */
 187 #define Tx_EnUnder             0x00000100 /* 1:Enable Underrun               */
 188 #define Tx_EnExDefer           0x00000200 /* 1:Enable Excessive Deferral     */
 189 #define Tx_EnLCarr             0x00000400 /* 1:Enable Lost Carrier           */
 190 #define Tx_EnExColl            0x00000800 /* 1:Enable Excessive Collision    */
 191 #define Tx_EnLateColl          0x00001000 /* 1:Enable Late Collision         */
 192 #define Tx_EnTxPar             0x00002000 /* 1:Enable Transmit Parity        */
 193 #define Tx_EnComp              0x00004000 /* 1:Enable Completion             */
 194 
 195 /* Tx_Stat bit assign ------------------------------------------------------- */
 196 #define Tx_TxColl_MASK         0x0000000F /* Tx Collision Count              */
 197 #define Tx_ExColl              0x00000010 /* Excessive Collision             */
 198 #define Tx_TXDefer             0x00000020 /* Transmit Defered                */
 199 #define Tx_Paused              0x00000040 /* Transmit Paused                 */
 200 #define Tx_IntTx               0x00000080 /* Interrupt on Tx                 */
 201 #define Tx_Under               0x00000100 /* Underrun                        */
 202 #define Tx_Defer               0x00000200 /* Deferral                        */
 203 #define Tx_NCarr               0x00000400 /* No Carrier                      */
 204 #define Tx_10Stat              0x00000800 /* 10Mbps Status                   */
 205 #define Tx_LateColl            0x00001000 /* Late Collision                  */
 206 #define Tx_TxPar               0x00002000 /* Tx Parity Error                 */
 207 #define Tx_Comp                0x00004000 /* Completion                      */
 208 #define Tx_Halted              0x00008000 /* Tx Halted                       */
 209 #define Tx_SQErr               0x00010000 /* Signal Quality Error(SQE)       */
 210 
 211 /* Rx_Ctl bit assign -------------------------------------------------------- */
 212 #define Rx_EnGood              0x00004000 /* 1:Enable Good                   */
 213 #define Rx_EnRxPar             0x00002000 /* 1:Enable Receive Parity         */
 214 #define Rx_EnLongErr           0x00000800 /* 1:Enable Long Error             */
 215 #define Rx_EnOver              0x00000400 /* 1:Enable OverFlow               */
 216 #define Rx_EnCRCErr            0x00000200 /* 1:Enable CRC Error              */
 217 #define Rx_EnAlign             0x00000100 /* 1:Enable Alignment              */
 218 #define Rx_IgnoreCRC           0x00000040 /* 1:Ignore CRC Value              */
 219 #define Rx_StripCRC            0x00000010 /* 1:Strip CRC Value               */
 220 #define Rx_ShortEn             0x00000008 /* 1:Short Enable                  */
 221 #define Rx_LongEn              0x00000004 /* 1:Long Enable                   */
 222 #define Rx_RxHalt              0x00000002 /* 1:Receive Halt Request          */
 223 #define Rx_RxEn                0x00000001 /* 1:Receive Intrrupt Enable       */
 224 
 225 /* Rx_Stat bit assign ------------------------------------------------------- */
 226 #define Rx_Halted              0x00008000 /* Rx Halted                       */
 227 #define Rx_Good                0x00004000 /* Rx Good                         */
 228 #define Rx_RxPar               0x00002000 /* Rx Parity Error                 */
 229 #define Rx_TypePkt             0x00001000 /* Rx Type Packet                  */
 230 #define Rx_LongErr             0x00000800 /* Rx Long Error                   */
 231 #define Rx_Over                0x00000400 /* Rx Overflow                     */
 232 #define Rx_CRCErr              0x00000200 /* Rx CRC Error                    */
 233 #define Rx_Align               0x00000100 /* Rx Alignment Error              */
 234 #define Rx_10Stat              0x00000080 /* Rx 10Mbps Status                */
 235 #define Rx_IntRx               0x00000040 /* Rx Interrupt                    */
 236 #define Rx_CtlRecd             0x00000020 /* Rx Control Receive              */
 237 #define Rx_InLenErr            0x00000010 /* Rx In Range Frame Length Error  */
 238 
 239 #define Rx_Stat_Mask           0x0000FFF0 /* Rx All Status Mask              */
 240 
 241 /* Int_En bit assign -------------------------------------------------------- */
 242 #define Int_NRAbtEn            0x00000800 /* 1:Non-recoverable Abort Enable  */
 243 #define Int_TxCtlCmpEn         0x00000400 /* 1:Transmit Ctl Complete Enable  */
 244 #define Int_DmParErrEn         0x00000200 /* 1:DMA Parity Error Enable       */
 245 #define Int_DParDEn            0x00000100 /* 1:Data Parity Error Enable      */
 246 #define Int_EarNotEn           0x00000080 /* 1:Early Notify Enable           */
 247 #define Int_DParErrEn          0x00000040 /* 1:Detected Parity Error Enable  */
 248 #define Int_SSysErrEn          0x00000020 /* 1:Signalled System Error Enable */
 249 #define Int_RMasAbtEn          0x00000010 /* 1:Received Master Abort Enable  */
 250 #define Int_RTargAbtEn         0x00000008 /* 1:Received Target Abort Enable  */
 251 #define Int_STargAbtEn         0x00000004 /* 1:Signalled Target Abort Enable */
 252 #define Int_BLExEn             0x00000002 /* 1:Buffer List Exhausted Enable  */
 253 #define Int_FDAExEn            0x00000001 /* 1:Free Descriptor Area          */
 254                                           /*               Exhausted Enable  */
 255 
 256 /* Int_Src bit assign ------------------------------------------------------- */
 257 #define Int_NRabt              0x00004000 /* 1:Non Recoverable error         */
 258 #define Int_DmParErrStat       0x00002000 /* 1:DMA Parity Error & Clear      */
 259 #define Int_BLEx               0x00001000 /* 1:Buffer List Empty & Clear     */
 260 #define Int_FDAEx              0x00000800 /* 1:FDA Empty & Clear             */
 261 #define Int_IntNRAbt           0x00000400 /* 1:Non Recoverable Abort         */
 262 #define Int_IntCmp             0x00000200 /* 1:MAC control packet complete   */
 263 #define Int_IntExBD            0x00000100 /* 1:Interrupt Extra BD & Clear    */
 264 #define Int_DmParErr           0x00000080 /* 1:DMA Parity Error & Clear      */
 265 #define Int_IntEarNot          0x00000040 /* 1:Receive Data write & Clear    */
 266 #define Int_SWInt              0x00000020 /* 1:Software request & Clear      */
 267 #define Int_IntBLEx            0x00000010 /* 1:Buffer List Empty & Clear     */
 268 #define Int_IntFDAEx           0x00000008 /* 1:FDA Empty & Clear             */
 269 #define Int_IntPCI             0x00000004 /* 1:PCI controller & Clear        */
 270 #define Int_IntMacRx           0x00000002 /* 1:Rx controller & Clear         */
 271 #define Int_IntMacTx           0x00000001 /* 1:Tx controller & Clear         */
 272 
 273 /* MD_CA bit assign --------------------------------------------------------- */
 274 #define MD_CA_PreSup           0x00001000 /* 1:Preamble Suppress                     */
 275 #define MD_CA_Busy             0x00000800 /* 1:Busy (Start Operation)        */
 276 #define MD_CA_Wr               0x00000400 /* 1:Write 0:Read                  */
 277 
 278 
 279 /*
 280  * Descriptors
 281  */
 282 
 283 /* Frame descriptor */
 284 struct FDesc {
 285         volatile __u32 FDNext;
 286         volatile __u32 FDSystem;
 287         volatile __u32 FDStat;
 288         volatile __u32 FDCtl;
 289 };
 290 
 291 /* Buffer descriptor */
 292 struct BDesc {
 293         volatile __u32 BuffData;
 294         volatile __u32 BDCtl;
 295 };
 296 
 297 #define FD_ALIGN        16
 298 
 299 /* Frame Descriptor bit assign ---------------------------------------------- */
 300 #define FD_FDLength_MASK       0x0000FFFF /* Length MASK                     */
 301 #define FD_BDCnt_MASK          0x001F0000 /* BD count MASK in FD             */
 302 #define FD_FrmOpt_MASK         0x7C000000 /* Frame option MASK               */
 303 #define FD_FrmOpt_BigEndian    0x40000000 /* Tx/Rx */
 304 #define FD_FrmOpt_IntTx        0x20000000 /* Tx only */
 305 #define FD_FrmOpt_NoCRC        0x10000000 /* Tx only */
 306 #define FD_FrmOpt_NoPadding    0x08000000 /* Tx only */
 307 #define FD_FrmOpt_Packing      0x04000000 /* Rx only */
 308 #define FD_CownsFD             0x80000000 /* FD Controller owner bit         */
 309 #define FD_Next_EOL            0x00000001 /* FD EOL indicator                */
 310 #define FD_BDCnt_SHIFT         16
 311 
 312 /* Buffer Descriptor bit assign --------------------------------------------- */
 313 #define BD_BuffLength_MASK     0x0000FFFF /* Receive Data Size               */
 314 #define BD_RxBDID_MASK         0x00FF0000 /* BD ID Number MASK               */
 315 #define BD_RxBDSeqN_MASK       0x7F000000 /* Rx BD Sequence Number           */
 316 #define BD_CownsBD             0x80000000 /* BD Controller owner bit         */
 317 #define BD_RxBDID_SHIFT        16
 318 #define BD_RxBDSeqN_SHIFT      24
 319 
 320 
 321 /* Some useful constants. */
 322 
 323 #define TX_CTL_CMD      (Tx_EnTxPar | Tx_EnLateColl | \
 324         Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
 325         Tx_En)  /* maybe  0x7b01 */
 326 /* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
 327 #define RX_CTL_CMD      (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
 328         | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
 329 #define INT_EN_CMD  (Int_NRAbtEn | \
 330         Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
 331         Int_SSysErrEn  | Int_RMasAbtEn | Int_RTargAbtEn | \
 332         Int_STargAbtEn | \
 333         Int_BLExEn  | Int_FDAExEn) /* maybe 0xb7f*/
 334 #define DMA_CTL_CMD     DMA_BURST_SIZE
 335 #define HAVE_DMA_RXALIGN(lp)    likely((lp)->chiptype != TC35815CF)
 336 
 337 /* Tuning parameters */
 338 #define DMA_BURST_SIZE  32
 339 #define TX_THRESHOLD    1024
 340 /* used threshold with packet max byte for low pci transfer ability.*/
 341 #define TX_THRESHOLD_MAX 1536
 342 /* setting threshold max value when overrun error occurred this count. */
 343 #define TX_THRESHOLD_KEEP_LIMIT 10
 344 
 345 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
 346 #define FD_PAGE_NUM 4
 347 #define RX_BUF_NUM      128     /* < 256 */
 348 #define RX_FD_NUM       256     /* >= 32 */
 349 #define TX_FD_NUM       128
 350 #if RX_CTL_CMD & Rx_LongEn
 351 #define RX_BUF_SIZE     PAGE_SIZE
 352 #elif RX_CTL_CMD & Rx_StripCRC
 353 #define RX_BUF_SIZE     \
 354         L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
 355 #else
 356 #define RX_BUF_SIZE     \
 357         L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
 358 #endif
 359 #define RX_FD_RESERVE   (2 / 2) /* max 2 BD per RxFD */
 360 #define NAPI_WEIGHT     16
 361 
 362 struct TxFD {
 363         struct FDesc fd;
 364         struct BDesc bd;
 365         struct BDesc unused;
 366 };
 367 
 368 struct RxFD {
 369         struct FDesc fd;
 370         struct BDesc bd[0];     /* variable length */
 371 };
 372 
 373 struct FrFD {
 374         struct FDesc fd;
 375         struct BDesc bd[RX_BUF_NUM];
 376 };
 377 
 378 
 379 #define tc_readl(addr)  ioread32(addr)
 380 #define tc_writel(d, addr)      iowrite32(d, addr)
 381 
 382 #define TC35815_TX_TIMEOUT  msecs_to_jiffies(400)
 383 
 384 /* Information that need to be kept for each controller. */
 385 struct tc35815_local {
 386         struct pci_dev *pci_dev;
 387 
 388         struct net_device *dev;
 389         struct napi_struct napi;
 390 
 391         /* statistics */
 392         struct {
 393                 int max_tx_qlen;
 394                 int tx_ints;
 395                 int rx_ints;
 396                 int tx_underrun;
 397         } lstats;
 398 
 399         /* Tx control lock.  This protects the transmit buffer ring
 400          * state along with the "tx full" state of the driver.  This
 401          * means all netif_queue flow control actions are protected
 402          * by this lock as well.
 403          */
 404         spinlock_t lock;
 405         spinlock_t rx_lock;
 406 
 407         struct mii_bus *mii_bus;
 408         int duplex;
 409         int speed;
 410         int link;
 411         struct work_struct restart_work;
 412 
 413         /*
 414          * Transmitting: Batch Mode.
 415          *      1 BD in 1 TxFD.
 416          * Receiving: Non-Packing Mode.
 417          *      1 circular FD for Free Buffer List.
 418          *      RX_BUF_NUM BD in Free Buffer FD.
 419          *      One Free Buffer BD has ETH_FRAME_LEN data buffer.
 420          */
 421         void *fd_buf;   /* for TxFD, RxFD, FrFD */
 422         dma_addr_t fd_buf_dma;
 423         struct TxFD *tfd_base;
 424         unsigned int tfd_start;
 425         unsigned int tfd_end;
 426         struct RxFD *rfd_base;
 427         struct RxFD *rfd_limit;
 428         struct RxFD *rfd_cur;
 429         struct FrFD *fbl_ptr;
 430         unsigned int fbl_count;
 431         struct {
 432                 struct sk_buff *skb;
 433                 dma_addr_t skb_dma;
 434         } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
 435         u32 msg_enable;
 436         enum tc35815_chiptype chiptype;
 437 };
 438 
 439 static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
 440 {
 441         return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
 442 }
 443 #ifdef DEBUG
 444 static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
 445 {
 446         return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
 447 }
 448 #endif
 449 static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
 450                                        struct pci_dev *hwdev,
 451                                        dma_addr_t *dma_handle)
 452 {
 453         struct sk_buff *skb;
 454         skb = netdev_alloc_skb(dev, RX_BUF_SIZE);
 455         if (!skb)
 456                 return NULL;
 457         *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
 458                                      PCI_DMA_FROMDEVICE);
 459         if (pci_dma_mapping_error(hwdev, *dma_handle)) {
 460                 dev_kfree_skb_any(skb);
 461                 return NULL;
 462         }
 463         skb_reserve(skb, 2);    /* make IP header 4byte aligned */
 464         return skb;
 465 }
 466 
 467 static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
 468 {
 469         pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
 470                          PCI_DMA_FROMDEVICE);
 471         dev_kfree_skb_any(skb);
 472 }
 473 
 474 /* Index to functions, as function prototypes. */
 475 
 476 static int      tc35815_open(struct net_device *dev);
 477 static netdev_tx_t      tc35815_send_packet(struct sk_buff *skb,
 478                                             struct net_device *dev);
 479 static irqreturn_t      tc35815_interrupt(int irq, void *dev_id);
 480 static int      tc35815_rx(struct net_device *dev, int limit);
 481 static int      tc35815_poll(struct napi_struct *napi, int budget);
 482 static void     tc35815_txdone(struct net_device *dev);
 483 static int      tc35815_close(struct net_device *dev);
 484 static struct   net_device_stats *tc35815_get_stats(struct net_device *dev);
 485 static void     tc35815_set_multicast_list(struct net_device *dev);
 486 static void     tc35815_tx_timeout(struct net_device *dev);
 487 static int      tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 488 #ifdef CONFIG_NET_POLL_CONTROLLER
 489 static void     tc35815_poll_controller(struct net_device *dev);
 490 #endif
 491 static const struct ethtool_ops tc35815_ethtool_ops;
 492 
 493 /* Example routines you must write ;->. */
 494 static void     tc35815_chip_reset(struct net_device *dev);
 495 static void     tc35815_chip_init(struct net_device *dev);
 496 
 497 #ifdef DEBUG
 498 static void     panic_queues(struct net_device *dev);
 499 #endif
 500 
 501 static void tc35815_restart_work(struct work_struct *work);
 502 
 503 static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 504 {
 505         struct net_device *dev = bus->priv;
 506         struct tc35815_regs __iomem *tr =
 507                 (struct tc35815_regs __iomem *)dev->base_addr;
 508         unsigned long timeout = jiffies + HZ;
 509 
 510         tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
 511         udelay(12); /* it takes 32 x 400ns at least */
 512         while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
 513                 if (time_after(jiffies, timeout))
 514                         return -EIO;
 515                 cpu_relax();
 516         }
 517         return tc_readl(&tr->MD_Data) & 0xffff;
 518 }
 519 
 520 static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
 521 {
 522         struct net_device *dev = bus->priv;
 523         struct tc35815_regs __iomem *tr =
 524                 (struct tc35815_regs __iomem *)dev->base_addr;
 525         unsigned long timeout = jiffies + HZ;
 526 
 527         tc_writel(val, &tr->MD_Data);
 528         tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
 529                   &tr->MD_CA);
 530         udelay(12); /* it takes 32 x 400ns at least */
 531         while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
 532                 if (time_after(jiffies, timeout))
 533                         return -EIO;
 534                 cpu_relax();
 535         }
 536         return 0;
 537 }
 538 
 539 static void tc_handle_link_change(struct net_device *dev)
 540 {
 541         struct tc35815_local *lp = netdev_priv(dev);
 542         struct phy_device *phydev = dev->phydev;
 543         unsigned long flags;
 544         int status_change = 0;
 545 
 546         spin_lock_irqsave(&lp->lock, flags);
 547         if (phydev->link &&
 548             (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
 549                 struct tc35815_regs __iomem *tr =
 550                         (struct tc35815_regs __iomem *)dev->base_addr;
 551                 u32 reg;
 552 
 553                 reg = tc_readl(&tr->MAC_Ctl);
 554                 reg |= MAC_HaltReq;
 555                 tc_writel(reg, &tr->MAC_Ctl);
 556                 if (phydev->duplex == DUPLEX_FULL)
 557                         reg |= MAC_FullDup;
 558                 else
 559                         reg &= ~MAC_FullDup;
 560                 tc_writel(reg, &tr->MAC_Ctl);
 561                 reg &= ~MAC_HaltReq;
 562                 tc_writel(reg, &tr->MAC_Ctl);
 563 
 564                 /*
 565                  * TX4939 PCFG.SPEEDn bit will be changed on
 566                  * NETDEV_CHANGE event.
 567                  */
 568                 /*
 569                  * WORKAROUND: enable LostCrS only if half duplex
 570                  * operation.
 571                  * (TX4939 does not have EnLCarr)
 572                  */
 573                 if (phydev->duplex == DUPLEX_HALF &&
 574                     lp->chiptype != TC35815_TX4939)
 575                         tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
 576                                   &tr->Tx_Ctl);
 577 
 578                 lp->speed = phydev->speed;
 579                 lp->duplex = phydev->duplex;
 580                 status_change = 1;
 581         }
 582 
 583         if (phydev->link != lp->link) {
 584                 if (phydev->link) {
 585                         /* delayed promiscuous enabling */
 586                         if (dev->flags & IFF_PROMISC)
 587                                 tc35815_set_multicast_list(dev);
 588                 } else {
 589                         lp->speed = 0;
 590                         lp->duplex = -1;
 591                 }
 592                 lp->link = phydev->link;
 593 
 594                 status_change = 1;
 595         }
 596         spin_unlock_irqrestore(&lp->lock, flags);
 597 
 598         if (status_change && netif_msg_link(lp)) {
 599                 phy_print_status(phydev);
 600                 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
 601                          dev->name,
 602                          phy_read(phydev, MII_BMCR),
 603                          phy_read(phydev, MII_BMSR),
 604                          phy_read(phydev, MII_LPA));
 605         }
 606 }
 607 
 608 static int tc_mii_probe(struct net_device *dev)
 609 {
 610         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 611         struct tc35815_local *lp = netdev_priv(dev);
 612         struct phy_device *phydev;
 613 
 614         phydev = phy_find_first(lp->mii_bus);
 615         if (!phydev) {
 616                 printk(KERN_ERR "%s: no PHY found\n", dev->name);
 617                 return -ENODEV;
 618         }
 619 
 620         /* attach the mac to the phy */
 621         phydev = phy_connect(dev, phydev_name(phydev),
 622                              &tc_handle_link_change,
 623                              lp->chiptype == TC35815_TX4939 ? PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
 624         if (IS_ERR(phydev)) {
 625                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 626                 return PTR_ERR(phydev);
 627         }
 628 
 629         phy_attached_info(phydev);
 630 
 631         /* mask with MAC supported features */
 632         phy_set_max_speed(phydev, SPEED_100);
 633         if (options.speed == 10) {
 634                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
 635                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
 636         } else if (options.speed == 100) {
 637                 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mask);
 638                 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mask);
 639         }
 640         if (options.duplex == 1) {
 641                 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mask);
 642                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
 643         } else if (options.duplex == 2) {
 644                 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mask);
 645                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
 646         }
 647         linkmode_andnot(phydev->supported, phydev->supported, mask);
 648         linkmode_copy(phydev->advertising, phydev->supported);
 649 
 650         lp->link = 0;
 651         lp->speed = 0;
 652         lp->duplex = -1;
 653 
 654         return 0;
 655 }
 656 
 657 static int tc_mii_init(struct net_device *dev)
 658 {
 659         struct tc35815_local *lp = netdev_priv(dev);
 660         int err;
 661 
 662         lp->mii_bus = mdiobus_alloc();
 663         if (lp->mii_bus == NULL) {
 664                 err = -ENOMEM;
 665                 goto err_out;
 666         }
 667 
 668         lp->mii_bus->name = "tc35815_mii_bus";
 669         lp->mii_bus->read = tc_mdio_read;
 670         lp->mii_bus->write = tc_mdio_write;
 671         snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
 672                  (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
 673         lp->mii_bus->priv = dev;
 674         lp->mii_bus->parent = &lp->pci_dev->dev;
 675         err = mdiobus_register(lp->mii_bus);
 676         if (err)
 677                 goto err_out_free_mii_bus;
 678         err = tc_mii_probe(dev);
 679         if (err)
 680                 goto err_out_unregister_bus;
 681         return 0;
 682 
 683 err_out_unregister_bus:
 684         mdiobus_unregister(lp->mii_bus);
 685 err_out_free_mii_bus:
 686         mdiobus_free(lp->mii_bus);
 687 err_out:
 688         return err;
 689 }
 690 
 691 #ifdef CONFIG_CPU_TX49XX
 692 /*
 693  * Find a platform_device providing a MAC address.  The platform code
 694  * should provide a "tc35815-mac" device with a MAC address in its
 695  * platform_data.
 696  */
 697 static int tc35815_mac_match(struct device *dev, const void *data)
 698 {
 699         struct platform_device *plat_dev = to_platform_device(dev);
 700         const struct pci_dev *pci_dev = data;
 701         unsigned int id = pci_dev->irq;
 702         return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
 703 }
 704 
 705 static int tc35815_read_plat_dev_addr(struct net_device *dev)
 706 {
 707         struct tc35815_local *lp = netdev_priv(dev);
 708         struct device *pd = bus_find_device(&platform_bus_type, NULL,
 709                                             lp->pci_dev, tc35815_mac_match);
 710         if (pd) {
 711                 if (pd->platform_data)
 712                         memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
 713                 put_device(pd);
 714                 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
 715         }
 716         return -ENODEV;
 717 }
 718 #else
 719 static int tc35815_read_plat_dev_addr(struct net_device *dev)
 720 {
 721         return -ENODEV;
 722 }
 723 #endif
 724 
 725 static int tc35815_init_dev_addr(struct net_device *dev)
 726 {
 727         struct tc35815_regs __iomem *tr =
 728                 (struct tc35815_regs __iomem *)dev->base_addr;
 729         int i;
 730 
 731         while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
 732                 ;
 733         for (i = 0; i < 6; i += 2) {
 734                 unsigned short data;
 735                 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
 736                 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
 737                         ;
 738                 data = tc_readl(&tr->PROM_Data);
 739                 dev->dev_addr[i] = data & 0xff;
 740                 dev->dev_addr[i+1] = data >> 8;
 741         }
 742         if (!is_valid_ether_addr(dev->dev_addr))
 743                 return tc35815_read_plat_dev_addr(dev);
 744         return 0;
 745 }
 746 
 747 static const struct net_device_ops tc35815_netdev_ops = {
 748         .ndo_open               = tc35815_open,
 749         .ndo_stop               = tc35815_close,
 750         .ndo_start_xmit         = tc35815_send_packet,
 751         .ndo_get_stats          = tc35815_get_stats,
 752         .ndo_set_rx_mode        = tc35815_set_multicast_list,
 753         .ndo_tx_timeout         = tc35815_tx_timeout,
 754         .ndo_do_ioctl           = tc35815_ioctl,
 755         .ndo_validate_addr      = eth_validate_addr,
 756         .ndo_set_mac_address    = eth_mac_addr,
 757 #ifdef CONFIG_NET_POLL_CONTROLLER
 758         .ndo_poll_controller    = tc35815_poll_controller,
 759 #endif
 760 };
 761 
 762 static int tc35815_init_one(struct pci_dev *pdev,
 763                             const struct pci_device_id *ent)
 764 {
 765         void __iomem *ioaddr = NULL;
 766         struct net_device *dev;
 767         struct tc35815_local *lp;
 768         int rc;
 769 
 770         static int printed_version;
 771         if (!printed_version++) {
 772                 printk(version);
 773                 dev_printk(KERN_DEBUG, &pdev->dev,
 774                            "speed:%d duplex:%d\n",
 775                            options.speed, options.duplex);
 776         }
 777 
 778         if (!pdev->irq) {
 779                 dev_warn(&pdev->dev, "no IRQ assigned.\n");
 780                 return -ENODEV;
 781         }
 782 
 783         /* dev zeroed in alloc_etherdev */
 784         dev = alloc_etherdev(sizeof(*lp));
 785         if (dev == NULL)
 786                 return -ENOMEM;
 787 
 788         SET_NETDEV_DEV(dev, &pdev->dev);
 789         lp = netdev_priv(dev);
 790         lp->dev = dev;
 791 
 792         /* enable device (incl. PCI PM wakeup), and bus-mastering */
 793         rc = pcim_enable_device(pdev);
 794         if (rc)
 795                 goto err_out;
 796         rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
 797         if (rc)
 798                 goto err_out;
 799         pci_set_master(pdev);
 800         ioaddr = pcim_iomap_table(pdev)[1];
 801 
 802         /* Initialize the device structure. */
 803         dev->netdev_ops = &tc35815_netdev_ops;
 804         dev->ethtool_ops = &tc35815_ethtool_ops;
 805         dev->watchdog_timeo = TC35815_TX_TIMEOUT;
 806         netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
 807 
 808         dev->irq = pdev->irq;
 809         dev->base_addr = (unsigned long)ioaddr;
 810 
 811         INIT_WORK(&lp->restart_work, tc35815_restart_work);
 812         spin_lock_init(&lp->lock);
 813         spin_lock_init(&lp->rx_lock);
 814         lp->pci_dev = pdev;
 815         lp->chiptype = ent->driver_data;
 816 
 817         lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
 818         pci_set_drvdata(pdev, dev);
 819 
 820         /* Soft reset the chip. */
 821         tc35815_chip_reset(dev);
 822 
 823         /* Retrieve the ethernet address. */
 824         if (tc35815_init_dev_addr(dev)) {
 825                 dev_warn(&pdev->dev, "not valid ether addr\n");
 826                 eth_hw_addr_random(dev);
 827         }
 828 
 829         rc = register_netdev(dev);
 830         if (rc)
 831                 goto err_out;
 832 
 833         printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
 834                 dev->name,
 835                 chip_info[ent->driver_data].name,
 836                 dev->base_addr,
 837                 dev->dev_addr,
 838                 dev->irq);
 839 
 840         rc = tc_mii_init(dev);
 841         if (rc)
 842                 goto err_out_unregister;
 843 
 844         return 0;
 845 
 846 err_out_unregister:
 847         unregister_netdev(dev);
 848 err_out:
 849         free_netdev(dev);
 850         return rc;
 851 }
 852 
 853 
 854 static void tc35815_remove_one(struct pci_dev *pdev)
 855 {
 856         struct net_device *dev = pci_get_drvdata(pdev);
 857         struct tc35815_local *lp = netdev_priv(dev);
 858 
 859         phy_disconnect(dev->phydev);
 860         mdiobus_unregister(lp->mii_bus);
 861         mdiobus_free(lp->mii_bus);
 862         unregister_netdev(dev);
 863         free_netdev(dev);
 864 }
 865 
 866 static int
 867 tc35815_init_queues(struct net_device *dev)
 868 {
 869         struct tc35815_local *lp = netdev_priv(dev);
 870         int i;
 871         unsigned long fd_addr;
 872 
 873         if (!lp->fd_buf) {
 874                 BUG_ON(sizeof(struct FDesc) +
 875                        sizeof(struct BDesc) * RX_BUF_NUM +
 876                        sizeof(struct FDesc) * RX_FD_NUM +
 877                        sizeof(struct TxFD) * TX_FD_NUM >
 878                        PAGE_SIZE * FD_PAGE_NUM);
 879 
 880                 lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
 881                                                   PAGE_SIZE * FD_PAGE_NUM,
 882                                                   &lp->fd_buf_dma);
 883                 if (!lp->fd_buf)
 884                         return -ENOMEM;
 885                 for (i = 0; i < RX_BUF_NUM; i++) {
 886                         lp->rx_skbs[i].skb =
 887                                 alloc_rxbuf_skb(dev, lp->pci_dev,
 888                                                 &lp->rx_skbs[i].skb_dma);
 889                         if (!lp->rx_skbs[i].skb) {
 890                                 while (--i >= 0) {
 891                                         free_rxbuf_skb(lp->pci_dev,
 892                                                        lp->rx_skbs[i].skb,
 893                                                        lp->rx_skbs[i].skb_dma);
 894                                         lp->rx_skbs[i].skb = NULL;
 895                                 }
 896                                 pci_free_consistent(lp->pci_dev,
 897                                                     PAGE_SIZE * FD_PAGE_NUM,
 898                                                     lp->fd_buf,
 899                                                     lp->fd_buf_dma);
 900                                 lp->fd_buf = NULL;
 901                                 return -ENOMEM;
 902                         }
 903                 }
 904                 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
 905                        dev->name, lp->fd_buf);
 906                 printk("\n");
 907         } else {
 908                 for (i = 0; i < FD_PAGE_NUM; i++)
 909                         clear_page((void *)((unsigned long)lp->fd_buf +
 910                                             i * PAGE_SIZE));
 911         }
 912         fd_addr = (unsigned long)lp->fd_buf;
 913 
 914         /* Free Descriptors (for Receive) */
 915         lp->rfd_base = (struct RxFD *)fd_addr;
 916         fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
 917         for (i = 0; i < RX_FD_NUM; i++)
 918                 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
 919         lp->rfd_cur = lp->rfd_base;
 920         lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
 921 
 922         /* Transmit Descriptors */
 923         lp->tfd_base = (struct TxFD *)fd_addr;
 924         fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
 925         for (i = 0; i < TX_FD_NUM; i++) {
 926                 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
 927                 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
 928                 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
 929         }
 930         lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
 931         lp->tfd_start = 0;
 932         lp->tfd_end = 0;
 933 
 934         /* Buffer List (for Receive) */
 935         lp->fbl_ptr = (struct FrFD *)fd_addr;
 936         lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
 937         lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
 938         /*
 939          * move all allocated skbs to head of rx_skbs[] array.
 940          * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
 941          * tc35815_rx() had failed.
 942          */
 943         lp->fbl_count = 0;
 944         for (i = 0; i < RX_BUF_NUM; i++) {
 945                 if (lp->rx_skbs[i].skb) {
 946                         if (i != lp->fbl_count) {
 947                                 lp->rx_skbs[lp->fbl_count].skb =
 948                                         lp->rx_skbs[i].skb;
 949                                 lp->rx_skbs[lp->fbl_count].skb_dma =
 950                                         lp->rx_skbs[i].skb_dma;
 951                         }
 952                         lp->fbl_count++;
 953                 }
 954         }
 955         for (i = 0; i < RX_BUF_NUM; i++) {
 956                 if (i >= lp->fbl_count) {
 957                         lp->fbl_ptr->bd[i].BuffData = 0;
 958                         lp->fbl_ptr->bd[i].BDCtl = 0;
 959                         continue;
 960                 }
 961                 lp->fbl_ptr->bd[i].BuffData =
 962                         cpu_to_le32(lp->rx_skbs[i].skb_dma);
 963                 /* BDID is index of FrFD.bd[] */
 964                 lp->fbl_ptr->bd[i].BDCtl =
 965                         cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
 966                                     RX_BUF_SIZE);
 967         }
 968 
 969         printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
 970                dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
 971         return 0;
 972 }
 973 
 974 static void
 975 tc35815_clear_queues(struct net_device *dev)
 976 {
 977         struct tc35815_local *lp = netdev_priv(dev);
 978         int i;
 979 
 980         for (i = 0; i < TX_FD_NUM; i++) {
 981                 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
 982                 struct sk_buff *skb =
 983                         fdsystem != 0xffffffff ?
 984                         lp->tx_skbs[fdsystem].skb : NULL;
 985 #ifdef DEBUG
 986                 if (lp->tx_skbs[i].skb != skb) {
 987                         printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
 988                         panic_queues(dev);
 989                 }
 990 #else
 991                 BUG_ON(lp->tx_skbs[i].skb != skb);
 992 #endif
 993                 if (skb) {
 994                         pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
 995                         lp->tx_skbs[i].skb = NULL;
 996                         lp->tx_skbs[i].skb_dma = 0;
 997                         dev_kfree_skb_any(skb);
 998                 }
 999                 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1000         }
1001 
1002         tc35815_init_queues(dev);
1003 }
1004 
1005 static void
1006 tc35815_free_queues(struct net_device *dev)
1007 {
1008         struct tc35815_local *lp = netdev_priv(dev);
1009         int i;
1010 
1011         if (lp->tfd_base) {
1012                 for (i = 0; i < TX_FD_NUM; i++) {
1013                         u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1014                         struct sk_buff *skb =
1015                                 fdsystem != 0xffffffff ?
1016                                 lp->tx_skbs[fdsystem].skb : NULL;
1017 #ifdef DEBUG
1018                         if (lp->tx_skbs[i].skb != skb) {
1019                                 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1020                                 panic_queues(dev);
1021                         }
1022 #else
1023                         BUG_ON(lp->tx_skbs[i].skb != skb);
1024 #endif
1025                         if (skb) {
1026                                 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1027                                 dev_kfree_skb(skb);
1028                                 lp->tx_skbs[i].skb = NULL;
1029                                 lp->tx_skbs[i].skb_dma = 0;
1030                         }
1031                         lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1032                 }
1033         }
1034 
1035         lp->rfd_base = NULL;
1036         lp->rfd_limit = NULL;
1037         lp->rfd_cur = NULL;
1038         lp->fbl_ptr = NULL;
1039 
1040         for (i = 0; i < RX_BUF_NUM; i++) {
1041                 if (lp->rx_skbs[i].skb) {
1042                         free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1043                                        lp->rx_skbs[i].skb_dma);
1044                         lp->rx_skbs[i].skb = NULL;
1045                 }
1046         }
1047         if (lp->fd_buf) {
1048                 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1049                                     lp->fd_buf, lp->fd_buf_dma);
1050                 lp->fd_buf = NULL;
1051         }
1052 }
1053 
1054 static void
1055 dump_txfd(struct TxFD *fd)
1056 {
1057         printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1058                le32_to_cpu(fd->fd.FDNext),
1059                le32_to_cpu(fd->fd.FDSystem),
1060                le32_to_cpu(fd->fd.FDStat),
1061                le32_to_cpu(fd->fd.FDCtl));
1062         printk("BD: ");
1063         printk(" %08x %08x",
1064                le32_to_cpu(fd->bd.BuffData),
1065                le32_to_cpu(fd->bd.BDCtl));
1066         printk("\n");
1067 }
1068 
1069 static int
1070 dump_rxfd(struct RxFD *fd)
1071 {
1072         int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1073         if (bd_count > 8)
1074                 bd_count = 8;
1075         printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1076                le32_to_cpu(fd->fd.FDNext),
1077                le32_to_cpu(fd->fd.FDSystem),
1078                le32_to_cpu(fd->fd.FDStat),
1079                le32_to_cpu(fd->fd.FDCtl));
1080         if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1081                 return 0;
1082         printk("BD: ");
1083         for (i = 0; i < bd_count; i++)
1084                 printk(" %08x %08x",
1085                        le32_to_cpu(fd->bd[i].BuffData),
1086                        le32_to_cpu(fd->bd[i].BDCtl));
1087         printk("\n");
1088         return bd_count;
1089 }
1090 
1091 #ifdef DEBUG
1092 static void
1093 dump_frfd(struct FrFD *fd)
1094 {
1095         int i;
1096         printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1097                le32_to_cpu(fd->fd.FDNext),
1098                le32_to_cpu(fd->fd.FDSystem),
1099                le32_to_cpu(fd->fd.FDStat),
1100                le32_to_cpu(fd->fd.FDCtl));
1101         printk("BD: ");
1102         for (i = 0; i < RX_BUF_NUM; i++)
1103                 printk(" %08x %08x",
1104                        le32_to_cpu(fd->bd[i].BuffData),
1105                        le32_to_cpu(fd->bd[i].BDCtl));
1106         printk("\n");
1107 }
1108 
1109 static void
1110 panic_queues(struct net_device *dev)
1111 {
1112         struct tc35815_local *lp = netdev_priv(dev);
1113         int i;
1114 
1115         printk("TxFD base %p, start %u, end %u\n",
1116                lp->tfd_base, lp->tfd_start, lp->tfd_end);
1117         printk("RxFD base %p limit %p cur %p\n",
1118                lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1119         printk("FrFD %p\n", lp->fbl_ptr);
1120         for (i = 0; i < TX_FD_NUM; i++)
1121                 dump_txfd(&lp->tfd_base[i]);
1122         for (i = 0; i < RX_FD_NUM; i++) {
1123                 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1124                 i += (bd_count + 1) / 2;        /* skip BDs */
1125         }
1126         dump_frfd(lp->fbl_ptr);
1127         panic("%s: Illegal queue state.", dev->name);
1128 }
1129 #endif
1130 
1131 static void print_eth(const u8 *add)
1132 {
1133         printk(KERN_DEBUG "print_eth(%p)\n", add);
1134         printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1135                 add + 6, add, add[12], add[13]);
1136 }
1137 
1138 static int tc35815_tx_full(struct net_device *dev)
1139 {
1140         struct tc35815_local *lp = netdev_priv(dev);
1141         return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end;
1142 }
1143 
1144 static void tc35815_restart(struct net_device *dev)
1145 {
1146         struct tc35815_local *lp = netdev_priv(dev);
1147         int ret;
1148 
1149         if (dev->phydev) {
1150                 ret = phy_init_hw(dev->phydev);
1151                 if (ret)
1152                         printk(KERN_ERR "%s: PHY init failed.\n", dev->name);
1153         }
1154 
1155         spin_lock_bh(&lp->rx_lock);
1156         spin_lock_irq(&lp->lock);
1157         tc35815_chip_reset(dev);
1158         tc35815_clear_queues(dev);
1159         tc35815_chip_init(dev);
1160         /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1161         tc35815_set_multicast_list(dev);
1162         spin_unlock_irq(&lp->lock);
1163         spin_unlock_bh(&lp->rx_lock);
1164 
1165         netif_wake_queue(dev);
1166 }
1167 
1168 static void tc35815_restart_work(struct work_struct *work)
1169 {
1170         struct tc35815_local *lp =
1171                 container_of(work, struct tc35815_local, restart_work);
1172         struct net_device *dev = lp->dev;
1173 
1174         tc35815_restart(dev);
1175 }
1176 
1177 static void tc35815_schedule_restart(struct net_device *dev)
1178 {
1179         struct tc35815_local *lp = netdev_priv(dev);
1180         struct tc35815_regs __iomem *tr =
1181                 (struct tc35815_regs __iomem *)dev->base_addr;
1182         unsigned long flags;
1183 
1184         /* disable interrupts */
1185         spin_lock_irqsave(&lp->lock, flags);
1186         tc_writel(0, &tr->Int_En);
1187         tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1188         schedule_work(&lp->restart_work);
1189         spin_unlock_irqrestore(&lp->lock, flags);
1190 }
1191 
1192 static void tc35815_tx_timeout(struct net_device *dev)
1193 {
1194         struct tc35815_regs __iomem *tr =
1195                 (struct tc35815_regs __iomem *)dev->base_addr;
1196 
1197         printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1198                dev->name, tc_readl(&tr->Tx_Stat));
1199 
1200         /* Try to restart the adaptor. */
1201         tc35815_schedule_restart(dev);
1202         dev->stats.tx_errors++;
1203 }
1204 
1205 /*
1206  * Open/initialize the controller. This is called (in the current kernel)
1207  * sometime after booting when the 'ifconfig' program is run.
1208  *
1209  * This routine should set everything up anew at each open, even
1210  * registers that "should" only need to be set once at boot, so that
1211  * there is non-reboot way to recover if something goes wrong.
1212  */
1213 static int
1214 tc35815_open(struct net_device *dev)
1215 {
1216         struct tc35815_local *lp = netdev_priv(dev);
1217 
1218         /*
1219          * This is used if the interrupt line can turned off (shared).
1220          * See 3c503.c for an example of selecting the IRQ at config-time.
1221          */
1222         if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
1223                         dev->name, dev))
1224                 return -EAGAIN;
1225 
1226         tc35815_chip_reset(dev);
1227 
1228         if (tc35815_init_queues(dev) != 0) {
1229                 free_irq(dev->irq, dev);
1230                 return -EAGAIN;
1231         }
1232 
1233         napi_enable(&lp->napi);
1234 
1235         /* Reset the hardware here. Don't forget to set the station address. */
1236         spin_lock_irq(&lp->lock);
1237         tc35815_chip_init(dev);
1238         spin_unlock_irq(&lp->lock);
1239 
1240         netif_carrier_off(dev);
1241         /* schedule a link state check */
1242         phy_start(dev->phydev);
1243 
1244         /* We are now ready to accept transmit requeusts from
1245          * the queueing layer of the networking.
1246          */
1247         netif_start_queue(dev);
1248 
1249         return 0;
1250 }
1251 
1252 /* This will only be invoked if your driver is _not_ in XOFF state.
1253  * What this means is that you need not check it, and that this
1254  * invariant will hold if you make sure that the netif_*_queue()
1255  * calls are done at the proper times.
1256  */
1257 static netdev_tx_t
1258 tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1259 {
1260         struct tc35815_local *lp = netdev_priv(dev);
1261         struct TxFD *txfd;
1262         unsigned long flags;
1263 
1264         /* If some error occurs while trying to transmit this
1265          * packet, you should return '1' from this function.
1266          * In such a case you _may not_ do anything to the
1267          * SKB, it is still owned by the network queueing
1268          * layer when an error is returned.  This means you
1269          * may not modify any SKB fields, you may not free
1270          * the SKB, etc.
1271          */
1272 
1273         /* This is the most common case for modern hardware.
1274          * The spinlock protects this code from the TX complete
1275          * hardware interrupt handler.  Queue flow control is
1276          * thus managed under this lock as well.
1277          */
1278         spin_lock_irqsave(&lp->lock, flags);
1279 
1280         /* failsafe... (handle txdone now if half of FDs are used) */
1281         if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1282             TX_FD_NUM / 2)
1283                 tc35815_txdone(dev);
1284 
1285         if (netif_msg_pktdata(lp))
1286                 print_eth(skb->data);
1287 #ifdef DEBUG
1288         if (lp->tx_skbs[lp->tfd_start].skb) {
1289                 printk("%s: tx_skbs conflict.\n", dev->name);
1290                 panic_queues(dev);
1291         }
1292 #else
1293         BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1294 #endif
1295         lp->tx_skbs[lp->tfd_start].skb = skb;
1296         lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1297 
1298         /*add to ring */
1299         txfd = &lp->tfd_base[lp->tfd_start];
1300         txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1301         txfd->bd.BDCtl = cpu_to_le32(skb->len);
1302         txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1303         txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1304 
1305         if (lp->tfd_start == lp->tfd_end) {
1306                 struct tc35815_regs __iomem *tr =
1307                         (struct tc35815_regs __iomem *)dev->base_addr;
1308                 /* Start DMA Transmitter. */
1309                 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1310                 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1311                 if (netif_msg_tx_queued(lp)) {
1312                         printk("%s: starting TxFD.\n", dev->name);
1313                         dump_txfd(txfd);
1314                 }
1315                 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1316         } else {
1317                 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1318                 if (netif_msg_tx_queued(lp)) {
1319                         printk("%s: queueing TxFD.\n", dev->name);
1320                         dump_txfd(txfd);
1321                 }
1322         }
1323         lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1324 
1325         /* If we just used up the very last entry in the
1326          * TX ring on this device, tell the queueing
1327          * layer to send no more.
1328          */
1329         if (tc35815_tx_full(dev)) {
1330                 if (netif_msg_tx_queued(lp))
1331                         printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1332                 netif_stop_queue(dev);
1333         }
1334 
1335         /* When the TX completion hw interrupt arrives, this
1336          * is when the transmit statistics are updated.
1337          */
1338 
1339         spin_unlock_irqrestore(&lp->lock, flags);
1340         return NETDEV_TX_OK;
1341 }
1342 
1343 #define FATAL_ERROR_INT \
1344         (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1345 static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1346 {
1347         static int count;
1348         printk(KERN_WARNING "%s: Fatal Error Interrupt (%#x):",
1349                dev->name, status);
1350         if (status & Int_IntPCI)
1351                 printk(" IntPCI");
1352         if (status & Int_DmParErr)
1353                 printk(" DmParErr");
1354         if (status & Int_IntNRAbt)
1355                 printk(" IntNRAbt");
1356         printk("\n");
1357         if (count++ > 100)
1358                 panic("%s: Too many fatal errors.", dev->name);
1359         printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1360         /* Try to restart the adaptor. */
1361         tc35815_schedule_restart(dev);
1362 }
1363 
1364 static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1365 {
1366         struct tc35815_local *lp = netdev_priv(dev);
1367         int ret = -1;
1368 
1369         /* Fatal errors... */
1370         if (status & FATAL_ERROR_INT) {
1371                 tc35815_fatal_error_interrupt(dev, status);
1372                 return 0;
1373         }
1374         /* recoverable errors */
1375         if (status & Int_IntFDAEx) {
1376                 if (netif_msg_rx_err(lp))
1377                         dev_warn(&dev->dev,
1378                                  "Free Descriptor Area Exhausted (%#x).\n",
1379                                  status);
1380                 dev->stats.rx_dropped++;
1381                 ret = 0;
1382         }
1383         if (status & Int_IntBLEx) {
1384                 if (netif_msg_rx_err(lp))
1385                         dev_warn(&dev->dev,
1386                                  "Buffer List Exhausted (%#x).\n",
1387                                  status);
1388                 dev->stats.rx_dropped++;
1389                 ret = 0;
1390         }
1391         if (status & Int_IntExBD) {
1392                 if (netif_msg_rx_err(lp))
1393                         dev_warn(&dev->dev,
1394                                  "Excessive Buffer Descriptors (%#x).\n",
1395                                  status);
1396                 dev->stats.rx_length_errors++;
1397                 ret = 0;
1398         }
1399 
1400         /* normal notification */
1401         if (status & Int_IntMacRx) {
1402                 /* Got a packet(s). */
1403                 ret = tc35815_rx(dev, limit);
1404                 lp->lstats.rx_ints++;
1405         }
1406         if (status & Int_IntMacTx) {
1407                 /* Transmit complete. */
1408                 lp->lstats.tx_ints++;
1409                 spin_lock_irq(&lp->lock);
1410                 tc35815_txdone(dev);
1411                 spin_unlock_irq(&lp->lock);
1412                 if (ret < 0)
1413                         ret = 0;
1414         }
1415         return ret;
1416 }
1417 
1418 /*
1419  * The typical workload of the driver:
1420  * Handle the network interface interrupts.
1421  */
1422 static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1423 {
1424         struct net_device *dev = dev_id;
1425         struct tc35815_local *lp = netdev_priv(dev);
1426         struct tc35815_regs __iomem *tr =
1427                 (struct tc35815_regs __iomem *)dev->base_addr;
1428         u32 dmactl = tc_readl(&tr->DMA_Ctl);
1429 
1430         if (!(dmactl & DMA_IntMask)) {
1431                 /* disable interrupts */
1432                 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1433                 if (napi_schedule_prep(&lp->napi))
1434                         __napi_schedule(&lp->napi);
1435                 else {
1436                         printk(KERN_ERR "%s: interrupt taken in poll\n",
1437                                dev->name);
1438                         BUG();
1439                 }
1440                 (void)tc_readl(&tr->Int_Src);   /* flush */
1441                 return IRQ_HANDLED;
1442         }
1443         return IRQ_NONE;
1444 }
1445 
1446 #ifdef CONFIG_NET_POLL_CONTROLLER
1447 static void tc35815_poll_controller(struct net_device *dev)
1448 {
1449         disable_irq(dev->irq);
1450         tc35815_interrupt(dev->irq, dev);
1451         enable_irq(dev->irq);
1452 }
1453 #endif
1454 
1455 /* We have a good packet(s), get it/them out of the buffers. */
1456 static int
1457 tc35815_rx(struct net_device *dev, int limit)
1458 {
1459         struct tc35815_local *lp = netdev_priv(dev);
1460         unsigned int fdctl;
1461         int i;
1462         int received = 0;
1463 
1464         while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1465                 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1466                 int pkt_len = fdctl & FD_FDLength_MASK;
1467                 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1468 #ifdef DEBUG
1469                 struct RxFD *next_rfd;
1470 #endif
1471 #if (RX_CTL_CMD & Rx_StripCRC) == 0
1472                 pkt_len -= ETH_FCS_LEN;
1473 #endif
1474 
1475                 if (netif_msg_rx_status(lp))
1476                         dump_rxfd(lp->rfd_cur);
1477                 if (status & Rx_Good) {
1478                         struct sk_buff *skb;
1479                         unsigned char *data;
1480                         int cur_bd;
1481 
1482                         if (--limit < 0)
1483                                 break;
1484                         BUG_ON(bd_count > 1);
1485                         cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1486                                   & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1487 #ifdef DEBUG
1488                         if (cur_bd >= RX_BUF_NUM) {
1489                                 printk("%s: invalid BDID.\n", dev->name);
1490                                 panic_queues(dev);
1491                         }
1492                         BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1493                                (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1494                         if (!lp->rx_skbs[cur_bd].skb) {
1495                                 printk("%s: NULL skb.\n", dev->name);
1496                                 panic_queues(dev);
1497                         }
1498 #else
1499                         BUG_ON(cur_bd >= RX_BUF_NUM);
1500 #endif
1501                         skb = lp->rx_skbs[cur_bd].skb;
1502                         prefetch(skb->data);
1503                         lp->rx_skbs[cur_bd].skb = NULL;
1504                         pci_unmap_single(lp->pci_dev,
1505                                          lp->rx_skbs[cur_bd].skb_dma,
1506                                          RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1507                         if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN != 0)
1508                                 memmove(skb->data, skb->data - NET_IP_ALIGN,
1509                                         pkt_len);
1510                         data = skb_put(skb, pkt_len);
1511                         if (netif_msg_pktdata(lp))
1512                                 print_eth(data);
1513                         skb->protocol = eth_type_trans(skb, dev);
1514                         netif_receive_skb(skb);
1515                         received++;
1516                         dev->stats.rx_packets++;
1517                         dev->stats.rx_bytes += pkt_len;
1518                 } else {
1519                         dev->stats.rx_errors++;
1520                         if (netif_msg_rx_err(lp))
1521                                 dev_info(&dev->dev, "Rx error (status %x)\n",
1522                                          status & Rx_Stat_Mask);
1523                         /* WORKAROUND: LongErr and CRCErr means Overflow. */
1524                         if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1525                                 status &= ~(Rx_LongErr|Rx_CRCErr);
1526                                 status |= Rx_Over;
1527                         }
1528                         if (status & Rx_LongErr)
1529                                 dev->stats.rx_length_errors++;
1530                         if (status & Rx_Over)
1531                                 dev->stats.rx_fifo_errors++;
1532                         if (status & Rx_CRCErr)
1533                                 dev->stats.rx_crc_errors++;
1534                         if (status & Rx_Align)
1535                                 dev->stats.rx_frame_errors++;
1536                 }
1537 
1538                 if (bd_count > 0) {
1539                         /* put Free Buffer back to controller */
1540                         int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1541                         unsigned char id =
1542                                 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1543 #ifdef DEBUG
1544                         if (id >= RX_BUF_NUM) {
1545                                 printk("%s: invalid BDID.\n", dev->name);
1546                                 panic_queues(dev);
1547                         }
1548 #else
1549                         BUG_ON(id >= RX_BUF_NUM);
1550 #endif
1551                         /* free old buffers */
1552                         lp->fbl_count--;
1553                         while (lp->fbl_count < RX_BUF_NUM)
1554                         {
1555                                 unsigned char curid =
1556                                         (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1557                                 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1558 #ifdef DEBUG
1559                                 bdctl = le32_to_cpu(bd->BDCtl);
1560                                 if (bdctl & BD_CownsBD) {
1561                                         printk("%s: Freeing invalid BD.\n",
1562                                                dev->name);
1563                                         panic_queues(dev);
1564                                 }
1565 #endif
1566                                 /* pass BD to controller */
1567                                 if (!lp->rx_skbs[curid].skb) {
1568                                         lp->rx_skbs[curid].skb =
1569                                                 alloc_rxbuf_skb(dev,
1570                                                                 lp->pci_dev,
1571                                                                 &lp->rx_skbs[curid].skb_dma);
1572                                         if (!lp->rx_skbs[curid].skb)
1573                                                 break; /* try on next reception */
1574                                         bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1575                                 }
1576                                 /* Note: BDLength was modified by chip. */
1577                                 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1578                                                         (curid << BD_RxBDID_SHIFT) |
1579                                                         RX_BUF_SIZE);
1580                                 lp->fbl_count++;
1581                         }
1582                 }
1583 
1584                 /* put RxFD back to controller */
1585 #ifdef DEBUG
1586                 next_rfd = fd_bus_to_virt(lp,
1587                                           le32_to_cpu(lp->rfd_cur->fd.FDNext));
1588                 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1589                         printk("%s: RxFD FDNext invalid.\n", dev->name);
1590                         panic_queues(dev);
1591                 }
1592 #endif
1593                 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1594                         /* pass FD to controller */
1595 #ifdef DEBUG
1596                         lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1597 #else
1598                         lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1599 #endif
1600                         lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1601                         lp->rfd_cur++;
1602                 }
1603                 if (lp->rfd_cur > lp->rfd_limit)
1604                         lp->rfd_cur = lp->rfd_base;
1605 #ifdef DEBUG
1606                 if (lp->rfd_cur != next_rfd)
1607                         printk("rfd_cur = %p, next_rfd %p\n",
1608                                lp->rfd_cur, next_rfd);
1609 #endif
1610         }
1611 
1612         return received;
1613 }
1614 
1615 static int tc35815_poll(struct napi_struct *napi, int budget)
1616 {
1617         struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1618         struct net_device *dev = lp->dev;
1619         struct tc35815_regs __iomem *tr =
1620                 (struct tc35815_regs __iomem *)dev->base_addr;
1621         int received = 0, handled;
1622         u32 status;
1623 
1624         if (budget <= 0)
1625                 return received;
1626 
1627         spin_lock(&lp->rx_lock);
1628         status = tc_readl(&tr->Int_Src);
1629         do {
1630                 /* BLEx, FDAEx will be cleared later */
1631                 tc_writel(status & ~(Int_BLEx | Int_FDAEx),
1632                           &tr->Int_Src);        /* write to clear */
1633 
1634                 handled = tc35815_do_interrupt(dev, status, budget - received);
1635                 if (status & (Int_BLEx | Int_FDAEx))
1636                         tc_writel(status & (Int_BLEx | Int_FDAEx),
1637                                   &tr->Int_Src);
1638                 if (handled >= 0) {
1639                         received += handled;
1640                         if (received >= budget)
1641                                 break;
1642                 }
1643                 status = tc_readl(&tr->Int_Src);
1644         } while (status);
1645         spin_unlock(&lp->rx_lock);
1646 
1647         if (received < budget) {
1648                 napi_complete_done(napi, received);
1649                 /* enable interrupts */
1650                 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1651         }
1652         return received;
1653 }
1654 
1655 #define TX_STA_ERR      (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1656 
1657 static void
1658 tc35815_check_tx_stat(struct net_device *dev, int status)
1659 {
1660         struct tc35815_local *lp = netdev_priv(dev);
1661         const char *msg = NULL;
1662 
1663         /* count collisions */
1664         if (status & Tx_ExColl)
1665                 dev->stats.collisions += 16;
1666         if (status & Tx_TxColl_MASK)
1667                 dev->stats.collisions += status & Tx_TxColl_MASK;
1668 
1669         /* TX4939 does not have NCarr */
1670         if (lp->chiptype == TC35815_TX4939)
1671                 status &= ~Tx_NCarr;
1672         /* WORKAROUND: ignore LostCrS in full duplex operation */
1673         if (!lp->link || lp->duplex == DUPLEX_FULL)
1674                 status &= ~Tx_NCarr;
1675 
1676         if (!(status & TX_STA_ERR)) {
1677                 /* no error. */
1678                 dev->stats.tx_packets++;
1679                 return;
1680         }
1681 
1682         dev->stats.tx_errors++;
1683         if (status & Tx_ExColl) {
1684                 dev->stats.tx_aborted_errors++;
1685                 msg = "Excessive Collision.";
1686         }
1687         if (status & Tx_Under) {
1688                 dev->stats.tx_fifo_errors++;
1689                 msg = "Tx FIFO Underrun.";
1690                 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1691                         lp->lstats.tx_underrun++;
1692                         if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1693                                 struct tc35815_regs __iomem *tr =
1694                                         (struct tc35815_regs __iomem *)dev->base_addr;
1695                                 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1696                                 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1697                         }
1698                 }
1699         }
1700         if (status & Tx_Defer) {
1701                 dev->stats.tx_fifo_errors++;
1702                 msg = "Excessive Deferral.";
1703         }
1704         if (status & Tx_NCarr) {
1705                 dev->stats.tx_carrier_errors++;
1706                 msg = "Lost Carrier Sense.";
1707         }
1708         if (status & Tx_LateColl) {
1709                 dev->stats.tx_aborted_errors++;
1710                 msg = "Late Collision.";
1711         }
1712         if (status & Tx_TxPar) {
1713                 dev->stats.tx_fifo_errors++;
1714                 msg = "Transmit Parity Error.";
1715         }
1716         if (status & Tx_SQErr) {
1717                 dev->stats.tx_heartbeat_errors++;
1718                 msg = "Signal Quality Error.";
1719         }
1720         if (msg && netif_msg_tx_err(lp))
1721                 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1722 }
1723 
1724 /* This handles TX complete events posted by the device
1725  * via interrupts.
1726  */
1727 static void
1728 tc35815_txdone(struct net_device *dev)
1729 {
1730         struct tc35815_local *lp = netdev_priv(dev);
1731         struct TxFD *txfd;
1732         unsigned int fdctl;
1733 
1734         txfd = &lp->tfd_base[lp->tfd_end];
1735         while (lp->tfd_start != lp->tfd_end &&
1736                !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1737                 int status = le32_to_cpu(txfd->fd.FDStat);
1738                 struct sk_buff *skb;
1739                 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
1740                 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
1741 
1742                 if (netif_msg_tx_done(lp)) {
1743                         printk("%s: complete TxFD.\n", dev->name);
1744                         dump_txfd(txfd);
1745                 }
1746                 tc35815_check_tx_stat(dev, status);
1747 
1748                 skb = fdsystem != 0xffffffff ?
1749                         lp->tx_skbs[fdsystem].skb : NULL;
1750 #ifdef DEBUG
1751                 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
1752                         printk("%s: tx_skbs mismatch.\n", dev->name);
1753                         panic_queues(dev);
1754                 }
1755 #else
1756                 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
1757 #endif
1758                 if (skb) {
1759                         dev->stats.tx_bytes += skb->len;
1760                         pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
1761                         lp->tx_skbs[lp->tfd_end].skb = NULL;
1762                         lp->tx_skbs[lp->tfd_end].skb_dma = 0;
1763                         dev_kfree_skb_any(skb);
1764                 }
1765                 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
1766 
1767                 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1768                 txfd = &lp->tfd_base[lp->tfd_end];
1769 #ifdef DEBUG
1770                 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
1771                         printk("%s: TxFD FDNext invalid.\n", dev->name);
1772                         panic_queues(dev);
1773                 }
1774 #endif
1775                 if (fdnext & FD_Next_EOL) {
1776                         /* DMA Transmitter has been stopping... */
1777                         if (lp->tfd_end != lp->tfd_start) {
1778                                 struct tc35815_regs __iomem *tr =
1779                                         (struct tc35815_regs __iomem *)dev->base_addr;
1780                                 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
1781                                 struct TxFD *txhead = &lp->tfd_base[head];
1782                                 int qlen = (lp->tfd_start + TX_FD_NUM
1783                                             - lp->tfd_end) % TX_FD_NUM;
1784 
1785 #ifdef DEBUG
1786                                 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1787                                         printk("%s: TxFD FDCtl invalid.\n", dev->name);
1788                                         panic_queues(dev);
1789                                 }
1790 #endif
1791                                 /* log max queue length */
1792                                 if (lp->lstats.max_tx_qlen < qlen)
1793                                         lp->lstats.max_tx_qlen = qlen;
1794 
1795 
1796                                 /* start DMA Transmitter again */
1797                                 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1798                                 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1799                                 if (netif_msg_tx_queued(lp)) {
1800                                         printk("%s: start TxFD on queue.\n",
1801                                                dev->name);
1802                                         dump_txfd(txfd);
1803                                 }
1804                                 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1805                         }
1806                         break;
1807                 }
1808         }
1809 
1810         /* If we had stopped the queue due to a "tx full"
1811          * condition, and space has now been made available,
1812          * wake up the queue.
1813          */
1814         if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
1815                 netif_wake_queue(dev);
1816 }
1817 
1818 /* The inverse routine to tc35815_open(). */
1819 static int
1820 tc35815_close(struct net_device *dev)
1821 {
1822         struct tc35815_local *lp = netdev_priv(dev);
1823 
1824         netif_stop_queue(dev);
1825         napi_disable(&lp->napi);
1826         if (dev->phydev)
1827                 phy_stop(dev->phydev);
1828         cancel_work_sync(&lp->restart_work);
1829 
1830         /* Flush the Tx and disable Rx here. */
1831         tc35815_chip_reset(dev);
1832         free_irq(dev->irq, dev);
1833 
1834         tc35815_free_queues(dev);
1835 
1836         return 0;
1837 
1838 }
1839 
1840 /*
1841  * Get the current statistics.
1842  * This may be called with the card open or closed.
1843  */
1844 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1845 {
1846         struct tc35815_regs __iomem *tr =
1847                 (struct tc35815_regs __iomem *)dev->base_addr;
1848         if (netif_running(dev))
1849                 /* Update the statistics from the device registers. */
1850                 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1851 
1852         return &dev->stats;
1853 }
1854 
1855 static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
1856 {
1857         struct tc35815_local *lp = netdev_priv(dev);
1858         struct tc35815_regs __iomem *tr =
1859                 (struct tc35815_regs __iomem *)dev->base_addr;
1860         int cam_index = index * 6;
1861         u32 cam_data;
1862         u32 saved_addr;
1863 
1864         saved_addr = tc_readl(&tr->CAM_Adr);
1865 
1866         if (netif_msg_hw(lp))
1867                 printk(KERN_DEBUG "%s: CAM %d: %pM\n",
1868                         dev->name, index, addr);
1869         if (index & 1) {
1870                 /* read modify write */
1871                 tc_writel(cam_index - 2, &tr->CAM_Adr);
1872                 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1873                 cam_data |= addr[0] << 8 | addr[1];
1874                 tc_writel(cam_data, &tr->CAM_Data);
1875                 /* write whole word */
1876                 tc_writel(cam_index + 2, &tr->CAM_Adr);
1877                 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1878                 tc_writel(cam_data, &tr->CAM_Data);
1879         } else {
1880                 /* write whole word */
1881                 tc_writel(cam_index, &tr->CAM_Adr);
1882                 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1883                 tc_writel(cam_data, &tr->CAM_Data);
1884                 /* read modify write */
1885                 tc_writel(cam_index + 4, &tr->CAM_Adr);
1886                 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1887                 cam_data |= addr[4] << 24 | (addr[5] << 16);
1888                 tc_writel(cam_data, &tr->CAM_Data);
1889         }
1890 
1891         tc_writel(saved_addr, &tr->CAM_Adr);
1892 }
1893 
1894 
1895 /*
1896  * Set or clear the multicast filter for this adaptor.
1897  * num_addrs == -1      Promiscuous mode, receive all packets
1898  * num_addrs == 0       Normal mode, clear multicast list
1899  * num_addrs > 0        Multicast mode, receive normal and MC packets,
1900  *                      and do best-effort filtering.
1901  */
1902 static void
1903 tc35815_set_multicast_list(struct net_device *dev)
1904 {
1905         struct tc35815_regs __iomem *tr =
1906                 (struct tc35815_regs __iomem *)dev->base_addr;
1907 
1908         if (dev->flags & IFF_PROMISC) {
1909                 /* With some (all?) 100MHalf HUB, controller will hang
1910                  * if we enabled promiscuous mode before linkup... */
1911                 struct tc35815_local *lp = netdev_priv(dev);
1912 
1913                 if (!lp->link)
1914                         return;
1915                 /* Enable promiscuous mode */
1916                 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1917         } else if ((dev->flags & IFF_ALLMULTI) ||
1918                   netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) {
1919                 /* CAM 0, 1, 20 are reserved. */
1920                 /* Disable promiscuous mode, use normal mode. */
1921                 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1922         } else if (!netdev_mc_empty(dev)) {
1923                 struct netdev_hw_addr *ha;
1924                 int i;
1925                 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1926 
1927                 tc_writel(0, &tr->CAM_Ctl);
1928                 /* Walk the address list, and load the filter */
1929                 i = 0;
1930                 netdev_for_each_mc_addr(ha, dev) {
1931                         /* entry 0,1 is reserved. */
1932                         tc35815_set_cam_entry(dev, i + 2, ha->addr);
1933                         ena_bits |= CAM_Ena_Bit(i + 2);
1934                         i++;
1935                 }
1936                 tc_writel(ena_bits, &tr->CAM_Ena);
1937                 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1938         } else {
1939                 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1940                 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1941         }
1942 }
1943 
1944 static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1945 {
1946         struct tc35815_local *lp = netdev_priv(dev);
1947 
1948         strlcpy(info->driver, MODNAME, sizeof(info->driver));
1949         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1950         strlcpy(info->bus_info, pci_name(lp->pci_dev), sizeof(info->bus_info));
1951 }
1952 
1953 static u32 tc35815_get_msglevel(struct net_device *dev)
1954 {
1955         struct tc35815_local *lp = netdev_priv(dev);
1956         return lp->msg_enable;
1957 }
1958 
1959 static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
1960 {
1961         struct tc35815_local *lp = netdev_priv(dev);
1962         lp->msg_enable = datum;
1963 }
1964 
1965 static int tc35815_get_sset_count(struct net_device *dev, int sset)
1966 {
1967         struct tc35815_local *lp = netdev_priv(dev);
1968 
1969         switch (sset) {
1970         case ETH_SS_STATS:
1971                 return sizeof(lp->lstats) / sizeof(int);
1972         default:
1973                 return -EOPNOTSUPP;
1974         }
1975 }
1976 
1977 static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
1978 {
1979         struct tc35815_local *lp = netdev_priv(dev);
1980         data[0] = lp->lstats.max_tx_qlen;
1981         data[1] = lp->lstats.tx_ints;
1982         data[2] = lp->lstats.rx_ints;
1983         data[3] = lp->lstats.tx_underrun;
1984 }
1985 
1986 static struct {
1987         const char str[ETH_GSTRING_LEN];
1988 } ethtool_stats_keys[] = {
1989         { "max_tx_qlen" },
1990         { "tx_ints" },
1991         { "rx_ints" },
1992         { "tx_underrun" },
1993 };
1994 
1995 static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1996 {
1997         memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
1998 }
1999 
2000 static const struct ethtool_ops tc35815_ethtool_ops = {
2001         .get_drvinfo            = tc35815_get_drvinfo,
2002         .get_link               = ethtool_op_get_link,
2003         .get_msglevel           = tc35815_get_msglevel,
2004         .set_msglevel           = tc35815_set_msglevel,
2005         .get_strings            = tc35815_get_strings,
2006         .get_sset_count         = tc35815_get_sset_count,
2007         .get_ethtool_stats      = tc35815_get_ethtool_stats,
2008         .get_link_ksettings = phy_ethtool_get_link_ksettings,
2009         .set_link_ksettings = phy_ethtool_set_link_ksettings,
2010 };
2011 
2012 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2013 {
2014         if (!netif_running(dev))
2015                 return -EINVAL;
2016         if (!dev->phydev)
2017                 return -ENODEV;
2018         return phy_mii_ioctl(dev->phydev, rq, cmd);
2019 }
2020 
2021 static void tc35815_chip_reset(struct net_device *dev)
2022 {
2023         struct tc35815_regs __iomem *tr =
2024                 (struct tc35815_regs __iomem *)dev->base_addr;
2025         int i;
2026         /* reset the controller */
2027         tc_writel(MAC_Reset, &tr->MAC_Ctl);
2028         udelay(4); /* 3200ns */
2029         i = 0;
2030         while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2031                 if (i++ > 100) {
2032                         printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2033                         break;
2034                 }
2035                 mdelay(1);
2036         }
2037         tc_writel(0, &tr->MAC_Ctl);
2038 
2039         /* initialize registers to default value */
2040         tc_writel(0, &tr->DMA_Ctl);
2041         tc_writel(0, &tr->TxThrsh);
2042         tc_writel(0, &tr->TxPollCtr);
2043         tc_writel(0, &tr->RxFragSize);
2044         tc_writel(0, &tr->Int_En);
2045         tc_writel(0, &tr->FDA_Bas);
2046         tc_writel(0, &tr->FDA_Lim);
2047         tc_writel(0xffffffff, &tr->Int_Src);    /* Write 1 to clear */
2048         tc_writel(0, &tr->CAM_Ctl);
2049         tc_writel(0, &tr->Tx_Ctl);
2050         tc_writel(0, &tr->Rx_Ctl);
2051         tc_writel(0, &tr->CAM_Ena);
2052         (void)tc_readl(&tr->Miss_Cnt);  /* Read to clear */
2053 
2054         /* initialize internal SRAM */
2055         tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2056         for (i = 0; i < 0x1000; i += 4) {
2057                 tc_writel(i, &tr->CAM_Adr);
2058                 tc_writel(0, &tr->CAM_Data);
2059         }
2060         tc_writel(0, &tr->DMA_Ctl);
2061 }
2062 
2063 static void tc35815_chip_init(struct net_device *dev)
2064 {
2065         struct tc35815_local *lp = netdev_priv(dev);
2066         struct tc35815_regs __iomem *tr =
2067                 (struct tc35815_regs __iomem *)dev->base_addr;
2068         unsigned long txctl = TX_CTL_CMD;
2069 
2070         /* load station address to CAM */
2071         tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2072 
2073         /* Enable CAM (broadcast and unicast) */
2074         tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2075         tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2076 
2077         /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2078         if (HAVE_DMA_RXALIGN(lp))
2079                 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2080         else
2081                 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2082         tc_writel(0, &tr->TxPollCtr);   /* Batch mode */
2083         tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2084         tc_writel(INT_EN_CMD, &tr->Int_En);
2085 
2086         /* set queues */
2087         tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2088         tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2089                   &tr->FDA_Lim);
2090         /*
2091          * Activation method:
2092          * First, enable the MAC Transmitter and the DMA Receive circuits.
2093          * Then enable the DMA Transmitter and the MAC Receive circuits.
2094          */
2095         tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr);      /* start DMA receiver */
2096         tc_writel(RX_CTL_CMD, &tr->Rx_Ctl);     /* start MAC receiver */
2097 
2098         /* start MAC transmitter */
2099         /* TX4939 does not have EnLCarr */
2100         if (lp->chiptype == TC35815_TX4939)
2101                 txctl &= ~Tx_EnLCarr;
2102         /* WORKAROUND: ignore LostCrS in full duplex operation */
2103         if (!dev->phydev || !lp->link || lp->duplex == DUPLEX_FULL)
2104                 txctl &= ~Tx_EnLCarr;
2105         tc_writel(txctl, &tr->Tx_Ctl);
2106 }
2107 
2108 #ifdef CONFIG_PM
2109 static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2110 {
2111         struct net_device *dev = pci_get_drvdata(pdev);
2112         struct tc35815_local *lp = netdev_priv(dev);
2113         unsigned long flags;
2114 
2115         pci_save_state(pdev);
2116         if (!netif_running(dev))
2117                 return 0;
2118         netif_device_detach(dev);
2119         if (dev->phydev)
2120                 phy_stop(dev->phydev);
2121         spin_lock_irqsave(&lp->lock, flags);
2122         tc35815_chip_reset(dev);
2123         spin_unlock_irqrestore(&lp->lock, flags);
2124         pci_set_power_state(pdev, PCI_D3hot);
2125         return 0;
2126 }
2127 
2128 static int tc35815_resume(struct pci_dev *pdev)
2129 {
2130         struct net_device *dev = pci_get_drvdata(pdev);
2131 
2132         pci_restore_state(pdev);
2133         if (!netif_running(dev))
2134                 return 0;
2135         pci_set_power_state(pdev, PCI_D0);
2136         tc35815_restart(dev);
2137         netif_carrier_off(dev);
2138         if (dev->phydev)
2139                 phy_start(dev->phydev);
2140         netif_device_attach(dev);
2141         return 0;
2142 }
2143 #endif /* CONFIG_PM */
2144 
2145 static struct pci_driver tc35815_pci_driver = {
2146         .name           = MODNAME,
2147         .id_table       = tc35815_pci_tbl,
2148         .probe          = tc35815_init_one,
2149         .remove         = tc35815_remove_one,
2150 #ifdef CONFIG_PM
2151         .suspend        = tc35815_suspend,
2152         .resume         = tc35815_resume,
2153 #endif
2154 };
2155 
2156 module_param_named(speed, options.speed, int, 0);
2157 MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2158 module_param_named(duplex, options.duplex, int, 0);
2159 MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2160 
2161 module_pci_driver(tc35815_pci_driver);
2162 MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2163 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/toshiba/tc35815.c

DEFINITIONS
