root/drivers/net/ethernet/mellanox/mlx4/en_cq.c

DEFINITIONS

1. mlx4_en_cq_event
2. mlx4_en_create_cq
3. mlx4_en_activate_cq
4. mlx4_en_destroy_cq
5. mlx4_en_deactivate_cq
6. mlx4_en_set_cq_moder
7. mlx4_en_arm_cq

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33 
  34 #include <linux/mlx4/cq.h>
  35 #include <linux/mlx4/qp.h>
  36 #include <linux/mlx4/cmd.h>
  37 
  38 #include "mlx4_en.h"
  39 
  40 static void mlx4_en_cq_event(struct mlx4_cq *cq, enum mlx4_event event)
  41 {
  42         return;
  43 }
  44 
  45 
  46 int mlx4_en_create_cq(struct mlx4_en_priv *priv,
  47                       struct mlx4_en_cq **pcq,
  48                       int entries, int ring, enum cq_type mode,
  49                       int node)
  50 {
  51         struct mlx4_en_dev *mdev = priv->mdev;
  52         struct mlx4_en_cq *cq;
  53         int err;
  54 
  55         cq = kzalloc_node(sizeof(*cq), GFP_KERNEL, node);
  56         if (!cq) {
  57                 en_err(priv, "Failed to allocate CQ structure\n");
  58                 return -ENOMEM;
  59         }
  60 
  61         cq->size = entries;
  62         cq->buf_size = cq->size * mdev->dev->caps.cqe_size;
  63 
  64         cq->ring = ring;
  65         cq->type = mode;
  66         cq->vector = mdev->dev->caps.num_comp_vectors;
  67 
  68         /* Allocate HW buffers on provided NUMA node.
  69          * dev->numa_node is used in mtt range allocation flow.
  70          */
  71         set_dev_node(&mdev->dev->persist->pdev->dev, node);
  72         err = mlx4_alloc_hwq_res(mdev->dev, &cq->wqres,
  73                                 cq->buf_size);
  74         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
  75         if (err)
  76                 goto err_cq;
  77 
  78         cq->buf = (struct mlx4_cqe *)cq->wqres.buf.direct.buf;
  79         *pcq = cq;
  80 
  81         return 0;
  82 
  83 err_cq:
  84         kfree(cq);
  85         *pcq = NULL;
  86         return err;
  87 }
  88 
  89 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
  90                         int cq_idx)
  91 {
  92         struct mlx4_en_dev *mdev = priv->mdev;
  93         int err = 0;
  94         int timestamp_en = 0;
  95         bool assigned_eq = false;
  96 
  97         cq->dev = mdev->pndev[priv->port];
  98         cq->mcq.set_ci_db  = cq->wqres.db.db;
  99         cq->mcq.arm_db     = cq->wqres.db.db + 1;
 100         *cq->mcq.set_ci_db = 0;
 101         *cq->mcq.arm_db    = 0;
 102         memset(cq->buf, 0, cq->buf_size);
 103 
 104         if (cq->type == RX) {
 105                 if (!mlx4_is_eq_vector_valid(mdev->dev, priv->port,
 106                                              cq->vector)) {
 107                         cq->vector = cpumask_first(priv->rx_ring[cq->ring]->affinity_mask);
 108 
 109                         err = mlx4_assign_eq(mdev->dev, priv->port,
 110                                              &cq->vector);
 111                         if (err) {
 112                                 mlx4_err(mdev, "Failed assigning an EQ to CQ vector %d\n",
 113                                          cq->vector);
 114                                 goto free_eq;
 115                         }
 116 
 117                         assigned_eq = true;
 118                 }
 119 
 120                 cq->irq_desc =
 121                         irq_to_desc(mlx4_eq_get_irq(mdev->dev,
 122                                                     cq->vector));
 123         } else {
 124                 /* For TX we use the same irq per
 125                 ring we assigned for the RX    */
 126                 struct mlx4_en_cq *rx_cq;
 127 
 128                 cq_idx = cq_idx % priv->rx_ring_num;
 129                 rx_cq = priv->rx_cq[cq_idx];
 130                 cq->vector = rx_cq->vector;
 131         }
 132 
 133         if (cq->type == RX)
 134                 cq->size = priv->rx_ring[cq->ring]->actual_size;
 135 
 136         if ((cq->type != RX && priv->hwtstamp_config.tx_type) ||
 137             (cq->type == RX && priv->hwtstamp_config.rx_filter))
 138                 timestamp_en = 1;
 139 
 140         cq->mcq.usage = MLX4_RES_USAGE_DRIVER;
 141         err = mlx4_cq_alloc(mdev->dev, cq->size, &cq->wqres.mtt,
 142                             &mdev->priv_uar, cq->wqres.db.dma, &cq->mcq,
 143                             cq->vector, 0, timestamp_en, &cq->wqres.buf, false);
 144         if (err)
 145                 goto free_eq;
 146 
 147         cq->mcq.event = mlx4_en_cq_event;
 148 
 149         switch (cq->type) {
 150         case TX:
 151                 cq->mcq.comp = mlx4_en_tx_irq;
 152                 netif_tx_napi_add(cq->dev, &cq->napi, mlx4_en_poll_tx_cq,
 153                                   NAPI_POLL_WEIGHT);
 154                 napi_enable(&cq->napi);
 155                 break;
 156         case RX:
 157                 cq->mcq.comp = mlx4_en_rx_irq;
 158                 netif_napi_add(cq->dev, &cq->napi, mlx4_en_poll_rx_cq, 64);
 159                 napi_enable(&cq->napi);
 160                 break;
 161         case TX_XDP:
 162                 /* nothing regarding napi, it's shared with rx ring */
 163                 cq->xdp_busy = false;
 164                 break;
 165         }
 166 
 167         return 0;
 168 
 169 free_eq:
 170         if (assigned_eq)
 171                 mlx4_release_eq(mdev->dev, cq->vector);
 172         cq->vector = mdev->dev->caps.num_comp_vectors;
 173         return err;
 174 }
 175 
 176 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq)
 177 {
 178         struct mlx4_en_dev *mdev = priv->mdev;
 179         struct mlx4_en_cq *cq = *pcq;
 180 
 181         mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size);
 182         if (mlx4_is_eq_vector_valid(mdev->dev, priv->port, cq->vector) &&
 183             cq->type == RX)
 184                 mlx4_release_eq(priv->mdev->dev, cq->vector);
 185         cq->vector = 0;
 186         cq->buf_size = 0;
 187         cq->buf = NULL;
 188         kfree(cq);
 189         *pcq = NULL;
 190 }
 191 
 192 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
 193 {
 194         if (cq->type != TX_XDP) {
 195                 napi_disable(&cq->napi);
 196                 netif_napi_del(&cq->napi);
 197         }
 198 
 199         mlx4_cq_free(priv->mdev->dev, &cq->mcq);
 200 }
 201 
 202 /* Set rx cq moderation parameters */
 203 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
 204 {
 205         return mlx4_cq_modify(priv->mdev->dev, &cq->mcq,
 206                               cq->moder_cnt, cq->moder_time);
 207 }
 208 
 209 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
 210 {
 211         mlx4_cq_arm(&cq->mcq, MLX4_CQ_DB_REQ_NOT, priv->mdev->uar_map,
 212                     &priv->mdev->uar_lock);
 213 }
 214 
 215