root/drivers/net/ethernet/mellanox/mlx5/core/en_main.c

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DEFINITIONS

This source file includes following definitions.
  1. mlx5e_check_fragmented_striding_rq_cap
  2. mlx5e_init_rq_type_params
  3. mlx5e_striding_rq_possible
  4. mlx5e_set_rq_type
  5. mlx5e_update_carrier
  6. mlx5e_update_carrier_work
  7. mlx5e_update_stats
  8. mlx5e_update_ndo_stats
  9. mlx5e_update_stats_work
  10. mlx5e_queue_update_stats
  11. async_event
  12. mlx5e_enable_async_events
  13. mlx5e_disable_async_events
  14. mlx5e_build_umr_wqe
  15. mlx5e_rq_alloc_mpwqe_info
  16. mlx5e_create_umr_mkey
  17. mlx5e_create_rq_umr_mkey
  18. mlx5e_get_mpwqe_offset
  19. mlx5e_init_frags_partition
  20. mlx5e_init_di_list
  21. mlx5e_free_di_list
  22. mlx5e_rq_err_cqe_work
  23. mlx5e_alloc_rq
  24. mlx5e_free_rq
  25. mlx5e_create_rq
  26. mlx5e_modify_rq_state
  27. mlx5e_modify_rq_scatter_fcs
  28. mlx5e_modify_rq_vsd
  29. mlx5e_destroy_rq
  30. mlx5e_wait_for_min_rx_wqes
  31. mlx5e_free_rx_in_progress_descs
  32. mlx5e_free_rx_descs
  33. mlx5e_open_rq
  34. mlx5e_activate_rq
  35. mlx5e_deactivate_rq
  36. mlx5e_close_rq
  37. mlx5e_free_xdpsq_db
  38. mlx5e_alloc_xdpsq_fifo
  39. mlx5e_alloc_xdpsq_db
  40. mlx5e_alloc_xdpsq
  41. mlx5e_free_xdpsq
  42. mlx5e_free_icosq_db
  43. mlx5e_alloc_icosq_db
  44. mlx5e_icosq_err_cqe_work
  45. mlx5e_alloc_icosq
  46. mlx5e_free_icosq
  47. mlx5e_free_txqsq_db
  48. mlx5e_alloc_txqsq_db
  49. mlx5e_alloc_txqsq
  50. mlx5e_free_txqsq
  51. mlx5e_create_sq
  52. mlx5e_modify_sq
  53. mlx5e_destroy_sq
  54. mlx5e_create_sq_rdy
  55. mlx5e_open_txqsq
  56. mlx5e_activate_txqsq
  57. mlx5e_tx_disable_queue
  58. mlx5e_deactivate_txqsq
  59. mlx5e_close_txqsq
  60. mlx5e_tx_err_cqe_work
  61. mlx5e_open_icosq
  62. mlx5e_activate_icosq
  63. mlx5e_deactivate_icosq
  64. mlx5e_close_icosq
  65. mlx5e_open_xdpsq
  66. mlx5e_close_xdpsq
  67. mlx5e_alloc_cq_common
  68. mlx5e_alloc_cq
  69. mlx5e_free_cq
  70. mlx5e_create_cq
  71. mlx5e_destroy_cq
  72. mlx5e_open_cq
  73. mlx5e_close_cq
  74. mlx5e_open_tx_cqs
  75. mlx5e_close_tx_cqs
  76. mlx5e_open_sqs
  77. mlx5e_close_sqs
  78. mlx5e_set_sq_maxrate
  79. mlx5e_set_tx_maxrate
  80. mlx5e_alloc_xps_cpumask
  81. mlx5e_free_xps_cpumask
  82. mlx5e_open_queues
  83. mlx5e_close_queues
  84. mlx5e_enumerate_lag_port
  85. mlx5e_open_channel
  86. mlx5e_activate_channel
  87. mlx5e_deactivate_channel
  88. mlx5e_close_channel
  89. mlx5e_build_rq_frags_info
  90. mlx5e_get_rqwq_log_stride
  91. mlx5e_get_rq_log_wq_sz
  92. mlx5e_build_rq_param
  93. mlx5e_build_drop_rq_param
  94. mlx5e_build_sq_param_common
  95. mlx5e_build_sq_param
  96. mlx5e_build_common_cq_param
  97. mlx5e_build_rx_cq_param
  98. mlx5e_build_tx_cq_param
  99. mlx5e_build_ico_cq_param
  100. mlx5e_build_icosq_param
  101. mlx5e_build_xdpsq_param
  102. mlx5e_build_icosq_log_wq_sz
  103. mlx5e_build_channel_param
  104. mlx5e_open_channels
  105. mlx5e_activate_channels
  106. mlx5e_wait_channels_min_rx_wqes
  107. mlx5e_deactivate_channels
  108. mlx5e_close_channels
  109. mlx5e_create_rqt
  110. mlx5e_destroy_rqt
  111. mlx5e_create_indirect_rqt
  112. mlx5e_create_direct_rqts
  113. mlx5e_destroy_direct_rqts
  114. mlx5e_rx_hash_fn
  115. mlx5e_bits_invert
  116. mlx5e_fill_rqt_rqns
  117. mlx5e_redirect_rqt
  118. mlx5e_get_direct_rqn
  119. mlx5e_redirect_rqts
  120. mlx5e_redirect_rqts_to_channels
  121. mlx5e_redirect_rqts_to_drop
  122. mlx5e_tirc_get_default_config
  123. mlx5e_build_tir_ctx_lro
  124. mlx5e_build_indir_tir_ctx_hash
  125. mlx5e_update_rx_hash_fields
  126. mlx5e_modify_tirs_hash
  127. mlx5e_modify_tirs_lro
  128. mlx5e_set_mtu
  129. mlx5e_query_mtu
  130. mlx5e_set_dev_port_mtu
  131. mlx5e_set_netdev_mtu_boundaries
  132. mlx5e_netdev_set_tcs
  133. mlx5e_update_netdev_queues
  134. mlx5e_num_channels_changed
  135. mlx5e_build_txq_maps
  136. mlx5e_activate_priv_channels
  137. mlx5e_deactivate_priv_channels
  138. mlx5e_switch_priv_channels
  139. mlx5e_safe_switch_channels
  140. mlx5e_safe_reopen_channels
  141. mlx5e_timestamp_init
  142. mlx5e_open_locked
  143. mlx5e_open
  144. mlx5e_close_locked
  145. mlx5e_close
  146. mlx5e_alloc_drop_rq
  147. mlx5e_alloc_drop_cq
  148. mlx5e_open_drop_rq
  149. mlx5e_close_drop_rq
  150. mlx5e_create_tis
  151. mlx5e_destroy_tis
  152. mlx5e_destroy_tises
  153. mlx5e_lag_should_assign_affinity
  154. mlx5e_create_tises
  155. mlx5e_cleanup_nic_tx
  156. mlx5e_build_indir_tir_ctx_common
  157. mlx5e_build_indir_tir_ctx
  158. mlx5e_build_direct_tir_ctx
  159. mlx5e_build_inner_indir_tir_ctx
  160. mlx5e_create_indirect_tirs
  161. mlx5e_create_direct_tirs
  162. mlx5e_destroy_indirect_tirs
  163. mlx5e_destroy_direct_tirs
  164. mlx5e_modify_channels_scatter_fcs
  165. mlx5e_modify_channels_vsd
  166. mlx5e_setup_tc_mqprio
  167. mlx5e_setup_tc_cls_flower
  168. mlx5e_setup_tc_block_cb
  169. mlx5e_setup_tc
  170. mlx5e_fold_sw_stats64
  171. mlx5e_get_stats
  172. mlx5e_set_rx_mode
  173. mlx5e_set_mac
  174. set_feature_lro
  175. set_feature_cvlan_filter
  176. set_feature_tc_num_filters
  177. set_feature_rx_all
  178. set_feature_rx_fcs
  179. set_feature_rx_vlan
  180. set_feature_arfs
  181. mlx5e_handle_feature
  182. mlx5e_set_features
  183. mlx5e_fix_features
  184. mlx5e_xsk_validate_mtu
  185. mlx5e_change_mtu
  186. mlx5e_change_nic_mtu
  187. mlx5e_hwstamp_set
  188. mlx5e_hwstamp_get
  189. mlx5e_ioctl
  190. mlx5e_set_vf_mac
  191. mlx5e_set_vf_vlan
  192. mlx5e_set_vf_spoofchk
  193. mlx5e_set_vf_trust
  194. mlx5e_set_vf_rate
  195. mlx5_vport_link2ifla
  196. mlx5_ifla_link2vport
  197. mlx5e_set_vf_link_state
  198. mlx5e_get_vf_config
  199. mlx5e_get_vf_stats
  200. mlx5e_vxlan_add_work
  201. mlx5e_vxlan_del_work
  202. mlx5e_vxlan_queue_work
  203. mlx5e_add_vxlan_port
  204. mlx5e_del_vxlan_port
  205. mlx5e_tunnel_features_check
  206. mlx5e_features_check
  207. mlx5e_tx_timeout_work
  208. mlx5e_tx_timeout
  209. mlx5e_xdp_allowed
  210. mlx5e_xdp_set
  211. mlx5e_xdp_query
  212. mlx5e_xdp
  213. mlx5e_bridge_getlink
  214. mlx5e_bridge_setlink
  215. mlx5e_check_required_hca_cap
  216. mlx5e_build_default_indir_rqt
  217. slow_pci_heuristic
  218. mlx5e_get_def_tx_moderation
  219. mlx5e_get_def_rx_moderation
  220. mlx5_to_net_dim_cq_period_mode
  221. mlx5e_set_tx_cq_mode_params
  222. mlx5e_set_rx_cq_mode_params
  223. mlx5e_choose_lro_timeout
  224. mlx5e_build_rq_params
  225. mlx5e_build_rss_params
  226. mlx5e_build_nic_params
  227. mlx5e_set_netdev_dev_addr
  228. mlx5e_build_nic_netdev
  229. mlx5e_create_q_counters
  230. mlx5e_destroy_q_counters
  231. mlx5e_nic_init
  232. mlx5e_nic_cleanup
  233. mlx5e_init_nic_rx
  234. mlx5e_cleanup_nic_rx
  235. mlx5e_init_nic_tx
  236. mlx5e_nic_enable
  237. mlx5e_nic_disable
  238. mlx5e_update_nic_rx
  239. mlx5e_netdev_init
  240. mlx5e_netdev_cleanup
  241. mlx5e_create_netdev
  242. mlx5e_attach_netdev
  243. mlx5e_detach_netdev
  244. mlx5e_destroy_netdev
  245. mlx5e_attach
  246. mlx5e_detach
  247. mlx5e_add
  248. mlx5e_remove
  249. mlx5e_init
  250. mlx5e_cleanup

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/tls.h"
  51 #include "accel/ipsec.h"
  52 #include "accel/tls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/health.h"
  60 #include "en/params.h"
  61 #include "en/xsk/umem.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65 #include "en/hv_vhca_stats.h"
  66 
  67 
  68 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  69 {
  70         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  71                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  72                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  73         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  74         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  75 
  76         if (!striding_rq_umr)
  77                 return false;
  78         if (!inline_umr) {
  79                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  80                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  81                 return false;
  82         }
  83         return true;
  84 }
  85 
  86 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  87                                struct mlx5e_params *params)
  88 {
  89         params->log_rq_mtu_frames = is_kdump_kernel() ?
  90                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  91                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  92 
  93         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  94                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  95                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  96                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  97                        BIT(params->log_rq_mtu_frames),
  98                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
  99                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 100 }
 101 
 102 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 103                                 struct mlx5e_params *params)
 104 {
 105         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 106                 return false;
 107 
 108         if (MLX5_IPSEC_DEV(mdev))
 109                 return false;
 110 
 111         if (params->xdp_prog) {
 112                 /* XSK params are not considered here. If striding RQ is in use,
 113                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 114                  * be called with the known XSK params.
 115                  */
 116                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 117                         return false;
 118         }
 119 
 120         return true;
 121 }
 122 
 123 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 124 {
 125         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 126                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 127                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 128                 MLX5_WQ_TYPE_CYCLIC;
 129 }
 130 
 131 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 132 {
 133         struct mlx5_core_dev *mdev = priv->mdev;
 134         u8 port_state;
 135 
 136         port_state = mlx5_query_vport_state(mdev,
 137                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 138                                             0);
 139 
 140         if (port_state == VPORT_STATE_UP) {
 141                 netdev_info(priv->netdev, "Link up\n");
 142                 netif_carrier_on(priv->netdev);
 143         } else {
 144                 netdev_info(priv->netdev, "Link down\n");
 145                 netif_carrier_off(priv->netdev);
 146         }
 147 }
 148 
 149 static void mlx5e_update_carrier_work(struct work_struct *work)
 150 {
 151         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 152                                                update_carrier_work);
 153 
 154         mutex_lock(&priv->state_lock);
 155         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 156                 if (priv->profile->update_carrier)
 157                         priv->profile->update_carrier(priv);
 158         mutex_unlock(&priv->state_lock);
 159 }
 160 
 161 void mlx5e_update_stats(struct mlx5e_priv *priv)
 162 {
 163         int i;
 164 
 165         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 166                 if (mlx5e_stats_grps[i].update_stats)
 167                         mlx5e_stats_grps[i].update_stats(priv);
 168 }
 169 
 170 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 171 {
 172         int i;
 173 
 174         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 175                 if (mlx5e_stats_grps[i].update_stats_mask &
 176                     MLX5E_NDO_UPDATE_STATS)
 177                         mlx5e_stats_grps[i].update_stats(priv);
 178 }
 179 
 180 static void mlx5e_update_stats_work(struct work_struct *work)
 181 {
 182         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 183                                                update_stats_work);
 184 
 185         mutex_lock(&priv->state_lock);
 186         priv->profile->update_stats(priv);
 187         mutex_unlock(&priv->state_lock);
 188 }
 189 
 190 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 191 {
 192         if (!priv->profile->update_stats)
 193                 return;
 194 
 195         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 196                 return;
 197 
 198         queue_work(priv->wq, &priv->update_stats_work);
 199 }
 200 
 201 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 202 {
 203         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 204         struct mlx5_eqe   *eqe = data;
 205 
 206         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 207                 return NOTIFY_DONE;
 208 
 209         switch (eqe->sub_type) {
 210         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 211         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 212                 queue_work(priv->wq, &priv->update_carrier_work);
 213                 break;
 214         default:
 215                 return NOTIFY_DONE;
 216         }
 217 
 218         return NOTIFY_OK;
 219 }
 220 
 221 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 222 {
 223         priv->events_nb.notifier_call = async_event;
 224         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 225 }
 226 
 227 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 228 {
 229         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 230 }
 231 
 232 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 233                                        struct mlx5e_icosq *sq,
 234                                        struct mlx5e_umr_wqe *wqe)
 235 {
 236         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 237         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 238         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 239 
 240         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 241                                       ds_cnt);
 242         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 243         cseg->imm       = rq->mkey_be;
 244 
 245         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 246         ucseg->xlt_octowords =
 247                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 248         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 249 }
 250 
 251 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 252                                      struct mlx5e_channel *c)
 253 {
 254         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 255 
 256         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 257                                                   sizeof(*rq->mpwqe.info)),
 258                                        GFP_KERNEL, cpu_to_node(c->cpu));
 259         if (!rq->mpwqe.info)
 260                 return -ENOMEM;
 261 
 262         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 263 
 264         return 0;
 265 }
 266 
 267 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 268                                  u64 npages, u8 page_shift,
 269                                  struct mlx5_core_mkey *umr_mkey)
 270 {
 271         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 272         void *mkc;
 273         u32 *in;
 274         int err;
 275 
 276         in = kvzalloc(inlen, GFP_KERNEL);
 277         if (!in)
 278                 return -ENOMEM;
 279 
 280         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 281 
 282         MLX5_SET(mkc, mkc, free, 1);
 283         MLX5_SET(mkc, mkc, umr_en, 1);
 284         MLX5_SET(mkc, mkc, lw, 1);
 285         MLX5_SET(mkc, mkc, lr, 1);
 286         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 287 
 288         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 289         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 290         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 291         MLX5_SET(mkc, mkc, translations_octword_size,
 292                  MLX5_MTT_OCTW(npages));
 293         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 294 
 295         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 296 
 297         kvfree(in);
 298         return err;
 299 }
 300 
 301 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 302 {
 303         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 304 
 305         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 306 }
 307 
 308 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 309 {
 310         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 311 }
 312 
 313 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 314 {
 315         struct mlx5e_wqe_frag_info next_frag = {};
 316         struct mlx5e_wqe_frag_info *prev = NULL;
 317         int i;
 318 
 319         next_frag.di = &rq->wqe.di[0];
 320 
 321         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 322                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 323                 struct mlx5e_wqe_frag_info *frag =
 324                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 325                 int f;
 326 
 327                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 328                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 329                                 next_frag.di++;
 330                                 next_frag.offset = 0;
 331                                 if (prev)
 332                                         prev->last_in_page = true;
 333                         }
 334                         *frag = next_frag;
 335 
 336                         /* prepare next */
 337                         next_frag.offset += frag_info[f].frag_stride;
 338                         prev = frag;
 339                 }
 340         }
 341 
 342         if (prev)
 343                 prev->last_in_page = true;
 344 }
 345 
 346 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 347                               int wq_sz, int cpu)
 348 {
 349         int len = wq_sz << rq->wqe.info.log_num_frags;
 350 
 351         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 352                                    GFP_KERNEL, cpu_to_node(cpu));
 353         if (!rq->wqe.di)
 354                 return -ENOMEM;
 355 
 356         mlx5e_init_frags_partition(rq);
 357 
 358         return 0;
 359 }
 360 
 361 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 362 {
 363         kvfree(rq->wqe.di);
 364 }
 365 
 366 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 367 {
 368         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 369 
 370         mlx5e_reporter_rq_cqe_err(rq);
 371 }
 372 
 373 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 374                           struct mlx5e_params *params,
 375                           struct mlx5e_xsk_param *xsk,
 376                           struct xdp_umem *umem,
 377                           struct mlx5e_rq_param *rqp,
 378                           struct mlx5e_rq *rq)
 379 {
 380         struct page_pool_params pp_params = { 0 };
 381         struct mlx5_core_dev *mdev = c->mdev;
 382         void *rqc = rqp->rqc;
 383         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 384         u32 num_xsk_frames = 0;
 385         u32 rq_xdp_ix;
 386         u32 pool_size;
 387         int wq_sz;
 388         int err;
 389         int i;
 390 
 391         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 392 
 393         rq->wq_type = params->rq_wq_type;
 394         rq->pdev    = c->pdev;
 395         rq->netdev  = c->netdev;
 396         rq->tstamp  = c->tstamp;
 397         rq->clock   = &mdev->clock;
 398         rq->channel = c;
 399         rq->ix      = c->ix;
 400         rq->mdev    = mdev;
 401         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 402         rq->xdpsq   = &c->rq_xdpsq;
 403         rq->umem    = umem;
 404 
 405         if (rq->umem)
 406                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 407         else
 408                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 409         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 410 
 411         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 412         if (IS_ERR(rq->xdp_prog)) {
 413                 err = PTR_ERR(rq->xdp_prog);
 414                 rq->xdp_prog = NULL;
 415                 goto err_rq_wq_destroy;
 416         }
 417 
 418         rq_xdp_ix = rq->ix;
 419         if (xsk)
 420                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 421         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
 422         if (err < 0)
 423                 goto err_rq_wq_destroy;
 424 
 425         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 426         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 427         rq->buff.umem_headroom = xsk ? xsk->headroom : 0;
 428         pool_size = 1 << params->log_rq_mtu_frames;
 429 
 430         switch (rq->wq_type) {
 431         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 432                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 433                                         &rq->wq_ctrl);
 434                 if (err)
 435                         return err;
 436 
 437                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 438 
 439                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 440 
 441                 if (xsk)
 442                         num_xsk_frames = wq_sz <<
 443                                 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
 444 
 445                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 446                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 447 
 448                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 449                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 450 
 451                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 452 #ifdef CONFIG_MLX5_EN_IPSEC
 453                 if (MLX5_IPSEC_DEV(mdev)) {
 454                         err = -EINVAL;
 455                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 456                         goto err_rq_wq_destroy;
 457                 }
 458 #endif
 459                 if (!rq->handle_rx_cqe) {
 460                         err = -EINVAL;
 461                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 462                         goto err_rq_wq_destroy;
 463                 }
 464 
 465                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
 466                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
 467                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
 468                                 mlx5e_skb_from_cqe_mpwrq_linear :
 469                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
 470 
 471                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 472                 rq->mpwqe.num_strides =
 473                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 474 
 475                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 476                 if (err)
 477                         goto err_rq_wq_destroy;
 478                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 479 
 480                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 481                 if (err)
 482                         goto err_free;
 483                 break;
 484         default: /* MLX5_WQ_TYPE_CYCLIC */
 485                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 486                                          &rq->wq_ctrl);
 487                 if (err)
 488                         return err;
 489 
 490                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 491 
 492                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 493 
 494                 if (xsk)
 495                         num_xsk_frames = wq_sz << rq->wqe.info.log_num_frags;
 496 
 497                 rq->wqe.info = rqp->frags_info;
 498                 rq->wqe.frags =
 499                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 500                                         (wq_sz << rq->wqe.info.log_num_frags)),
 501                                       GFP_KERNEL, cpu_to_node(c->cpu));
 502                 if (!rq->wqe.frags) {
 503                         err = -ENOMEM;
 504                         goto err_free;
 505                 }
 506 
 507                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 508                 if (err)
 509                         goto err_free;
 510 
 511                 rq->post_wqes = mlx5e_post_rx_wqes;
 512                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 513 
 514 #ifdef CONFIG_MLX5_EN_IPSEC
 515                 if (c->priv->ipsec)
 516                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 517                 else
 518 #endif
 519                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 520                 if (!rq->handle_rx_cqe) {
 521                         err = -EINVAL;
 522                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 523                         goto err_free;
 524                 }
 525 
 526                 rq->wqe.skb_from_cqe = xsk ?
 527                         mlx5e_xsk_skb_from_cqe_linear :
 528                         mlx5e_rx_is_linear_skb(params, NULL) ?
 529                                 mlx5e_skb_from_cqe_linear :
 530                                 mlx5e_skb_from_cqe_nonlinear;
 531                 rq->mkey_be = c->mkey_be;
 532         }
 533 
 534         if (xsk) {
 535                 err = mlx5e_xsk_resize_reuseq(umem, num_xsk_frames);
 536                 if (unlikely(err)) {
 537                         mlx5_core_err(mdev, "Unable to allocate the Reuse Ring for %u frames\n",
 538                                       num_xsk_frames);
 539                         goto err_free;
 540                 }
 541 
 542                 rq->zca.free = mlx5e_xsk_zca_free;
 543                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 544                                                  MEM_TYPE_ZERO_COPY,
 545                                                  &rq->zca);
 546         } else {
 547                 /* Create a page_pool and register it with rxq */
 548                 pp_params.order     = 0;
 549                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 550                 pp_params.pool_size = pool_size;
 551                 pp_params.nid       = cpu_to_node(c->cpu);
 552                 pp_params.dev       = c->pdev;
 553                 pp_params.dma_dir   = rq->buff.map_dir;
 554 
 555                 /* page_pool can be used even when there is no rq->xdp_prog,
 556                  * given page_pool does not handle DMA mapping there is no
 557                  * required state to clear. And page_pool gracefully handle
 558                  * elevated refcnt.
 559                  */
 560                 rq->page_pool = page_pool_create(&pp_params);
 561                 if (IS_ERR(rq->page_pool)) {
 562                         err = PTR_ERR(rq->page_pool);
 563                         rq->page_pool = NULL;
 564                         goto err_free;
 565                 }
 566                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 567                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 568         }
 569         if (err)
 570                 goto err_free;
 571 
 572         for (i = 0; i < wq_sz; i++) {
 573                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 574                         struct mlx5e_rx_wqe_ll *wqe =
 575                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 576                         u32 byte_count =
 577                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 578                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 579 
 580                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 581                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 582                         wqe->data[0].lkey = rq->mkey_be;
 583                 } else {
 584                         struct mlx5e_rx_wqe_cyc *wqe =
 585                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 586                         int f;
 587 
 588                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 589                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 590                                         MLX5_HW_START_PADDING;
 591 
 592                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 593                                 wqe->data[f].lkey = rq->mkey_be;
 594                         }
 595                         /* check if num_frags is not a pow of two */
 596                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 597                                 wqe->data[f].byte_count = 0;
 598                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 599                                 wqe->data[f].addr = 0;
 600                         }
 601                 }
 602         }
 603 
 604         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 605 
 606         switch (params->rx_cq_moderation.cq_period_mode) {
 607         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 608                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 609                 break;
 610         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 611         default:
 612                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 613         }
 614 
 615         rq->page_cache.head = 0;
 616         rq->page_cache.tail = 0;
 617 
 618         return 0;
 619 
 620 err_free:
 621         switch (rq->wq_type) {
 622         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 623                 kvfree(rq->mpwqe.info);
 624                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 625                 break;
 626         default: /* MLX5_WQ_TYPE_CYCLIC */
 627                 kvfree(rq->wqe.frags);
 628                 mlx5e_free_di_list(rq);
 629         }
 630 
 631 err_rq_wq_destroy:
 632         if (rq->xdp_prog)
 633                 bpf_prog_put(rq->xdp_prog);
 634         xdp_rxq_info_unreg(&rq->xdp_rxq);
 635         page_pool_destroy(rq->page_pool);
 636         mlx5_wq_destroy(&rq->wq_ctrl);
 637 
 638         return err;
 639 }
 640 
 641 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 642 {
 643         int i;
 644 
 645         if (rq->xdp_prog)
 646                 bpf_prog_put(rq->xdp_prog);
 647 
 648         switch (rq->wq_type) {
 649         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 650                 kvfree(rq->mpwqe.info);
 651                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 652                 break;
 653         default: /* MLX5_WQ_TYPE_CYCLIC */
 654                 kvfree(rq->wqe.frags);
 655                 mlx5e_free_di_list(rq);
 656         }
 657 
 658         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 659              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 660                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 661 
 662                 /* With AF_XDP, page_cache is not used, so this loop is not
 663                  * entered, and it's safe to call mlx5e_page_release_dynamic
 664                  * directly.
 665                  */
 666                 mlx5e_page_release_dynamic(rq, dma_info, false);
 667         }
 668 
 669         xdp_rxq_info_unreg(&rq->xdp_rxq);
 670         page_pool_destroy(rq->page_pool);
 671         mlx5_wq_destroy(&rq->wq_ctrl);
 672 }
 673 
 674 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 675                            struct mlx5e_rq_param *param)
 676 {
 677         struct mlx5_core_dev *mdev = rq->mdev;
 678 
 679         void *in;
 680         void *rqc;
 681         void *wq;
 682         int inlen;
 683         int err;
 684 
 685         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 686                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 687         in = kvzalloc(inlen, GFP_KERNEL);
 688         if (!in)
 689                 return -ENOMEM;
 690 
 691         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 692         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 693 
 694         memcpy(rqc, param->rqc, sizeof(param->rqc));
 695 
 696         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 697         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 698         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 699                                                 MLX5_ADAPTER_PAGE_SHIFT);
 700         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 701 
 702         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 703                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 704 
 705         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 706 
 707         kvfree(in);
 708 
 709         return err;
 710 }
 711 
 712 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 713 {
 714         struct mlx5_core_dev *mdev = rq->mdev;
 715 
 716         void *in;
 717         void *rqc;
 718         int inlen;
 719         int err;
 720 
 721         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 722         in = kvzalloc(inlen, GFP_KERNEL);
 723         if (!in)
 724                 return -ENOMEM;
 725 
 726         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 727                 mlx5e_rqwq_reset(rq);
 728 
 729         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 730 
 731         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 732         MLX5_SET(rqc, rqc, state, next_state);
 733 
 734         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 735 
 736         kvfree(in);
 737 
 738         return err;
 739 }
 740 
 741 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 742 {
 743         struct mlx5e_channel *c = rq->channel;
 744         struct mlx5e_priv *priv = c->priv;
 745         struct mlx5_core_dev *mdev = priv->mdev;
 746 
 747         void *in;
 748         void *rqc;
 749         int inlen;
 750         int err;
 751 
 752         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 753         in = kvzalloc(inlen, GFP_KERNEL);
 754         if (!in)
 755                 return -ENOMEM;
 756 
 757         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 758 
 759         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 760         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 761                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 762         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 763         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 764 
 765         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 766 
 767         kvfree(in);
 768 
 769         return err;
 770 }
 771 
 772 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 773 {
 774         struct mlx5e_channel *c = rq->channel;
 775         struct mlx5_core_dev *mdev = c->mdev;
 776         void *in;
 777         void *rqc;
 778         int inlen;
 779         int err;
 780 
 781         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 782         in = kvzalloc(inlen, GFP_KERNEL);
 783         if (!in)
 784                 return -ENOMEM;
 785 
 786         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 787 
 788         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 789         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 790                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 791         MLX5_SET(rqc, rqc, vsd, vsd);
 792         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 793 
 794         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 795 
 796         kvfree(in);
 797 
 798         return err;
 799 }
 800 
 801 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 802 {
 803         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 804 }
 805 
 806 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 807 {
 808         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 809         struct mlx5e_channel *c = rq->channel;
 810 
 811         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 812 
 813         do {
 814                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 815                         return 0;
 816 
 817                 msleep(20);
 818         } while (time_before(jiffies, exp_time));
 819 
 820         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 821                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 822 
 823         mlx5e_reporter_rx_timeout(rq);
 824         return -ETIMEDOUT;
 825 }
 826 
 827 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 828 {
 829         struct mlx5_wq_ll *wq;
 830         u16 head;
 831         int i;
 832 
 833         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 834                 return;
 835 
 836         wq = &rq->mpwqe.wq;
 837         head = wq->head;
 838 
 839         /* Outstanding UMR WQEs (in progress) start at wq->head */
 840         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 841                 rq->dealloc_wqe(rq, head);
 842                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 843         }
 844 
 845         rq->mpwqe.actual_wq_head = wq->head;
 846         rq->mpwqe.umr_in_progress = 0;
 847         rq->mpwqe.umr_completed = 0;
 848 }
 849 
 850 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 851 {
 852         __be16 wqe_ix_be;
 853         u16 wqe_ix;
 854 
 855         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 856                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 857 
 858                 mlx5e_free_rx_in_progress_descs(rq);
 859 
 860                 while (!mlx5_wq_ll_is_empty(wq)) {
 861                         struct mlx5e_rx_wqe_ll *wqe;
 862 
 863                         wqe_ix_be = *wq->tail_next;
 864                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 865                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 866                         rq->dealloc_wqe(rq, wqe_ix);
 867                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 868                                        &wqe->next.next_wqe_index);
 869                 }
 870         } else {
 871                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 872 
 873                 while (!mlx5_wq_cyc_is_empty(wq)) {
 874                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 875                         rq->dealloc_wqe(rq, wqe_ix);
 876                         mlx5_wq_cyc_pop(wq);
 877                 }
 878         }
 879 
 880 }
 881 
 882 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 883                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 884                   struct xdp_umem *umem, struct mlx5e_rq *rq)
 885 {
 886         int err;
 887 
 888         err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
 889         if (err)
 890                 return err;
 891 
 892         err = mlx5e_create_rq(rq, param);
 893         if (err)
 894                 goto err_free_rq;
 895 
 896         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 897         if (err)
 898                 goto err_destroy_rq;
 899 
 900         if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
 901                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
 902 
 903         if (params->rx_dim_enabled)
 904                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 905 
 906         /* We disable csum_complete when XDP is enabled since
 907          * XDP programs might manipulate packets which will render
 908          * skb->checksum incorrect.
 909          */
 910         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 911                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 912 
 913         return 0;
 914 
 915 err_destroy_rq:
 916         mlx5e_destroy_rq(rq);
 917 err_free_rq:
 918         mlx5e_free_rq(rq);
 919 
 920         return err;
 921 }
 922 
 923 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 924 {
 925         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 926         mlx5e_trigger_irq(&rq->channel->icosq);
 927 }
 928 
 929 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 930 {
 931         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 932         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 933 }
 934 
 935 void mlx5e_close_rq(struct mlx5e_rq *rq)
 936 {
 937         cancel_work_sync(&rq->dim.work);
 938         cancel_work_sync(&rq->channel->icosq.recover_work);
 939         cancel_work_sync(&rq->recover_work);
 940         mlx5e_destroy_rq(rq);
 941         mlx5e_free_rx_descs(rq);
 942         mlx5e_free_rq(rq);
 943 }
 944 
 945 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 946 {
 947         kvfree(sq->db.xdpi_fifo.xi);
 948         kvfree(sq->db.wqe_info);
 949 }
 950 
 951 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 952 {
 953         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 954         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 955         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 956 
 957         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 958                                       GFP_KERNEL, numa);
 959         if (!xdpi_fifo->xi)
 960                 return -ENOMEM;
 961 
 962         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 963         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 964         xdpi_fifo->mask = dsegs_per_wq - 1;
 965 
 966         return 0;
 967 }
 968 
 969 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 970 {
 971         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 972         int err;
 973 
 974         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 975                                         GFP_KERNEL, numa);
 976         if (!sq->db.wqe_info)
 977                 return -ENOMEM;
 978 
 979         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 980         if (err) {
 981                 mlx5e_free_xdpsq_db(sq);
 982                 return err;
 983         }
 984 
 985         return 0;
 986 }
 987 
 988 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 989                              struct mlx5e_params *params,
 990                              struct xdp_umem *umem,
 991                              struct mlx5e_sq_param *param,
 992                              struct mlx5e_xdpsq *sq,
 993                              bool is_redirect)
 994 {
 995         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 996         struct mlx5_core_dev *mdev = c->mdev;
 997         struct mlx5_wq_cyc *wq = &sq->wq;
 998         int err;
 999 
1000         sq->pdev      = c->pdev;
1001         sq->mkey_be   = c->mkey_be;
1002         sq->channel   = c;
1003         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1004         sq->min_inline_mode = params->tx_min_inline_mode;
1005         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1006         sq->umem      = umem;
1007 
1008         sq->stats = sq->umem ?
1009                 &c->priv->channel_stats[c->ix].xsksq :
1010                 is_redirect ?
1011                         &c->priv->channel_stats[c->ix].xdpsq :
1012                         &c->priv->channel_stats[c->ix].rq_xdpsq;
1013 
1014         param->wq.db_numa_node = cpu_to_node(c->cpu);
1015         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1016         if (err)
1017                 return err;
1018         wq->db = &wq->db[MLX5_SND_DBR];
1019 
1020         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1021         if (err)
1022                 goto err_sq_wq_destroy;
1023 
1024         return 0;
1025 
1026 err_sq_wq_destroy:
1027         mlx5_wq_destroy(&sq->wq_ctrl);
1028 
1029         return err;
1030 }
1031 
1032 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1033 {
1034         mlx5e_free_xdpsq_db(sq);
1035         mlx5_wq_destroy(&sq->wq_ctrl);
1036 }
1037 
1038 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1039 {
1040         kvfree(sq->db.ico_wqe);
1041 }
1042 
1043 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1044 {
1045         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1046 
1047         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1048                                                   sizeof(*sq->db.ico_wqe)),
1049                                        GFP_KERNEL, numa);
1050         if (!sq->db.ico_wqe)
1051                 return -ENOMEM;
1052 
1053         return 0;
1054 }
1055 
1056 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1057 {
1058         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1059                                               recover_work);
1060 
1061         mlx5e_reporter_icosq_cqe_err(sq);
1062 }
1063 
1064 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1065                              struct mlx5e_sq_param *param,
1066                              struct mlx5e_icosq *sq)
1067 {
1068         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1069         struct mlx5_core_dev *mdev = c->mdev;
1070         struct mlx5_wq_cyc *wq = &sq->wq;
1071         int err;
1072 
1073         sq->channel   = c;
1074         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1075 
1076         param->wq.db_numa_node = cpu_to_node(c->cpu);
1077         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1078         if (err)
1079                 return err;
1080         wq->db = &wq->db[MLX5_SND_DBR];
1081 
1082         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1083         if (err)
1084                 goto err_sq_wq_destroy;
1085 
1086         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1087 
1088         return 0;
1089 
1090 err_sq_wq_destroy:
1091         mlx5_wq_destroy(&sq->wq_ctrl);
1092 
1093         return err;
1094 }
1095 
1096 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1097 {
1098         mlx5e_free_icosq_db(sq);
1099         mlx5_wq_destroy(&sq->wq_ctrl);
1100 }
1101 
1102 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1103 {
1104         kvfree(sq->db.wqe_info);
1105         kvfree(sq->db.dma_fifo);
1106 }
1107 
1108 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1109 {
1110         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1111         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1112 
1113         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1114                                                    sizeof(*sq->db.dma_fifo)),
1115                                         GFP_KERNEL, numa);
1116         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1117                                                    sizeof(*sq->db.wqe_info)),
1118                                         GFP_KERNEL, numa);
1119         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1120                 mlx5e_free_txqsq_db(sq);
1121                 return -ENOMEM;
1122         }
1123 
1124         sq->dma_fifo_mask = df_sz - 1;
1125 
1126         return 0;
1127 }
1128 
1129 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1130 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1131                              int txq_ix,
1132                              struct mlx5e_params *params,
1133                              struct mlx5e_sq_param *param,
1134                              struct mlx5e_txqsq *sq,
1135                              int tc)
1136 {
1137         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1138         struct mlx5_core_dev *mdev = c->mdev;
1139         struct mlx5_wq_cyc *wq = &sq->wq;
1140         int err;
1141 
1142         sq->pdev      = c->pdev;
1143         sq->tstamp    = c->tstamp;
1144         sq->clock     = &mdev->clock;
1145         sq->mkey_be   = c->mkey_be;
1146         sq->channel   = c;
1147         sq->ch_ix     = c->ix;
1148         sq->txq_ix    = txq_ix;
1149         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1150         sq->min_inline_mode = params->tx_min_inline_mode;
1151         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1152         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1153         sq->stop_room = MLX5E_SQ_STOP_ROOM;
1154         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1155         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1156                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1157         if (MLX5_IPSEC_DEV(c->priv->mdev))
1158                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1159 #ifdef CONFIG_MLX5_EN_TLS
1160         if (mlx5_accel_is_tls_device(c->priv->mdev)) {
1161                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1162                 sq->stop_room += MLX5E_SQ_TLS_ROOM +
1163                         mlx5e_ktls_dumps_num_wqebbs(sq, MAX_SKB_FRAGS,
1164                                                     TLS_MAX_PAYLOAD_SIZE);
1165         }
1166 #endif
1167 
1168         param->wq.db_numa_node = cpu_to_node(c->cpu);
1169         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1170         if (err)
1171                 return err;
1172         wq->db    = &wq->db[MLX5_SND_DBR];
1173 
1174         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1175         if (err)
1176                 goto err_sq_wq_destroy;
1177 
1178         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1179         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1180 
1181         return 0;
1182 
1183 err_sq_wq_destroy:
1184         mlx5_wq_destroy(&sq->wq_ctrl);
1185 
1186         return err;
1187 }
1188 
1189 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1190 {
1191         mlx5e_free_txqsq_db(sq);
1192         mlx5_wq_destroy(&sq->wq_ctrl);
1193 }
1194 
1195 struct mlx5e_create_sq_param {
1196         struct mlx5_wq_ctrl        *wq_ctrl;
1197         u32                         cqn;
1198         u32                         tisn;
1199         u8                          tis_lst_sz;
1200         u8                          min_inline_mode;
1201 };
1202 
1203 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1204                            struct mlx5e_sq_param *param,
1205                            struct mlx5e_create_sq_param *csp,
1206                            u32 *sqn)
1207 {
1208         void *in;
1209         void *sqc;
1210         void *wq;
1211         int inlen;
1212         int err;
1213 
1214         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1215                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1216         in = kvzalloc(inlen, GFP_KERNEL);
1217         if (!in)
1218                 return -ENOMEM;
1219 
1220         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1221         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1222 
1223         memcpy(sqc, param->sqc, sizeof(param->sqc));
1224         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1225         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1226         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1227 
1228         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1229                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1230 
1231         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1232         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1233 
1234         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1235         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1236         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1237                                           MLX5_ADAPTER_PAGE_SHIFT);
1238         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1239 
1240         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1241                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1242 
1243         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1244 
1245         kvfree(in);
1246 
1247         return err;
1248 }
1249 
1250 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1251                     struct mlx5e_modify_sq_param *p)
1252 {
1253         void *in;
1254         void *sqc;
1255         int inlen;
1256         int err;
1257 
1258         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1259         in = kvzalloc(inlen, GFP_KERNEL);
1260         if (!in)
1261                 return -ENOMEM;
1262 
1263         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1264 
1265         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1266         MLX5_SET(sqc, sqc, state, p->next_state);
1267         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1268                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1269                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1270         }
1271 
1272         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1273 
1274         kvfree(in);
1275 
1276         return err;
1277 }
1278 
1279 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1280 {
1281         mlx5_core_destroy_sq(mdev, sqn);
1282 }
1283 
1284 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1285                                struct mlx5e_sq_param *param,
1286                                struct mlx5e_create_sq_param *csp,
1287                                u32 *sqn)
1288 {
1289         struct mlx5e_modify_sq_param msp = {0};
1290         int err;
1291 
1292         err = mlx5e_create_sq(mdev, param, csp, sqn);
1293         if (err)
1294                 return err;
1295 
1296         msp.curr_state = MLX5_SQC_STATE_RST;
1297         msp.next_state = MLX5_SQC_STATE_RDY;
1298         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1299         if (err)
1300                 mlx5e_destroy_sq(mdev, *sqn);
1301 
1302         return err;
1303 }
1304 
1305 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1306                                 struct mlx5e_txqsq *sq, u32 rate);
1307 
1308 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1309                             u32 tisn,
1310                             int txq_ix,
1311                             struct mlx5e_params *params,
1312                             struct mlx5e_sq_param *param,
1313                             struct mlx5e_txqsq *sq,
1314                             int tc)
1315 {
1316         struct mlx5e_create_sq_param csp = {};
1317         u32 tx_rate;
1318         int err;
1319 
1320         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1321         if (err)
1322                 return err;
1323 
1324         csp.tisn            = tisn;
1325         csp.tis_lst_sz      = 1;
1326         csp.cqn             = sq->cq.mcq.cqn;
1327         csp.wq_ctrl         = &sq->wq_ctrl;
1328         csp.min_inline_mode = sq->min_inline_mode;
1329         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1330         if (err)
1331                 goto err_free_txqsq;
1332 
1333         tx_rate = c->priv->tx_rates[sq->txq_ix];
1334         if (tx_rate)
1335                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1336 
1337         if (params->tx_dim_enabled)
1338                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1339 
1340         return 0;
1341 
1342 err_free_txqsq:
1343         mlx5e_free_txqsq(sq);
1344 
1345         return err;
1346 }
1347 
1348 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1349 {
1350         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1351         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1352         netdev_tx_reset_queue(sq->txq);
1353         netif_tx_start_queue(sq->txq);
1354 }
1355 
1356 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1357 {
1358         __netif_tx_lock_bh(txq);
1359         netif_tx_stop_queue(txq);
1360         __netif_tx_unlock_bh(txq);
1361 }
1362 
1363 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1364 {
1365         struct mlx5e_channel *c = sq->channel;
1366         struct mlx5_wq_cyc *wq = &sq->wq;
1367 
1368         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1369         /* prevent netif_tx_wake_queue */
1370         napi_synchronize(&c->napi);
1371 
1372         mlx5e_tx_disable_queue(sq->txq);
1373 
1374         /* last doorbell out, godspeed .. */
1375         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1376                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1377                 struct mlx5e_tx_wqe_info *wi;
1378                 struct mlx5e_tx_wqe *nop;
1379 
1380                 wi = &sq->db.wqe_info[pi];
1381 
1382                 memset(wi, 0, sizeof(*wi));
1383                 wi->num_wqebbs = 1;
1384                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1385                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1386         }
1387 }
1388 
1389 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1390 {
1391         struct mlx5e_channel *c = sq->channel;
1392         struct mlx5_core_dev *mdev = c->mdev;
1393         struct mlx5_rate_limit rl = {0};
1394 
1395         cancel_work_sync(&sq->dim.work);
1396         cancel_work_sync(&sq->recover_work);
1397         mlx5e_destroy_sq(mdev, sq->sqn);
1398         if (sq->rate_limit) {
1399                 rl.rate = sq->rate_limit;
1400                 mlx5_rl_remove_rate(mdev, &rl);
1401         }
1402         mlx5e_free_txqsq_descs(sq);
1403         mlx5e_free_txqsq(sq);
1404 }
1405 
1406 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1407 {
1408         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1409                                               recover_work);
1410 
1411         mlx5e_reporter_tx_err_cqe(sq);
1412 }
1413 
1414 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1415                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1416 {
1417         struct mlx5e_create_sq_param csp = {};
1418         int err;
1419 
1420         err = mlx5e_alloc_icosq(c, param, sq);
1421         if (err)
1422                 return err;
1423 
1424         csp.cqn             = sq->cq.mcq.cqn;
1425         csp.wq_ctrl         = &sq->wq_ctrl;
1426         csp.min_inline_mode = params->tx_min_inline_mode;
1427         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1428         if (err)
1429                 goto err_free_icosq;
1430 
1431         return 0;
1432 
1433 err_free_icosq:
1434         mlx5e_free_icosq(sq);
1435 
1436         return err;
1437 }
1438 
1439 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1440 {
1441         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1442 }
1443 
1444 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1445 {
1446         struct mlx5e_channel *c = icosq->channel;
1447 
1448         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1449         napi_synchronize(&c->napi);
1450 }
1451 
1452 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1453 {
1454         struct mlx5e_channel *c = sq->channel;
1455 
1456         mlx5e_destroy_sq(c->mdev, sq->sqn);
1457         mlx5e_free_icosq(sq);
1458 }
1459 
1460 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1461                      struct mlx5e_sq_param *param, struct xdp_umem *umem,
1462                      struct mlx5e_xdpsq *sq, bool is_redirect)
1463 {
1464         struct mlx5e_create_sq_param csp = {};
1465         int err;
1466 
1467         err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1468         if (err)
1469                 return err;
1470 
1471         csp.tis_lst_sz      = 1;
1472         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1473         csp.cqn             = sq->cq.mcq.cqn;
1474         csp.wq_ctrl         = &sq->wq_ctrl;
1475         csp.min_inline_mode = sq->min_inline_mode;
1476         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1477         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1478         if (err)
1479                 goto err_free_xdpsq;
1480 
1481         mlx5e_set_xmit_fp(sq, param->is_mpw);
1482 
1483         if (!param->is_mpw) {
1484                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1485                 unsigned int inline_hdr_sz = 0;
1486                 int i;
1487 
1488                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1489                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1490                         ds_cnt++;
1491                 }
1492 
1493                 /* Pre initialize fixed WQE fields */
1494                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1495                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1496                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1497                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1498                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1499                         struct mlx5_wqe_data_seg *dseg;
1500 
1501                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1502                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1503 
1504                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1505                         dseg->lkey = sq->mkey_be;
1506 
1507                         wi->num_wqebbs = 1;
1508                         wi->num_pkts   = 1;
1509                 }
1510         }
1511 
1512         return 0;
1513 
1514 err_free_xdpsq:
1515         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1516         mlx5e_free_xdpsq(sq);
1517 
1518         return err;
1519 }
1520 
1521 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1522 {
1523         struct mlx5e_channel *c = sq->channel;
1524 
1525         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1526         napi_synchronize(&c->napi);
1527 
1528         mlx5e_destroy_sq(c->mdev, sq->sqn);
1529         mlx5e_free_xdpsq_descs(sq);
1530         mlx5e_free_xdpsq(sq);
1531 }
1532 
1533 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1534                                  struct mlx5e_cq_param *param,
1535                                  struct mlx5e_cq *cq)
1536 {
1537         struct mlx5_core_cq *mcq = &cq->mcq;
1538         int eqn_not_used;
1539         unsigned int irqn;
1540         int err;
1541         u32 i;
1542 
1543         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1544         if (err)
1545                 return err;
1546 
1547         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1548                                &cq->wq_ctrl);
1549         if (err)
1550                 return err;
1551 
1552         mcq->cqe_sz     = 64;
1553         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1554         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1555         *mcq->set_ci_db = 0;
1556         *mcq->arm_db    = 0;
1557         mcq->vector     = param->eq_ix;
1558         mcq->comp       = mlx5e_completion_event;
1559         mcq->event      = mlx5e_cq_error_event;
1560         mcq->irqn       = irqn;
1561 
1562         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1563                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1564 
1565                 cqe->op_own = 0xf1;
1566         }
1567 
1568         cq->mdev = mdev;
1569 
1570         return 0;
1571 }
1572 
1573 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1574                           struct mlx5e_cq_param *param,
1575                           struct mlx5e_cq *cq)
1576 {
1577         struct mlx5_core_dev *mdev = c->priv->mdev;
1578         int err;
1579 
1580         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1581         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1582         param->eq_ix   = c->ix;
1583 
1584         err = mlx5e_alloc_cq_common(mdev, param, cq);
1585 
1586         cq->napi    = &c->napi;
1587         cq->channel = c;
1588 
1589         return err;
1590 }
1591 
1592 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1593 {
1594         mlx5_wq_destroy(&cq->wq_ctrl);
1595 }
1596 
1597 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1598 {
1599         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1600         struct mlx5_core_dev *mdev = cq->mdev;
1601         struct mlx5_core_cq *mcq = &cq->mcq;
1602 
1603         void *in;
1604         void *cqc;
1605         int inlen;
1606         unsigned int irqn_not_used;
1607         int eqn;
1608         int err;
1609 
1610         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1611         if (err)
1612                 return err;
1613 
1614         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1615                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1616         in = kvzalloc(inlen, GFP_KERNEL);
1617         if (!in)
1618                 return -ENOMEM;
1619 
1620         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1621 
1622         memcpy(cqc, param->cqc, sizeof(param->cqc));
1623 
1624         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1625                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1626 
1627         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1628         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1629         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1630         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1631                                             MLX5_ADAPTER_PAGE_SHIFT);
1632         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1633 
1634         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1635 
1636         kvfree(in);
1637 
1638         if (err)
1639                 return err;
1640 
1641         mlx5e_cq_arm(cq);
1642 
1643         return 0;
1644 }
1645 
1646 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1647 {
1648         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1649 }
1650 
1651 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1652                   struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1653 {
1654         struct mlx5_core_dev *mdev = c->mdev;
1655         int err;
1656 
1657         err = mlx5e_alloc_cq(c, param, cq);
1658         if (err)
1659                 return err;
1660 
1661         err = mlx5e_create_cq(cq, param);
1662         if (err)
1663                 goto err_free_cq;
1664 
1665         if (MLX5_CAP_GEN(mdev, cq_moderation))
1666                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1667         return 0;
1668 
1669 err_free_cq:
1670         mlx5e_free_cq(cq);
1671 
1672         return err;
1673 }
1674 
1675 void mlx5e_close_cq(struct mlx5e_cq *cq)
1676 {
1677         mlx5e_destroy_cq(cq);
1678         mlx5e_free_cq(cq);
1679 }
1680 
1681 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1682                              struct mlx5e_params *params,
1683                              struct mlx5e_channel_param *cparam)
1684 {
1685         int err;
1686         int tc;
1687 
1688         for (tc = 0; tc < c->num_tc; tc++) {
1689                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1690                                     &cparam->tx_cq, &c->sq[tc].cq);
1691                 if (err)
1692                         goto err_close_tx_cqs;
1693         }
1694 
1695         return 0;
1696 
1697 err_close_tx_cqs:
1698         for (tc--; tc >= 0; tc--)
1699                 mlx5e_close_cq(&c->sq[tc].cq);
1700 
1701         return err;
1702 }
1703 
1704 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1705 {
1706         int tc;
1707 
1708         for (tc = 0; tc < c->num_tc; tc++)
1709                 mlx5e_close_cq(&c->sq[tc].cq);
1710 }
1711 
1712 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1713                           struct mlx5e_params *params,
1714                           struct mlx5e_channel_param *cparam)
1715 {
1716         int err, tc;
1717 
1718         for (tc = 0; tc < params->num_tc; tc++) {
1719                 int txq_ix = c->ix + tc * params->num_channels;
1720 
1721                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1722                                        params, &cparam->sq, &c->sq[tc], tc);
1723                 if (err)
1724                         goto err_close_sqs;
1725         }
1726 
1727         return 0;
1728 
1729 err_close_sqs:
1730         for (tc--; tc >= 0; tc--)
1731                 mlx5e_close_txqsq(&c->sq[tc]);
1732 
1733         return err;
1734 }
1735 
1736 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1737 {
1738         int tc;
1739 
1740         for (tc = 0; tc < c->num_tc; tc++)
1741                 mlx5e_close_txqsq(&c->sq[tc]);
1742 }
1743 
1744 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1745                                 struct mlx5e_txqsq *sq, u32 rate)
1746 {
1747         struct mlx5e_priv *priv = netdev_priv(dev);
1748         struct mlx5_core_dev *mdev = priv->mdev;
1749         struct mlx5e_modify_sq_param msp = {0};
1750         struct mlx5_rate_limit rl = {0};
1751         u16 rl_index = 0;
1752         int err;
1753 
1754         if (rate == sq->rate_limit)
1755                 /* nothing to do */
1756                 return 0;
1757 
1758         if (sq->rate_limit) {
1759                 rl.rate = sq->rate_limit;
1760                 /* remove current rl index to free space to next ones */
1761                 mlx5_rl_remove_rate(mdev, &rl);
1762         }
1763 
1764         sq->rate_limit = 0;
1765 
1766         if (rate) {
1767                 rl.rate = rate;
1768                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1769                 if (err) {
1770                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1771                                    rate, err);
1772                         return err;
1773                 }
1774         }
1775 
1776         msp.curr_state = MLX5_SQC_STATE_RDY;
1777         msp.next_state = MLX5_SQC_STATE_RDY;
1778         msp.rl_index   = rl_index;
1779         msp.rl_update  = true;
1780         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1781         if (err) {
1782                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1783                            rate, err);
1784                 /* remove the rate from the table */
1785                 if (rate)
1786                         mlx5_rl_remove_rate(mdev, &rl);
1787                 return err;
1788         }
1789 
1790         sq->rate_limit = rate;
1791         return 0;
1792 }
1793 
1794 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1795 {
1796         struct mlx5e_priv *priv = netdev_priv(dev);
1797         struct mlx5_core_dev *mdev = priv->mdev;
1798         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1799         int err = 0;
1800 
1801         if (!mlx5_rl_is_supported(mdev)) {
1802                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1803                 return -EINVAL;
1804         }
1805 
1806         /* rate is given in Mb/sec, HW config is in Kb/sec */
1807         rate = rate << 10;
1808 
1809         /* Check whether rate in valid range, 0 is always valid */
1810         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1811                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1812                 return -ERANGE;
1813         }
1814 
1815         mutex_lock(&priv->state_lock);
1816         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1817                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1818         if (!err)
1819                 priv->tx_rates[index] = rate;
1820         mutex_unlock(&priv->state_lock);
1821 
1822         return err;
1823 }
1824 
1825 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1826                                    struct mlx5e_params *params)
1827 {
1828         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1829         int irq;
1830 
1831         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1832                 return -ENOMEM;
1833 
1834         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1835                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1836 
1837                 cpumask_set_cpu(cpu, c->xps_cpumask);
1838         }
1839 
1840         return 0;
1841 }
1842 
1843 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1844 {
1845         free_cpumask_var(c->xps_cpumask);
1846 }
1847 
1848 static int mlx5e_open_queues(struct mlx5e_channel *c,
1849                              struct mlx5e_params *params,
1850                              struct mlx5e_channel_param *cparam)
1851 {
1852         struct dim_cq_moder icocq_moder = {0, 0};
1853         int err;
1854 
1855         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1856         if (err)
1857                 return err;
1858 
1859         err = mlx5e_open_tx_cqs(c, params, cparam);
1860         if (err)
1861                 goto err_close_icosq_cq;
1862 
1863         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1864         if (err)
1865                 goto err_close_tx_cqs;
1866 
1867         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1868         if (err)
1869                 goto err_close_xdp_tx_cqs;
1870 
1871         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1872         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1873                                      &cparam->tx_cq, &c->rq_xdpsq.cq) : 0;
1874         if (err)
1875                 goto err_close_rx_cq;
1876 
1877         napi_enable(&c->napi);
1878 
1879         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1880         if (err)
1881                 goto err_disable_napi;
1882 
1883         err = mlx5e_open_sqs(c, params, cparam);
1884         if (err)
1885                 goto err_close_icosq;
1886 
1887         if (c->xdp) {
1888                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1889                                        &c->rq_xdpsq, false);
1890                 if (err)
1891                         goto err_close_sqs;
1892         }
1893 
1894         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1895         if (err)
1896                 goto err_close_xdp_sq;
1897 
1898         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1899         if (err)
1900                 goto err_close_rq;
1901 
1902         return 0;
1903 
1904 err_close_rq:
1905         mlx5e_close_rq(&c->rq);
1906 
1907 err_close_xdp_sq:
1908         if (c->xdp)
1909                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1910 
1911 err_close_sqs:
1912         mlx5e_close_sqs(c);
1913 
1914 err_close_icosq:
1915         mlx5e_close_icosq(&c->icosq);
1916 
1917 err_disable_napi:
1918         napi_disable(&c->napi);
1919 
1920         if (c->xdp)
1921                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1922 
1923 err_close_rx_cq:
1924         mlx5e_close_cq(&c->rq.cq);
1925 
1926 err_close_xdp_tx_cqs:
1927         mlx5e_close_cq(&c->xdpsq.cq);
1928 
1929 err_close_tx_cqs:
1930         mlx5e_close_tx_cqs(c);
1931 
1932 err_close_icosq_cq:
1933         mlx5e_close_cq(&c->icosq.cq);
1934 
1935         return err;
1936 }
1937 
1938 static void mlx5e_close_queues(struct mlx5e_channel *c)
1939 {
1940         mlx5e_close_xdpsq(&c->xdpsq);
1941         mlx5e_close_rq(&c->rq);
1942         if (c->xdp)
1943                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1944         mlx5e_close_sqs(c);
1945         mlx5e_close_icosq(&c->icosq);
1946         napi_disable(&c->napi);
1947         if (c->xdp)
1948                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1949         mlx5e_close_cq(&c->rq.cq);
1950         mlx5e_close_cq(&c->xdpsq.cq);
1951         mlx5e_close_tx_cqs(c);
1952         mlx5e_close_cq(&c->icosq.cq);
1953 }
1954 
1955 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1956 {
1957         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1958 
1959         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1960 }
1961 
1962 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1963                               struct mlx5e_params *params,
1964                               struct mlx5e_channel_param *cparam,
1965                               struct xdp_umem *umem,
1966                               struct mlx5e_channel **cp)
1967 {
1968         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1969         struct net_device *netdev = priv->netdev;
1970         struct mlx5e_xsk_param xsk;
1971         struct mlx5e_channel *c;
1972         unsigned int irq;
1973         int err;
1974         int eqn;
1975 
1976         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1977         if (err)
1978                 return err;
1979 
1980         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1981         if (!c)
1982                 return -ENOMEM;
1983 
1984         c->priv     = priv;
1985         c->mdev     = priv->mdev;
1986         c->tstamp   = &priv->tstamp;
1987         c->ix       = ix;
1988         c->cpu      = cpu;
1989         c->pdev     = priv->mdev->device;
1990         c->netdev   = priv->netdev;
1991         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1992         c->num_tc   = params->num_tc;
1993         c->xdp      = !!params->xdp_prog;
1994         c->stats    = &priv->channel_stats[ix].ch;
1995         c->irq_desc = irq_to_desc(irq);
1996         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
1997 
1998         err = mlx5e_alloc_xps_cpumask(c, params);
1999         if (err)
2000                 goto err_free_channel;
2001 
2002         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2003 
2004         err = mlx5e_open_queues(c, params, cparam);
2005         if (unlikely(err))
2006                 goto err_napi_del;
2007 
2008         if (umem) {
2009                 mlx5e_build_xsk_param(umem, &xsk);
2010                 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
2011                 if (unlikely(err))
2012                         goto err_close_queues;
2013         }
2014 
2015         *cp = c;
2016 
2017         return 0;
2018 
2019 err_close_queues:
2020         mlx5e_close_queues(c);
2021 
2022 err_napi_del:
2023         netif_napi_del(&c->napi);
2024         mlx5e_free_xps_cpumask(c);
2025 
2026 err_free_channel:
2027         kvfree(c);
2028 
2029         return err;
2030 }
2031 
2032 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2033 {
2034         int tc;
2035 
2036         for (tc = 0; tc < c->num_tc; tc++)
2037                 mlx5e_activate_txqsq(&c->sq[tc]);
2038         mlx5e_activate_icosq(&c->icosq);
2039         mlx5e_activate_rq(&c->rq);
2040         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
2041 
2042         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2043                 mlx5e_activate_xsk(c);
2044 }
2045 
2046 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2047 {
2048         int tc;
2049 
2050         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2051                 mlx5e_deactivate_xsk(c);
2052 
2053         mlx5e_deactivate_rq(&c->rq);
2054         mlx5e_deactivate_icosq(&c->icosq);
2055         for (tc = 0; tc < c->num_tc; tc++)
2056                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2057 }
2058 
2059 static void mlx5e_close_channel(struct mlx5e_channel *c)
2060 {
2061         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2062                 mlx5e_close_xsk(c);
2063         mlx5e_close_queues(c);
2064         netif_napi_del(&c->napi);
2065         mlx5e_free_xps_cpumask(c);
2066 
2067         kvfree(c);
2068 }
2069 
2070 #define DEFAULT_FRAG_SIZE (2048)
2071 
2072 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2073                                       struct mlx5e_params *params,
2074                                       struct mlx5e_xsk_param *xsk,
2075                                       struct mlx5e_rq_frags_info *info)
2076 {
2077         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2078         int frag_size_max = DEFAULT_FRAG_SIZE;
2079         u32 buf_size = 0;
2080         int i;
2081 
2082 #ifdef CONFIG_MLX5_EN_IPSEC
2083         if (MLX5_IPSEC_DEV(mdev))
2084                 byte_count += MLX5E_METADATA_ETHER_LEN;
2085 #endif
2086 
2087         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2088                 int frag_stride;
2089 
2090                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2091                 frag_stride = roundup_pow_of_two(frag_stride);
2092 
2093                 info->arr[0].frag_size = byte_count;
2094                 info->arr[0].frag_stride = frag_stride;
2095                 info->num_frags = 1;
2096                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2097                 goto out;
2098         }
2099 
2100         if (byte_count > PAGE_SIZE +
2101             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2102                 frag_size_max = PAGE_SIZE;
2103 
2104         i = 0;
2105         while (buf_size < byte_count) {
2106                 int frag_size = byte_count - buf_size;
2107 
2108                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2109                         frag_size = min(frag_size, frag_size_max);
2110 
2111                 info->arr[i].frag_size = frag_size;
2112                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2113 
2114                 buf_size += frag_size;
2115                 i++;
2116         }
2117         info->num_frags = i;
2118         /* number of different wqes sharing a page */
2119         info->wqe_bulk = 1 + (info->num_frags % 2);
2120 
2121 out:
2122         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2123         info->log_num_frags = order_base_2(info->num_frags);
2124 }
2125 
2126 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2127 {
2128         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2129 
2130         switch (wq_type) {
2131         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2132                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2133                 break;
2134         default: /* MLX5_WQ_TYPE_CYCLIC */
2135                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2136         }
2137 
2138         return order_base_2(sz);
2139 }
2140 
2141 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2142 {
2143         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2144 
2145         return MLX5_GET(wq, wq, log_wq_sz);
2146 }
2147 
2148 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2149                           struct mlx5e_params *params,
2150                           struct mlx5e_xsk_param *xsk,
2151                           struct mlx5e_rq_param *param)
2152 {
2153         struct mlx5_core_dev *mdev = priv->mdev;
2154         void *rqc = param->rqc;
2155         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2156         int ndsegs = 1;
2157 
2158         switch (params->rq_wq_type) {
2159         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2160                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2161                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2162                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2163                 MLX5_SET(wq, wq, log_wqe_stride_size,
2164                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2165                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2166                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2167                 break;
2168         default: /* MLX5_WQ_TYPE_CYCLIC */
2169                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2170                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2171                 ndsegs = param->frags_info.num_frags;
2172         }
2173 
2174         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2175         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2176         MLX5_SET(wq, wq, log_wq_stride,
2177                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2178         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2179         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2180         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2181         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2182 
2183         param->wq.buf_numa_node = dev_to_node(mdev->device);
2184 }
2185 
2186 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2187                                       struct mlx5e_rq_param *param)
2188 {
2189         struct mlx5_core_dev *mdev = priv->mdev;
2190         void *rqc = param->rqc;
2191         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2192 
2193         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2194         MLX5_SET(wq, wq, log_wq_stride,
2195                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2196         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2197 
2198         param->wq.buf_numa_node = dev_to_node(mdev->device);
2199 }
2200 
2201 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2202                                  struct mlx5e_sq_param *param)
2203 {
2204         void *sqc = param->sqc;
2205         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2206 
2207         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2208         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2209 
2210         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2211 }
2212 
2213 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2214                                  struct mlx5e_params *params,
2215                                  struct mlx5e_sq_param *param)
2216 {
2217         void *sqc = param->sqc;
2218         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2219         bool allow_swp;
2220 
2221         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2222                     !!MLX5_IPSEC_DEV(priv->mdev);
2223         mlx5e_build_sq_param_common(priv, param);
2224         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2225         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2226 }
2227 
2228 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2229                                         struct mlx5e_cq_param *param)
2230 {
2231         void *cqc = param->cqc;
2232 
2233         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2234         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2235                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2236 }
2237 
2238 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2239                              struct mlx5e_params *params,
2240                              struct mlx5e_xsk_param *xsk,
2241                              struct mlx5e_cq_param *param)
2242 {
2243         struct mlx5_core_dev *mdev = priv->mdev;
2244         void *cqc = param->cqc;
2245         u8 log_cq_size;
2246 
2247         switch (params->rq_wq_type) {
2248         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2249                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2250                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2251                 break;
2252         default: /* MLX5_WQ_TYPE_CYCLIC */
2253                 log_cq_size = params->log_rq_mtu_frames;
2254         }
2255 
2256         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2257         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2258                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2259                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2260         }
2261 
2262         mlx5e_build_common_cq_param(priv, param);
2263         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2264 }
2265 
2266 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2267                              struct mlx5e_params *params,
2268                              struct mlx5e_cq_param *param)
2269 {
2270         void *cqc = param->cqc;
2271 
2272         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2273 
2274         mlx5e_build_common_cq_param(priv, param);
2275         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2276 }
2277 
2278 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2279                               u8 log_wq_size,
2280                               struct mlx5e_cq_param *param)
2281 {
2282         void *cqc = param->cqc;
2283 
2284         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2285 
2286         mlx5e_build_common_cq_param(priv, param);
2287 
2288         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2289 }
2290 
2291 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2292                              u8 log_wq_size,
2293                              struct mlx5e_sq_param *param)
2294 {
2295         void *sqc = param->sqc;
2296         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2297 
2298         mlx5e_build_sq_param_common(priv, param);
2299 
2300         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2301         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2302 }
2303 
2304 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2305                              struct mlx5e_params *params,
2306                              struct mlx5e_sq_param *param)
2307 {
2308         void *sqc = param->sqc;
2309         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2310 
2311         mlx5e_build_sq_param_common(priv, param);
2312         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2313         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2314 }
2315 
2316 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2317                                       struct mlx5e_rq_param *rqp)
2318 {
2319         switch (params->rq_wq_type) {
2320         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2321                 return order_base_2(MLX5E_UMR_WQEBBS) +
2322                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2323         default: /* MLX5_WQ_TYPE_CYCLIC */
2324                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2325         }
2326 }
2327 
2328 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2329                                       struct mlx5e_params *params,
2330                                       struct mlx5e_channel_param *cparam)
2331 {
2332         u8 icosq_log_wq_sz;
2333 
2334         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2335 
2336         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2337 
2338         mlx5e_build_sq_param(priv, params, &cparam->sq);
2339         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2340         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2341         mlx5e_build_rx_cq_param(priv, params, NULL, &cparam->rx_cq);
2342         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2343         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2344 }
2345 
2346 int mlx5e_open_channels(struct mlx5e_priv *priv,
2347                         struct mlx5e_channels *chs)
2348 {
2349         struct mlx5e_channel_param *cparam;
2350         int err = -ENOMEM;
2351         int i;
2352 
2353         chs->num = chs->params.num_channels;
2354 
2355         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2356         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2357         if (!chs->c || !cparam)
2358                 goto err_free;
2359 
2360         mlx5e_build_channel_param(priv, &chs->params, cparam);
2361         for (i = 0; i < chs->num; i++) {
2362                 struct xdp_umem *umem = NULL;
2363 
2364                 if (chs->params.xdp_prog)
2365                         umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2366 
2367                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2368                 if (err)
2369                         goto err_close_channels;
2370         }
2371 
2372         mlx5e_health_channels_update(priv);
2373         kvfree(cparam);
2374         return 0;
2375 
2376 err_close_channels:
2377         for (i--; i >= 0; i--)
2378                 mlx5e_close_channel(chs->c[i]);
2379 
2380 err_free:
2381         kfree(chs->c);
2382         kvfree(cparam);
2383         chs->num = 0;
2384         return err;
2385 }
2386 
2387 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2388 {
2389         int i;
2390 
2391         for (i = 0; i < chs->num; i++)
2392                 mlx5e_activate_channel(chs->c[i]);
2393 }
2394 
2395 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2396 
2397 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2398 {
2399         int err = 0;
2400         int i;
2401 
2402         for (i = 0; i < chs->num; i++) {
2403                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2404 
2405                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2406 
2407                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2408                  * doesn't provide any Fill Ring entries at the setup stage.
2409                  */
2410         }
2411 
2412         return err ? -ETIMEDOUT : 0;
2413 }
2414 
2415 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2416 {
2417         int i;
2418 
2419         for (i = 0; i < chs->num; i++)
2420                 mlx5e_deactivate_channel(chs->c[i]);
2421 }
2422 
2423 void mlx5e_close_channels(struct mlx5e_channels *chs)
2424 {
2425         int i;
2426 
2427         for (i = 0; i < chs->num; i++)
2428                 mlx5e_close_channel(chs->c[i]);
2429 
2430         kfree(chs->c);
2431         chs->num = 0;
2432 }
2433 
2434 static int
2435 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2436 {
2437         struct mlx5_core_dev *mdev = priv->mdev;
2438         void *rqtc;
2439         int inlen;
2440         int err;
2441         u32 *in;
2442         int i;
2443 
2444         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2445         in = kvzalloc(inlen, GFP_KERNEL);
2446         if (!in)
2447                 return -ENOMEM;
2448 
2449         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2450 
2451         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2452         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2453 
2454         for (i = 0; i < sz; i++)
2455                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2456 
2457         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2458         if (!err)
2459                 rqt->enabled = true;
2460 
2461         kvfree(in);
2462         return err;
2463 }
2464 
2465 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2466 {
2467         rqt->enabled = false;
2468         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2469 }
2470 
2471 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2472 {
2473         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2474         int err;
2475 
2476         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2477         if (err)
2478                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2479         return err;
2480 }
2481 
2482 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2483 {
2484         int err;
2485         int ix;
2486 
2487         for (ix = 0; ix < priv->max_nch; ix++) {
2488                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2489                 if (unlikely(err))
2490                         goto err_destroy_rqts;
2491         }
2492 
2493         return 0;
2494 
2495 err_destroy_rqts:
2496         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2497         for (ix--; ix >= 0; ix--)
2498                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2499 
2500         return err;
2501 }
2502 
2503 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2504 {
2505         int i;
2506 
2507         for (i = 0; i < priv->max_nch; i++)
2508                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2509 }
2510 
2511 static int mlx5e_rx_hash_fn(int hfunc)
2512 {
2513         return (hfunc == ETH_RSS_HASH_TOP) ?
2514                MLX5_RX_HASH_FN_TOEPLITZ :
2515                MLX5_RX_HASH_FN_INVERTED_XOR8;
2516 }
2517 
2518 int mlx5e_bits_invert(unsigned long a, int size)
2519 {
2520         int inv = 0;
2521         int i;
2522 
2523         for (i = 0; i < size; i++)
2524                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2525 
2526         return inv;
2527 }
2528 
2529 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2530                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2531 {
2532         int i;
2533 
2534         for (i = 0; i < sz; i++) {
2535                 u32 rqn;
2536 
2537                 if (rrp.is_rss) {
2538                         int ix = i;
2539 
2540                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2541                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2542 
2543                         ix = priv->rss_params.indirection_rqt[ix];
2544                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2545                 } else {
2546                         rqn = rrp.rqn;
2547                 }
2548                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2549         }
2550 }
2551 
2552 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2553                        struct mlx5e_redirect_rqt_param rrp)
2554 {
2555         struct mlx5_core_dev *mdev = priv->mdev;
2556         void *rqtc;
2557         int inlen;
2558         u32 *in;
2559         int err;
2560 
2561         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2562         in = kvzalloc(inlen, GFP_KERNEL);
2563         if (!in)
2564                 return -ENOMEM;
2565 
2566         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2567 
2568         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2569         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2570         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2571         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2572 
2573         kvfree(in);
2574         return err;
2575 }
2576 
2577 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2578                                 struct mlx5e_redirect_rqt_param rrp)
2579 {
2580         if (!rrp.is_rss)
2581                 return rrp.rqn;
2582 
2583         if (ix >= rrp.rss.channels->num)
2584                 return priv->drop_rq.rqn;
2585 
2586         return rrp.rss.channels->c[ix]->rq.rqn;
2587 }
2588 
2589 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2590                                 struct mlx5e_redirect_rqt_param rrp)
2591 {
2592         u32 rqtn;
2593         int ix;
2594 
2595         if (priv->indir_rqt.enabled) {
2596                 /* RSS RQ table */
2597                 rqtn = priv->indir_rqt.rqtn;
2598                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2599         }
2600 
2601         for (ix = 0; ix < priv->max_nch; ix++) {
2602                 struct mlx5e_redirect_rqt_param direct_rrp = {
2603                         .is_rss = false,
2604                         {
2605                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2606                         },
2607                 };
2608 
2609                 /* Direct RQ Tables */
2610                 if (!priv->direct_tir[ix].rqt.enabled)
2611                         continue;
2612 
2613                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2614                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2615         }
2616 }
2617 
2618 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2619                                             struct mlx5e_channels *chs)
2620 {
2621         struct mlx5e_redirect_rqt_param rrp = {
2622                 .is_rss        = true,
2623                 {
2624                         .rss = {
2625                                 .channels  = chs,
2626                                 .hfunc     = priv->rss_params.hfunc,
2627                         }
2628                 },
2629         };
2630 
2631         mlx5e_redirect_rqts(priv, rrp);
2632 }
2633 
2634 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2635 {
2636         struct mlx5e_redirect_rqt_param drop_rrp = {
2637                 .is_rss = false,
2638                 {
2639                         .rqn = priv->drop_rq.rqn,
2640                 },
2641         };
2642 
2643         mlx5e_redirect_rqts(priv, drop_rrp);
2644 }
2645 
2646 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2647         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2648                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2649                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2650         },
2651         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2652                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2653                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2654         },
2655         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2656                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2657                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2658         },
2659         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2660                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2661                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2662         },
2663         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2664                                      .l4_prot_type = 0,
2665                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2666         },
2667         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2668                                      .l4_prot_type = 0,
2669                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2670         },
2671         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2672                                       .l4_prot_type = 0,
2673                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2674         },
2675         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2676                                       .l4_prot_type = 0,
2677                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2678         },
2679         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2680                             .l4_prot_type = 0,
2681                             .rx_hash_fields = MLX5_HASH_IP,
2682         },
2683         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2684                             .l4_prot_type = 0,
2685                             .rx_hash_fields = MLX5_HASH_IP,
2686         },
2687 };
2688 
2689 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2690 {
2691         return tirc_default_config[tt];
2692 }
2693 
2694 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2695 {
2696         if (!params->lro_en)
2697                 return;
2698 
2699 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2700 
2701         MLX5_SET(tirc, tirc, lro_enable_mask,
2702                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2703                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2704         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2705                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2706         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2707 }
2708 
2709 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2710                                     const struct mlx5e_tirc_config *ttconfig,
2711                                     void *tirc, bool inner)
2712 {
2713         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2714                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2715 
2716         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2717         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2718                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2719                                              rx_hash_toeplitz_key);
2720                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2721                                                rx_hash_toeplitz_key);
2722 
2723                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2724                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2725         }
2726         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2727                  ttconfig->l3_prot_type);
2728         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2729                  ttconfig->l4_prot_type);
2730         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2731                  ttconfig->rx_hash_fields);
2732 }
2733 
2734 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2735                                         enum mlx5e_traffic_types tt,
2736                                         u32 rx_hash_fields)
2737 {
2738         *ttconfig                = tirc_default_config[tt];
2739         ttconfig->rx_hash_fields = rx_hash_fields;
2740 }
2741 
2742 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2743 {
2744         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2745         struct mlx5e_rss_params *rss = &priv->rss_params;
2746         struct mlx5_core_dev *mdev = priv->mdev;
2747         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2748         struct mlx5e_tirc_config ttconfig;
2749         int tt;
2750 
2751         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2752 
2753         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2754                 memset(tirc, 0, ctxlen);
2755                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2756                                             rss->rx_hash_fields[tt]);
2757                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2758                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2759         }
2760 
2761         /* Verify inner tirs resources allocated */
2762         if (!priv->inner_indir_tir[0].tirn)
2763                 return;
2764 
2765         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2766                 memset(tirc, 0, ctxlen);
2767                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2768                                             rss->rx_hash_fields[tt]);
2769                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2770                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2771                                      inlen);
2772         }
2773 }
2774 
2775 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2776 {
2777         struct mlx5_core_dev *mdev = priv->mdev;
2778 
2779         void *in;
2780         void *tirc;
2781         int inlen;
2782         int err;
2783         int tt;
2784         int ix;
2785 
2786         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2787         in = kvzalloc(inlen, GFP_KERNEL);
2788         if (!in)
2789                 return -ENOMEM;
2790 
2791         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2792         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2793 
2794         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2795 
2796         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2797                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2798                                            inlen);
2799                 if (err)
2800                         goto free_in;
2801         }
2802 
2803         for (ix = 0; ix < priv->max_nch; ix++) {
2804                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2805                                            in, inlen);
2806                 if (err)
2807                         goto free_in;
2808         }
2809 
2810 free_in:
2811         kvfree(in);
2812 
2813         return err;
2814 }
2815 
2816 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2817                          struct mlx5e_params *params, u16 mtu)
2818 {
2819         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2820         int err;
2821 
2822         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2823         if (err)
2824                 return err;
2825 
2826         /* Update vport context MTU */
2827         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2828         return 0;
2829 }
2830 
2831 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2832                             struct mlx5e_params *params, u16 *mtu)
2833 {
2834         u16 hw_mtu = 0;
2835         int err;
2836 
2837         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2838         if (err || !hw_mtu) /* fallback to port oper mtu */
2839                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2840 
2841         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2842 }
2843 
2844 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2845 {
2846         struct mlx5e_params *params = &priv->channels.params;
2847         struct net_device *netdev = priv->netdev;
2848         struct mlx5_core_dev *mdev = priv->mdev;
2849         u16 mtu;
2850         int err;
2851 
2852         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2853         if (err)
2854                 return err;
2855 
2856         mlx5e_query_mtu(mdev, params, &mtu);
2857         if (mtu != params->sw_mtu)
2858                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2859                             __func__, mtu, params->sw_mtu);
2860 
2861         params->sw_mtu = mtu;
2862         return 0;
2863 }
2864 
2865 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2866 {
2867         struct mlx5e_params *params = &priv->channels.params;
2868         struct net_device *netdev   = priv->netdev;
2869         struct mlx5_core_dev *mdev  = priv->mdev;
2870         u16 max_mtu;
2871 
2872         /* MTU range: 68 - hw-specific max */
2873         netdev->min_mtu = ETH_MIN_MTU;
2874 
2875         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2876         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2877                                 ETH_MAX_MTU);
2878 }
2879 
2880 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2881 {
2882         struct mlx5e_priv *priv = netdev_priv(netdev);
2883         int nch = priv->channels.params.num_channels;
2884         int ntc = priv->channels.params.num_tc;
2885         int tc;
2886 
2887         netdev_reset_tc(netdev);
2888 
2889         if (ntc == 1)
2890                 return;
2891 
2892         netdev_set_num_tc(netdev, ntc);
2893 
2894         /* Map netdev TCs to offset 0
2895          * We have our own UP to TXQ mapping for QoS
2896          */
2897         for (tc = 0; tc < ntc; tc++)
2898                 netdev_set_tc_queue(netdev, tc, nch, 0);
2899 }
2900 
2901 static void mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2902 {
2903         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2904         int num_rxqs = priv->channels.num * priv->profile->rq_groups;
2905         struct net_device *netdev = priv->netdev;
2906 
2907         mlx5e_netdev_set_tcs(netdev);
2908         netif_set_real_num_tx_queues(netdev, num_txqs);
2909         netif_set_real_num_rx_queues(netdev, num_rxqs);
2910 }
2911 
2912 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2913 {
2914         u16 count = priv->channels.params.num_channels;
2915 
2916         if (!netif_is_rxfh_configured(priv->netdev))
2917                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
2918                                               MLX5E_INDIR_RQT_SIZE, count);
2919 
2920         return 0;
2921 }
2922 
2923 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2924 {
2925         int i, ch;
2926 
2927         ch = priv->channels.num;
2928 
2929         for (i = 0; i < ch; i++) {
2930                 int tc;
2931 
2932                 for (tc = 0; tc < priv->channels.params.num_tc; tc++) {
2933                         struct mlx5e_channel *c = priv->channels.c[i];
2934                         struct mlx5e_txqsq *sq = &c->sq[tc];
2935 
2936                         priv->txq2sq[sq->txq_ix] = sq;
2937                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2938                 }
2939         }
2940 }
2941 
2942 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2943 {
2944         mlx5e_update_netdev_queues(priv);
2945 
2946         mlx5e_build_txq_maps(priv);
2947         mlx5e_activate_channels(&priv->channels);
2948         mlx5e_xdp_tx_enable(priv);
2949         netif_tx_start_all_queues(priv->netdev);
2950 
2951         if (mlx5e_is_vport_rep(priv))
2952                 mlx5e_add_sqs_fwd_rules(priv);
2953 
2954         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2955         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2956 
2957         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2958 }
2959 
2960 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2961 {
2962         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2963 
2964         mlx5e_redirect_rqts_to_drop(priv);
2965 
2966         if (mlx5e_is_vport_rep(priv))
2967                 mlx5e_remove_sqs_fwd_rules(priv);
2968 
2969         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2970          * polling for inactive tx queues.
2971          */
2972         netif_tx_stop_all_queues(priv->netdev);
2973         netif_tx_disable(priv->netdev);
2974         mlx5e_xdp_tx_disable(priv);
2975         mlx5e_deactivate_channels(&priv->channels);
2976 }
2977 
2978 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2979                                        struct mlx5e_channels *new_chs,
2980                                        mlx5e_fp_preactivate preactivate)
2981 {
2982         struct net_device *netdev = priv->netdev;
2983         int new_num_txqs;
2984         int carrier_ok;
2985 
2986         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2987 
2988         carrier_ok = netif_carrier_ok(netdev);
2989         netif_carrier_off(netdev);
2990 
2991         if (new_num_txqs < netdev->real_num_tx_queues)
2992                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2993 
2994         mlx5e_deactivate_priv_channels(priv);
2995         mlx5e_close_channels(&priv->channels);
2996 
2997         priv->channels = *new_chs;
2998 
2999         /* New channels are ready to roll, call the preactivate hook if needed
3000          * to modify HW settings or update kernel parameters.
3001          */
3002         if (preactivate)
3003                 preactivate(priv);
3004 
3005         priv->profile->update_rx(priv);
3006         mlx5e_activate_priv_channels(priv);
3007 
3008         /* return carrier back if needed */
3009         if (carrier_ok)
3010                 netif_carrier_on(netdev);
3011 }
3012 
3013 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
3014                                struct mlx5e_channels *new_chs,
3015                                mlx5e_fp_preactivate preactivate)
3016 {
3017         int err;
3018 
3019         err = mlx5e_open_channels(priv, new_chs);
3020         if (err)
3021                 return err;
3022 
3023         mlx5e_switch_priv_channels(priv, new_chs, preactivate);
3024         return 0;
3025 }
3026 
3027 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
3028 {
3029         struct mlx5e_channels new_channels = {};
3030 
3031         new_channels.params = priv->channels.params;
3032         return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3033 }
3034 
3035 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3036 {
3037         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
3038         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3039 }
3040 
3041 int mlx5e_open_locked(struct net_device *netdev)
3042 {
3043         struct mlx5e_priv *priv = netdev_priv(netdev);
3044         int err;
3045 
3046         set_bit(MLX5E_STATE_OPENED, &priv->state);
3047 
3048         err = mlx5e_open_channels(priv, &priv->channels);
3049         if (err)
3050                 goto err_clear_state_opened_flag;
3051 
3052         priv->profile->update_rx(priv);
3053         mlx5e_activate_priv_channels(priv);
3054         if (priv->profile->update_carrier)
3055                 priv->profile->update_carrier(priv);
3056 
3057         mlx5e_queue_update_stats(priv);
3058         return 0;
3059 
3060 err_clear_state_opened_flag:
3061         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3062         return err;
3063 }
3064 
3065 int mlx5e_open(struct net_device *netdev)
3066 {
3067         struct mlx5e_priv *priv = netdev_priv(netdev);
3068         int err;
3069 
3070         mutex_lock(&priv->state_lock);
3071         err = mlx5e_open_locked(netdev);
3072         if (!err)
3073                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3074         mutex_unlock(&priv->state_lock);
3075 
3076         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3077                 udp_tunnel_get_rx_info(netdev);
3078 
3079         return err;
3080 }
3081 
3082 int mlx5e_close_locked(struct net_device *netdev)
3083 {
3084         struct mlx5e_priv *priv = netdev_priv(netdev);
3085 
3086         /* May already be CLOSED in case a previous configuration operation
3087          * (e.g RX/TX queue size change) that involves close&open failed.
3088          */
3089         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3090                 return 0;
3091 
3092         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3093 
3094         netif_carrier_off(priv->netdev);
3095         mlx5e_deactivate_priv_channels(priv);
3096         mlx5e_close_channels(&priv->channels);
3097 
3098         return 0;
3099 }
3100 
3101 int mlx5e_close(struct net_device *netdev)
3102 {
3103         struct mlx5e_priv *priv = netdev_priv(netdev);
3104         int err;
3105 
3106         if (!netif_device_present(netdev))
3107                 return -ENODEV;
3108 
3109         mutex_lock(&priv->state_lock);
3110         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3111         err = mlx5e_close_locked(netdev);
3112         mutex_unlock(&priv->state_lock);
3113 
3114         return err;
3115 }
3116 
3117 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3118                                struct mlx5e_rq *rq,
3119                                struct mlx5e_rq_param *param)
3120 {
3121         void *rqc = param->rqc;
3122         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3123         int err;
3124 
3125         param->wq.db_numa_node = param->wq.buf_numa_node;
3126 
3127         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3128                                  &rq->wq_ctrl);
3129         if (err)
3130                 return err;
3131 
3132         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3133         xdp_rxq_info_unused(&rq->xdp_rxq);
3134 
3135         rq->mdev = mdev;
3136 
3137         return 0;
3138 }
3139 
3140 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3141                                struct mlx5e_cq *cq,
3142                                struct mlx5e_cq_param *param)
3143 {
3144         param->wq.buf_numa_node = dev_to_node(mdev->device);
3145         param->wq.db_numa_node  = dev_to_node(mdev->device);
3146 
3147         return mlx5e_alloc_cq_common(mdev, param, cq);
3148 }
3149 
3150 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3151                        struct mlx5e_rq *drop_rq)
3152 {
3153         struct mlx5_core_dev *mdev = priv->mdev;
3154         struct mlx5e_cq_param cq_param = {};
3155         struct mlx5e_rq_param rq_param = {};
3156         struct mlx5e_cq *cq = &drop_rq->cq;
3157         int err;
3158 
3159         mlx5e_build_drop_rq_param(priv, &rq_param);
3160 
3161         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3162         if (err)
3163                 return err;
3164 
3165         err = mlx5e_create_cq(cq, &cq_param);
3166         if (err)
3167                 goto err_free_cq;
3168 
3169         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3170         if (err)
3171                 goto err_destroy_cq;
3172 
3173         err = mlx5e_create_rq(drop_rq, &rq_param);
3174         if (err)
3175                 goto err_free_rq;
3176 
3177         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3178         if (err)
3179                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3180 
3181         return 0;
3182 
3183 err_free_rq:
3184         mlx5e_free_rq(drop_rq);
3185 
3186 err_destroy_cq:
3187         mlx5e_destroy_cq(cq);
3188 
3189 err_free_cq:
3190         mlx5e_free_cq(cq);
3191 
3192         return err;
3193 }
3194 
3195 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3196 {
3197         mlx5e_destroy_rq(drop_rq);
3198         mlx5e_free_rq(drop_rq);
3199         mlx5e_destroy_cq(&drop_rq->cq);
3200         mlx5e_free_cq(&drop_rq->cq);
3201 }
3202 
3203 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3204 {
3205         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3206 
3207         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3208 
3209         if (MLX5_GET(tisc, tisc, tls_en))
3210                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3211 
3212         if (mlx5_lag_is_lacp_owner(mdev))
3213                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3214 
3215         return mlx5_core_create_tis(mdev, in, MLX5_ST_SZ_BYTES(create_tis_in), tisn);
3216 }
3217 
3218 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3219 {
3220         mlx5_core_destroy_tis(mdev, tisn);
3221 }
3222 
3223 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3224 {
3225         int tc, i;
3226 
3227         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3228                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3229                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3230 }
3231 
3232 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3233 {
3234         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3235 }
3236 
3237 int mlx5e_create_tises(struct mlx5e_priv *priv)
3238 {
3239         int tc, i;
3240         int err;
3241 
3242         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3243                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3244                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3245                         void *tisc;
3246 
3247                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3248 
3249                         MLX5_SET(tisc, tisc, prio, tc << 1);
3250 
3251                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3252                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3253 
3254                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3255                         if (err)
3256                                 goto err_close_tises;
3257                 }
3258         }
3259 
3260         return 0;
3261 
3262 err_close_tises:
3263         for (; i >= 0; i--) {
3264                 for (tc--; tc >= 0; tc--)
3265                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3266                 tc = priv->profile->max_tc;
3267         }
3268 
3269         return err;
3270 }
3271 
3272 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3273 {
3274         mlx5e_destroy_tises(priv);
3275 }
3276 
3277 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3278                                              u32 rqtn, u32 *tirc)
3279 {
3280         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3281         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3282         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3283         MLX5_SET(tirc, tirc, tunneled_offload_en,
3284                  priv->channels.params.tunneled_offload_en);
3285 
3286         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3287 }
3288 
3289 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3290                                       enum mlx5e_traffic_types tt,
3291                                       u32 *tirc)
3292 {
3293         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3294         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3295                                        &tirc_default_config[tt], tirc, false);
3296 }
3297 
3298 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3299 {
3300         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3301         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3302 }
3303 
3304 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3305                                             enum mlx5e_traffic_types tt,
3306                                             u32 *tirc)
3307 {
3308         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3309         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3310                                        &tirc_default_config[tt], tirc, true);
3311 }
3312 
3313 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3314 {
3315         struct mlx5e_tir *tir;
3316         void *tirc;
3317         int inlen;
3318         int i = 0;
3319         int err;
3320         u32 *in;
3321         int tt;
3322 
3323         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3324         in = kvzalloc(inlen, GFP_KERNEL);
3325         if (!in)
3326                 return -ENOMEM;
3327 
3328         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3329                 memset(in, 0, inlen);
3330                 tir = &priv->indir_tir[tt];
3331                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3332                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3333                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3334                 if (err) {
3335                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3336                         goto err_destroy_inner_tirs;
3337                 }
3338         }
3339 
3340         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3341                 goto out;
3342 
3343         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3344                 memset(in, 0, inlen);
3345                 tir = &priv->inner_indir_tir[i];
3346                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3347                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3348                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3349                 if (err) {
3350                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3351                         goto err_destroy_inner_tirs;
3352                 }
3353         }
3354 
3355 out:
3356         kvfree(in);
3357 
3358         return 0;
3359 
3360 err_destroy_inner_tirs:
3361         for (i--; i >= 0; i--)
3362                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3363 
3364         for (tt--; tt >= 0; tt--)
3365                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3366 
3367         kvfree(in);
3368 
3369         return err;
3370 }
3371 
3372 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3373 {
3374         struct mlx5e_tir *tir;
3375         void *tirc;
3376         int inlen;
3377         int err = 0;
3378         u32 *in;
3379         int ix;
3380 
3381         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3382         in = kvzalloc(inlen, GFP_KERNEL);
3383         if (!in)
3384                 return -ENOMEM;
3385 
3386         for (ix = 0; ix < priv->max_nch; ix++) {
3387                 memset(in, 0, inlen);
3388                 tir = &tirs[ix];
3389                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3390                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3391                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3392                 if (unlikely(err))
3393                         goto err_destroy_ch_tirs;
3394         }
3395 
3396         goto out;
3397 
3398 err_destroy_ch_tirs:
3399         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3400         for (ix--; ix >= 0; ix--)
3401                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3402 
3403 out:
3404         kvfree(in);
3405 
3406         return err;
3407 }
3408 
3409 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3410 {
3411         int i;
3412 
3413         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3414                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3415 
3416         /* Verify inner tirs resources allocated */
3417         if (!priv->inner_indir_tir[0].tirn)
3418                 return;
3419 
3420         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3421                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3422 }
3423 
3424 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3425 {
3426         int i;
3427 
3428         for (i = 0; i < priv->max_nch; i++)
3429                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3430 }
3431 
3432 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3433 {
3434         int err = 0;
3435         int i;
3436 
3437         for (i = 0; i < chs->num; i++) {
3438                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3439                 if (err)
3440                         return err;
3441         }
3442 
3443         return 0;
3444 }
3445 
3446 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3447 {
3448         int err = 0;
3449         int i;
3450 
3451         for (i = 0; i < chs->num; i++) {
3452                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3453                 if (err)
3454                         return err;
3455         }
3456 
3457         return 0;
3458 }
3459 
3460 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3461                                  struct tc_mqprio_qopt *mqprio)
3462 {
3463         struct mlx5e_channels new_channels = {};
3464         u8 tc = mqprio->num_tc;
3465         int err = 0;
3466 
3467         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3468 
3469         if (tc && tc != MLX5E_MAX_NUM_TC)
3470                 return -EINVAL;
3471 
3472         mutex_lock(&priv->state_lock);
3473 
3474         new_channels.params = priv->channels.params;
3475         new_channels.params.num_tc = tc ? tc : 1;
3476 
3477         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3478                 priv->channels.params = new_channels.params;
3479                 goto out;
3480         }
3481 
3482         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3483         if (err)
3484                 goto out;
3485 
3486         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3487                                     new_channels.params.num_tc);
3488 out:
3489         mutex_unlock(&priv->state_lock);
3490         return err;
3491 }
3492 
3493 #ifdef CONFIG_MLX5_ESWITCH
3494 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3495                                      struct flow_cls_offload *cls_flower,
3496                                      unsigned long flags)
3497 {
3498         switch (cls_flower->command) {
3499         case FLOW_CLS_REPLACE:
3500                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3501                                               flags);
3502         case FLOW_CLS_DESTROY:
3503                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3504                                            flags);
3505         case FLOW_CLS_STATS:
3506                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3507                                           flags);
3508         default:
3509                 return -EOPNOTSUPP;
3510         }
3511 }
3512 
3513 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3514                                    void *cb_priv)
3515 {
3516         unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
3517         struct mlx5e_priv *priv = cb_priv;
3518 
3519         switch (type) {
3520         case TC_SETUP_CLSFLOWER:
3521                 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
3522         default:
3523                 return -EOPNOTSUPP;
3524         }
3525 }
3526 #endif
3527 
3528 static LIST_HEAD(mlx5e_block_cb_list);
3529 
3530 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3531                           void *type_data)
3532 {
3533         struct mlx5e_priv *priv = netdev_priv(dev);
3534 
3535         switch (type) {
3536 #ifdef CONFIG_MLX5_ESWITCH
3537         case TC_SETUP_BLOCK: {
3538                 struct flow_block_offload *f = type_data;
3539 
3540                 f->unlocked_driver_cb = true;
3541                 return flow_block_cb_setup_simple(type_data,
3542                                                   &mlx5e_block_cb_list,
3543                                                   mlx5e_setup_tc_block_cb,
3544                                                   priv, priv, true);
3545         }
3546 #endif
3547         case TC_SETUP_QDISC_MQPRIO:
3548                 return mlx5e_setup_tc_mqprio(priv, type_data);
3549         default:
3550                 return -EOPNOTSUPP;
3551         }
3552 }
3553 
3554 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3555 {
3556         int i;
3557 
3558         for (i = 0; i < priv->max_nch; i++) {
3559                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3560                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3561                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3562                 int j;
3563 
3564                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3565                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3566 
3567                 for (j = 0; j < priv->max_opened_tc; j++) {
3568                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3569 
3570                         s->tx_packets    += sq_stats->packets;
3571                         s->tx_bytes      += sq_stats->bytes;
3572                         s->tx_dropped    += sq_stats->dropped;
3573                 }
3574         }
3575 }
3576 
3577 void
3578 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3579 {
3580         struct mlx5e_priv *priv = netdev_priv(dev);
3581         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3582         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3583 
3584         /* In switchdev mode, monitor counters doesn't monitor
3585          * rx/tx stats of 802_3. The update stats mechanism
3586          * should keep the 802_3 layout counters updated
3587          */
3588         if (!mlx5e_monitor_counter_supported(priv) ||
3589             mlx5e_is_uplink_rep(priv)) {
3590                 /* update HW stats in background for next time */
3591                 mlx5e_queue_update_stats(priv);
3592         }
3593 
3594         if (mlx5e_is_uplink_rep(priv)) {
3595                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3596                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3597                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3598                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3599         } else {
3600                 mlx5e_fold_sw_stats64(priv, stats);
3601         }
3602 
3603         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3604 
3605         stats->rx_length_errors =
3606                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3607                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3608                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3609         stats->rx_crc_errors =
3610                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3611         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3612         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3613         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3614                            stats->rx_frame_errors;
3615         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3616 
3617         /* vport multicast also counts packets that are dropped due to steering
3618          * or rx out of buffer
3619          */
3620         stats->multicast =
3621                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3622 }
3623 
3624 static void mlx5e_set_rx_mode(struct net_device *dev)
3625 {
3626         struct mlx5e_priv *priv = netdev_priv(dev);
3627 
3628         queue_work(priv->wq, &priv->set_rx_mode_work);
3629 }
3630 
3631 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3632 {
3633         struct mlx5e_priv *priv = netdev_priv(netdev);
3634         struct sockaddr *saddr = addr;
3635 
3636         if (!is_valid_ether_addr(saddr->sa_data))
3637                 return -EADDRNOTAVAIL;
3638 
3639         netif_addr_lock_bh(netdev);
3640         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3641         netif_addr_unlock_bh(netdev);
3642 
3643         queue_work(priv->wq, &priv->set_rx_mode_work);
3644 
3645         return 0;
3646 }
3647 
3648 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3649         do {                                            \
3650                 if (enable)                             \
3651                         *features |= feature;           \
3652                 else                                    \
3653                         *features &= ~feature;          \
3654         } while (0)
3655 
3656 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3657 
3658 static int set_feature_lro(struct net_device *netdev, bool enable)
3659 {
3660         struct mlx5e_priv *priv = netdev_priv(netdev);
3661         struct mlx5_core_dev *mdev = priv->mdev;
3662         struct mlx5e_channels new_channels = {};
3663         struct mlx5e_params *old_params;
3664         int err = 0;
3665         bool reset;
3666 
3667         mutex_lock(&priv->state_lock);
3668 
3669         if (enable && priv->xsk.refcnt) {
3670                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3671                             priv->xsk.refcnt);
3672                 err = -EINVAL;
3673                 goto out;
3674         }
3675 
3676         old_params = &priv->channels.params;
3677         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3678                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3679                 err = -EINVAL;
3680                 goto out;
3681         }
3682 
3683         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3684 
3685         new_channels.params = *old_params;
3686         new_channels.params.lro_en = enable;
3687 
3688         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3689                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3690                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3691                         reset = false;
3692         }
3693 
3694         if (!reset) {
3695                 *old_params = new_channels.params;
3696                 err = mlx5e_modify_tirs_lro(priv);
3697                 goto out;
3698         }
3699 
3700         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3701 out:
3702         mutex_unlock(&priv->state_lock);
3703         return err;
3704 }
3705 
3706 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3707 {
3708         struct mlx5e_priv *priv = netdev_priv(netdev);
3709 
3710         if (enable)
3711                 mlx5e_enable_cvlan_filter(priv);
3712         else
3713                 mlx5e_disable_cvlan_filter(priv);
3714 
3715         return 0;
3716 }
3717 
3718 #ifdef CONFIG_MLX5_ESWITCH
3719 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3720 {
3721         struct mlx5e_priv *priv = netdev_priv(netdev);
3722 
3723         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3724                 netdev_err(netdev,
3725                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3726                 return -EINVAL;
3727         }
3728 
3729         return 0;
3730 }
3731 #endif
3732 
3733 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3734 {
3735         struct mlx5e_priv *priv = netdev_priv(netdev);
3736         struct mlx5_core_dev *mdev = priv->mdev;
3737 
3738         return mlx5_set_port_fcs(mdev, !enable);
3739 }
3740 
3741 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3742 {
3743         struct mlx5e_priv *priv = netdev_priv(netdev);
3744         int err;
3745 
3746         mutex_lock(&priv->state_lock);
3747 
3748         priv->channels.params.scatter_fcs_en = enable;
3749         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3750         if (err)
3751                 priv->channels.params.scatter_fcs_en = !enable;
3752 
3753         mutex_unlock(&priv->state_lock);
3754 
3755         return err;
3756 }
3757 
3758 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3759 {
3760         struct mlx5e_priv *priv = netdev_priv(netdev);
3761         int err = 0;
3762 
3763         mutex_lock(&priv->state_lock);
3764 
3765         priv->channels.params.vlan_strip_disable = !enable;
3766         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3767                 goto unlock;
3768 
3769         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3770         if (err)
3771                 priv->channels.params.vlan_strip_disable = enable;
3772 
3773 unlock:
3774         mutex_unlock(&priv->state_lock);
3775 
3776         return err;
3777 }
3778 
3779 #ifdef CONFIG_MLX5_EN_ARFS
3780 static int set_feature_arfs(struct net_device *netdev, bool enable)
3781 {
3782         struct mlx5e_priv *priv = netdev_priv(netdev);
3783         int err;
3784 
3785         if (enable)
3786                 err = mlx5e_arfs_enable(priv);
3787         else
3788                 err = mlx5e_arfs_disable(priv);
3789 
3790         return err;
3791 }
3792 #endif
3793 
3794 static int mlx5e_handle_feature(struct net_device *netdev,
3795                                 netdev_features_t *features,
3796                                 netdev_features_t wanted_features,
3797                                 netdev_features_t feature,
3798                                 mlx5e_feature_handler feature_handler)
3799 {
3800         netdev_features_t changes = wanted_features ^ netdev->features;
3801         bool enable = !!(wanted_features & feature);
3802         int err;
3803 
3804         if (!(changes & feature))
3805                 return 0;
3806 
3807         err = feature_handler(netdev, enable);
3808         if (err) {
3809                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3810                            enable ? "Enable" : "Disable", &feature, err);
3811                 return err;
3812         }
3813 
3814         MLX5E_SET_FEATURE(features, feature, enable);
3815         return 0;
3816 }
3817 
3818 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3819 {
3820         netdev_features_t oper_features = netdev->features;
3821         int err = 0;
3822 
3823 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3824         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3825 
3826         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3827         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3828                                     set_feature_cvlan_filter);
3829 #ifdef CONFIG_MLX5_ESWITCH
3830         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3831 #endif
3832         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3833         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3834         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3835 #ifdef CONFIG_MLX5_EN_ARFS
3836         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3837 #endif
3838 
3839         if (err) {
3840                 netdev->features = oper_features;
3841                 return -EINVAL;
3842         }
3843 
3844         return 0;
3845 }
3846 
3847 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3848                                             netdev_features_t features)
3849 {
3850         struct mlx5e_priv *priv = netdev_priv(netdev);
3851         struct mlx5e_params *params;
3852 
3853         mutex_lock(&priv->state_lock);
3854         params = &priv->channels.params;
3855         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3856                 /* HW strips the outer C-tag header, this is a problem
3857                  * for S-tag traffic.
3858                  */
3859                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3860                 if (!params->vlan_strip_disable)
3861                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3862         }
3863         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3864                 if (features & NETIF_F_LRO) {
3865                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3866                         features &= ~NETIF_F_LRO;
3867                 }
3868         }
3869 
3870         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3871                 features &= ~NETIF_F_RXHASH;
3872                 if (netdev->features & NETIF_F_RXHASH)
3873                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3874         }
3875 
3876         mutex_unlock(&priv->state_lock);
3877 
3878         return features;
3879 }
3880 
3881 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3882                                    struct mlx5e_channels *chs,
3883                                    struct mlx5e_params *new_params,
3884                                    struct mlx5_core_dev *mdev)
3885 {
3886         u16 ix;
3887 
3888         for (ix = 0; ix < chs->params.num_channels; ix++) {
3889                 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3890                 struct mlx5e_xsk_param xsk;
3891 
3892                 if (!umem)
3893                         continue;
3894 
3895                 mlx5e_build_xsk_param(umem, &xsk);
3896 
3897                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3898                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3899                         int max_mtu_frame, max_mtu_page, max_mtu;
3900 
3901                         /* Two criteria must be met:
3902                          * 1. HW MTU + all headrooms <= XSK frame size.
3903                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3904                          */
3905                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3906                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3907                         max_mtu = min(max_mtu_frame, max_mtu_page);
3908 
3909                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3910                                    new_params->sw_mtu, ix, max_mtu);
3911                         return false;
3912                 }
3913         }
3914 
3915         return true;
3916 }
3917 
3918 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3919                      change_hw_mtu_cb set_mtu_cb)
3920 {
3921         struct mlx5e_priv *priv = netdev_priv(netdev);
3922         struct mlx5e_channels new_channels = {};
3923         struct mlx5e_params *params;
3924         int err = 0;
3925         bool reset;
3926 
3927         mutex_lock(&priv->state_lock);
3928 
3929         params = &priv->channels.params;
3930 
3931         reset = !params->lro_en;
3932         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3933 
3934         new_channels.params = *params;
3935         new_channels.params.sw_mtu = new_mtu;
3936 
3937         if (params->xdp_prog &&
3938             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3939                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3940                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3941                 err = -EINVAL;
3942                 goto out;
3943         }
3944 
3945         if (priv->xsk.refcnt &&
3946             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3947                                     &new_channels.params, priv->mdev)) {
3948                 err = -EINVAL;
3949                 goto out;
3950         }
3951 
3952         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3953                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3954                                                               &new_channels.params,
3955                                                               NULL);
3956                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3957                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3958 
3959                 /* If XSK is active, XSK RQs are linear. */
3960                 is_linear |= priv->xsk.refcnt;
3961 
3962                 /* Always reset in linear mode - hw_mtu is used in data path. */
3963                 reset = reset && (is_linear || (ppw_old != ppw_new));
3964         }
3965 
3966         if (!reset) {
3967                 params->sw_mtu = new_mtu;
3968                 if (set_mtu_cb)
3969                         set_mtu_cb(priv);
3970                 netdev->mtu = params->sw_mtu;
3971                 goto out;
3972         }
3973 
3974         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3975         if (err)
3976                 goto out;
3977 
3978         netdev->mtu = new_channels.params.sw_mtu;
3979 
3980 out:
3981         mutex_unlock(&priv->state_lock);
3982         return err;
3983 }
3984 
3985 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3986 {
3987         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3988 }
3989 
3990 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3991 {
3992         struct hwtstamp_config config;
3993         int err;
3994 
3995         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3996             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3997                 return -EOPNOTSUPP;
3998 
3999         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4000                 return -EFAULT;
4001 
4002         /* TX HW timestamp */
4003         switch (config.tx_type) {
4004         case HWTSTAMP_TX_OFF:
4005         case HWTSTAMP_TX_ON:
4006                 break;
4007         default:
4008                 return -ERANGE;
4009         }
4010 
4011         mutex_lock(&priv->state_lock);
4012         /* RX HW timestamp */
4013         switch (config.rx_filter) {
4014         case HWTSTAMP_FILTER_NONE:
4015                 /* Reset CQE compression to Admin default */
4016                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
4017                 break;
4018         case HWTSTAMP_FILTER_ALL:
4019         case HWTSTAMP_FILTER_SOME:
4020         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4021         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4022         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4023         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4024         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4025         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4026         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4027         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4028         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4029         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4030         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4031         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4032         case HWTSTAMP_FILTER_NTP_ALL:
4033                 /* Disable CQE compression */
4034                 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4035                         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4036                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4037                 if (err) {
4038                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4039                         mutex_unlock(&priv->state_lock);
4040                         return err;
4041                 }
4042                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4043                 break;
4044         default:
4045                 mutex_unlock(&priv->state_lock);
4046                 return -ERANGE;
4047         }
4048 
4049         memcpy(&priv->tstamp, &config, sizeof(config));
4050         mutex_unlock(&priv->state_lock);
4051 
4052         /* might need to fix some features */
4053         netdev_update_features(priv->netdev);
4054 
4055         return copy_to_user(ifr->ifr_data, &config,
4056                             sizeof(config)) ? -EFAULT : 0;
4057 }
4058 
4059 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4060 {
4061         struct hwtstamp_config *cfg = &priv->tstamp;
4062 
4063         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4064                 return -EOPNOTSUPP;
4065 
4066         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4067 }
4068 
4069 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4070 {
4071         struct mlx5e_priv *priv = netdev_priv(dev);
4072 
4073         switch (cmd) {
4074         case SIOCSHWTSTAMP:
4075                 return mlx5e_hwstamp_set(priv, ifr);
4076         case SIOCGHWTSTAMP:
4077                 return mlx5e_hwstamp_get(priv, ifr);
4078         default:
4079                 return -EOPNOTSUPP;
4080         }
4081 }
4082 
4083 #ifdef CONFIG_MLX5_ESWITCH
4084 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4085 {
4086         struct mlx5e_priv *priv = netdev_priv(dev);
4087         struct mlx5_core_dev *mdev = priv->mdev;
4088 
4089         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4090 }
4091 
4092 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4093                              __be16 vlan_proto)
4094 {
4095         struct mlx5e_priv *priv = netdev_priv(dev);
4096         struct mlx5_core_dev *mdev = priv->mdev;
4097 
4098         if (vlan_proto != htons(ETH_P_8021Q))
4099                 return -EPROTONOSUPPORT;
4100 
4101         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4102                                            vlan, qos);
4103 }
4104 
4105 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4106 {
4107         struct mlx5e_priv *priv = netdev_priv(dev);
4108         struct mlx5_core_dev *mdev = priv->mdev;
4109 
4110         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4111 }
4112 
4113 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4114 {
4115         struct mlx5e_priv *priv = netdev_priv(dev);
4116         struct mlx5_core_dev *mdev = priv->mdev;
4117 
4118         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4119 }
4120 
4121 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4122                       int max_tx_rate)
4123 {
4124         struct mlx5e_priv *priv = netdev_priv(dev);
4125         struct mlx5_core_dev *mdev = priv->mdev;
4126 
4127         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4128                                            max_tx_rate, min_tx_rate);
4129 }
4130 
4131 static int mlx5_vport_link2ifla(u8 esw_link)
4132 {
4133         switch (esw_link) {
4134         case MLX5_VPORT_ADMIN_STATE_DOWN:
4135                 return IFLA_VF_LINK_STATE_DISABLE;
4136         case MLX5_VPORT_ADMIN_STATE_UP:
4137                 return IFLA_VF_LINK_STATE_ENABLE;
4138         }
4139         return IFLA_VF_LINK_STATE_AUTO;
4140 }
4141 
4142 static int mlx5_ifla_link2vport(u8 ifla_link)
4143 {
4144         switch (ifla_link) {
4145         case IFLA_VF_LINK_STATE_DISABLE:
4146                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4147         case IFLA_VF_LINK_STATE_ENABLE:
4148                 return MLX5_VPORT_ADMIN_STATE_UP;
4149         }
4150         return MLX5_VPORT_ADMIN_STATE_AUTO;
4151 }
4152 
4153 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4154                                    int link_state)
4155 {
4156         struct mlx5e_priv *priv = netdev_priv(dev);
4157         struct mlx5_core_dev *mdev = priv->mdev;
4158 
4159         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4160                                             mlx5_ifla_link2vport(link_state));
4161 }
4162 
4163 int mlx5e_get_vf_config(struct net_device *dev,
4164                         int vf, struct ifla_vf_info *ivi)
4165 {
4166         struct mlx5e_priv *priv = netdev_priv(dev);
4167         struct mlx5_core_dev *mdev = priv->mdev;
4168         int err;
4169 
4170         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4171         if (err)
4172                 return err;
4173         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4174         return 0;
4175 }
4176 
4177 int mlx5e_get_vf_stats(struct net_device *dev,
4178                        int vf, struct ifla_vf_stats *vf_stats)
4179 {
4180         struct mlx5e_priv *priv = netdev_priv(dev);
4181         struct mlx5_core_dev *mdev = priv->mdev;
4182 
4183         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4184                                             vf_stats);
4185 }
4186 #endif
4187 
4188 struct mlx5e_vxlan_work {
4189         struct work_struct      work;
4190         struct mlx5e_priv       *priv;
4191         u16                     port;
4192 };
4193 
4194 static void mlx5e_vxlan_add_work(struct work_struct *work)
4195 {
4196         struct mlx5e_vxlan_work *vxlan_work =
4197                 container_of(work, struct mlx5e_vxlan_work, work);
4198         struct mlx5e_priv *priv = vxlan_work->priv;
4199         u16 port = vxlan_work->port;
4200 
4201         mutex_lock(&priv->state_lock);
4202         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4203         mutex_unlock(&priv->state_lock);
4204 
4205         kfree(vxlan_work);
4206 }
4207 
4208 static void mlx5e_vxlan_del_work(struct work_struct *work)
4209 {
4210         struct mlx5e_vxlan_work *vxlan_work =
4211                 container_of(work, struct mlx5e_vxlan_work, work);
4212         struct mlx5e_priv *priv         = vxlan_work->priv;
4213         u16 port = vxlan_work->port;
4214 
4215         mutex_lock(&priv->state_lock);
4216         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4217         mutex_unlock(&priv->state_lock);
4218         kfree(vxlan_work);
4219 }
4220 
4221 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4222 {
4223         struct mlx5e_vxlan_work *vxlan_work;
4224 
4225         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4226         if (!vxlan_work)
4227                 return;
4228 
4229         if (add)
4230                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4231         else
4232                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4233 
4234         vxlan_work->priv = priv;
4235         vxlan_work->port = port;
4236         queue_work(priv->wq, &vxlan_work->work);
4237 }
4238 
4239 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4240 {
4241         struct mlx5e_priv *priv = netdev_priv(netdev);
4242 
4243         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4244                 return;
4245 
4246         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4247                 return;
4248 
4249         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4250 }
4251 
4252 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4253 {
4254         struct mlx5e_priv *priv = netdev_priv(netdev);
4255 
4256         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4257                 return;
4258 
4259         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4260                 return;
4261 
4262         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4263 }
4264 
4265 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4266                                                      struct sk_buff *skb,
4267                                                      netdev_features_t features)
4268 {
4269         unsigned int offset = 0;
4270         struct udphdr *udph;
4271         u8 proto;
4272         u16 port;
4273 
4274         switch (vlan_get_protocol(skb)) {
4275         case htons(ETH_P_IP):
4276                 proto = ip_hdr(skb)->protocol;
4277                 break;
4278         case htons(ETH_P_IPV6):
4279                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4280                 break;
4281         default:
4282                 goto out;
4283         }
4284 
4285         switch (proto) {
4286         case IPPROTO_GRE:
4287                 return features;
4288         case IPPROTO_IPIP:
4289         case IPPROTO_IPV6:
4290                 if (mlx5e_tunnel_proto_supported(priv->mdev, IPPROTO_IPIP))
4291                         return features;
4292                 break;
4293         case IPPROTO_UDP:
4294                 udph = udp_hdr(skb);
4295                 port = be16_to_cpu(udph->dest);
4296 
4297                 /* Verify if UDP port is being offloaded by HW */
4298                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4299                         return features;
4300 
4301 #if IS_ENABLED(CONFIG_GENEVE)
4302                 /* Support Geneve offload for default UDP port */
4303                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4304                         return features;
4305 #endif
4306         }
4307 
4308 out:
4309         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4310         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4311 }
4312 
4313 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4314                                        struct net_device *netdev,
4315                                        netdev_features_t features)
4316 {
4317         struct mlx5e_priv *priv = netdev_priv(netdev);
4318 
4319         features = vlan_features_check(skb, features);
4320         features = vxlan_features_check(skb, features);
4321 
4322 #ifdef CONFIG_MLX5_EN_IPSEC
4323         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4324                 return features;
4325 #endif
4326 
4327         /* Validate if the tunneled packet is being offloaded by HW */
4328         if (skb->encapsulation &&
4329             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4330                 return mlx5e_tunnel_features_check(priv, skb, features);
4331 
4332         return features;
4333 }
4334 
4335 static void mlx5e_tx_timeout_work(struct work_struct *work)
4336 {
4337         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4338                                                tx_timeout_work);
4339         bool report_failed = false;
4340         int err;
4341         int i;
4342 
4343         rtnl_lock();
4344         mutex_lock(&priv->state_lock);
4345 
4346         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4347                 goto unlock;
4348 
4349         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4350                 struct netdev_queue *dev_queue =
4351                         netdev_get_tx_queue(priv->netdev, i);
4352                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4353 
4354                 if (!netif_xmit_stopped(dev_queue))
4355                         continue;
4356 
4357                 if (mlx5e_reporter_tx_timeout(sq))
4358                         report_failed = true;
4359         }
4360 
4361         if (!report_failed)
4362                 goto unlock;
4363 
4364         err = mlx5e_safe_reopen_channels(priv);
4365         if (err)
4366                 netdev_err(priv->netdev,
4367                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4368                            err);
4369 
4370 unlock:
4371         mutex_unlock(&priv->state_lock);
4372         rtnl_unlock();
4373 }
4374 
4375 static void mlx5e_tx_timeout(struct net_device *dev)
4376 {
4377         struct mlx5e_priv *priv = netdev_priv(dev);
4378 
4379         netdev_err(dev, "TX timeout detected\n");
4380         queue_work(priv->wq, &priv->tx_timeout_work);
4381 }
4382 
4383 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4384 {
4385         struct net_device *netdev = priv->netdev;
4386         struct mlx5e_channels new_channels = {};
4387 
4388         if (priv->channels.params.lro_en) {
4389                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4390                 return -EINVAL;
4391         }
4392 
4393         if (MLX5_IPSEC_DEV(priv->mdev)) {
4394                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4395                 return -EINVAL;
4396         }
4397 
4398         new_channels.params = priv->channels.params;
4399         new_channels.params.xdp_prog = prog;
4400 
4401         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4402          * the XDP program.
4403          */
4404         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4405                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4406                             new_channels.params.sw_mtu,
4407                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4408                 return -EINVAL;
4409         }
4410 
4411         return 0;
4412 }
4413 
4414 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4415 {
4416         struct mlx5e_priv *priv = netdev_priv(netdev);
4417         struct bpf_prog *old_prog;
4418         bool reset, was_opened;
4419         int err = 0;
4420         int i;
4421 
4422         mutex_lock(&priv->state_lock);
4423 
4424         if (prog) {
4425                 err = mlx5e_xdp_allowed(priv, prog);
4426                 if (err)
4427                         goto unlock;
4428         }
4429 
4430         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4431         /* no need for full reset when exchanging programs */
4432         reset = (!priv->channels.params.xdp_prog || !prog);
4433 
4434         if (was_opened && !reset) {
4435                 /* num_channels is invariant here, so we can take the
4436                  * batched reference right upfront.
4437                  */
4438                 prog = bpf_prog_add(prog, priv->channels.num);
4439                 if (IS_ERR(prog)) {
4440                         err = PTR_ERR(prog);
4441                         goto unlock;
4442                 }
4443         }
4444 
4445         if (was_opened && reset) {
4446                 struct mlx5e_channels new_channels = {};
4447 
4448                 new_channels.params = priv->channels.params;
4449                 new_channels.params.xdp_prog = prog;
4450                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4451                 old_prog = priv->channels.params.xdp_prog;
4452 
4453                 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
4454                 if (err)
4455                         goto unlock;
4456         } else {
4457                 /* exchange programs, extra prog reference we got from caller
4458                  * as long as we don't fail from this point onwards.
4459                  */
4460                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4461         }
4462 
4463         if (old_prog)
4464                 bpf_prog_put(old_prog);
4465 
4466         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4467                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4468 
4469         if (!was_opened || reset)
4470                 goto unlock;
4471 
4472         /* exchanging programs w/o reset, we update ref counts on behalf
4473          * of the channels RQs here.
4474          */
4475         for (i = 0; i < priv->channels.num; i++) {
4476                 struct mlx5e_channel *c = priv->channels.c[i];
4477                 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4478 
4479                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4480                 if (xsk_open)
4481                         clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4482                 napi_synchronize(&c->napi);
4483                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4484 
4485                 old_prog = xchg(&c->rq.xdp_prog, prog);
4486                 if (old_prog)
4487                         bpf_prog_put(old_prog);
4488 
4489                 if (xsk_open) {
4490                         old_prog = xchg(&c->xskrq.xdp_prog, prog);
4491                         if (old_prog)
4492                                 bpf_prog_put(old_prog);
4493                 }
4494 
4495                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4496                 if (xsk_open)
4497                         set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4498                 /* napi_schedule in case we have missed anything */
4499                 napi_schedule(&c->napi);
4500         }
4501 
4502 unlock:
4503         mutex_unlock(&priv->state_lock);
4504         return err;
4505 }
4506 
4507 static u32 mlx5e_xdp_query(struct net_device *dev)
4508 {
4509         struct mlx5e_priv *priv = netdev_priv(dev);
4510         const struct bpf_prog *xdp_prog;
4511         u32 prog_id = 0;
4512 
4513         mutex_lock(&priv->state_lock);
4514         xdp_prog = priv->channels.params.xdp_prog;
4515         if (xdp_prog)
4516                 prog_id = xdp_prog->aux->id;
4517         mutex_unlock(&priv->state_lock);
4518 
4519         return prog_id;
4520 }
4521 
4522 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4523 {
4524         switch (xdp->command) {
4525         case XDP_SETUP_PROG:
4526                 return mlx5e_xdp_set(dev, xdp->prog);
4527         case XDP_QUERY_PROG:
4528                 xdp->prog_id = mlx5e_xdp_query(dev);
4529                 return 0;
4530         case XDP_SETUP_XSK_UMEM:
4531                 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4532                                             xdp->xsk.queue_id);
4533         default:
4534                 return -EINVAL;
4535         }
4536 }
4537 
4538 #ifdef CONFIG_MLX5_ESWITCH
4539 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4540                                 struct net_device *dev, u32 filter_mask,
4541                                 int nlflags)
4542 {
4543         struct mlx5e_priv *priv = netdev_priv(dev);
4544         struct mlx5_core_dev *mdev = priv->mdev;
4545         u8 mode, setting;
4546         int err;
4547 
4548         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4549         if (err)
4550                 return err;
4551         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4552         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4553                                        mode,
4554                                        0, 0, nlflags, filter_mask, NULL);
4555 }
4556 
4557 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4558                                 u16 flags, struct netlink_ext_ack *extack)
4559 {
4560         struct mlx5e_priv *priv = netdev_priv(dev);
4561         struct mlx5_core_dev *mdev = priv->mdev;
4562         struct nlattr *attr, *br_spec;
4563         u16 mode = BRIDGE_MODE_UNDEF;
4564         u8 setting;
4565         int rem;
4566 
4567         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4568         if (!br_spec)
4569                 return -EINVAL;
4570 
4571         nla_for_each_nested(attr, br_spec, rem) {
4572                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4573                         continue;
4574 
4575                 if (nla_len(attr) < sizeof(mode))
4576                         return -EINVAL;
4577 
4578                 mode = nla_get_u16(attr);
4579                 if (mode > BRIDGE_MODE_VEPA)
4580                         return -EINVAL;
4581 
4582                 break;
4583         }
4584 
4585         if (mode == BRIDGE_MODE_UNDEF)
4586                 return -EINVAL;
4587 
4588         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4589         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4590 }
4591 #endif
4592 
4593 const struct net_device_ops mlx5e_netdev_ops = {
4594         .ndo_open                = mlx5e_open,
4595         .ndo_stop                = mlx5e_close,
4596         .ndo_start_xmit          = mlx5e_xmit,
4597         .ndo_setup_tc            = mlx5e_setup_tc,
4598         .ndo_select_queue        = mlx5e_select_queue,
4599         .ndo_get_stats64         = mlx5e_get_stats,
4600         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4601         .ndo_set_mac_address     = mlx5e_set_mac,
4602         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4603         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4604         .ndo_set_features        = mlx5e_set_features,
4605         .ndo_fix_features        = mlx5e_fix_features,
4606         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4607         .ndo_do_ioctl            = mlx5e_ioctl,
4608         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4609         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4610         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4611         .ndo_features_check      = mlx5e_features_check,
4612         .ndo_tx_timeout          = mlx5e_tx_timeout,
4613         .ndo_bpf                 = mlx5e_xdp,
4614         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4615         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4616 #ifdef CONFIG_MLX5_EN_ARFS
4617         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4618 #endif
4619 #ifdef CONFIG_MLX5_ESWITCH
4620         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4621         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4622 
4623         /* SRIOV E-Switch NDOs */
4624         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4625         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4626         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4627         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4628         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4629         .ndo_get_vf_config       = mlx5e_get_vf_config,
4630         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4631         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4632 #endif
4633 };
4634 
4635 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4636 {
4637         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4638                 return -EOPNOTSUPP;
4639         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4640             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4641             !MLX5_CAP_ETH(mdev, csum_cap) ||
4642             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4643             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4644             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4645             MLX5_CAP_FLOWTABLE(mdev,
4646                                flow_table_properties_nic_receive.max_ft_level)
4647                                < 3) {
4648                 mlx5_core_warn(mdev,
4649                                "Not creating net device, some required device capabilities are missing\n");
4650                 return -EOPNOTSUPP;
4651         }
4652         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4653                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4654         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4655                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4656 
4657         return 0;
4658 }
4659 
4660 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4661                                    int num_channels)
4662 {
4663         int i;
4664 
4665         for (i = 0; i < len; i++)
4666                 indirection_rqt[i] = i % num_channels;
4667 }
4668 
4669 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4670 {
4671         u32 link_speed = 0;
4672         u32 pci_bw = 0;
4673 
4674         mlx5e_port_max_linkspeed(mdev, &link_speed);
4675         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4676         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4677                            link_speed, pci_bw);
4678 
4679 #define MLX5E_SLOW_PCI_RATIO (2)
4680 
4681         return link_speed && pci_bw &&
4682                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4683 }
4684 
4685 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4686 {
4687         struct dim_cq_moder moder;
4688 
4689         moder.cq_period_mode = cq_period_mode;
4690         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4691         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4692         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4693                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4694 
4695         return moder;
4696 }
4697 
4698 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4699 {
4700         struct dim_cq_moder moder;
4701 
4702         moder.cq_period_mode = cq_period_mode;
4703         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4704         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4705         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4706                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4707 
4708         return moder;
4709 }
4710 
4711 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4712 {
4713         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4714                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4715                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4716 }
4717 
4718 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4719 {
4720         if (params->tx_dim_enabled) {
4721                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4722 
4723                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4724         } else {
4725                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4726         }
4727 
4728         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4729                         params->tx_cq_moderation.cq_period_mode ==
4730                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4731 }
4732 
4733 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4734 {
4735         if (params->rx_dim_enabled) {
4736                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4737 
4738                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4739         } else {
4740                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4741         }
4742 
4743         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4744                         params->rx_cq_moderation.cq_period_mode ==
4745                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4746 }
4747 
4748 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4749 {
4750         int i;
4751 
4752         /* The supported periods are organized in ascending order */
4753         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4754                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4755                         break;
4756 
4757         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4758 }
4759 
4760 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4761                            struct mlx5e_params *params)
4762 {
4763         /* Prefer Striding RQ, unless any of the following holds:
4764          * - Striding RQ configuration is not possible/supported.
4765          * - Slow PCI heuristic.
4766          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4767          *
4768          * No XSK params: checking the availability of striding RQ in general.
4769          */
4770         if (!slow_pci_heuristic(mdev) &&
4771             mlx5e_striding_rq_possible(mdev, params) &&
4772             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4773              !mlx5e_rx_is_linear_skb(params, NULL)))
4774                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4775         mlx5e_set_rq_type(mdev, params);
4776         mlx5e_init_rq_type_params(mdev, params);
4777 }
4778 
4779 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4780                             u16 num_channels)
4781 {
4782         enum mlx5e_traffic_types tt;
4783 
4784         rss_params->hfunc = ETH_RSS_HASH_TOP;
4785         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4786                             sizeof(rss_params->toeplitz_hash_key));
4787         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4788                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4789         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4790                 rss_params->rx_hash_fields[tt] =
4791                         tirc_default_config[tt].rx_hash_fields;
4792 }
4793 
4794 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4795                             struct mlx5e_xsk *xsk,
4796                             struct mlx5e_rss_params *rss_params,
4797                             struct mlx5e_params *params,
4798                             u16 max_channels, u16 mtu)
4799 {
4800         u8 rx_cq_period_mode;
4801 
4802         params->sw_mtu = mtu;
4803         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4804         params->num_channels = max_channels;
4805         params->num_tc       = 1;
4806 
4807         /* SQ */
4808         params->log_sq_size = is_kdump_kernel() ?
4809                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4810                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4811 
4812         /* XDP SQ */
4813         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4814                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4815 
4816         /* set CQE compression */
4817         params->rx_cqe_compress_def = false;
4818         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4819             MLX5_CAP_GEN(mdev, vport_group_manager))
4820                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4821 
4822         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4823         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4824 
4825         /* RQ */
4826         mlx5e_build_rq_params(mdev, params);
4827 
4828         /* HW LRO */
4829 
4830         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4831         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4832                 /* No XSK params: checking the availability of striding RQ in general. */
4833                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4834                         params->lro_en = !slow_pci_heuristic(mdev);
4835         }
4836         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4837 
4838         /* CQ moderation params */
4839         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4840                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4841                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4842         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4843         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4844         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4845         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4846 
4847         /* TX inline */
4848         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4849 
4850         /* RSS */
4851         mlx5e_build_rss_params(rss_params, params->num_channels);
4852         params->tunneled_offload_en =
4853                 mlx5e_tunnel_inner_ft_supported(mdev);
4854 
4855         /* AF_XDP */
4856         params->xsk = xsk;
4857 }
4858 
4859 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4860 {
4861         struct mlx5e_priv *priv = netdev_priv(netdev);
4862 
4863         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4864         if (is_zero_ether_addr(netdev->dev_addr) &&
4865             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4866                 eth_hw_addr_random(netdev);
4867                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4868         }
4869 }
4870 
4871 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4872 {
4873         struct mlx5e_priv *priv = netdev_priv(netdev);
4874         struct mlx5_core_dev *mdev = priv->mdev;
4875         bool fcs_supported;
4876         bool fcs_enabled;
4877 
4878         SET_NETDEV_DEV(netdev, mdev->device);
4879 
4880         netdev->netdev_ops = &mlx5e_netdev_ops;
4881 
4882 #ifdef CONFIG_MLX5_CORE_EN_DCB
4883         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4884                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4885 #endif
4886 
4887         netdev->watchdog_timeo    = 15 * HZ;
4888 
4889         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4890 
4891         netdev->vlan_features    |= NETIF_F_SG;
4892         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4893         netdev->vlan_features    |= NETIF_F_GRO;
4894         netdev->vlan_features    |= NETIF_F_TSO;
4895         netdev->vlan_features    |= NETIF_F_TSO6;
4896         netdev->vlan_features    |= NETIF_F_RXCSUM;
4897         netdev->vlan_features    |= NETIF_F_RXHASH;
4898 
4899         netdev->mpls_features    |= NETIF_F_SG;
4900         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4901         netdev->mpls_features    |= NETIF_F_TSO;
4902         netdev->mpls_features    |= NETIF_F_TSO6;
4903 
4904         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4905         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4906 
4907         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4908             mlx5e_check_fragmented_striding_rq_cap(mdev))
4909                 netdev->vlan_features    |= NETIF_F_LRO;
4910 
4911         netdev->hw_features       = netdev->vlan_features;
4912         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4913         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4914         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4915         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4916 
4917         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4918             mlx5e_any_tunnel_proto_supported(mdev)) {
4919                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4920                 netdev->hw_enc_features |= NETIF_F_TSO;
4921                 netdev->hw_enc_features |= NETIF_F_TSO6;
4922                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4923         }
4924 
4925         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4926                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4927                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4928                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4929                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4930                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4931         }
4932 
4933         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_GRE)) {
4934                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4935                                            NETIF_F_GSO_GRE_CSUM;
4936                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4937                                            NETIF_F_GSO_GRE_CSUM;
4938                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4939                                                 NETIF_F_GSO_GRE_CSUM;
4940         }
4941 
4942         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_IPIP)) {
4943                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4944                                        NETIF_F_GSO_IPXIP6;
4945                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4946                                            NETIF_F_GSO_IPXIP6;
4947                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4948                                                 NETIF_F_GSO_IPXIP6;
4949         }
4950 
4951         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4952         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4953         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4954         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4955 
4956         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4957 
4958         if (fcs_supported)
4959                 netdev->hw_features |= NETIF_F_RXALL;
4960 
4961         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4962                 netdev->hw_features |= NETIF_F_RXFCS;
4963 
4964         netdev->features          = netdev->hw_features;
4965         if (!priv->channels.params.lro_en)
4966                 netdev->features  &= ~NETIF_F_LRO;
4967 
4968         if (fcs_enabled)
4969                 netdev->features  &= ~NETIF_F_RXALL;
4970 
4971         if (!priv->channels.params.scatter_fcs_en)
4972                 netdev->features  &= ~NETIF_F_RXFCS;
4973 
4974         /* prefere CQE compression over rxhash */
4975         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4976                 netdev->features &= ~NETIF_F_RXHASH;
4977 
4978 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4979         if (FT_CAP(flow_modify_en) &&
4980             FT_CAP(modify_root) &&
4981             FT_CAP(identified_miss_table_mode) &&
4982             FT_CAP(flow_table_modify)) {
4983 #ifdef CONFIG_MLX5_ESWITCH
4984                 netdev->hw_features      |= NETIF_F_HW_TC;
4985 #endif
4986 #ifdef CONFIG_MLX5_EN_ARFS
4987                 netdev->hw_features      |= NETIF_F_NTUPLE;
4988 #endif
4989         }
4990 
4991         netdev->features         |= NETIF_F_HIGHDMA;
4992         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4993 
4994         netdev->priv_flags       |= IFF_UNICAST_FLT;
4995 
4996         mlx5e_set_netdev_dev_addr(netdev);
4997         mlx5e_ipsec_build_netdev(priv);
4998         mlx5e_tls_build_netdev(priv);
4999 }
5000 
5001 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
5002 {
5003         struct mlx5_core_dev *mdev = priv->mdev;
5004         int err;
5005 
5006         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
5007         if (err) {
5008                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
5009                 priv->q_counter = 0;
5010         }
5011 
5012         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
5013         if (err) {
5014                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
5015                 priv->drop_rq_q_counter = 0;
5016         }
5017 }
5018 
5019 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
5020 {
5021         if (priv->q_counter)
5022                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
5023 
5024         if (priv->drop_rq_q_counter)
5025                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
5026 }
5027 
5028 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5029                           struct net_device *netdev,
5030                           const struct mlx5e_profile *profile,
5031                           void *ppriv)
5032 {
5033         struct mlx5e_priv *priv = netdev_priv(netdev);
5034         struct mlx5e_rss_params *rss = &priv->rss_params;
5035         int err;
5036 
5037         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
5038         if (err)
5039                 return err;
5040 
5041         mlx5e_build_nic_params(mdev, &priv->xsk, rss, &priv->channels.params,
5042                                priv->max_nch, netdev->mtu);
5043 
5044         mlx5e_timestamp_init(priv);
5045 
5046         err = mlx5e_ipsec_init(priv);
5047         if (err)
5048                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5049         err = mlx5e_tls_init(priv);
5050         if (err)
5051                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5052         mlx5e_build_nic_netdev(netdev);
5053         mlx5e_health_create_reporters(priv);
5054 
5055         return 0;
5056 }
5057 
5058 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5059 {
5060         mlx5e_health_destroy_reporters(priv);
5061         mlx5e_tls_cleanup(priv);
5062         mlx5e_ipsec_cleanup(priv);
5063         mlx5e_netdev_cleanup(priv->netdev, priv);
5064 }
5065 
5066 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5067 {
5068         struct mlx5_core_dev *mdev = priv->mdev;
5069         int err;
5070 
5071         mlx5e_create_q_counters(priv);
5072 
5073         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5074         if (err) {
5075                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5076                 goto err_destroy_q_counters;
5077         }
5078 
5079         err = mlx5e_create_indirect_rqt(priv);
5080         if (err)
5081                 goto err_close_drop_rq;
5082 
5083         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5084         if (err)
5085                 goto err_destroy_indirect_rqts;
5086 
5087         err = mlx5e_create_indirect_tirs(priv, true);
5088         if (err)
5089                 goto err_destroy_direct_rqts;
5090 
5091         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5092         if (err)
5093                 goto err_destroy_indirect_tirs;
5094 
5095         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5096         if (unlikely(err))
5097                 goto err_destroy_direct_tirs;
5098 
5099         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5100         if (unlikely(err))
5101                 goto err_destroy_xsk_rqts;
5102 
5103         err = mlx5e_create_flow_steering(priv);
5104         if (err) {
5105                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5106                 goto err_destroy_xsk_tirs;
5107         }
5108 
5109         err = mlx5e_tc_nic_init(priv);
5110         if (err)
5111                 goto err_destroy_flow_steering;
5112 
5113         return 0;
5114 
5115 err_destroy_flow_steering:
5116         mlx5e_destroy_flow_steering(priv);
5117 err_destroy_xsk_tirs:
5118         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5119 err_destroy_xsk_rqts:
5120         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5121 err_destroy_direct_tirs:
5122         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5123 err_destroy_indirect_tirs:
5124         mlx5e_destroy_indirect_tirs(priv);
5125 err_destroy_direct_rqts:
5126         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5127 err_destroy_indirect_rqts:
5128         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5129 err_close_drop_rq:
5130         mlx5e_close_drop_rq(&priv->drop_rq);
5131 err_destroy_q_counters:
5132         mlx5e_destroy_q_counters(priv);
5133         return err;
5134 }
5135 
5136 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5137 {
5138         mlx5e_tc_nic_cleanup(priv);
5139         mlx5e_destroy_flow_steering(priv);
5140         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5141         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5142         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5143         mlx5e_destroy_indirect_tirs(priv);
5144         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5145         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5146         mlx5e_close_drop_rq(&priv->drop_rq);
5147         mlx5e_destroy_q_counters(priv);
5148 }
5149 
5150 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5151 {
5152         int err;
5153 
5154         err = mlx5e_create_tises(priv);
5155         if (err) {
5156                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5157                 return err;
5158         }
5159 
5160 #ifdef CONFIG_MLX5_CORE_EN_DCB
5161         mlx5e_dcbnl_initialize(priv);
5162 #endif
5163         return 0;
5164 }
5165 
5166 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5167 {
5168         struct net_device *netdev = priv->netdev;
5169         struct mlx5_core_dev *mdev = priv->mdev;
5170 
5171         mlx5e_init_l2_addr(priv);
5172 
5173         /* Marking the link as currently not needed by the Driver */
5174         if (!netif_running(netdev))
5175                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5176 
5177         mlx5e_set_netdev_mtu_boundaries(priv);
5178         mlx5e_set_dev_port_mtu(priv);
5179 
5180         mlx5_lag_add(mdev, netdev);
5181 
5182         mlx5e_enable_async_events(priv);
5183         if (mlx5e_monitor_counter_supported(priv))
5184                 mlx5e_monitor_counter_init(priv);
5185 
5186         mlx5e_hv_vhca_stats_create(priv);
5187         if (netdev->reg_state != NETREG_REGISTERED)
5188                 return;
5189 #ifdef CONFIG_MLX5_CORE_EN_DCB
5190         mlx5e_dcbnl_init_app(priv);
5191 #endif
5192 
5193         queue_work(priv->wq, &priv->set_rx_mode_work);
5194 
5195         rtnl_lock();
5196         if (netif_running(netdev))
5197                 mlx5e_open(netdev);
5198         netif_device_attach(netdev);
5199         rtnl_unlock();
5200 }
5201 
5202 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5203 {
5204         struct mlx5_core_dev *mdev = priv->mdev;
5205 
5206 #ifdef CONFIG_MLX5_CORE_EN_DCB
5207         if (priv->netdev->reg_state == NETREG_REGISTERED)
5208                 mlx5e_dcbnl_delete_app(priv);
5209 #endif
5210 
5211         rtnl_lock();
5212         if (netif_running(priv->netdev))
5213                 mlx5e_close(priv->netdev);
5214         netif_device_detach(priv->netdev);
5215         rtnl_unlock();
5216 
5217         queue_work(priv->wq, &priv->set_rx_mode_work);
5218 
5219         mlx5e_hv_vhca_stats_destroy(priv);
5220         if (mlx5e_monitor_counter_supported(priv))
5221                 mlx5e_monitor_counter_cleanup(priv);
5222 
5223         mlx5e_disable_async_events(priv);
5224         mlx5_lag_remove(mdev);
5225 }
5226 
5227 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5228 {
5229         return mlx5e_refresh_tirs(priv, false);
5230 }
5231 
5232 static const struct mlx5e_profile mlx5e_nic_profile = {
5233         .init              = mlx5e_nic_init,
5234         .cleanup           = mlx5e_nic_cleanup,
5235         .init_rx           = mlx5e_init_nic_rx,
5236         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5237         .init_tx           = mlx5e_init_nic_tx,
5238         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5239         .enable            = mlx5e_nic_enable,
5240         .disable           = mlx5e_nic_disable,
5241         .update_rx         = mlx5e_update_nic_rx,
5242         .update_stats      = mlx5e_update_ndo_stats,
5243         .update_carrier    = mlx5e_update_carrier,
5244         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
5245         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5246         .max_tc            = MLX5E_MAX_NUM_TC,
5247         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5248 };
5249 
5250 /* mlx5e generic netdev management API (move to en_common.c) */
5251 
5252 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5253 int mlx5e_netdev_init(struct net_device *netdev,
5254                       struct mlx5e_priv *priv,
5255                       struct mlx5_core_dev *mdev,
5256                       const struct mlx5e_profile *profile,
5257                       void *ppriv)
5258 {
5259         /* priv init */
5260         priv->mdev        = mdev;
5261         priv->netdev      = netdev;
5262         priv->profile     = profile;
5263         priv->ppriv       = ppriv;
5264         priv->msglevel    = MLX5E_MSG_LEVEL;
5265         priv->max_nch     = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5266         priv->max_opened_tc = 1;
5267 
5268         mutex_init(&priv->state_lock);
5269         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5270         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5271         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5272         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5273 
5274         priv->wq = create_singlethread_workqueue("mlx5e");
5275         if (!priv->wq)
5276                 return -ENOMEM;
5277 
5278         /* netdev init */
5279         netif_carrier_off(netdev);
5280 
5281 #ifdef CONFIG_MLX5_EN_ARFS
5282         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5283 #endif
5284 
5285         return 0;
5286 }
5287 
5288 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5289 {
5290         destroy_workqueue(priv->wq);
5291 }
5292 
5293 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5294                                        const struct mlx5e_profile *profile,
5295                                        int nch,
5296                                        void *ppriv)
5297 {
5298         struct net_device *netdev;
5299         int err;
5300 
5301         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5302                                     nch * profile->max_tc,
5303                                     nch * profile->rq_groups);
5304         if (!netdev) {
5305                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5306                 return NULL;
5307         }
5308 
5309         err = profile->init(mdev, netdev, profile, ppriv);
5310         if (err) {
5311                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5312                 goto err_free_netdev;
5313         }
5314 
5315         return netdev;
5316 
5317 err_free_netdev:
5318         free_netdev(netdev);
5319 
5320         return NULL;
5321 }
5322 
5323 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5324 {
5325         const struct mlx5e_profile *profile;
5326         int max_nch;
5327         int err;
5328 
5329         profile = priv->profile;
5330         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5331 
5332         /* max number of channels may have changed */
5333         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5334         if (priv->channels.params.num_channels > max_nch) {
5335                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5336                 /* Reducing the number of channels - RXFH has to be reset. */
5337                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5338                 priv->channels.params.num_channels = max_nch;
5339                 mlx5e_num_channels_changed(priv);
5340         }
5341 
5342         err = profile->init_tx(priv);
5343         if (err)
5344                 goto out;
5345 
5346         err = profile->init_rx(priv);
5347         if (err)
5348                 goto err_cleanup_tx;
5349 
5350         if (profile->enable)
5351                 profile->enable(priv);
5352 
5353         return 0;
5354 
5355 err_cleanup_tx:
5356         profile->cleanup_tx(priv);
5357 
5358 out:
5359         return err;
5360 }
5361 
5362 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5363 {
5364         const struct mlx5e_profile *profile = priv->profile;
5365 
5366         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5367 
5368         if (profile->disable)
5369                 profile->disable(priv);
5370         flush_workqueue(priv->wq);
5371 
5372         profile->cleanup_rx(priv);
5373         profile->cleanup_tx(priv);
5374         cancel_work_sync(&priv->update_stats_work);
5375 }
5376 
5377 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5378 {
5379         const struct mlx5e_profile *profile = priv->profile;
5380         struct net_device *netdev = priv->netdev;
5381 
5382         if (profile->cleanup)
5383                 profile->cleanup(priv);
5384         free_netdev(netdev);
5385 }
5386 
5387 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5388  * hardware contexts and to connect it to the current netdev.
5389  */
5390 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5391 {
5392         struct mlx5e_priv *priv = vpriv;
5393         struct net_device *netdev = priv->netdev;
5394         int err;
5395 
5396         if (netif_device_present(netdev))
5397                 return 0;
5398 
5399         err = mlx5e_create_mdev_resources(mdev);
5400         if (err)
5401                 return err;
5402 
5403         err = mlx5e_attach_netdev(priv);
5404         if (err) {
5405                 mlx5e_destroy_mdev_resources(mdev);
5406                 return err;
5407         }
5408 
5409         return 0;
5410 }
5411 
5412 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5413 {
5414         struct mlx5e_priv *priv = vpriv;
5415         struct net_device *netdev = priv->netdev;
5416 
5417 #ifdef CONFIG_MLX5_ESWITCH
5418         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5419                 return;
5420 #endif
5421 
5422         if (!netif_device_present(netdev))
5423                 return;
5424 
5425         mlx5e_detach_netdev(priv);
5426         mlx5e_destroy_mdev_resources(mdev);
5427 }
5428 
5429 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5430 {
5431         struct net_device *netdev;
5432         void *priv;
5433         int err;
5434         int nch;
5435 
5436         err = mlx5e_check_required_hca_cap(mdev);
5437         if (err)
5438                 return NULL;
5439 
5440 #ifdef CONFIG_MLX5_ESWITCH
5441         if (MLX5_ESWITCH_MANAGER(mdev) &&
5442             mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5443                 mlx5e_rep_register_vport_reps(mdev);
5444                 return mdev;
5445         }
5446 #endif
5447 
5448         nch = mlx5e_get_max_num_channels(mdev);
5449         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5450         if (!netdev) {
5451                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5452                 return NULL;
5453         }
5454 
5455         priv = netdev_priv(netdev);
5456 
5457         err = mlx5e_attach(mdev, priv);
5458         if (err) {
5459                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5460                 goto err_destroy_netdev;
5461         }
5462 
5463         err = register_netdev(netdev);
5464         if (err) {
5465                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5466                 goto err_detach;
5467         }
5468 
5469 #ifdef CONFIG_MLX5_CORE_EN_DCB
5470         mlx5e_dcbnl_init_app(priv);
5471 #endif
5472         return priv;
5473 
5474 err_detach:
5475         mlx5e_detach(mdev, priv);
5476 err_destroy_netdev:
5477         mlx5e_destroy_netdev(priv);
5478         return NULL;
5479 }
5480 
5481 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5482 {
5483         struct mlx5e_priv *priv;
5484 
5485 #ifdef CONFIG_MLX5_ESWITCH
5486         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5487                 mlx5e_rep_unregister_vport_reps(mdev);
5488                 return;
5489         }
5490 #endif
5491         priv = vpriv;
5492 #ifdef CONFIG_MLX5_CORE_EN_DCB
5493         mlx5e_dcbnl_delete_app(priv);
5494 #endif
5495         unregister_netdev(priv->netdev);
5496         mlx5e_detach(mdev, vpriv);
5497         mlx5e_destroy_netdev(priv);
5498 }
5499 
5500 static struct mlx5_interface mlx5e_interface = {
5501         .add       = mlx5e_add,
5502         .remove    = mlx5e_remove,
5503         .attach    = mlx5e_attach,
5504         .detach    = mlx5e_detach,
5505         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5506 };
5507 
5508 void mlx5e_init(void)
5509 {
5510         mlx5e_ipsec_build_inverse_table();
5511         mlx5e_build_ptys2ethtool_map();
5512         mlx5_register_interface(&mlx5e_interface);
5513 }
5514 
5515 void mlx5e_cleanup(void)
5516 {
5517         mlx5_unregister_interface(&mlx5e_interface);
5518 }

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