root/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

DEFINITIONS

1. mlx5e_flow_get
2. mlx5e_flow_put
3. __flow_flag_set
4. __flow_flag_test_and_set
5. __flow_flag_clear
6. __flow_flag_test
7. mlx5e_is_eswitch_flow
8. mlx5e_is_offloaded_flow
9. hash_mod_hdr_info
10. cmp_mod_hdr_info
11. get_mod_hdr_table
12. mlx5e_mod_hdr_get
13. mlx5e_mod_hdr_put
14. get_flow_name_space
15. mlx5e_attach_mod_hdr
16. mlx5e_detach_mod_hdr
17. mlx5e_hairpin_get_mdev
18. mlx5e_hairpin_create_transport
19. mlx5e_hairpin_destroy_transport
20. mlx5e_hairpin_fill_rqt_rqns
21. mlx5e_hairpin_create_indirect_rqt
22. mlx5e_hairpin_create_indirect_tirs
23. mlx5e_hairpin_destroy_indirect_tirs
24. mlx5e_hairpin_set_ttc_params
25. mlx5e_hairpin_rss_init
26. mlx5e_hairpin_rss_cleanup
27. mlx5e_hairpin_create
28. mlx5e_hairpin_destroy
29. hash_hairpin_info
30. mlx5e_hairpin_get
31. mlx5e_hairpin_put
32. mlx5e_hairpin_get_prio
33. mlx5e_hairpin_flow_add
34. mlx5e_hairpin_flow_del
35. mlx5e_tc_add_nic_flow
36. mlx5e_tc_del_nic_flow
37. mlx5e_tc_offload_fdb_rules
38. mlx5e_tc_unoffload_fdb_rules
39. mlx5e_tc_offload_to_slow_path
40. mlx5e_tc_unoffload_from_slow_path
41. unready_flow_add
42. unready_flow_del
43. add_unready_flow
44. remove_unready_flow
45. mlx5e_tc_add_fdb_flow
46. mlx5_flow_has_geneve_opt
47. mlx5e_tc_del_fdb_flow
48. mlx5e_tc_encap_flows_add
49. mlx5e_tc_encap_flows_del
50. mlx5e_tc_get_counter
51. mlx5e_take_all_encap_flows
52. mlx5e_put_encap_flow_list
53. mlx5e_get_next_valid_encap
54. mlx5e_tc_update_neigh_used_value
55. mlx5e_encap_dealloc
56. mlx5e_encap_put
57. mlx5e_detach_encap
58. __mlx5e_tc_del_fdb_peer_flow
59. mlx5e_tc_del_fdb_peer_flow
60. mlx5e_tc_del_flow
61. parse_tunnel_attr
62. get_match_headers_criteria
63. get_match_headers_value
64. __parse_cls_flower
65. parse_cls_flower
66. set_pedit_val
67. cmp_val_mask
68. offload_pedit_fields
69. mlx5e_flow_namespace_max_modify_action
70. alloc_mod_hdr_actions
71. parse_tc_pedit_action
72. alloc_tc_pedit_action
73. csum_offload_supported
74. is_action_keys_supported
75. modify_header_match_supported
76. actions_match_supported
77. same_hw_devs
78. add_vlan_rewrite_action
79. add_vlan_prio_tag_rewrite_action
80. parse_tc_nic_actions
81. cmp_encap_info
82. hash_encap_info
83. is_merged_eswitch_dev
84. mlx5e_encap_take
85. mlx5e_encap_get
86. dup_tun_info
87. mlx5e_attach_encap
88. parse_tc_vlan_action
89. add_vlan_push_action
90. add_vlan_pop_action
91. mlx5e_is_valid_eswitch_fwd_dev
92. parse_tc_fdb_actions
93. get_flags
94. get_tc_ht
95. is_peer_flow_needed
96. mlx5e_alloc_flow
97. mlx5e_flow_esw_attr_init
98. __mlx5e_add_fdb_flow
99. mlx5e_tc_add_fdb_peer_flow
100. mlx5e_add_fdb_flow
101. mlx5e_add_nic_flow
102. mlx5e_tc_add_flow
103. mlx5e_configure_flower
104. same_flow_direction
105. mlx5e_delete_flower
106. mlx5e_stats_flower
107. apply_police_params
108. scan_tc_matchall_fdb_actions
109. mlx5e_tc_configure_matchall
110. mlx5e_tc_delete_matchall
111. mlx5e_tc_stats_matchall
112. mlx5e_tc_hairpin_update_dead_peer
113. mlx5e_tc_netdev_event
114. mlx5e_tc_nic_init
115. _mlx5e_tc_del_flow
116. mlx5e_tc_nic_cleanup
117. mlx5e_tc_esw_init
118. mlx5e_tc_esw_cleanup
119. mlx5e_tc_num_filters
120. mlx5e_tc_clean_fdb_peer_flows
121. mlx5e_tc_reoffload_flows_work

   1 /*
   2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 
  33 #include <net/flow_dissector.h>
  34 #include <net/sch_generic.h>
  35 #include <net/pkt_cls.h>
  36 #include <net/tc_act/tc_gact.h>
  37 #include <net/tc_act/tc_skbedit.h>
  38 #include <linux/mlx5/fs.h>
  39 #include <linux/mlx5/device.h>
  40 #include <linux/rhashtable.h>
  41 #include <linux/refcount.h>
  42 #include <linux/completion.h>
  43 #include <net/tc_act/tc_mirred.h>
  44 #include <net/tc_act/tc_vlan.h>
  45 #include <net/tc_act/tc_tunnel_key.h>
  46 #include <net/tc_act/tc_pedit.h>
  47 #include <net/tc_act/tc_csum.h>
  48 #include <net/arp.h>
  49 #include <net/ipv6_stubs.h>
  50 #include "en.h"
  51 #include "en_rep.h"
  52 #include "en_tc.h"
  53 #include "eswitch.h"
  54 #include "fs_core.h"
  55 #include "en/port.h"
  56 #include "en/tc_tun.h"
  57 #include "lib/devcom.h"
  58 #include "lib/geneve.h"
  59 #include "diag/en_tc_tracepoint.h"
  60 
  61 struct mlx5_nic_flow_attr {
  62         u32 action;
  63         u32 flow_tag;
  64         struct mlx5_modify_hdr *modify_hdr;
  65         u32 hairpin_tirn;
  66         u8 match_level;
  67         struct mlx5_flow_table  *hairpin_ft;
  68         struct mlx5_fc          *counter;
  69 };
  70 
  71 #define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
  72 
  73 enum {
  74         MLX5E_TC_FLOW_FLAG_INGRESS      = MLX5E_TC_FLAG_INGRESS_BIT,
  75         MLX5E_TC_FLOW_FLAG_EGRESS       = MLX5E_TC_FLAG_EGRESS_BIT,
  76         MLX5E_TC_FLOW_FLAG_ESWITCH      = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
  77         MLX5E_TC_FLOW_FLAG_NIC          = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
  78         MLX5E_TC_FLOW_FLAG_OFFLOADED    = MLX5E_TC_FLOW_BASE,
  79         MLX5E_TC_FLOW_FLAG_HAIRPIN      = MLX5E_TC_FLOW_BASE + 1,
  80         MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS  = MLX5E_TC_FLOW_BASE + 2,
  81         MLX5E_TC_FLOW_FLAG_SLOW         = MLX5E_TC_FLOW_BASE + 3,
  82         MLX5E_TC_FLOW_FLAG_DUP          = MLX5E_TC_FLOW_BASE + 4,
  83         MLX5E_TC_FLOW_FLAG_NOT_READY    = MLX5E_TC_FLOW_BASE + 5,
  84         MLX5E_TC_FLOW_FLAG_DELETED      = MLX5E_TC_FLOW_BASE + 6,
  85 };
  86 
  87 #define MLX5E_TC_MAX_SPLITS 1
  88 
  89 /* Helper struct for accessing a struct containing list_head array.
  90  * Containing struct
  91  *   |- Helper array
  92  *      [0] Helper item 0
  93  *          |- list_head item 0
  94  *          |- index (0)
  95  *      [1] Helper item 1
  96  *          |- list_head item 1
  97  *          |- index (1)
  98  * To access the containing struct from one of the list_head items:
  99  * 1. Get the helper item from the list_head item using
 100  *    helper item =
 101  *        container_of(list_head item, helper struct type, list_head field)
 102  * 2. Get the contining struct from the helper item and its index in the array:
 103  *    containing struct =
 104  *        container_of(helper item, containing struct type, helper field[index])
 105  */
 106 struct encap_flow_item {
 107         struct mlx5e_encap_entry *e; /* attached encap instance */
 108         struct list_head list;
 109         int index;
 110 };
 111 
 112 struct mlx5e_tc_flow {
 113         struct rhash_head       node;
 114         struct mlx5e_priv       *priv;
 115         u64                     cookie;
 116         unsigned long           flags;
 117         struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
 118         /* Flow can be associated with multiple encap IDs.
 119          * The number of encaps is bounded by the number of supported
 120          * destinations.
 121          */
 122         struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
 123         struct mlx5e_tc_flow    *peer_flow;
 124         struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
 125         struct list_head        mod_hdr; /* flows sharing the same mod hdr ID */
 126         struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
 127         struct list_head        hairpin; /* flows sharing the same hairpin */
 128         struct list_head        peer;    /* flows with peer flow */
 129         struct list_head        unready; /* flows not ready to be offloaded (e.g due to missing route) */
 130         int                     tmp_efi_index;
 131         struct list_head        tmp_list; /* temporary flow list used by neigh update */
 132         refcount_t              refcnt;
 133         struct rcu_head         rcu_head;
 134         struct completion       init_done;
 135         union {
 136                 struct mlx5_esw_flow_attr esw_attr[0];
 137                 struct mlx5_nic_flow_attr nic_attr[0];
 138         };
 139 };
 140 
 141 struct mlx5e_tc_flow_parse_attr {
 142         const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
 143         struct net_device *filter_dev;
 144         struct mlx5_flow_spec spec;
 145         int num_mod_hdr_actions;
 146         int max_mod_hdr_actions;
 147         void *mod_hdr_actions;
 148         int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
 149 };
 150 
 151 #define MLX5E_TC_TABLE_NUM_GROUPS 4
 152 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
 153 
 154 struct mlx5e_hairpin {
 155         struct mlx5_hairpin *pair;
 156 
 157         struct mlx5_core_dev *func_mdev;
 158         struct mlx5e_priv *func_priv;
 159         u32 tdn;
 160         u32 tirn;
 161 
 162         int num_channels;
 163         struct mlx5e_rqt indir_rqt;
 164         u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
 165         struct mlx5e_ttc_table ttc;
 166 };
 167 
 168 struct mlx5e_hairpin_entry {
 169         /* a node of a hash table which keeps all the  hairpin entries */
 170         struct hlist_node hairpin_hlist;
 171 
 172         /* protects flows list */
 173         spinlock_t flows_lock;
 174         /* flows sharing the same hairpin */
 175         struct list_head flows;
 176         /* hpe's that were not fully initialized when dead peer update event
 177          * function traversed them.
 178          */
 179         struct list_head dead_peer_wait_list;
 180 
 181         u16 peer_vhca_id;
 182         u8 prio;
 183         struct mlx5e_hairpin *hp;
 184         refcount_t refcnt;
 185         struct completion res_ready;
 186 };
 187 
 188 struct mod_hdr_key {
 189         int num_actions;
 190         void *actions;
 191 };
 192 
 193 struct mlx5e_mod_hdr_entry {
 194         /* a node of a hash table which keeps all the mod_hdr entries */
 195         struct hlist_node mod_hdr_hlist;
 196 
 197         /* protects flows list */
 198         spinlock_t flows_lock;
 199         /* flows sharing the same mod_hdr entry */
 200         struct list_head flows;
 201 
 202         struct mod_hdr_key key;
 203 
 204         struct mlx5_modify_hdr *modify_hdr;
 205 
 206         refcount_t refcnt;
 207         struct completion res_ready;
 208         int compl_result;
 209 };
 210 
 211 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
 212 
 213 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
 214                               struct mlx5e_tc_flow *flow);
 215 
 216 static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
 217 {
 218         if (!flow || !refcount_inc_not_zero(&flow->refcnt))
 219                 return ERR_PTR(-EINVAL);
 220         return flow;
 221 }
 222 
 223 static void mlx5e_flow_put(struct mlx5e_priv *priv,
 224                            struct mlx5e_tc_flow *flow)
 225 {
 226         if (refcount_dec_and_test(&flow->refcnt)) {
 227                 mlx5e_tc_del_flow(priv, flow);
 228                 kfree_rcu(flow, rcu_head);
 229         }
 230 }
 231 
 232 static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
 233 {
 234         /* Complete all memory stores before setting bit. */
 235         smp_mb__before_atomic();
 236         set_bit(flag, &flow->flags);
 237 }
 238 
 239 #define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
 240 
 241 static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
 242                                      unsigned long flag)
 243 {
 244         /* test_and_set_bit() provides all necessary barriers */
 245         return test_and_set_bit(flag, &flow->flags);
 246 }
 247 
 248 #define flow_flag_test_and_set(flow, flag)                      \
 249         __flow_flag_test_and_set(flow,                          \
 250                                  MLX5E_TC_FLOW_FLAG_##flag)
 251 
 252 static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
 253 {
 254         /* Complete all memory stores before clearing bit. */
 255         smp_mb__before_atomic();
 256         clear_bit(flag, &flow->flags);
 257 }
 258 
 259 #define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
 260                                                       MLX5E_TC_FLOW_FLAG_##flag)
 261 
 262 static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
 263 {
 264         bool ret = test_bit(flag, &flow->flags);
 265 
 266         /* Read fields of flow structure only after checking flags. */
 267         smp_mb__after_atomic();
 268         return ret;
 269 }
 270 
 271 #define flow_flag_test(flow, flag) __flow_flag_test(flow, \
 272                                                     MLX5E_TC_FLOW_FLAG_##flag)
 273 
 274 static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
 275 {
 276         return flow_flag_test(flow, ESWITCH);
 277 }
 278 
 279 static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
 280 {
 281         return flow_flag_test(flow, OFFLOADED);
 282 }
 283 
 284 static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
 285 {
 286         return jhash(key->actions,
 287                      key->num_actions * MLX5_MH_ACT_SZ, 0);
 288 }
 289 
 290 static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
 291                                    struct mod_hdr_key *b)
 292 {
 293         if (a->num_actions != b->num_actions)
 294                 return 1;
 295 
 296         return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
 297 }
 298 
 299 static struct mod_hdr_tbl *
 300 get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
 301 {
 302         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 303 
 304         return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
 305                 &priv->fs.tc.mod_hdr;
 306 }
 307 
 308 static struct mlx5e_mod_hdr_entry *
 309 mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
 310 {
 311         struct mlx5e_mod_hdr_entry *mh, *found = NULL;
 312 
 313         hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
 314                 if (!cmp_mod_hdr_info(&mh->key, key)) {
 315                         refcount_inc(&mh->refcnt);
 316                         found = mh;
 317                         break;
 318                 }
 319         }
 320 
 321         return found;
 322 }
 323 
 324 static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
 325                               struct mlx5e_mod_hdr_entry *mh,
 326                               int namespace)
 327 {
 328         struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
 329 
 330         if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
 331                 return;
 332         hash_del(&mh->mod_hdr_hlist);
 333         mutex_unlock(&tbl->lock);
 334 
 335         WARN_ON(!list_empty(&mh->flows));
 336         if (mh->compl_result > 0)
 337                 mlx5_modify_header_dealloc(priv->mdev, mh->modify_hdr);
 338 
 339         kfree(mh);
 340 }
 341 
 342 static int get_flow_name_space(struct mlx5e_tc_flow *flow)
 343 {
 344         return mlx5e_is_eswitch_flow(flow) ?
 345                 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
 346 }
 347 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
 348                                 struct mlx5e_tc_flow *flow,
 349                                 struct mlx5e_tc_flow_parse_attr *parse_attr)
 350 {
 351         int num_actions, actions_size, namespace, err;
 352         struct mlx5e_mod_hdr_entry *mh;
 353         struct mod_hdr_tbl *tbl;
 354         struct mod_hdr_key key;
 355         u32 hash_key;
 356 
 357         num_actions  = parse_attr->num_mod_hdr_actions;
 358         actions_size = MLX5_MH_ACT_SZ * num_actions;
 359 
 360         key.actions = parse_attr->mod_hdr_actions;
 361         key.num_actions = num_actions;
 362 
 363         hash_key = hash_mod_hdr_info(&key);
 364 
 365         namespace = get_flow_name_space(flow);
 366         tbl = get_mod_hdr_table(priv, namespace);
 367 
 368         mutex_lock(&tbl->lock);
 369         mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
 370         if (mh) {
 371                 mutex_unlock(&tbl->lock);
 372                 wait_for_completion(&mh->res_ready);
 373 
 374                 if (mh->compl_result < 0) {
 375                         err = -EREMOTEIO;
 376                         goto attach_header_err;
 377                 }
 378                 goto attach_flow;
 379         }
 380 
 381         mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
 382         if (!mh) {
 383                 mutex_unlock(&tbl->lock);
 384                 return -ENOMEM;
 385         }
 386 
 387         mh->key.actions = (void *)mh + sizeof(*mh);
 388         memcpy(mh->key.actions, key.actions, actions_size);
 389         mh->key.num_actions = num_actions;
 390         spin_lock_init(&mh->flows_lock);
 391         INIT_LIST_HEAD(&mh->flows);
 392         refcount_set(&mh->refcnt, 1);
 393         init_completion(&mh->res_ready);
 394 
 395         hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
 396         mutex_unlock(&tbl->lock);
 397 
 398         mh->modify_hdr = mlx5_modify_header_alloc(priv->mdev, namespace,
 399                                                   mh->key.num_actions,
 400                                                   mh->key.actions);
 401         if (IS_ERR(mh->modify_hdr)) {
 402                 err = PTR_ERR(mh->modify_hdr);
 403                 mh->compl_result = err;
 404                 goto alloc_header_err;
 405         }
 406         mh->compl_result = 1;
 407         complete_all(&mh->res_ready);
 408 
 409 attach_flow:
 410         flow->mh = mh;
 411         spin_lock(&mh->flows_lock);
 412         list_add(&flow->mod_hdr, &mh->flows);
 413         spin_unlock(&mh->flows_lock);
 414         if (mlx5e_is_eswitch_flow(flow))
 415                 flow->esw_attr->modify_hdr = mh->modify_hdr;
 416         else
 417                 flow->nic_attr->modify_hdr = mh->modify_hdr;
 418 
 419         return 0;
 420 
 421 alloc_header_err:
 422         complete_all(&mh->res_ready);
 423 attach_header_err:
 424         mlx5e_mod_hdr_put(priv, mh, namespace);
 425         return err;
 426 }
 427 
 428 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
 429                                  struct mlx5e_tc_flow *flow)
 430 {
 431         /* flow wasn't fully initialized */
 432         if (!flow->mh)
 433                 return;
 434 
 435         spin_lock(&flow->mh->flows_lock);
 436         list_del(&flow->mod_hdr);
 437         spin_unlock(&flow->mh->flows_lock);
 438 
 439         mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
 440         flow->mh = NULL;
 441 }
 442 
 443 static
 444 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
 445 {
 446         struct net_device *netdev;
 447         struct mlx5e_priv *priv;
 448 
 449         netdev = __dev_get_by_index(net, ifindex);
 450         priv = netdev_priv(netdev);
 451         return priv->mdev;
 452 }
 453 
 454 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
 455 {
 456         u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
 457         void *tirc;
 458         int err;
 459 
 460         err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
 461         if (err)
 462                 goto alloc_tdn_err;
 463 
 464         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
 465 
 466         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
 467         MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
 468         MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
 469 
 470         err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
 471         if (err)
 472                 goto create_tir_err;
 473 
 474         return 0;
 475 
 476 create_tir_err:
 477         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 478 alloc_tdn_err:
 479         return err;
 480 }
 481 
 482 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
 483 {
 484         mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
 485         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 486 }
 487 
 488 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
 489 {
 490         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
 491         struct mlx5e_priv *priv = hp->func_priv;
 492         int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
 493 
 494         mlx5e_build_default_indir_rqt(indirection_rqt, sz,
 495                                       hp->num_channels);
 496 
 497         for (i = 0; i < sz; i++) {
 498                 ix = i;
 499                 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
 500                         ix = mlx5e_bits_invert(i, ilog2(sz));
 501                 ix = indirection_rqt[ix];
 502                 rqn = hp->pair->rqn[ix];
 503                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
 504         }
 505 }
 506 
 507 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
 508 {
 509         int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
 510         struct mlx5e_priv *priv = hp->func_priv;
 511         struct mlx5_core_dev *mdev = priv->mdev;
 512         void *rqtc;
 513         u32 *in;
 514 
 515         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
 516         in = kvzalloc(inlen, GFP_KERNEL);
 517         if (!in)
 518                 return -ENOMEM;
 519 
 520         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
 521 
 522         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
 523         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
 524 
 525         mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
 526 
 527         err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
 528         if (!err)
 529                 hp->indir_rqt.enabled = true;
 530 
 531         kvfree(in);
 532         return err;
 533 }
 534 
 535 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
 536 {
 537         struct mlx5e_priv *priv = hp->func_priv;
 538         u32 in[MLX5_ST_SZ_DW(create_tir_in)];
 539         int tt, i, err;
 540         void *tirc;
 541 
 542         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
 543                 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
 544 
 545                 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
 546                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
 547 
 548                 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
 549                 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
 550                 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
 551                 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
 552 
 553                 err = mlx5_core_create_tir(hp->func_mdev, in,
 554                                            MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
 555                 if (err) {
 556                         mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
 557                         goto err_destroy_tirs;
 558                 }
 559         }
 560         return 0;
 561 
 562 err_destroy_tirs:
 563         for (i = 0; i < tt; i++)
 564                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
 565         return err;
 566 }
 567 
 568 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
 569 {
 570         int tt;
 571 
 572         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 573                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
 574 }
 575 
 576 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
 577                                          struct ttc_params *ttc_params)
 578 {
 579         struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
 580         int tt;
 581 
 582         memset(ttc_params, 0, sizeof(*ttc_params));
 583 
 584         ttc_params->any_tt_tirn = hp->tirn;
 585 
 586         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 587                 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
 588 
 589         ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
 590         ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
 591         ft_attr->prio = MLX5E_TC_PRIO;
 592 }
 593 
 594 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
 595 {
 596         struct mlx5e_priv *priv = hp->func_priv;
 597         struct ttc_params ttc_params;
 598         int err;
 599 
 600         err = mlx5e_hairpin_create_indirect_rqt(hp);
 601         if (err)
 602                 return err;
 603 
 604         err = mlx5e_hairpin_create_indirect_tirs(hp);
 605         if (err)
 606                 goto err_create_indirect_tirs;
 607 
 608         mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
 609         err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
 610         if (err)
 611                 goto err_create_ttc_table;
 612 
 613         netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
 614                    hp->num_channels, hp->ttc.ft.t->id);
 615 
 616         return 0;
 617 
 618 err_create_ttc_table:
 619         mlx5e_hairpin_destroy_indirect_tirs(hp);
 620 err_create_indirect_tirs:
 621         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
 622 
 623         return err;
 624 }
 625 
 626 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
 627 {
 628         struct mlx5e_priv *priv = hp->func_priv;
 629 
 630         mlx5e_destroy_ttc_table(priv, &hp->ttc);
 631         mlx5e_hairpin_destroy_indirect_tirs(hp);
 632         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
 633 }
 634 
 635 static struct mlx5e_hairpin *
 636 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
 637                      int peer_ifindex)
 638 {
 639         struct mlx5_core_dev *func_mdev, *peer_mdev;
 640         struct mlx5e_hairpin *hp;
 641         struct mlx5_hairpin *pair;
 642         int err;
 643 
 644         hp = kzalloc(sizeof(*hp), GFP_KERNEL);
 645         if (!hp)
 646                 return ERR_PTR(-ENOMEM);
 647 
 648         func_mdev = priv->mdev;
 649         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 650 
 651         pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
 652         if (IS_ERR(pair)) {
 653                 err = PTR_ERR(pair);
 654                 goto create_pair_err;
 655         }
 656         hp->pair = pair;
 657         hp->func_mdev = func_mdev;
 658         hp->func_priv = priv;
 659         hp->num_channels = params->num_channels;
 660 
 661         err = mlx5e_hairpin_create_transport(hp);
 662         if (err)
 663                 goto create_transport_err;
 664 
 665         if (hp->num_channels > 1) {
 666                 err = mlx5e_hairpin_rss_init(hp);
 667                 if (err)
 668                         goto rss_init_err;
 669         }
 670 
 671         return hp;
 672 
 673 rss_init_err:
 674         mlx5e_hairpin_destroy_transport(hp);
 675 create_transport_err:
 676         mlx5_core_hairpin_destroy(hp->pair);
 677 create_pair_err:
 678         kfree(hp);
 679         return ERR_PTR(err);
 680 }
 681 
 682 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
 683 {
 684         if (hp->num_channels > 1)
 685                 mlx5e_hairpin_rss_cleanup(hp);
 686         mlx5e_hairpin_destroy_transport(hp);
 687         mlx5_core_hairpin_destroy(hp->pair);
 688         kvfree(hp);
 689 }
 690 
 691 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
 692 {
 693         return (peer_vhca_id << 16 | prio);
 694 }
 695 
 696 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
 697                                                      u16 peer_vhca_id, u8 prio)
 698 {
 699         struct mlx5e_hairpin_entry *hpe;
 700         u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
 701 
 702         hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
 703                                hairpin_hlist, hash_key) {
 704                 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
 705                         refcount_inc(&hpe->refcnt);
 706                         return hpe;
 707                 }
 708         }
 709 
 710         return NULL;
 711 }
 712 
 713 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
 714                               struct mlx5e_hairpin_entry *hpe)
 715 {
 716         /* no more hairpin flows for us, release the hairpin pair */
 717         if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
 718                 return;
 719         hash_del(&hpe->hairpin_hlist);
 720         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 721 
 722         if (!IS_ERR_OR_NULL(hpe->hp)) {
 723                 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
 724                            dev_name(hpe->hp->pair->peer_mdev->device));
 725 
 726                 mlx5e_hairpin_destroy(hpe->hp);
 727         }
 728 
 729         WARN_ON(!list_empty(&hpe->flows));
 730         kfree(hpe);
 731 }
 732 
 733 #define UNKNOWN_MATCH_PRIO 8
 734 
 735 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
 736                                   struct mlx5_flow_spec *spec, u8 *match_prio,
 737                                   struct netlink_ext_ack *extack)
 738 {
 739         void *headers_c, *headers_v;
 740         u8 prio_val, prio_mask = 0;
 741         bool vlan_present;
 742 
 743 #ifdef CONFIG_MLX5_CORE_EN_DCB
 744         if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
 745                 NL_SET_ERR_MSG_MOD(extack,
 746                                    "only PCP trust state supported for hairpin");
 747                 return -EOPNOTSUPP;
 748         }
 749 #endif
 750         headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
 751         headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
 752 
 753         vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
 754         if (vlan_present) {
 755                 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
 756                 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
 757         }
 758 
 759         if (!vlan_present || !prio_mask) {
 760                 prio_val = UNKNOWN_MATCH_PRIO;
 761         } else if (prio_mask != 0x7) {
 762                 NL_SET_ERR_MSG_MOD(extack,
 763                                    "masked priority match not supported for hairpin");
 764                 return -EOPNOTSUPP;
 765         }
 766 
 767         *match_prio = prio_val;
 768         return 0;
 769 }
 770 
 771 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
 772                                   struct mlx5e_tc_flow *flow,
 773                                   struct mlx5e_tc_flow_parse_attr *parse_attr,
 774                                   struct netlink_ext_ack *extack)
 775 {
 776         int peer_ifindex = parse_attr->mirred_ifindex[0];
 777         struct mlx5_hairpin_params params;
 778         struct mlx5_core_dev *peer_mdev;
 779         struct mlx5e_hairpin_entry *hpe;
 780         struct mlx5e_hairpin *hp;
 781         u64 link_speed64;
 782         u32 link_speed;
 783         u8 match_prio;
 784         u16 peer_id;
 785         int err;
 786 
 787         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 788         if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
 789                 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
 790                 return -EOPNOTSUPP;
 791         }
 792 
 793         peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
 794         err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
 795                                      extack);
 796         if (err)
 797                 return err;
 798 
 799         mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
 800         hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
 801         if (hpe) {
 802                 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 803                 wait_for_completion(&hpe->res_ready);
 804 
 805                 if (IS_ERR(hpe->hp)) {
 806                         err = -EREMOTEIO;
 807                         goto out_err;
 808                 }
 809                 goto attach_flow;
 810         }
 811 
 812         hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
 813         if (!hpe) {
 814                 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 815                 return -ENOMEM;
 816         }
 817 
 818         spin_lock_init(&hpe->flows_lock);
 819         INIT_LIST_HEAD(&hpe->flows);
 820         INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
 821         hpe->peer_vhca_id = peer_id;
 822         hpe->prio = match_prio;
 823         refcount_set(&hpe->refcnt, 1);
 824         init_completion(&hpe->res_ready);
 825 
 826         hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
 827                  hash_hairpin_info(peer_id, match_prio));
 828         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 829 
 830         params.log_data_size = 15;
 831         params.log_data_size = min_t(u8, params.log_data_size,
 832                                      MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
 833         params.log_data_size = max_t(u8, params.log_data_size,
 834                                      MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
 835 
 836         params.log_num_packets = params.log_data_size -
 837                                  MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
 838         params.log_num_packets = min_t(u8, params.log_num_packets,
 839                                        MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
 840 
 841         params.q_counter = priv->q_counter;
 842         /* set hairpin pair per each 50Gbs share of the link */
 843         mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
 844         link_speed = max_t(u32, link_speed, 50000);
 845         link_speed64 = link_speed;
 846         do_div(link_speed64, 50000);
 847         params.num_channels = link_speed64;
 848 
 849         hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
 850         hpe->hp = hp;
 851         complete_all(&hpe->res_ready);
 852         if (IS_ERR(hp)) {
 853                 err = PTR_ERR(hp);
 854                 goto out_err;
 855         }
 856 
 857         netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
 858                    hp->tirn, hp->pair->rqn[0],
 859                    dev_name(hp->pair->peer_mdev->device),
 860                    hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
 861 
 862 attach_flow:
 863         if (hpe->hp->num_channels > 1) {
 864                 flow_flag_set(flow, HAIRPIN_RSS);
 865                 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
 866         } else {
 867                 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
 868         }
 869 
 870         flow->hpe = hpe;
 871         spin_lock(&hpe->flows_lock);
 872         list_add(&flow->hairpin, &hpe->flows);
 873         spin_unlock(&hpe->flows_lock);
 874 
 875         return 0;
 876 
 877 out_err:
 878         mlx5e_hairpin_put(priv, hpe);
 879         return err;
 880 }
 881 
 882 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
 883                                    struct mlx5e_tc_flow *flow)
 884 {
 885         /* flow wasn't fully initialized */
 886         if (!flow->hpe)
 887                 return;
 888 
 889         spin_lock(&flow->hpe->flows_lock);
 890         list_del(&flow->hairpin);
 891         spin_unlock(&flow->hpe->flows_lock);
 892 
 893         mlx5e_hairpin_put(priv, flow->hpe);
 894         flow->hpe = NULL;
 895 }
 896 
 897 static int
 898 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
 899                       struct mlx5e_tc_flow_parse_attr *parse_attr,
 900                       struct mlx5e_tc_flow *flow,
 901                       struct netlink_ext_ack *extack)
 902 {
 903         struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
 904         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
 905         struct mlx5_core_dev *dev = priv->mdev;
 906         struct mlx5_flow_destination dest[2] = {};
 907         struct mlx5_flow_act flow_act = {
 908                 .action = attr->action,
 909                 .flags    = FLOW_ACT_NO_APPEND,
 910         };
 911         struct mlx5_fc *counter = NULL;
 912         int err, dest_ix = 0;
 913 
 914         flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
 915         flow_context->flow_tag = attr->flow_tag;
 916 
 917         if (flow_flag_test(flow, HAIRPIN)) {
 918                 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
 919                 if (err)
 920                         return err;
 921 
 922                 if (flow_flag_test(flow, HAIRPIN_RSS)) {
 923                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
 924                         dest[dest_ix].ft = attr->hairpin_ft;
 925                 } else {
 926                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
 927                         dest[dest_ix].tir_num = attr->hairpin_tirn;
 928                 }
 929                 dest_ix++;
 930         } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
 931                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
 932                 dest[dest_ix].ft = priv->fs.vlan.ft.t;
 933                 dest_ix++;
 934         }
 935 
 936         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
 937                 counter = mlx5_fc_create(dev, true);
 938                 if (IS_ERR(counter))
 939                         return PTR_ERR(counter);
 940 
 941                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
 942                 dest[dest_ix].counter_id = mlx5_fc_id(counter);
 943                 dest_ix++;
 944                 attr->counter = counter;
 945         }
 946 
 947         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
 948                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
 949                 flow_act.modify_hdr = attr->modify_hdr;
 950                 kfree(parse_attr->mod_hdr_actions);
 951                 if (err)
 952                         return err;
 953         }
 954 
 955         mutex_lock(&priv->fs.tc.t_lock);
 956         if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
 957                 int tc_grp_size, tc_tbl_size;
 958                 u32 max_flow_counter;
 959 
 960                 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
 961                                     MLX5_CAP_GEN(dev, max_flow_counter_15_0);
 962 
 963                 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
 964 
 965                 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
 966                                     BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
 967 
 968                 priv->fs.tc.t =
 969                         mlx5_create_auto_grouped_flow_table(priv->fs.ns,
 970                                                             MLX5E_TC_PRIO,
 971                                                             tc_tbl_size,
 972                                                             MLX5E_TC_TABLE_NUM_GROUPS,
 973                                                             MLX5E_TC_FT_LEVEL, 0);
 974                 if (IS_ERR(priv->fs.tc.t)) {
 975                         mutex_unlock(&priv->fs.tc.t_lock);
 976                         NL_SET_ERR_MSG_MOD(extack,
 977                                            "Failed to create tc offload table\n");
 978                         netdev_err(priv->netdev,
 979                                    "Failed to create tc offload table\n");
 980                         return PTR_ERR(priv->fs.tc.t);
 981                 }
 982         }
 983 
 984         if (attr->match_level != MLX5_MATCH_NONE)
 985                 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
 986 
 987         flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
 988                                             &flow_act, dest, dest_ix);
 989         mutex_unlock(&priv->fs.tc.t_lock);
 990 
 991         return PTR_ERR_OR_ZERO(flow->rule[0]);
 992 }
 993 
 994 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
 995                                   struct mlx5e_tc_flow *flow)
 996 {
 997         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
 998         struct mlx5_fc *counter = NULL;
 999 
1000         counter = attr->counter;
1001         if (!IS_ERR_OR_NULL(flow->rule[0]))
1002                 mlx5_del_flow_rules(flow->rule[0]);
1003         mlx5_fc_destroy(priv->mdev, counter);
1004 
1005         mutex_lock(&priv->fs.tc.t_lock);
1006         if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
1007                 mlx5_destroy_flow_table(priv->fs.tc.t);
1008                 priv->fs.tc.t = NULL;
1009         }
1010         mutex_unlock(&priv->fs.tc.t_lock);
1011 
1012         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1013                 mlx5e_detach_mod_hdr(priv, flow);
1014 
1015         if (flow_flag_test(flow, HAIRPIN))
1016                 mlx5e_hairpin_flow_del(priv, flow);
1017 }
1018 
1019 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1020                                struct mlx5e_tc_flow *flow, int out_index);
1021 
1022 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1023                               struct mlx5e_tc_flow *flow,
1024                               struct net_device *mirred_dev,
1025                               int out_index,
1026                               struct netlink_ext_ack *extack,
1027                               struct net_device **encap_dev,
1028                               bool *encap_valid);
1029 
1030 static struct mlx5_flow_handle *
1031 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1032                            struct mlx5e_tc_flow *flow,
1033                            struct mlx5_flow_spec *spec,
1034                            struct mlx5_esw_flow_attr *attr)
1035 {
1036         struct mlx5_flow_handle *rule;
1037 
1038         rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1039         if (IS_ERR(rule))
1040                 return rule;
1041 
1042         if (attr->split_count) {
1043                 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1044                 if (IS_ERR(flow->rule[1])) {
1045                         mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1046                         return flow->rule[1];
1047                 }
1048         }
1049 
1050         return rule;
1051 }
1052 
1053 static void
1054 mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1055                              struct mlx5e_tc_flow *flow,
1056                            struct mlx5_esw_flow_attr *attr)
1057 {
1058         flow_flag_clear(flow, OFFLOADED);
1059 
1060         if (attr->split_count)
1061                 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1062 
1063         mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1064 }
1065 
1066 static struct mlx5_flow_handle *
1067 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1068                               struct mlx5e_tc_flow *flow,
1069                               struct mlx5_flow_spec *spec,
1070                               struct mlx5_esw_flow_attr *slow_attr)
1071 {
1072         struct mlx5_flow_handle *rule;
1073 
1074         memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
1075         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1076         slow_attr->split_count = 0;
1077         slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
1078 
1079         rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1080         if (!IS_ERR(rule))
1081                 flow_flag_set(flow, SLOW);
1082 
1083         return rule;
1084 }
1085 
1086 static void
1087 mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1088                                   struct mlx5e_tc_flow *flow,
1089                                   struct mlx5_esw_flow_attr *slow_attr)
1090 {
1091         memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
1092         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1093         slow_attr->split_count = 0;
1094         slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
1095         mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
1096         flow_flag_clear(flow, SLOW);
1097 }
1098 
1099 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1100  * function.
1101  */
1102 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1103                              struct list_head *unready_flows)
1104 {
1105         flow_flag_set(flow, NOT_READY);
1106         list_add_tail(&flow->unready, unready_flows);
1107 }
1108 
1109 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1110  * function.
1111  */
1112 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1113 {
1114         list_del(&flow->unready);
1115         flow_flag_clear(flow, NOT_READY);
1116 }
1117 
1118 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1119 {
1120         struct mlx5_rep_uplink_priv *uplink_priv;
1121         struct mlx5e_rep_priv *rpriv;
1122         struct mlx5_eswitch *esw;
1123 
1124         esw = flow->priv->mdev->priv.eswitch;
1125         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1126         uplink_priv = &rpriv->uplink_priv;
1127 
1128         mutex_lock(&uplink_priv->unready_flows_lock);
1129         unready_flow_add(flow, &uplink_priv->unready_flows);
1130         mutex_unlock(&uplink_priv->unready_flows_lock);
1131 }
1132 
1133 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1134 {
1135         struct mlx5_rep_uplink_priv *uplink_priv;
1136         struct mlx5e_rep_priv *rpriv;
1137         struct mlx5_eswitch *esw;
1138 
1139         esw = flow->priv->mdev->priv.eswitch;
1140         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1141         uplink_priv = &rpriv->uplink_priv;
1142 
1143         mutex_lock(&uplink_priv->unready_flows_lock);
1144         unready_flow_del(flow);
1145         mutex_unlock(&uplink_priv->unready_flows_lock);
1146 }
1147 
1148 static int
1149 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1150                       struct mlx5e_tc_flow *flow,
1151                       struct netlink_ext_ack *extack)
1152 {
1153         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1154         u32 max_chain = mlx5_eswitch_get_chain_range(esw);
1155         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1156         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1157         u16 max_prio = mlx5_eswitch_get_prio_range(esw);
1158         struct net_device *out_dev, *encap_dev = NULL;
1159         struct mlx5_fc *counter = NULL;
1160         struct mlx5e_rep_priv *rpriv;
1161         struct mlx5e_priv *out_priv;
1162         bool encap_valid = true;
1163         int err = 0;
1164         int out_index;
1165 
1166         if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
1167                 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
1168                 return -EOPNOTSUPP;
1169         }
1170 
1171         if (attr->chain > max_chain) {
1172                 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
1173                 return -EOPNOTSUPP;
1174         }
1175 
1176         if (attr->prio > max_prio) {
1177                 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
1178                 return -EOPNOTSUPP;
1179         }
1180 
1181         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1182                 int mirred_ifindex;
1183 
1184                 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1185                         continue;
1186 
1187                 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
1188                 out_dev = __dev_get_by_index(dev_net(priv->netdev),
1189                                              mirred_ifindex);
1190                 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
1191                                          extack, &encap_dev, &encap_valid);
1192                 if (err)
1193                         return err;
1194 
1195                 out_priv = netdev_priv(encap_dev);
1196                 rpriv = out_priv->ppriv;
1197                 attr->dests[out_index].rep = rpriv->rep;
1198                 attr->dests[out_index].mdev = out_priv->mdev;
1199         }
1200 
1201         err = mlx5_eswitch_add_vlan_action(esw, attr);
1202         if (err)
1203                 return err;
1204 
1205         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1206                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1207                 kfree(parse_attr->mod_hdr_actions);
1208                 if (err)
1209                         return err;
1210         }
1211 
1212         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1213                 counter = mlx5_fc_create(attr->counter_dev, true);
1214                 if (IS_ERR(counter))
1215                         return PTR_ERR(counter);
1216 
1217                 attr->counter = counter;
1218         }
1219 
1220         /* we get here if one of the following takes place:
1221          * (1) there's no error
1222          * (2) there's an encap action and we don't have valid neigh
1223          */
1224         if (!encap_valid) {
1225                 /* continue with goto slow path rule instead */
1226                 struct mlx5_esw_flow_attr slow_attr;
1227 
1228                 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1229         } else {
1230                 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
1231         }
1232 
1233         if (IS_ERR(flow->rule[0]))
1234                 return PTR_ERR(flow->rule[0]);
1235         else
1236                 flow_flag_set(flow, OFFLOADED);
1237 
1238         return 0;
1239 }
1240 
1241 static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1242 {
1243         struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1244         void *headers_v = MLX5_ADDR_OF(fte_match_param,
1245                                        spec->match_value,
1246                                        misc_parameters_3);
1247         u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1248                                              headers_v,
1249                                              geneve_tlv_option_0_data);
1250 
1251         return !!geneve_tlv_opt_0_data;
1252 }
1253 
1254 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1255                                   struct mlx5e_tc_flow *flow)
1256 {
1257         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1258         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1259         struct mlx5_esw_flow_attr slow_attr;
1260         int out_index;
1261 
1262         if (flow_flag_test(flow, NOT_READY)) {
1263                 remove_unready_flow(flow);
1264                 kvfree(attr->parse_attr);
1265                 return;
1266         }
1267 
1268         if (mlx5e_is_offloaded_flow(flow)) {
1269                 if (flow_flag_test(flow, SLOW))
1270                         mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1271                 else
1272                         mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1273         }
1274 
1275         if (mlx5_flow_has_geneve_opt(flow))
1276                 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1277 
1278         mlx5_eswitch_del_vlan_action(esw, attr);
1279 
1280         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1281                 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
1282                         mlx5e_detach_encap(priv, flow, out_index);
1283                         kfree(attr->parse_attr->tun_info[out_index]);
1284                 }
1285         kvfree(attr->parse_attr);
1286 
1287         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1288                 mlx5e_detach_mod_hdr(priv, flow);
1289 
1290         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1291                 mlx5_fc_destroy(attr->counter_dev, attr->counter);
1292 }
1293 
1294 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1295                               struct mlx5e_encap_entry *e,
1296                               struct list_head *flow_list)
1297 {
1298         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1299         struct mlx5_esw_flow_attr slow_attr, *esw_attr;
1300         struct mlx5_flow_handle *rule;
1301         struct mlx5_flow_spec *spec;
1302         struct mlx5e_tc_flow *flow;
1303         int err;
1304 
1305         e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1306                                                      e->reformat_type,
1307                                                      e->encap_size, e->encap_header,
1308                                                      MLX5_FLOW_NAMESPACE_FDB);
1309         if (IS_ERR(e->pkt_reformat)) {
1310                 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1311                                PTR_ERR(e->pkt_reformat));
1312                 return;
1313         }
1314         e->flags |= MLX5_ENCAP_ENTRY_VALID;
1315         mlx5e_rep_queue_neigh_stats_work(priv);
1316 
1317         list_for_each_entry(flow, flow_list, tmp_list) {
1318                 bool all_flow_encaps_valid = true;
1319                 int i;
1320 
1321                 if (!mlx5e_is_offloaded_flow(flow))
1322                         continue;
1323                 esw_attr = flow->esw_attr;
1324                 spec = &esw_attr->parse_attr->spec;
1325 
1326                 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
1327                 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1328                 /* Flow can be associated with multiple encap entries.
1329                  * Before offloading the flow verify that all of them have
1330                  * a valid neighbour.
1331                  */
1332                 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1333                         if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1334                                 continue;
1335                         if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1336                                 all_flow_encaps_valid = false;
1337                                 break;
1338                         }
1339                 }
1340                 /* Do not offload flows with unresolved neighbors */
1341                 if (!all_flow_encaps_valid)
1342                         continue;
1343                 /* update from slow path rule to encap rule */
1344                 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1345                 if (IS_ERR(rule)) {
1346                         err = PTR_ERR(rule);
1347                         mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1348                                        err);
1349                         continue;
1350                 }
1351 
1352                 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1353                 flow->rule[0] = rule;
1354                 /* was unset when slow path rule removed */
1355                 flow_flag_set(flow, OFFLOADED);
1356         }
1357 }
1358 
1359 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1360                               struct mlx5e_encap_entry *e,
1361                               struct list_head *flow_list)
1362 {
1363         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1364         struct mlx5_esw_flow_attr slow_attr;
1365         struct mlx5_flow_handle *rule;
1366         struct mlx5_flow_spec *spec;
1367         struct mlx5e_tc_flow *flow;
1368         int err;
1369 
1370         list_for_each_entry(flow, flow_list, tmp_list) {
1371                 if (!mlx5e_is_offloaded_flow(flow))
1372                         continue;
1373                 spec = &flow->esw_attr->parse_attr->spec;
1374 
1375                 /* update from encap rule to slow path rule */
1376                 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
1377                 /* mark the flow's encap dest as non-valid */
1378                 flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
1379 
1380                 if (IS_ERR(rule)) {
1381                         err = PTR_ERR(rule);
1382                         mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1383                                        err);
1384                         continue;
1385                 }
1386 
1387                 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1388                 flow->rule[0] = rule;
1389                 /* was unset when fast path rule removed */
1390                 flow_flag_set(flow, OFFLOADED);
1391         }
1392 
1393         /* we know that the encap is valid */
1394         e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1395         mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
1396 }
1397 
1398 static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1399 {
1400         if (mlx5e_is_eswitch_flow(flow))
1401                 return flow->esw_attr->counter;
1402         else
1403                 return flow->nic_attr->counter;
1404 }
1405 
1406 /* Takes reference to all flows attached to encap and adds the flows to
1407  * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1408  */
1409 void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1410 {
1411         struct encap_flow_item *efi;
1412         struct mlx5e_tc_flow *flow;
1413 
1414         list_for_each_entry(efi, &e->flows, list) {
1415                 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1416                 if (IS_ERR(mlx5e_flow_get(flow)))
1417                         continue;
1418                 wait_for_completion(&flow->init_done);
1419 
1420                 flow->tmp_efi_index = efi->index;
1421                 list_add(&flow->tmp_list, flow_list);
1422         }
1423 }
1424 
1425 /* Iterate over tmp_list of flows attached to flow_list head. */
1426 void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
1427 {
1428         struct mlx5e_tc_flow *flow, *tmp;
1429 
1430         list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1431                 mlx5e_flow_put(priv, flow);
1432 }
1433 
1434 static struct mlx5e_encap_entry *
1435 mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1436                            struct mlx5e_encap_entry *e)
1437 {
1438         struct mlx5e_encap_entry *next = NULL;
1439 
1440 retry:
1441         rcu_read_lock();
1442 
1443         /* find encap with non-zero reference counter value */
1444         for (next = e ?
1445                      list_next_or_null_rcu(&nhe->encap_list,
1446                                            &e->encap_list,
1447                                            struct mlx5e_encap_entry,
1448                                            encap_list) :
1449                      list_first_or_null_rcu(&nhe->encap_list,
1450                                             struct mlx5e_encap_entry,
1451                                             encap_list);
1452              next;
1453              next = list_next_or_null_rcu(&nhe->encap_list,
1454                                           &next->encap_list,
1455                                           struct mlx5e_encap_entry,
1456                                           encap_list))
1457                 if (mlx5e_encap_take(next))
1458                         break;
1459 
1460         rcu_read_unlock();
1461 
1462         /* release starting encap */
1463         if (e)
1464                 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1465         if (!next)
1466                 return next;
1467 
1468         /* wait for encap to be fully initialized */
1469         wait_for_completion(&next->res_ready);
1470         /* continue searching if encap entry is not in valid state after completion */
1471         if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1472                 e = next;
1473                 goto retry;
1474         }
1475 
1476         return next;
1477 }
1478 
1479 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1480 {
1481         struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1482         struct mlx5e_encap_entry *e = NULL;
1483         struct mlx5e_tc_flow *flow;
1484         struct mlx5_fc *counter;
1485         struct neigh_table *tbl;
1486         bool neigh_used = false;
1487         struct neighbour *n;
1488         u64 lastuse;
1489 
1490         if (m_neigh->family == AF_INET)
1491                 tbl = &arp_tbl;
1492 #if IS_ENABLED(CONFIG_IPV6)
1493         else if (m_neigh->family == AF_INET6)
1494                 tbl = ipv6_stub->nd_tbl;
1495 #endif
1496         else
1497                 return;
1498 
1499         /* mlx5e_get_next_valid_encap() releases previous encap before returning
1500          * next one.
1501          */
1502         while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
1503                 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
1504                 struct encap_flow_item *efi, *tmp;
1505                 struct mlx5_eswitch *esw;
1506                 LIST_HEAD(flow_list);
1507 
1508                 esw = priv->mdev->priv.eswitch;
1509                 mutex_lock(&esw->offloads.encap_tbl_lock);
1510                 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
1511                         flow = container_of(efi, struct mlx5e_tc_flow,
1512                                             encaps[efi->index]);
1513                         if (IS_ERR(mlx5e_flow_get(flow)))
1514                                 continue;
1515                         list_add(&flow->tmp_list, &flow_list);
1516 
1517                         if (mlx5e_is_offloaded_flow(flow)) {
1518                                 counter = mlx5e_tc_get_counter(flow);
1519                                 lastuse = mlx5_fc_query_lastuse(counter);
1520                                 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1521                                         neigh_used = true;
1522                                         break;
1523                                 }
1524                         }
1525                 }
1526                 mutex_unlock(&esw->offloads.encap_tbl_lock);
1527 
1528                 mlx5e_put_encap_flow_list(priv, &flow_list);
1529                 if (neigh_used) {
1530                         /* release current encap before breaking the loop */
1531                         mlx5e_encap_put(priv, e);
1532                         break;
1533                 }
1534         }
1535 
1536         trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1537 
1538         if (neigh_used) {
1539                 nhe->reported_lastuse = jiffies;
1540 
1541                 /* find the relevant neigh according to the cached device and
1542                  * dst ip pair
1543                  */
1544                 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1545                 if (!n)
1546                         return;
1547 
1548                 neigh_event_send(n, NULL);
1549                 neigh_release(n);
1550         }
1551 }
1552 
1553 static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1554 {
1555         WARN_ON(!list_empty(&e->flows));
1556 
1557         if (e->compl_result > 0) {
1558                 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1559 
1560                 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1561                         mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
1562         }
1563 
1564         kfree(e->tun_info);
1565         kfree(e->encap_header);
1566         kfree_rcu(e, rcu);
1567 }
1568 
1569 void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1570 {
1571         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1572 
1573         if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1574                 return;
1575         hash_del_rcu(&e->encap_hlist);
1576         mutex_unlock(&esw->offloads.encap_tbl_lock);
1577 
1578         mlx5e_encap_dealloc(priv, e);
1579 }
1580 
1581 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1582                                struct mlx5e_tc_flow *flow, int out_index)
1583 {
1584         struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1585         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1586 
1587         /* flow wasn't fully initialized */
1588         if (!e)
1589                 return;
1590 
1591         mutex_lock(&esw->offloads.encap_tbl_lock);
1592         list_del(&flow->encaps[out_index].list);
1593         flow->encaps[out_index].e = NULL;
1594         if (!refcount_dec_and_test(&e->refcnt)) {
1595                 mutex_unlock(&esw->offloads.encap_tbl_lock);
1596                 return;
1597         }
1598         hash_del_rcu(&e->encap_hlist);
1599         mutex_unlock(&esw->offloads.encap_tbl_lock);
1600 
1601         mlx5e_encap_dealloc(priv, e);
1602 }
1603 
1604 static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1605 {
1606         struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1607 
1608         if (!flow_flag_test(flow, ESWITCH) ||
1609             !flow_flag_test(flow, DUP))
1610                 return;
1611 
1612         mutex_lock(&esw->offloads.peer_mutex);
1613         list_del(&flow->peer);
1614         mutex_unlock(&esw->offloads.peer_mutex);
1615 
1616         flow_flag_clear(flow, DUP);
1617 
1618         if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1619                 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1620                 kfree(flow->peer_flow);
1621         }
1622 
1623         flow->peer_flow = NULL;
1624 }
1625 
1626 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1627 {
1628         struct mlx5_core_dev *dev = flow->priv->mdev;
1629         struct mlx5_devcom *devcom = dev->priv.devcom;
1630         struct mlx5_eswitch *peer_esw;
1631 
1632         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1633         if (!peer_esw)
1634                 return;
1635 
1636         __mlx5e_tc_del_fdb_peer_flow(flow);
1637         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1638 }
1639 
1640 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1641                               struct mlx5e_tc_flow *flow)
1642 {
1643         if (mlx5e_is_eswitch_flow(flow)) {
1644                 mlx5e_tc_del_fdb_peer_flow(flow);
1645                 mlx5e_tc_del_fdb_flow(priv, flow);
1646         } else {
1647                 mlx5e_tc_del_nic_flow(priv, flow);
1648         }
1649 }
1650 
1651 
1652 static int parse_tunnel_attr(struct mlx5e_priv *priv,
1653                              struct mlx5_flow_spec *spec,
1654                              struct flow_cls_offload *f,
1655                              struct net_device *filter_dev, u8 *match_level)
1656 {
1657         struct netlink_ext_ack *extack = f->common.extack;
1658         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1659                                        outer_headers);
1660         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1661                                        outer_headers);
1662         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1663         int err;
1664 
1665         err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1666                                  headers_c, headers_v, match_level);
1667         if (err) {
1668                 NL_SET_ERR_MSG_MOD(extack,
1669                                    "failed to parse tunnel attributes");
1670                 return err;
1671         }
1672 
1673         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1674                 struct flow_match_control match;
1675                 u16 addr_type;
1676 
1677                 flow_rule_match_enc_control(rule, &match);
1678                 addr_type = match.key->addr_type;
1679 
1680                 /* For tunnel addr_type used same key id`s as for non-tunnel */
1681                 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1682                         struct flow_match_ipv4_addrs match;
1683 
1684                         flow_rule_match_enc_ipv4_addrs(rule, &match);
1685                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1686                                  src_ipv4_src_ipv6.ipv4_layout.ipv4,
1687                                  ntohl(match.mask->src));
1688                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1689                                  src_ipv4_src_ipv6.ipv4_layout.ipv4,
1690                                  ntohl(match.key->src));
1691 
1692                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1693                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1694                                  ntohl(match.mask->dst));
1695                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1696                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1697                                  ntohl(match.key->dst));
1698 
1699                         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c,
1700                                          ethertype);
1701                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1702                                  ETH_P_IP);
1703                 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1704                         struct flow_match_ipv6_addrs match;
1705 
1706                         flow_rule_match_enc_ipv6_addrs(rule, &match);
1707                         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1708                                             src_ipv4_src_ipv6.ipv6_layout.ipv6),
1709                                &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout,
1710                                                                    ipv6));
1711                         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1712                                             src_ipv4_src_ipv6.ipv6_layout.ipv6),
1713                                &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout,
1714                                                                   ipv6));
1715 
1716                         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1717                                             dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1718                                &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout,
1719                                                                    ipv6));
1720                         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1721                                             dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1722                                &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout,
1723                                                                   ipv6));
1724 
1725                         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c,
1726                                          ethertype);
1727                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1728                                  ETH_P_IPV6);
1729                 }
1730         }
1731 
1732         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1733                 struct flow_match_ip match;
1734 
1735                 flow_rule_match_enc_ip(rule, &match);
1736                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1737                          match.mask->tos & 0x3);
1738                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1739                          match.key->tos & 0x3);
1740 
1741                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1742                          match.mask->tos >> 2);
1743                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1744                          match.key->tos  >> 2);
1745 
1746                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1747                          match.mask->ttl);
1748                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1749                          match.key->ttl);
1750 
1751                 if (match.mask->ttl &&
1752                     !MLX5_CAP_ESW_FLOWTABLE_FDB
1753                         (priv->mdev,
1754                          ft_field_support.outer_ipv4_ttl)) {
1755                         NL_SET_ERR_MSG_MOD(extack,
1756                                            "Matching on TTL is not supported");
1757                         return -EOPNOTSUPP;
1758                 }
1759 
1760         }
1761 
1762         /* Enforce DMAC when offloading incoming tunneled flows.
1763          * Flow counters require a match on the DMAC.
1764          */
1765         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1766         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1767         ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1768                                      dmac_47_16), priv->netdev->dev_addr);
1769 
1770         /* let software handle IP fragments */
1771         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1772         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1773 
1774         return 0;
1775 }
1776 
1777 static void *get_match_headers_criteria(u32 flags,
1778                                         struct mlx5_flow_spec *spec)
1779 {
1780         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1781                 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1782                              inner_headers) :
1783                 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1784                              outer_headers);
1785 }
1786 
1787 static void *get_match_headers_value(u32 flags,
1788                                      struct mlx5_flow_spec *spec)
1789 {
1790         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1791                 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1792                              inner_headers) :
1793                 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1794                              outer_headers);
1795 }
1796 
1797 static int __parse_cls_flower(struct mlx5e_priv *priv,
1798                               struct mlx5_flow_spec *spec,
1799                               struct flow_cls_offload *f,
1800                               struct net_device *filter_dev,
1801                               u8 *inner_match_level, u8 *outer_match_level)
1802 {
1803         struct netlink_ext_ack *extack = f->common.extack;
1804         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1805                                        outer_headers);
1806         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1807                                        outer_headers);
1808         void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1809                                     misc_parameters);
1810         void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1811                                     misc_parameters);
1812         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1813         struct flow_dissector *dissector = rule->match.dissector;
1814         u16 addr_type = 0;
1815         u8 ip_proto = 0;
1816         u8 *match_level;
1817 
1818         match_level = outer_match_level;
1819 
1820         if (dissector->used_keys &
1821             ~(BIT(FLOW_DISSECTOR_KEY_META) |
1822               BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1823               BIT(FLOW_DISSECTOR_KEY_BASIC) |
1824               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
1825               BIT(FLOW_DISSECTOR_KEY_VLAN) |
1826               BIT(FLOW_DISSECTOR_KEY_CVLAN) |
1827               BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1828               BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
1829               BIT(FLOW_DISSECTOR_KEY_PORTS) |
1830               BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1831               BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1832               BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1833               BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
1834               BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
1835               BIT(FLOW_DISSECTOR_KEY_TCP) |
1836               BIT(FLOW_DISSECTOR_KEY_IP)  |
1837               BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1838               BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
1839                 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
1840                 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1841                             dissector->used_keys);
1842                 return -EOPNOTSUPP;
1843         }
1844 
1845         if (mlx5e_get_tc_tun(filter_dev)) {
1846                 if (parse_tunnel_attr(priv, spec, f, filter_dev,
1847                                       outer_match_level))
1848                         return -EOPNOTSUPP;
1849 
1850                 /* At this point, header pointers should point to the inner
1851                  * headers, outer header were already set by parse_tunnel_attr
1852                  */
1853                 match_level = inner_match_level;
1854                 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1855                                                        spec);
1856                 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1857                                                     spec);
1858         }
1859 
1860         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1861                 struct flow_match_basic match;
1862 
1863                 flow_rule_match_basic(rule, &match);
1864                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1865                          ntohs(match.mask->n_proto));
1866                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1867                          ntohs(match.key->n_proto));
1868 
1869                 if (match.mask->n_proto)
1870                         *match_level = MLX5_MATCH_L2;
1871         }
1872         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1873             is_vlan_dev(filter_dev)) {
1874                 struct flow_dissector_key_vlan filter_dev_mask;
1875                 struct flow_dissector_key_vlan filter_dev_key;
1876                 struct flow_match_vlan match;
1877 
1878                 if (is_vlan_dev(filter_dev)) {
1879                         match.key = &filter_dev_key;
1880                         match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1881                         match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1882                         match.key->vlan_priority = 0;
1883                         match.mask = &filter_dev_mask;
1884                         memset(match.mask, 0xff, sizeof(*match.mask));
1885                         match.mask->vlan_priority = 0;
1886                 } else {
1887                         flow_rule_match_vlan(rule, &match);
1888                 }
1889                 if (match.mask->vlan_id ||
1890                     match.mask->vlan_priority ||
1891                     match.mask->vlan_tpid) {
1892                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
1893                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1894                                          svlan_tag, 1);
1895                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1896                                          svlan_tag, 1);
1897                         } else {
1898                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1899                                          cvlan_tag, 1);
1900                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1901                                          cvlan_tag, 1);
1902                         }
1903 
1904                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1905                                  match.mask->vlan_id);
1906                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1907                                  match.key->vlan_id);
1908 
1909                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1910                                  match.mask->vlan_priority);
1911                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1912                                  match.key->vlan_priority);
1913 
1914                         *match_level = MLX5_MATCH_L2;
1915                 }
1916         } else if (*match_level != MLX5_MATCH_NONE) {
1917                 /* cvlan_tag enabled in match criteria and
1918                  * disabled in match value means both S & C tags
1919                  * don't exist (untagged of both)
1920                  */
1921                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1922                 *match_level = MLX5_MATCH_L2;
1923         }
1924 
1925         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1926                 struct flow_match_vlan match;
1927 
1928                 flow_rule_match_cvlan(rule, &match);
1929                 if (match.mask->vlan_id ||
1930                     match.mask->vlan_priority ||
1931                     match.mask->vlan_tpid) {
1932                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
1933                                 MLX5_SET(fte_match_set_misc, misc_c,
1934                                          outer_second_svlan_tag, 1);
1935                                 MLX5_SET(fte_match_set_misc, misc_v,
1936                                          outer_second_svlan_tag, 1);
1937                         } else {
1938                                 MLX5_SET(fte_match_set_misc, misc_c,
1939                                          outer_second_cvlan_tag, 1);
1940                                 MLX5_SET(fte_match_set_misc, misc_v,
1941                                          outer_second_cvlan_tag, 1);
1942                         }
1943 
1944                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1945                                  match.mask->vlan_id);
1946                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1947                                  match.key->vlan_id);
1948                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1949                                  match.mask->vlan_priority);
1950                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1951                                  match.key->vlan_priority);
1952 
1953                         *match_level = MLX5_MATCH_L2;
1954                 }
1955         }
1956 
1957         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1958                 struct flow_match_eth_addrs match;
1959 
1960                 flow_rule_match_eth_addrs(rule, &match);
1961                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1962                                              dmac_47_16),
1963                                 match.mask->dst);
1964                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1965                                              dmac_47_16),
1966                                 match.key->dst);
1967 
1968                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1969                                              smac_47_16),
1970                                 match.mask->src);
1971                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1972                                              smac_47_16),
1973                                 match.key->src);
1974 
1975                 if (!is_zero_ether_addr(match.mask->src) ||
1976                     !is_zero_ether_addr(match.mask->dst))
1977                         *match_level = MLX5_MATCH_L2;
1978         }
1979 
1980         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
1981                 struct flow_match_control match;
1982 
1983                 flow_rule_match_control(rule, &match);
1984                 addr_type = match.key->addr_type;
1985 
1986                 /* the HW doesn't support frag first/later */
1987                 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
1988                         return -EOPNOTSUPP;
1989 
1990                 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
1991                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1992                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1993                                  match.key->flags & FLOW_DIS_IS_FRAGMENT);
1994 
1995                         /* the HW doesn't need L3 inline to match on frag=no */
1996                         if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
1997                                 *match_level = MLX5_MATCH_L2;
1998         /* ***  L2 attributes parsing up to here *** */
1999                         else
2000                                 *match_level = MLX5_MATCH_L3;
2001                 }
2002         }
2003 
2004         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2005                 struct flow_match_basic match;
2006 
2007                 flow_rule_match_basic(rule, &match);
2008                 ip_proto = match.key->ip_proto;
2009 
2010                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2011                          match.mask->ip_proto);
2012                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2013                          match.key->ip_proto);
2014 
2015                 if (match.mask->ip_proto)
2016                         *match_level = MLX5_MATCH_L3;
2017         }
2018 
2019         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
2020                 struct flow_match_ipv4_addrs match;
2021 
2022                 flow_rule_match_ipv4_addrs(rule, &match);
2023                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2024                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2025                        &match.mask->src, sizeof(match.mask->src));
2026                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2027                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2028                        &match.key->src, sizeof(match.key->src));
2029                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2030                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2031                        &match.mask->dst, sizeof(match.mask->dst));
2032                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2033                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2034                        &match.key->dst, sizeof(match.key->dst));
2035 
2036                 if (match.mask->src || match.mask->dst)
2037                         *match_level = MLX5_MATCH_L3;
2038         }
2039 
2040         if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
2041                 struct flow_match_ipv6_addrs match;
2042 
2043                 flow_rule_match_ipv6_addrs(rule, &match);
2044                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2045                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2046                        &match.mask->src, sizeof(match.mask->src));
2047                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2048                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2049                        &match.key->src, sizeof(match.key->src));
2050 
2051                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2052                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2053                        &match.mask->dst, sizeof(match.mask->dst));
2054                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2055                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2056                        &match.key->dst, sizeof(match.key->dst));
2057 
2058                 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2059                     ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
2060                         *match_level = MLX5_MATCH_L3;
2061         }
2062 
2063         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2064                 struct flow_match_ip match;
2065 
2066                 flow_rule_match_ip(rule, &match);
2067                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2068                          match.mask->tos & 0x3);
2069                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2070                          match.key->tos & 0x3);
2071 
2072                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2073                          match.mask->tos >> 2);
2074                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2075                          match.key->tos  >> 2);
2076 
2077                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2078                          match.mask->ttl);
2079                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2080                          match.key->ttl);
2081 
2082                 if (match.mask->ttl &&
2083                     !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
2084                                                 ft_field_support.outer_ipv4_ttl)) {
2085                         NL_SET_ERR_MSG_MOD(extack,
2086                                            "Matching on TTL is not supported");
2087                         return -EOPNOTSUPP;
2088                 }
2089 
2090                 if (match.mask->tos || match.mask->ttl)
2091                         *match_level = MLX5_MATCH_L3;
2092         }
2093 
2094         /* ***  L3 attributes parsing up to here *** */
2095 
2096         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2097                 struct flow_match_ports match;
2098 
2099                 flow_rule_match_ports(rule, &match);
2100                 switch (ip_proto) {
2101                 case IPPROTO_TCP:
2102                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2103                                  tcp_sport, ntohs(match.mask->src));
2104                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2105                                  tcp_sport, ntohs(match.key->src));
2106 
2107                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2108                                  tcp_dport, ntohs(match.mask->dst));
2109                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2110                                  tcp_dport, ntohs(match.key->dst));
2111                         break;
2112 
2113                 case IPPROTO_UDP:
2114                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2115                                  udp_sport, ntohs(match.mask->src));
2116                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2117                                  udp_sport, ntohs(match.key->src));
2118 
2119                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2120                                  udp_dport, ntohs(match.mask->dst));
2121                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2122                                  udp_dport, ntohs(match.key->dst));
2123                         break;
2124                 default:
2125                         NL_SET_ERR_MSG_MOD(extack,
2126                                            "Only UDP and TCP transports are supported for L4 matching");
2127                         netdev_err(priv->netdev,
2128                                    "Only UDP and TCP transport are supported\n");
2129                         return -EINVAL;
2130                 }
2131 
2132                 if (match.mask->src || match.mask->dst)
2133                         *match_level = MLX5_MATCH_L4;
2134         }
2135 
2136         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2137                 struct flow_match_tcp match;
2138 
2139                 flow_rule_match_tcp(rule, &match);
2140                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
2141                          ntohs(match.mask->flags));
2142                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
2143                          ntohs(match.key->flags));
2144 
2145                 if (match.mask->flags)
2146                         *match_level = MLX5_MATCH_L4;
2147         }
2148 
2149         return 0;
2150 }
2151 
2152 static int parse_cls_flower(struct mlx5e_priv *priv,
2153                             struct mlx5e_tc_flow *flow,
2154                             struct mlx5_flow_spec *spec,
2155                             struct flow_cls_offload *f,
2156                             struct net_device *filter_dev)
2157 {
2158         u8 inner_match_level, outer_match_level, non_tunnel_match_level;
2159         struct netlink_ext_ack *extack = f->common.extack;
2160         struct mlx5_core_dev *dev = priv->mdev;
2161         struct mlx5_eswitch *esw = dev->priv.eswitch;
2162         struct mlx5e_rep_priv *rpriv = priv->ppriv;
2163         struct mlx5_eswitch_rep *rep;
2164         bool is_eswitch_flow;
2165         int err;
2166 
2167         inner_match_level = MLX5_MATCH_NONE;
2168         outer_match_level = MLX5_MATCH_NONE;
2169 
2170         err = __parse_cls_flower(priv, spec, f, filter_dev, &inner_match_level,
2171                                  &outer_match_level);
2172         non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2173                                  outer_match_level : inner_match_level;
2174 
2175         is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2176         if (!err && is_eswitch_flow) {
2177                 rep = rpriv->rep;
2178                 if (rep->vport != MLX5_VPORT_UPLINK &&
2179                     (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
2180                     esw->offloads.inline_mode < non_tunnel_match_level)) {
2181                         NL_SET_ERR_MSG_MOD(extack,
2182                                            "Flow is not offloaded due to min inline setting");
2183                         netdev_warn(priv->netdev,
2184                                     "Flow is not offloaded due to min inline setting, required %d actual %d\n",
2185                                     non_tunnel_match_level, esw->offloads.inline_mode);
2186                         return -EOPNOTSUPP;
2187                 }
2188         }
2189 
2190         if (is_eswitch_flow) {
2191                 flow->esw_attr->inner_match_level = inner_match_level;
2192                 flow->esw_attr->outer_match_level = outer_match_level;
2193         } else {
2194                 flow->nic_attr->match_level = non_tunnel_match_level;
2195         }
2196 
2197         return err;
2198 }
2199 
2200 struct pedit_headers {
2201         struct ethhdr  eth;
2202         struct vlan_hdr vlan;
2203         struct iphdr   ip4;
2204         struct ipv6hdr ip6;
2205         struct tcphdr  tcp;
2206         struct udphdr  udp;
2207 };
2208 
2209 struct pedit_headers_action {
2210         struct pedit_headers    vals;
2211         struct pedit_headers    masks;
2212         u32                     pedits;
2213 };
2214 
2215 static int pedit_header_offsets[] = {
2216         [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2217         [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2218         [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2219         [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2220         [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
2221 };
2222 
2223 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2224 
2225 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
2226                          struct pedit_headers_action *hdrs)
2227 {
2228         u32 *curr_pmask, *curr_pval;
2229 
2230         curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2231         curr_pval  = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
2232 
2233         if (*curr_pmask & mask)  /* disallow acting twice on the same location */
2234                 goto out_err;
2235 
2236         *curr_pmask |= mask;
2237         *curr_pval  |= (val & mask);
2238 
2239         return 0;
2240 
2241 out_err:
2242         return -EOPNOTSUPP;
2243 }
2244 
2245 struct mlx5_fields {
2246         u8  field;
2247         u8  size;
2248         u32 offset;
2249         u32 match_offset;
2250 };
2251 
2252 #define OFFLOAD(fw_field, size, field, off, match_field) \
2253                 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, \
2254                  offsetof(struct pedit_headers, field) + (off), \
2255                  MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2256 
2257 /* masked values are the same and there are no rewrites that do not have a
2258  * match.
2259  */
2260 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2261         type matchmaskx = *(type *)(matchmaskp); \
2262         type matchvalx = *(type *)(matchvalp); \
2263         type maskx = *(type *)(maskp); \
2264         type valx = *(type *)(valp); \
2265         \
2266         (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2267                                                                  matchmaskx)); \
2268 })
2269 
2270 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
2271                          void *matchmaskp, int size)
2272 {
2273         bool same = false;
2274 
2275         switch (size) {
2276         case sizeof(u8):
2277                 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
2278                 break;
2279         case sizeof(u16):
2280                 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
2281                 break;
2282         case sizeof(u32):
2283                 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
2284                 break;
2285         }
2286 
2287         return same;
2288 }
2289 
2290 static struct mlx5_fields fields[] = {
2291         OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0, dmac_47_16),
2292         OFFLOAD(DMAC_15_0,  2, eth.h_dest[4], 0, dmac_15_0),
2293         OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0, smac_47_16),
2294         OFFLOAD(SMAC_15_0,  2, eth.h_source[4], 0, smac_15_0),
2295         OFFLOAD(ETHERTYPE,  2, eth.h_proto, 0, ethertype),
2296         OFFLOAD(FIRST_VID,  2, vlan.h_vlan_TCI, 0, first_vid),
2297 
2298         OFFLOAD(IP_TTL, 1, ip4.ttl,   0, ttl_hoplimit),
2299         OFFLOAD(SIPV4,  4, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2300         OFFLOAD(DIPV4,  4, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2301 
2302         OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0,
2303                 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
2304         OFFLOAD(SIPV6_95_64,  4, ip6.saddr.s6_addr32[1], 0,
2305                 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
2306         OFFLOAD(SIPV6_63_32,  4, ip6.saddr.s6_addr32[2], 0,
2307                 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
2308         OFFLOAD(SIPV6_31_0,   4, ip6.saddr.s6_addr32[3], 0,
2309                 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
2310         OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0,
2311                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
2312         OFFLOAD(DIPV6_95_64,  4, ip6.daddr.s6_addr32[1], 0,
2313                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
2314         OFFLOAD(DIPV6_63_32,  4, ip6.daddr.s6_addr32[2], 0,
2315                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
2316         OFFLOAD(DIPV6_31_0,   4, ip6.daddr.s6_addr32[3], 0,
2317                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
2318         OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0, ttl_hoplimit),
2319 
2320         OFFLOAD(TCP_SPORT, 2, tcp.source,  0, tcp_sport),
2321         OFFLOAD(TCP_DPORT, 2, tcp.dest,    0, tcp_dport),
2322         OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5, tcp_flags),
2323 
2324         OFFLOAD(UDP_SPORT, 2, udp.source, 0, udp_sport),
2325         OFFLOAD(UDP_DPORT, 2, udp.dest,   0, udp_dport),
2326 };
2327 
2328 /* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
2329  * max from the SW pedit action. On success, attr->num_mod_hdr_actions
2330  * says how many HW actions were actually parsed.
2331  */
2332 static int offload_pedit_fields(struct pedit_headers_action *hdrs,
2333                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2334                                 u32 *action_flags,
2335                                 struct netlink_ext_ack *extack)
2336 {
2337         struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2338         void *headers_c = get_match_headers_criteria(*action_flags,
2339                                                      &parse_attr->spec);
2340         void *headers_v = get_match_headers_value(*action_flags,
2341                                                   &parse_attr->spec);
2342         int i, action_size, nactions, max_actions, first, last, next_z;
2343         void *s_masks_p, *a_masks_p, *vals_p;
2344         struct mlx5_fields *f;
2345         u8 cmd, field_bsize;
2346         u32 s_mask, a_mask;
2347         unsigned long mask;
2348         __be32 mask_be32;
2349         __be16 mask_be16;
2350         void *action;
2351 
2352         set_masks = &hdrs[0].masks;
2353         add_masks = &hdrs[1].masks;
2354         set_vals = &hdrs[0].vals;
2355         add_vals = &hdrs[1].vals;
2356 
2357         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2358         action = parse_attr->mod_hdr_actions +
2359                  parse_attr->num_mod_hdr_actions * action_size;
2360 
2361         max_actions = parse_attr->max_mod_hdr_actions;
2362         nactions = parse_attr->num_mod_hdr_actions;
2363 
2364         for (i = 0; i < ARRAY_SIZE(fields); i++) {
2365                 bool skip;
2366 
2367                 f = &fields[i];
2368                 /* avoid seeing bits set from previous iterations */
2369                 s_mask = 0;
2370                 a_mask = 0;
2371 
2372                 s_masks_p = (void *)set_masks + f->offset;
2373                 a_masks_p = (void *)add_masks + f->offset;
2374 
2375                 memcpy(&s_mask, s_masks_p, f->size);
2376                 memcpy(&a_mask, a_masks_p, f->size);
2377 
2378                 if (!s_mask && !a_mask) /* nothing to offload here */
2379                         continue;
2380 
2381                 if (s_mask && a_mask) {
2382                         NL_SET_ERR_MSG_MOD(extack,
2383                                            "can't set and add to the same HW field");
2384                         printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2385                         return -EOPNOTSUPP;
2386                 }
2387 
2388                 if (nactions == max_actions) {
2389                         NL_SET_ERR_MSG_MOD(extack,
2390                                            "too many pedit actions, can't offload");
2391                         printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2392                         return -EOPNOTSUPP;
2393                 }
2394 
2395                 skip = false;
2396                 if (s_mask) {
2397                         void *match_mask = headers_c + f->match_offset;
2398                         void *match_val = headers_v + f->match_offset;
2399 
2400                         cmd  = MLX5_ACTION_TYPE_SET;
2401                         mask = s_mask;
2402                         vals_p = (void *)set_vals + f->offset;
2403                         /* don't rewrite if we have a match on the same value */
2404                         if (cmp_val_mask(vals_p, s_masks_p, match_val,
2405                                          match_mask, f->size))
2406                                 skip = true;
2407                         /* clear to denote we consumed this field */
2408                         memset(s_masks_p, 0, f->size);
2409                 } else {
2410                         u32 zero = 0;
2411 
2412                         cmd  = MLX5_ACTION_TYPE_ADD;
2413                         mask = a_mask;
2414                         vals_p = (void *)add_vals + f->offset;
2415                         /* add 0 is no change */
2416                         if (!memcmp(vals_p, &zero, f->size))
2417                                 skip = true;
2418                         /* clear to denote we consumed this field */
2419                         memset(a_masks_p, 0, f->size);
2420                 }
2421                 if (skip)
2422                         continue;
2423 
2424                 field_bsize = f->size * BITS_PER_BYTE;
2425 
2426                 if (field_bsize == 32) {
2427                         mask_be32 = *(__be32 *)&mask;
2428                         mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2429                 } else if (field_bsize == 16) {
2430                         mask_be16 = *(__be16 *)&mask;
2431                         mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2432                 }
2433 
2434                 first = find_first_bit(&mask, field_bsize);
2435                 next_z = find_next_zero_bit(&mask, field_bsize, first);
2436                 last  = find_last_bit(&mask, field_bsize);
2437                 if (first < next_z && next_z < last) {
2438                         NL_SET_ERR_MSG_MOD(extack,
2439                                            "rewrite of few sub-fields isn't supported");
2440                         printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2441                                mask);
2442                         return -EOPNOTSUPP;
2443                 }
2444 
2445                 MLX5_SET(set_action_in, action, action_type, cmd);
2446                 MLX5_SET(set_action_in, action, field, f->field);
2447 
2448                 if (cmd == MLX5_ACTION_TYPE_SET) {
2449                         MLX5_SET(set_action_in, action, offset, first);
2450                         /* length is num of bits to be written, zero means length of 32 */
2451                         MLX5_SET(set_action_in, action, length, (last - first + 1));
2452                 }
2453 
2454                 if (field_bsize == 32)
2455                         MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
2456                 else if (field_bsize == 16)
2457                         MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
2458                 else if (field_bsize == 8)
2459                         MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
2460 
2461                 action += action_size;
2462                 nactions++;
2463         }
2464 
2465         parse_attr->num_mod_hdr_actions = nactions;
2466         return 0;
2467 }
2468 
2469 static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2470                                                   int namespace)
2471 {
2472         if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2473                 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2474         else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2475                 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2476 }
2477 
2478 static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
2479                                  struct pedit_headers_action *hdrs,
2480                                  int namespace,
2481                                  struct mlx5e_tc_flow_parse_attr *parse_attr)
2482 {
2483         int nkeys, action_size, max_actions;
2484 
2485         nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2486                 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
2487         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2488 
2489         max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
2490         /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2491         max_actions = min(max_actions, nkeys * 16);
2492 
2493         parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2494         if (!parse_attr->mod_hdr_actions)
2495                 return -ENOMEM;
2496 
2497         parse_attr->max_mod_hdr_actions = max_actions;
2498         return 0;
2499 }
2500 
2501 static const struct pedit_headers zero_masks = {};
2502 
2503 static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2504                                  const struct flow_action_entry *act, int namespace,
2505                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2506                                  struct pedit_headers_action *hdrs,
2507                                  struct netlink_ext_ack *extack)
2508 {
2509         u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2510         int err = -EOPNOTSUPP;
2511         u32 mask, val, offset;
2512         u8 htype;
2513 
2514         htype = act->mangle.htype;
2515         err = -EOPNOTSUPP; /* can't be all optimistic */
2516 
2517         if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2518                 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2519                 goto out_err;
2520         }
2521 
2522         if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2523                 NL_SET_ERR_MSG_MOD(extack,
2524                                    "The pedit offload action is not supported");
2525                 goto out_err;
2526         }
2527 
2528         mask = act->mangle.mask;
2529         val = act->mangle.val;
2530         offset = act->mangle.offset;
2531 
2532         err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2533         if (err)
2534                 goto out_err;
2535 
2536         hdrs[cmd].pedits++;
2537 
2538         return 0;
2539 out_err:
2540         return err;
2541 }
2542 
2543 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2544                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2545                                  struct pedit_headers_action *hdrs,
2546                                  u32 *action_flags,
2547                                  struct netlink_ext_ack *extack)
2548 {
2549         struct pedit_headers *cmd_masks;
2550         int err;
2551         u8 cmd;
2552 
2553         if (!parse_attr->mod_hdr_actions) {
2554                 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
2555                 if (err)
2556                         goto out_err;
2557         }
2558 
2559         err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
2560         if (err < 0)
2561                 goto out_dealloc_parsed_actions;
2562 
2563         for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2564                 cmd_masks = &hdrs[cmd].masks;
2565                 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
2566                         NL_SET_ERR_MSG_MOD(extack,
2567                                            "attempt to offload an unsupported field");
2568                         netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
2569                         print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2570                                        16, 1, cmd_masks, sizeof(zero_masks), true);
2571                         err = -EOPNOTSUPP;
2572                         goto out_dealloc_parsed_actions;
2573                 }
2574         }
2575 
2576         return 0;
2577 
2578 out_dealloc_parsed_actions:
2579         kfree(parse_attr->mod_hdr_actions);
2580 out_err:
2581         return err;
2582 }
2583 
2584 static bool csum_offload_supported(struct mlx5e_priv *priv,
2585                                    u32 action,
2586                                    u32 update_flags,
2587                                    struct netlink_ext_ack *extack)
2588 {
2589         u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2590                          TCA_CSUM_UPDATE_FLAG_UDP;
2591 
2592         /*  The HW recalcs checksums only if re-writing headers */
2593         if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
2594                 NL_SET_ERR_MSG_MOD(extack,
2595                                    "TC csum action is only offloaded with pedit");
2596                 netdev_warn(priv->netdev,
2597                             "TC csum action is only offloaded with pedit\n");
2598                 return false;
2599         }
2600 
2601         if (update_flags & ~prot_flags) {
2602                 NL_SET_ERR_MSG_MOD(extack,
2603                                    "can't offload TC csum action for some header/s");
2604                 netdev_warn(priv->netdev,
2605                             "can't offload TC csum action for some header/s - flags %#x\n",
2606                             update_flags);
2607                 return false;
2608         }
2609 
2610         return true;
2611 }
2612 
2613 struct ip_ttl_word {
2614         __u8    ttl;
2615         __u8    protocol;
2616         __sum16 check;
2617 };
2618 
2619 struct ipv6_hoplimit_word {
2620         __be16  payload_len;
2621         __u8    nexthdr;
2622         __u8    hop_limit;
2623 };
2624 
2625 static bool is_action_keys_supported(const struct flow_action_entry *act)
2626 {
2627         u32 mask, offset;
2628         u8 htype;
2629 
2630         htype = act->mangle.htype;
2631         offset = act->mangle.offset;
2632         mask = ~act->mangle.mask;
2633         /* For IPv4 & IPv6 header check 4 byte word,
2634          * to determine that modified fields
2635          * are NOT ttl & hop_limit only.
2636          */
2637         if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2638                 struct ip_ttl_word *ttl_word =
2639                         (struct ip_ttl_word *)&mask;
2640 
2641                 if (offset != offsetof(struct iphdr, ttl) ||
2642                     ttl_word->protocol ||
2643                     ttl_word->check) {
2644                         return true;
2645                 }
2646         } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2647                 struct ipv6_hoplimit_word *hoplimit_word =
2648                         (struct ipv6_hoplimit_word *)&mask;
2649 
2650                 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2651                     hoplimit_word->payload_len ||
2652                     hoplimit_word->nexthdr) {
2653                         return true;
2654                 }
2655         }
2656         return false;
2657 }
2658 
2659 static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
2660                                           struct flow_action *flow_action,
2661                                           u32 actions,
2662                                           struct netlink_ext_ack *extack)
2663 {
2664         const struct flow_action_entry *act;
2665         bool modify_ip_header;
2666         void *headers_v;
2667         u16 ethertype;
2668         u8 ip_proto;
2669         int i;
2670 
2671         headers_v = get_match_headers_value(actions, spec);
2672         ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2673 
2674         /* for non-IP we only re-write MACs, so we're okay */
2675         if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2676                 goto out_ok;
2677 
2678         modify_ip_header = false;
2679         flow_action_for_each(i, act, flow_action) {
2680                 if (act->id != FLOW_ACTION_MANGLE &&
2681                     act->id != FLOW_ACTION_ADD)
2682                         continue;
2683 
2684                 if (is_action_keys_supported(act)) {
2685                         modify_ip_header = true;
2686                         break;
2687                 }
2688         }
2689 
2690         ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
2691         if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2692             ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
2693                 NL_SET_ERR_MSG_MOD(extack,
2694                                    "can't offload re-write of non TCP/UDP");
2695                 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2696                 return false;
2697         }
2698 
2699 out_ok:
2700         return true;
2701 }
2702 
2703 static bool actions_match_supported(struct mlx5e_priv *priv,
2704                                     struct flow_action *flow_action,
2705                                     struct mlx5e_tc_flow_parse_attr *parse_attr,
2706                                     struct mlx5e_tc_flow *flow,
2707                                     struct netlink_ext_ack *extack)
2708 {
2709         u32 actions;
2710 
2711         if (mlx5e_is_eswitch_flow(flow))
2712                 actions = flow->esw_attr->action;
2713         else
2714                 actions = flow->nic_attr->action;
2715 
2716         if (flow_flag_test(flow, EGRESS) &&
2717             !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
2718               (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
2719               (actions & MLX5_FLOW_CONTEXT_ACTION_DROP)))
2720                 return false;
2721 
2722         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2723                 return modify_header_match_supported(&parse_attr->spec,
2724                                                      flow_action, actions,
2725                                                      extack);
2726 
2727         return true;
2728 }
2729 
2730 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2731 {
2732         struct mlx5_core_dev *fmdev, *pmdev;
2733         u64 fsystem_guid, psystem_guid;
2734 
2735         fmdev = priv->mdev;
2736         pmdev = peer_priv->mdev;
2737 
2738         fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2739         psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
2740 
2741         return (fsystem_guid == psystem_guid);
2742 }
2743 
2744 static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2745                                    const struct flow_action_entry *act,
2746                                    struct mlx5e_tc_flow_parse_attr *parse_attr,
2747                                    struct pedit_headers_action *hdrs,
2748                                    u32 *action, struct netlink_ext_ack *extack)
2749 {
2750         u16 mask16 = VLAN_VID_MASK;
2751         u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2752         const struct flow_action_entry pedit_act = {
2753                 .id = FLOW_ACTION_MANGLE,
2754                 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2755                 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2756                 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2757                 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2758         };
2759         u8 match_prio_mask, match_prio_val;
2760         void *headers_c, *headers_v;
2761         int err;
2762 
2763         headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2764         headers_v = get_match_headers_value(*action, &parse_attr->spec);
2765 
2766         if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2767               MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2768                 NL_SET_ERR_MSG_MOD(extack,
2769                                    "VLAN rewrite action must have VLAN protocol match");
2770                 return -EOPNOTSUPP;
2771         }
2772 
2773         match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2774         match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2775         if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2776                 NL_SET_ERR_MSG_MOD(extack,
2777                                    "Changing VLAN prio is not supported");
2778                 return -EOPNOTSUPP;
2779         }
2780 
2781         err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr,
2782                                     hdrs, NULL);
2783         *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2784 
2785         return err;
2786 }
2787 
2788 static int
2789 add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
2790                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2791                                  struct pedit_headers_action *hdrs,
2792                                  u32 *action, struct netlink_ext_ack *extack)
2793 {
2794         const struct flow_action_entry prio_tag_act = {
2795                 .vlan.vid = 0,
2796                 .vlan.prio =
2797                         MLX5_GET(fte_match_set_lyr_2_4,
2798                                  get_match_headers_value(*action,
2799                                                          &parse_attr->spec),
2800                                  first_prio) &
2801                         MLX5_GET(fte_match_set_lyr_2_4,
2802                                  get_match_headers_criteria(*action,
2803                                                             &parse_attr->spec),
2804                                  first_prio),
2805         };
2806 
2807         return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
2808                                        &prio_tag_act, parse_attr, hdrs, action,
2809                                        extack);
2810 }
2811 
2812 static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2813                                 struct flow_action *flow_action,
2814                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2815                                 struct mlx5e_tc_flow *flow,
2816                                 struct netlink_ext_ack *extack)
2817 {
2818         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
2819         struct pedit_headers_action hdrs[2] = {};
2820         const struct flow_action_entry *act;
2821         u32 action = 0;
2822         int err, i;
2823 
2824         if (!flow_action_has_entries(flow_action))
2825                 return -EINVAL;
2826 
2827         attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2828 
2829         flow_action_for_each(i, act, flow_action) {
2830                 switch (act->id) {
2831                 case FLOW_ACTION_DROP:
2832                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2833                         if (MLX5_CAP_FLOWTABLE(priv->mdev,
2834                                                flow_table_properties_nic_receive.flow_counter))
2835                                 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2836                         break;
2837                 case FLOW_ACTION_MANGLE:
2838                 case FLOW_ACTION_ADD:
2839                         err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
2840                                                     parse_attr, hdrs, extack);
2841                         if (err)
2842                                 return err;
2843 
2844                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2845                                   MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2846                         break;
2847                 case FLOW_ACTION_VLAN_MANGLE:
2848                         err = add_vlan_rewrite_action(priv,
2849                                                       MLX5_FLOW_NAMESPACE_KERNEL,
2850                                                       act, parse_attr, hdrs,
2851                                                       &action, extack);
2852                         if (err)
2853                                 return err;
2854 
2855                         break;
2856                 case FLOW_ACTION_CSUM:
2857                         if (csum_offload_supported(priv, action,
2858                                                    act->csum_flags,
2859                                                    extack))
2860                                 break;
2861 
2862                         return -EOPNOTSUPP;
2863                 case FLOW_ACTION_REDIRECT: {
2864                         struct net_device *peer_dev = act->dev;
2865 
2866                         if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2867                             same_hw_devs(priv, netdev_priv(peer_dev))) {
2868                                 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
2869                                 flow_flag_set(flow, HAIRPIN);
2870                                 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2871                                           MLX5_FLOW_CONTEXT_ACTION_COUNT;
2872                         } else {
2873                                 NL_SET_ERR_MSG_MOD(extack,
2874                                                    "device is not on same HW, can't offload");
2875                                 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2876                                             peer_dev->name);
2877                                 return -EINVAL;
2878                         }
2879                         }
2880                         break;
2881                 case FLOW_ACTION_MARK: {
2882                         u32 mark = act->mark;
2883 
2884                         if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
2885                                 NL_SET_ERR_MSG_MOD(extack,
2886                                                    "Bad flow mark - only 16 bit is supported");
2887                                 return -EINVAL;
2888                         }
2889 
2890                         attr->flow_tag = mark;
2891                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2892                         }
2893                         break;
2894                 default:
2895                         NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2896                         return -EOPNOTSUPP;
2897                 }
2898         }
2899 
2900         if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2901             hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2902                 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
2903                                             parse_attr, hdrs, &action, extack);
2904                 if (err)
2905                         return err;
2906                 /* in case all pedit actions are skipped, remove the MOD_HDR
2907                  * flag.
2908                  */
2909                 if (parse_attr->num_mod_hdr_actions == 0) {
2910                         action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2911                         kfree(parse_attr->mod_hdr_actions);
2912                 }
2913         }
2914 
2915         attr->action = action;
2916         if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
2917                 return -EOPNOTSUPP;
2918 
2919         return 0;
2920 }
2921 
2922 struct encap_key {
2923         const struct ip_tunnel_key *ip_tun_key;
2924         struct mlx5e_tc_tunnel *tc_tunnel;
2925 };
2926 
2927 static inline int cmp_encap_info(struct encap_key *a,
2928                                  struct encap_key *b)
2929 {
2930         return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
2931                a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
2932 }
2933 
2934 static inline int hash_encap_info(struct encap_key *key)
2935 {
2936         return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
2937                      key->tc_tunnel->tunnel_type);
2938 }
2939 
2940 
2941 static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2942                                   struct net_device *peer_netdev)
2943 {
2944         struct mlx5e_priv *peer_priv;
2945 
2946         peer_priv = netdev_priv(peer_netdev);
2947 
2948         return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2949                 mlx5e_eswitch_rep(priv->netdev) &&
2950                 mlx5e_eswitch_rep(peer_netdev) &&
2951                 same_hw_devs(priv, peer_priv));
2952 }
2953 
2954 
2955 
2956 bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
2957 {
2958         return refcount_inc_not_zero(&e->refcnt);
2959 }
2960 
2961 static struct mlx5e_encap_entry *
2962 mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
2963                 uintptr_t hash_key)
2964 {
2965         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2966         struct mlx5e_encap_entry *e;
2967         struct encap_key e_key;
2968 
2969         hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2970                                    encap_hlist, hash_key) {
2971                 e_key.ip_tun_key = &e->tun_info->key;
2972                 e_key.tc_tunnel = e->tunnel;
2973                 if (!cmp_encap_info(&e_key, key) &&
2974                     mlx5e_encap_take(e))
2975                         return e;
2976         }
2977 
2978         return NULL;
2979 }
2980 
2981 static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
2982 {
2983         size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
2984 
2985         return kmemdup(tun_info, tun_size, GFP_KERNEL);
2986 }
2987 
2988 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2989                               struct mlx5e_tc_flow *flow,
2990                               struct net_device *mirred_dev,
2991                               int out_index,
2992                               struct netlink_ext_ack *extack,
2993                               struct net_device **encap_dev,
2994                               bool *encap_valid)
2995 {
2996         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2997         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2998         struct mlx5e_tc_flow_parse_attr *parse_attr;
2999         const struct ip_tunnel_info *tun_info;
3000         struct encap_key key;
3001         struct mlx5e_encap_entry *e;
3002         unsigned short family;
3003         uintptr_t hash_key;
3004         int err = 0;
3005 
3006         parse_attr = attr->parse_attr;
3007         tun_info = parse_attr->tun_info[out_index];
3008         family = ip_tunnel_info_af(tun_info);
3009         key.ip_tun_key = &tun_info->key;
3010         key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
3011         if (!key.tc_tunnel) {
3012                 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3013                 return -EOPNOTSUPP;
3014         }
3015 
3016         hash_key = hash_encap_info(&key);
3017 
3018         mutex_lock(&esw->offloads.encap_tbl_lock);
3019         e = mlx5e_encap_get(priv, &key, hash_key);
3020 
3021         /* must verify if encap is valid or not */
3022         if (e) {
3023                 mutex_unlock(&esw->offloads.encap_tbl_lock);
3024                 wait_for_completion(&e->res_ready);
3025 
3026                 /* Protect against concurrent neigh update. */
3027                 mutex_lock(&esw->offloads.encap_tbl_lock);
3028                 if (e->compl_result < 0) {
3029                         err = -EREMOTEIO;
3030                         goto out_err;
3031                 }
3032                 goto attach_flow;
3033         }
3034 
3035         e = kzalloc(sizeof(*e), GFP_KERNEL);
3036         if (!e) {
3037                 err = -ENOMEM;
3038                 goto out_err;
3039         }
3040 
3041         refcount_set(&e->refcnt, 1);
3042         init_completion(&e->res_ready);
3043 
3044         tun_info = dup_tun_info(tun_info);
3045         if (!tun_info) {
3046                 err = -ENOMEM;
3047                 goto out_err_init;
3048         }
3049         e->tun_info = tun_info;
3050         err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
3051         if (err)
3052                 goto out_err_init;
3053 
3054         INIT_LIST_HEAD(&e->flows);
3055         hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3056         mutex_unlock(&esw->offloads.encap_tbl_lock);
3057 
3058         if (family == AF_INET)
3059                 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
3060         else if (family == AF_INET6)
3061                 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
3062 
3063         /* Protect against concurrent neigh update. */
3064         mutex_lock(&esw->offloads.encap_tbl_lock);
3065         complete_all(&e->res_ready);
3066         if (err) {
3067                 e->compl_result = err;
3068                 goto out_err;
3069         }
3070         e->compl_result = 1;
3071 
3072 attach_flow:
3073         flow->encaps[out_index].e = e;
3074         list_add(&flow->encaps[out_index].list, &e->flows);
3075         flow->encaps[out_index].index = out_index;
3076         *encap_dev = e->out_dev;
3077         if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
3078                 attr->dests[out_index].pkt_reformat = e->pkt_reformat;
3079                 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
3080                 *encap_valid = true;
3081         } else {
3082                 *encap_valid = false;
3083         }
3084         mutex_unlock(&esw->offloads.encap_tbl_lock);
3085 
3086         return err;
3087 
3088 out_err:
3089         mutex_unlock(&esw->offloads.encap_tbl_lock);
3090         if (e)
3091                 mlx5e_encap_put(priv, e);
3092         return err;
3093 
3094 out_err_init:
3095         mutex_unlock(&esw->offloads.encap_tbl_lock);
3096         kfree(tun_info);
3097         kfree(e);
3098         return err;
3099 }
3100 
3101 static int parse_tc_vlan_action(struct mlx5e_priv *priv,
3102                                 const struct flow_action_entry *act,
3103                                 struct mlx5_esw_flow_attr *attr,
3104                                 u32 *action)
3105 {
3106         u8 vlan_idx = attr->total_vlan;
3107 
3108         if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3109                 return -EOPNOTSUPP;
3110 
3111         switch (act->id) {
3112         case FLOW_ACTION_VLAN_POP:
3113                 if (vlan_idx) {
3114                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3115                                                                  MLX5_FS_VLAN_DEPTH))
3116                                 return -EOPNOTSUPP;
3117 
3118                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3119                 } else {
3120                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3121                 }
3122                 break;
3123         case FLOW_ACTION_VLAN_PUSH:
3124                 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3125                 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3126                 attr->vlan_proto[vlan_idx] = act->vlan.proto;
3127                 if (!attr->vlan_proto[vlan_idx])
3128                         attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3129 
3130                 if (vlan_idx) {
3131                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3132                                                                  MLX5_FS_VLAN_DEPTH))
3133                                 return -EOPNOTSUPP;
3134 
3135                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3136                 } else {
3137                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
3138                             (act->vlan.proto != htons(ETH_P_8021Q) ||
3139                              act->vlan.prio))
3140                                 return -EOPNOTSUPP;
3141 
3142                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
3143                 }
3144                 break;
3145         default:
3146                 return -EINVAL;
3147         }
3148 
3149         attr->total_vlan = vlan_idx + 1;
3150 
3151         return 0;
3152 }
3153 
3154 static int add_vlan_push_action(struct mlx5e_priv *priv,
3155                                 struct mlx5_esw_flow_attr *attr,
3156                                 struct net_device **out_dev,
3157                                 u32 *action)
3158 {
3159         struct net_device *vlan_dev = *out_dev;
3160         struct flow_action_entry vlan_act = {
3161                 .id = FLOW_ACTION_VLAN_PUSH,
3162                 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3163                 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3164                 .vlan.prio = 0,
3165         };
3166         int err;
3167 
3168         err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3169         if (err)
3170                 return err;
3171 
3172         *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3173                                         dev_get_iflink(vlan_dev));
3174         if (is_vlan_dev(*out_dev))
3175                 err = add_vlan_push_action(priv, attr, out_dev, action);
3176 
3177         return err;
3178 }
3179 
3180 static int add_vlan_pop_action(struct mlx5e_priv *priv,
3181                                struct mlx5_esw_flow_attr *attr,
3182                                u32 *action)
3183 {
3184         struct flow_action_entry vlan_act = {
3185                 .id = FLOW_ACTION_VLAN_POP,
3186         };
3187         int nest_level, err = 0;
3188 
3189         nest_level = attr->parse_attr->filter_dev->lower_level -
3190                                                 priv->netdev->lower_level;
3191         while (nest_level--) {
3192                 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3193                 if (err)
3194                         return err;
3195         }
3196 
3197         return err;
3198 }
3199 
3200 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3201                                     struct net_device *out_dev)
3202 {
3203         if (is_merged_eswitch_dev(priv, out_dev))
3204                 return true;
3205 
3206         return mlx5e_eswitch_rep(out_dev) &&
3207                same_hw_devs(priv, netdev_priv(out_dev));
3208 }
3209 
3210 static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3211                                 struct flow_action *flow_action,
3212                                 struct mlx5e_tc_flow *flow,
3213                                 struct netlink_ext_ack *extack)
3214 {
3215         struct pedit_headers_action hdrs[2] = {};
3216         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3217         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3218         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3219         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3220         const struct ip_tunnel_info *info = NULL;
3221         const struct flow_action_entry *act;
3222         bool encap = false;
3223         u32 action = 0;
3224         int err, i;
3225 
3226         if (!flow_action_has_entries(flow_action))
3227                 return -EINVAL;
3228 
3229         flow_action_for_each(i, act, flow_action) {
3230                 switch (act->id) {
3231                 case FLOW_ACTION_DROP:
3232                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3233                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
3234                         break;
3235                 case FLOW_ACTION_MANGLE:
3236                 case FLOW_ACTION_ADD:
3237                         err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
3238                                                     parse_attr, hdrs, extack);
3239                         if (err)
3240                                 return err;
3241 
3242                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3243                         attr->split_count = attr->out_count;
3244                         break;
3245                 case FLOW_ACTION_CSUM:
3246                         if (csum_offload_supported(priv, action,
3247                                                    act->csum_flags, extack))
3248                                 break;
3249 
3250                         return -EOPNOTSUPP;
3251                 case FLOW_ACTION_REDIRECT:
3252                 case FLOW_ACTION_MIRRED: {
3253                         struct mlx5e_priv *out_priv;
3254                         struct net_device *out_dev;
3255 
3256                         out_dev = act->dev;
3257                         if (!out_dev) {
3258                                 /* out_dev is NULL when filters with
3259                                  * non-existing mirred device are replayed to
3260                                  * the driver.
3261                                  */
3262                                 return -EINVAL;
3263                         }
3264 
3265                         if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
3266                                 NL_SET_ERR_MSG_MOD(extack,
3267                                                    "can't support more output ports, can't offload forwarding");
3268                                 pr_err("can't support more than %d output ports, can't offload forwarding\n",
3269                                        attr->out_count);
3270                                 return -EOPNOTSUPP;
3271                         }
3272 
3273                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3274                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
3275                         if (encap) {
3276                                 parse_attr->mirred_ifindex[attr->out_count] =
3277                                         out_dev->ifindex;
3278                                 parse_attr->tun_info[attr->out_count] = dup_tun_info(info);
3279                                 if (!parse_attr->tun_info[attr->out_count])
3280                                         return -ENOMEM;
3281                                 encap = false;
3282                                 attr->dests[attr->out_count].flags |=
3283                                         MLX5_ESW_DEST_ENCAP;
3284                                 attr->out_count++;
3285                                 /* attr->dests[].rep is resolved when we
3286                                  * handle encap
3287                                  */
3288                         } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
3289                                 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3290                                 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
3291                                 struct net_device *uplink_upper;
3292 
3293                                 rcu_read_lock();
3294                                 uplink_upper =
3295                                         netdev_master_upper_dev_get_rcu(uplink_dev);
3296                                 if (uplink_upper &&
3297                                     netif_is_lag_master(uplink_upper) &&
3298                                     uplink_upper == out_dev)
3299                                         out_dev = uplink_dev;
3300                                 rcu_read_unlock();
3301 
3302                                 if (is_vlan_dev(out_dev)) {
3303                                         err = add_vlan_push_action(priv, attr,
3304                                                                    &out_dev,
3305                                                                    &action);
3306                                         if (err)
3307                                                 return err;
3308                                 }
3309 
3310                                 if (is_vlan_dev(parse_attr->filter_dev)) {
3311                                         err = add_vlan_pop_action(priv, attr,
3312                                                                   &action);
3313                                         if (err)
3314                                                 return err;
3315                                 }
3316 
3317                                 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3318                                         NL_SET_ERR_MSG_MOD(extack,
3319                                                            "devices are not on same switch HW, can't offload forwarding");
3320                                         pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3321                                                priv->netdev->name, out_dev->name);
3322                                         return -EOPNOTSUPP;
3323                                 }
3324 
3325                                 out_priv = netdev_priv(out_dev);
3326                                 rpriv = out_priv->ppriv;
3327                                 attr->dests[attr->out_count].rep = rpriv->rep;
3328                                 attr->dests[attr->out_count].mdev = out_priv->mdev;
3329                                 attr->out_count++;
3330                         } else if (parse_attr->filter_dev != priv->netdev) {
3331                                 /* All mlx5 devices are called to configure
3332                                  * high level device filters. Therefore, the
3333                                  * *attempt* to  install a filter on invalid
3334                                  * eswitch should not trigger an explicit error
3335                                  */
3336                                 return -EINVAL;
3337                         } else {
3338                                 NL_SET_ERR_MSG_MOD(extack,
3339                                                    "devices are not on same switch HW, can't offload forwarding");
3340                                 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3341                                        priv->netdev->name, out_dev->name);
3342                                 return -EINVAL;
3343                         }
3344                         }
3345                         break;
3346                 case FLOW_ACTION_TUNNEL_ENCAP:
3347                         info = act->tunnel;
3348                         if (info)
3349                                 encap = true;
3350                         else
3351                                 return -EOPNOTSUPP;
3352 
3353                         break;
3354                 case FLOW_ACTION_VLAN_PUSH:
3355                 case FLOW_ACTION_VLAN_POP:
3356                         if (act->id == FLOW_ACTION_VLAN_PUSH &&
3357                             (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3358                                 /* Replace vlan pop+push with vlan modify */
3359                                 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3360                                 err = add_vlan_rewrite_action(priv,
3361                                                               MLX5_FLOW_NAMESPACE_FDB,
3362                                                               act, parse_attr, hdrs,
3363                                                               &action, extack);
3364                         } else {
3365                                 err = parse_tc_vlan_action(priv, act, attr, &action);
3366                         }
3367                         if (err)
3368                                 return err;
3369 
3370                         attr->split_count = attr->out_count;
3371                         break;
3372                 case FLOW_ACTION_VLAN_MANGLE:
3373                         err = add_vlan_rewrite_action(priv,
3374                                                       MLX5_FLOW_NAMESPACE_FDB,
3375                                                       act, parse_attr, hdrs,
3376                                                       &action, extack);
3377                         if (err)
3378                                 return err;
3379 
3380                         attr->split_count = attr->out_count;
3381                         break;
3382                 case FLOW_ACTION_TUNNEL_DECAP:
3383                         action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
3384                         break;
3385                 case FLOW_ACTION_GOTO: {
3386                         u32 dest_chain = act->chain_index;
3387                         u32 max_chain = mlx5_eswitch_get_chain_range(esw);
3388 
3389                         if (dest_chain <= attr->chain) {
3390                                 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
3391                                 return -EOPNOTSUPP;
3392                         }
3393                         if (dest_chain > max_chain) {
3394                                 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
3395                                 return -EOPNOTSUPP;
3396                         }
3397                         action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3398                         attr->dest_chain = dest_chain;
3399                         break;
3400                         }
3401                 default:
3402                         NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3403                         return -EOPNOTSUPP;
3404                 }
3405         }
3406 
3407         if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3408             action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3409                 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3410                  * tag rewrite.
3411                  */
3412                 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3413                 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3414                                                        &action, extack);
3415                 if (err)
3416                         return err;
3417         }
3418 
3419         if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3420             hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3421                 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3422                                             parse_attr, hdrs, &action, extack);
3423                 if (err)
3424                         return err;
3425                 /* in case all pedit actions are skipped, remove the MOD_HDR
3426                  * flag. we might have set split_count either by pedit or
3427                  * pop/push. if there is no pop/push either, reset it too.
3428                  */
3429                 if (parse_attr->num_mod_hdr_actions == 0) {
3430                         action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3431                         kfree(parse_attr->mod_hdr_actions);
3432                         if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3433                               (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3434                                 attr->split_count = 0;
3435                 }
3436         }
3437 
3438         attr->action = action;
3439         if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
3440                 return -EOPNOTSUPP;
3441 
3442         if (attr->dest_chain) {
3443                 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3444                         NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3445                         return -EOPNOTSUPP;
3446                 }
3447                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3448         }
3449 
3450         if (!(attr->action &
3451               (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3452                 NL_SET_ERR_MSG(extack, "Rule must have at least one forward/drop action");
3453                 return -EOPNOTSUPP;
3454         }
3455 
3456         if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3457                 NL_SET_ERR_MSG_MOD(extack,
3458                                    "current firmware doesn't support split rule for port mirroring");
3459                 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3460                 return -EOPNOTSUPP;
3461         }
3462 
3463         return 0;
3464 }
3465 
3466 static void get_flags(int flags, unsigned long *flow_flags)
3467 {
3468         unsigned long __flow_flags = 0;
3469 
3470         if (flags & MLX5_TC_FLAG(INGRESS))
3471                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3472         if (flags & MLX5_TC_FLAG(EGRESS))
3473                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
3474 
3475         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3476                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3477         if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3478                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
3479 
3480         *flow_flags = __flow_flags;
3481 }
3482 
3483 static const struct rhashtable_params tc_ht_params = {
3484         .head_offset = offsetof(struct mlx5e_tc_flow, node),
3485         .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3486         .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3487         .automatic_shrinking = true,
3488 };
3489 
3490 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3491                                     unsigned long flags)
3492 {
3493         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3494         struct mlx5e_rep_priv *uplink_rpriv;
3495 
3496         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
3497                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3498                 return &uplink_rpriv->uplink_priv.tc_ht;
3499         } else /* NIC offload */
3500                 return &priv->fs.tc.ht;
3501 }
3502 
3503 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3504 {
3505         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3506         bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
3507                 flow_flag_test(flow, INGRESS);
3508         bool act_is_encap = !!(attr->action &
3509                                MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3510         bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3511                                                 MLX5_DEVCOM_ESW_OFFLOADS);
3512 
3513         if (!esw_paired)
3514                 return false;
3515 
3516         if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3517              mlx5_lag_is_multipath(attr->in_mdev)) &&
3518             (is_rep_ingress || act_is_encap))
3519                 return true;
3520 
3521         return false;
3522 }
3523 
3524 static int
3525 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
3526                  struct flow_cls_offload *f, unsigned long flow_flags,
3527                  struct mlx5e_tc_flow_parse_attr **__parse_attr,
3528                  struct mlx5e_tc_flow **__flow)
3529 {
3530         struct mlx5e_tc_flow_parse_attr *parse_attr;
3531         struct mlx5e_tc_flow *flow;
3532         int out_index, err;
3533 
3534         flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
3535         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
3536         if (!parse_attr || !flow) {
3537                 err = -ENOMEM;
3538                 goto err_free;
3539         }
3540 
3541         flow->cookie = f->cookie;
3542         flow->flags = flow_flags;
3543         flow->priv = priv;
3544         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3545                 INIT_LIST_HEAD(&flow->encaps[out_index].list);
3546         INIT_LIST_HEAD(&flow->mod_hdr);
3547         INIT_LIST_HEAD(&flow->hairpin);
3548         refcount_set(&flow->refcnt, 1);
3549         init_completion(&flow->init_done);
3550 
3551         *__flow = flow;
3552         *__parse_attr = parse_attr;
3553 
3554         return 0;
3555 
3556 err_free:
3557         kfree(flow);
3558         kvfree(parse_attr);
3559         return err;
3560 }
3561 
3562 static void
3563 mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3564                          struct mlx5e_priv *priv,
3565                          struct mlx5e_tc_flow_parse_attr *parse_attr,
3566                          struct flow_cls_offload *f,
3567                          struct mlx5_eswitch_rep *in_rep,
3568                          struct mlx5_core_dev *in_mdev)
3569 {
3570         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3571 
3572         esw_attr->parse_attr = parse_attr;
3573         esw_attr->chain = f->common.chain_index;
3574         esw_attr->prio = f->common.prio;
3575 
3576         esw_attr->in_rep = in_rep;
3577         esw_attr->in_mdev = in_mdev;
3578 
3579         if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3580             MLX5_COUNTER_SOURCE_ESWITCH)
3581                 esw_attr->counter_dev = in_mdev;
3582         else
3583                 esw_attr->counter_dev = priv->mdev;
3584 }
3585 
3586 static struct mlx5e_tc_flow *
3587 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3588                      struct flow_cls_offload *f,
3589                      unsigned long flow_flags,
3590                      struct net_device *filter_dev,
3591                      struct mlx5_eswitch_rep *in_rep,
3592                      struct mlx5_core_dev *in_mdev)
3593 {
3594         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
3595         struct netlink_ext_ack *extack = f->common.extack;
3596         struct mlx5e_tc_flow_parse_attr *parse_attr;
3597         struct mlx5e_tc_flow *flow;
3598         int attr_size, err;
3599 
3600         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3601         attr_size  = sizeof(struct mlx5_esw_flow_attr);
3602         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3603                                &parse_attr, &flow);
3604         if (err)
3605                 goto out;
3606 
3607         parse_attr->filter_dev = filter_dev;
3608         mlx5e_flow_esw_attr_init(flow->esw_attr,
3609                                  priv, parse_attr,
3610                                  f, in_rep, in_mdev);
3611 
3612         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3613                                f, filter_dev);
3614         if (err)
3615                 goto err_free;
3616 
3617         err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
3618         if (err)
3619                 goto err_free;
3620 
3621         err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
3622         complete_all(&flow->init_done);
3623         if (err) {
3624                 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3625                         goto err_free;
3626 
3627                 add_unready_flow(flow);
3628         }
3629 
3630         return flow;
3631 
3632 err_free:
3633         mlx5e_flow_put(priv, flow);
3634 out:
3635         return ERR_PTR(err);
3636 }
3637 
3638 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
3639                                       struct mlx5e_tc_flow *flow,
3640                                       unsigned long flow_flags)
3641 {
3642         struct mlx5e_priv *priv = flow->priv, *peer_priv;
3643         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3644         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3645         struct mlx5e_tc_flow_parse_attr *parse_attr;
3646         struct mlx5e_rep_priv *peer_urpriv;
3647         struct mlx5e_tc_flow *peer_flow;
3648         struct mlx5_core_dev *in_mdev;
3649         int err = 0;
3650 
3651         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3652         if (!peer_esw)
3653                 return -ENODEV;
3654 
3655         peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3656         peer_priv = netdev_priv(peer_urpriv->netdev);
3657 
3658         /* in_mdev is assigned of which the packet originated from.
3659          * So packets redirected to uplink use the same mdev of the
3660          * original flow and packets redirected from uplink use the
3661          * peer mdev.
3662          */
3663         if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
3664                 in_mdev = peer_priv->mdev;
3665         else
3666                 in_mdev = priv->mdev;
3667 
3668         parse_attr = flow->esw_attr->parse_attr;
3669         peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
3670                                          parse_attr->filter_dev,
3671                                          flow->esw_attr->in_rep, in_mdev);
3672         if (IS_ERR(peer_flow)) {
3673                 err = PTR_ERR(peer_flow);
3674                 goto out;
3675         }
3676 
3677         flow->peer_flow = peer_flow;
3678         flow_flag_set(flow, DUP);
3679         mutex_lock(&esw->offloads.peer_mutex);
3680         list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3681         mutex_unlock(&esw->offloads.peer_mutex);
3682 
3683 out:
3684         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3685         return err;
3686 }
3687 
3688 static int
3689 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3690                    struct flow_cls_offload *f,
3691                    unsigned long flow_flags,
3692                    struct net_device *filter_dev,
3693                    struct mlx5e_tc_flow **__flow)
3694 {
3695         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3696         struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3697         struct mlx5_core_dev *in_mdev = priv->mdev;
3698         struct mlx5e_tc_flow *flow;
3699         int err;
3700 
3701         flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3702                                     in_mdev);
3703         if (IS_ERR(flow))
3704                 return PTR_ERR(flow);
3705 
3706         if (is_peer_flow_needed(flow)) {
3707                 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
3708                 if (err) {
3709                         mlx5e_tc_del_fdb_flow(priv, flow);
3710                         goto out;
3711                 }
3712         }
3713 
3714         *__flow = flow;
3715 
3716         return 0;
3717 
3718 out:
3719         return err;
3720 }
3721 
3722 static int
3723 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
3724                    struct flow_cls_offload *f,
3725                    unsigned long flow_flags,
3726                    struct net_device *filter_dev,
3727                    struct mlx5e_tc_flow **__flow)
3728 {
3729         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
3730         struct netlink_ext_ack *extack = f->common.extack;
3731         struct mlx5e_tc_flow_parse_attr *parse_attr;
3732         struct mlx5e_tc_flow *flow;
3733         int attr_size, err;
3734 
3735         /* multi-chain not supported for NIC rules */
3736         if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3737                 return -EOPNOTSUPP;
3738 
3739         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
3740         attr_size  = sizeof(struct mlx5_nic_flow_attr);
3741         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3742                                &parse_attr, &flow);
3743         if (err)
3744                 goto out;
3745 
3746         parse_attr->filter_dev = filter_dev;
3747         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3748                                f, filter_dev);
3749         if (err)
3750                 goto err_free;
3751 
3752         err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
3753         if (err)
3754                 goto err_free;
3755 
3756         err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3757         if (err)
3758                 goto err_free;
3759 
3760         flow_flag_set(flow, OFFLOADED);
3761         kvfree(parse_attr);
3762         *__flow = flow;
3763 
3764         return 0;
3765 
3766 err_free:
3767         mlx5e_flow_put(priv, flow);
3768         kvfree(parse_attr);
3769 out:
3770         return err;
3771 }
3772 
3773 static int
3774 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
3775                   struct flow_cls_offload *f,
3776                   unsigned long flags,
3777                   struct net_device *filter_dev,
3778                   struct mlx5e_tc_flow **flow)
3779 {
3780         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3781         unsigned long flow_flags;
3782         int err;
3783 
3784         get_flags(flags, &flow_flags);
3785 
3786         if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3787                 return -EOPNOTSUPP;
3788 
3789         if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
3790                 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3791                                          filter_dev, flow);
3792         else
3793                 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3794                                          filter_dev, flow);
3795 
3796         return err;
3797 }
3798 
3799 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
3800                            struct flow_cls_offload *f, unsigned long flags)
3801 {
3802         struct netlink_ext_ack *extack = f->common.extack;
3803         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3804         struct mlx5e_tc_flow *flow;
3805         int err = 0;
3806 
3807         rcu_read_lock();
3808         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
3809         rcu_read_unlock();
3810         if (flow) {
3811                 NL_SET_ERR_MSG_MOD(extack,
3812                                    "flow cookie already exists, ignoring");
3813                 netdev_warn_once(priv->netdev,
3814                                  "flow cookie %lx already exists, ignoring\n",
3815                                  f->cookie);
3816                 err = -EEXIST;
3817                 goto out;
3818         }
3819 
3820         trace_mlx5e_configure_flower(f);
3821         err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
3822         if (err)
3823                 goto out;
3824 
3825         err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
3826         if (err)
3827                 goto err_free;
3828 
3829         return 0;
3830 
3831 err_free:
3832         mlx5e_flow_put(priv, flow);
3833 out:
3834         return err;
3835 }
3836 
3837 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3838 {
3839         bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
3840         bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
3841 
3842         return flow_flag_test(flow, INGRESS) == dir_ingress &&
3843                 flow_flag_test(flow, EGRESS) == dir_egress;
3844 }
3845 
3846 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
3847                         struct flow_cls_offload *f, unsigned long flags)
3848 {
3849         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3850         struct mlx5e_tc_flow *flow;
3851         int err;
3852 
3853         rcu_read_lock();
3854         flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
3855         if (!flow || !same_flow_direction(flow, flags)) {
3856                 err = -EINVAL;
3857                 goto errout;
3858         }
3859 
3860         /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
3861          * set.
3862          */
3863         if (flow_flag_test_and_set(flow, DELETED)) {
3864                 err = -EINVAL;
3865                 goto errout;
3866         }
3867         rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
3868         rcu_read_unlock();
3869 
3870         trace_mlx5e_delete_flower(f);
3871         mlx5e_flow_put(priv, flow);
3872 
3873         return 0;
3874 
3875 errout:
3876         rcu_read_unlock();
3877         return err;
3878 }
3879 
3880 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
3881                        struct flow_cls_offload *f, unsigned long flags)
3882 {
3883         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3884         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3885         struct mlx5_eswitch *peer_esw;
3886         struct mlx5e_tc_flow *flow;
3887         struct mlx5_fc *counter;
3888         u64 lastuse = 0;
3889         u64 packets = 0;
3890         u64 bytes = 0;
3891         int err = 0;
3892 
3893         rcu_read_lock();
3894         flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
3895                                                 tc_ht_params));
3896         rcu_read_unlock();
3897         if (IS_ERR(flow))
3898                 return PTR_ERR(flow);
3899 
3900         if (!same_flow_direction(flow, flags)) {
3901                 err = -EINVAL;
3902                 goto errout;
3903         }
3904 
3905         if (mlx5e_is_offloaded_flow(flow)) {
3906                 counter = mlx5e_tc_get_counter(flow);
3907                 if (!counter)
3908                         goto errout;
3909 
3910                 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3911         }
3912 
3913         /* Under multipath it's possible for one rule to be currently
3914          * un-offloaded while the other rule is offloaded.
3915          */
3916         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3917         if (!peer_esw)
3918                 goto out;
3919 
3920         if (flow_flag_test(flow, DUP) &&
3921             flow_flag_test(flow->peer_flow, OFFLOADED)) {
3922                 u64 bytes2;
3923                 u64 packets2;
3924                 u64 lastuse2;
3925 
3926                 counter = mlx5e_tc_get_counter(flow->peer_flow);
3927                 if (!counter)
3928                         goto no_peer_counter;
3929                 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3930 
3931                 bytes += bytes2;
3932                 packets += packets2;
3933                 lastuse = max_t(u64, lastuse, lastuse2);
3934         }
3935 
3936 no_peer_counter:
3937         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3938 out:
3939         flow_stats_update(&f->stats, bytes, packets, lastuse);
3940         trace_mlx5e_stats_flower(f);
3941 errout:
3942         mlx5e_flow_put(priv, flow);
3943         return err;
3944 }
3945 
3946 static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
3947                                struct netlink_ext_ack *extack)
3948 {
3949         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3950         struct mlx5_eswitch *esw;
3951         u16 vport_num;
3952         u32 rate_mbps;
3953         int err;
3954 
3955         vport_num = rpriv->rep->vport;
3956         if (vport_num >= MLX5_VPORT_ECPF) {
3957                 NL_SET_ERR_MSG_MOD(extack,
3958                                    "Ingress rate limit is supported only for Eswitch ports connected to VFs");
3959                 return -EOPNOTSUPP;
3960         }
3961 
3962         esw = priv->mdev->priv.eswitch;
3963         /* rate is given in bytes/sec.
3964          * First convert to bits/sec and then round to the nearest mbit/secs.
3965          * mbit means million bits.
3966          * Moreover, if rate is non zero we choose to configure to a minimum of
3967          * 1 mbit/sec.
3968          */
3969         rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
3970         err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
3971         if (err)
3972                 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
3973 
3974         return err;
3975 }
3976 
3977 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
3978                                         struct flow_action *flow_action,
3979                                         struct netlink_ext_ack *extack)
3980 {
3981         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3982         const struct flow_action_entry *act;
3983         int err;
3984         int i;
3985 
3986         if (!flow_action_has_entries(flow_action)) {
3987                 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
3988                 return -EINVAL;
3989         }
3990 
3991         if (!flow_offload_has_one_action(flow_action)) {
3992                 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
3993                 return -EOPNOTSUPP;
3994         }
3995 
3996         flow_action_for_each(i, act, flow_action) {
3997                 switch (act->id) {
3998                 case FLOW_ACTION_POLICE:
3999                         err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4000                         if (err)
4001                                 return err;
4002 
4003                         rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4004                         break;
4005                 default:
4006                         NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4007                         return -EOPNOTSUPP;
4008                 }
4009         }
4010 
4011         return 0;
4012 }
4013 
4014 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4015                                 struct tc_cls_matchall_offload *ma)
4016 {
4017         struct netlink_ext_ack *extack = ma->common.extack;
4018 
4019         if (ma->common.prio != 1) {
4020                 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4021                 return -EINVAL;
4022         }
4023 
4024         return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4025 }
4026 
4027 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4028                              struct tc_cls_matchall_offload *ma)
4029 {
4030         struct netlink_ext_ack *extack = ma->common.extack;
4031 
4032         return apply_police_params(priv, 0, extack);
4033 }
4034 
4035 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4036                              struct tc_cls_matchall_offload *ma)
4037 {
4038         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4039         struct rtnl_link_stats64 cur_stats;
4040         u64 dbytes;
4041         u64 dpkts;
4042 
4043         cur_stats = priv->stats.vf_vport;
4044         dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4045         dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4046         rpriv->prev_vf_vport_stats = cur_stats;
4047         flow_stats_update(&ma->stats, dpkts, dbytes, jiffies);
4048 }
4049 
4050 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4051                                               struct mlx5e_priv *peer_priv)
4052 {
4053         struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
4054         struct mlx5e_hairpin_entry *hpe, *tmp;
4055         LIST_HEAD(init_wait_list);
4056         u16 peer_vhca_id;
4057         int bkt;
4058 
4059         if (!same_hw_devs(priv, peer_priv))
4060                 return;
4061 
4062         peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4063 
4064         mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
4065         hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4066                 if (refcount_inc_not_zero(&hpe->refcnt))
4067                         list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4068         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4069 
4070         list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4071                 wait_for_completion(&hpe->res_ready);
4072                 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4073                         hpe->hp->pair->peer_gone = true;
4074 
4075                 mlx5e_hairpin_put(priv, hpe);
4076         }
4077 }
4078 
4079 static int mlx5e_tc_netdev_event(struct notifier_block *this,
4080                                  unsigned long event, void *ptr)
4081 {
4082         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4083         struct mlx5e_flow_steering *fs;
4084         struct mlx5e_priv *peer_priv;
4085         struct mlx5e_tc_table *tc;
4086         struct mlx5e_priv *priv;
4087 
4088         if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4089             event != NETDEV_UNREGISTER ||
4090             ndev->reg_state == NETREG_REGISTERED)
4091                 return NOTIFY_DONE;
4092 
4093         tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4094         fs = container_of(tc, struct mlx5e_flow_steering, tc);
4095         priv = container_of(fs, struct mlx5e_priv, fs);
4096         peer_priv = netdev_priv(ndev);
4097         if (priv == peer_priv ||
4098             !(priv->netdev->features & NETIF_F_HW_TC))
4099                 return NOTIFY_DONE;
4100 
4101         mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4102 
4103         return NOTIFY_DONE;
4104 }
4105 
4106 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
4107 {
4108         struct mlx5e_tc_table *tc = &priv->fs.tc;
4109         int err;
4110 
4111         mutex_init(&tc->t_lock);
4112         mutex_init(&tc->mod_hdr.lock);
4113         hash_init(tc->mod_hdr.hlist);
4114         mutex_init(&tc->hairpin_tbl_lock);
4115         hash_init(tc->hairpin_tbl);
4116 
4117         err = rhashtable_init(&tc->ht, &tc_ht_params);
4118         if (err)
4119                 return err;
4120 
4121         tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
4122         if (register_netdevice_notifier(&tc->netdevice_nb)) {
4123                 tc->netdevice_nb.notifier_call = NULL;
4124                 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4125         }
4126 
4127         return err;
4128 }
4129 
4130 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4131 {
4132         struct mlx5e_tc_flow *flow = ptr;
4133         struct mlx5e_priv *priv = flow->priv;
4134 
4135         mlx5e_tc_del_flow(priv, flow);
4136         kfree(flow);
4137 }
4138 
4139 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
4140 {
4141         struct mlx5e_tc_table *tc = &priv->fs.tc;
4142 
4143         if (tc->netdevice_nb.notifier_call)
4144                 unregister_netdevice_notifier(&tc->netdevice_nb);
4145 
4146         mutex_destroy(&tc->mod_hdr.lock);
4147         mutex_destroy(&tc->hairpin_tbl_lock);
4148 
4149         rhashtable_destroy(&tc->ht);
4150 
4151         if (!IS_ERR_OR_NULL(tc->t)) {
4152                 mlx5_destroy_flow_table(tc->t);
4153                 tc->t = NULL;
4154         }
4155         mutex_destroy(&tc->t_lock);
4156 }
4157 
4158 int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4159 {
4160         return rhashtable_init(tc_ht, &tc_ht_params);
4161 }
4162 
4163 void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4164 {
4165         rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4166 }
4167 
4168 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
4169 {
4170         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4171 
4172         return atomic_read(&tc_ht->nelems);
4173 }
4174 
4175 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4176 {
4177         struct mlx5e_tc_flow *flow, *tmp;
4178 
4179         list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4180                 __mlx5e_tc_del_fdb_peer_flow(flow);
4181 }
4182 
4183 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4184 {
4185         struct mlx5_rep_uplink_priv *rpriv =
4186                 container_of(work, struct mlx5_rep_uplink_priv,
4187                              reoffload_flows_work);
4188         struct mlx5e_tc_flow *flow, *tmp;
4189 
4190         mutex_lock(&rpriv->unready_flows_lock);
4191         list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4192                 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
4193                         unready_flow_del(flow);
4194         }
4195         mutex_unlock(&rpriv->unready_flows_lock);
4196 }