1
2
3
4 #ifndef MLX5_IFC_DR_H
5 #define MLX5_IFC_DR_H
6
7 enum {
8 MLX5DR_ACTION_MDFY_HW_FLD_L2_0 = 0,
9 MLX5DR_ACTION_MDFY_HW_FLD_L2_1 = 1,
10 MLX5DR_ACTION_MDFY_HW_FLD_L2_2 = 2,
11 MLX5DR_ACTION_MDFY_HW_FLD_L3_0 = 3,
12 MLX5DR_ACTION_MDFY_HW_FLD_L3_1 = 4,
13 MLX5DR_ACTION_MDFY_HW_FLD_L3_2 = 5,
14 MLX5DR_ACTION_MDFY_HW_FLD_L3_3 = 6,
15 MLX5DR_ACTION_MDFY_HW_FLD_L3_4 = 7,
16 MLX5DR_ACTION_MDFY_HW_FLD_L4_0 = 8,
17 MLX5DR_ACTION_MDFY_HW_FLD_L4_1 = 9,
18 MLX5DR_ACTION_MDFY_HW_FLD_MPLS = 10,
19 MLX5DR_ACTION_MDFY_HW_FLD_L2_TNL_0 = 11,
20 MLX5DR_ACTION_MDFY_HW_FLD_REG_0 = 12,
21 MLX5DR_ACTION_MDFY_HW_FLD_REG_1 = 13,
22 MLX5DR_ACTION_MDFY_HW_FLD_REG_2 = 14,
23 MLX5DR_ACTION_MDFY_HW_FLD_REG_3 = 15,
24 MLX5DR_ACTION_MDFY_HW_FLD_L4_2 = 16,
25 MLX5DR_ACTION_MDFY_HW_FLD_FLEX_0 = 17,
26 MLX5DR_ACTION_MDFY_HW_FLD_FLEX_1 = 18,
27 MLX5DR_ACTION_MDFY_HW_FLD_FLEX_2 = 19,
28 MLX5DR_ACTION_MDFY_HW_FLD_FLEX_3 = 20,
29 MLX5DR_ACTION_MDFY_HW_FLD_L2_TNL_1 = 21,
30 MLX5DR_ACTION_MDFY_HW_FLD_METADATA = 22,
31 MLX5DR_ACTION_MDFY_HW_FLD_RESERVED = 23,
32 };
33
34 enum {
35 MLX5DR_ACTION_MDFY_HW_OP_SET = 0x2,
36 MLX5DR_ACTION_MDFY_HW_OP_ADD = 0x3,
37 };
38
39 enum {
40 MLX5DR_ACTION_MDFY_HW_HDR_L3_NONE = 0x0,
41 MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4 = 0x1,
42 MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6 = 0x2,
43 };
44
45 enum {
46 MLX5DR_ACTION_MDFY_HW_HDR_L4_NONE = 0x0,
47 MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP = 0x1,
48 MLX5DR_ACTION_MDFY_HW_HDR_L4_UDP = 0x2,
49 };
50
51 enum {
52 MLX5DR_STE_LU_TYPE_NOP = 0x00,
53 MLX5DR_STE_LU_TYPE_SRC_GVMI_AND_QP = 0x05,
54 MLX5DR_STE_LU_TYPE_ETHL2_TUNNELING_I = 0x0a,
55 MLX5DR_STE_LU_TYPE_ETHL2_DST_O = 0x06,
56 MLX5DR_STE_LU_TYPE_ETHL2_DST_I = 0x07,
57 MLX5DR_STE_LU_TYPE_ETHL2_DST_D = 0x1b,
58 MLX5DR_STE_LU_TYPE_ETHL2_SRC_O = 0x08,
59 MLX5DR_STE_LU_TYPE_ETHL2_SRC_I = 0x09,
60 MLX5DR_STE_LU_TYPE_ETHL2_SRC_D = 0x1c,
61 MLX5DR_STE_LU_TYPE_ETHL2_SRC_DST_O = 0x36,
62 MLX5DR_STE_LU_TYPE_ETHL2_SRC_DST_I = 0x37,
63 MLX5DR_STE_LU_TYPE_ETHL2_SRC_DST_D = 0x38,
64 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_DST_O = 0x0d,
65 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_DST_I = 0x0e,
66 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_DST_D = 0x1e,
67 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_O = 0x0f,
68 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_I = 0x10,
69 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_D = 0x1f,
70 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_5_TUPLE_O = 0x11,
71 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_5_TUPLE_I = 0x12,
72 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_5_TUPLE_D = 0x20,
73 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_MISC_O = 0x29,
74 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_MISC_I = 0x2a,
75 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_MISC_D = 0x2b,
76 MLX5DR_STE_LU_TYPE_ETHL4_O = 0x13,
77 MLX5DR_STE_LU_TYPE_ETHL4_I = 0x14,
78 MLX5DR_STE_LU_TYPE_ETHL4_D = 0x21,
79 MLX5DR_STE_LU_TYPE_ETHL4_MISC_O = 0x2c,
80 MLX5DR_STE_LU_TYPE_ETHL4_MISC_I = 0x2d,
81 MLX5DR_STE_LU_TYPE_ETHL4_MISC_D = 0x2e,
82 MLX5DR_STE_LU_TYPE_MPLS_FIRST_O = 0x15,
83 MLX5DR_STE_LU_TYPE_MPLS_FIRST_I = 0x24,
84 MLX5DR_STE_LU_TYPE_MPLS_FIRST_D = 0x25,
85 MLX5DR_STE_LU_TYPE_GRE = 0x16,
86 MLX5DR_STE_LU_TYPE_FLEX_PARSER_0 = 0x22,
87 MLX5DR_STE_LU_TYPE_FLEX_PARSER_1 = 0x23,
88 MLX5DR_STE_LU_TYPE_FLEX_PARSER_TNL_HEADER = 0x19,
89 MLX5DR_STE_LU_TYPE_GENERAL_PURPOSE = 0x18,
90 MLX5DR_STE_LU_TYPE_STEERING_REGISTERS_0 = 0x2f,
91 MLX5DR_STE_LU_TYPE_STEERING_REGISTERS_1 = 0x30,
92 MLX5DR_STE_LU_TYPE_DONT_CARE = 0x0f,
93 };
94
95 enum mlx5dr_ste_entry_type {
96 MLX5DR_STE_TYPE_TX = 1,
97 MLX5DR_STE_TYPE_RX = 2,
98 MLX5DR_STE_TYPE_MODIFY_PKT = 6,
99 };
100
101 struct mlx5_ifc_ste_general_bits {
102 u8 entry_type[0x4];
103 u8 reserved_at_4[0x4];
104 u8 entry_sub_type[0x8];
105 u8 byte_mask[0x10];
106
107 u8 next_table_base_63_48[0x10];
108 u8 next_lu_type[0x8];
109 u8 next_table_base_39_32_size[0x8];
110
111 u8 next_table_base_31_5_size[0x1b];
112 u8 linear_hash_enable[0x1];
113 u8 reserved_at_5c[0x2];
114 u8 next_table_rank[0x2];
115
116 u8 reserved_at_60[0xa0];
117 u8 tag_value[0x60];
118 u8 bit_mask[0x60];
119 };
120
121 struct mlx5_ifc_ste_sx_transmit_bits {
122 u8 entry_type[0x4];
123 u8 reserved_at_4[0x4];
124 u8 entry_sub_type[0x8];
125 u8 byte_mask[0x10];
126
127 u8 next_table_base_63_48[0x10];
128 u8 next_lu_type[0x8];
129 u8 next_table_base_39_32_size[0x8];
130
131 u8 next_table_base_31_5_size[0x1b];
132 u8 linear_hash_enable[0x1];
133 u8 reserved_at_5c[0x2];
134 u8 next_table_rank[0x2];
135
136 u8 sx_wire[0x1];
137 u8 sx_func_lb[0x1];
138 u8 sx_sniffer[0x1];
139 u8 sx_wire_enable[0x1];
140 u8 sx_func_lb_enable[0x1];
141 u8 sx_sniffer_enable[0x1];
142 u8 action_type[0x3];
143 u8 reserved_at_69[0x1];
144 u8 action_description[0x6];
145 u8 gvmi[0x10];
146
147 u8 encap_pointer_vlan_data[0x20];
148
149 u8 loopback_syndome_en[0x8];
150 u8 loopback_syndome[0x8];
151 u8 counter_trigger[0x10];
152
153 u8 miss_address_63_48[0x10];
154 u8 counter_trigger_23_16[0x8];
155 u8 miss_address_39_32[0x8];
156
157 u8 miss_address_31_6[0x1a];
158 u8 learning_point[0x1];
159 u8 go_back[0x1];
160 u8 match_polarity[0x1];
161 u8 mask_mode[0x1];
162 u8 miss_rank[0x2];
163 };
164
165 struct mlx5_ifc_ste_rx_steering_mult_bits {
166 u8 entry_type[0x4];
167 u8 reserved_at_4[0x4];
168 u8 entry_sub_type[0x8];
169 u8 byte_mask[0x10];
170
171 u8 next_table_base_63_48[0x10];
172 u8 next_lu_type[0x8];
173 u8 next_table_base_39_32_size[0x8];
174
175 u8 next_table_base_31_5_size[0x1b];
176 u8 linear_hash_enable[0x1];
177 u8 reserved_at_[0x2];
178 u8 next_table_rank[0x2];
179
180 u8 member_count[0x10];
181 u8 gvmi[0x10];
182
183 u8 qp_list_pointer[0x20];
184
185 u8 reserved_at_a0[0x1];
186 u8 tunneling_action[0x3];
187 u8 action_description[0x4];
188 u8 reserved_at_a8[0x8];
189 u8 counter_trigger_15_0[0x10];
190
191 u8 miss_address_63_48[0x10];
192 u8 counter_trigger_23_16[0x08];
193 u8 miss_address_39_32[0x8];
194
195 u8 miss_address_31_6[0x1a];
196 u8 learning_point[0x1];
197 u8 fail_on_error[0x1];
198 u8 match_polarity[0x1];
199 u8 mask_mode[0x1];
200 u8 miss_rank[0x2];
201 };
202
203 struct mlx5_ifc_ste_modify_packet_bits {
204 u8 entry_type[0x4];
205 u8 reserved_at_4[0x4];
206 u8 entry_sub_type[0x8];
207 u8 byte_mask[0x10];
208
209 u8 next_table_base_63_48[0x10];
210 u8 next_lu_type[0x8];
211 u8 next_table_base_39_32_size[0x8];
212
213 u8 next_table_base_31_5_size[0x1b];
214 u8 linear_hash_enable[0x1];
215 u8 reserved_at_[0x2];
216 u8 next_table_rank[0x2];
217
218 u8 number_of_re_write_actions[0x10];
219 u8 gvmi[0x10];
220
221 u8 header_re_write_actions_pointer[0x20];
222
223 u8 reserved_at_a0[0x1];
224 u8 tunneling_action[0x3];
225 u8 action_description[0x4];
226 u8 reserved_at_a8[0x8];
227 u8 counter_trigger_15_0[0x10];
228
229 u8 miss_address_63_48[0x10];
230 u8 counter_trigger_23_16[0x08];
231 u8 miss_address_39_32[0x8];
232
233 u8 miss_address_31_6[0x1a];
234 u8 learning_point[0x1];
235 u8 fail_on_error[0x1];
236 u8 match_polarity[0x1];
237 u8 mask_mode[0x1];
238 u8 miss_rank[0x2];
239 };
240
241 struct mlx5_ifc_ste_eth_l2_src_bits {
242 u8 smac_47_16[0x20];
243
244 u8 smac_15_0[0x10];
245 u8 l3_ethertype[0x10];
246
247 u8 qp_type[0x2];
248 u8 ethertype_filter[0x1];
249 u8 reserved_at_43[0x1];
250 u8 sx_sniffer[0x1];
251 u8 force_lb[0x1];
252 u8 functional_lb[0x1];
253 u8 port[0x1];
254 u8 reserved_at_48[0x4];
255 u8 first_priority[0x3];
256 u8 first_cfi[0x1];
257 u8 first_vlan_qualifier[0x2];
258 u8 reserved_at_52[0x2];
259 u8 first_vlan_id[0xc];
260
261 u8 ip_fragmented[0x1];
262 u8 tcp_syn[0x1];
263 u8 encp_type[0x2];
264 u8 l3_type[0x2];
265 u8 l4_type[0x2];
266 u8 reserved_at_68[0x4];
267 u8 second_priority[0x3];
268 u8 second_cfi[0x1];
269 u8 second_vlan_qualifier[0x2];
270 u8 reserved_at_72[0x2];
271 u8 second_vlan_id[0xc];
272 };
273
274 struct mlx5_ifc_ste_eth_l2_dst_bits {
275 u8 dmac_47_16[0x20];
276
277 u8 dmac_15_0[0x10];
278 u8 l3_ethertype[0x10];
279
280 u8 qp_type[0x2];
281 u8 ethertype_filter[0x1];
282 u8 reserved_at_43[0x1];
283 u8 sx_sniffer[0x1];
284 u8 force_lb[0x1];
285 u8 functional_lb[0x1];
286 u8 port[0x1];
287 u8 reserved_at_48[0x4];
288 u8 first_priority[0x3];
289 u8 first_cfi[0x1];
290 u8 first_vlan_qualifier[0x2];
291 u8 reserved_at_52[0x2];
292 u8 first_vlan_id[0xc];
293
294 u8 ip_fragmented[0x1];
295 u8 tcp_syn[0x1];
296 u8 encp_type[0x2];
297 u8 l3_type[0x2];
298 u8 l4_type[0x2];
299 u8 reserved_at_68[0x4];
300 u8 second_priority[0x3];
301 u8 second_cfi[0x1];
302 u8 second_vlan_qualifier[0x2];
303 u8 reserved_at_72[0x2];
304 u8 second_vlan_id[0xc];
305 };
306
307 struct mlx5_ifc_ste_eth_l2_src_dst_bits {
308 u8 dmac_47_16[0x20];
309
310 u8 dmac_15_0[0x10];
311 u8 smac_47_32[0x10];
312
313 u8 smac_31_0[0x20];
314
315 u8 sx_sniffer[0x1];
316 u8 force_lb[0x1];
317 u8 functional_lb[0x1];
318 u8 port[0x1];
319 u8 l3_type[0x2];
320 u8 reserved_at_66[0x6];
321 u8 first_priority[0x3];
322 u8 first_cfi[0x1];
323 u8 first_vlan_qualifier[0x2];
324 u8 reserved_at_72[0x2];
325 u8 first_vlan_id[0xc];
326 };
327
328 struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_bits {
329 u8 destination_address[0x20];
330
331 u8 source_address[0x20];
332
333 u8 source_port[0x10];
334 u8 destination_port[0x10];
335
336 u8 fragmented[0x1];
337 u8 first_fragment[0x1];
338 u8 reserved_at_62[0x2];
339 u8 reserved_at_64[0x1];
340 u8 ecn[0x2];
341 u8 tcp_ns[0x1];
342 u8 tcp_cwr[0x1];
343 u8 tcp_ece[0x1];
344 u8 tcp_urg[0x1];
345 u8 tcp_ack[0x1];
346 u8 tcp_psh[0x1];
347 u8 tcp_rst[0x1];
348 u8 tcp_syn[0x1];
349 u8 tcp_fin[0x1];
350 u8 dscp[0x6];
351 u8 reserved_at_76[0x2];
352 u8 protocol[0x8];
353 };
354
355 struct mlx5_ifc_ste_eth_l3_ipv6_dst_bits {
356 u8 dst_ip_127_96[0x20];
357
358 u8 dst_ip_95_64[0x20];
359
360 u8 dst_ip_63_32[0x20];
361
362 u8 dst_ip_31_0[0x20];
363 };
364
365 struct mlx5_ifc_ste_eth_l2_tnl_bits {
366 u8 dmac_47_16[0x20];
367
368 u8 dmac_15_0[0x10];
369 u8 l3_ethertype[0x10];
370
371 u8 l2_tunneling_network_id[0x20];
372
373 u8 ip_fragmented[0x1];
374 u8 tcp_syn[0x1];
375 u8 encp_type[0x2];
376 u8 l3_type[0x2];
377 u8 l4_type[0x2];
378 u8 first_priority[0x3];
379 u8 first_cfi[0x1];
380 u8 reserved_at_6c[0x3];
381 u8 gre_key_flag[0x1];
382 u8 first_vlan_qualifier[0x2];
383 u8 reserved_at_72[0x2];
384 u8 first_vlan_id[0xc];
385 };
386
387 struct mlx5_ifc_ste_eth_l3_ipv6_src_bits {
388 u8 src_ip_127_96[0x20];
389
390 u8 src_ip_95_64[0x20];
391
392 u8 src_ip_63_32[0x20];
393
394 u8 src_ip_31_0[0x20];
395 };
396
397 struct mlx5_ifc_ste_eth_l3_ipv4_misc_bits {
398 u8 version[0x4];
399 u8 ihl[0x4];
400 u8 reserved_at_8[0x8];
401 u8 total_length[0x10];
402
403 u8 identification[0x10];
404 u8 flags[0x3];
405 u8 fragment_offset[0xd];
406
407 u8 time_to_live[0x8];
408 u8 reserved_at_48[0x8];
409 u8 checksum[0x10];
410
411 u8 reserved_at_60[0x20];
412 };
413
414 struct mlx5_ifc_ste_eth_l4_bits {
415 u8 fragmented[0x1];
416 u8 first_fragment[0x1];
417 u8 reserved_at_2[0x6];
418 u8 protocol[0x8];
419 u8 dst_port[0x10];
420
421 u8 ipv6_version[0x4];
422 u8 reserved_at_24[0x1];
423 u8 ecn[0x2];
424 u8 tcp_ns[0x1];
425 u8 tcp_cwr[0x1];
426 u8 tcp_ece[0x1];
427 u8 tcp_urg[0x1];
428 u8 tcp_ack[0x1];
429 u8 tcp_psh[0x1];
430 u8 tcp_rst[0x1];
431 u8 tcp_syn[0x1];
432 u8 tcp_fin[0x1];
433 u8 src_port[0x10];
434
435 u8 ipv6_payload_length[0x10];
436 u8 ipv6_hop_limit[0x8];
437 u8 dscp[0x6];
438 u8 reserved_at_5e[0x2];
439
440 u8 tcp_data_offset[0x4];
441 u8 reserved_at_64[0x8];
442 u8 flow_label[0x14];
443 };
444
445 struct mlx5_ifc_ste_eth_l4_misc_bits {
446 u8 checksum[0x10];
447 u8 length[0x10];
448
449 u8 seq_num[0x20];
450
451 u8 ack_num[0x20];
452
453 u8 urgent_pointer[0x10];
454 u8 window_size[0x10];
455 };
456
457 struct mlx5_ifc_ste_mpls_bits {
458 u8 mpls0_label[0x14];
459 u8 mpls0_exp[0x3];
460 u8 mpls0_s_bos[0x1];
461 u8 mpls0_ttl[0x8];
462
463 u8 mpls1_label[0x20];
464
465 u8 mpls2_label[0x20];
466
467 u8 reserved_at_60[0x16];
468 u8 mpls4_s_bit[0x1];
469 u8 mpls4_qualifier[0x1];
470 u8 mpls3_s_bit[0x1];
471 u8 mpls3_qualifier[0x1];
472 u8 mpls2_s_bit[0x1];
473 u8 mpls2_qualifier[0x1];
474 u8 mpls1_s_bit[0x1];
475 u8 mpls1_qualifier[0x1];
476 u8 mpls0_s_bit[0x1];
477 u8 mpls0_qualifier[0x1];
478 };
479
480 struct mlx5_ifc_ste_register_0_bits {
481 u8 register_0_h[0x20];
482
483 u8 register_0_l[0x20];
484
485 u8 register_1_h[0x20];
486
487 u8 register_1_l[0x20];
488 };
489
490 struct mlx5_ifc_ste_register_1_bits {
491 u8 register_2_h[0x20];
492
493 u8 register_2_l[0x20];
494
495 u8 register_3_h[0x20];
496
497 u8 register_3_l[0x20];
498 };
499
500 struct mlx5_ifc_ste_gre_bits {
501 u8 gre_c_present[0x1];
502 u8 reserved_at_30[0x1];
503 u8 gre_k_present[0x1];
504 u8 gre_s_present[0x1];
505 u8 strict_src_route[0x1];
506 u8 recur[0x3];
507 u8 flags[0x5];
508 u8 version[0x3];
509 u8 gre_protocol[0x10];
510
511 u8 checksum[0x10];
512 u8 offset[0x10];
513
514 u8 gre_key_h[0x18];
515 u8 gre_key_l[0x8];
516
517 u8 seq_num[0x20];
518 };
519
520 struct mlx5_ifc_ste_flex_parser_0_bits {
521 u8 parser_3_label[0x14];
522 u8 parser_3_exp[0x3];
523 u8 parser_3_s_bos[0x1];
524 u8 parser_3_ttl[0x8];
525
526 u8 flex_parser_2[0x20];
527
528 u8 flex_parser_1[0x20];
529
530 u8 flex_parser_0[0x20];
531 };
532
533 struct mlx5_ifc_ste_flex_parser_1_bits {
534 u8 flex_parser_7[0x20];
535
536 u8 flex_parser_6[0x20];
537
538 u8 flex_parser_5[0x20];
539
540 u8 flex_parser_4[0x20];
541 };
542
543 struct mlx5_ifc_ste_flex_parser_tnl_bits {
544 u8 flex_parser_tunneling_header_63_32[0x20];
545
546 u8 flex_parser_tunneling_header_31_0[0x20];
547
548 u8 reserved_at_40[0x40];
549 };
550
551 struct mlx5_ifc_ste_general_purpose_bits {
552 u8 general_purpose_lookup_field[0x20];
553
554 u8 reserved_at_20[0x20];
555
556 u8 reserved_at_40[0x20];
557
558 u8 reserved_at_60[0x20];
559 };
560
561 struct mlx5_ifc_ste_src_gvmi_qp_bits {
562 u8 loopback_syndrome[0x8];
563 u8 reserved_at_8[0x8];
564 u8 source_gvmi[0x10];
565
566 u8 reserved_at_20[0x5];
567 u8 force_lb[0x1];
568 u8 functional_lb[0x1];
569 u8 source_is_requestor[0x1];
570 u8 source_qp[0x18];
571
572 u8 reserved_at_40[0x20];
573
574 u8 reserved_at_60[0x20];
575 };
576
577 struct mlx5_ifc_l2_hdr_bits {
578 u8 dmac_47_16[0x20];
579
580 u8 dmac_15_0[0x10];
581 u8 smac_47_32[0x10];
582
583 u8 smac_31_0[0x20];
584
585 u8 ethertype[0x10];
586 u8 vlan_type[0x10];
587
588 u8 vlan[0x10];
589 u8 reserved_at_90[0x10];
590 };
591
592
593 struct mlx5_ifc_dr_action_hw_set_bits {
594 u8 opcode[0x8];
595 u8 destination_field_code[0x8];
596 u8 reserved_at_10[0x2];
597 u8 destination_left_shifter[0x6];
598 u8 reserved_at_18[0x3];
599 u8 destination_length[0x5];
600
601 u8 inline_data[0x20];
602 };
603
604 #endif