This source file includes following definitions.
- mlx5e_get_num_lag_ports
- mlx5_min_rx_wqes
- mlx5e_get_max_num_channels
- mlx5e_rqwq_get_size
- mlx5e_rqwq_get_cur_sz
- mlx5_tx_swp_supported
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32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
50 #include <net/xdp.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
53 #include "wq.h"
54 #include "mlx5_core.h"
55 #include "en_stats.h"
56 #include "en/fs.h"
57 #include "lib/hv_vhca.h"
58
59 extern const struct net_device_ops mlx5e_netdev_ops;
60 struct page_pool;
61
62 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
63 #define MLX5E_METADATA_ETHER_LEN 8
64
65 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
66
67 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
68
69 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
70 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
71
72 #define MLX5E_MAX_PRIORITY 8
73 #define MLX5E_MAX_DSCP 64
74 #define MLX5E_MAX_NUM_TC 8
75
76 #define MLX5_RX_HEADROOM NET_SKB_PAD
77 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
78 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
79
80 #define MLX5E_RX_MAX_HEAD (256)
81
82 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
83 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte))
84 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
85 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
86 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
87 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
88
89 #define MLX5_MPWRQ_LOG_WQE_SZ 18
90 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
91 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
92 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
93
94 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
95 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
96 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
97 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
98 #define MLX5E_MAX_RQ_NUM_MTTS \
99 ((1 << 16) * 2)
100 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
101 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
102 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
103 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
104 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
105 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
106
107 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
108 #define MLX5E_LOG_MAX_RX_WQE_BULK \
109 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
110
111 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
112 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
113 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
114
115 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
116 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
117 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
118 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
119
120 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
121
122 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
123 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
124 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
125
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
128 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
131 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
133 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
134
135 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
136 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
137 #define MLX5E_MIN_NUM_CHANNELS 0x1
138 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
139 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
140 #define MLX5E_TX_CQ_POLL_BUDGET 128
141 #define MLX5E_TX_XSK_POLL_BUDGET 64
142 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500
143
144 #define MLX5E_UMR_WQE_INLINE_SZ \
145 (sizeof(struct mlx5e_umr_wqe) + \
146 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
147 MLX5_UMR_MTT_ALIGNMENT))
148 #define MLX5E_UMR_WQEBBS \
149 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
150
151 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
152
153 #define mlx5e_dbg(mlevel, priv, format, ...) \
154 do { \
155 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
156 netdev_warn(priv->netdev, format, \
157 ##__VA_ARGS__); \
158 } while (0)
159
160 enum mlx5e_rq_group {
161 MLX5E_RQ_GROUP_REGULAR,
162 MLX5E_RQ_GROUP_XSK,
163 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
164 };
165
166 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
167 {
168 if (mlx5_lag_is_lacp_owner(mdev))
169 return 1;
170
171 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
172 }
173
174 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
175 {
176 switch (wq_type) {
177 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
178 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
179 wq_size / 2);
180 default:
181 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
182 wq_size / 2);
183 }
184 }
185
186
187 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
188 {
189 return is_kdump_kernel() ?
190 MLX5E_MIN_NUM_CHANNELS :
191 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
192 }
193
194 struct mlx5e_tx_wqe {
195 struct mlx5_wqe_ctrl_seg ctrl;
196 union {
197 struct {
198 struct mlx5_wqe_eth_seg eth;
199 struct mlx5_wqe_data_seg data[0];
200 };
201 u8 tls_progress_params_ctx[0];
202 };
203 };
204
205 struct mlx5e_rx_wqe_ll {
206 struct mlx5_wqe_srq_next_seg next;
207 struct mlx5_wqe_data_seg data[0];
208 };
209
210 struct mlx5e_rx_wqe_cyc {
211 struct mlx5_wqe_data_seg data[0];
212 };
213
214 struct mlx5e_umr_wqe {
215 struct mlx5_wqe_ctrl_seg ctrl;
216 struct mlx5_wqe_umr_ctrl_seg uctrl;
217 struct mlx5_mkey_seg mkc;
218 union {
219 struct mlx5_mtt inline_mtts[0];
220 u8 tls_static_params_ctx[0];
221 };
222 };
223
224 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
225
226 enum mlx5e_priv_flag {
227 MLX5E_PFLAG_RX_CQE_BASED_MODER,
228 MLX5E_PFLAG_TX_CQE_BASED_MODER,
229 MLX5E_PFLAG_RX_CQE_COMPRESS,
230 MLX5E_PFLAG_RX_STRIDING_RQ,
231 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
232 MLX5E_PFLAG_XDP_TX_MPWQE,
233 MLX5E_NUM_PFLAGS,
234 };
235
236 #define MLX5E_SET_PFLAG(params, pflag, enable) \
237 do { \
238 if (enable) \
239 (params)->pflags |= BIT(pflag); \
240 else \
241 (params)->pflags &= ~(BIT(pflag)); \
242 } while (0)
243
244 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
245
246 #ifdef CONFIG_MLX5_CORE_EN_DCB
247 #define MLX5E_MAX_BW_ALLOC 100
248 #endif
249
250 struct mlx5e_params {
251 u8 log_sq_size;
252 u8 rq_wq_type;
253 u8 log_rq_mtu_frames;
254 u16 num_channels;
255 u8 num_tc;
256 bool rx_cqe_compress_def;
257 bool tunneled_offload_en;
258 struct dim_cq_moder rx_cq_moderation;
259 struct dim_cq_moder tx_cq_moderation;
260 bool lro_en;
261 u8 tx_min_inline_mode;
262 bool vlan_strip_disable;
263 bool scatter_fcs_en;
264 bool rx_dim_enabled;
265 bool tx_dim_enabled;
266 u32 lro_timeout;
267 u32 pflags;
268 struct bpf_prog *xdp_prog;
269 struct mlx5e_xsk *xsk;
270 unsigned int sw_mtu;
271 int hard_mtu;
272 };
273
274 #ifdef CONFIG_MLX5_CORE_EN_DCB
275 struct mlx5e_cee_config {
276
277 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
278 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
279 bool pfc_setting[CEE_DCBX_MAX_PRIO];
280 bool pfc_enable;
281 };
282
283 enum {
284 MLX5_DCB_CHG_RESET,
285 MLX5_DCB_NO_CHG,
286 MLX5_DCB_CHG_NO_RESET,
287 };
288
289 struct mlx5e_dcbx {
290 enum mlx5_dcbx_oper_mode mode;
291 struct mlx5e_cee_config cee_cfg;
292 u8 dscp_app_cnt;
293
294
295 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
296 u8 cap;
297
298
299 bool manual_buffer;
300 u32 cable_len;
301 u32 xoff;
302 };
303
304 struct mlx5e_dcbx_dp {
305 u8 dscp2prio[MLX5E_MAX_DSCP];
306 u8 trust_state;
307 };
308 #endif
309
310 enum {
311 MLX5E_RQ_STATE_ENABLED,
312 MLX5E_RQ_STATE_RECOVERING,
313 MLX5E_RQ_STATE_AM,
314 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
315 MLX5E_RQ_STATE_CSUM_FULL,
316 };
317
318 struct mlx5e_cq {
319
320 struct mlx5_cqwq wq;
321
322
323 u16 event_ctr;
324 struct napi_struct *napi;
325 struct mlx5_core_cq mcq;
326 struct mlx5e_channel *channel;
327
328
329 struct mlx5_core_dev *mdev;
330 struct mlx5_wq_ctrl wq_ctrl;
331 } ____cacheline_aligned_in_smp;
332
333 struct mlx5e_cq_decomp {
334
335 struct mlx5_cqe64 title;
336 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
337 u8 mini_arr_idx;
338 u16 left;
339 u16 wqe_counter;
340 } ____cacheline_aligned_in_smp;
341
342 struct mlx5e_tx_wqe_info {
343 struct sk_buff *skb;
344 u32 num_bytes;
345 u8 num_wqebbs;
346 u8 num_dma;
347 #ifdef CONFIG_MLX5_EN_TLS
348 struct page *resync_dump_frag_page;
349 #endif
350 };
351
352 enum mlx5e_dma_map_type {
353 MLX5E_DMA_MAP_SINGLE,
354 MLX5E_DMA_MAP_PAGE
355 };
356
357 struct mlx5e_sq_dma {
358 dma_addr_t addr;
359 u32 size;
360 enum mlx5e_dma_map_type type;
361 };
362
363 enum {
364 MLX5E_SQ_STATE_ENABLED,
365 MLX5E_SQ_STATE_RECOVERING,
366 MLX5E_SQ_STATE_IPSEC,
367 MLX5E_SQ_STATE_AM,
368 MLX5E_SQ_STATE_TLS,
369 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
370 MLX5E_SQ_STATE_PENDING_XSK_TX,
371 };
372
373 struct mlx5e_sq_wqe_info {
374 u8 opcode;
375 u8 num_wqebbs;
376
377
378 union {
379 struct {
380 struct mlx5e_rq *rq;
381 } umr;
382 };
383 };
384
385 struct mlx5e_txqsq {
386
387
388
389 u16 cc;
390 u32 dma_fifo_cc;
391 struct dim dim;
392
393
394 u16 pc ____cacheline_aligned_in_smp;
395 u32 dma_fifo_pc;
396
397 struct mlx5e_cq cq;
398
399
400 struct mlx5_wq_cyc wq;
401 u32 dma_fifo_mask;
402 struct mlx5e_sq_stats *stats;
403 struct {
404 struct mlx5e_sq_dma *dma_fifo;
405 struct mlx5e_tx_wqe_info *wqe_info;
406 } db;
407 void __iomem *uar_map;
408 struct netdev_queue *txq;
409 u32 sqn;
410 u16 stop_room;
411 u8 min_inline_mode;
412 struct device *pdev;
413 __be32 mkey_be;
414 unsigned long state;
415 unsigned int hw_mtu;
416 struct hwtstamp_config *tstamp;
417 struct mlx5_clock *clock;
418
419
420 struct mlx5_wq_ctrl wq_ctrl;
421 struct mlx5e_channel *channel;
422 int ch_ix;
423 int txq_ix;
424 u32 rate_limit;
425 struct work_struct recover_work;
426 } ____cacheline_aligned_in_smp;
427
428 struct mlx5e_dma_info {
429 dma_addr_t addr;
430 union {
431 struct page *page;
432 struct {
433 u64 handle;
434 void *data;
435 } xsk;
436 };
437 };
438
439
440
441
442 enum mlx5e_xdp_xmit_mode {
443
444
445
446
447 MLX5E_XDP_XMIT_MODE_FRAME,
448
449
450
451
452 MLX5E_XDP_XMIT_MODE_PAGE,
453
454
455
456
457 MLX5E_XDP_XMIT_MODE_XSK,
458 };
459
460 struct mlx5e_xdp_info {
461 enum mlx5e_xdp_xmit_mode mode;
462 union {
463 struct {
464 struct xdp_frame *xdpf;
465 dma_addr_t dma_addr;
466 } frame;
467 struct {
468 struct mlx5e_rq *rq;
469 struct mlx5e_dma_info di;
470 } page;
471 };
472 };
473
474 struct mlx5e_xdp_xmit_data {
475 dma_addr_t dma_addr;
476 void *data;
477 u32 len;
478 };
479
480 struct mlx5e_xdp_info_fifo {
481 struct mlx5e_xdp_info *xi;
482 u32 *cc;
483 u32 *pc;
484 u32 mask;
485 };
486
487 struct mlx5e_xdp_wqe_info {
488 u8 num_wqebbs;
489 u8 num_pkts;
490 };
491
492 struct mlx5e_xdp_mpwqe {
493
494 struct mlx5e_tx_wqe *wqe;
495 u8 ds_count;
496 u8 pkt_count;
497 u8 inline_on;
498 };
499
500 struct mlx5e_xdpsq;
501 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
502 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
503 struct mlx5e_xdp_xmit_data *,
504 struct mlx5e_xdp_info *,
505 int);
506
507 struct mlx5e_xdpsq {
508
509
510
511 u32 xdpi_fifo_cc;
512 u16 cc;
513
514
515 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
516 u16 pc;
517 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
518 struct mlx5e_xdp_mpwqe mpwqe;
519
520 struct mlx5e_cq cq;
521
522
523 struct xdp_umem *umem;
524 struct mlx5_wq_cyc wq;
525 struct mlx5e_xdpsq_stats *stats;
526 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
527 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
528 struct {
529 struct mlx5e_xdp_wqe_info *wqe_info;
530 struct mlx5e_xdp_info_fifo xdpi_fifo;
531 } db;
532 void __iomem *uar_map;
533 u32 sqn;
534 struct device *pdev;
535 __be32 mkey_be;
536 u8 min_inline_mode;
537 unsigned long state;
538 unsigned int hw_mtu;
539
540
541 struct mlx5_wq_ctrl wq_ctrl;
542 struct mlx5e_channel *channel;
543 } ____cacheline_aligned_in_smp;
544
545 struct mlx5e_icosq {
546
547 u16 cc;
548 u16 pc;
549
550 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
551 struct mlx5e_cq cq;
552
553
554 struct {
555 struct mlx5e_sq_wqe_info *ico_wqe;
556 } db;
557
558
559 struct mlx5_wq_cyc wq;
560 void __iomem *uar_map;
561 u32 sqn;
562 unsigned long state;
563
564
565 struct mlx5_wq_ctrl wq_ctrl;
566 struct mlx5e_channel *channel;
567
568 struct work_struct recover_work;
569 } ____cacheline_aligned_in_smp;
570
571 struct mlx5e_wqe_frag_info {
572 struct mlx5e_dma_info *di;
573 u32 offset;
574 bool last_in_page;
575 };
576
577 struct mlx5e_umr_dma_info {
578 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
579 };
580
581 struct mlx5e_mpw_info {
582 struct mlx5e_umr_dma_info umr;
583 u16 consumed_strides;
584 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
585 };
586
587 #define MLX5E_MAX_RX_FRAGS 4
588
589
590
591
592 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
593 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
594 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
595 struct mlx5e_page_cache {
596 u32 head;
597 u32 tail;
598 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
599 };
600
601 struct mlx5e_rq;
602 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
603 typedef struct sk_buff *
604 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
605 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
606 typedef struct sk_buff *
607 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
608 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
609 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
610 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
611
612 enum mlx5e_rq_flag {
613 MLX5E_RQ_FLAG_XDP_XMIT,
614 MLX5E_RQ_FLAG_XDP_REDIRECT,
615 };
616
617 struct mlx5e_rq_frag_info {
618 int frag_size;
619 int frag_stride;
620 };
621
622 struct mlx5e_rq_frags_info {
623 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
624 u8 num_frags;
625 u8 log_num_frags;
626 u8 wqe_bulk;
627 };
628
629 struct mlx5e_rq {
630
631 union {
632 struct {
633 struct mlx5_wq_cyc wq;
634 struct mlx5e_wqe_frag_info *frags;
635 struct mlx5e_dma_info *di;
636 struct mlx5e_rq_frags_info info;
637 mlx5e_fp_skb_from_cqe skb_from_cqe;
638 } wqe;
639 struct {
640 struct mlx5_wq_ll wq;
641 struct mlx5e_umr_wqe umr_wqe;
642 struct mlx5e_mpw_info *info;
643 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
644 u16 num_strides;
645 u16 actual_wq_head;
646 u8 log_stride_sz;
647 u8 umr_in_progress;
648 u8 umr_last_bulk;
649 u8 umr_completed;
650 } mpwqe;
651 };
652 struct {
653 u16 umem_headroom;
654 u16 headroom;
655 u8 map_dir;
656 } buff;
657
658 struct mlx5e_channel *channel;
659 struct device *pdev;
660 struct net_device *netdev;
661 struct mlx5e_rq_stats *stats;
662 struct mlx5e_cq cq;
663 struct mlx5e_cq_decomp cqd;
664 struct mlx5e_page_cache page_cache;
665 struct hwtstamp_config *tstamp;
666 struct mlx5_clock *clock;
667
668 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
669 mlx5e_fp_post_rx_wqes post_wqes;
670 mlx5e_fp_dealloc_wqe dealloc_wqe;
671
672 unsigned long state;
673 int ix;
674 unsigned int hw_mtu;
675
676 struct dim dim;
677
678
679 struct bpf_prog *xdp_prog;
680 struct mlx5e_xdpsq *xdpsq;
681 DECLARE_BITMAP(flags, 8);
682 struct page_pool *page_pool;
683
684
685 struct zero_copy_allocator zca;
686 struct xdp_umem *umem;
687
688 struct work_struct recover_work;
689
690
691 struct mlx5_wq_ctrl wq_ctrl;
692 __be32 mkey_be;
693 u8 wq_type;
694 u32 rqn;
695 struct mlx5_core_dev *mdev;
696 struct mlx5_core_mkey umr_mkey;
697
698
699 struct xdp_rxq_info xdp_rxq;
700 } ____cacheline_aligned_in_smp;
701
702 enum mlx5e_channel_state {
703 MLX5E_CHANNEL_STATE_XSK,
704 MLX5E_CHANNEL_NUM_STATES
705 };
706
707 struct mlx5e_channel {
708
709 struct mlx5e_rq rq;
710 struct mlx5e_xdpsq rq_xdpsq;
711 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
712 struct mlx5e_icosq icosq;
713 bool xdp;
714 struct napi_struct napi;
715 struct device *pdev;
716 struct net_device *netdev;
717 __be32 mkey_be;
718 u8 num_tc;
719 u8 lag_port;
720
721
722 struct mlx5e_xdpsq xdpsq;
723
724
725 struct mlx5e_rq xskrq;
726 struct mlx5e_xdpsq xsksq;
727 struct mlx5e_icosq xskicosq;
728
729 spinlock_t xskicosq_lock;
730
731
732 struct irq_desc *irq_desc;
733 struct mlx5e_ch_stats *stats;
734
735
736 struct mlx5e_priv *priv;
737 struct mlx5_core_dev *mdev;
738 struct hwtstamp_config *tstamp;
739 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
740 int ix;
741 int cpu;
742 cpumask_var_t xps_cpumask;
743 };
744
745 struct mlx5e_channels {
746 struct mlx5e_channel **c;
747 unsigned int num;
748 struct mlx5e_params params;
749 };
750
751 struct mlx5e_channel_stats {
752 struct mlx5e_ch_stats ch;
753 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
754 struct mlx5e_rq_stats rq;
755 struct mlx5e_rq_stats xskrq;
756 struct mlx5e_xdpsq_stats rq_xdpsq;
757 struct mlx5e_xdpsq_stats xdpsq;
758 struct mlx5e_xdpsq_stats xsksq;
759 } ____cacheline_aligned_in_smp;
760
761 enum {
762 MLX5E_STATE_OPENED,
763 MLX5E_STATE_DESTROYING,
764 MLX5E_STATE_XDP_TX_ENABLED,
765 MLX5E_STATE_XDP_ACTIVE,
766 };
767
768 struct mlx5e_rqt {
769 u32 rqtn;
770 bool enabled;
771 };
772
773 struct mlx5e_tir {
774 u32 tirn;
775 struct mlx5e_rqt rqt;
776 struct list_head list;
777 };
778
779 enum {
780 MLX5E_TC_PRIO = 0,
781 MLX5E_NIC_PRIO
782 };
783
784 struct mlx5e_rss_params {
785 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
786 u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];
787 u8 toeplitz_hash_key[40];
788 u8 hfunc;
789 };
790
791 struct mlx5e_modify_sq_param {
792 int curr_state;
793 int next_state;
794 int rl_update;
795 int rl_index;
796 };
797
798 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
799 struct mlx5e_hv_vhca_stats_agent {
800 struct mlx5_hv_vhca_agent *agent;
801 struct delayed_work work;
802 u16 delay;
803 void *buf;
804 };
805 #endif
806
807 struct mlx5e_xsk {
808
809
810
811
812
813 struct xdp_umem **umems;
814 u16 refcnt;
815 bool ever_used;
816 };
817
818 struct mlx5e_priv {
819
820 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
821 int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
822 #ifdef CONFIG_MLX5_CORE_EN_DCB
823 struct mlx5e_dcbx_dp dcbx_dp;
824 #endif
825
826
827 u32 msglevel;
828 unsigned long state;
829 struct mutex state_lock;
830 struct mlx5e_rq drop_rq;
831
832 struct mlx5e_channels channels;
833 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
834 struct mlx5e_rqt indir_rqt;
835 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
836 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
837 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
838 struct mlx5e_tir xsk_tir[MLX5E_MAX_NUM_CHANNELS];
839 struct mlx5e_rss_params rss_params;
840 u32 tx_rates[MLX5E_MAX_NUM_SQS];
841
842 struct mlx5e_flow_steering fs;
843
844 struct workqueue_struct *wq;
845 struct work_struct update_carrier_work;
846 struct work_struct set_rx_mode_work;
847 struct work_struct tx_timeout_work;
848 struct work_struct update_stats_work;
849 struct work_struct monitor_counters_work;
850 struct mlx5_nb monitor_counters_nb;
851
852 struct mlx5_core_dev *mdev;
853 struct net_device *netdev;
854 struct mlx5e_stats stats;
855 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
856 u16 max_nch;
857 u8 max_opened_tc;
858 struct hwtstamp_config tstamp;
859 u16 q_counter;
860 u16 drop_rq_q_counter;
861 struct notifier_block events_nb;
862
863 #ifdef CONFIG_MLX5_CORE_EN_DCB
864 struct mlx5e_dcbx dcbx;
865 #endif
866
867 const struct mlx5e_profile *profile;
868 void *ppriv;
869 #ifdef CONFIG_MLX5_EN_IPSEC
870 struct mlx5e_ipsec *ipsec;
871 #endif
872 #ifdef CONFIG_MLX5_EN_TLS
873 struct mlx5e_tls *tls;
874 #endif
875 struct devlink_health_reporter *tx_reporter;
876 struct devlink_health_reporter *rx_reporter;
877 struct mlx5e_xsk xsk;
878 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
879 struct mlx5e_hv_vhca_stats_agent stats_agent;
880 #endif
881 };
882
883 struct mlx5e_profile {
884 int (*init)(struct mlx5_core_dev *mdev,
885 struct net_device *netdev,
886 const struct mlx5e_profile *profile, void *ppriv);
887 void (*cleanup)(struct mlx5e_priv *priv);
888 int (*init_rx)(struct mlx5e_priv *priv);
889 void (*cleanup_rx)(struct mlx5e_priv *priv);
890 int (*init_tx)(struct mlx5e_priv *priv);
891 void (*cleanup_tx)(struct mlx5e_priv *priv);
892 void (*enable)(struct mlx5e_priv *priv);
893 void (*disable)(struct mlx5e_priv *priv);
894 int (*update_rx)(struct mlx5e_priv *priv);
895 void (*update_stats)(struct mlx5e_priv *priv);
896 void (*update_carrier)(struct mlx5e_priv *priv);
897 struct {
898 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
899 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
900 } rx_handlers;
901 int max_tc;
902 u8 rq_groups;
903 };
904
905 void mlx5e_build_ptys2ethtool_map(void);
906
907 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
908 struct net_device *sb_dev);
909 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
910 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
911 struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more);
912
913 void mlx5e_trigger_irq(struct mlx5e_icosq *sq);
914 void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe);
915 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
916 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
917 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
918 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
919 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
920
921 static inline u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
922 {
923 switch (rq->wq_type) {
924 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
925 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
926 default:
927 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
928 }
929 }
930
931 static inline u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
932 {
933 switch (rq->wq_type) {
934 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
935 return rq->mpwqe.wq.cur_sz;
936 default:
937 return rq->wqe.wq.cur_sz;
938 }
939 }
940
941 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
942 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
943 struct mlx5e_params *params);
944
945 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info);
946 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
947 struct mlx5e_dma_info *dma_info,
948 bool recycle);
949 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
950 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
951 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
952 int mlx5e_poll_ico_cq(struct mlx5e_cq *cq);
953 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
954 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
955 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
956 struct sk_buff *
957 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
958 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
959 struct sk_buff *
960 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
961 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
962 struct sk_buff *
963 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
964 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
965 struct sk_buff *
966 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
967 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
968
969 void mlx5e_update_stats(struct mlx5e_priv *priv);
970 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
971 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
972
973 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
974 int mlx5e_self_test_num(struct mlx5e_priv *priv);
975 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
976 u64 *buf);
977 void mlx5e_set_rx_mode_work(struct work_struct *work);
978
979 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
980 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
981 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
982
983 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
984 u16 vid);
985 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
986 u16 vid);
987 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
988
989 struct mlx5e_redirect_rqt_param {
990 bool is_rss;
991 union {
992 u32 rqn;
993 struct {
994 u8 hfunc;
995 struct mlx5e_channels *channels;
996 } rss;
997 };
998 };
999
1000 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
1001 struct mlx5e_redirect_rqt_param rrp);
1002 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
1003 const struct mlx5e_tirc_config *ttconfig,
1004 void *tirc, bool inner);
1005 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen);
1006 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
1007
1008 struct mlx5e_xsk_param;
1009
1010 struct mlx5e_rq_param;
1011 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
1012 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
1013 struct xdp_umem *umem, struct mlx5e_rq *rq);
1014 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
1015 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1016 void mlx5e_close_rq(struct mlx5e_rq *rq);
1017
1018 struct mlx5e_sq_param;
1019 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1020 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq);
1021 void mlx5e_close_icosq(struct mlx5e_icosq *sq);
1022 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1023 struct mlx5e_sq_param *param, struct xdp_umem *umem,
1024 struct mlx5e_xdpsq *sq, bool is_redirect);
1025 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
1026
1027 struct mlx5e_cq_param;
1028 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1029 struct mlx5e_cq_param *param, struct mlx5e_cq *cq);
1030 void mlx5e_close_cq(struct mlx5e_cq *cq);
1031
1032 int mlx5e_open_locked(struct net_device *netdev);
1033 int mlx5e_close_locked(struct net_device *netdev);
1034
1035 int mlx5e_open_channels(struct mlx5e_priv *priv,
1036 struct mlx5e_channels *chs);
1037 void mlx5e_close_channels(struct mlx5e_channels *chs);
1038
1039
1040
1041
1042 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv);
1043 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1044 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
1045 struct mlx5e_channels *new_chs,
1046 mlx5e_fp_preactivate preactivate);
1047 int mlx5e_num_channels_changed(struct mlx5e_priv *priv);
1048 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1049 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1050
1051 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
1052 int num_channels);
1053 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
1054 u8 cq_period_mode);
1055 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
1056 u8 cq_period_mode);
1057 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
1058 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
1059 struct mlx5e_params *params);
1060 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state);
1061 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1062 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1063 void mlx5e_free_rx_descs(struct mlx5e_rq *rq);
1064 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq);
1065 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1066 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1067
1068 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1069 struct mlx5e_modify_sq_param *p);
1070 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1071 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1072
1073 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1074 {
1075 return MLX5_CAP_ETH(mdev, swp) &&
1076 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1077 }
1078
1079 extern const struct ethtool_ops mlx5e_ethtool_ops;
1080 #ifdef CONFIG_MLX5_CORE_EN_DCB
1081 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
1082 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
1083 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
1084 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
1085 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
1086 #endif
1087
1088 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
1089 struct mlx5e_tir *tir, u32 *in, int inlen);
1090 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1091 struct mlx5e_tir *tir);
1092 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1093 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1094 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
1095
1096
1097 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1098 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1099 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1100 struct mlx5e_rq *drop_rq);
1101 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1102
1103 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1104
1105 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1106 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
1107
1108 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1109 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1110 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1111 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1112 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1113
1114 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1115 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1116
1117 int mlx5e_create_tises(struct mlx5e_priv *priv);
1118 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1119 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1120 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1121 int mlx5e_close(struct net_device *netdev);
1122 int mlx5e_open(struct net_device *netdev);
1123 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv);
1124
1125 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1126 int mlx5e_bits_invert(unsigned long a, int size);
1127
1128 typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv);
1129 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1130 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1131 change_hw_mtu_cb set_mtu_cb);
1132
1133
1134 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1135 struct ethtool_drvinfo *drvinfo);
1136 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1137 uint32_t stringset, uint8_t *data);
1138 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1139 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1140 struct ethtool_stats *stats, u64 *data);
1141 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1142 struct ethtool_ringparam *param);
1143 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1144 struct ethtool_ringparam *param);
1145 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1146 struct ethtool_channels *ch);
1147 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1148 struct ethtool_channels *ch);
1149 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1150 struct ethtool_coalesce *coal);
1151 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1152 struct ethtool_coalesce *coal);
1153 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1154 struct ethtool_link_ksettings *link_ksettings);
1155 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1156 const struct ethtool_link_ksettings *link_ksettings);
1157 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1158 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1159 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1160 struct ethtool_ts_info *info);
1161 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1162 struct ethtool_flash *flash);
1163 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1164 struct ethtool_pauseparam *pauseparam);
1165 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1166 struct ethtool_pauseparam *pauseparam);
1167
1168
1169 int mlx5e_netdev_init(struct net_device *netdev,
1170 struct mlx5e_priv *priv,
1171 struct mlx5_core_dev *mdev,
1172 const struct mlx5e_profile *profile,
1173 void *ppriv);
1174 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv);
1175 struct net_device*
1176 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1177 int nch, void *ppriv);
1178 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1179 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1180 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1181 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1182 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1183 struct mlx5e_xsk *xsk,
1184 struct mlx5e_rss_params *rss_params,
1185 struct mlx5e_params *params,
1186 u16 max_channels, u16 mtu);
1187 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
1188 struct mlx5e_params *params);
1189 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
1190 u16 num_channels);
1191 void mlx5e_rx_dim_work(struct work_struct *work);
1192 void mlx5e_tx_dim_work(struct work_struct *work);
1193
1194 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1195 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1196 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1197 struct net_device *netdev,
1198 netdev_features_t features);
1199 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1200 #ifdef CONFIG_MLX5_ESWITCH
1201 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1202 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1203 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1204 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1205 #endif
1206 #endif