1 /*
2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef MLX5_FPGA_SDK_H
35 #define MLX5_FPGA_SDK_H
36
37 #include <linux/types.h>
38 #include <linux/dma-direction.h>
39
40 /**
41 * DOC: Innova SDK
42 * This header defines the in-kernel API for Innova FPGA client drivers.
43 */
44 #define SBU_QP_QUEUE_SIZE 8
45 #define MLX5_FPGA_CMD_TIMEOUT_MSEC (60 * 1000)
46
47 /**
48 * enum mlx5_fpga_access_type - Enumerated the different methods possible for
49 * accessing the device memory address space
50 */
51 enum mlx5_fpga_access_type {
52 /** Use the slow CX-FPGA I2C bus */
53 MLX5_FPGA_ACCESS_TYPE_I2C = 0x0,
54 /** Use the fastest available method */
55 MLX5_FPGA_ACCESS_TYPE_DONTCARE = 0x0,
56 };
57
58 struct mlx5_fpga_conn;
59 struct mlx5_fpga_device;
60
61 /**
62 * struct mlx5_fpga_dma_entry - A scatter-gather DMA entry
63 */
64 struct mlx5_fpga_dma_entry {
65 /** @data: Virtual address pointer to the data */
66 void *data;
67 /** @size: Size in bytes of the data */
68 unsigned int size;
69 /** @dma_addr: Private member. Physical DMA-mapped address of the data */
70 dma_addr_t dma_addr;
71 };
72
73 /**
74 * struct mlx5_fpga_dma_buf - A packet buffer
75 * May contain up to 2 scatter-gather data entries
76 */
77 struct mlx5_fpga_dma_buf {
78 /** @dma_dir: DMA direction */
79 enum dma_data_direction dma_dir;
80 /** @sg: Scatter-gather entries pointing to the data in memory */
81 struct mlx5_fpga_dma_entry sg[2];
82 /** @list: Item in SQ backlog, for TX packets */
83 struct list_head list;
84 /**
85 * @complete: Completion routine, for TX packets
86 * @conn: FPGA Connection this packet was sent to
87 * @fdev: FPGA device this packet was sent to
88 * @buf: The packet buffer
89 * @status: 0 if successful, or an error code otherwise
90 */
91 void (*complete)(struct mlx5_fpga_conn *conn,
92 struct mlx5_fpga_device *fdev,
93 struct mlx5_fpga_dma_buf *buf, u8 status);
94 };
95
96 /**
97 * struct mlx5_fpga_conn_attr - FPGA connection attributes
98 * Describes the attributes of a connection
99 */
100 struct mlx5_fpga_conn_attr {
101 /** @tx_size: Size of connection TX queue, in packets */
102 unsigned int tx_size;
103 /** @rx_size: Size of connection RX queue, in packets */
104 unsigned int rx_size;
105 /**
106 * @recv_cb: Callback function which is called for received packets
107 * @cb_arg: The value provided in mlx5_fpga_conn_attr.cb_arg
108 * @buf: A buffer containing a received packet
109 *
110 * buf is guaranteed to only contain a single scatter-gather entry.
111 * The size of the actual packet received is specified in buf.sg[0].size
112 * When this callback returns, the packet buffer may be re-used for
113 * subsequent receives.
114 */
115 void (*recv_cb)(void *cb_arg, struct mlx5_fpga_dma_buf *buf);
116 void *cb_arg;
117 };
118
119 /**
120 * mlx5_fpga_sbu_conn_create() - Initialize a new FPGA SBU connection
121 * @fdev: The FPGA device
122 * @attr: Attributes of the new connection
123 *
124 * Sets up a new FPGA SBU connection with the specified attributes.
125 * The receive callback function may be called for incoming messages even
126 * before this function returns.
127 *
128 * The caller must eventually destroy the connection by calling
129 * mlx5_fpga_sbu_conn_destroy.
130 *
131 * Return: A new connection, or ERR_PTR() error value otherwise.
132 */
133 struct mlx5_fpga_conn *
134 mlx5_fpga_sbu_conn_create(struct mlx5_fpga_device *fdev,
135 struct mlx5_fpga_conn_attr *attr);
136
137 /**
138 * mlx5_fpga_sbu_conn_destroy() - Destroy an FPGA SBU connection
139 * @conn: The FPGA SBU connection to destroy
140 *
141 * Cleans up an FPGA SBU connection which was previously created with
142 * mlx5_fpga_sbu_conn_create.
143 */
144 void mlx5_fpga_sbu_conn_destroy(struct mlx5_fpga_conn *conn);
145
146 /**
147 * mlx5_fpga_sbu_conn_sendmsg() - Queue the transmission of a packet
148 * @fdev: An FPGA SBU connection
149 * @buf: The packet buffer
150 *
151 * Queues a packet for transmission over an FPGA SBU connection.
152 * The buffer should not be modified or freed until completion.
153 * Upon completion, the buf's complete() callback is invoked, indicating the
154 * success or error status of the transmission.
155 *
156 * Return: 0 if successful, or an error value otherwise.
157 */
158 int mlx5_fpga_sbu_conn_sendmsg(struct mlx5_fpga_conn *conn,
159 struct mlx5_fpga_dma_buf *buf);
160
161 /**
162 * mlx5_fpga_mem_read() - Read from FPGA memory address space
163 * @fdev: The FPGA device
164 * @size: Size of chunk to read, in bytes
165 * @addr: Starting address to read from, in FPGA address space
166 * @buf: Buffer to read into
167 * @access_type: Method for reading
168 *
169 * Reads from the specified address into the specified buffer.
170 * The address may point to configuration space or to DDR.
171 * Large reads may be performed internally as several non-atomic operations.
172 * This function may sleep, so should not be called from atomic contexts.
173 *
174 * Return: 0 if successful, or an error value otherwise.
175 */
176 int mlx5_fpga_mem_read(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
177 void *buf, enum mlx5_fpga_access_type access_type);
178
179 /**
180 * mlx5_fpga_mem_write() - Write to FPGA memory address space
181 * @fdev: The FPGA device
182 * @size: Size of chunk to write, in bytes
183 * @addr: Starting address to write to, in FPGA address space
184 * @buf: Buffer which contains data to write
185 * @access_type: Method for writing
186 *
187 * Writes the specified buffer data to FPGA memory at the specified address.
188 * The address may point to configuration space or to DDR.
189 * Large writes may be performed internally as several non-atomic operations.
190 * This function may sleep, so should not be called from atomic contexts.
191 *
192 * Return: 0 if successful, or an error value otherwise.
193 */
194 int mlx5_fpga_mem_write(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
195 void *buf, enum mlx5_fpga_access_type access_type);
196
197 /**
198 * mlx5_fpga_get_sbu_caps() - Read the SBU capabilities
199 * @fdev: The FPGA device
200 * @size: Size of the buffer to read into
201 * @buf: Buffer to read the capabilities into
202 *
203 * Reads the FPGA SBU capabilities into the specified buffer.
204 * The format of the capabilities buffer is SBU-dependent.
205 *
206 * Return: 0 if successful
207 * -EINVAL if the buffer is not large enough to contain SBU caps
208 * or any other error value otherwise.
209 */
210 int mlx5_fpga_get_sbu_caps(struct mlx5_fpga_device *fdev, int size, void *buf);
211
212 #endif /* MLX5_FPGA_SDK_H */