This source file includes following definitions.
- mlxsw_sp_component_query
- mlxsw_sp_fsm_lock
- mlxsw_sp_fsm_component_update
- mlxsw_sp_fsm_block_download
- mlxsw_sp_fsm_component_verify
- mlxsw_sp_fsm_activate
- mlxsw_sp_fsm_query_state
- mlxsw_sp_fsm_cancel
- mlxsw_sp_fsm_release
- mlxsw_sp_status_notify
- mlxsw_sp_firmware_flash
- mlxsw_sp_fw_rev_validate
- mlxsw_sp_flash_update
- mlxsw_sp_flow_counter_get
- mlxsw_sp_flow_counter_clear
- mlxsw_sp_flow_counter_alloc
- mlxsw_sp_flow_counter_free
- mlxsw_sp_txhdr_construct
- mlxsw_sp_stp_spms_state
- mlxsw_sp_port_vid_stp_set
- mlxsw_sp_base_mac_get
- mlxsw_sp_port_sample_set
- mlxsw_sp_port_admin_status_set
- mlxsw_sp_port_dev_addr_set
- mlxsw_sp_port_dev_addr_init
- mlxsw_sp_port_mtu_set
- mlxsw_sp_port_swid_set
- mlxsw_sp_port_vp_mode_set
- mlxsw_sp_port_vid_learning_set
- __mlxsw_sp_port_pvid_set
- mlxsw_sp_port_allow_untagged_set
- mlxsw_sp_port_pvid_set
- mlxsw_sp_port_system_port_mapping_set
- mlxsw_sp_port_module_info_get
- mlxsw_sp_port_module_map
- mlxsw_sp_port_module_unmap
- mlxsw_sp_port_open
- mlxsw_sp_port_stop
- mlxsw_sp_port_xmit
- mlxsw_sp_set_rx_mode
- mlxsw_sp_port_set_mac_address
- mlxsw_sp_pg_buf_threshold_get
- mlxsw_sp_pfc_delay_get
- mlxsw_sp_pg_buf_delay_get
- mlxsw_sp_pg_buf_pack
- __mlxsw_sp_port_headroom_set
- mlxsw_sp_port_headroom_set
- mlxsw_sp_port_change_mtu
- mlxsw_sp_port_get_sw_stats64
- mlxsw_sp_port_has_offload_stats
- mlxsw_sp_port_get_offload_stats
- mlxsw_sp_port_get_stats_raw
- mlxsw_sp_port_get_hw_stats
- mlxsw_sp_port_get_hw_xstats
- update_stats_cache
- mlxsw_sp_port_get_stats64
- __mlxsw_sp_port_vlan_set
- mlxsw_sp_port_vlan_set
- mlxsw_sp_port_vlan_flush
- mlxsw_sp_port_vlan_cleanup
- mlxsw_sp_port_vlan_create
- mlxsw_sp_port_vlan_destroy
- mlxsw_sp_port_add_vid
- mlxsw_sp_port_kill_vid
- mlxsw_sp_port_mall_tc_entry_find
- mlxsw_sp_port_add_cls_matchall_mirror
- mlxsw_sp_port_del_cls_matchall_mirror
- mlxsw_sp_port_add_cls_matchall_sample
- mlxsw_sp_port_del_cls_matchall_sample
- mlxsw_sp_port_add_cls_matchall
- mlxsw_sp_port_del_cls_matchall
- mlxsw_sp_setup_tc_cls_matchall
- mlxsw_sp_setup_tc_cls_flower
- mlxsw_sp_setup_tc_block_cb_matchall
- mlxsw_sp_setup_tc_block_cb_matchall_ig
- mlxsw_sp_setup_tc_block_cb_matchall_eg
- mlxsw_sp_setup_tc_block_cb_flower
- mlxsw_sp_tc_block_flower_release
- mlxsw_sp_setup_tc_block_flower_bind
- mlxsw_sp_setup_tc_block_flower_unbind
- mlxsw_sp_setup_tc_block
- mlxsw_sp_setup_tc
- mlxsw_sp_feature_hw_tc
- mlxsw_sp_feature_loopback
- mlxsw_sp_handle_feature
- mlxsw_sp_set_features
- mlxsw_sp_port_get_devlink_port
- mlxsw_sp_port_hwtstamp_set
- mlxsw_sp_port_hwtstamp_get
- mlxsw_sp_port_ptp_clear
- mlxsw_sp_port_ioctl
- mlxsw_sp_port_get_drvinfo
- mlxsw_sp_port_get_pauseparam
- mlxsw_sp_port_pause_set
- mlxsw_sp_port_set_pauseparam
- mlxsw_sp_port_get_prio_strings
- mlxsw_sp_port_get_tc_strings
- mlxsw_sp_port_get_strings
- mlxsw_sp_port_set_phys_id
- mlxsw_sp_get_hw_stats_by_group
- __mlxsw_sp_port_get_stats
- mlxsw_sp_port_get_stats
- mlxsw_sp_port_get_sset_count
- mlxsw_sp1_from_ptys_supported_port
- mlxsw_sp1_from_ptys_link
- mlxsw_sp1_from_ptys_speed
- mlxsw_sp1_from_ptys_speed_duplex
- mlxsw_sp1_to_ptys_advert_link
- mlxsw_sp1_to_ptys_speed
- mlxsw_sp1_to_ptys_upper_speed
- mlxsw_sp1_port_speed_base
- mlxsw_sp1_reg_ptys_eth_pack
- mlxsw_sp1_reg_ptys_eth_unpack
- mlxsw_sp_port_mask_width_get
- mlxsw_sp2_from_ptys_supported_port
- mlxsw_sp2_set_bit_ethtool
- mlxsw_sp2_from_ptys_link
- mlxsw_sp2_from_ptys_speed
- mlxsw_sp2_from_ptys_speed_duplex
- mlxsw_sp2_test_bit_ethtool
- mlxsw_sp2_to_ptys_advert_link
- mlxsw_sp2_to_ptys_speed
- mlxsw_sp2_to_ptys_upper_speed
- mlxsw_sp2_port_speed_base
- mlxsw_sp2_reg_ptys_eth_pack
- mlxsw_sp2_reg_ptys_eth_unpack
- mlxsw_sp_port_get_link_supported
- mlxsw_sp_port_get_link_advertise
- mlxsw_sp_port_connector_port
- mlxsw_sp_port_get_link_ksettings
- mlxsw_sp_port_set_link_ksettings
- mlxsw_sp_get_module_info
- mlxsw_sp_get_module_eeprom
- mlxsw_sp_get_ts_info
- mlxsw_sp_port_speed_by_width_set
- mlxsw_sp_port_ets_set
- mlxsw_sp_port_ets_maxrate_set
- mlxsw_sp_port_min_bw_set
- mlxsw_sp_port_prio_tc_set
- mlxsw_sp_port_ets_init
- mlxsw_sp_port_tc_mc_mode_set
- mlxsw_sp_port_create
- mlxsw_sp_port_remove
- mlxsw_sp_cpu_port_create
- mlxsw_sp_cpu_port_remove
- mlxsw_sp_port_created
- mlxsw_sp_ports_remove
- mlxsw_sp_ports_create
- mlxsw_sp_cluster_base_port_get
- mlxsw_sp_port_split_create
- mlxsw_sp_port_unsplit_create
- mlxsw_sp_port_get_by_local_port
- mlxsw_sp_port_split
- mlxsw_sp_port_unsplit
- mlxsw_sp_port_down_wipe_counters
- mlxsw_sp_pude_event_func
- mlxsw_sp1_ptp_fifo_event_func
- mlxsw_sp1_ptp_ing_fifo_event_func
- mlxsw_sp1_ptp_egr_fifo_event_func
- mlxsw_sp_rx_listener_no_mark_func
- mlxsw_sp_rx_listener_mark_func
- mlxsw_sp_rx_listener_l3_mark_func
- mlxsw_sp_rx_listener_sample_func
- mlxsw_sp_rx_listener_ptp
- mlxsw_sp_cpu_policers_set
- mlxsw_sp_trap_groups_set
- mlxsw_sp_traps_register
- mlxsw_sp_traps_unregister
- mlxsw_sp_traps_init
- mlxsw_sp_traps_fini
- mlxsw_sp_lag_init
- mlxsw_sp_lag_fini
- mlxsw_sp_basic_trap_groups_set
- mlxsw_sp_init
- mlxsw_sp1_init
- mlxsw_sp2_init
- mlxsw_sp_fini
- mlxsw_sp_resource_size_params_prepare
- mlxsw_sp1_resources_kvd_register
- mlxsw_sp2_resources_kvd_register
- mlxsw_sp1_resources_register
- mlxsw_sp2_resources_register
- mlxsw_sp_kvd_sizes_get
- mlxsw_sp_devlink_param_fw_load_policy_validate
- mlxsw_sp_params_register
- mlxsw_sp_params_unregister
- mlxsw_sp_params_acl_region_rehash_intrvl_get
- mlxsw_sp_params_acl_region_rehash_intrvl_set
- mlxsw_sp2_params_register
- mlxsw_sp2_params_unregister
- mlxsw_sp_ptp_transmitted
- mlxsw_sp_port_dev_check
- mlxsw_sp_lower_dev_walk
- mlxsw_sp_port_dev_lower_find
- mlxsw_sp_lower_get
- mlxsw_sp_port_dev_lower_find_rcu
- mlxsw_sp_port_lower_dev_hold
- mlxsw_sp_port_dev_put
- mlxsw_sp_port_lag_uppers_cleanup
- mlxsw_sp_lag_create
- mlxsw_sp_lag_destroy
- mlxsw_sp_lag_col_port_add
- mlxsw_sp_lag_col_port_remove
- mlxsw_sp_lag_col_port_enable
- mlxsw_sp_lag_col_port_disable
- mlxsw_sp_lag_index_get
- mlxsw_sp_master_lag_check
- mlxsw_sp_port_lag_index_get
- mlxsw_sp_port_lag_join
- mlxsw_sp_port_lag_leave
- mlxsw_sp_lag_dist_port_add
- mlxsw_sp_lag_dist_port_remove
- mlxsw_sp_port_lag_col_dist_enable
- mlxsw_sp_port_lag_col_dist_disable
- mlxsw_sp_port_lag_changed
- mlxsw_sp_port_stp_set
- mlxsw_sp_port_ovs_join
- mlxsw_sp_port_ovs_leave
- mlxsw_sp_bridge_has_multiple_vxlans
- mlxsw_sp_bridge_vxlan_vlan_is_valid
- mlxsw_sp_bridge_vxlan_is_valid
- mlxsw_sp_netdevice_port_upper_event
- mlxsw_sp_netdevice_port_lower_event
- mlxsw_sp_netdevice_port_event
- mlxsw_sp_netdevice_lag_event
- mlxsw_sp_netdevice_port_vlan_event
- mlxsw_sp_netdevice_lag_port_vlan_event
- mlxsw_sp_netdevice_bridge_vlan_event
- mlxsw_sp_netdevice_vlan_event
- mlxsw_sp_netdevice_bridge_event
- mlxsw_sp_netdevice_macvlan_event
- mlxsw_sp_is_vrf_event
- mlxsw_sp_netdevice_vxlan_event
- mlxsw_sp_netdevice_event
- mlxsw_sp_module_init
- mlxsw_sp_module_exit
1
2
3
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
7 #include <linux/pci.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/ethtool.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/if_bridge.h>
16 #include <linux/workqueue.h>
17 #include <linux/jiffies.h>
18 #include <linux/bitops.h>
19 #include <linux/list.h>
20 #include <linux/notifier.h>
21 #include <linux/dcbnl.h>
22 #include <linux/inetdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/jhash.h>
25 #include <net/switchdev.h>
26 #include <net/pkt_cls.h>
27 #include <net/tc_act/tc_mirred.h>
28 #include <net/netevent.h>
29 #include <net/tc_act/tc_sample.h>
30 #include <net/addrconf.h>
31
32 #include "spectrum.h"
33 #include "pci.h"
34 #include "core.h"
35 #include "core_env.h"
36 #include "reg.h"
37 #include "port.h"
38 #include "trap.h"
39 #include "txheader.h"
40 #include "spectrum_cnt.h"
41 #include "spectrum_dpipe.h"
42 #include "spectrum_acl_flex_actions.h"
43 #include "spectrum_span.h"
44 #include "spectrum_ptp.h"
45 #include "../mlxfw/mlxfw.h"
46
47 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
48
49 #define MLXSW_SP1_FWREV_MAJOR 13
50 #define MLXSW_SP1_FWREV_MINOR 2000
51 #define MLXSW_SP1_FWREV_SUBMINOR 1886
52 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
53
54 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
55 .major = MLXSW_SP1_FWREV_MAJOR,
56 .minor = MLXSW_SP1_FWREV_MINOR,
57 .subminor = MLXSW_SP1_FWREV_SUBMINOR,
58 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
59 };
60
61 #define MLXSW_SP1_FW_FILENAME \
62 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
63 "." __stringify(MLXSW_SP1_FWREV_MINOR) \
64 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
65
66 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
67 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
68 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3";
69 static const char mlxsw_sp_driver_version[] = "1.0";
70
71 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
72 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
73 };
74 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
75 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
76 };
77
78
79
80
81
82 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
83
84
85
86
87
88
89 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
90
91
92
93
94 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
95
96
97
98
99 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
100
101
102
103
104
105 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
106
107
108
109
110 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
111
112
113
114
115
116 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
117
118
119
120
121 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
122
123
124
125
126
127
128
129
130
131 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
132
133
134
135
136
137
138 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
139
140
141
142
143
144 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
145
146 struct mlxsw_sp_mlxfw_dev {
147 struct mlxfw_dev mlxfw_dev;
148 struct mlxsw_sp *mlxsw_sp;
149 };
150
151 struct mlxsw_sp_ptp_ops {
152 struct mlxsw_sp_ptp_clock *
153 (*clock_init)(struct mlxsw_sp *mlxsw_sp, struct device *dev);
154 void (*clock_fini)(struct mlxsw_sp_ptp_clock *clock);
155
156 struct mlxsw_sp_ptp_state *(*init)(struct mlxsw_sp *mlxsw_sp);
157 void (*fini)(struct mlxsw_sp_ptp_state *ptp_state);
158
159
160
161
162 void (*receive)(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
163 u8 local_port);
164
165
166
167
168 void (*transmitted)(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
169 u8 local_port);
170
171 int (*hwtstamp_get)(struct mlxsw_sp_port *mlxsw_sp_port,
172 struct hwtstamp_config *config);
173 int (*hwtstamp_set)(struct mlxsw_sp_port *mlxsw_sp_port,
174 struct hwtstamp_config *config);
175 void (*shaper_work)(struct work_struct *work);
176 int (*get_ts_info)(struct mlxsw_sp *mlxsw_sp,
177 struct ethtool_ts_info *info);
178 int (*get_stats_count)(void);
179 void (*get_stats_strings)(u8 **p);
180 void (*get_stats)(struct mlxsw_sp_port *mlxsw_sp_port,
181 u64 *data, int data_index);
182 };
183
184 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
185 u16 component_index, u32 *p_max_size,
186 u8 *p_align_bits, u16 *p_max_write_size)
187 {
188 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
189 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
190 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
191 char mcqi_pl[MLXSW_REG_MCQI_LEN];
192 int err;
193
194 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
195 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
196 if (err)
197 return err;
198 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
199 p_max_write_size);
200
201 *p_align_bits = max_t(u8, *p_align_bits, 2);
202 *p_max_write_size = min_t(u16, *p_max_write_size,
203 MLXSW_REG_MCDA_MAX_DATA_LEN);
204 return 0;
205 }
206
207 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
208 {
209 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
210 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
211 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
212 char mcc_pl[MLXSW_REG_MCC_LEN];
213 u8 control_state;
214 int err;
215
216 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
217 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
218 if (err)
219 return err;
220
221 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
222 if (control_state != MLXFW_FSM_STATE_IDLE)
223 return -EBUSY;
224
225 mlxsw_reg_mcc_pack(mcc_pl,
226 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
227 0, *fwhandle, 0);
228 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
229 }
230
231 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
232 u32 fwhandle, u16 component_index,
233 u32 component_size)
234 {
235 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
236 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
237 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
238 char mcc_pl[MLXSW_REG_MCC_LEN];
239
240 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
241 component_index, fwhandle, component_size);
242 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
243 }
244
245 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
246 u32 fwhandle, u8 *data, u16 size,
247 u32 offset)
248 {
249 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
250 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
251 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
252 char mcda_pl[MLXSW_REG_MCDA_LEN];
253
254 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
255 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
256 }
257
258 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
259 u32 fwhandle, u16 component_index)
260 {
261 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
262 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
263 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
264 char mcc_pl[MLXSW_REG_MCC_LEN];
265
266 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
267 component_index, fwhandle, 0);
268 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
269 }
270
271 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
272 {
273 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
274 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
275 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
276 char mcc_pl[MLXSW_REG_MCC_LEN];
277
278 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
279 fwhandle, 0);
280 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
281 }
282
283 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
284 enum mlxfw_fsm_state *fsm_state,
285 enum mlxfw_fsm_state_err *fsm_state_err)
286 {
287 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
288 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
289 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
290 char mcc_pl[MLXSW_REG_MCC_LEN];
291 u8 control_state;
292 u8 error_code;
293 int err;
294
295 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
296 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
297 if (err)
298 return err;
299
300 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
301 *fsm_state = control_state;
302 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
303 MLXFW_FSM_STATE_ERR_MAX);
304 return 0;
305 }
306
307 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
308 {
309 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
310 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
311 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
312 char mcc_pl[MLXSW_REG_MCC_LEN];
313
314 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
315 fwhandle, 0);
316 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
317 }
318
319 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
320 {
321 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
322 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
323 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
324 char mcc_pl[MLXSW_REG_MCC_LEN];
325
326 mlxsw_reg_mcc_pack(mcc_pl,
327 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
328 fwhandle, 0);
329 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
330 }
331
332 static void mlxsw_sp_status_notify(struct mlxfw_dev *mlxfw_dev,
333 const char *msg, const char *comp_name,
334 u32 done_bytes, u32 total_bytes)
335 {
336 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
337 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
338 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
339
340 devlink_flash_update_status_notify(priv_to_devlink(mlxsw_sp->core),
341 msg, comp_name,
342 done_bytes, total_bytes);
343 }
344
345 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
346 .component_query = mlxsw_sp_component_query,
347 .fsm_lock = mlxsw_sp_fsm_lock,
348 .fsm_component_update = mlxsw_sp_fsm_component_update,
349 .fsm_block_download = mlxsw_sp_fsm_block_download,
350 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
351 .fsm_activate = mlxsw_sp_fsm_activate,
352 .fsm_query_state = mlxsw_sp_fsm_query_state,
353 .fsm_cancel = mlxsw_sp_fsm_cancel,
354 .fsm_release = mlxsw_sp_fsm_release,
355 .status_notify = mlxsw_sp_status_notify,
356 };
357
358 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
359 const struct firmware *firmware,
360 struct netlink_ext_ack *extack)
361 {
362 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
363 .mlxfw_dev = {
364 .ops = &mlxsw_sp_mlxfw_dev_ops,
365 .psid = mlxsw_sp->bus_info->psid,
366 .psid_size = strlen(mlxsw_sp->bus_info->psid),
367 },
368 .mlxsw_sp = mlxsw_sp
369 };
370 int err;
371
372 mlxsw_core_fw_flash_start(mlxsw_sp->core);
373 devlink_flash_update_begin_notify(priv_to_devlink(mlxsw_sp->core));
374 err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev,
375 firmware, extack);
376 devlink_flash_update_end_notify(priv_to_devlink(mlxsw_sp->core));
377 mlxsw_core_fw_flash_end(mlxsw_sp->core);
378
379 return err;
380 }
381
382 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
383 {
384 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
385 const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
386 const char *fw_filename = mlxsw_sp->fw_filename;
387 union devlink_param_value value;
388 const struct firmware *firmware;
389 int err;
390
391
392 if (!req_rev || !fw_filename)
393 return 0;
394
395
396 err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_sp->core),
397 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
398 &value);
399 if (err)
400 return err;
401 if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)
402 return 0;
403
404
405 if (rev->major != req_rev->major) {
406 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
407 rev->major, req_rev->major);
408 return -EINVAL;
409 }
410 if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
411 MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) &&
412 (rev->minor > req_rev->minor ||
413 (rev->minor == req_rev->minor &&
414 rev->subminor >= req_rev->subminor)))
415 return 0;
416
417 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
418 rev->major, rev->minor, rev->subminor);
419 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
420 fw_filename);
421
422 err = request_firmware_direct(&firmware, fw_filename,
423 mlxsw_sp->bus_info->dev);
424 if (err) {
425 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
426 fw_filename);
427 return err;
428 }
429
430 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware, NULL);
431 release_firmware(firmware);
432 if (err)
433 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
434
435
436
437
438 if (rev->minor >= req_rev->can_reset_minor)
439 return err ? err : -EAGAIN;
440 else
441 return 0;
442 }
443
444 static int mlxsw_sp_flash_update(struct mlxsw_core *mlxsw_core,
445 const char *file_name, const char *component,
446 struct netlink_ext_ack *extack)
447 {
448 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
449 const struct firmware *firmware;
450 int err;
451
452 if (component)
453 return -EOPNOTSUPP;
454
455 err = request_firmware_direct(&firmware, file_name,
456 mlxsw_sp->bus_info->dev);
457 if (err)
458 return err;
459 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware, extack);
460 release_firmware(firmware);
461
462 return err;
463 }
464
465 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
466 unsigned int counter_index, u64 *packets,
467 u64 *bytes)
468 {
469 char mgpc_pl[MLXSW_REG_MGPC_LEN];
470 int err;
471
472 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
473 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
474 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
475 if (err)
476 return err;
477 if (packets)
478 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
479 if (bytes)
480 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
481 return 0;
482 }
483
484 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
485 unsigned int counter_index)
486 {
487 char mgpc_pl[MLXSW_REG_MGPC_LEN];
488
489 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
490 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
491 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
492 }
493
494 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
495 unsigned int *p_counter_index)
496 {
497 int err;
498
499 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
500 p_counter_index);
501 if (err)
502 return err;
503 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
504 if (err)
505 goto err_counter_clear;
506 return 0;
507
508 err_counter_clear:
509 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
510 *p_counter_index);
511 return err;
512 }
513
514 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
515 unsigned int counter_index)
516 {
517 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
518 counter_index);
519 }
520
521 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
522 const struct mlxsw_tx_info *tx_info)
523 {
524 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
525
526 memset(txhdr, 0, MLXSW_TXHDR_LEN);
527
528 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
529 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
530 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
531 mlxsw_tx_hdr_swid_set(txhdr, 0);
532 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
533 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
534 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
535 }
536
537 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
538 {
539 switch (state) {
540 case BR_STATE_FORWARDING:
541 return MLXSW_REG_SPMS_STATE_FORWARDING;
542 case BR_STATE_LEARNING:
543 return MLXSW_REG_SPMS_STATE_LEARNING;
544 case BR_STATE_LISTENING:
545 case BR_STATE_DISABLED:
546 case BR_STATE_BLOCKING:
547 return MLXSW_REG_SPMS_STATE_DISCARDING;
548 default:
549 BUG();
550 }
551 }
552
553 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
554 u8 state)
555 {
556 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
558 char *spms_pl;
559 int err;
560
561 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
562 if (!spms_pl)
563 return -ENOMEM;
564 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
565 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
566
567 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
568 kfree(spms_pl);
569 return err;
570 }
571
572 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
573 {
574 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
575 int err;
576
577 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
578 if (err)
579 return err;
580 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
581 return 0;
582 }
583
584 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
585 bool enable, u32 rate)
586 {
587 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
588 char mpsc_pl[MLXSW_REG_MPSC_LEN];
589
590 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
591 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
592 }
593
594 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
595 bool is_up)
596 {
597 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
598 char paos_pl[MLXSW_REG_PAOS_LEN];
599
600 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
601 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
602 MLXSW_PORT_ADMIN_STATUS_DOWN);
603 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
604 }
605
606 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
607 unsigned char *addr)
608 {
609 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
610 char ppad_pl[MLXSW_REG_PPAD_LEN];
611
612 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
613 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
614 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
615 }
616
617 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
618 {
619 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
620 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
621
622 ether_addr_copy(addr, mlxsw_sp->base_mac);
623 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
624 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
625 }
626
627 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
628 {
629 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
630 char pmtu_pl[MLXSW_REG_PMTU_LEN];
631 int max_mtu;
632 int err;
633
634 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
635 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
636 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
637 if (err)
638 return err;
639 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
640
641 if (mtu > max_mtu)
642 return -EINVAL;
643
644 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
645 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
646 }
647
648 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
649 {
650 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
651 char pspa_pl[MLXSW_REG_PSPA_LEN];
652
653 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
654 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
655 }
656
657 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
658 {
659 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
660 char svpe_pl[MLXSW_REG_SVPE_LEN];
661
662 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
663 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
664 }
665
666 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
667 bool learn_enable)
668 {
669 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
670 char *spvmlr_pl;
671 int err;
672
673 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
674 if (!spvmlr_pl)
675 return -ENOMEM;
676 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
677 learn_enable);
678 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
679 kfree(spvmlr_pl);
680 return err;
681 }
682
683 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
684 u16 vid)
685 {
686 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
687 char spvid_pl[MLXSW_REG_SPVID_LEN];
688
689 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
690 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
691 }
692
693 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
694 bool allow)
695 {
696 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
697 char spaft_pl[MLXSW_REG_SPAFT_LEN];
698
699 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
700 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
701 }
702
703 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
704 {
705 int err;
706
707 if (!vid) {
708 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
709 if (err)
710 return err;
711 } else {
712 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
713 if (err)
714 return err;
715 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
716 if (err)
717 goto err_port_allow_untagged_set;
718 }
719
720 mlxsw_sp_port->pvid = vid;
721 return 0;
722
723 err_port_allow_untagged_set:
724 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
725 return err;
726 }
727
728 static int
729 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
730 {
731 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
732 char sspr_pl[MLXSW_REG_SSPR_LEN];
733
734 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
735 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
736 }
737
738 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
739 u8 local_port, u8 *p_module,
740 u8 *p_width, u8 *p_lane)
741 {
742 char pmlp_pl[MLXSW_REG_PMLP_LEN];
743 int err;
744
745 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
746 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
747 if (err)
748 return err;
749 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
750 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
751 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
752 return 0;
753 }
754
755 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
756 u8 module, u8 width, u8 lane)
757 {
758 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
759 char pmlp_pl[MLXSW_REG_PMLP_LEN];
760 int i;
761
762 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
763 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
764 for (i = 0; i < width; i++) {
765 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
766 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i);
767 }
768
769 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
770 }
771
772 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
773 {
774 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
775 char pmlp_pl[MLXSW_REG_PMLP_LEN];
776
777 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
778 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
779 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
780 }
781
782 static int mlxsw_sp_port_open(struct net_device *dev)
783 {
784 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
785 int err;
786
787 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
788 if (err)
789 return err;
790 netif_start_queue(dev);
791 return 0;
792 }
793
794 static int mlxsw_sp_port_stop(struct net_device *dev)
795 {
796 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
797
798 netif_stop_queue(dev);
799 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
800 }
801
802 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
803 struct net_device *dev)
804 {
805 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
806 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
807 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
808 const struct mlxsw_tx_info tx_info = {
809 .local_port = mlxsw_sp_port->local_port,
810 .is_emad = false,
811 };
812 u64 len;
813 int err;
814
815 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
816 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
817 dev_kfree_skb_any(skb);
818 return NETDEV_TX_OK;
819 }
820
821 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
822
823 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
824 return NETDEV_TX_BUSY;
825
826 if (eth_skb_pad(skb)) {
827 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
828 return NETDEV_TX_OK;
829 }
830
831 mlxsw_sp_txhdr_construct(skb, &tx_info);
832
833
834
835 len = skb->len - MLXSW_TXHDR_LEN;
836
837
838
839
840 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
841
842 if (!err) {
843 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
844 u64_stats_update_begin(&pcpu_stats->syncp);
845 pcpu_stats->tx_packets++;
846 pcpu_stats->tx_bytes += len;
847 u64_stats_update_end(&pcpu_stats->syncp);
848 } else {
849 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
850 dev_kfree_skb_any(skb);
851 }
852 return NETDEV_TX_OK;
853 }
854
855 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
856 {
857 }
858
859 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
860 {
861 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
862 struct sockaddr *addr = p;
863 int err;
864
865 if (!is_valid_ether_addr(addr->sa_data))
866 return -EADDRNOTAVAIL;
867
868 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
869 if (err)
870 return err;
871 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
872 return 0;
873 }
874
875 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
876 int mtu)
877 {
878 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
879 }
880
881 #define MLXSW_SP_CELL_FACTOR 2
882
883 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
884 u16 delay)
885 {
886 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
887 BITS_PER_BYTE));
888 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
889 mtu);
890 }
891
892
893
894
895 #define MLXSW_SP_PAUSE_DELAY 58752
896
897 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
898 u16 delay, bool pfc, bool pause)
899 {
900 if (pfc)
901 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
902 else if (pause)
903 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
904 else
905 return 0;
906 }
907
908 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
909 bool lossy)
910 {
911 if (lossy)
912 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
913 else
914 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
915 thres);
916 }
917
918 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
919 u8 *prio_tc, bool pause_en,
920 struct ieee_pfc *my_pfc)
921 {
922 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
923 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
924 u16 delay = !!my_pfc ? my_pfc->delay : 0;
925 char pbmc_pl[MLXSW_REG_PBMC_LEN];
926 u32 taken_headroom_cells = 0;
927 u32 max_headroom_cells;
928 int i, j, err;
929
930 max_headroom_cells = mlxsw_sp_sb_max_headroom_cells(mlxsw_sp);
931
932 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
933 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
934 if (err)
935 return err;
936
937 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
938 bool configure = false;
939 bool pfc = false;
940 u16 thres_cells;
941 u16 delay_cells;
942 u16 total_cells;
943 bool lossy;
944
945 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
946 if (prio_tc[j] == i) {
947 pfc = pfc_en & BIT(j);
948 configure = true;
949 break;
950 }
951 }
952
953 if (!configure)
954 continue;
955
956 lossy = !(pfc || pause_en);
957 thres_cells = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
958 delay_cells = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay,
959 pfc, pause_en);
960 total_cells = thres_cells + delay_cells;
961
962 taken_headroom_cells += total_cells;
963 if (taken_headroom_cells > max_headroom_cells)
964 return -ENOBUFS;
965
966 mlxsw_sp_pg_buf_pack(pbmc_pl, i, total_cells,
967 thres_cells, lossy);
968 }
969
970 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
971 }
972
973 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
974 int mtu, bool pause_en)
975 {
976 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
977 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
978 struct ieee_pfc *my_pfc;
979 u8 *prio_tc;
980
981 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
982 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
983
984 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
985 pause_en, my_pfc);
986 }
987
988 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
989 {
990 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
991 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
992 int err;
993
994 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
995 if (err)
996 return err;
997 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
998 if (err)
999 goto err_span_port_mtu_update;
1000 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1001 if (err)
1002 goto err_port_mtu_set;
1003 dev->mtu = mtu;
1004 return 0;
1005
1006 err_port_mtu_set:
1007 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1008 err_span_port_mtu_update:
1009 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1010 return err;
1011 }
1012
1013 static int
1014 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1015 struct rtnl_link_stats64 *stats)
1016 {
1017 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1018 struct mlxsw_sp_port_pcpu_stats *p;
1019 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1020 u32 tx_dropped = 0;
1021 unsigned int start;
1022 int i;
1023
1024 for_each_possible_cpu(i) {
1025 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1026 do {
1027 start = u64_stats_fetch_begin_irq(&p->syncp);
1028 rx_packets = p->rx_packets;
1029 rx_bytes = p->rx_bytes;
1030 tx_packets = p->tx_packets;
1031 tx_bytes = p->tx_bytes;
1032 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1033
1034 stats->rx_packets += rx_packets;
1035 stats->rx_bytes += rx_bytes;
1036 stats->tx_packets += tx_packets;
1037 stats->tx_bytes += tx_bytes;
1038
1039 tx_dropped += p->tx_dropped;
1040 }
1041 stats->tx_dropped = tx_dropped;
1042 return 0;
1043 }
1044
1045 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
1046 {
1047 switch (attr_id) {
1048 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1049 return true;
1050 }
1051
1052 return false;
1053 }
1054
1055 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1056 void *sp)
1057 {
1058 switch (attr_id) {
1059 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1060 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1061 }
1062
1063 return -EINVAL;
1064 }
1065
1066 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1067 int prio, char *ppcnt_pl)
1068 {
1069 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1070 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1071
1072 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1073 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1074 }
1075
1076 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1077 struct rtnl_link_stats64 *stats)
1078 {
1079 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1080 int err;
1081
1082 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1083 0, ppcnt_pl);
1084 if (err)
1085 goto out;
1086
1087 stats->tx_packets =
1088 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1089 stats->rx_packets =
1090 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1091 stats->tx_bytes =
1092 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1093 stats->rx_bytes =
1094 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1095 stats->multicast =
1096 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1097
1098 stats->rx_crc_errors =
1099 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1100 stats->rx_frame_errors =
1101 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1102
1103 stats->rx_length_errors = (
1104 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1105 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1106 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1107
1108 stats->rx_errors = (stats->rx_crc_errors +
1109 stats->rx_frame_errors + stats->rx_length_errors);
1110
1111 out:
1112 return err;
1113 }
1114
1115 static void
1116 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1117 struct mlxsw_sp_port_xstats *xstats)
1118 {
1119 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1120 int err, i;
1121
1122 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1123 ppcnt_pl);
1124 if (!err)
1125 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1126
1127 for (i = 0; i < TC_MAX_QUEUE; i++) {
1128 err = mlxsw_sp_port_get_stats_raw(dev,
1129 MLXSW_REG_PPCNT_TC_CONG_TC,
1130 i, ppcnt_pl);
1131 if (!err)
1132 xstats->wred_drop[i] =
1133 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1134
1135 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1136 i, ppcnt_pl);
1137 if (err)
1138 continue;
1139
1140 xstats->backlog[i] =
1141 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1142 xstats->tail_drop[i] =
1143 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1144 }
1145
1146 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1147 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1148 i, ppcnt_pl);
1149 if (err)
1150 continue;
1151
1152 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1153 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1154 }
1155 }
1156
1157 static void update_stats_cache(struct work_struct *work)
1158 {
1159 struct mlxsw_sp_port *mlxsw_sp_port =
1160 container_of(work, struct mlxsw_sp_port,
1161 periodic_hw_stats.update_dw.work);
1162
1163 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1164
1165
1166
1167 goto out;
1168
1169 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1170 &mlxsw_sp_port->periodic_hw_stats.stats);
1171 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1172 &mlxsw_sp_port->periodic_hw_stats.xstats);
1173
1174 out:
1175 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1176 MLXSW_HW_STATS_UPDATE_TIME);
1177 }
1178
1179
1180
1181
1182 static void
1183 mlxsw_sp_port_get_stats64(struct net_device *dev,
1184 struct rtnl_link_stats64 *stats)
1185 {
1186 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1187
1188 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1189 }
1190
1191 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1192 u16 vid_begin, u16 vid_end,
1193 bool is_member, bool untagged)
1194 {
1195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1196 char *spvm_pl;
1197 int err;
1198
1199 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1200 if (!spvm_pl)
1201 return -ENOMEM;
1202
1203 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1204 vid_end, is_member, untagged);
1205 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1206 kfree(spvm_pl);
1207 return err;
1208 }
1209
1210 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1211 u16 vid_end, bool is_member, bool untagged)
1212 {
1213 u16 vid, vid_e;
1214 int err;
1215
1216 for (vid = vid_begin; vid <= vid_end;
1217 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1218 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1219 vid_end);
1220
1221 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1222 is_member, untagged);
1223 if (err)
1224 return err;
1225 }
1226
1227 return 0;
1228 }
1229
1230 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
1231 bool flush_default)
1232 {
1233 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1234
1235 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1236 &mlxsw_sp_port->vlans_list, list) {
1237 if (!flush_default &&
1238 mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
1239 continue;
1240 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1241 }
1242 }
1243
1244 static void
1245 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1246 {
1247 if (mlxsw_sp_port_vlan->bridge_port)
1248 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1249 else if (mlxsw_sp_port_vlan->fid)
1250 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1251 }
1252
1253 struct mlxsw_sp_port_vlan *
1254 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1255 {
1256 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1257 bool untagged = vid == MLXSW_SP_DEFAULT_VID;
1258 int err;
1259
1260 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1261 if (mlxsw_sp_port_vlan)
1262 return ERR_PTR(-EEXIST);
1263
1264 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1265 if (err)
1266 return ERR_PTR(err);
1267
1268 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1269 if (!mlxsw_sp_port_vlan) {
1270 err = -ENOMEM;
1271 goto err_port_vlan_alloc;
1272 }
1273
1274 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1275 mlxsw_sp_port_vlan->vid = vid;
1276 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1277
1278 return mlxsw_sp_port_vlan;
1279
1280 err_port_vlan_alloc:
1281 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1282 return ERR_PTR(err);
1283 }
1284
1285 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1286 {
1287 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1288 u16 vid = mlxsw_sp_port_vlan->vid;
1289
1290 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
1291 list_del(&mlxsw_sp_port_vlan->list);
1292 kfree(mlxsw_sp_port_vlan);
1293 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1294 }
1295
1296 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1297 __be16 __always_unused proto, u16 vid)
1298 {
1299 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1300
1301
1302
1303
1304 if (!vid)
1305 return 0;
1306
1307 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
1308 }
1309
1310 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1311 __be16 __always_unused proto, u16 vid)
1312 {
1313 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1314 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1315
1316
1317
1318
1319 if (!vid)
1320 return 0;
1321
1322 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1323 if (!mlxsw_sp_port_vlan)
1324 return 0;
1325 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1326
1327 return 0;
1328 }
1329
1330 static struct mlxsw_sp_port_mall_tc_entry *
1331 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1332 unsigned long cookie) {
1333 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1334
1335 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1336 if (mall_tc_entry->cookie == cookie)
1337 return mall_tc_entry;
1338
1339 return NULL;
1340 }
1341
1342 static int
1343 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1344 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1345 const struct flow_action_entry *act,
1346 bool ingress)
1347 {
1348 enum mlxsw_sp_span_type span_type;
1349
1350 if (!act->dev) {
1351 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1352 return -EINVAL;
1353 }
1354
1355 mirror->ingress = ingress;
1356 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1357 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, act->dev, span_type,
1358 true, &mirror->span_id);
1359 }
1360
1361 static void
1362 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1363 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1364 {
1365 enum mlxsw_sp_span_type span_type;
1366
1367 span_type = mirror->ingress ?
1368 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1369 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1370 span_type, true);
1371 }
1372
1373 static int
1374 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1375 struct tc_cls_matchall_offload *cls,
1376 const struct flow_action_entry *act,
1377 bool ingress)
1378 {
1379 int err;
1380
1381 if (!mlxsw_sp_port->sample)
1382 return -EOPNOTSUPP;
1383 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1384 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1385 return -EEXIST;
1386 }
1387 if (act->sample.rate > MLXSW_REG_MPSC_RATE_MAX) {
1388 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1389 return -EOPNOTSUPP;
1390 }
1391
1392 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1393 act->sample.psample_group);
1394 mlxsw_sp_port->sample->truncate = act->sample.truncate;
1395 mlxsw_sp_port->sample->trunc_size = act->sample.trunc_size;
1396 mlxsw_sp_port->sample->rate = act->sample.rate;
1397
1398 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, act->sample.rate);
1399 if (err)
1400 goto err_port_sample_set;
1401 return 0;
1402
1403 err_port_sample_set:
1404 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1405 return err;
1406 }
1407
1408 static void
1409 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1410 {
1411 if (!mlxsw_sp_port->sample)
1412 return;
1413
1414 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1415 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1416 }
1417
1418 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1419 struct tc_cls_matchall_offload *f,
1420 bool ingress)
1421 {
1422 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1423 __be16 protocol = f->common.protocol;
1424 struct flow_action_entry *act;
1425 int err;
1426
1427 if (!flow_offload_has_one_action(&f->rule->action)) {
1428 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1429 return -EOPNOTSUPP;
1430 }
1431
1432 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1433 if (!mall_tc_entry)
1434 return -ENOMEM;
1435 mall_tc_entry->cookie = f->cookie;
1436
1437 act = &f->rule->action.entries[0];
1438
1439 if (act->id == FLOW_ACTION_MIRRED && protocol == htons(ETH_P_ALL)) {
1440 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1441
1442 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1443 mirror = &mall_tc_entry->mirror;
1444 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1445 mirror, act,
1446 ingress);
1447 } else if (act->id == FLOW_ACTION_SAMPLE &&
1448 protocol == htons(ETH_P_ALL)) {
1449 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1450 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1451 act, ingress);
1452 } else {
1453 err = -EOPNOTSUPP;
1454 }
1455
1456 if (err)
1457 goto err_add_action;
1458
1459 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1460 return 0;
1461
1462 err_add_action:
1463 kfree(mall_tc_entry);
1464 return err;
1465 }
1466
1467 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1468 struct tc_cls_matchall_offload *f)
1469 {
1470 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1471
1472 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1473 f->cookie);
1474 if (!mall_tc_entry) {
1475 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1476 return;
1477 }
1478 list_del(&mall_tc_entry->list);
1479
1480 switch (mall_tc_entry->type) {
1481 case MLXSW_SP_PORT_MALL_MIRROR:
1482 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1483 &mall_tc_entry->mirror);
1484 break;
1485 case MLXSW_SP_PORT_MALL_SAMPLE:
1486 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1487 break;
1488 default:
1489 WARN_ON(1);
1490 }
1491
1492 kfree(mall_tc_entry);
1493 }
1494
1495 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1496 struct tc_cls_matchall_offload *f,
1497 bool ingress)
1498 {
1499 switch (f->command) {
1500 case TC_CLSMATCHALL_REPLACE:
1501 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1502 ingress);
1503 case TC_CLSMATCHALL_DESTROY:
1504 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1505 return 0;
1506 default:
1507 return -EOPNOTSUPP;
1508 }
1509 }
1510
1511 static int
1512 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1513 struct flow_cls_offload *f)
1514 {
1515 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1516
1517 switch (f->command) {
1518 case FLOW_CLS_REPLACE:
1519 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1520 case FLOW_CLS_DESTROY:
1521 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1522 return 0;
1523 case FLOW_CLS_STATS:
1524 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1525 case FLOW_CLS_TMPLT_CREATE:
1526 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1527 case FLOW_CLS_TMPLT_DESTROY:
1528 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1529 return 0;
1530 default:
1531 return -EOPNOTSUPP;
1532 }
1533 }
1534
1535 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1536 void *type_data,
1537 void *cb_priv, bool ingress)
1538 {
1539 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1540
1541 switch (type) {
1542 case TC_SETUP_CLSMATCHALL:
1543 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1544 type_data))
1545 return -EOPNOTSUPP;
1546
1547 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1548 ingress);
1549 case TC_SETUP_CLSFLOWER:
1550 return 0;
1551 default:
1552 return -EOPNOTSUPP;
1553 }
1554 }
1555
1556 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1557 void *type_data,
1558 void *cb_priv)
1559 {
1560 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1561 cb_priv, true);
1562 }
1563
1564 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1565 void *type_data,
1566 void *cb_priv)
1567 {
1568 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1569 cb_priv, false);
1570 }
1571
1572 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1573 void *type_data, void *cb_priv)
1574 {
1575 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1576
1577 switch (type) {
1578 case TC_SETUP_CLSMATCHALL:
1579 return 0;
1580 case TC_SETUP_CLSFLOWER:
1581 if (mlxsw_sp_acl_block_disabled(acl_block))
1582 return -EOPNOTSUPP;
1583
1584 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1585 default:
1586 return -EOPNOTSUPP;
1587 }
1588 }
1589
1590 static void mlxsw_sp_tc_block_flower_release(void *cb_priv)
1591 {
1592 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1593
1594 mlxsw_sp_acl_block_destroy(acl_block);
1595 }
1596
1597 static LIST_HEAD(mlxsw_sp_block_cb_list);
1598
1599 static int
1600 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1601 struct flow_block_offload *f, bool ingress)
1602 {
1603 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1604 struct mlxsw_sp_acl_block *acl_block;
1605 struct flow_block_cb *block_cb;
1606 bool register_block = false;
1607 int err;
1608
1609 block_cb = flow_block_cb_lookup(f->block,
1610 mlxsw_sp_setup_tc_block_cb_flower,
1611 mlxsw_sp);
1612 if (!block_cb) {
1613 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, f->net);
1614 if (!acl_block)
1615 return -ENOMEM;
1616 block_cb = flow_block_cb_alloc(mlxsw_sp_setup_tc_block_cb_flower,
1617 mlxsw_sp, acl_block,
1618 mlxsw_sp_tc_block_flower_release);
1619 if (IS_ERR(block_cb)) {
1620 mlxsw_sp_acl_block_destroy(acl_block);
1621 err = PTR_ERR(block_cb);
1622 goto err_cb_register;
1623 }
1624 register_block = true;
1625 } else {
1626 acl_block = flow_block_cb_priv(block_cb);
1627 }
1628 flow_block_cb_incref(block_cb);
1629 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1630 mlxsw_sp_port, ingress, f->extack);
1631 if (err)
1632 goto err_block_bind;
1633
1634 if (ingress)
1635 mlxsw_sp_port->ing_acl_block = acl_block;
1636 else
1637 mlxsw_sp_port->eg_acl_block = acl_block;
1638
1639 if (register_block) {
1640 flow_block_cb_add(block_cb, f);
1641 list_add_tail(&block_cb->driver_list, &mlxsw_sp_block_cb_list);
1642 }
1643
1644 return 0;
1645
1646 err_block_bind:
1647 if (!flow_block_cb_decref(block_cb))
1648 flow_block_cb_free(block_cb);
1649 err_cb_register:
1650 return err;
1651 }
1652
1653 static void
1654 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1655 struct flow_block_offload *f, bool ingress)
1656 {
1657 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1658 struct mlxsw_sp_acl_block *acl_block;
1659 struct flow_block_cb *block_cb;
1660 int err;
1661
1662 block_cb = flow_block_cb_lookup(f->block,
1663 mlxsw_sp_setup_tc_block_cb_flower,
1664 mlxsw_sp);
1665 if (!block_cb)
1666 return;
1667
1668 if (ingress)
1669 mlxsw_sp_port->ing_acl_block = NULL;
1670 else
1671 mlxsw_sp_port->eg_acl_block = NULL;
1672
1673 acl_block = flow_block_cb_priv(block_cb);
1674 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1675 mlxsw_sp_port, ingress);
1676 if (!err && !flow_block_cb_decref(block_cb)) {
1677 flow_block_cb_remove(block_cb, f);
1678 list_del(&block_cb->driver_list);
1679 }
1680 }
1681
1682 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1683 struct flow_block_offload *f)
1684 {
1685 struct flow_block_cb *block_cb;
1686 flow_setup_cb_t *cb;
1687 bool ingress;
1688 int err;
1689
1690 if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1691 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1692 ingress = true;
1693 } else if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1694 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1695 ingress = false;
1696 } else {
1697 return -EOPNOTSUPP;
1698 }
1699
1700 f->driver_block_list = &mlxsw_sp_block_cb_list;
1701
1702 switch (f->command) {
1703 case FLOW_BLOCK_BIND:
1704 if (flow_block_cb_is_busy(cb, mlxsw_sp_port,
1705 &mlxsw_sp_block_cb_list))
1706 return -EBUSY;
1707
1708 block_cb = flow_block_cb_alloc(cb, mlxsw_sp_port,
1709 mlxsw_sp_port, NULL);
1710 if (IS_ERR(block_cb))
1711 return PTR_ERR(block_cb);
1712 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, f,
1713 ingress);
1714 if (err) {
1715 flow_block_cb_free(block_cb);
1716 return err;
1717 }
1718 flow_block_cb_add(block_cb, f);
1719 list_add_tail(&block_cb->driver_list, &mlxsw_sp_block_cb_list);
1720 return 0;
1721 case FLOW_BLOCK_UNBIND:
1722 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1723 f, ingress);
1724 block_cb = flow_block_cb_lookup(f->block, cb, mlxsw_sp_port);
1725 if (!block_cb)
1726 return -ENOENT;
1727
1728 flow_block_cb_remove(block_cb, f);
1729 list_del(&block_cb->driver_list);
1730 return 0;
1731 default:
1732 return -EOPNOTSUPP;
1733 }
1734 }
1735
1736 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1737 void *type_data)
1738 {
1739 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1740
1741 switch (type) {
1742 case TC_SETUP_BLOCK:
1743 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1744 case TC_SETUP_QDISC_RED:
1745 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1746 case TC_SETUP_QDISC_PRIO:
1747 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1748 default:
1749 return -EOPNOTSUPP;
1750 }
1751 }
1752
1753
1754 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1755 {
1756 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1757
1758 if (!enable) {
1759 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1760 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1761 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1762 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1763 return -EINVAL;
1764 }
1765 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1766 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1767 } else {
1768 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1769 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1770 }
1771 return 0;
1772 }
1773
1774 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable)
1775 {
1776 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1777 char pplr_pl[MLXSW_REG_PPLR_LEN];
1778 int err;
1779
1780 if (netif_running(dev))
1781 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1782
1783 mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable);
1784 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
1785 pplr_pl);
1786
1787 if (netif_running(dev))
1788 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1789
1790 return err;
1791 }
1792
1793 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1794
1795 static int mlxsw_sp_handle_feature(struct net_device *dev,
1796 netdev_features_t wanted_features,
1797 netdev_features_t feature,
1798 mlxsw_sp_feature_handler feature_handler)
1799 {
1800 netdev_features_t changes = wanted_features ^ dev->features;
1801 bool enable = !!(wanted_features & feature);
1802 int err;
1803
1804 if (!(changes & feature))
1805 return 0;
1806
1807 err = feature_handler(dev, enable);
1808 if (err) {
1809 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1810 enable ? "Enable" : "Disable", &feature, err);
1811 return err;
1812 }
1813
1814 if (enable)
1815 dev->features |= feature;
1816 else
1817 dev->features &= ~feature;
1818
1819 return 0;
1820 }
1821 static int mlxsw_sp_set_features(struct net_device *dev,
1822 netdev_features_t features)
1823 {
1824 netdev_features_t oper_features = dev->features;
1825 int err = 0;
1826
1827 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1828 mlxsw_sp_feature_hw_tc);
1829 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK,
1830 mlxsw_sp_feature_loopback);
1831
1832 if (err) {
1833 dev->features = oper_features;
1834 return -EINVAL;
1835 }
1836
1837 return 0;
1838 }
1839
1840 static struct devlink_port *
1841 mlxsw_sp_port_get_devlink_port(struct net_device *dev)
1842 {
1843 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1844 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1845
1846 return mlxsw_core_port_devlink_port_get(mlxsw_sp->core,
1847 mlxsw_sp_port->local_port);
1848 }
1849
1850 static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
1851 struct ifreq *ifr)
1852 {
1853 struct hwtstamp_config config;
1854 int err;
1855
1856 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1857 return -EFAULT;
1858
1859 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
1860 &config);
1861 if (err)
1862 return err;
1863
1864 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1865 return -EFAULT;
1866
1867 return 0;
1868 }
1869
1870 static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
1871 struct ifreq *ifr)
1872 {
1873 struct hwtstamp_config config;
1874 int err;
1875
1876 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
1877 &config);
1878 if (err)
1879 return err;
1880
1881 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1882 return -EFAULT;
1883
1884 return 0;
1885 }
1886
1887 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port)
1888 {
1889 struct hwtstamp_config config = {0};
1890
1891 mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config);
1892 }
1893
1894 static int
1895 mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1896 {
1897 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1898
1899 switch (cmd) {
1900 case SIOCSHWTSTAMP:
1901 return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr);
1902 case SIOCGHWTSTAMP:
1903 return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr);
1904 default:
1905 return -EOPNOTSUPP;
1906 }
1907 }
1908
1909 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1910 .ndo_open = mlxsw_sp_port_open,
1911 .ndo_stop = mlxsw_sp_port_stop,
1912 .ndo_start_xmit = mlxsw_sp_port_xmit,
1913 .ndo_setup_tc = mlxsw_sp_setup_tc,
1914 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
1915 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1916 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1917 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
1918 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1919 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
1920 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1921 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1922 .ndo_set_features = mlxsw_sp_set_features,
1923 .ndo_get_devlink_port = mlxsw_sp_port_get_devlink_port,
1924 .ndo_do_ioctl = mlxsw_sp_port_ioctl,
1925 };
1926
1927 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1928 struct ethtool_drvinfo *drvinfo)
1929 {
1930 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1931 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1932
1933 strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1934 sizeof(drvinfo->driver));
1935 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1936 sizeof(drvinfo->version));
1937 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1938 "%d.%d.%d",
1939 mlxsw_sp->bus_info->fw_rev.major,
1940 mlxsw_sp->bus_info->fw_rev.minor,
1941 mlxsw_sp->bus_info->fw_rev.subminor);
1942 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1943 sizeof(drvinfo->bus_info));
1944 }
1945
1946 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1947 struct ethtool_pauseparam *pause)
1948 {
1949 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1950
1951 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1952 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1953 }
1954
1955 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1956 struct ethtool_pauseparam *pause)
1957 {
1958 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1959
1960 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1961 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1962 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1963
1964 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1965 pfcc_pl);
1966 }
1967
1968 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1969 struct ethtool_pauseparam *pause)
1970 {
1971 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1972 bool pause_en = pause->tx_pause || pause->rx_pause;
1973 int err;
1974
1975 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1976 netdev_err(dev, "PFC already enabled on port\n");
1977 return -EINVAL;
1978 }
1979
1980 if (pause->autoneg) {
1981 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1982 return -EINVAL;
1983 }
1984
1985 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1986 if (err) {
1987 netdev_err(dev, "Failed to configure port's headroom\n");
1988 return err;
1989 }
1990
1991 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1992 if (err) {
1993 netdev_err(dev, "Failed to set PAUSE parameters\n");
1994 goto err_port_pause_configure;
1995 }
1996
1997 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1998 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1999
2000 return 0;
2001
2002 err_port_pause_configure:
2003 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
2004 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2005 return err;
2006 }
2007
2008 struct mlxsw_sp_port_hw_stats {
2009 char str[ETH_GSTRING_LEN];
2010 u64 (*getter)(const char *payload);
2011 bool cells_bytes;
2012 };
2013
2014 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
2015 {
2016 .str = "a_frames_transmitted_ok",
2017 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
2018 },
2019 {
2020 .str = "a_frames_received_ok",
2021 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
2022 },
2023 {
2024 .str = "a_frame_check_sequence_errors",
2025 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2026 },
2027 {
2028 .str = "a_alignment_errors",
2029 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2030 },
2031 {
2032 .str = "a_octets_transmitted_ok",
2033 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2034 },
2035 {
2036 .str = "a_octets_received_ok",
2037 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2038 },
2039 {
2040 .str = "a_multicast_frames_xmitted_ok",
2041 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2042 },
2043 {
2044 .str = "a_broadcast_frames_xmitted_ok",
2045 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2046 },
2047 {
2048 .str = "a_multicast_frames_received_ok",
2049 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2050 },
2051 {
2052 .str = "a_broadcast_frames_received_ok",
2053 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2054 },
2055 {
2056 .str = "a_in_range_length_errors",
2057 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2058 },
2059 {
2060 .str = "a_out_of_range_length_field",
2061 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2062 },
2063 {
2064 .str = "a_frame_too_long_errors",
2065 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2066 },
2067 {
2068 .str = "a_symbol_error_during_carrier",
2069 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2070 },
2071 {
2072 .str = "a_mac_control_frames_transmitted",
2073 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2074 },
2075 {
2076 .str = "a_mac_control_frames_received",
2077 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2078 },
2079 {
2080 .str = "a_unsupported_opcodes_received",
2081 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2082 },
2083 {
2084 .str = "a_pause_mac_ctrl_frames_received",
2085 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2086 },
2087 {
2088 .str = "a_pause_mac_ctrl_frames_xmitted",
2089 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2090 },
2091 };
2092
2093 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2094
2095 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2863_stats[] = {
2096 {
2097 .str = "if_in_discards",
2098 .getter = mlxsw_reg_ppcnt_if_in_discards_get,
2099 },
2100 {
2101 .str = "if_out_discards",
2102 .getter = mlxsw_reg_ppcnt_if_out_discards_get,
2103 },
2104 {
2105 .str = "if_out_errors",
2106 .getter = mlxsw_reg_ppcnt_if_out_errors_get,
2107 },
2108 };
2109
2110 #define MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN \
2111 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2863_stats)
2112
2113 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
2114 {
2115 .str = "ether_stats_undersize_pkts",
2116 .getter = mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get,
2117 },
2118 {
2119 .str = "ether_stats_oversize_pkts",
2120 .getter = mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get,
2121 },
2122 {
2123 .str = "ether_stats_fragments",
2124 .getter = mlxsw_reg_ppcnt_ether_stats_fragments_get,
2125 },
2126 {
2127 .str = "ether_pkts64octets",
2128 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
2129 },
2130 {
2131 .str = "ether_pkts65to127octets",
2132 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
2133 },
2134 {
2135 .str = "ether_pkts128to255octets",
2136 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
2137 },
2138 {
2139 .str = "ether_pkts256to511octets",
2140 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
2141 },
2142 {
2143 .str = "ether_pkts512to1023octets",
2144 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
2145 },
2146 {
2147 .str = "ether_pkts1024to1518octets",
2148 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
2149 },
2150 {
2151 .str = "ether_pkts1519to2047octets",
2152 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
2153 },
2154 {
2155 .str = "ether_pkts2048to4095octets",
2156 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
2157 },
2158 {
2159 .str = "ether_pkts4096to8191octets",
2160 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
2161 },
2162 {
2163 .str = "ether_pkts8192to10239octets",
2164 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
2165 },
2166 };
2167
2168 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
2169 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
2170
2171 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_3635_stats[] = {
2172 {
2173 .str = "dot3stats_fcs_errors",
2174 .getter = mlxsw_reg_ppcnt_dot3stats_fcs_errors_get,
2175 },
2176 {
2177 .str = "dot3stats_symbol_errors",
2178 .getter = mlxsw_reg_ppcnt_dot3stats_symbol_errors_get,
2179 },
2180 {
2181 .str = "dot3control_in_unknown_opcodes",
2182 .getter = mlxsw_reg_ppcnt_dot3control_in_unknown_opcodes_get,
2183 },
2184 {
2185 .str = "dot3in_pause_frames",
2186 .getter = mlxsw_reg_ppcnt_dot3in_pause_frames_get,
2187 },
2188 };
2189
2190 #define MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN \
2191 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_3635_stats)
2192
2193 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_discard_stats[] = {
2194 {
2195 .str = "discard_ingress_general",
2196 .getter = mlxsw_reg_ppcnt_ingress_general_get,
2197 },
2198 {
2199 .str = "discard_ingress_policy_engine",
2200 .getter = mlxsw_reg_ppcnt_ingress_policy_engine_get,
2201 },
2202 {
2203 .str = "discard_ingress_vlan_membership",
2204 .getter = mlxsw_reg_ppcnt_ingress_vlan_membership_get,
2205 },
2206 {
2207 .str = "discard_ingress_tag_frame_type",
2208 .getter = mlxsw_reg_ppcnt_ingress_tag_frame_type_get,
2209 },
2210 {
2211 .str = "discard_egress_vlan_membership",
2212 .getter = mlxsw_reg_ppcnt_egress_vlan_membership_get,
2213 },
2214 {
2215 .str = "discard_loopback_filter",
2216 .getter = mlxsw_reg_ppcnt_loopback_filter_get,
2217 },
2218 {
2219 .str = "discard_egress_general",
2220 .getter = mlxsw_reg_ppcnt_egress_general_get,
2221 },
2222 {
2223 .str = "discard_egress_hoq",
2224 .getter = mlxsw_reg_ppcnt_egress_hoq_get,
2225 },
2226 {
2227 .str = "discard_egress_policy_engine",
2228 .getter = mlxsw_reg_ppcnt_egress_policy_engine_get,
2229 },
2230 {
2231 .str = "discard_ingress_tx_link_down",
2232 .getter = mlxsw_reg_ppcnt_ingress_tx_link_down_get,
2233 },
2234 {
2235 .str = "discard_egress_stp_filter",
2236 .getter = mlxsw_reg_ppcnt_egress_stp_filter_get,
2237 },
2238 {
2239 .str = "discard_egress_sll",
2240 .getter = mlxsw_reg_ppcnt_egress_sll_get,
2241 },
2242 };
2243
2244 #define MLXSW_SP_PORT_HW_DISCARD_STATS_LEN \
2245 ARRAY_SIZE(mlxsw_sp_port_hw_discard_stats)
2246
2247 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2248 {
2249 .str = "rx_octets_prio",
2250 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2251 },
2252 {
2253 .str = "rx_frames_prio",
2254 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2255 },
2256 {
2257 .str = "tx_octets_prio",
2258 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2259 },
2260 {
2261 .str = "tx_frames_prio",
2262 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2263 },
2264 {
2265 .str = "rx_pause_prio",
2266 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2267 },
2268 {
2269 .str = "rx_pause_duration_prio",
2270 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2271 },
2272 {
2273 .str = "tx_pause_prio",
2274 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2275 },
2276 {
2277 .str = "tx_pause_duration_prio",
2278 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2279 },
2280 };
2281
2282 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2283
2284 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2285 {
2286 .str = "tc_transmit_queue_tc",
2287 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2288 .cells_bytes = true,
2289 },
2290 {
2291 .str = "tc_no_buffer_discard_uc_tc",
2292 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2293 },
2294 };
2295
2296 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2297
2298 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
2299 MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN + \
2300 MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
2301 MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN + \
2302 MLXSW_SP_PORT_HW_DISCARD_STATS_LEN + \
2303 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
2304 IEEE_8021QAZ_MAX_TCS) + \
2305 (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
2306 TC_MAX_QUEUE))
2307
2308 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2309 {
2310 int i;
2311
2312 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2313 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2314 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2315 *p += ETH_GSTRING_LEN;
2316 }
2317 }
2318
2319 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2320 {
2321 int i;
2322
2323 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2324 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2325 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2326 *p += ETH_GSTRING_LEN;
2327 }
2328 }
2329
2330 static void mlxsw_sp_port_get_strings(struct net_device *dev,
2331 u32 stringset, u8 *data)
2332 {
2333 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2334 u8 *p = data;
2335 int i;
2336
2337 switch (stringset) {
2338 case ETH_SS_STATS:
2339 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2340 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2341 ETH_GSTRING_LEN);
2342 p += ETH_GSTRING_LEN;
2343 }
2344
2345 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; i++) {
2346 memcpy(p, mlxsw_sp_port_hw_rfc_2863_stats[i].str,
2347 ETH_GSTRING_LEN);
2348 p += ETH_GSTRING_LEN;
2349 }
2350
2351 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2352 memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2353 ETH_GSTRING_LEN);
2354 p += ETH_GSTRING_LEN;
2355 }
2356
2357 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; i++) {
2358 memcpy(p, mlxsw_sp_port_hw_rfc_3635_stats[i].str,
2359 ETH_GSTRING_LEN);
2360 p += ETH_GSTRING_LEN;
2361 }
2362
2363 for (i = 0; i < MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; i++) {
2364 memcpy(p, mlxsw_sp_port_hw_discard_stats[i].str,
2365 ETH_GSTRING_LEN);
2366 p += ETH_GSTRING_LEN;
2367 }
2368
2369 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2370 mlxsw_sp_port_get_prio_strings(&p, i);
2371
2372 for (i = 0; i < TC_MAX_QUEUE; i++)
2373 mlxsw_sp_port_get_tc_strings(&p, i);
2374
2375 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_strings(&p);
2376 break;
2377 }
2378 }
2379
2380 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2381 enum ethtool_phys_id_state state)
2382 {
2383 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2384 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2385 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2386 bool active;
2387
2388 switch (state) {
2389 case ETHTOOL_ID_ACTIVE:
2390 active = true;
2391 break;
2392 case ETHTOOL_ID_INACTIVE:
2393 active = false;
2394 break;
2395 default:
2396 return -EOPNOTSUPP;
2397 }
2398
2399 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2400 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2401 }
2402
2403 static int
2404 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2405 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2406 {
2407 switch (grp) {
2408 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2409 *p_hw_stats = mlxsw_sp_port_hw_stats;
2410 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2411 break;
2412 case MLXSW_REG_PPCNT_RFC_2863_CNT:
2413 *p_hw_stats = mlxsw_sp_port_hw_rfc_2863_stats;
2414 *p_len = MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2415 break;
2416 case MLXSW_REG_PPCNT_RFC_2819_CNT:
2417 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2418 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2419 break;
2420 case MLXSW_REG_PPCNT_RFC_3635_CNT:
2421 *p_hw_stats = mlxsw_sp_port_hw_rfc_3635_stats;
2422 *p_len = MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2423 break;
2424 case MLXSW_REG_PPCNT_DISCARD_CNT:
2425 *p_hw_stats = mlxsw_sp_port_hw_discard_stats;
2426 *p_len = MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2427 break;
2428 case MLXSW_REG_PPCNT_PRIO_CNT:
2429 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2430 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2431 break;
2432 case MLXSW_REG_PPCNT_TC_CNT:
2433 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2434 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2435 break;
2436 default:
2437 WARN_ON(1);
2438 return -EOPNOTSUPP;
2439 }
2440 return 0;
2441 }
2442
2443 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2444 enum mlxsw_reg_ppcnt_grp grp, int prio,
2445 u64 *data, int data_index)
2446 {
2447 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2448 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2449 struct mlxsw_sp_port_hw_stats *hw_stats;
2450 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2451 int i, len;
2452 int err;
2453
2454 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2455 if (err)
2456 return;
2457 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2458 for (i = 0; i < len; i++) {
2459 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2460 if (!hw_stats[i].cells_bytes)
2461 continue;
2462 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2463 data[data_index + i]);
2464 }
2465 }
2466
2467 static void mlxsw_sp_port_get_stats(struct net_device *dev,
2468 struct ethtool_stats *stats, u64 *data)
2469 {
2470 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2471 int i, data_index = 0;
2472
2473
2474 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2475 data, data_index);
2476 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2477
2478
2479 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2863_CNT, 0,
2480 data, data_index);
2481 data_index += MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2482
2483
2484 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2485 data, data_index);
2486 data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2487
2488
2489 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_3635_CNT, 0,
2490 data, data_index);
2491 data_index += MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2492
2493
2494 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_DISCARD_CNT, 0,
2495 data, data_index);
2496 data_index += MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2497
2498
2499 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2500 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2501 data, data_index);
2502 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2503 }
2504
2505
2506 for (i = 0; i < TC_MAX_QUEUE; i++) {
2507 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2508 data, data_index);
2509 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2510 }
2511
2512
2513 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats(mlxsw_sp_port,
2514 data, data_index);
2515 data_index += mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
2516 }
2517
2518 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2519 {
2520 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2521
2522 switch (sset) {
2523 case ETH_SS_STATS:
2524 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN +
2525 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
2526 default:
2527 return -EOPNOTSUPP;
2528 }
2529 }
2530
2531 struct mlxsw_sp1_port_link_mode {
2532 enum ethtool_link_mode_bit_indices mask_ethtool;
2533 u32 mask;
2534 u32 speed;
2535 };
2536
2537 static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = {
2538 {
2539 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2540 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2541 .speed = SPEED_100,
2542 },
2543 {
2544 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2545 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2546 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2547 .speed = SPEED_1000,
2548 },
2549 {
2550 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2551 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2552 .speed = SPEED_10000,
2553 },
2554 {
2555 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2556 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2557 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2558 .speed = SPEED_10000,
2559 },
2560 {
2561 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2562 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2563 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2564 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2565 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2566 .speed = SPEED_10000,
2567 },
2568 {
2569 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2570 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2571 .speed = SPEED_20000,
2572 },
2573 {
2574 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2575 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2576 .speed = SPEED_40000,
2577 },
2578 {
2579 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2580 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2581 .speed = SPEED_40000,
2582 },
2583 {
2584 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2585 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2586 .speed = SPEED_40000,
2587 },
2588 {
2589 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2590 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2591 .speed = SPEED_40000,
2592 },
2593 {
2594 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2595 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2596 .speed = SPEED_25000,
2597 },
2598 {
2599 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2600 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2601 .speed = SPEED_25000,
2602 },
2603 {
2604 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2605 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2606 .speed = SPEED_25000,
2607 },
2608 {
2609 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2610 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2611 .speed = SPEED_50000,
2612 },
2613 {
2614 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2615 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2616 .speed = SPEED_50000,
2617 },
2618 {
2619 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2620 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2621 .speed = SPEED_50000,
2622 },
2623 {
2624 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2625 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2626 .speed = SPEED_100000,
2627 },
2628 {
2629 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2630 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2631 .speed = SPEED_100000,
2632 },
2633 {
2634 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2635 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2636 .speed = SPEED_100000,
2637 },
2638 {
2639 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2640 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2641 .speed = SPEED_100000,
2642 },
2643 };
2644
2645 #define MLXSW_SP1_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp1_port_link_mode)
2646
2647 static void
2648 mlxsw_sp1_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
2649 u32 ptys_eth_proto,
2650 struct ethtool_link_ksettings *cmd)
2651 {
2652 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2653 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2654 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2655 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2656 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2657 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2658 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2659
2660 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2661 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2662 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2663 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2664 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2665 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2666 }
2667
2668 static void
2669 mlxsw_sp1_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
2670 u8 width, unsigned long *mode)
2671 {
2672 int i;
2673
2674 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2675 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
2676 __set_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
2677 mode);
2678 }
2679 }
2680
2681 static u32
2682 mlxsw_sp1_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
2683 {
2684 int i;
2685
2686 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2687 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
2688 return mlxsw_sp1_port_link_mode[i].speed;
2689 }
2690
2691 return SPEED_UNKNOWN;
2692 }
2693
2694 static void
2695 mlxsw_sp1_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
2696 u32 ptys_eth_proto,
2697 struct ethtool_link_ksettings *cmd)
2698 {
2699 cmd->base.speed = SPEED_UNKNOWN;
2700 cmd->base.duplex = DUPLEX_UNKNOWN;
2701
2702 if (!carrier_ok)
2703 return;
2704
2705 cmd->base.speed = mlxsw_sp1_from_ptys_speed(mlxsw_sp, ptys_eth_proto);
2706 if (cmd->base.speed != SPEED_UNKNOWN)
2707 cmd->base.duplex = DUPLEX_FULL;
2708 }
2709
2710 static u32
2711 mlxsw_sp1_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, u8 width,
2712 const struct ethtool_link_ksettings *cmd)
2713 {
2714 u32 ptys_proto = 0;
2715 int i;
2716
2717 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2718 if (test_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
2719 cmd->link_modes.advertising))
2720 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2721 }
2722 return ptys_proto;
2723 }
2724
2725 static u32 mlxsw_sp1_to_ptys_speed(struct mlxsw_sp *mlxsw_sp, u8 width,
2726 u32 speed)
2727 {
2728 u32 ptys_proto = 0;
2729 int i;
2730
2731 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2732 if (speed == mlxsw_sp1_port_link_mode[i].speed)
2733 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2734 }
2735 return ptys_proto;
2736 }
2737
2738 static u32
2739 mlxsw_sp1_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed)
2740 {
2741 u32 ptys_proto = 0;
2742 int i;
2743
2744 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2745 if (mlxsw_sp1_port_link_mode[i].speed <= upper_speed)
2746 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2747 }
2748 return ptys_proto;
2749 }
2750
2751 static int
2752 mlxsw_sp1_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2753 u32 *base_speed)
2754 {
2755 *base_speed = MLXSW_SP_PORT_BASE_SPEED_25G;
2756 return 0;
2757 }
2758
2759 static void
2760 mlxsw_sp1_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
2761 u8 local_port, u32 proto_admin, bool autoneg)
2762 {
2763 mlxsw_reg_ptys_eth_pack(payload, local_port, proto_admin, autoneg);
2764 }
2765
2766 static void
2767 mlxsw_sp1_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
2768 u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
2769 u32 *p_eth_proto_oper)
2770 {
2771 mlxsw_reg_ptys_eth_unpack(payload, p_eth_proto_cap, p_eth_proto_admin,
2772 p_eth_proto_oper);
2773 }
2774
2775 static const struct mlxsw_sp_port_type_speed_ops
2776 mlxsw_sp1_port_type_speed_ops = {
2777 .from_ptys_supported_port = mlxsw_sp1_from_ptys_supported_port,
2778 .from_ptys_link = mlxsw_sp1_from_ptys_link,
2779 .from_ptys_speed = mlxsw_sp1_from_ptys_speed,
2780 .from_ptys_speed_duplex = mlxsw_sp1_from_ptys_speed_duplex,
2781 .to_ptys_advert_link = mlxsw_sp1_to_ptys_advert_link,
2782 .to_ptys_speed = mlxsw_sp1_to_ptys_speed,
2783 .to_ptys_upper_speed = mlxsw_sp1_to_ptys_upper_speed,
2784 .port_speed_base = mlxsw_sp1_port_speed_base,
2785 .reg_ptys_eth_pack = mlxsw_sp1_reg_ptys_eth_pack,
2786 .reg_ptys_eth_unpack = mlxsw_sp1_reg_ptys_eth_unpack,
2787 };
2788
2789 static const enum ethtool_link_mode_bit_indices
2790 mlxsw_sp2_mask_ethtool_sgmii_100m[] = {
2791 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2792 };
2793
2794 #define MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN \
2795 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_sgmii_100m)
2796
2797 static const enum ethtool_link_mode_bit_indices
2798 mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] = {
2799 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2800 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2801 };
2802
2803 #define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \
2804 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii)
2805
2806 static const enum ethtool_link_mode_bit_indices
2807 mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii[] = {
2808 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
2809 };
2810
2811 #define MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN \
2812 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii)
2813
2814 static const enum ethtool_link_mode_bit_indices
2815 mlxsw_sp2_mask_ethtool_5gbase_r[] = {
2816 ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
2817 };
2818
2819 #define MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN \
2820 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_5gbase_r)
2821
2822 static const enum ethtool_link_mode_bit_indices
2823 mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g[] = {
2824 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2825 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2826 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
2827 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
2828 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
2829 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
2830 ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
2831 };
2832
2833 #define MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN \
2834 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g)
2835
2836 static const enum ethtool_link_mode_bit_indices
2837 mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g[] = {
2838 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2839 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2840 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2841 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2842 };
2843
2844 #define MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN \
2845 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g)
2846
2847 static const enum ethtool_link_mode_bit_indices
2848 mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr[] = {
2849 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2850 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2851 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2852 };
2853
2854 #define MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN \
2855 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr)
2856
2857 static const enum ethtool_link_mode_bit_indices
2858 mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2[] = {
2859 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2860 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2861 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2862 };
2863
2864 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN \
2865 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2)
2866
2867 static const enum ethtool_link_mode_bit_indices
2868 mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr[] = {
2869 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
2870 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
2871 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
2872 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
2873 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
2874 };
2875
2876 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN \
2877 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr)
2878
2879 static const enum ethtool_link_mode_bit_indices
2880 mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4[] = {
2881 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2882 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2883 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2884 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2885 };
2886
2887 #define MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN \
2888 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4)
2889
2890 static const enum ethtool_link_mode_bit_indices
2891 mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2[] = {
2892 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
2893 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
2894 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
2895 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
2896 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
2897 };
2898
2899 #define MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN \
2900 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2)
2901
2902 static const enum ethtool_link_mode_bit_indices
2903 mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = {
2904 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
2905 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
2906 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
2907 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
2908 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
2909 };
2910
2911 #define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \
2912 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4)
2913
2914 #define MLXSW_SP_PORT_MASK_WIDTH_1X BIT(0)
2915 #define MLXSW_SP_PORT_MASK_WIDTH_2X BIT(1)
2916 #define MLXSW_SP_PORT_MASK_WIDTH_4X BIT(2)
2917
2918 static u8 mlxsw_sp_port_mask_width_get(u8 width)
2919 {
2920 switch (width) {
2921 case 1:
2922 return MLXSW_SP_PORT_MASK_WIDTH_1X;
2923 case 2:
2924 return MLXSW_SP_PORT_MASK_WIDTH_2X;
2925 case 4:
2926 return MLXSW_SP_PORT_MASK_WIDTH_4X;
2927 default:
2928 WARN_ON_ONCE(1);
2929 return 0;
2930 }
2931 }
2932
2933 struct mlxsw_sp2_port_link_mode {
2934 const enum ethtool_link_mode_bit_indices *mask_ethtool;
2935 int m_ethtool_len;
2936 u32 mask;
2937 u32 speed;
2938 u8 mask_width;
2939 };
2940
2941 static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
2942 {
2943 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M,
2944 .mask_ethtool = mlxsw_sp2_mask_ethtool_sgmii_100m,
2945 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN,
2946 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
2947 MLXSW_SP_PORT_MASK_WIDTH_2X |
2948 MLXSW_SP_PORT_MASK_WIDTH_4X,
2949 .speed = SPEED_100,
2950 },
2951 {
2952 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII,
2953 .mask_ethtool = mlxsw_sp2_mask_ethtool_1000base_x_sgmii,
2954 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN,
2955 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
2956 MLXSW_SP_PORT_MASK_WIDTH_2X |
2957 MLXSW_SP_PORT_MASK_WIDTH_4X,
2958 .speed = SPEED_1000,
2959 },
2960 {
2961 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII,
2962 .mask_ethtool = mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii,
2963 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN,
2964 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
2965 MLXSW_SP_PORT_MASK_WIDTH_2X |
2966 MLXSW_SP_PORT_MASK_WIDTH_4X,
2967 .speed = SPEED_2500,
2968 },
2969 {
2970 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R,
2971 .mask_ethtool = mlxsw_sp2_mask_ethtool_5gbase_r,
2972 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN,
2973 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
2974 MLXSW_SP_PORT_MASK_WIDTH_2X |
2975 MLXSW_SP_PORT_MASK_WIDTH_4X,
2976 .speed = SPEED_5000,
2977 },
2978 {
2979 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G,
2980 .mask_ethtool = mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g,
2981 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN,
2982 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
2983 MLXSW_SP_PORT_MASK_WIDTH_2X |
2984 MLXSW_SP_PORT_MASK_WIDTH_4X,
2985 .speed = SPEED_10000,
2986 },
2987 {
2988 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G,
2989 .mask_ethtool = mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g,
2990 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN,
2991 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_4X,
2992 .speed = SPEED_40000,
2993 },
2994 {
2995 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR,
2996 .mask_ethtool = mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr,
2997 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN,
2998 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
2999 MLXSW_SP_PORT_MASK_WIDTH_2X |
3000 MLXSW_SP_PORT_MASK_WIDTH_4X,
3001 .speed = SPEED_25000,
3002 },
3003 {
3004 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
3005 .mask_ethtool = mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2,
3006 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN,
3007 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_2X |
3008 MLXSW_SP_PORT_MASK_WIDTH_4X,
3009 .speed = SPEED_50000,
3010 },
3011 {
3012 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR,
3013 .mask_ethtool = mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr,
3014 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN,
3015 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X,
3016 .speed = SPEED_50000,
3017 },
3018 {
3019 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4,
3020 .mask_ethtool = mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4,
3021 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN,
3022 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_4X,
3023 .speed = SPEED_100000,
3024 },
3025 {
3026 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2,
3027 .mask_ethtool = mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2,
3028 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN,
3029 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_2X,
3030 .speed = SPEED_100000,
3031 },
3032 {
3033 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4,
3034 .mask_ethtool = mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4,
3035 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN,
3036 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_4X,
3037 .speed = SPEED_200000,
3038 },
3039 };
3040
3041 #define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)
3042
3043 static void
3044 mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
3045 u32 ptys_eth_proto,
3046 struct ethtool_link_ksettings *cmd)
3047 {
3048 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
3049 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
3050 }
3051
3052 static void
3053 mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
3054 unsigned long *mode)
3055 {
3056 int i;
3057
3058 for (i = 0; i < link_mode->m_ethtool_len; i++)
3059 __set_bit(link_mode->mask_ethtool[i], mode);
3060 }
3061
3062 static void
3063 mlxsw_sp2_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
3064 u8 width, unsigned long *mode)
3065 {
3066 u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3067 int i;
3068
3069 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3070 if ((ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) &&
3071 (mask_width & mlxsw_sp2_port_link_mode[i].mask_width))
3072 mlxsw_sp2_set_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
3073 mode);
3074 }
3075 }
3076
3077 static u32
3078 mlxsw_sp2_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
3079 {
3080 int i;
3081
3082 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3083 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask)
3084 return mlxsw_sp2_port_link_mode[i].speed;
3085 }
3086
3087 return SPEED_UNKNOWN;
3088 }
3089
3090 static void
3091 mlxsw_sp2_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
3092 u32 ptys_eth_proto,
3093 struct ethtool_link_ksettings *cmd)
3094 {
3095 cmd->base.speed = SPEED_UNKNOWN;
3096 cmd->base.duplex = DUPLEX_UNKNOWN;
3097
3098 if (!carrier_ok)
3099 return;
3100
3101 cmd->base.speed = mlxsw_sp2_from_ptys_speed(mlxsw_sp, ptys_eth_proto);
3102 if (cmd->base.speed != SPEED_UNKNOWN)
3103 cmd->base.duplex = DUPLEX_FULL;
3104 }
3105
3106 static bool
3107 mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
3108 const unsigned long *mode)
3109 {
3110 int cnt = 0;
3111 int i;
3112
3113 for (i = 0; i < link_mode->m_ethtool_len; i++) {
3114 if (test_bit(link_mode->mask_ethtool[i], mode))
3115 cnt++;
3116 }
3117
3118 return cnt == link_mode->m_ethtool_len;
3119 }
3120
3121 static u32
3122 mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, u8 width,
3123 const struct ethtool_link_ksettings *cmd)
3124 {
3125 u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3126 u32 ptys_proto = 0;
3127 int i;
3128
3129 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3130 if ((mask_width & mlxsw_sp2_port_link_mode[i].mask_width) &&
3131 mlxsw_sp2_test_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
3132 cmd->link_modes.advertising))
3133 ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3134 }
3135 return ptys_proto;
3136 }
3137
3138 static u32 mlxsw_sp2_to_ptys_speed(struct mlxsw_sp *mlxsw_sp,
3139 u8 width, u32 speed)
3140 {
3141 u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3142 u32 ptys_proto = 0;
3143 int i;
3144
3145 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3146 if ((speed == mlxsw_sp2_port_link_mode[i].speed) &&
3147 (mask_width & mlxsw_sp2_port_link_mode[i].mask_width))
3148 ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3149 }
3150 return ptys_proto;
3151 }
3152
3153 static u32
3154 mlxsw_sp2_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed)
3155 {
3156 u32 ptys_proto = 0;
3157 int i;
3158
3159 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3160 if (mlxsw_sp2_port_link_mode[i].speed <= upper_speed)
3161 ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3162 }
3163 return ptys_proto;
3164 }
3165
3166 static int
3167 mlxsw_sp2_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3168 u32 *base_speed)
3169 {
3170 char ptys_pl[MLXSW_REG_PTYS_LEN];
3171 u32 eth_proto_cap;
3172 int err;
3173
3174
3175
3176
3177 mlxsw_reg_ptys_ext_eth_pack(ptys_pl, local_port, 0, false);
3178 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3179 if (err)
3180 return err;
3181 mlxsw_reg_ptys_ext_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL);
3182
3183 if (eth_proto_cap &
3184 MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR) {
3185 *base_speed = MLXSW_SP_PORT_BASE_SPEED_50G;
3186 return 0;
3187 }
3188
3189 if (eth_proto_cap &
3190 MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR) {
3191 *base_speed = MLXSW_SP_PORT_BASE_SPEED_25G;
3192 return 0;
3193 }
3194
3195 return -EIO;
3196 }
3197
3198 static void
3199 mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
3200 u8 local_port, u32 proto_admin,
3201 bool autoneg)
3202 {
3203 mlxsw_reg_ptys_ext_eth_pack(payload, local_port, proto_admin, autoneg);
3204 }
3205
3206 static void
3207 mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
3208 u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
3209 u32 *p_eth_proto_oper)
3210 {
3211 mlxsw_reg_ptys_ext_eth_unpack(payload, p_eth_proto_cap,
3212 p_eth_proto_admin, p_eth_proto_oper);
3213 }
3214
3215 static const struct mlxsw_sp_port_type_speed_ops
3216 mlxsw_sp2_port_type_speed_ops = {
3217 .from_ptys_supported_port = mlxsw_sp2_from_ptys_supported_port,
3218 .from_ptys_link = mlxsw_sp2_from_ptys_link,
3219 .from_ptys_speed = mlxsw_sp2_from_ptys_speed,
3220 .from_ptys_speed_duplex = mlxsw_sp2_from_ptys_speed_duplex,
3221 .to_ptys_advert_link = mlxsw_sp2_to_ptys_advert_link,
3222 .to_ptys_speed = mlxsw_sp2_to_ptys_speed,
3223 .to_ptys_upper_speed = mlxsw_sp2_to_ptys_upper_speed,
3224 .port_speed_base = mlxsw_sp2_port_speed_base,
3225 .reg_ptys_eth_pack = mlxsw_sp2_reg_ptys_eth_pack,
3226 .reg_ptys_eth_unpack = mlxsw_sp2_reg_ptys_eth_unpack,
3227 };
3228
3229 static void
3230 mlxsw_sp_port_get_link_supported(struct mlxsw_sp *mlxsw_sp, u32 eth_proto_cap,
3231 u8 width, struct ethtool_link_ksettings *cmd)
3232 {
3233 const struct mlxsw_sp_port_type_speed_ops *ops;
3234
3235 ops = mlxsw_sp->port_type_speed_ops;
3236
3237 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
3238 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
3239 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
3240
3241 ops->from_ptys_supported_port(mlxsw_sp, eth_proto_cap, cmd);
3242 ops->from_ptys_link(mlxsw_sp, eth_proto_cap, width,
3243 cmd->link_modes.supported);
3244 }
3245
3246 static void
3247 mlxsw_sp_port_get_link_advertise(struct mlxsw_sp *mlxsw_sp,
3248 u32 eth_proto_admin, bool autoneg, u8 width,
3249 struct ethtool_link_ksettings *cmd)
3250 {
3251 const struct mlxsw_sp_port_type_speed_ops *ops;
3252
3253 ops = mlxsw_sp->port_type_speed_ops;
3254
3255 if (!autoneg)
3256 return;
3257
3258 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
3259 ops->from_ptys_link(mlxsw_sp, eth_proto_admin, width,
3260 cmd->link_modes.advertising);
3261 }
3262
3263 static u8
3264 mlxsw_sp_port_connector_port(enum mlxsw_reg_ptys_connector_type connector_type)
3265 {
3266 switch (connector_type) {
3267 case MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR:
3268 return PORT_OTHER;
3269 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE:
3270 return PORT_NONE;
3271 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP:
3272 return PORT_TP;
3273 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI:
3274 return PORT_AUI;
3275 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC:
3276 return PORT_BNC;
3277 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII:
3278 return PORT_MII;
3279 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE:
3280 return PORT_FIBRE;
3281 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA:
3282 return PORT_DA;
3283 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER:
3284 return PORT_OTHER;
3285 default:
3286 WARN_ON_ONCE(1);
3287 return PORT_OTHER;
3288 }
3289 }
3290
3291 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
3292 struct ethtool_link_ksettings *cmd)
3293 {
3294 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
3295 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3296 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3297 const struct mlxsw_sp_port_type_speed_ops *ops;
3298 char ptys_pl[MLXSW_REG_PTYS_LEN];
3299 u8 connector_type;
3300 bool autoneg;
3301 int err;
3302
3303 ops = mlxsw_sp->port_type_speed_ops;
3304
3305 autoneg = mlxsw_sp_port->link.autoneg;
3306 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3307 0, false);
3308 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3309 if (err)
3310 return err;
3311 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap,
3312 ð_proto_admin, ð_proto_oper);
3313
3314 mlxsw_sp_port_get_link_supported(mlxsw_sp, eth_proto_cap,
3315 mlxsw_sp_port->mapping.width, cmd);
3316
3317 mlxsw_sp_port_get_link_advertise(mlxsw_sp, eth_proto_admin, autoneg,
3318 mlxsw_sp_port->mapping.width, cmd);
3319
3320 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3321 connector_type = mlxsw_reg_ptys_connector_type_get(ptys_pl);
3322 cmd->base.port = mlxsw_sp_port_connector_port(connector_type);
3323 ops->from_ptys_speed_duplex(mlxsw_sp, netif_carrier_ok(dev),
3324 eth_proto_oper, cmd);
3325
3326 return 0;
3327 }
3328
3329 static int
3330 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
3331 const struct ethtool_link_ksettings *cmd)
3332 {
3333 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3334 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3335 const struct mlxsw_sp_port_type_speed_ops *ops;
3336 char ptys_pl[MLXSW_REG_PTYS_LEN];
3337 u32 eth_proto_cap, eth_proto_new;
3338 bool autoneg;
3339 int err;
3340
3341 ops = mlxsw_sp->port_type_speed_ops;
3342
3343 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3344 0, false);
3345 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3346 if (err)
3347 return err;
3348 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap, NULL, NULL);
3349
3350 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
3351 eth_proto_new = autoneg ?
3352 ops->to_ptys_advert_link(mlxsw_sp, mlxsw_sp_port->mapping.width,
3353 cmd) :
3354 ops->to_ptys_speed(mlxsw_sp, mlxsw_sp_port->mapping.width,
3355 cmd->base.speed);
3356
3357 eth_proto_new = eth_proto_new & eth_proto_cap;
3358 if (!eth_proto_new) {
3359 netdev_err(dev, "No supported speed requested\n");
3360 return -EINVAL;
3361 }
3362
3363 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3364 eth_proto_new, autoneg);
3365 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3366 if (err)
3367 return err;
3368
3369 mlxsw_sp_port->link.autoneg = autoneg;
3370
3371 if (!netif_running(dev))
3372 return 0;
3373
3374 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3375 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
3376
3377 return 0;
3378 }
3379
3380 static int mlxsw_sp_get_module_info(struct net_device *netdev,
3381 struct ethtool_modinfo *modinfo)
3382 {
3383 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3384 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3385 int err;
3386
3387 err = mlxsw_env_get_module_info(mlxsw_sp->core,
3388 mlxsw_sp_port->mapping.module,
3389 modinfo);
3390
3391 return err;
3392 }
3393
3394 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
3395 struct ethtool_eeprom *ee,
3396 u8 *data)
3397 {
3398 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3399 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3400 int err;
3401
3402 err = mlxsw_env_get_module_eeprom(netdev, mlxsw_sp->core,
3403 mlxsw_sp_port->mapping.module, ee,
3404 data);
3405
3406 return err;
3407 }
3408
3409 static int
3410 mlxsw_sp_get_ts_info(struct net_device *netdev, struct ethtool_ts_info *info)
3411 {
3412 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3413 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3414
3415 return mlxsw_sp->ptp_ops->get_ts_info(mlxsw_sp, info);
3416 }
3417
3418 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
3419 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
3420 .get_link = ethtool_op_get_link,
3421 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
3422 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
3423 .get_strings = mlxsw_sp_port_get_strings,
3424 .set_phys_id = mlxsw_sp_port_set_phys_id,
3425 .get_ethtool_stats = mlxsw_sp_port_get_stats,
3426 .get_sset_count = mlxsw_sp_port_get_sset_count,
3427 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
3428 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
3429 .get_module_info = mlxsw_sp_get_module_info,
3430 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
3431 .get_ts_info = mlxsw_sp_get_ts_info,
3432 };
3433
3434 static int
3435 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
3436 {
3437 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3438 const struct mlxsw_sp_port_type_speed_ops *ops;
3439 char ptys_pl[MLXSW_REG_PTYS_LEN];
3440 u32 eth_proto_admin;
3441 u32 upper_speed;
3442 u32 base_speed;
3443 int err;
3444
3445 ops = mlxsw_sp->port_type_speed_ops;
3446
3447 err = ops->port_speed_base(mlxsw_sp, mlxsw_sp_port->local_port,
3448 &base_speed);
3449 if (err)
3450 return err;
3451 upper_speed = base_speed * width;
3452
3453 eth_proto_admin = ops->to_ptys_upper_speed(mlxsw_sp, upper_speed);
3454 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3455 eth_proto_admin, mlxsw_sp_port->link.autoneg);
3456 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3457 }
3458
3459 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
3460 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
3461 bool dwrr, u8 dwrr_weight)
3462 {
3463 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3464 char qeec_pl[MLXSW_REG_QEEC_LEN];
3465
3466 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3467 next_index);
3468 mlxsw_reg_qeec_de_set(qeec_pl, true);
3469 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
3470 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
3471 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3472 }
3473
3474 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
3475 enum mlxsw_reg_qeec_hr hr, u8 index,
3476 u8 next_index, u32 maxrate)
3477 {
3478 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3479 char qeec_pl[MLXSW_REG_QEEC_LEN];
3480
3481 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3482 next_index);
3483 mlxsw_reg_qeec_mase_set(qeec_pl, true);
3484 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
3485 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3486 }
3487
3488 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
3489 enum mlxsw_reg_qeec_hr hr, u8 index,
3490 u8 next_index, u32 minrate)
3491 {
3492 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3493 char qeec_pl[MLXSW_REG_QEEC_LEN];
3494
3495 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3496 next_index);
3497 mlxsw_reg_qeec_mise_set(qeec_pl, true);
3498 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
3499
3500 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3501 }
3502
3503 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
3504 u8 switch_prio, u8 tclass)
3505 {
3506 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3507 char qtct_pl[MLXSW_REG_QTCT_LEN];
3508
3509 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
3510 tclass);
3511 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
3512 }
3513
3514 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
3515 {
3516 int err, i;
3517
3518
3519
3520
3521 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3522 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
3523 0);
3524 if (err)
3525 return err;
3526 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3527 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3528 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
3529 0, false, 0);
3530 if (err)
3531 return err;
3532 }
3533 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3534 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3535 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
3536 false, 0);
3537 if (err)
3538 return err;
3539
3540 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3541 MLXSW_REG_QEEC_HIERARCY_TC,
3542 i + 8, i,
3543 true, 100);
3544 if (err)
3545 return err;
3546 }
3547
3548
3549
3550
3551
3552 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3553 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
3554 MLXSW_REG_QEEC_MAS_DIS);
3555 if (err)
3556 return err;
3557 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3558 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3559 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3560 i, 0,
3561 MLXSW_REG_QEEC_MAS_DIS);
3562 if (err)
3563 return err;
3564 }
3565 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3566 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3567 MLXSW_REG_QEEC_HIERARCY_TC,
3568 i, i,
3569 MLXSW_REG_QEEC_MAS_DIS);
3570 if (err)
3571 return err;
3572
3573 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3574 MLXSW_REG_QEEC_HIERARCY_TC,
3575 i + 8, i,
3576 MLXSW_REG_QEEC_MAS_DIS);
3577 if (err)
3578 return err;
3579 }
3580
3581
3582 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3583 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
3584 MLXSW_REG_QEEC_HIERARCY_TC,
3585 i + 8, i,
3586 MLXSW_REG_QEEC_MIS_MIN);
3587 if (err)
3588 return err;
3589 }
3590
3591
3592 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3593 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
3594 if (err)
3595 return err;
3596 }
3597
3598 return 0;
3599 }
3600
3601 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
3602 bool enable)
3603 {
3604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3605 char qtctm_pl[MLXSW_REG_QTCTM_LEN];
3606
3607 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
3608 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
3609 }
3610
3611 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3612 bool split, u8 module, u8 width, u8 lane)
3613 {
3614 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
3615 struct mlxsw_sp_port *mlxsw_sp_port;
3616 struct net_device *dev;
3617 int err;
3618
3619 err = mlxsw_core_port_init(mlxsw_sp->core, local_port,
3620 module + 1, split, lane / width,
3621 mlxsw_sp->base_mac,
3622 sizeof(mlxsw_sp->base_mac));
3623 if (err) {
3624 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
3625 local_port);
3626 return err;
3627 }
3628
3629 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
3630 if (!dev) {
3631 err = -ENOMEM;
3632 goto err_alloc_etherdev;
3633 }
3634 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
3635 mlxsw_sp_port = netdev_priv(dev);
3636 mlxsw_sp_port->dev = dev;
3637 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3638 mlxsw_sp_port->local_port = local_port;
3639 mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
3640 mlxsw_sp_port->split = split;
3641 mlxsw_sp_port->mapping.module = module;
3642 mlxsw_sp_port->mapping.width = width;
3643 mlxsw_sp_port->mapping.lane = lane;
3644 mlxsw_sp_port->link.autoneg = 1;
3645 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
3646 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
3647
3648 mlxsw_sp_port->pcpu_stats =
3649 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
3650 if (!mlxsw_sp_port->pcpu_stats) {
3651 err = -ENOMEM;
3652 goto err_alloc_stats;
3653 }
3654
3655 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
3656 GFP_KERNEL);
3657 if (!mlxsw_sp_port->sample) {
3658 err = -ENOMEM;
3659 goto err_alloc_sample;
3660 }
3661
3662 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
3663 &update_stats_cache);
3664
3665 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
3666 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3667
3668 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
3669 if (err) {
3670 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3671 mlxsw_sp_port->local_port);
3672 goto err_port_module_map;
3673 }
3674
3675 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3676 if (err) {
3677 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3678 mlxsw_sp_port->local_port);
3679 goto err_port_swid_set;
3680 }
3681
3682 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3683 if (err) {
3684 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3685 mlxsw_sp_port->local_port);
3686 goto err_dev_addr_init;
3687 }
3688
3689 netif_carrier_off(dev);
3690
3691 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
3692 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3693 dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK;
3694
3695 dev->min_mtu = 0;
3696 dev->max_mtu = ETH_MAX_MTU;
3697
3698
3699
3700
3701 dev->needed_headroom = MLXSW_TXHDR_LEN;
3702
3703 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3704 if (err) {
3705 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3706 mlxsw_sp_port->local_port);
3707 goto err_port_system_port_mapping_set;
3708 }
3709
3710 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3711 if (err) {
3712 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3713 mlxsw_sp_port->local_port);
3714 goto err_port_speed_by_width_set;
3715 }
3716
3717 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3718 if (err) {
3719 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3720 mlxsw_sp_port->local_port);
3721 goto err_port_mtu_set;
3722 }
3723
3724 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3725 if (err)
3726 goto err_port_admin_status_set;
3727
3728 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3729 if (err) {
3730 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3731 mlxsw_sp_port->local_port);
3732 goto err_port_buffers_init;
3733 }
3734
3735 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3736 if (err) {
3737 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3738 mlxsw_sp_port->local_port);
3739 goto err_port_ets_init;
3740 }
3741
3742 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
3743 if (err) {
3744 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
3745 mlxsw_sp_port->local_port);
3746 goto err_port_tc_mc_mode;
3747 }
3748
3749
3750 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3751 if (err) {
3752 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3753 mlxsw_sp_port->local_port);
3754 goto err_port_dcb_init;
3755 }
3756
3757 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
3758 if (err) {
3759 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
3760 mlxsw_sp_port->local_port);
3761 goto err_port_fids_init;
3762 }
3763
3764 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3765 if (err) {
3766 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3767 mlxsw_sp_port->local_port);
3768 goto err_port_qdiscs_init;
3769 }
3770
3771 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false,
3772 false);
3773 if (err) {
3774 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
3775 mlxsw_sp_port->local_port);
3776 goto err_port_vlan_clear;
3777 }
3778
3779 err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
3780 if (err) {
3781 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
3782 mlxsw_sp_port->local_port);
3783 goto err_port_nve_init;
3784 }
3785
3786 err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
3787 if (err) {
3788 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
3789 mlxsw_sp_port->local_port);
3790 goto err_port_pvid_set;
3791 }
3792
3793 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
3794 MLXSW_SP_DEFAULT_VID);
3795 if (IS_ERR(mlxsw_sp_port_vlan)) {
3796 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
3797 mlxsw_sp_port->local_port);
3798 err = PTR_ERR(mlxsw_sp_port_vlan);
3799 goto err_port_vlan_create;
3800 }
3801 mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
3802
3803 INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw,
3804 mlxsw_sp->ptp_ops->shaper_work);
3805
3806 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
3807 err = register_netdev(dev);
3808 if (err) {
3809 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3810 mlxsw_sp_port->local_port);
3811 goto err_register_netdev;
3812 }
3813
3814 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3815 mlxsw_sp_port, dev);
3816 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
3817 return 0;
3818
3819 err_register_netdev:
3820 mlxsw_sp->ports[local_port] = NULL;
3821 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
3822 err_port_vlan_create:
3823 err_port_pvid_set:
3824 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3825 err_port_nve_init:
3826 err_port_vlan_clear:
3827 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3828 err_port_qdiscs_init:
3829 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3830 err_port_fids_init:
3831 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3832 err_port_dcb_init:
3833 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3834 err_port_tc_mc_mode:
3835 err_port_ets_init:
3836 err_port_buffers_init:
3837 err_port_admin_status_set:
3838 err_port_mtu_set:
3839 err_port_speed_by_width_set:
3840 err_port_system_port_mapping_set:
3841 err_dev_addr_init:
3842 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3843 err_port_swid_set:
3844 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3845 err_port_module_map:
3846 kfree(mlxsw_sp_port->sample);
3847 err_alloc_sample:
3848 free_percpu(mlxsw_sp_port->pcpu_stats);
3849 err_alloc_stats:
3850 free_netdev(dev);
3851 err_alloc_etherdev:
3852 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3853 return err;
3854 }
3855
3856 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3857 {
3858 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3859
3860 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
3861 cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw);
3862 mlxsw_sp_port_ptp_clear(mlxsw_sp_port);
3863 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
3864 unregister_netdev(mlxsw_sp_port->dev);
3865 mlxsw_sp->ports[local_port] = NULL;
3866 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
3867 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3868 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3869 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3870 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3871 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3872 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3873 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3874 kfree(mlxsw_sp_port->sample);
3875 free_percpu(mlxsw_sp_port->pcpu_stats);
3876 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
3877 free_netdev(mlxsw_sp_port->dev);
3878 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3879 }
3880
3881 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
3882 {
3883 struct mlxsw_sp_port *mlxsw_sp_port;
3884 int err;
3885
3886 mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL);
3887 if (!mlxsw_sp_port)
3888 return -ENOMEM;
3889
3890 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3891 mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT;
3892
3893 err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
3894 mlxsw_sp_port,
3895 mlxsw_sp->base_mac,
3896 sizeof(mlxsw_sp->base_mac));
3897 if (err) {
3898 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
3899 goto err_core_cpu_port_init;
3900 }
3901
3902 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
3903 return 0;
3904
3905 err_core_cpu_port_init:
3906 kfree(mlxsw_sp_port);
3907 return err;
3908 }
3909
3910 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
3911 {
3912 struct mlxsw_sp_port *mlxsw_sp_port =
3913 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
3914
3915 mlxsw_core_cpu_port_fini(mlxsw_sp->core);
3916 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
3917 kfree(mlxsw_sp_port);
3918 }
3919
3920 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3921 {
3922 return mlxsw_sp->ports[local_port] != NULL;
3923 }
3924
3925 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3926 {
3927 int i;
3928
3929 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3930 if (mlxsw_sp_port_created(mlxsw_sp, i))
3931 mlxsw_sp_port_remove(mlxsw_sp, i);
3932 mlxsw_sp_cpu_port_remove(mlxsw_sp);
3933 kfree(mlxsw_sp->port_to_module);
3934 kfree(mlxsw_sp->ports);
3935 mlxsw_sp->ports = NULL;
3936 }
3937
3938 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3939 {
3940 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3941 u8 module, width, lane;
3942 size_t alloc_size;
3943 int i;
3944 int err;
3945
3946 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
3947 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3948 if (!mlxsw_sp->ports)
3949 return -ENOMEM;
3950
3951 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3952 GFP_KERNEL);
3953 if (!mlxsw_sp->port_to_module) {
3954 err = -ENOMEM;
3955 goto err_port_to_module_alloc;
3956 }
3957
3958 err = mlxsw_sp_cpu_port_create(mlxsw_sp);
3959 if (err)
3960 goto err_cpu_port_create;
3961
3962 for (i = 1; i < max_ports; i++) {
3963
3964 mlxsw_sp->port_to_module[i] = -1;
3965
3966 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
3967 &width, &lane);
3968 if (err)
3969 goto err_port_module_info_get;
3970 if (!width)
3971 continue;
3972 mlxsw_sp->port_to_module[i] = module;
3973 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3974 module, width, lane);
3975 if (err)
3976 goto err_port_create;
3977 }
3978 return 0;
3979
3980 err_port_create:
3981 err_port_module_info_get:
3982 for (i--; i >= 1; i--)
3983 if (mlxsw_sp_port_created(mlxsw_sp, i))
3984 mlxsw_sp_port_remove(mlxsw_sp, i);
3985 mlxsw_sp_cpu_port_remove(mlxsw_sp);
3986 err_cpu_port_create:
3987 kfree(mlxsw_sp->port_to_module);
3988 err_port_to_module_alloc:
3989 kfree(mlxsw_sp->ports);
3990 mlxsw_sp->ports = NULL;
3991 return err;
3992 }
3993
3994 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3995 {
3996 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3997
3998 return local_port - offset;
3999 }
4000
4001 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
4002 u8 module, unsigned int count, u8 offset)
4003 {
4004 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
4005 int err, i;
4006
4007 for (i = 0; i < count; i++) {
4008 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i * offset,
4009 true, module, width, i * width);
4010 if (err)
4011 goto err_port_create;
4012 }
4013
4014 return 0;
4015
4016 err_port_create:
4017 for (i--; i >= 0; i--)
4018 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4019 mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4020 return err;
4021 }
4022
4023 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
4024 u8 base_port, unsigned int count)
4025 {
4026 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
4027 int i;
4028
4029
4030
4031
4032 count = count / 2;
4033
4034 for (i = 0; i < count; i++) {
4035 local_port = base_port + i * 2;
4036 if (mlxsw_sp->port_to_module[local_port] < 0)
4037 continue;
4038 module = mlxsw_sp->port_to_module[local_port];
4039
4040 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
4041 width, 0);
4042 }
4043 }
4044
4045 static struct mlxsw_sp_port *
4046 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u8 local_port)
4047 {
4048 if (mlxsw_sp->ports && mlxsw_sp->ports[local_port])
4049 return mlxsw_sp->ports[local_port];
4050 return NULL;
4051 }
4052
4053 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
4054 unsigned int count,
4055 struct netlink_ext_ack *extack)
4056 {
4057 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4058 u8 local_ports_in_1x, local_ports_in_2x, offset;
4059 struct mlxsw_sp_port *mlxsw_sp_port;
4060 u8 module, cur_width, base_port;
4061 int i;
4062 int err;
4063
4064 if (!MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_1X) ||
4065 !MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_2X))
4066 return -EIO;
4067
4068 local_ports_in_1x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_1X);
4069 local_ports_in_2x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_2X);
4070
4071 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
4072 if (!mlxsw_sp_port) {
4073 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
4074 local_port);
4075 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
4076 return -EINVAL;
4077 }
4078
4079 module = mlxsw_sp_port->mapping.module;
4080 cur_width = mlxsw_sp_port->mapping.width;
4081
4082 if (count != 2 && count != 4) {
4083 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
4084 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
4085 return -EINVAL;
4086 }
4087
4088 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
4089 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
4090 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
4091 return -EINVAL;
4092 }
4093
4094
4095 if (count == 2) {
4096 offset = local_ports_in_2x;
4097 base_port = local_port;
4098 if (mlxsw_sp->ports[base_port + local_ports_in_2x]) {
4099 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
4100 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
4101 return -EINVAL;
4102 }
4103 } else {
4104 offset = local_ports_in_1x;
4105 base_port = mlxsw_sp_cluster_base_port_get(local_port);
4106 if (mlxsw_sp->ports[base_port + 1] ||
4107 mlxsw_sp->ports[base_port + 3]) {
4108 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
4109 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
4110 return -EINVAL;
4111 }
4112 }
4113
4114 for (i = 0; i < count; i++)
4115 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4116 mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4117
4118 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count,
4119 offset);
4120 if (err) {
4121 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
4122 goto err_port_split_create;
4123 }
4124
4125 return 0;
4126
4127 err_port_split_create:
4128 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
4129 return err;
4130 }
4131
4132 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
4133 struct netlink_ext_ack *extack)
4134 {
4135 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4136 u8 local_ports_in_1x, local_ports_in_2x, offset;
4137 struct mlxsw_sp_port *mlxsw_sp_port;
4138 u8 cur_width, base_port;
4139 unsigned int count;
4140 int i;
4141
4142 if (!MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_1X) ||
4143 !MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_2X))
4144 return -EIO;
4145
4146 local_ports_in_1x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_1X);
4147 local_ports_in_2x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_2X);
4148
4149 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
4150 if (!mlxsw_sp_port) {
4151 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
4152 local_port);
4153 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
4154 return -EINVAL;
4155 }
4156
4157 if (!mlxsw_sp_port->split) {
4158 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
4159 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
4160 return -EINVAL;
4161 }
4162
4163 cur_width = mlxsw_sp_port->mapping.width;
4164 count = cur_width == 1 ? 4 : 2;
4165
4166 if (count == 2)
4167 offset = local_ports_in_2x;
4168 else
4169 offset = local_ports_in_1x;
4170
4171 base_port = mlxsw_sp_cluster_base_port_get(local_port);
4172
4173
4174 if (count == 2 && local_port >= base_port + 2)
4175 base_port = base_port + 2;
4176
4177 for (i = 0; i < count; i++)
4178 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4179 mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4180
4181 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
4182
4183 return 0;
4184 }
4185
4186 static void
4187 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port)
4188 {
4189 int i;
4190
4191 for (i = 0; i < TC_MAX_QUEUE; i++)
4192 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0;
4193 }
4194
4195 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
4196 char *pude_pl, void *priv)
4197 {
4198 struct mlxsw_sp *mlxsw_sp = priv;
4199 struct mlxsw_sp_port *mlxsw_sp_port;
4200 enum mlxsw_reg_pude_oper_status status;
4201 u8 local_port;
4202
4203 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
4204 mlxsw_sp_port = mlxsw_sp->ports[local_port];
4205 if (!mlxsw_sp_port)
4206 return;
4207
4208 status = mlxsw_reg_pude_oper_status_get(pude_pl);
4209 if (status == MLXSW_PORT_OPER_STATUS_UP) {
4210 netdev_info(mlxsw_sp_port->dev, "link up\n");
4211 netif_carrier_on(mlxsw_sp_port->dev);
4212 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0);
4213 } else {
4214 netdev_info(mlxsw_sp_port->dev, "link down\n");
4215 netif_carrier_off(mlxsw_sp_port->dev);
4216 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port);
4217 }
4218 }
4219
4220 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
4221 char *mtpptr_pl, bool ingress)
4222 {
4223 u8 local_port;
4224 u8 num_rec;
4225 int i;
4226
4227 local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl);
4228 num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl);
4229 for (i = 0; i < num_rec; i++) {
4230 u8 domain_number;
4231 u8 message_type;
4232 u16 sequence_id;
4233 u64 timestamp;
4234
4235 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type,
4236 &domain_number, &sequence_id,
4237 ×tamp);
4238 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
4239 message_type, domain_number,
4240 sequence_id, timestamp);
4241 }
4242 }
4243
4244 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg,
4245 char *mtpptr_pl, void *priv)
4246 {
4247 struct mlxsw_sp *mlxsw_sp = priv;
4248
4249 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
4250 }
4251
4252 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg,
4253 char *mtpptr_pl, void *priv)
4254 {
4255 struct mlxsw_sp *mlxsw_sp = priv;
4256
4257 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
4258 }
4259
4260 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
4261 u8 local_port, void *priv)
4262 {
4263 struct mlxsw_sp *mlxsw_sp = priv;
4264 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
4265 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
4266
4267 if (unlikely(!mlxsw_sp_port)) {
4268 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
4269 local_port);
4270 return;
4271 }
4272
4273 skb->dev = mlxsw_sp_port->dev;
4274
4275 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
4276 u64_stats_update_begin(&pcpu_stats->syncp);
4277 pcpu_stats->rx_packets++;
4278 pcpu_stats->rx_bytes += skb->len;
4279 u64_stats_update_end(&pcpu_stats->syncp);
4280
4281 skb->protocol = eth_type_trans(skb, skb->dev);
4282 netif_receive_skb(skb);
4283 }
4284
4285 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
4286 void *priv)
4287 {
4288 skb->offload_fwd_mark = 1;
4289 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
4290 }
4291
4292 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
4293 u8 local_port, void *priv)
4294 {
4295 skb->offload_l3_fwd_mark = 1;
4296 skb->offload_fwd_mark = 1;
4297 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
4298 }
4299
4300 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
4301 void *priv)
4302 {
4303 struct mlxsw_sp *mlxsw_sp = priv;
4304 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
4305 struct psample_group *psample_group;
4306 u32 size;
4307
4308 if (unlikely(!mlxsw_sp_port)) {
4309 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
4310 local_port);
4311 goto out;
4312 }
4313 if (unlikely(!mlxsw_sp_port->sample)) {
4314 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
4315 local_port);
4316 goto out;
4317 }
4318
4319 size = mlxsw_sp_port->sample->truncate ?
4320 mlxsw_sp_port->sample->trunc_size : skb->len;
4321
4322 rcu_read_lock();
4323 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
4324 if (!psample_group)
4325 goto out_unlock;
4326 psample_sample_packet(psample_group, skb, size,
4327 mlxsw_sp_port->dev->ifindex, 0,
4328 mlxsw_sp_port->sample->rate);
4329 out_unlock:
4330 rcu_read_unlock();
4331 out:
4332 consume_skb(skb);
4333 }
4334
4335 static void mlxsw_sp_rx_listener_ptp(struct sk_buff *skb, u8 local_port,
4336 void *priv)
4337 {
4338 struct mlxsw_sp *mlxsw_sp = priv;
4339
4340 mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
4341 }
4342
4343 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
4344 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
4345 _is_ctrl, SP_##_trap_group, DISCARD)
4346
4347 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
4348 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
4349 _is_ctrl, SP_##_trap_group, DISCARD)
4350
4351 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
4352 MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \
4353 _is_ctrl, SP_##_trap_group, DISCARD)
4354
4355 #define MLXSW_SP_EVENTL(_func, _trap_id) \
4356 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
4357
4358 static const struct mlxsw_listener mlxsw_sp_listener[] = {
4359
4360 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
4361
4362 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
4363 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
4364 MLXSW_RXL(mlxsw_sp_rx_listener_ptp, LLDP, TRAP_TO_CPU,
4365 false, SP_LLDP, DISCARD),
4366 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
4367 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
4368 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
4369 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
4370 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
4371 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
4372 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
4373 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
4374 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
4375 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
4376 false),
4377 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
4378 false),
4379 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
4380 false),
4381 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
4382 false),
4383
4384 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4385 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4386 MLXSW_SP_RXL_L3_MARK(LBERROR, MIRROR_TO_CPU, LBERROR, false),
4387 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
4388 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
4389 false),
4390 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
4391 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
4392 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
4393 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
4394 false),
4395 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
4396 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
4397 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
4398 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
4399 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
4400 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
4401 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
4402 false),
4403 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
4404 false),
4405 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
4406 false),
4407 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
4408 false),
4409 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
4410 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
4411 false),
4412 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
4413 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
4414 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
4415 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
4416 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4417 MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false),
4418 MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, VRRP, false),
4419 MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, VRRP, false),
4420
4421 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
4422 false, SP_IP2ME, DISCARD),
4423
4424 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
4425
4426 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
4427 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
4428 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
4429 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
4430 MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
4431
4432 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false),
4433 MLXSW_SP_RXL_NO_MARK(NVE_DECAP_ARP, TRAP_TO_CPU, ARP, false),
4434
4435 MLXSW_RXL(mlxsw_sp_rx_listener_ptp, PTP0, TRAP_TO_CPU,
4436 false, SP_PTP0, DISCARD),
4437 MLXSW_SP_RXL_NO_MARK(PTP1, TRAP_TO_CPU, PTP1, false),
4438 };
4439
4440 static const struct mlxsw_listener mlxsw_sp1_listener[] = {
4441
4442 MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0),
4443 MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0),
4444 };
4445
4446 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
4447 {
4448 char qpcr_pl[MLXSW_REG_QPCR_LEN];
4449 enum mlxsw_reg_qpcr_ir_units ir_units;
4450 int max_cpu_policers;
4451 bool is_bytes;
4452 u8 burst_size;
4453 u32 rate;
4454 int i, err;
4455
4456 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
4457 return -EIO;
4458
4459 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
4460
4461 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
4462 for (i = 0; i < max_cpu_policers; i++) {
4463 is_bytes = false;
4464 switch (i) {
4465 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
4466 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
4467 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
4468 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
4469 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
4470 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
4471 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
4472 rate = 128;
4473 burst_size = 7;
4474 break;
4475 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
4476 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
4477 rate = 16 * 1024;
4478 burst_size = 10;
4479 break;
4480 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
4481 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
4482 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
4483 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
4484 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
4485 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
4486 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
4487 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
4488 rate = 1024;
4489 burst_size = 7;
4490 break;
4491 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
4492 rate = 1024;
4493 burst_size = 7;
4494 break;
4495 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:
4496 rate = 24 * 1024;
4497 burst_size = 12;
4498 break;
4499 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:
4500 rate = 19 * 1024;
4501 burst_size = 12;
4502 break;
4503 case MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP:
4504 rate = 360;
4505 burst_size = 7;
4506 break;
4507 default:
4508 continue;
4509 }
4510
4511 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
4512 burst_size);
4513 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
4514 if (err)
4515 return err;
4516 }
4517
4518 return 0;
4519 }
4520
4521 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
4522 {
4523 char htgt_pl[MLXSW_REG_HTGT_LEN];
4524 enum mlxsw_reg_htgt_trap_group i;
4525 int max_cpu_policers;
4526 int max_trap_groups;
4527 u8 priority, tc;
4528 u16 policer_id;
4529 int err;
4530
4531 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
4532 return -EIO;
4533
4534 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
4535 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
4536
4537 for (i = 0; i < max_trap_groups; i++) {
4538 policer_id = i;
4539 switch (i) {
4540 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
4541 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
4542 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
4543 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
4544 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
4545 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:
4546 case MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP:
4547 priority = 5;
4548 tc = 5;
4549 break;
4550 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
4551 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
4552 priority = 4;
4553 tc = 4;
4554 break;
4555 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
4556 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
4557 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
4558 priority = 3;
4559 tc = 3;
4560 break;
4561 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
4562 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
4563 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
4564 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:
4565 priority = 2;
4566 tc = 2;
4567 break;
4568 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
4569 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
4570 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
4571 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
4572 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
4573 priority = 1;
4574 tc = 1;
4575 break;
4576 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
4577 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
4578 tc = MLXSW_REG_HTGT_DEFAULT_TC;
4579 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
4580 break;
4581 default:
4582 continue;
4583 }
4584
4585 if (max_cpu_policers <= policer_id &&
4586 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
4587 return -EIO;
4588
4589 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
4590 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
4591 if (err)
4592 return err;
4593 }
4594
4595 return 0;
4596 }
4597
4598 static int mlxsw_sp_traps_register(struct mlxsw_sp *mlxsw_sp,
4599 const struct mlxsw_listener listeners[],
4600 size_t listeners_count)
4601 {
4602 int i;
4603 int err;
4604
4605 for (i = 0; i < listeners_count; i++) {
4606 err = mlxsw_core_trap_register(mlxsw_sp->core,
4607 &listeners[i],
4608 mlxsw_sp);
4609 if (err)
4610 goto err_listener_register;
4611
4612 }
4613 return 0;
4614
4615 err_listener_register:
4616 for (i--; i >= 0; i--) {
4617 mlxsw_core_trap_unregister(mlxsw_sp->core,
4618 &listeners[i],
4619 mlxsw_sp);
4620 }
4621 return err;
4622 }
4623
4624 static void mlxsw_sp_traps_unregister(struct mlxsw_sp *mlxsw_sp,
4625 const struct mlxsw_listener listeners[],
4626 size_t listeners_count)
4627 {
4628 int i;
4629
4630 for (i = 0; i < listeners_count; i++) {
4631 mlxsw_core_trap_unregister(mlxsw_sp->core,
4632 &listeners[i],
4633 mlxsw_sp);
4634 }
4635 }
4636
4637 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
4638 {
4639 int err;
4640
4641 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
4642 if (err)
4643 return err;
4644
4645 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
4646 if (err)
4647 return err;
4648
4649 err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp_listener,
4650 ARRAY_SIZE(mlxsw_sp_listener));
4651 if (err)
4652 return err;
4653
4654 err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp->listeners,
4655 mlxsw_sp->listeners_count);
4656 if (err)
4657 goto err_extra_traps_init;
4658
4659 return 0;
4660
4661 err_extra_traps_init:
4662 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
4663 ARRAY_SIZE(mlxsw_sp_listener));
4664 return err;
4665 }
4666
4667 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
4668 {
4669 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp->listeners,
4670 mlxsw_sp->listeners_count);
4671 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
4672 ARRAY_SIZE(mlxsw_sp_listener));
4673 }
4674
4675 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe
4676
4677 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
4678 {
4679 char slcr_pl[MLXSW_REG_SLCR_LEN];
4680 u32 seed;
4681 int err;
4682
4683 seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
4684 MLXSW_SP_LAG_SEED_INIT);
4685 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
4686 MLXSW_REG_SLCR_LAG_HASH_DMAC |
4687 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
4688 MLXSW_REG_SLCR_LAG_HASH_VLANID |
4689 MLXSW_REG_SLCR_LAG_HASH_SIP |
4690 MLXSW_REG_SLCR_LAG_HASH_DIP |
4691 MLXSW_REG_SLCR_LAG_HASH_SPORT |
4692 MLXSW_REG_SLCR_LAG_HASH_DPORT |
4693 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
4694 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
4695 if (err)
4696 return err;
4697
4698 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
4699 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
4700 return -EIO;
4701
4702 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
4703 sizeof(struct mlxsw_sp_upper),
4704 GFP_KERNEL);
4705 if (!mlxsw_sp->lags)
4706 return -ENOMEM;
4707
4708 return 0;
4709 }
4710
4711 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
4712 {
4713 kfree(mlxsw_sp->lags);
4714 }
4715
4716 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
4717 {
4718 char htgt_pl[MLXSW_REG_HTGT_LEN];
4719
4720 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
4721 MLXSW_REG_HTGT_INVALID_POLICER,
4722 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
4723 MLXSW_REG_HTGT_DEFAULT_TC);
4724 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
4725 }
4726
4727 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = {
4728 .clock_init = mlxsw_sp1_ptp_clock_init,
4729 .clock_fini = mlxsw_sp1_ptp_clock_fini,
4730 .init = mlxsw_sp1_ptp_init,
4731 .fini = mlxsw_sp1_ptp_fini,
4732 .receive = mlxsw_sp1_ptp_receive,
4733 .transmitted = mlxsw_sp1_ptp_transmitted,
4734 .hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get,
4735 .hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set,
4736 .shaper_work = mlxsw_sp1_ptp_shaper_work,
4737 .get_ts_info = mlxsw_sp1_ptp_get_ts_info,
4738 .get_stats_count = mlxsw_sp1_get_stats_count,
4739 .get_stats_strings = mlxsw_sp1_get_stats_strings,
4740 .get_stats = mlxsw_sp1_get_stats,
4741 };
4742
4743 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = {
4744 .clock_init = mlxsw_sp2_ptp_clock_init,
4745 .clock_fini = mlxsw_sp2_ptp_clock_fini,
4746 .init = mlxsw_sp2_ptp_init,
4747 .fini = mlxsw_sp2_ptp_fini,
4748 .receive = mlxsw_sp2_ptp_receive,
4749 .transmitted = mlxsw_sp2_ptp_transmitted,
4750 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get,
4751 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set,
4752 .shaper_work = mlxsw_sp2_ptp_shaper_work,
4753 .get_ts_info = mlxsw_sp2_ptp_get_ts_info,
4754 .get_stats_count = mlxsw_sp2_get_stats_count,
4755 .get_stats_strings = mlxsw_sp2_get_stats_strings,
4756 .get_stats = mlxsw_sp2_get_stats,
4757 };
4758
4759 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4760 unsigned long event, void *ptr);
4761
4762 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
4763 const struct mlxsw_bus_info *mlxsw_bus_info)
4764 {
4765 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4766 int err;
4767
4768 mlxsw_sp->core = mlxsw_core;
4769 mlxsw_sp->bus_info = mlxsw_bus_info;
4770
4771 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
4772 if (err)
4773 return err;
4774
4775 err = mlxsw_sp_base_mac_get(mlxsw_sp);
4776 if (err) {
4777 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
4778 return err;
4779 }
4780
4781 err = mlxsw_sp_kvdl_init(mlxsw_sp);
4782 if (err) {
4783 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
4784 return err;
4785 }
4786
4787 err = mlxsw_sp_fids_init(mlxsw_sp);
4788 if (err) {
4789 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
4790 goto err_fids_init;
4791 }
4792
4793 err = mlxsw_sp_traps_init(mlxsw_sp);
4794 if (err) {
4795 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
4796 goto err_traps_init;
4797 }
4798
4799 err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
4800 if (err) {
4801 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
4802 goto err_devlink_traps_init;
4803 }
4804
4805 err = mlxsw_sp_buffers_init(mlxsw_sp);
4806 if (err) {
4807 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
4808 goto err_buffers_init;
4809 }
4810
4811 err = mlxsw_sp_lag_init(mlxsw_sp);
4812 if (err) {
4813 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
4814 goto err_lag_init;
4815 }
4816
4817
4818
4819
4820 err = mlxsw_sp_span_init(mlxsw_sp);
4821 if (err) {
4822 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
4823 goto err_span_init;
4824 }
4825
4826 err = mlxsw_sp_switchdev_init(mlxsw_sp);
4827 if (err) {
4828 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
4829 goto err_switchdev_init;
4830 }
4831
4832 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
4833 if (err) {
4834 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
4835 goto err_counter_pool_init;
4836 }
4837
4838 err = mlxsw_sp_afa_init(mlxsw_sp);
4839 if (err) {
4840 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
4841 goto err_afa_init;
4842 }
4843
4844 err = mlxsw_sp_nve_init(mlxsw_sp);
4845 if (err) {
4846 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
4847 goto err_nve_init;
4848 }
4849
4850 err = mlxsw_sp_acl_init(mlxsw_sp);
4851 if (err) {
4852 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
4853 goto err_acl_init;
4854 }
4855
4856 err = mlxsw_sp_router_init(mlxsw_sp);
4857 if (err) {
4858 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
4859 goto err_router_init;
4860 }
4861
4862 if (mlxsw_sp->bus_info->read_frc_capable) {
4863
4864 mlxsw_sp->clock =
4865 mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
4866 mlxsw_sp->bus_info->dev);
4867 if (IS_ERR(mlxsw_sp->clock)) {
4868 err = PTR_ERR(mlxsw_sp->clock);
4869 dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
4870 goto err_ptp_clock_init;
4871 }
4872 }
4873
4874 if (mlxsw_sp->clock) {
4875
4876 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
4877 if (IS_ERR(mlxsw_sp->ptp_state)) {
4878 err = PTR_ERR(mlxsw_sp->ptp_state);
4879 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
4880 goto err_ptp_init;
4881 }
4882 }
4883
4884
4885
4886
4887
4888 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
4889 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4890 if (err) {
4891 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
4892 goto err_netdev_notifier;
4893 }
4894
4895 err = mlxsw_sp_dpipe_init(mlxsw_sp);
4896 if (err) {
4897 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
4898 goto err_dpipe_init;
4899 }
4900
4901 err = mlxsw_sp_ports_create(mlxsw_sp);
4902 if (err) {
4903 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
4904 goto err_ports_create;
4905 }
4906
4907 return 0;
4908
4909 err_ports_create:
4910 mlxsw_sp_dpipe_fini(mlxsw_sp);
4911 err_dpipe_init:
4912 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4913 err_netdev_notifier:
4914 if (mlxsw_sp->clock)
4915 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
4916 err_ptp_init:
4917 if (mlxsw_sp->clock)
4918 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
4919 err_ptp_clock_init:
4920 mlxsw_sp_router_fini(mlxsw_sp);
4921 err_router_init:
4922 mlxsw_sp_acl_fini(mlxsw_sp);
4923 err_acl_init:
4924 mlxsw_sp_nve_fini(mlxsw_sp);
4925 err_nve_init:
4926 mlxsw_sp_afa_fini(mlxsw_sp);
4927 err_afa_init:
4928 mlxsw_sp_counter_pool_fini(mlxsw_sp);
4929 err_counter_pool_init:
4930 mlxsw_sp_switchdev_fini(mlxsw_sp);
4931 err_switchdev_init:
4932 mlxsw_sp_span_fini(mlxsw_sp);
4933 err_span_init:
4934 mlxsw_sp_lag_fini(mlxsw_sp);
4935 err_lag_init:
4936 mlxsw_sp_buffers_fini(mlxsw_sp);
4937 err_buffers_init:
4938 mlxsw_sp_devlink_traps_fini(mlxsw_sp);
4939 err_devlink_traps_init:
4940 mlxsw_sp_traps_fini(mlxsw_sp);
4941 err_traps_init:
4942 mlxsw_sp_fids_fini(mlxsw_sp);
4943 err_fids_init:
4944 mlxsw_sp_kvdl_fini(mlxsw_sp);
4945 return err;
4946 }
4947
4948 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
4949 const struct mlxsw_bus_info *mlxsw_bus_info)
4950 {
4951 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4952
4953 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
4954 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
4955 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
4956 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
4957 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
4958 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
4959 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
4960 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
4961 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
4962 mlxsw_sp->rif_ops_arr = mlxsw_sp1_rif_ops_arr;
4963 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
4964 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
4965 mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
4966 mlxsw_sp->listeners = mlxsw_sp1_listener;
4967 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
4968
4969 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
4970 }
4971
4972 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
4973 const struct mlxsw_bus_info *mlxsw_bus_info)
4974 {
4975 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4976
4977 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
4978 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
4979 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
4980 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
4981 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
4982 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
4983 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
4984 mlxsw_sp->rif_ops_arr = mlxsw_sp2_rif_ops_arr;
4985 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
4986 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
4987 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
4988
4989 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
4990 }
4991
4992 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
4993 {
4994 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4995
4996 mlxsw_sp_ports_remove(mlxsw_sp);
4997 mlxsw_sp_dpipe_fini(mlxsw_sp);
4998 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4999 if (mlxsw_sp->clock) {
5000 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
5001 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
5002 }
5003 mlxsw_sp_router_fini(mlxsw_sp);
5004 mlxsw_sp_acl_fini(mlxsw_sp);
5005 mlxsw_sp_nve_fini(mlxsw_sp);
5006 mlxsw_sp_afa_fini(mlxsw_sp);
5007 mlxsw_sp_counter_pool_fini(mlxsw_sp);
5008 mlxsw_sp_switchdev_fini(mlxsw_sp);
5009 mlxsw_sp_span_fini(mlxsw_sp);
5010 mlxsw_sp_lag_fini(mlxsw_sp);
5011 mlxsw_sp_buffers_fini(mlxsw_sp);
5012 mlxsw_sp_devlink_traps_fini(mlxsw_sp);
5013 mlxsw_sp_traps_fini(mlxsw_sp);
5014 mlxsw_sp_fids_fini(mlxsw_sp);
5015 mlxsw_sp_kvdl_fini(mlxsw_sp);
5016 }
5017
5018
5019
5020
5021 #define MLXSW_SP_FID_FLOOD_TABLE_SIZE (MLXSW_SP_FID_8021D_MAX + \
5022 VLAN_VID_MASK - 1)
5023
5024 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
5025 .used_max_mid = 1,
5026 .max_mid = MLXSW_SP_MID_MAX,
5027 .used_flood_tables = 1,
5028 .used_flood_mode = 1,
5029 .flood_mode = 3,
5030 .max_fid_flood_tables = 3,
5031 .fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
5032 .used_max_ib_mc = 1,
5033 .max_ib_mc = 0,
5034 .used_max_pkey = 1,
5035 .max_pkey = 0,
5036 .used_kvd_sizes = 1,
5037 .kvd_hash_single_parts = 59,
5038 .kvd_hash_double_parts = 41,
5039 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
5040 .swid_config = {
5041 {
5042 .used_type = 1,
5043 .type = MLXSW_PORT_SWID_TYPE_ETH,
5044 }
5045 },
5046 };
5047
5048 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
5049 .used_max_mid = 1,
5050 .max_mid = MLXSW_SP_MID_MAX,
5051 .used_flood_tables = 1,
5052 .used_flood_mode = 1,
5053 .flood_mode = 3,
5054 .max_fid_flood_tables = 3,
5055 .fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
5056 .used_max_ib_mc = 1,
5057 .max_ib_mc = 0,
5058 .used_max_pkey = 1,
5059 .max_pkey = 0,
5060 .swid_config = {
5061 {
5062 .used_type = 1,
5063 .type = MLXSW_PORT_SWID_TYPE_ETH,
5064 }
5065 },
5066 };
5067
5068 static void
5069 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
5070 struct devlink_resource_size_params *kvd_size_params,
5071 struct devlink_resource_size_params *linear_size_params,
5072 struct devlink_resource_size_params *hash_double_size_params,
5073 struct devlink_resource_size_params *hash_single_size_params)
5074 {
5075 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
5076 KVD_SINGLE_MIN_SIZE);
5077 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
5078 KVD_DOUBLE_MIN_SIZE);
5079 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5080 u32 linear_size_min = 0;
5081
5082 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
5083 MLXSW_SP_KVD_GRANULARITY,
5084 DEVLINK_RESOURCE_UNIT_ENTRY);
5085 devlink_resource_size_params_init(linear_size_params, linear_size_min,
5086 kvd_size - single_size_min -
5087 double_size_min,
5088 MLXSW_SP_KVD_GRANULARITY,
5089 DEVLINK_RESOURCE_UNIT_ENTRY);
5090 devlink_resource_size_params_init(hash_double_size_params,
5091 double_size_min,
5092 kvd_size - single_size_min -
5093 linear_size_min,
5094 MLXSW_SP_KVD_GRANULARITY,
5095 DEVLINK_RESOURCE_UNIT_ENTRY);
5096 devlink_resource_size_params_init(hash_single_size_params,
5097 single_size_min,
5098 kvd_size - double_size_min -
5099 linear_size_min,
5100 MLXSW_SP_KVD_GRANULARITY,
5101 DEVLINK_RESOURCE_UNIT_ENTRY);
5102 }
5103
5104 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
5105 {
5106 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5107 struct devlink_resource_size_params hash_single_size_params;
5108 struct devlink_resource_size_params hash_double_size_params;
5109 struct devlink_resource_size_params linear_size_params;
5110 struct devlink_resource_size_params kvd_size_params;
5111 u32 kvd_size, single_size, double_size, linear_size;
5112 const struct mlxsw_config_profile *profile;
5113 int err;
5114
5115 profile = &mlxsw_sp1_config_profile;
5116 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
5117 return -EIO;
5118
5119 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
5120 &linear_size_params,
5121 &hash_double_size_params,
5122 &hash_single_size_params);
5123
5124 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5125 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
5126 kvd_size, MLXSW_SP_RESOURCE_KVD,
5127 DEVLINK_RESOURCE_ID_PARENT_TOP,
5128 &kvd_size_params);
5129 if (err)
5130 return err;
5131
5132 linear_size = profile->kvd_linear_size;
5133 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
5134 linear_size,
5135 MLXSW_SP_RESOURCE_KVD_LINEAR,
5136 MLXSW_SP_RESOURCE_KVD,
5137 &linear_size_params);
5138 if (err)
5139 return err;
5140
5141 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
5142 if (err)
5143 return err;
5144
5145 double_size = kvd_size - linear_size;
5146 double_size *= profile->kvd_hash_double_parts;
5147 double_size /= profile->kvd_hash_double_parts +
5148 profile->kvd_hash_single_parts;
5149 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
5150 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
5151 double_size,
5152 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
5153 MLXSW_SP_RESOURCE_KVD,
5154 &hash_double_size_params);
5155 if (err)
5156 return err;
5157
5158 single_size = kvd_size - double_size - linear_size;
5159 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
5160 single_size,
5161 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
5162 MLXSW_SP_RESOURCE_KVD,
5163 &hash_single_size_params);
5164 if (err)
5165 return err;
5166
5167 return 0;
5168 }
5169
5170 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core)
5171 {
5172 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5173 struct devlink_resource_size_params kvd_size_params;
5174 u32 kvd_size;
5175
5176 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
5177 return -EIO;
5178
5179 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5180 devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size,
5181 MLXSW_SP_KVD_GRANULARITY,
5182 DEVLINK_RESOURCE_UNIT_ENTRY);
5183
5184 return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
5185 kvd_size, MLXSW_SP_RESOURCE_KVD,
5186 DEVLINK_RESOURCE_ID_PARENT_TOP,
5187 &kvd_size_params);
5188 }
5189
5190 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
5191 {
5192 return mlxsw_sp1_resources_kvd_register(mlxsw_core);
5193 }
5194
5195 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
5196 {
5197 return mlxsw_sp2_resources_kvd_register(mlxsw_core);
5198 }
5199
5200 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
5201 const struct mlxsw_config_profile *profile,
5202 u64 *p_single_size, u64 *p_double_size,
5203 u64 *p_linear_size)
5204 {
5205 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5206 u32 double_size;
5207 int err;
5208
5209 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
5210 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
5211 return -EIO;
5212
5213
5214
5215
5216
5217
5218
5219
5220 err = devlink_resource_size_get(devlink,
5221 MLXSW_SP_RESOURCE_KVD_LINEAR,
5222 p_linear_size);
5223 if (err)
5224 *p_linear_size = profile->kvd_linear_size;
5225
5226 err = devlink_resource_size_get(devlink,
5227 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
5228 p_double_size);
5229 if (err) {
5230 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
5231 *p_linear_size;
5232 double_size *= profile->kvd_hash_double_parts;
5233 double_size /= profile->kvd_hash_double_parts +
5234 profile->kvd_hash_single_parts;
5235 *p_double_size = rounddown(double_size,
5236 MLXSW_SP_KVD_GRANULARITY);
5237 }
5238
5239 err = devlink_resource_size_get(devlink,
5240 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
5241 p_single_size);
5242 if (err)
5243 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
5244 *p_double_size - *p_linear_size;
5245
5246
5247 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
5248 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
5249 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
5250 return -EIO;
5251
5252 return 0;
5253 }
5254
5255 static int
5256 mlxsw_sp_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id,
5257 union devlink_param_value val,
5258 struct netlink_ext_ack *extack)
5259 {
5260 if ((val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER) &&
5261 (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)) {
5262 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'");
5263 return -EINVAL;
5264 }
5265
5266 return 0;
5267 }
5268
5269 static const struct devlink_param mlxsw_sp_devlink_params[] = {
5270 DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY,
5271 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
5272 NULL, NULL,
5273 mlxsw_sp_devlink_param_fw_load_policy_validate),
5274 };
5275
5276 static int mlxsw_sp_params_register(struct mlxsw_core *mlxsw_core)
5277 {
5278 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5279 union devlink_param_value value;
5280 int err;
5281
5282 err = devlink_params_register(devlink, mlxsw_sp_devlink_params,
5283 ARRAY_SIZE(mlxsw_sp_devlink_params));
5284 if (err)
5285 return err;
5286
5287 value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER;
5288 devlink_param_driverinit_value_set(devlink,
5289 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
5290 value);
5291 return 0;
5292 }
5293
5294 static void mlxsw_sp_params_unregister(struct mlxsw_core *mlxsw_core)
5295 {
5296 devlink_params_unregister(priv_to_devlink(mlxsw_core),
5297 mlxsw_sp_devlink_params,
5298 ARRAY_SIZE(mlxsw_sp_devlink_params));
5299 }
5300
5301 static int
5302 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id,
5303 struct devlink_param_gset_ctx *ctx)
5304 {
5305 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
5306 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5307
5308 ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp);
5309 return 0;
5310 }
5311
5312 static int
5313 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id,
5314 struct devlink_param_gset_ctx *ctx)
5315 {
5316 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
5317 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5318
5319 return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32);
5320 }
5321
5322 static const struct devlink_param mlxsw_sp2_devlink_params[] = {
5323 DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
5324 "acl_region_rehash_interval",
5325 DEVLINK_PARAM_TYPE_U32,
5326 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
5327 mlxsw_sp_params_acl_region_rehash_intrvl_get,
5328 mlxsw_sp_params_acl_region_rehash_intrvl_set,
5329 NULL),
5330 };
5331
5332 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core)
5333 {
5334 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5335 union devlink_param_value value;
5336 int err;
5337
5338 err = mlxsw_sp_params_register(mlxsw_core);
5339 if (err)
5340 return err;
5341
5342 err = devlink_params_register(devlink, mlxsw_sp2_devlink_params,
5343 ARRAY_SIZE(mlxsw_sp2_devlink_params));
5344 if (err)
5345 goto err_devlink_params_register;
5346
5347 value.vu32 = 0;
5348 devlink_param_driverinit_value_set(devlink,
5349 MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
5350 value);
5351 return 0;
5352
5353 err_devlink_params_register:
5354 mlxsw_sp_params_unregister(mlxsw_core);
5355 return err;
5356 }
5357
5358 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core)
5359 {
5360 devlink_params_unregister(priv_to_devlink(mlxsw_core),
5361 mlxsw_sp2_devlink_params,
5362 ARRAY_SIZE(mlxsw_sp2_devlink_params));
5363 mlxsw_sp_params_unregister(mlxsw_core);
5364 }
5365
5366 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core,
5367 struct sk_buff *skb, u8 local_port)
5368 {
5369 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5370
5371 skb_pull(skb, MLXSW_TXHDR_LEN);
5372 mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
5373 }
5374
5375 static struct mlxsw_driver mlxsw_sp1_driver = {
5376 .kind = mlxsw_sp1_driver_name,
5377 .priv_size = sizeof(struct mlxsw_sp),
5378 .init = mlxsw_sp1_init,
5379 .fini = mlxsw_sp_fini,
5380 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
5381 .port_split = mlxsw_sp_port_split,
5382 .port_unsplit = mlxsw_sp_port_unsplit,
5383 .sb_pool_get = mlxsw_sp_sb_pool_get,
5384 .sb_pool_set = mlxsw_sp_sb_pool_set,
5385 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
5386 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
5387 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
5388 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
5389 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
5390 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
5391 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
5392 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
5393 .flash_update = mlxsw_sp_flash_update,
5394 .trap_init = mlxsw_sp_trap_init,
5395 .trap_fini = mlxsw_sp_trap_fini,
5396 .trap_action_set = mlxsw_sp_trap_action_set,
5397 .trap_group_init = mlxsw_sp_trap_group_init,
5398 .txhdr_construct = mlxsw_sp_txhdr_construct,
5399 .resources_register = mlxsw_sp1_resources_register,
5400 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
5401 .params_register = mlxsw_sp_params_register,
5402 .params_unregister = mlxsw_sp_params_unregister,
5403 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
5404 .txhdr_len = MLXSW_TXHDR_LEN,
5405 .profile = &mlxsw_sp1_config_profile,
5406 .res_query_enabled = true,
5407 };
5408
5409 static struct mlxsw_driver mlxsw_sp2_driver = {
5410 .kind = mlxsw_sp2_driver_name,
5411 .priv_size = sizeof(struct mlxsw_sp),
5412 .init = mlxsw_sp2_init,
5413 .fini = mlxsw_sp_fini,
5414 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
5415 .port_split = mlxsw_sp_port_split,
5416 .port_unsplit = mlxsw_sp_port_unsplit,
5417 .sb_pool_get = mlxsw_sp_sb_pool_get,
5418 .sb_pool_set = mlxsw_sp_sb_pool_set,
5419 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
5420 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
5421 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
5422 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
5423 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
5424 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
5425 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
5426 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
5427 .flash_update = mlxsw_sp_flash_update,
5428 .trap_init = mlxsw_sp_trap_init,
5429 .trap_fini = mlxsw_sp_trap_fini,
5430 .trap_action_set = mlxsw_sp_trap_action_set,
5431 .trap_group_init = mlxsw_sp_trap_group_init,
5432 .txhdr_construct = mlxsw_sp_txhdr_construct,
5433 .resources_register = mlxsw_sp2_resources_register,
5434 .params_register = mlxsw_sp2_params_register,
5435 .params_unregister = mlxsw_sp2_params_unregister,
5436 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
5437 .txhdr_len = MLXSW_TXHDR_LEN,
5438 .profile = &mlxsw_sp2_config_profile,
5439 .res_query_enabled = true,
5440 };
5441
5442 static struct mlxsw_driver mlxsw_sp3_driver = {
5443 .kind = mlxsw_sp3_driver_name,
5444 .priv_size = sizeof(struct mlxsw_sp),
5445 .init = mlxsw_sp2_init,
5446 .fini = mlxsw_sp_fini,
5447 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
5448 .port_split = mlxsw_sp_port_split,
5449 .port_unsplit = mlxsw_sp_port_unsplit,
5450 .sb_pool_get = mlxsw_sp_sb_pool_get,
5451 .sb_pool_set = mlxsw_sp_sb_pool_set,
5452 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
5453 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
5454 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
5455 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
5456 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
5457 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
5458 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
5459 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
5460 .flash_update = mlxsw_sp_flash_update,
5461 .trap_init = mlxsw_sp_trap_init,
5462 .trap_fini = mlxsw_sp_trap_fini,
5463 .trap_action_set = mlxsw_sp_trap_action_set,
5464 .trap_group_init = mlxsw_sp_trap_group_init,
5465 .txhdr_construct = mlxsw_sp_txhdr_construct,
5466 .resources_register = mlxsw_sp2_resources_register,
5467 .params_register = mlxsw_sp2_params_register,
5468 .params_unregister = mlxsw_sp2_params_unregister,
5469 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
5470 .txhdr_len = MLXSW_TXHDR_LEN,
5471 .profile = &mlxsw_sp2_config_profile,
5472 .res_query_enabled = true,
5473 };
5474
5475 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
5476 {
5477 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
5478 }
5479
5480 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
5481 {
5482 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
5483 int ret = 0;
5484
5485 if (mlxsw_sp_port_dev_check(lower_dev)) {
5486 *p_mlxsw_sp_port = netdev_priv(lower_dev);
5487 ret = 1;
5488 }
5489
5490 return ret;
5491 }
5492
5493 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
5494 {
5495 struct mlxsw_sp_port *mlxsw_sp_port;
5496
5497 if (mlxsw_sp_port_dev_check(dev))
5498 return netdev_priv(dev);
5499
5500 mlxsw_sp_port = NULL;
5501 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
5502
5503 return mlxsw_sp_port;
5504 }
5505
5506 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
5507 {
5508 struct mlxsw_sp_port *mlxsw_sp_port;
5509
5510 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
5511 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
5512 }
5513
5514 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
5515 {
5516 struct mlxsw_sp_port *mlxsw_sp_port;
5517
5518 if (mlxsw_sp_port_dev_check(dev))
5519 return netdev_priv(dev);
5520
5521 mlxsw_sp_port = NULL;
5522 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
5523 &mlxsw_sp_port);
5524
5525 return mlxsw_sp_port;
5526 }
5527
5528 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
5529 {
5530 struct mlxsw_sp_port *mlxsw_sp_port;
5531
5532 rcu_read_lock();
5533 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
5534 if (mlxsw_sp_port)
5535 dev_hold(mlxsw_sp_port->dev);
5536 rcu_read_unlock();
5537 return mlxsw_sp_port;
5538 }
5539
5540 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
5541 {
5542 dev_put(mlxsw_sp_port->dev);
5543 }
5544
5545 static void
5546 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
5547 struct net_device *lag_dev)
5548 {
5549 struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
5550 struct net_device *upper_dev;
5551 struct list_head *iter;
5552
5553 if (netif_is_bridge_port(lag_dev))
5554 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
5555
5556 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
5557 if (!netif_is_bridge_port(upper_dev))
5558 continue;
5559 br_dev = netdev_master_upper_dev_get(upper_dev);
5560 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
5561 }
5562 }
5563
5564 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
5565 {
5566 char sldr_pl[MLXSW_REG_SLDR_LEN];
5567
5568 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
5569 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5570 }
5571
5572 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
5573 {
5574 char sldr_pl[MLXSW_REG_SLDR_LEN];
5575
5576 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
5577 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5578 }
5579
5580 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
5581 u16 lag_id, u8 port_index)
5582 {
5583 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5584 char slcor_pl[MLXSW_REG_SLCOR_LEN];
5585
5586 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
5587 lag_id, port_index);
5588 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5589 }
5590
5591 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
5592 u16 lag_id)
5593 {
5594 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5595 char slcor_pl[MLXSW_REG_SLCOR_LEN];
5596
5597 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
5598 lag_id);
5599 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5600 }
5601
5602 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
5603 u16 lag_id)
5604 {
5605 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5606 char slcor_pl[MLXSW_REG_SLCOR_LEN];
5607
5608 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
5609 lag_id);
5610 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5611 }
5612
5613 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
5614 u16 lag_id)
5615 {
5616 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5617 char slcor_pl[MLXSW_REG_SLCOR_LEN];
5618
5619 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
5620 lag_id);
5621 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5622 }
5623
5624 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
5625 struct net_device *lag_dev,
5626 u16 *p_lag_id)
5627 {
5628 struct mlxsw_sp_upper *lag;
5629 int free_lag_id = -1;
5630 u64 max_lag;
5631 int i;
5632
5633 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
5634 for (i = 0; i < max_lag; i++) {
5635 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
5636 if (lag->ref_count) {
5637 if (lag->dev == lag_dev) {
5638 *p_lag_id = i;
5639 return 0;
5640 }
5641 } else if (free_lag_id < 0) {
5642 free_lag_id = i;
5643 }
5644 }
5645 if (free_lag_id < 0)
5646 return -EBUSY;
5647 *p_lag_id = free_lag_id;
5648 return 0;
5649 }
5650
5651 static bool
5652 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
5653 struct net_device *lag_dev,
5654 struct netdev_lag_upper_info *lag_upper_info,
5655 struct netlink_ext_ack *extack)
5656 {
5657 u16 lag_id;
5658
5659 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
5660 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
5661 return false;
5662 }
5663 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
5664 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
5665 return false;
5666 }
5667 return true;
5668 }
5669
5670 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
5671 u16 lag_id, u8 *p_port_index)
5672 {
5673 u64 max_lag_members;
5674 int i;
5675
5676 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
5677 MAX_LAG_MEMBERS);
5678 for (i = 0; i < max_lag_members; i++) {
5679 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
5680 *p_port_index = i;
5681 return 0;
5682 }
5683 }
5684 return -EBUSY;
5685 }
5686
5687 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
5688 struct net_device *lag_dev)
5689 {
5690 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5691 struct mlxsw_sp_upper *lag;
5692 u16 lag_id;
5693 u8 port_index;
5694 int err;
5695
5696 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
5697 if (err)
5698 return err;
5699 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
5700 if (!lag->ref_count) {
5701 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
5702 if (err)
5703 return err;
5704 lag->dev = lag_dev;
5705 }
5706
5707 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
5708 if (err)
5709 return err;
5710 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
5711 if (err)
5712 goto err_col_port_add;
5713
5714 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
5715 mlxsw_sp_port->local_port);
5716 mlxsw_sp_port->lag_id = lag_id;
5717 mlxsw_sp_port->lagged = 1;
5718 lag->ref_count++;
5719
5720
5721 if (mlxsw_sp_port->default_vlan->fid)
5722 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
5723
5724 return 0;
5725
5726 err_col_port_add:
5727 if (!lag->ref_count)
5728 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
5729 return err;
5730 }
5731
5732 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
5733 struct net_device *lag_dev)
5734 {
5735 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5736 u16 lag_id = mlxsw_sp_port->lag_id;
5737 struct mlxsw_sp_upper *lag;
5738
5739 if (!mlxsw_sp_port->lagged)
5740 return;
5741 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
5742 WARN_ON(lag->ref_count == 0);
5743
5744 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
5745
5746
5747 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
5748 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
5749
5750
5751
5752 mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
5753
5754 if (lag->ref_count == 1)
5755 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
5756
5757 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
5758 mlxsw_sp_port->local_port);
5759 mlxsw_sp_port->lagged = 0;
5760 lag->ref_count--;
5761
5762
5763 mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
5764 }
5765
5766 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
5767 u16 lag_id)
5768 {
5769 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5770 char sldr_pl[MLXSW_REG_SLDR_LEN];
5771
5772 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
5773 mlxsw_sp_port->local_port);
5774 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5775 }
5776
5777 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
5778 u16 lag_id)
5779 {
5780 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5781 char sldr_pl[MLXSW_REG_SLDR_LEN];
5782
5783 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
5784 mlxsw_sp_port->local_port);
5785 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5786 }
5787
5788 static int
5789 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
5790 {
5791 int err;
5792
5793 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
5794 mlxsw_sp_port->lag_id);
5795 if (err)
5796 return err;
5797
5798 err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5799 if (err)
5800 goto err_dist_port_add;
5801
5802 return 0;
5803
5804 err_dist_port_add:
5805 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5806 return err;
5807 }
5808
5809 static int
5810 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
5811 {
5812 int err;
5813
5814 err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
5815 mlxsw_sp_port->lag_id);
5816 if (err)
5817 return err;
5818
5819 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
5820 mlxsw_sp_port->lag_id);
5821 if (err)
5822 goto err_col_port_disable;
5823
5824 return 0;
5825
5826 err_col_port_disable:
5827 mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5828 return err;
5829 }
5830
5831 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
5832 struct netdev_lag_lower_state_info *info)
5833 {
5834 if (info->tx_enabled)
5835 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
5836 else
5837 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
5838 }
5839
5840 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
5841 bool enable)
5842 {
5843 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5844 enum mlxsw_reg_spms_state spms_state;
5845 char *spms_pl;
5846 u16 vid;
5847 int err;
5848
5849 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
5850 MLXSW_REG_SPMS_STATE_DISCARDING;
5851
5852 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
5853 if (!spms_pl)
5854 return -ENOMEM;
5855 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
5856
5857 for (vid = 0; vid < VLAN_N_VID; vid++)
5858 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
5859
5860 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
5861 kfree(spms_pl);
5862 return err;
5863 }
5864
5865 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
5866 {
5867 u16 vid = 1;
5868 int err;
5869
5870 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
5871 if (err)
5872 return err;
5873 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
5874 if (err)
5875 goto err_port_stp_set;
5876 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
5877 true, false);
5878 if (err)
5879 goto err_port_vlan_set;
5880
5881 for (; vid <= VLAN_N_VID - 1; vid++) {
5882 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
5883 vid, false);
5884 if (err)
5885 goto err_vid_learning_set;
5886 }
5887
5888 return 0;
5889
5890 err_vid_learning_set:
5891 for (vid--; vid >= 1; vid--)
5892 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
5893 err_port_vlan_set:
5894 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
5895 err_port_stp_set:
5896 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
5897 return err;
5898 }
5899
5900 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
5901 {
5902 u16 vid;
5903
5904 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
5905 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
5906 vid, true);
5907
5908 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
5909 false, false);
5910 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
5911 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
5912 }
5913
5914 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
5915 {
5916 unsigned int num_vxlans = 0;
5917 struct net_device *dev;
5918 struct list_head *iter;
5919
5920 netdev_for_each_lower_dev(br_dev, dev, iter) {
5921 if (netif_is_vxlan(dev))
5922 num_vxlans++;
5923 }
5924
5925 return num_vxlans > 1;
5926 }
5927
5928 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
5929 {
5930 DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
5931 struct net_device *dev;
5932 struct list_head *iter;
5933
5934 netdev_for_each_lower_dev(br_dev, dev, iter) {
5935 u16 pvid;
5936 int err;
5937
5938 if (!netif_is_vxlan(dev))
5939 continue;
5940
5941 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
5942 if (err || !pvid)
5943 continue;
5944
5945 if (test_and_set_bit(pvid, vlans))
5946 return false;
5947 }
5948
5949 return true;
5950 }
5951
5952 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
5953 struct netlink_ext_ack *extack)
5954 {
5955 if (br_multicast_enabled(br_dev)) {
5956 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
5957 return false;
5958 }
5959
5960 if (!br_vlan_enabled(br_dev) &&
5961 mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
5962 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
5963 return false;
5964 }
5965
5966 if (br_vlan_enabled(br_dev) &&
5967 !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
5968 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
5969 return false;
5970 }
5971
5972 return true;
5973 }
5974
5975 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
5976 struct net_device *dev,
5977 unsigned long event, void *ptr)
5978 {
5979 struct netdev_notifier_changeupper_info *info;
5980 struct mlxsw_sp_port *mlxsw_sp_port;
5981 struct netlink_ext_ack *extack;
5982 struct net_device *upper_dev;
5983 struct mlxsw_sp *mlxsw_sp;
5984 int err = 0;
5985
5986 mlxsw_sp_port = netdev_priv(dev);
5987 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5988 info = ptr;
5989 extack = netdev_notifier_info_to_extack(&info->info);
5990
5991 switch (event) {
5992 case NETDEV_PRECHANGEUPPER:
5993 upper_dev = info->upper_dev;
5994 if (!is_vlan_dev(upper_dev) &&
5995 !netif_is_lag_master(upper_dev) &&
5996 !netif_is_bridge_master(upper_dev) &&
5997 !netif_is_ovs_master(upper_dev) &&
5998 !netif_is_macvlan(upper_dev)) {
5999 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6000 return -EINVAL;
6001 }
6002 if (!info->linking)
6003 break;
6004 if (netif_is_bridge_master(upper_dev) &&
6005 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
6006 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
6007 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6008 return -EOPNOTSUPP;
6009 if (netdev_has_any_upper_dev(upper_dev) &&
6010 (!netif_is_bridge_master(upper_dev) ||
6011 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
6012 upper_dev))) {
6013 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
6014 return -EINVAL;
6015 }
6016 if (netif_is_lag_master(upper_dev) &&
6017 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
6018 info->upper_info, extack))
6019 return -EINVAL;
6020 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
6021 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
6022 return -EINVAL;
6023 }
6024 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
6025 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
6026 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
6027 return -EINVAL;
6028 }
6029 if (netif_is_macvlan(upper_dev) &&
6030 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) {
6031 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6032 return -EOPNOTSUPP;
6033 }
6034 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
6035 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
6036 return -EINVAL;
6037 }
6038 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
6039 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
6040 return -EINVAL;
6041 }
6042 break;
6043 case NETDEV_CHANGEUPPER:
6044 upper_dev = info->upper_dev;
6045 if (netif_is_bridge_master(upper_dev)) {
6046 if (info->linking)
6047 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
6048 lower_dev,
6049 upper_dev,
6050 extack);
6051 else
6052 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
6053 lower_dev,
6054 upper_dev);
6055 } else if (netif_is_lag_master(upper_dev)) {
6056 if (info->linking) {
6057 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
6058 upper_dev);
6059 } else {
6060 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
6061 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
6062 upper_dev);
6063 }
6064 } else if (netif_is_ovs_master(upper_dev)) {
6065 if (info->linking)
6066 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
6067 else
6068 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
6069 } else if (netif_is_macvlan(upper_dev)) {
6070 if (!info->linking)
6071 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6072 } else if (is_vlan_dev(upper_dev)) {
6073 struct net_device *br_dev;
6074
6075 if (!netif_is_bridge_port(upper_dev))
6076 break;
6077 if (info->linking)
6078 break;
6079 br_dev = netdev_master_upper_dev_get(upper_dev);
6080 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
6081 br_dev);
6082 }
6083 break;
6084 }
6085
6086 return err;
6087 }
6088
6089 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
6090 unsigned long event, void *ptr)
6091 {
6092 struct netdev_notifier_changelowerstate_info *info;
6093 struct mlxsw_sp_port *mlxsw_sp_port;
6094 int err;
6095
6096 mlxsw_sp_port = netdev_priv(dev);
6097 info = ptr;
6098
6099 switch (event) {
6100 case NETDEV_CHANGELOWERSTATE:
6101 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
6102 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
6103 info->lower_state_info);
6104 if (err)
6105 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
6106 }
6107 break;
6108 }
6109
6110 return 0;
6111 }
6112
6113 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
6114 struct net_device *port_dev,
6115 unsigned long event, void *ptr)
6116 {
6117 switch (event) {
6118 case NETDEV_PRECHANGEUPPER:
6119 case NETDEV_CHANGEUPPER:
6120 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
6121 event, ptr);
6122 case NETDEV_CHANGELOWERSTATE:
6123 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
6124 ptr);
6125 }
6126
6127 return 0;
6128 }
6129
6130 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
6131 unsigned long event, void *ptr)
6132 {
6133 struct net_device *dev;
6134 struct list_head *iter;
6135 int ret;
6136
6137 netdev_for_each_lower_dev(lag_dev, dev, iter) {
6138 if (mlxsw_sp_port_dev_check(dev)) {
6139 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
6140 ptr);
6141 if (ret)
6142 return ret;
6143 }
6144 }
6145
6146 return 0;
6147 }
6148
6149 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
6150 struct net_device *dev,
6151 unsigned long event, void *ptr,
6152 u16 vid)
6153 {
6154 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
6155 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
6156 struct netdev_notifier_changeupper_info *info = ptr;
6157 struct netlink_ext_ack *extack;
6158 struct net_device *upper_dev;
6159 int err = 0;
6160
6161 extack = netdev_notifier_info_to_extack(&info->info);
6162
6163 switch (event) {
6164 case NETDEV_PRECHANGEUPPER:
6165 upper_dev = info->upper_dev;
6166 if (!netif_is_bridge_master(upper_dev) &&
6167 !netif_is_macvlan(upper_dev)) {
6168 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6169 return -EINVAL;
6170 }
6171 if (!info->linking)
6172 break;
6173 if (netif_is_bridge_master(upper_dev) &&
6174 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
6175 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
6176 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6177 return -EOPNOTSUPP;
6178 if (netdev_has_any_upper_dev(upper_dev) &&
6179 (!netif_is_bridge_master(upper_dev) ||
6180 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
6181 upper_dev))) {
6182 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
6183 return -EINVAL;
6184 }
6185 if (netif_is_macvlan(upper_dev) &&
6186 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
6187 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6188 return -EOPNOTSUPP;
6189 }
6190 break;
6191 case NETDEV_CHANGEUPPER:
6192 upper_dev = info->upper_dev;
6193 if (netif_is_bridge_master(upper_dev)) {
6194 if (info->linking)
6195 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
6196 vlan_dev,
6197 upper_dev,
6198 extack);
6199 else
6200 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
6201 vlan_dev,
6202 upper_dev);
6203 } else if (netif_is_macvlan(upper_dev)) {
6204 if (!info->linking)
6205 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6206 } else {
6207 err = -EINVAL;
6208 WARN_ON(1);
6209 }
6210 break;
6211 }
6212
6213 return err;
6214 }
6215
6216 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
6217 struct net_device *lag_dev,
6218 unsigned long event,
6219 void *ptr, u16 vid)
6220 {
6221 struct net_device *dev;
6222 struct list_head *iter;
6223 int ret;
6224
6225 netdev_for_each_lower_dev(lag_dev, dev, iter) {
6226 if (mlxsw_sp_port_dev_check(dev)) {
6227 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
6228 event, ptr,
6229 vid);
6230 if (ret)
6231 return ret;
6232 }
6233 }
6234
6235 return 0;
6236 }
6237
6238 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev,
6239 struct net_device *br_dev,
6240 unsigned long event, void *ptr,
6241 u16 vid)
6242 {
6243 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
6244 struct netdev_notifier_changeupper_info *info = ptr;
6245 struct netlink_ext_ack *extack;
6246 struct net_device *upper_dev;
6247
6248 if (!mlxsw_sp)
6249 return 0;
6250
6251 extack = netdev_notifier_info_to_extack(&info->info);
6252
6253 switch (event) {
6254 case NETDEV_PRECHANGEUPPER:
6255 upper_dev = info->upper_dev;
6256 if (!netif_is_macvlan(upper_dev)) {
6257 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6258 return -EOPNOTSUPP;
6259 }
6260 if (!info->linking)
6261 break;
6262 if (netif_is_macvlan(upper_dev) &&
6263 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
6264 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6265 return -EOPNOTSUPP;
6266 }
6267 break;
6268 case NETDEV_CHANGEUPPER:
6269 upper_dev = info->upper_dev;
6270 if (info->linking)
6271 break;
6272 if (netif_is_macvlan(upper_dev))
6273 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6274 break;
6275 }
6276
6277 return 0;
6278 }
6279
6280 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
6281 unsigned long event, void *ptr)
6282 {
6283 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
6284 u16 vid = vlan_dev_vlan_id(vlan_dev);
6285
6286 if (mlxsw_sp_port_dev_check(real_dev))
6287 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
6288 event, ptr, vid);
6289 else if (netif_is_lag_master(real_dev))
6290 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
6291 real_dev, event,
6292 ptr, vid);
6293 else if (netif_is_bridge_master(real_dev))
6294 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev,
6295 event, ptr, vid);
6296
6297 return 0;
6298 }
6299
6300 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
6301 unsigned long event, void *ptr)
6302 {
6303 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
6304 struct netdev_notifier_changeupper_info *info = ptr;
6305 struct netlink_ext_ack *extack;
6306 struct net_device *upper_dev;
6307
6308 if (!mlxsw_sp)
6309 return 0;
6310
6311 extack = netdev_notifier_info_to_extack(&info->info);
6312
6313 switch (event) {
6314 case NETDEV_PRECHANGEUPPER:
6315 upper_dev = info->upper_dev;
6316 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
6317 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6318 return -EOPNOTSUPP;
6319 }
6320 if (!info->linking)
6321 break;
6322 if (netif_is_macvlan(upper_dev) &&
6323 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) {
6324 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6325 return -EOPNOTSUPP;
6326 }
6327 break;
6328 case NETDEV_CHANGEUPPER:
6329 upper_dev = info->upper_dev;
6330 if (info->linking)
6331 break;
6332 if (is_vlan_dev(upper_dev))
6333 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
6334 if (netif_is_macvlan(upper_dev))
6335 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6336 break;
6337 }
6338
6339 return 0;
6340 }
6341
6342 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
6343 unsigned long event, void *ptr)
6344 {
6345 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
6346 struct netdev_notifier_changeupper_info *info = ptr;
6347 struct netlink_ext_ack *extack;
6348
6349 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
6350 return 0;
6351
6352 extack = netdev_notifier_info_to_extack(&info->info);
6353
6354
6355 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6356
6357 return -EOPNOTSUPP;
6358 }
6359
6360 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
6361 {
6362 struct netdev_notifier_changeupper_info *info = ptr;
6363
6364 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
6365 return false;
6366 return netif_is_l3_master(info->upper_dev);
6367 }
6368
6369 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
6370 struct net_device *dev,
6371 unsigned long event, void *ptr)
6372 {
6373 struct netdev_notifier_changeupper_info *cu_info;
6374 struct netdev_notifier_info *info = ptr;
6375 struct netlink_ext_ack *extack;
6376 struct net_device *upper_dev;
6377
6378 extack = netdev_notifier_info_to_extack(info);
6379
6380 switch (event) {
6381 case NETDEV_CHANGEUPPER:
6382 cu_info = container_of(info,
6383 struct netdev_notifier_changeupper_info,
6384 info);
6385 upper_dev = cu_info->upper_dev;
6386 if (!netif_is_bridge_master(upper_dev))
6387 return 0;
6388 if (!mlxsw_sp_lower_get(upper_dev))
6389 return 0;
6390 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6391 return -EOPNOTSUPP;
6392 if (cu_info->linking) {
6393 if (!netif_running(dev))
6394 return 0;
6395
6396
6397
6398
6399 if (br_vlan_enabled(upper_dev))
6400 return 0;
6401 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
6402 dev, 0, extack);
6403 } else {
6404
6405
6406
6407 if (br_vlan_enabled(upper_dev))
6408 return 0;
6409 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
6410 }
6411 break;
6412 case NETDEV_PRE_UP:
6413 upper_dev = netdev_master_upper_dev_get(dev);
6414 if (!upper_dev)
6415 return 0;
6416 if (!netif_is_bridge_master(upper_dev))
6417 return 0;
6418 if (!mlxsw_sp_lower_get(upper_dev))
6419 return 0;
6420 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
6421 extack);
6422 case NETDEV_DOWN:
6423 upper_dev = netdev_master_upper_dev_get(dev);
6424 if (!upper_dev)
6425 return 0;
6426 if (!netif_is_bridge_master(upper_dev))
6427 return 0;
6428 if (!mlxsw_sp_lower_get(upper_dev))
6429 return 0;
6430 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
6431 break;
6432 }
6433
6434 return 0;
6435 }
6436
6437 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
6438 unsigned long event, void *ptr)
6439 {
6440 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6441 struct mlxsw_sp_span_entry *span_entry;
6442 struct mlxsw_sp *mlxsw_sp;
6443 int err = 0;
6444
6445 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
6446 if (event == NETDEV_UNREGISTER) {
6447 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
6448 if (span_entry)
6449 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
6450 }
6451 mlxsw_sp_span_respin(mlxsw_sp);
6452
6453 if (netif_is_vxlan(dev))
6454 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
6455 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
6456 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
6457 event, ptr);
6458 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
6459 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
6460 event, ptr);
6461 else if (event == NETDEV_PRE_CHANGEADDR ||
6462 event == NETDEV_CHANGEADDR ||
6463 event == NETDEV_CHANGEMTU)
6464 err = mlxsw_sp_netdevice_router_port_event(dev, event, ptr);
6465 else if (mlxsw_sp_is_vrf_event(event, ptr))
6466 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
6467 else if (mlxsw_sp_port_dev_check(dev))
6468 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
6469 else if (netif_is_lag_master(dev))
6470 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
6471 else if (is_vlan_dev(dev))
6472 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
6473 else if (netif_is_bridge_master(dev))
6474 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
6475 else if (netif_is_macvlan(dev))
6476 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
6477
6478 return notifier_from_errno(err);
6479 }
6480
6481 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
6482 .notifier_call = mlxsw_sp_inetaddr_valid_event,
6483 };
6484
6485 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
6486 .notifier_call = mlxsw_sp_inet6addr_valid_event,
6487 };
6488
6489 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
6490 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
6491 {0, },
6492 };
6493
6494 static struct pci_driver mlxsw_sp1_pci_driver = {
6495 .name = mlxsw_sp1_driver_name,
6496 .id_table = mlxsw_sp1_pci_id_table,
6497 };
6498
6499 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
6500 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
6501 {0, },
6502 };
6503
6504 static struct pci_driver mlxsw_sp2_pci_driver = {
6505 .name = mlxsw_sp2_driver_name,
6506 .id_table = mlxsw_sp2_pci_id_table,
6507 };
6508
6509 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = {
6510 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0},
6511 {0, },
6512 };
6513
6514 static struct pci_driver mlxsw_sp3_pci_driver = {
6515 .name = mlxsw_sp3_driver_name,
6516 .id_table = mlxsw_sp3_pci_id_table,
6517 };
6518
6519 static int __init mlxsw_sp_module_init(void)
6520 {
6521 int err;
6522
6523 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6524 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6525
6526 err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
6527 if (err)
6528 goto err_sp1_core_driver_register;
6529
6530 err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
6531 if (err)
6532 goto err_sp2_core_driver_register;
6533
6534 err = mlxsw_core_driver_register(&mlxsw_sp3_driver);
6535 if (err)
6536 goto err_sp3_core_driver_register;
6537
6538 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
6539 if (err)
6540 goto err_sp1_pci_driver_register;
6541
6542 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
6543 if (err)
6544 goto err_sp2_pci_driver_register;
6545
6546 err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver);
6547 if (err)
6548 goto err_sp3_pci_driver_register;
6549
6550 return 0;
6551
6552 err_sp3_pci_driver_register:
6553 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
6554 err_sp2_pci_driver_register:
6555 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
6556 err_sp1_pci_driver_register:
6557 mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
6558 err_sp3_core_driver_register:
6559 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
6560 err_sp2_core_driver_register:
6561 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
6562 err_sp1_core_driver_register:
6563 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6564 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6565 return err;
6566 }
6567
6568 static void __exit mlxsw_sp_module_exit(void)
6569 {
6570 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
6571 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
6572 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
6573 mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
6574 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
6575 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
6576 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6577 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6578 }
6579
6580 module_init(mlxsw_sp_module_init);
6581 module_exit(mlxsw_sp_module_exit);
6582
6583 MODULE_LICENSE("Dual BSD/GPL");
6584 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
6585 MODULE_DESCRIPTION("Mellanox Spectrum driver");
6586 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
6587 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
6588 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table);
6589 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);