drivers/net/ethernet/mellanox/mlxsw/pci

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   1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3 
   4 #ifndef _MLXSW_PCI_HW_H
   5 #define _MLXSW_PCI_HW_H
   6 
   7 #include <linux/bitops.h>
   8 
   9 #include "item.h"
  10 
  11 #define MLXSW_PCI_BAR0_SIZE             (1024 * 1024) /* 1MB */
  12 #define MLXSW_PCI_PAGE_SIZE             4096
  13 
  14 #define MLXSW_PCI_CIR_BASE                      0x71000
  15 #define MLXSW_PCI_CIR_IN_PARAM_HI               MLXSW_PCI_CIR_BASE
  16 #define MLXSW_PCI_CIR_IN_PARAM_LO               (MLXSW_PCI_CIR_BASE + 0x04)
  17 #define MLXSW_PCI_CIR_IN_MODIFIER               (MLXSW_PCI_CIR_BASE + 0x08)
  18 #define MLXSW_PCI_CIR_OUT_PARAM_HI              (MLXSW_PCI_CIR_BASE + 0x0C)
  19 #define MLXSW_PCI_CIR_OUT_PARAM_LO              (MLXSW_PCI_CIR_BASE + 0x10)
  20 #define MLXSW_PCI_CIR_TOKEN                     (MLXSW_PCI_CIR_BASE + 0x14)
  21 #define MLXSW_PCI_CIR_CTRL                      (MLXSW_PCI_CIR_BASE + 0x18)
  22 #define MLXSW_PCI_CIR_CTRL_GO_BIT               BIT(23)
  23 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT            BIT(22)
  24 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT     12
  25 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT         24
  26 #define MLXSW_PCI_CIR_TIMEOUT_MSECS             1000
  27 
  28 #define MLXSW_PCI_SW_RESET                      0xF0010
  29 #define MLXSW_PCI_SW_RESET_RST_BIT              BIT(0)
  30 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS        20000
  31 #define MLXSW_PCI_SW_RESET_WAIT_MSECS           100
  32 #define MLXSW_PCI_FW_READY                      0xA1844
  33 #define MLXSW_PCI_FW_READY_MASK                 0xFFFF
  34 #define MLXSW_PCI_FW_READY_MAGIC                0x5E
  35 
  36 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET           0x000
  37 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET           0x200
  38 #define MLXSW_PCI_DOORBELL_CQ_OFFSET            0x400
  39 #define MLXSW_PCI_DOORBELL_EQ_OFFSET            0x600
  40 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET        0x800
  41 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET        0xA00
  42 
  43 #define MLXSW_PCI_DOORBELL(offset, type_offset, num)    \
  44         ((offset) + (type_offset) + (num) * 4)
  45 
  46 #define MLXSW_PCI_FREE_RUNNING_CLOCK_H(offset)  (offset)
  47 #define MLXSW_PCI_FREE_RUNNING_CLOCK_L(offset)  ((offset) + 4)
  48 
  49 #define MLXSW_PCI_CQS_MAX       96
  50 #define MLXSW_PCI_EQS_COUNT     2
  51 #define MLXSW_PCI_EQ_ASYNC_NUM  0
  52 #define MLXSW_PCI_EQ_COMP_NUM   1
  53 
  54 #define MLXSW_PCI_AQ_PAGES      8
  55 #define MLXSW_PCI_AQ_SIZE       (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
  56 #define MLXSW_PCI_WQE_SIZE      32 /* 32 bytes per element */
  57 #define MLXSW_PCI_CQE01_SIZE    16 /* 16 bytes per element */
  58 #define MLXSW_PCI_CQE2_SIZE     32 /* 32 bytes per element */
  59 #define MLXSW_PCI_CQE_SIZE_MAX  MLXSW_PCI_CQE2_SIZE
  60 #define MLXSW_PCI_EQE_SIZE      16 /* 16 bytes per element */
  61 #define MLXSW_PCI_WQE_COUNT     (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
  62 #define MLXSW_PCI_CQE01_COUNT   (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE)
  63 #define MLXSW_PCI_CQE2_COUNT    (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE)
  64 #define MLXSW_PCI_EQE_COUNT     (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
  65 #define MLXSW_PCI_EQE_UPDATE_COUNT      0x80
  66 
  67 #define MLXSW_PCI_WQE_SG_ENTRIES        3
  68 #define MLXSW_PCI_WQE_TYPE_ETHERNET     0xA
  69 
  70 /* pci_wqe_c
  71  * If set it indicates that a completion should be reported upon
  72  * execution of this descriptor.
  73  */
  74 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
  75 
  76 /* pci_wqe_lp
  77  * Local Processing, set if packet should be processed by the local
  78  * switch hardware:
  79  * For Ethernet EMAD (Direct Route and non Direct Route) -
  80  * must be set if packet destination is local device
  81  * For InfiniBand CTL - must be set if packet destination is local device
  82  * Otherwise it must be clear
  83  * Local Process packets must not exceed the size of 2K (including payload
  84  * and headers).
  85  */
  86 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
  87 
  88 /* pci_wqe_type
  89  * Packet type.
  90  */
  91 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
  92 
  93 /* pci_wqe_byte_count
  94  * Size of i-th scatter/gather entry, 0 if entry is unused.
  95  */
  96 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
  97 
  98 /* pci_wqe_address
  99  * Physical address of i-th scatter/gather entry.
 100  * Gather Entries must be 2Byte aligned.
 101  */
 102 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
 103 
 104 enum mlxsw_pci_cqe_v {
 105         MLXSW_PCI_CQE_V0,
 106         MLXSW_PCI_CQE_V1,
 107         MLXSW_PCI_CQE_V2,
 108 };
 109 
 110 #define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2)                            \
 111 static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \
 112 {                                                                               \
 113         switch (v) {                                                            \
 114         default:                                                                \
 115         case MLXSW_PCI_CQE_V0:                                                  \
 116                 return mlxsw_pci_cqe##v0##_##name##_get(cqe);                   \
 117         case MLXSW_PCI_CQE_V1:                                                  \
 118                 return mlxsw_pci_cqe##v1##_##name##_get(cqe);                   \
 119         case MLXSW_PCI_CQE_V2:                                                  \
 120                 return mlxsw_pci_cqe##v2##_##name##_get(cqe);                   \
 121         }                                                                       \
 122 }                                                                               \
 123 static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v,           \
 124                                               char *cqe, u32 val)               \
 125 {                                                                               \
 126         switch (v) {                                                            \
 127         default:                                                                \
 128         case MLXSW_PCI_CQE_V0:                                                  \
 129                 mlxsw_pci_cqe##v0##_##name##_set(cqe, val);                     \
 130                 break;                                                          \
 131         case MLXSW_PCI_CQE_V1:                                                  \
 132                 mlxsw_pci_cqe##v1##_##name##_set(cqe, val);                     \
 133                 break;                                                          \
 134         case MLXSW_PCI_CQE_V2:                                                  \
 135                 mlxsw_pci_cqe##v2##_##name##_set(cqe, val);                     \
 136                 break;                                                          \
 137         }                                                                       \
 138 }
 139 
 140 /* pci_cqe_lag
 141  * Packet arrives from a port which is a LAG
 142  */
 143 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
 144 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
 145 mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);
 146 
 147 /* pci_cqe_system_port/lag_id
 148  * When lag=0: System port on which the packet was received
 149  * When lag=1:
 150  * bits [15:4] LAG ID on which the packet was received
 151  * bits [3:0] sub_port on which the packet was received
 152  */
 153 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
 154 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
 155 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
 156 mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
 157 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
 158 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
 159 mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);
 160 
 161 /* pci_cqe_wqe_counter
 162  * WQE count of the WQEs completed on the associated dqn
 163  */
 164 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
 165 
 166 /* pci_cqe_byte_count
 167  * Byte count of received packets including additional two
 168  * Reserved Bytes that are append to the end of the frame.
 169  * Reserved for Send CQE.
 170  */
 171 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
 172 
 173 /* pci_cqe_trap_id
 174  * Trap ID that captured the packet.
 175  */
 176 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);
 177 
 178 /* pci_cqe_crc
 179  * Length include CRC. Indicates the length field includes
 180  * the packet's CRC.
 181  */
 182 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
 183 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
 184 mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);
 185 
 186 /* pci_cqe_e
 187  * CQE with Error.
 188  */
 189 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
 190 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
 191 mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);
 192 
 193 /* pci_cqe_sr
 194  * 1 - Send Queue
 195  * 0 - Receive Queue
 196  */
 197 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
 198 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
 199 mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);
 200 
 201 /* pci_cqe_dqn
 202  * Descriptor Queue (DQ) Number.
 203  */
 204 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
 205 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
 206 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
 207 
 208 /* pci_cqe_owner
 209  * Ownership bit.
 210  */
 211 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
 212 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
 213 mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2);
 214 
 215 /* pci_eqe_event_type
 216  * Event type.
 217  */
 218 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
 219 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP   0x00
 220 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD    0x0A
 221 
 222 /* pci_eqe_event_sub_type
 223  * Event type.
 224  */
 225 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
 226 
 227 /* pci_eqe_cqn
 228  * Completion Queue that triggered this EQE.
 229  */
 230 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
 231 
 232 /* pci_eqe_owner
 233  * Ownership bit.
 234  */
 235 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
 236 
 237 /* pci_eqe_cmd_token
 238  * Command completion event - token
 239  */
 240 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
 241 
 242 /* pci_eqe_cmd_status
 243  * Command completion event - status
 244  */
 245 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
 246 
 247 /* pci_eqe_cmd_out_param_h
 248  * Command completion event - output parameter - higher part
 249  */
 250 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
 251 
 252 /* pci_eqe_cmd_out_param_l
 253  * Command completion event - output parameter - lower part
 254  */
 255 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);
 256 
 257 #endif
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root/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h

INCLUDED FROM
