This source file includes following definitions.
- mlxsw_sx_txhdr_construct
- mlxsw_sx_port_admin_status_set
- mlxsw_sx_port_oper_status_get
- __mlxsw_sx_port_mtu_set
- mlxsw_sx_port_mtu_eth_set
- mlxsw_sx_port_mtu_ib_set
- mlxsw_sx_port_ib_port_set
- mlxsw_sx_port_swid_set
- mlxsw_sx_port_system_port_mapping_set
- mlxsw_sx_port_module_info_get
- mlxsw_sx_port_open
- mlxsw_sx_port_stop
- mlxsw_sx_port_xmit
- mlxsw_sx_port_change_mtu
- mlxsw_sx_port_get_stats64
- mlxsw_sx_port_get_devlink_port
- mlxsw_sx_port_get_drvinfo
- mlxsw_sx_port_get_strings
- mlxsw_sx_port_get_stats
- mlxsw_sx_port_get_sset_count
- mlxsw_sx_from_ptys_supported_port
- mlxsw_sx_from_ptys_supported_link
- mlxsw_sx_from_ptys_advert_link
- mlxsw_sx_from_ptys_speed_duplex
- mlxsw_sx_port_connector_port
- mlxsw_sx_port_get_link_ksettings
- mlxsw_sx_to_ptys_advert_link
- mlxsw_sx_to_ptys_speed
- mlxsw_sx_to_ptys_upper_speed
- mlxsw_sx_port_set_link_ksettings
- mlxsw_sx_hw_id_get
- mlxsw_sx_port_dev_addr_get
- mlxsw_sx_port_stp_state_set
- mlxsw_sx_port_ib_speed_set
- mlxsw_sx_port_speed_by_width_set
- mlxsw_sx_port_mac_learning_mode_set
- __mlxsw_sx_port_eth_create
- mlxsw_sx_port_eth_create
- __mlxsw_sx_port_eth_remove
- mlxsw_sx_port_created
- __mlxsw_sx_port_ib_create
- __mlxsw_sx_port_ib_remove
- __mlxsw_sx_port_remove
- mlxsw_sx_port_remove
- mlxsw_sx_ports_remove
- mlxsw_sx_ports_create
- mlxsw_sx_pude_eth_event_func
- mlxsw_sx_pude_ib_event_func
- mlxsw_sx_pude_event_func
- mlxsw_sx_rx_listener_func
- mlxsw_sx_port_type_set
- mlxsw_sx_traps_init
- mlxsw_sx_traps_fini
- mlxsw_sx_flood_init
- mlxsw_sx_basic_trap_groups_set
- mlxsw_sx_init
- mlxsw_sx_fini
- mlxsw_sx_module_init
- mlxsw_sx_module_exit
1
2
3
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
7 #include <linux/pci.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/slab.h>
11 #include <linux/device.h>
12 #include <linux/skbuff.h>
13 #include <linux/if_vlan.h>
14
15 #include "pci.h"
16 #include "core.h"
17 #include "reg.h"
18 #include "port.h"
19 #include "trap.h"
20 #include "txheader.h"
21 #include "ib.h"
22
23 static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
24 static const char mlxsw_sx_driver_version[] = "1.0";
25
26 struct mlxsw_sx_port;
27
28 struct mlxsw_sx {
29 struct mlxsw_sx_port **ports;
30 struct mlxsw_core *core;
31 const struct mlxsw_bus_info *bus_info;
32 u8 hw_id[ETH_ALEN];
33 };
34
35 struct mlxsw_sx_port_pcpu_stats {
36 u64 rx_packets;
37 u64 rx_bytes;
38 u64 tx_packets;
39 u64 tx_bytes;
40 struct u64_stats_sync syncp;
41 u32 tx_dropped;
42 };
43
44 struct mlxsw_sx_port {
45 struct net_device *dev;
46 struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
47 struct mlxsw_sx *mlxsw_sx;
48 u8 local_port;
49 struct {
50 u8 module;
51 } mapping;
52 };
53
54
55
56
57
58 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
59
60
61
62
63
64
65 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
66
67
68
69
70 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
71
72
73
74
75
76
77 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
78
79
80
81
82 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
83
84
85
86
87
88
89
90
91
92 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
93
94
95
96
97 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
98
99
100
101
102
103 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
104
105
106
107
108 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
109
110
111
112
113 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
114
115
116
117
118 MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
119
120
121
122
123 MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
124
125
126
127
128
129 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
130
131 static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
132 const struct mlxsw_tx_info *tx_info)
133 {
134 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
135 bool is_emad = tx_info->is_emad;
136
137 memset(txhdr, 0, MLXSW_TXHDR_LEN);
138
139
140 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
141 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
142 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
143 mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
144 MLXSW_TXHDR_ETCLASS_5);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
147 mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
148 mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
149 MLXSW_TXHDR_RDQ_OTHER);
150 mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
151 mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
152 mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
153 mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
154 MLXSW_TXHDR_NOT_EMAD);
155 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
156 }
157
158 static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
159 bool is_up)
160 {
161 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
162 char paos_pl[MLXSW_REG_PAOS_LEN];
163
164 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
165 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
166 MLXSW_PORT_ADMIN_STATUS_DOWN);
167 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
168 }
169
170 static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
171 bool *p_is_up)
172 {
173 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
174 char paos_pl[MLXSW_REG_PAOS_LEN];
175 u8 oper_status;
176 int err;
177
178 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
179 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
180 if (err)
181 return err;
182 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
183 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
184 return 0;
185 }
186
187 static int __mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port,
188 u16 mtu)
189 {
190 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
191 char pmtu_pl[MLXSW_REG_PMTU_LEN];
192 int max_mtu;
193 int err;
194
195 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
196 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
197 if (err)
198 return err;
199 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
200
201 if (mtu > max_mtu)
202 return -EINVAL;
203
204 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
205 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
206 }
207
208 static int mlxsw_sx_port_mtu_eth_set(struct mlxsw_sx_port *mlxsw_sx_port,
209 u16 mtu)
210 {
211 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
212 return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
213 }
214
215 static int mlxsw_sx_port_mtu_ib_set(struct mlxsw_sx_port *mlxsw_sx_port,
216 u16 mtu)
217 {
218 return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
219 }
220
221 static int mlxsw_sx_port_ib_port_set(struct mlxsw_sx_port *mlxsw_sx_port,
222 u8 ib_port)
223 {
224 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
225 char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
226 int err;
227
228 mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sx_port->local_port);
229 mlxsw_reg_plib_ib_port_set(plib_pl, ib_port);
230 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(plib), plib_pl);
231 return err;
232 }
233
234 static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
235 {
236 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
237 char pspa_pl[MLXSW_REG_PSPA_LEN];
238
239 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
240 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
241 }
242
243 static int
244 mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
245 {
246 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
247 char sspr_pl[MLXSW_REG_SSPR_LEN];
248
249 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
250 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
251 }
252
253 static int mlxsw_sx_port_module_info_get(struct mlxsw_sx *mlxsw_sx,
254 u8 local_port, u8 *p_module,
255 u8 *p_width)
256 {
257 char pmlp_pl[MLXSW_REG_PMLP_LEN];
258 int err;
259
260 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
261 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
262 if (err)
263 return err;
264 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
265 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
266 return 0;
267 }
268
269 static int mlxsw_sx_port_open(struct net_device *dev)
270 {
271 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
272 int err;
273
274 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
275 if (err)
276 return err;
277 netif_start_queue(dev);
278 return 0;
279 }
280
281 static int mlxsw_sx_port_stop(struct net_device *dev)
282 {
283 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
284
285 netif_stop_queue(dev);
286 return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
287 }
288
289 static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
290 struct net_device *dev)
291 {
292 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
293 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
294 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
295 const struct mlxsw_tx_info tx_info = {
296 .local_port = mlxsw_sx_port->local_port,
297 .is_emad = false,
298 };
299 u64 len;
300 int err;
301
302 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
303 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
304 dev_kfree_skb_any(skb);
305 return NETDEV_TX_OK;
306 }
307
308 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
309
310 if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
311 return NETDEV_TX_BUSY;
312
313 mlxsw_sx_txhdr_construct(skb, &tx_info);
314
315
316
317 len = skb->len - MLXSW_TXHDR_LEN;
318
319
320
321 err = mlxsw_core_skb_transmit(mlxsw_sx->core, skb, &tx_info);
322
323 if (!err) {
324 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
325 u64_stats_update_begin(&pcpu_stats->syncp);
326 pcpu_stats->tx_packets++;
327 pcpu_stats->tx_bytes += len;
328 u64_stats_update_end(&pcpu_stats->syncp);
329 } else {
330 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
331 dev_kfree_skb_any(skb);
332 }
333 return NETDEV_TX_OK;
334 }
335
336 static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
337 {
338 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
339 int err;
340
341 err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, mtu);
342 if (err)
343 return err;
344 dev->mtu = mtu;
345 return 0;
346 }
347
348 static void
349 mlxsw_sx_port_get_stats64(struct net_device *dev,
350 struct rtnl_link_stats64 *stats)
351 {
352 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
353 struct mlxsw_sx_port_pcpu_stats *p;
354 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
355 u32 tx_dropped = 0;
356 unsigned int start;
357 int i;
358
359 for_each_possible_cpu(i) {
360 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
361 do {
362 start = u64_stats_fetch_begin_irq(&p->syncp);
363 rx_packets = p->rx_packets;
364 rx_bytes = p->rx_bytes;
365 tx_packets = p->tx_packets;
366 tx_bytes = p->tx_bytes;
367 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
368
369 stats->rx_packets += rx_packets;
370 stats->rx_bytes += rx_bytes;
371 stats->tx_packets += tx_packets;
372 stats->tx_bytes += tx_bytes;
373
374 tx_dropped += p->tx_dropped;
375 }
376 stats->tx_dropped = tx_dropped;
377 }
378
379 static struct devlink_port *
380 mlxsw_sx_port_get_devlink_port(struct net_device *dev)
381 {
382 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
383 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
384
385 return mlxsw_core_port_devlink_port_get(mlxsw_sx->core,
386 mlxsw_sx_port->local_port);
387 }
388
389 static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
390 .ndo_open = mlxsw_sx_port_open,
391 .ndo_stop = mlxsw_sx_port_stop,
392 .ndo_start_xmit = mlxsw_sx_port_xmit,
393 .ndo_change_mtu = mlxsw_sx_port_change_mtu,
394 .ndo_get_stats64 = mlxsw_sx_port_get_stats64,
395 .ndo_get_devlink_port = mlxsw_sx_port_get_devlink_port,
396 };
397
398 static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
399 struct ethtool_drvinfo *drvinfo)
400 {
401 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
402 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
403
404 strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
405 strlcpy(drvinfo->version, mlxsw_sx_driver_version,
406 sizeof(drvinfo->version));
407 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
408 "%d.%d.%d",
409 mlxsw_sx->bus_info->fw_rev.major,
410 mlxsw_sx->bus_info->fw_rev.minor,
411 mlxsw_sx->bus_info->fw_rev.subminor);
412 strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
413 sizeof(drvinfo->bus_info));
414 }
415
416 struct mlxsw_sx_port_hw_stats {
417 char str[ETH_GSTRING_LEN];
418 u64 (*getter)(const char *payload);
419 };
420
421 static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
422 {
423 .str = "a_frames_transmitted_ok",
424 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
425 },
426 {
427 .str = "a_frames_received_ok",
428 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
429 },
430 {
431 .str = "a_frame_check_sequence_errors",
432 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
433 },
434 {
435 .str = "a_alignment_errors",
436 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
437 },
438 {
439 .str = "a_octets_transmitted_ok",
440 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
441 },
442 {
443 .str = "a_octets_received_ok",
444 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
445 },
446 {
447 .str = "a_multicast_frames_xmitted_ok",
448 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
449 },
450 {
451 .str = "a_broadcast_frames_xmitted_ok",
452 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
453 },
454 {
455 .str = "a_multicast_frames_received_ok",
456 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
457 },
458 {
459 .str = "a_broadcast_frames_received_ok",
460 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
461 },
462 {
463 .str = "a_in_range_length_errors",
464 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
465 },
466 {
467 .str = "a_out_of_range_length_field",
468 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
469 },
470 {
471 .str = "a_frame_too_long_errors",
472 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
473 },
474 {
475 .str = "a_symbol_error_during_carrier",
476 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
477 },
478 {
479 .str = "a_mac_control_frames_transmitted",
480 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
481 },
482 {
483 .str = "a_mac_control_frames_received",
484 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
485 },
486 {
487 .str = "a_unsupported_opcodes_received",
488 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
489 },
490 {
491 .str = "a_pause_mac_ctrl_frames_received",
492 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
493 },
494 {
495 .str = "a_pause_mac_ctrl_frames_xmitted",
496 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
497 },
498 };
499
500 #define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
501
502 static void mlxsw_sx_port_get_strings(struct net_device *dev,
503 u32 stringset, u8 *data)
504 {
505 u8 *p = data;
506 int i;
507
508 switch (stringset) {
509 case ETH_SS_STATS:
510 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
511 memcpy(p, mlxsw_sx_port_hw_stats[i].str,
512 ETH_GSTRING_LEN);
513 p += ETH_GSTRING_LEN;
514 }
515 break;
516 }
517 }
518
519 static void mlxsw_sx_port_get_stats(struct net_device *dev,
520 struct ethtool_stats *stats, u64 *data)
521 {
522 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
523 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
524 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
525 int i;
526 int err;
527
528 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port,
529 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
530 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
531 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
532 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
533 }
534
535 static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
536 {
537 switch (sset) {
538 case ETH_SS_STATS:
539 return MLXSW_SX_PORT_HW_STATS_LEN;
540 default:
541 return -EOPNOTSUPP;
542 }
543 }
544
545 struct mlxsw_sx_port_link_mode {
546 u32 mask;
547 u32 supported;
548 u32 advertised;
549 u32 speed;
550 };
551
552 static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
553 {
554 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
555 .supported = SUPPORTED_100baseT_Full,
556 .advertised = ADVERTISED_100baseT_Full,
557 .speed = 100,
558 },
559 {
560 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
561 .speed = 100,
562 },
563 {
564 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
565 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
566 .supported = SUPPORTED_1000baseKX_Full,
567 .advertised = ADVERTISED_1000baseKX_Full,
568 .speed = 1000,
569 },
570 {
571 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
572 .supported = SUPPORTED_10000baseT_Full,
573 .advertised = ADVERTISED_10000baseT_Full,
574 .speed = 10000,
575 },
576 {
577 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
578 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
579 .supported = SUPPORTED_10000baseKX4_Full,
580 .advertised = ADVERTISED_10000baseKX4_Full,
581 .speed = 10000,
582 },
583 {
584 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
585 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
586 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
587 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
588 .supported = SUPPORTED_10000baseKR_Full,
589 .advertised = ADVERTISED_10000baseKR_Full,
590 .speed = 10000,
591 },
592 {
593 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
594 .supported = SUPPORTED_20000baseKR2_Full,
595 .advertised = ADVERTISED_20000baseKR2_Full,
596 .speed = 20000,
597 },
598 {
599 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
600 .supported = SUPPORTED_40000baseCR4_Full,
601 .advertised = ADVERTISED_40000baseCR4_Full,
602 .speed = 40000,
603 },
604 {
605 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
606 .supported = SUPPORTED_40000baseKR4_Full,
607 .advertised = ADVERTISED_40000baseKR4_Full,
608 .speed = 40000,
609 },
610 {
611 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
612 .supported = SUPPORTED_40000baseSR4_Full,
613 .advertised = ADVERTISED_40000baseSR4_Full,
614 .speed = 40000,
615 },
616 {
617 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
618 .supported = SUPPORTED_40000baseLR4_Full,
619 .advertised = ADVERTISED_40000baseLR4_Full,
620 .speed = 40000,
621 },
622 {
623 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
624 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
625 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
626 .speed = 25000,
627 },
628 {
629 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
630 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
631 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
632 .speed = 50000,
633 },
634 {
635 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
636 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
637 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
638 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
639 .speed = 100000,
640 },
641 };
642
643 #define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
644 #define MLXSW_SX_PORT_BASE_SPEED 10000
645
646 static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
647 {
648 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
649 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
650 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
651 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
652 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
653 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
654 return SUPPORTED_FIBRE;
655
656 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
657 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
658 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
659 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
660 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
661 return SUPPORTED_Backplane;
662 return 0;
663 }
664
665 static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
666 {
667 u32 modes = 0;
668 int i;
669
670 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
671 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
672 modes |= mlxsw_sx_port_link_mode[i].supported;
673 }
674 return modes;
675 }
676
677 static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
678 {
679 u32 modes = 0;
680 int i;
681
682 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
683 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
684 modes |= mlxsw_sx_port_link_mode[i].advertised;
685 }
686 return modes;
687 }
688
689 static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
690 struct ethtool_link_ksettings *cmd)
691 {
692 u32 speed = SPEED_UNKNOWN;
693 u8 duplex = DUPLEX_UNKNOWN;
694 int i;
695
696 if (!carrier_ok)
697 goto out;
698
699 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
700 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
701 speed = mlxsw_sx_port_link_mode[i].speed;
702 duplex = DUPLEX_FULL;
703 break;
704 }
705 }
706 out:
707 cmd->base.speed = speed;
708 cmd->base.duplex = duplex;
709 }
710
711 static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
712 {
713 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
714 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
715 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
716 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
717 return PORT_FIBRE;
718
719 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
720 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
721 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
722 return PORT_DA;
723
724 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
725 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
726 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
727 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
728 return PORT_NONE;
729
730 return PORT_OTHER;
731 }
732
733 static int
734 mlxsw_sx_port_get_link_ksettings(struct net_device *dev,
735 struct ethtool_link_ksettings *cmd)
736 {
737 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
738 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
739 char ptys_pl[MLXSW_REG_PTYS_LEN];
740 u32 eth_proto_cap;
741 u32 eth_proto_admin;
742 u32 eth_proto_oper;
743 u32 supported, advertising, lp_advertising;
744 int err;
745
746 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
747 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
748 if (err) {
749 netdev_err(dev, "Failed to get proto");
750 return err;
751 }
752 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap,
753 ð_proto_admin, ð_proto_oper);
754
755 supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
756 mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
757 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
758 advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
759 mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
760 eth_proto_oper, cmd);
761
762 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
763 cmd->base.port = mlxsw_sx_port_connector_port(eth_proto_oper);
764 lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
765
766 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
767 supported);
768 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
769 advertising);
770 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
771 lp_advertising);
772
773 return 0;
774 }
775
776 static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
777 {
778 u32 ptys_proto = 0;
779 int i;
780
781 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
782 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
783 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
784 }
785 return ptys_proto;
786 }
787
788 static u32 mlxsw_sx_to_ptys_speed(u32 speed)
789 {
790 u32 ptys_proto = 0;
791 int i;
792
793 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
794 if (speed == mlxsw_sx_port_link_mode[i].speed)
795 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
796 }
797 return ptys_proto;
798 }
799
800 static u32 mlxsw_sx_to_ptys_upper_speed(u32 upper_speed)
801 {
802 u32 ptys_proto = 0;
803 int i;
804
805 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
806 if (mlxsw_sx_port_link_mode[i].speed <= upper_speed)
807 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
808 }
809 return ptys_proto;
810 }
811
812 static int
813 mlxsw_sx_port_set_link_ksettings(struct net_device *dev,
814 const struct ethtool_link_ksettings *cmd)
815 {
816 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
817 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
818 char ptys_pl[MLXSW_REG_PTYS_LEN];
819 u32 speed;
820 u32 eth_proto_new;
821 u32 eth_proto_cap;
822 u32 eth_proto_admin;
823 u32 advertising;
824 bool is_up;
825 int err;
826
827 speed = cmd->base.speed;
828
829 ethtool_convert_link_mode_to_legacy_u32(&advertising,
830 cmd->link_modes.advertising);
831
832 eth_proto_new = cmd->base.autoneg == AUTONEG_ENABLE ?
833 mlxsw_sx_to_ptys_advert_link(advertising) :
834 mlxsw_sx_to_ptys_speed(speed);
835
836 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
837 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
838 if (err) {
839 netdev_err(dev, "Failed to get proto");
840 return err;
841 }
842 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin,
843 NULL);
844
845 eth_proto_new = eth_proto_new & eth_proto_cap;
846 if (!eth_proto_new) {
847 netdev_err(dev, "Not supported proto admin requested");
848 return -EINVAL;
849 }
850 if (eth_proto_new == eth_proto_admin)
851 return 0;
852
853 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
854 eth_proto_new, true);
855 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
856 if (err) {
857 netdev_err(dev, "Failed to set proto admin");
858 return err;
859 }
860
861 err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
862 if (err) {
863 netdev_err(dev, "Failed to get oper status");
864 return err;
865 }
866 if (!is_up)
867 return 0;
868
869 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
870 if (err) {
871 netdev_err(dev, "Failed to set admin status");
872 return err;
873 }
874
875 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
876 if (err) {
877 netdev_err(dev, "Failed to set admin status");
878 return err;
879 }
880
881 return 0;
882 }
883
884 static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
885 .get_drvinfo = mlxsw_sx_port_get_drvinfo,
886 .get_link = ethtool_op_get_link,
887 .get_strings = mlxsw_sx_port_get_strings,
888 .get_ethtool_stats = mlxsw_sx_port_get_stats,
889 .get_sset_count = mlxsw_sx_port_get_sset_count,
890 .get_link_ksettings = mlxsw_sx_port_get_link_ksettings,
891 .set_link_ksettings = mlxsw_sx_port_set_link_ksettings,
892 };
893
894 static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
895 {
896 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
897 int err;
898
899 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
900 if (err)
901 return err;
902 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
903 return 0;
904 }
905
906 static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
907 {
908 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
909 struct net_device *dev = mlxsw_sx_port->dev;
910 char ppad_pl[MLXSW_REG_PPAD_LEN];
911 int err;
912
913 mlxsw_reg_ppad_pack(ppad_pl, false, 0);
914 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
915 if (err)
916 return err;
917 mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
918
919
920
921
922 dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
923 return 0;
924 }
925
926 static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
927 u16 vid, enum mlxsw_reg_spms_state state)
928 {
929 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
930 char *spms_pl;
931 int err;
932
933 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
934 if (!spms_pl)
935 return -ENOMEM;
936 mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port);
937 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
938 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
939 kfree(spms_pl);
940 return err;
941 }
942
943 static int mlxsw_sx_port_ib_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
944 u16 speed, u16 width)
945 {
946 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
947 char ptys_pl[MLXSW_REG_PTYS_LEN];
948
949 mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sx_port->local_port, speed,
950 width);
951 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
952 }
953
954 static int
955 mlxsw_sx_port_speed_by_width_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 width)
956 {
957 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
958 u32 upper_speed = MLXSW_SX_PORT_BASE_SPEED * width;
959 char ptys_pl[MLXSW_REG_PTYS_LEN];
960 u32 eth_proto_admin;
961
962 eth_proto_admin = mlxsw_sx_to_ptys_upper_speed(upper_speed);
963 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
964 eth_proto_admin, true);
965 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
966 }
967
968 static int
969 mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
970 enum mlxsw_reg_spmlr_learn_mode mode)
971 {
972 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
973 char spmlr_pl[MLXSW_REG_SPMLR_LEN];
974
975 mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
976 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
977 }
978
979 static int __mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
980 u8 module, u8 width)
981 {
982 struct mlxsw_sx_port *mlxsw_sx_port;
983 struct net_device *dev;
984 int err;
985
986 dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
987 if (!dev)
988 return -ENOMEM;
989 SET_NETDEV_DEV(dev, mlxsw_sx->bus_info->dev);
990 mlxsw_sx_port = netdev_priv(dev);
991 mlxsw_sx_port->dev = dev;
992 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
993 mlxsw_sx_port->local_port = local_port;
994 mlxsw_sx_port->mapping.module = module;
995
996 mlxsw_sx_port->pcpu_stats =
997 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
998 if (!mlxsw_sx_port->pcpu_stats) {
999 err = -ENOMEM;
1000 goto err_alloc_stats;
1001 }
1002
1003 dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
1004 dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
1005
1006 err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
1007 if (err) {
1008 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
1009 mlxsw_sx_port->local_port);
1010 goto err_dev_addr_get;
1011 }
1012
1013 netif_carrier_off(dev);
1014
1015 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1016 NETIF_F_VLAN_CHALLENGED;
1017
1018 dev->min_mtu = 0;
1019 dev->max_mtu = ETH_MAX_MTU;
1020
1021
1022
1023
1024 dev->needed_headroom = MLXSW_TXHDR_LEN;
1025
1026 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1027 if (err) {
1028 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1029 mlxsw_sx_port->local_port);
1030 goto err_port_system_port_mapping_set;
1031 }
1032
1033 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1034 if (err) {
1035 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1036 mlxsw_sx_port->local_port);
1037 goto err_port_swid_set;
1038 }
1039
1040 err = mlxsw_sx_port_speed_by_width_set(mlxsw_sx_port, width);
1041 if (err) {
1042 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1043 mlxsw_sx_port->local_port);
1044 goto err_port_speed_set;
1045 }
1046
1047 err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, ETH_DATA_LEN);
1048 if (err) {
1049 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1050 mlxsw_sx_port->local_port);
1051 goto err_port_mtu_set;
1052 }
1053
1054 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1055 if (err)
1056 goto err_port_admin_status_set;
1057
1058 err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1059 MLXSW_PORT_DEFAULT_VID,
1060 MLXSW_REG_SPMS_STATE_FORWARDING);
1061 if (err) {
1062 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1063 mlxsw_sx_port->local_port);
1064 goto err_port_stp_state_set;
1065 }
1066
1067 err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1068 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1069 if (err) {
1070 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1071 mlxsw_sx_port->local_port);
1072 goto err_port_mac_learning_mode_set;
1073 }
1074
1075 err = register_netdev(dev);
1076 if (err) {
1077 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1078 mlxsw_sx_port->local_port);
1079 goto err_register_netdev;
1080 }
1081
1082 mlxsw_core_port_eth_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1083 mlxsw_sx_port, dev);
1084 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1085 return 0;
1086
1087 err_register_netdev:
1088 err_port_mac_learning_mode_set:
1089 err_port_stp_state_set:
1090 err_port_admin_status_set:
1091 err_port_mtu_set:
1092 err_port_speed_set:
1093 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1094 err_port_swid_set:
1095 err_port_system_port_mapping_set:
1096 err_dev_addr_get:
1097 free_percpu(mlxsw_sx_port->pcpu_stats);
1098 err_alloc_stats:
1099 free_netdev(dev);
1100 return err;
1101 }
1102
1103 static int mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1104 u8 module, u8 width)
1105 {
1106 int err;
1107
1108 err = mlxsw_core_port_init(mlxsw_sx->core, local_port,
1109 module + 1, false, 0,
1110 mlxsw_sx->hw_id, sizeof(mlxsw_sx->hw_id));
1111 if (err) {
1112 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to init core port\n",
1113 local_port);
1114 return err;
1115 }
1116 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module, width);
1117 if (err)
1118 goto err_port_create;
1119
1120 return 0;
1121
1122 err_port_create:
1123 mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1124 return err;
1125 }
1126
1127 static void __mlxsw_sx_port_eth_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1128 {
1129 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1130
1131 mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1132 unregister_netdev(mlxsw_sx_port->dev);
1133 mlxsw_sx->ports[local_port] = NULL;
1134 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1135 free_percpu(mlxsw_sx_port->pcpu_stats);
1136 free_netdev(mlxsw_sx_port->dev);
1137 }
1138
1139 static bool mlxsw_sx_port_created(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1140 {
1141 return mlxsw_sx->ports[local_port] != NULL;
1142 }
1143
1144 static int __mlxsw_sx_port_ib_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1145 u8 module, u8 width)
1146 {
1147 struct mlxsw_sx_port *mlxsw_sx_port;
1148 int err;
1149
1150 mlxsw_sx_port = kzalloc(sizeof(*mlxsw_sx_port), GFP_KERNEL);
1151 if (!mlxsw_sx_port)
1152 return -ENOMEM;
1153 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
1154 mlxsw_sx_port->local_port = local_port;
1155 mlxsw_sx_port->mapping.module = module;
1156
1157 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1158 if (err) {
1159 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1160 mlxsw_sx_port->local_port);
1161 goto err_port_system_port_mapping_set;
1162 }
1163
1164
1165 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 1);
1166 if (err) {
1167 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1168 mlxsw_sx_port->local_port);
1169 goto err_port_swid_set;
1170 }
1171
1172
1173 err = mlxsw_sx_port_ib_port_set(mlxsw_sx_port, module + 1);
1174 if (err) {
1175 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set IB port\n",
1176 mlxsw_sx_port->local_port);
1177 goto err_port_ib_set;
1178 }
1179
1180
1181
1182
1183 err = mlxsw_sx_port_ib_speed_set(mlxsw_sx_port,
1184 MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
1185 BIT(3) - 1);
1186 if (err) {
1187 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1188 mlxsw_sx_port->local_port);
1189 goto err_port_speed_set;
1190 }
1191
1192
1193
1194
1195 err = mlxsw_sx_port_mtu_ib_set(mlxsw_sx_port, MLXSW_IB_DEFAULT_MTU);
1196 if (err) {
1197 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1198 mlxsw_sx_port->local_port);
1199 goto err_port_mtu_set;
1200 }
1201
1202 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
1203 if (err) {
1204 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
1205 mlxsw_sx_port->local_port);
1206 goto err_port_admin_set;
1207 }
1208
1209 mlxsw_core_port_ib_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1210 mlxsw_sx_port);
1211 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1212 return 0;
1213
1214 err_port_admin_set:
1215 err_port_mtu_set:
1216 err_port_speed_set:
1217 err_port_ib_set:
1218 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1219 err_port_swid_set:
1220 err_port_system_port_mapping_set:
1221 kfree(mlxsw_sx_port);
1222 return err;
1223 }
1224
1225 static void __mlxsw_sx_port_ib_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1226 {
1227 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1228
1229 mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1230 mlxsw_sx->ports[local_port] = NULL;
1231 mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1232 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1233 kfree(mlxsw_sx_port);
1234 }
1235
1236 static void __mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1237 {
1238 enum devlink_port_type port_type =
1239 mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1240
1241 if (port_type == DEVLINK_PORT_TYPE_ETH)
1242 __mlxsw_sx_port_eth_remove(mlxsw_sx, local_port);
1243 else if (port_type == DEVLINK_PORT_TYPE_IB)
1244 __mlxsw_sx_port_ib_remove(mlxsw_sx, local_port);
1245 }
1246
1247 static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1248 {
1249 __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1250 mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1251 }
1252
1253 static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1254 {
1255 int i;
1256
1257 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sx->core); i++)
1258 if (mlxsw_sx_port_created(mlxsw_sx, i))
1259 mlxsw_sx_port_remove(mlxsw_sx, i);
1260 kfree(mlxsw_sx->ports);
1261 mlxsw_sx->ports = NULL;
1262 }
1263
1264 static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1265 {
1266 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sx->core);
1267 size_t alloc_size;
1268 u8 module, width;
1269 int i;
1270 int err;
1271
1272 alloc_size = sizeof(struct mlxsw_sx_port *) * max_ports;
1273 mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1274 if (!mlxsw_sx->ports)
1275 return -ENOMEM;
1276
1277 for (i = 1; i < max_ports; i++) {
1278 err = mlxsw_sx_port_module_info_get(mlxsw_sx, i, &module,
1279 &width);
1280 if (err)
1281 goto err_port_module_info_get;
1282 if (!width)
1283 continue;
1284 err = mlxsw_sx_port_eth_create(mlxsw_sx, i, module, width);
1285 if (err)
1286 goto err_port_create;
1287 }
1288 return 0;
1289
1290 err_port_create:
1291 err_port_module_info_get:
1292 for (i--; i >= 1; i--)
1293 if (mlxsw_sx_port_created(mlxsw_sx, i))
1294 mlxsw_sx_port_remove(mlxsw_sx, i);
1295 kfree(mlxsw_sx->ports);
1296 mlxsw_sx->ports = NULL;
1297 return err;
1298 }
1299
1300 static void mlxsw_sx_pude_eth_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1301 enum mlxsw_reg_pude_oper_status status)
1302 {
1303 if (status == MLXSW_PORT_OPER_STATUS_UP) {
1304 netdev_info(mlxsw_sx_port->dev, "link up\n");
1305 netif_carrier_on(mlxsw_sx_port->dev);
1306 } else {
1307 netdev_info(mlxsw_sx_port->dev, "link down\n");
1308 netif_carrier_off(mlxsw_sx_port->dev);
1309 }
1310 }
1311
1312 static void mlxsw_sx_pude_ib_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1313 enum mlxsw_reg_pude_oper_status status)
1314 {
1315 if (status == MLXSW_PORT_OPER_STATUS_UP)
1316 pr_info("ib link for port %d - up\n",
1317 mlxsw_sx_port->mapping.module + 1);
1318 else
1319 pr_info("ib link for port %d - down\n",
1320 mlxsw_sx_port->mapping.module + 1);
1321 }
1322
1323 static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1324 char *pude_pl, void *priv)
1325 {
1326 struct mlxsw_sx *mlxsw_sx = priv;
1327 struct mlxsw_sx_port *mlxsw_sx_port;
1328 enum mlxsw_reg_pude_oper_status status;
1329 enum devlink_port_type port_type;
1330 u8 local_port;
1331
1332 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1333 mlxsw_sx_port = mlxsw_sx->ports[local_port];
1334 if (!mlxsw_sx_port) {
1335 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1336 local_port);
1337 return;
1338 }
1339
1340 status = mlxsw_reg_pude_oper_status_get(pude_pl);
1341 port_type = mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1342 if (port_type == DEVLINK_PORT_TYPE_ETH)
1343 mlxsw_sx_pude_eth_event_func(mlxsw_sx_port, status);
1344 else if (port_type == DEVLINK_PORT_TYPE_IB)
1345 mlxsw_sx_pude_ib_event_func(mlxsw_sx_port, status);
1346 }
1347
1348 static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1349 void *priv)
1350 {
1351 struct mlxsw_sx *mlxsw_sx = priv;
1352 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1353 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1354
1355 if (unlikely(!mlxsw_sx_port)) {
1356 dev_warn_ratelimited(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1357 local_port);
1358 return;
1359 }
1360
1361 skb->dev = mlxsw_sx_port->dev;
1362
1363 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1364 u64_stats_update_begin(&pcpu_stats->syncp);
1365 pcpu_stats->rx_packets++;
1366 pcpu_stats->rx_bytes += skb->len;
1367 u64_stats_update_end(&pcpu_stats->syncp);
1368
1369 skb->protocol = eth_type_trans(skb, skb->dev);
1370 netif_receive_skb(skb);
1371 }
1372
1373 static int mlxsw_sx_port_type_set(struct mlxsw_core *mlxsw_core, u8 local_port,
1374 enum devlink_port_type new_type)
1375 {
1376 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1377 u8 module, width;
1378 int err;
1379
1380 if (!mlxsw_sx->ports || !mlxsw_sx->ports[local_port]) {
1381 dev_err(mlxsw_sx->bus_info->dev, "Port number \"%d\" does not exist\n",
1382 local_port);
1383 return -EINVAL;
1384 }
1385
1386 if (new_type == DEVLINK_PORT_TYPE_AUTO)
1387 return -EOPNOTSUPP;
1388
1389 __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1390 err = mlxsw_sx_port_module_info_get(mlxsw_sx, local_port, &module,
1391 &width);
1392 if (err)
1393 goto err_port_module_info_get;
1394
1395 if (new_type == DEVLINK_PORT_TYPE_ETH)
1396 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module,
1397 width);
1398 else if (new_type == DEVLINK_PORT_TYPE_IB)
1399 err = __mlxsw_sx_port_ib_create(mlxsw_sx, local_port, module,
1400 width);
1401
1402 err_port_module_info_get:
1403 return err;
1404 }
1405
1406 #define MLXSW_SX_RXL(_trap_id) \
1407 MLXSW_RXL(mlxsw_sx_rx_listener_func, _trap_id, TRAP_TO_CPU, \
1408 false, SX2_RX, FORWARD)
1409
1410 static const struct mlxsw_listener mlxsw_sx_listener[] = {
1411 MLXSW_EVENTL(mlxsw_sx_pude_event_func, PUDE, EMAD),
1412 MLXSW_SX_RXL(FDB_MC),
1413 MLXSW_SX_RXL(STP),
1414 MLXSW_SX_RXL(LACP),
1415 MLXSW_SX_RXL(EAPOL),
1416 MLXSW_SX_RXL(LLDP),
1417 MLXSW_SX_RXL(MMRP),
1418 MLXSW_SX_RXL(MVRP),
1419 MLXSW_SX_RXL(RPVST),
1420 MLXSW_SX_RXL(DHCP),
1421 MLXSW_SX_RXL(IGMP_QUERY),
1422 MLXSW_SX_RXL(IGMP_V1_REPORT),
1423 MLXSW_SX_RXL(IGMP_V2_REPORT),
1424 MLXSW_SX_RXL(IGMP_V2_LEAVE),
1425 MLXSW_SX_RXL(IGMP_V3_REPORT),
1426 };
1427
1428 static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1429 {
1430 char htgt_pl[MLXSW_REG_HTGT_LEN];
1431 int i;
1432 int err;
1433
1434 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
1435 MLXSW_REG_HTGT_INVALID_POLICER,
1436 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1437 MLXSW_REG_HTGT_DEFAULT_TC);
1438 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1439 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX);
1440
1441 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1442 if (err)
1443 return err;
1444
1445 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
1446 MLXSW_REG_HTGT_INVALID_POLICER,
1447 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1448 MLXSW_REG_HTGT_DEFAULT_TC);
1449 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1450 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL);
1451
1452 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1453 if (err)
1454 return err;
1455
1456 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1457 err = mlxsw_core_trap_register(mlxsw_sx->core,
1458 &mlxsw_sx_listener[i],
1459 mlxsw_sx);
1460 if (err)
1461 goto err_listener_register;
1462
1463 }
1464 return 0;
1465
1466 err_listener_register:
1467 for (i--; i >= 0; i--) {
1468 mlxsw_core_trap_unregister(mlxsw_sx->core,
1469 &mlxsw_sx_listener[i],
1470 mlxsw_sx);
1471 }
1472 return err;
1473 }
1474
1475 static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1476 {
1477 int i;
1478
1479 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1480 mlxsw_core_trap_unregister(mlxsw_sx->core,
1481 &mlxsw_sx_listener[i],
1482 mlxsw_sx);
1483 }
1484 }
1485
1486 static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1487 {
1488 char sfgc_pl[MLXSW_REG_SFGC_LEN];
1489 char sgcr_pl[MLXSW_REG_SGCR_LEN];
1490 char *sftr_pl;
1491 int err;
1492
1493
1494 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1495 if (!sftr_pl)
1496 return -ENOMEM;
1497 mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0,
1498 MLXSW_PORT_CPU_PORT, true);
1499 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1500 kfree(sftr_pl);
1501 if (err)
1502 return err;
1503
1504
1505 mlxsw_reg_sfgc_pack(sfgc_pl,
1506 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1507 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1508 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1509 0);
1510 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1511 if (err)
1512 return err;
1513
1514 mlxsw_reg_sfgc_pack(sfgc_pl,
1515 MLXSW_REG_SFGC_TYPE_BROADCAST,
1516 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1517 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1518 0);
1519 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1520 if (err)
1521 return err;
1522
1523 mlxsw_reg_sfgc_pack(sfgc_pl,
1524 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1525 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1526 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1527 0);
1528 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1529 if (err)
1530 return err;
1531
1532 mlxsw_reg_sfgc_pack(sfgc_pl,
1533 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1534 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1535 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1536 0);
1537 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1538 if (err)
1539 return err;
1540
1541 mlxsw_reg_sfgc_pack(sfgc_pl,
1542 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1543 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1544 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1545 0);
1546 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1547 if (err)
1548 return err;
1549
1550 mlxsw_reg_sgcr_pack(sgcr_pl, true);
1551 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1552 }
1553
1554 static int mlxsw_sx_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
1555 {
1556 char htgt_pl[MLXSW_REG_HTGT_LEN];
1557
1558 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
1559 MLXSW_REG_HTGT_INVALID_POLICER,
1560 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1561 MLXSW_REG_HTGT_DEFAULT_TC);
1562 mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
1563 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1564 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD);
1565 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
1566 }
1567
1568 static int mlxsw_sx_init(struct mlxsw_core *mlxsw_core,
1569 const struct mlxsw_bus_info *mlxsw_bus_info)
1570 {
1571 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1572 int err;
1573
1574 mlxsw_sx->core = mlxsw_core;
1575 mlxsw_sx->bus_info = mlxsw_bus_info;
1576
1577 err = mlxsw_sx_hw_id_get(mlxsw_sx);
1578 if (err) {
1579 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1580 return err;
1581 }
1582
1583 err = mlxsw_sx_ports_create(mlxsw_sx);
1584 if (err) {
1585 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1586 return err;
1587 }
1588
1589 err = mlxsw_sx_traps_init(mlxsw_sx);
1590 if (err) {
1591 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps\n");
1592 goto err_listener_register;
1593 }
1594
1595 err = mlxsw_sx_flood_init(mlxsw_sx);
1596 if (err) {
1597 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1598 goto err_flood_init;
1599 }
1600
1601 return 0;
1602
1603 err_flood_init:
1604 mlxsw_sx_traps_fini(mlxsw_sx);
1605 err_listener_register:
1606 mlxsw_sx_ports_remove(mlxsw_sx);
1607 return err;
1608 }
1609
1610 static void mlxsw_sx_fini(struct mlxsw_core *mlxsw_core)
1611 {
1612 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1613
1614 mlxsw_sx_traps_fini(mlxsw_sx);
1615 mlxsw_sx_ports_remove(mlxsw_sx);
1616 }
1617
1618 static const struct mlxsw_config_profile mlxsw_sx_config_profile = {
1619 .used_max_vepa_channels = 1,
1620 .max_vepa_channels = 0,
1621 .used_max_mid = 1,
1622 .max_mid = 7000,
1623 .used_max_pgt = 1,
1624 .max_pgt = 0,
1625 .used_max_system_port = 1,
1626 .max_system_port = 48000,
1627 .used_max_vlan_groups = 1,
1628 .max_vlan_groups = 127,
1629 .used_max_regions = 1,
1630 .max_regions = 400,
1631 .used_flood_tables = 1,
1632 .max_flood_tables = 2,
1633 .max_vid_flood_tables = 1,
1634 .used_flood_mode = 1,
1635 .flood_mode = 3,
1636 .used_max_ib_mc = 1,
1637 .max_ib_mc = 6,
1638 .used_max_pkey = 1,
1639 .max_pkey = 0,
1640 .swid_config = {
1641 {
1642 .used_type = 1,
1643 .type = MLXSW_PORT_SWID_TYPE_ETH,
1644 },
1645 {
1646 .used_type = 1,
1647 .type = MLXSW_PORT_SWID_TYPE_IB,
1648 }
1649 },
1650 };
1651
1652 static struct mlxsw_driver mlxsw_sx_driver = {
1653 .kind = mlxsw_sx_driver_name,
1654 .priv_size = sizeof(struct mlxsw_sx),
1655 .init = mlxsw_sx_init,
1656 .fini = mlxsw_sx_fini,
1657 .basic_trap_groups_set = mlxsw_sx_basic_trap_groups_set,
1658 .txhdr_construct = mlxsw_sx_txhdr_construct,
1659 .txhdr_len = MLXSW_TXHDR_LEN,
1660 .profile = &mlxsw_sx_config_profile,
1661 .port_type_set = mlxsw_sx_port_type_set,
1662 };
1663
1664 static const struct pci_device_id mlxsw_sx_pci_id_table[] = {
1665 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
1666 {0, },
1667 };
1668
1669 static struct pci_driver mlxsw_sx_pci_driver = {
1670 .name = mlxsw_sx_driver_name,
1671 .id_table = mlxsw_sx_pci_id_table,
1672 };
1673
1674 static int __init mlxsw_sx_module_init(void)
1675 {
1676 int err;
1677
1678 err = mlxsw_core_driver_register(&mlxsw_sx_driver);
1679 if (err)
1680 return err;
1681
1682 err = mlxsw_pci_driver_register(&mlxsw_sx_pci_driver);
1683 if (err)
1684 goto err_pci_driver_register;
1685
1686 return 0;
1687
1688 err_pci_driver_register:
1689 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1690 return err;
1691 }
1692
1693 static void __exit mlxsw_sx_module_exit(void)
1694 {
1695 mlxsw_pci_driver_unregister(&mlxsw_sx_pci_driver);
1696 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1697 }
1698
1699 module_init(mlxsw_sx_module_init);
1700 module_exit(mlxsw_sx_module_exit);
1701
1702 MODULE_LICENSE("Dual BSD/GPL");
1703 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1704 MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1705 MODULE_DEVICE_TABLE(pci, mlxsw_sx_pci_id_table);