drivers/net/ethernet/mellanox/mlxsw/reg.h

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
mlxsw_reg_sgcr_pack
mlxsw_reg_smid_pack
mlxsw_reg_sspr_pack
mlxsw_reg_sfdat_pack
mlxsw_reg_sfd_pack
mlxsw_reg_sfd_rec_pack
mlxsw_reg_sfd_uc_pack
mlxsw_reg_sfd_uc_unpack
mlxsw_reg_sfd_uc_lag_pack
mlxsw_reg_sfd_uc_lag_unpack
mlxsw_reg_sfd_mc_pack
mlxsw_reg_sfd_uc_tunnel_pack
mlxsw_reg_sfn_pack
mlxsw_reg_sfn_mac_unpack
mlxsw_reg_sfn_mac_lag_unpack
mlxsw_reg_sfn_uc_tunnel_unpack
mlxsw_reg_spms_pack
mlxsw_reg_spms_vid_pack
mlxsw_reg_spvid_pack
mlxsw_reg_spvm_pack
mlxsw_reg_spaft_pack
mlxsw_reg_sfgc_pack
mlxsw_reg_sftr_pack
mlxsw_reg_sfdf_pack
mlxsw_reg_sldr_lag_create_pack
mlxsw_reg_sldr_lag_destroy_pack
mlxsw_reg_sldr_lag_add_port_pack
mlxsw_reg_sldr_lag_remove_port_pack
mlxsw_reg_slcr_pack
mlxsw_reg_slcor_pack
mlxsw_reg_slcor_port_add_pack
mlxsw_reg_slcor_port_remove_pack
mlxsw_reg_slcor_col_enable_pack
mlxsw_reg_slcor_col_disable_pack
mlxsw_reg_spmlr_pack
mlxsw_reg_svfa_pack
mlxsw_reg_svpe_pack
mlxsw_reg_sfmr_pack
mlxsw_reg_spvmlr_pack
mlxsw_reg_cwtp_pack
mlxsw_reg_cwtp_profile_pack
mlxsw_reg_cwtpm_pack
mlxsw_reg_pgcr_pack
mlxsw_reg_ppbt_pack
mlxsw_reg_pacl_pack
mlxsw_reg_pagt_pack
mlxsw_reg_pagt_acl_id_pack
mlxsw_reg_ptar_pack
mlxsw_reg_ptar_key_id_pack
mlxsw_reg_ptar_unpack
mlxsw_reg_ppbs_pack
mlxsw_reg_prcr_pack
mlxsw_reg_pefa_pack
mlxsw_reg_pefa_unpack
mlxsw_reg_pemrbt_pack
mlxsw_reg_ptce2_pack
mlxsw_reg_perpt_erp_vector_pack
mlxsw_reg_perpt_pack
mlxsw_reg_perar_hw_regions_needed
mlxsw_reg_perar_pack
mlxsw_reg_ptce3_pack
mlxsw_reg_percr_pack
mlxsw_reg_pererp_erp_vector_pack
mlxsw_reg_pererp_pack
mlxsw_reg_peabfe_pack
mlxsw_reg_peabfe_rec_pack
mlxsw_reg_iedr_pack
mlxsw_reg_iedr_rec_pack
mlxsw_reg_qpts_pack
mlxsw_reg_qpcr_pack
mlxsw_reg_qtct_pack
mlxsw_reg_qeec_pack
mlxsw_reg_qeec_ptps_pack
mlxsw_reg_qrwe_pack
mlxsw_reg_qpdsm_pack
mlxsw_reg_qpdsm_prio_pack
mlxsw_reg_qpdpm_pack
mlxsw_reg_qpdpm_dscp_pack
mlxsw_reg_qtctm_pack
mlxsw_reg_qpsc_pack
mlxsw_reg_pmlp_pack
mlxsw_reg_pmtu_pack
mlxsw_reg_ptys_eth_pack
mlxsw_reg_ptys_ext_eth_pack
mlxsw_reg_ptys_eth_unpack
mlxsw_reg_ptys_ext_eth_unpack
mlxsw_reg_ptys_ib_pack
mlxsw_reg_ptys_ib_unpack
mlxsw_reg_ppad_pack
mlxsw_reg_paos_pack
mlxsw_reg_pfcc_prio_pack
mlxsw_reg_pfcc_pack
mlxsw_reg_ppcnt_pack
mlxsw_reg_pptb_pack
mlxsw_reg_pptb_prio_to_buff_pack
mlxsw_reg_pbmc_pack
mlxsw_reg_pbmc_lossy_buffer_pack
mlxsw_reg_pbmc_lossless_buffer_pack
mlxsw_reg_pspa_pack
mlxsw_reg_pplr_pack
mlxsw_reg_htgt_pack
mlxsw_reg_hpkt_pack
mlxsw_reg_rgcr_pack
mlxsw_reg_ritr_fid_set
mlxsw_reg_ritr_counter_pack
mlxsw_reg_ritr_rif_pack
mlxsw_reg_ritr_sp_if_pack
mlxsw_reg_ritr_pack
mlxsw_reg_ritr_mac_pack
mlxsw_reg_ritr_loopback_ipip_common_pack
mlxsw_reg_ritr_loopback_ipip4_pack
mlxsw_reg_rtar_pack
mlxsw_reg_ratr_pack
mlxsw_reg_ratr_eth_entry_pack
mlxsw_reg_ratr_ipip4_entry_pack
mlxsw_reg_ratr_counter_pack
mlxsw_reg_rdpm_pack
mlxsw_reg_ricnt_pack
mlxsw_reg_rrcr_pack
mlxsw_reg_ralta_pack
mlxsw_reg_ralst_pack
mlxsw_reg_ralst_bin_pack
mlxsw_reg_raltb_pack
mlxsw_reg_ralue_pack
mlxsw_reg_ralue_pack4
mlxsw_reg_ralue_pack6
mlxsw_reg_ralue_act_remote_pack
mlxsw_reg_ralue_act_local_pack
mlxsw_reg_ralue_act_ip2me_pack
mlxsw_reg_ralue_act_ip2me_tun_pack
mlxsw_reg_rauht_pack
mlxsw_reg_rauht_pack4
mlxsw_reg_rauht_pack6
mlxsw_reg_rauht_pack_counter
mlxsw_reg_raleu_pack
mlxsw_reg_rauhtd_pack
mlxsw_reg_rauhtd_ent_ipv4_unpack
mlxsw_reg_rauhtd_ent_ipv6_unpack
mlxsw_reg_rtdp_pack
mlxsw_reg_rtdp_ipip4_pack
mlxsw_reg_rigr2_pack
mlxsw_reg_rigr2_erif_entry_pack
mlxsw_reg_recr2_ipv4_sip_enable
mlxsw_reg_recr2_ipv4_dip_enable
mlxsw_reg_recr2_ipv6_sip_enable
mlxsw_reg_recr2_ipv6_dip_enable
mlxsw_reg_recr2_pack
mlxsw_reg_rmft2_common_pack
mlxsw_reg_rmft2_ipv4_pack
mlxsw_reg_rmft2_ipv6_pack
mlxsw_reg_mfcr_pack
mlxsw_reg_mfcr_unpack
mlxsw_reg_mfsc_pack
mlxsw_reg_mfsm_pack
mlxsw_reg_mfsl_pack
mlxsw_reg_mfsl_unpack
mlxsw_reg_fore_unpack
mlxsw_reg_mtmp_pack
mlxsw_reg_mtmp_unpack
mlxsw_reg_mtbr_pack
mlxsw_reg_mtbr_temp_unpack
mlxsw_reg_mcia_pack
mlxsw_reg_mpat_pack
mlxsw_reg_mpat_eth_rspan_pack
mlxsw_reg_mpat_eth_rspan_l2_pack
mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack
mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack
mlxsw_reg_mpar_pack
mlxsw_reg_mgir_pack
mlxsw_reg_mgir_unpack
mlxsw_reg_mrsr_pack
mlxsw_reg_mlcr_pack
mlxsw_reg_mtpps_vpin_pack
mlxsw_reg_mtutc_pack
mlxsw_reg_mcqi_pack
mlxsw_reg_mcqi_unpack
mlxsw_reg_mcc_pack
mlxsw_reg_mcc_unpack
mlxsw_reg_mcda_pack
mlxsw_reg_mpsc_pack
mlxsw_reg_mgpc_pack
mlxsw_reg_mprs_pack
mlxsw_reg_mtpppc_pack
mlxsw_reg_mtpptr_unpack
mlxsw_reg_mtptptp_pack
mlxsw_reg_mgpir_pack
mlxsw_reg_mgpir_unpack
mlxsw_reg_tngcr_pack
mlxsw_reg_tnumt_pack
mlxsw_reg_tnqcr_pack
mlxsw_reg_tnqdr_pack
mlxsw_reg_tneem_pack
mlxsw_reg_tndem_pack
mlxsw_reg_tnpc_pack
mlxsw_reg_tigcr_pack
mlxsw_reg_sbpr_pack
mlxsw_reg_sbcm_pack
mlxsw_reg_sbpm_pack
mlxsw_reg_sbpm_unpack
mlxsw_reg_sbmm_pack
mlxsw_reg_sbsr_pack
mlxsw_reg_sbsr_rec_unpack
mlxsw_reg_sbib_pack
mlxsw_reg_id_str
   1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3 
   4 #ifndef _MLXSW_REG_H
   5 #define _MLXSW_REG_H
   6 
   7 #include <linux/kernel.h>
   8 #include <linux/string.h>
   9 #include <linux/bitops.h>
  10 #include <linux/if_vlan.h>
  11 
  12 #include "item.h"
  13 #include "port.h"
  14 
  15 struct mlxsw_reg_info {
  16         u16 id;
  17         u16 len; /* In u8 */
  18         const char *name;
  19 };
  20 
  21 #define MLXSW_REG_DEFINE(_name, _id, _len)                              \
  22 static const struct mlxsw_reg_info mlxsw_reg_##_name = {                \
  23         .id = _id,                                                      \
  24         .len = _len,                                                    \
  25         .name = #_name,                                                 \
  26 }
  27 
  28 #define MLXSW_REG(type) (&mlxsw_reg_##type)
  29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
  30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
  31 
  32 /* SGCR - Switch General Configuration Register
  33  * --------------------------------------------
  34  * This register is used for configuration of the switch capabilities.
  35  */
  36 #define MLXSW_REG_SGCR_ID 0x2000
  37 #define MLXSW_REG_SGCR_LEN 0x10
  38 
  39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
  40 
  41 /* reg_sgcr_llb
  42  * Link Local Broadcast (Default=0)
  43  * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
  44  * packets and ignore the IGMP snooping entries.
  45  * Access: RW
  46  */
  47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
  48 
  49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
  50 {
  51         MLXSW_REG_ZERO(sgcr, payload);
  52         mlxsw_reg_sgcr_llb_set(payload, !!llb);
  53 }
  54 
  55 /* SPAD - Switch Physical Address Register
  56  * ---------------------------------------
  57  * The SPAD register configures the switch physical MAC address.
  58  */
  59 #define MLXSW_REG_SPAD_ID 0x2002
  60 #define MLXSW_REG_SPAD_LEN 0x10
  61 
  62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
  63 
  64 /* reg_spad_base_mac
  65  * Base MAC address for the switch partitions.
  66  * Per switch partition MAC address is equal to:
  67  * base_mac + swid
  68  * Access: RW
  69  */
  70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
  71 
  72 /* SMID - Switch Multicast ID
  73  * --------------------------
  74  * The MID record maps from a MID (Multicast ID), which is a unique identifier
  75  * of the multicast group within the stacking domain, into a list of local
  76  * ports into which the packet is replicated.
  77  */
  78 #define MLXSW_REG_SMID_ID 0x2007
  79 #define MLXSW_REG_SMID_LEN 0x240
  80 
  81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
  82 
  83 /* reg_smid_swid
  84  * Switch partition ID.
  85  * Access: Index
  86  */
  87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
  88 
  89 /* reg_smid_mid
  90  * Multicast identifier - global identifier that represents the multicast group
  91  * across all devices.
  92  * Access: Index
  93  */
  94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
  95 
  96 /* reg_smid_port
  97  * Local port memebership (1 bit per port).
  98  * Access: RW
  99  */
 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
 101 
 102 /* reg_smid_port_mask
 103  * Local port mask (1 bit per port).
 104  * Access: W
 105  */
 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
 107 
 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
 109                                        u8 port, bool set)
 110 {
 111         MLXSW_REG_ZERO(smid, payload);
 112         mlxsw_reg_smid_swid_set(payload, 0);
 113         mlxsw_reg_smid_mid_set(payload, mid);
 114         mlxsw_reg_smid_port_set(payload, port, set);
 115         mlxsw_reg_smid_port_mask_set(payload, port, 1);
 116 }
 117 
 118 /* SSPR - Switch System Port Record Register
 119  * -----------------------------------------
 120  * Configures the system port to local port mapping.
 121  */
 122 #define MLXSW_REG_SSPR_ID 0x2008
 123 #define MLXSW_REG_SSPR_LEN 0x8
 124 
 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
 126 
 127 /* reg_sspr_m
 128  * Master - if set, then the record describes the master system port.
 129  * This is needed in case a local port is mapped into several system ports
 130  * (for multipathing). That number will be reported as the source system
 131  * port when packets are forwarded to the CPU. Only one master port is allowed
 132  * per local port.
 133  *
 134  * Note: Must be set for Spectrum.
 135  * Access: RW
 136  */
 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
 138 
 139 /* reg_sspr_local_port
 140  * Local port number.
 141  *
 142  * Access: RW
 143  */
 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
 145 
 146 /* reg_sspr_sub_port
 147  * Virtual port within the physical port.
 148  * Should be set to 0 when virtual ports are not enabled on the port.
 149  *
 150  * Access: RW
 151  */
 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
 153 
 154 /* reg_sspr_system_port
 155  * Unique identifier within the stacking domain that represents all the ports
 156  * that are available in the system (external ports).
 157  *
 158  * Currently, only single-ASIC configurations are supported, so we default to
 159  * 1:1 mapping between system ports and local ports.
 160  * Access: Index
 161  */
 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
 163 
 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
 165 {
 166         MLXSW_REG_ZERO(sspr, payload);
 167         mlxsw_reg_sspr_m_set(payload, 1);
 168         mlxsw_reg_sspr_local_port_set(payload, local_port);
 169         mlxsw_reg_sspr_sub_port_set(payload, 0);
 170         mlxsw_reg_sspr_system_port_set(payload, local_port);
 171 }
 172 
 173 /* SFDAT - Switch Filtering Database Aging Time
 174  * --------------------------------------------
 175  * Controls the Switch aging time. Aging time is able to be set per Switch
 176  * Partition.
 177  */
 178 #define MLXSW_REG_SFDAT_ID 0x2009
 179 #define MLXSW_REG_SFDAT_LEN 0x8
 180 
 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
 182 
 183 /* reg_sfdat_swid
 184  * Switch partition ID.
 185  * Access: Index
 186  */
 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
 188 
 189 /* reg_sfdat_age_time
 190  * Aging time in seconds
 191  * Min - 10 seconds
 192  * Max - 1,000,000 seconds
 193  * Default is 300 seconds.
 194  * Access: RW
 195  */
 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
 197 
 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
 199 {
 200         MLXSW_REG_ZERO(sfdat, payload);
 201         mlxsw_reg_sfdat_swid_set(payload, 0);
 202         mlxsw_reg_sfdat_age_time_set(payload, age_time);
 203 }
 204 
 205 /* SFD - Switch Filtering Database
 206  * -------------------------------
 207  * The following register defines the access to the filtering database.
 208  * The register supports querying, adding, removing and modifying the database.
 209  * The access is optimized for bulk updates in which case more than one
 210  * FDB record is present in the same command.
 211  */
 212 #define MLXSW_REG_SFD_ID 0x200A
 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN +     \
 217                            MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
 218 
 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
 220 
 221 /* reg_sfd_swid
 222  * Switch partition ID for queries. Reserved on Write.
 223  * Access: Index
 224  */
 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
 226 
 227 enum mlxsw_reg_sfd_op {
 228         /* Dump entire FDB a (process according to record_locator) */
 229         MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
 230         /* Query records by {MAC, VID/FID} value */
 231         MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
 232         /* Query and clear activity. Query records by {MAC, VID/FID} value */
 233         MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
 234         /* Test. Response indicates if each of the records could be
 235          * added to the FDB.
 236          */
 237         MLXSW_REG_SFD_OP_WRITE_TEST = 0,
 238         /* Add/modify. Aged-out records cannot be added. This command removes
 239          * the learning notification of the {MAC, VID/FID}. Response includes
 240          * the entries that were added to the FDB.
 241          */
 242         MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
 243         /* Remove record by {MAC, VID/FID}. This command also removes
 244          * the learning notification and aged-out notifications
 245          * of the {MAC, VID/FID}. The response provides current (pre-removal)
 246          * entries as non-aged-out.
 247          */
 248         MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
 249         /* Remove learned notification by {MAC, VID/FID}. The response provides
 250          * the removed learning notification.
 251          */
 252         MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
 253 };
 254 
 255 /* reg_sfd_op
 256  * Operation.
 257  * Access: OP
 258  */
 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
 260 
 261 /* reg_sfd_record_locator
 262  * Used for querying the FDB. Use record_locator=0 to initiate the
 263  * query. When a record is returned, a new record_locator is
 264  * returned to be used in the subsequent query.
 265  * Reserved for database update.
 266  * Access: Index
 267  */
 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
 269 
 270 /* reg_sfd_num_rec
 271  * Request: Number of records to read/add/modify/remove
 272  * Response: Number of records read/added/replaced/removed
 273  * See above description for more details.
 274  * Ranges 0..64
 275  * Access: RW
 276  */
 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
 278 
 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
 280                                       u32 record_locator)
 281 {
 282         MLXSW_REG_ZERO(sfd, payload);
 283         mlxsw_reg_sfd_op_set(payload, op);
 284         mlxsw_reg_sfd_record_locator_set(payload, record_locator);
 285 }
 286 
 287 /* reg_sfd_rec_swid
 288  * Switch partition ID.
 289  * Access: Index
 290  */
 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
 292                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 293 
 294 enum mlxsw_reg_sfd_rec_type {
 295         MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
 296         MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
 297         MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
 298         MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
 299 };
 300 
 301 /* reg_sfd_rec_type
 302  * FDB record type.
 303  * Access: RW
 304  */
 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
 306                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 307 
 308 enum mlxsw_reg_sfd_rec_policy {
 309         /* Replacement disabled, aging disabled. */
 310         MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
 311         /* (mlag remote): Replacement enabled, aging disabled,
 312          * learning notification enabled on this port.
 313          */
 314         MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
 315         /* (ingress device): Replacement enabled, aging enabled. */
 316         MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
 317 };
 318 
 319 /* reg_sfd_rec_policy
 320  * Policy.
 321  * Access: RW
 322  */
 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
 324                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 325 
 326 /* reg_sfd_rec_a
 327  * Activity. Set for new static entries. Set for static entries if a frame SMAC
 328  * lookup hits on the entry.
 329  * To clear the a bit, use "query and clear activity" op.
 330  * Access: RO
 331  */
 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
 333                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 334 
 335 /* reg_sfd_rec_mac
 336  * MAC address.
 337  * Access: Index
 338  */
 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
 340                        MLXSW_REG_SFD_REC_LEN, 0x02);
 341 
 342 enum mlxsw_reg_sfd_rec_action {
 343         /* forward */
 344         MLXSW_REG_SFD_REC_ACTION_NOP = 0,
 345         /* forward and trap, trap_id is FDB_TRAP */
 346         MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
 347         /* trap and do not forward, trap_id is FDB_TRAP */
 348         MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
 349         /* forward to IP router */
 350         MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
 351         MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
 352 };
 353 
 354 /* reg_sfd_rec_action
 355  * Action to apply on the packet.
 356  * Note: Dynamic entries can only be configured with NOP action.
 357  * Access: RW
 358  */
 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
 360                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 361 
 362 /* reg_sfd_uc_sub_port
 363  * VEPA channel on local port.
 364  * Valid only if local port is a non-stacking port. Must be 0 if multichannel
 365  * VEPA is not enabled.
 366  * Access: RW
 367  */
 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
 369                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 370 
 371 /* reg_sfd_uc_fid_vid
 372  * Filtering ID or VLAN ID
 373  * For SwitchX and SwitchX-2:
 374  * - Dynamic entries (policy 2,3) use FID
 375  * - Static entries (policy 0) use VID
 376  * - When independent learning is configured, VID=FID
 377  * For Spectrum: use FID for both Dynamic and Static entries.
 378  * VID should not be used.
 379  * Access: Index
 380  */
 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 382                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 383 
 384 /* reg_sfd_uc_system_port
 385  * Unique port identifier for the final destination of the packet.
 386  * Access: RW
 387  */
 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 389                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 390 
 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
 392                                           enum mlxsw_reg_sfd_rec_type rec_type,
 393                                           const char *mac,
 394                                           enum mlxsw_reg_sfd_rec_action action)
 395 {
 396         u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
 397 
 398         if (rec_index >= num_rec)
 399                 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
 400         mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
 401         mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
 402         mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
 403         mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
 404 }
 405 
 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
 407                                          enum mlxsw_reg_sfd_rec_policy policy,
 408                                          const char *mac, u16 fid_vid,
 409                                          enum mlxsw_reg_sfd_rec_action action,
 410                                          u8 local_port)
 411 {
 412         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 413                                MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
 414         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 415         mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
 416         mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
 417         mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
 418 }
 419 
 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
 421                                            char *mac, u16 *p_fid_vid,
 422                                            u8 *p_local_port)
 423 {
 424         mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
 425         *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
 426         *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
 427 }
 428 
 429 /* reg_sfd_uc_lag_sub_port
 430  * LAG sub port.
 431  * Must be 0 if multichannel VEPA is not enabled.
 432  * Access: RW
 433  */
 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
 435                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 436 
 437 /* reg_sfd_uc_lag_fid_vid
 438  * Filtering ID or VLAN ID
 439  * For SwitchX and SwitchX-2:
 440  * - Dynamic entries (policy 2,3) use FID
 441  * - Static entries (policy 0) use VID
 442  * - When independent learning is configured, VID=FID
 443  * For Spectrum: use FID for both Dynamic and Static entries.
 444  * VID should not be used.
 445  * Access: Index
 446  */
 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 448                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 449 
 450 /* reg_sfd_uc_lag_lag_vid
 451  * Indicates VID in case of vFIDs. Reserved for FIDs.
 452  * Access: RW
 453  */
 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
 455                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 456 
 457 /* reg_sfd_uc_lag_lag_id
 458  * LAG Identifier - pointer into the LAG descriptor table.
 459  * Access: RW
 460  */
 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
 462                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 463 
 464 static inline void
 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
 466                           enum mlxsw_reg_sfd_rec_policy policy,
 467                           const char *mac, u16 fid_vid,
 468                           enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
 469                           u16 lag_id)
 470 {
 471         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 472                                MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
 473                                mac, action);
 474         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 475         mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
 476         mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
 477         mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
 478         mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
 479 }
 480 
 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
 482                                                char *mac, u16 *p_vid,
 483                                                u16 *p_lag_id)
 484 {
 485         mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
 486         *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
 487         *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
 488 }
 489 
 490 /* reg_sfd_mc_pgi
 491  *
 492  * Multicast port group index - index into the port group table.
 493  * Value 0x1FFF indicates the pgi should point to the MID entry.
 494  * For Spectrum this value must be set to 0x1FFF
 495  * Access: RW
 496  */
 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
 498                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 499 
 500 /* reg_sfd_mc_fid_vid
 501  *
 502  * Filtering ID or VLAN ID
 503  * Access: Index
 504  */
 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 506                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 507 
 508 /* reg_sfd_mc_mid
 509  *
 510  * Multicast identifier - global identifier that represents the multicast
 511  * group across all devices.
 512  * Access: RW
 513  */
 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 515                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 516 
 517 static inline void
 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
 519                       const char *mac, u16 fid_vid,
 520                       enum mlxsw_reg_sfd_rec_action action, u16 mid)
 521 {
 522         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 523                                MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
 524         mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
 525         mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
 526         mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
 527 }
 528 
 529 /* reg_sfd_uc_tunnel_uip_msb
 530  * When protocol is IPv4, the most significant byte of the underlay IPv4
 531  * destination IP.
 532  * When protocol is IPv6, reserved.
 533  * Access: RW
 534  */
 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
 536                      8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
 537 
 538 /* reg_sfd_uc_tunnel_fid
 539  * Filtering ID.
 540  * Access: Index
 541  */
 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 543                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 544 
 545 enum mlxsw_reg_sfd_uc_tunnel_protocol {
 546         MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
 547         MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
 548 };
 549 
 550 /* reg_sfd_uc_tunnel_protocol
 551  * IP protocol.
 552  * Access: RW
 553  */
 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
 555                      1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 556 
 557 /* reg_sfd_uc_tunnel_uip_lsb
 558  * When protocol is IPv4, the least significant bytes of the underlay
 559  * IPv4 destination IP.
 560  * When protocol is IPv6, pointer to the underlay IPv6 destination IP
 561  * which is configured by RIPS.
 562  * Access: RW
 563  */
 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
 565                      24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 566 
 567 static inline void
 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
 569                              enum mlxsw_reg_sfd_rec_policy policy,
 570                              const char *mac, u16 fid,
 571                              enum mlxsw_reg_sfd_rec_action action, u32 uip,
 572                              enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
 573 {
 574         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 575                                MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
 576                                action);
 577         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 578         mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
 579         mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
 580         mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
 581         mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
 582 }
 583 
 584 /* SFN - Switch FDB Notification Register
 585  * -------------------------------------------
 586  * The switch provides notifications on newly learned FDB entries and
 587  * aged out entries. The notifications can be polled by software.
 588  */
 589 #define MLXSW_REG_SFN_ID 0x200B
 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN +     \
 594                            MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
 595 
 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
 597 
 598 /* reg_sfn_swid
 599  * Switch partition ID.
 600  * Access: Index
 601  */
 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
 603 
 604 /* reg_sfn_end
 605  * Forces the current session to end.
 606  * Access: OP
 607  */
 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
 609 
 610 /* reg_sfn_num_rec
 611  * Request: Number of learned notifications and aged-out notification
 612  * records requested.
 613  * Response: Number of notification records returned (must be smaller
 614  * than or equal to the value requested)
 615  * Ranges 0..64
 616  * Access: OP
 617  */
 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
 619 
 620 static inline void mlxsw_reg_sfn_pack(char *payload)
 621 {
 622         MLXSW_REG_ZERO(sfn, payload);
 623         mlxsw_reg_sfn_swid_set(payload, 0);
 624         mlxsw_reg_sfn_end_set(payload, 1);
 625         mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
 626 }
 627 
 628 /* reg_sfn_rec_swid
 629  * Switch partition ID.
 630  * Access: RO
 631  */
 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
 633                      MLXSW_REG_SFN_REC_LEN, 0x00, false);
 634 
 635 enum mlxsw_reg_sfn_rec_type {
 636         /* MAC addresses learned on a regular port. */
 637         MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
 638         /* MAC addresses learned on a LAG port. */
 639         MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
 640         /* Aged-out MAC address on a regular port. */
 641         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
 642         /* Aged-out MAC address on a LAG port. */
 643         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
 644         /* Learned unicast tunnel record. */
 645         MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
 646         /* Aged-out unicast tunnel record. */
 647         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
 648 };
 649 
 650 /* reg_sfn_rec_type
 651  * Notification record type.
 652  * Access: RO
 653  */
 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
 655                      MLXSW_REG_SFN_REC_LEN, 0x00, false);
 656 
 657 /* reg_sfn_rec_mac
 658  * MAC address.
 659  * Access: RO
 660  */
 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
 662                        MLXSW_REG_SFN_REC_LEN, 0x02);
 663 
 664 /* reg_sfn_mac_sub_port
 665  * VEPA channel on the local port.
 666  * 0 if multichannel VEPA is not enabled.
 667  * Access: RO
 668  */
 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
 670                      MLXSW_REG_SFN_REC_LEN, 0x08, false);
 671 
 672 /* reg_sfn_mac_fid
 673  * Filtering identifier.
 674  * Access: RO
 675  */
 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
 677                      MLXSW_REG_SFN_REC_LEN, 0x08, false);
 678 
 679 /* reg_sfn_mac_system_port
 680  * Unique port identifier for the final destination of the packet.
 681  * Access: RO
 682  */
 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
 684                      MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 685 
 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
 687                                             char *mac, u16 *p_vid,
 688                                             u8 *p_local_port)
 689 {
 690         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 691         *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 692         *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
 693 }
 694 
 695 /* reg_sfn_mac_lag_lag_id
 696  * LAG ID (pointer into the LAG descriptor table).
 697  * Access: RO
 698  */
 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
 700                      MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 701 
 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
 703                                                 char *mac, u16 *p_vid,
 704                                                 u16 *p_lag_id)
 705 {
 706         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 707         *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 708         *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
 709 }
 710 
 711 /* reg_sfn_uc_tunnel_uip_msb
 712  * When protocol is IPv4, the most significant byte of the underlay IPv4
 713  * address of the remote VTEP.
 714  * When protocol is IPv6, reserved.
 715  * Access: RO
 716  */
 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
 718                      8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
 719 
 720 enum mlxsw_reg_sfn_uc_tunnel_protocol {
 721         MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
 722         MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
 723 };
 724 
 725 /* reg_sfn_uc_tunnel_protocol
 726  * IP protocol.
 727  * Access: RO
 728  */
 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
 730                      1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 731 
 732 /* reg_sfn_uc_tunnel_uip_lsb
 733  * When protocol is IPv4, the least significant bytes of the underlay
 734  * IPv4 address of the remote VTEP.
 735  * When protocol is IPv6, ipv6_id to be queried from TNIPSD.
 736  * Access: RO
 737  */
 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
 739                      24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 740 
 741 enum mlxsw_reg_sfn_tunnel_port {
 742         MLXSW_REG_SFN_TUNNEL_PORT_NVE,
 743         MLXSW_REG_SFN_TUNNEL_PORT_VPLS,
 744         MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0,
 745         MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1,
 746 };
 747 
 748 /* reg_sfn_uc_tunnel_port
 749  * Tunnel port.
 750  * Reserved on Spectrum.
 751  * Access: RO
 752  */
 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
 754                      MLXSW_REG_SFN_REC_LEN, 0x10, false);
 755 
 756 static inline void
 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
 758                                u16 *p_fid, u32 *p_uip,
 759                                enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
 760 {
 761         u32 uip_msb, uip_lsb;
 762 
 763         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 764         *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 765         uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
 766         uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
 767         *p_uip = uip_msb << 24 | uip_lsb;
 768         *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
 769 }
 770 
 771 /* SPMS - Switch Port MSTP/RSTP State Register
 772  * -------------------------------------------
 773  * Configures the spanning tree state of a physical port.
 774  */
 775 #define MLXSW_REG_SPMS_ID 0x200D
 776 #define MLXSW_REG_SPMS_LEN 0x404
 777 
 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
 779 
 780 /* reg_spms_local_port
 781  * Local port number.
 782  * Access: Index
 783  */
 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
 785 
 786 enum mlxsw_reg_spms_state {
 787         MLXSW_REG_SPMS_STATE_NO_CHANGE,
 788         MLXSW_REG_SPMS_STATE_DISCARDING,
 789         MLXSW_REG_SPMS_STATE_LEARNING,
 790         MLXSW_REG_SPMS_STATE_FORWARDING,
 791 };
 792 
 793 /* reg_spms_state
 794  * Spanning tree state of each VLAN ID (VID) of the local port.
 795  * 0 - Do not change spanning tree state (used only when writing).
 796  * 1 - Discarding. No learning or forwarding to/from this port (default).
 797  * 2 - Learning. Port is learning, but not forwarding.
 798  * 3 - Forwarding. Port is learning and forwarding.
 799  * Access: RW
 800  */
 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
 802 
 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
 804 {
 805         MLXSW_REG_ZERO(spms, payload);
 806         mlxsw_reg_spms_local_port_set(payload, local_port);
 807 }
 808 
 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
 810                                            enum mlxsw_reg_spms_state state)
 811 {
 812         mlxsw_reg_spms_state_set(payload, vid, state);
 813 }
 814 
 815 /* SPVID - Switch Port VID
 816  * -----------------------
 817  * The switch port VID configures the default VID for a port.
 818  */
 819 #define MLXSW_REG_SPVID_ID 0x200E
 820 #define MLXSW_REG_SPVID_LEN 0x08
 821 
 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
 823 
 824 /* reg_spvid_local_port
 825  * Local port number.
 826  * Access: Index
 827  */
 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
 829 
 830 /* reg_spvid_sub_port
 831  * Virtual port within the physical port.
 832  * Should be set to 0 when virtual ports are not enabled on the port.
 833  * Access: Index
 834  */
 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
 836 
 837 /* reg_spvid_pvid
 838  * Port default VID
 839  * Access: RW
 840  */
 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
 842 
 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
 844 {
 845         MLXSW_REG_ZERO(spvid, payload);
 846         mlxsw_reg_spvid_local_port_set(payload, local_port);
 847         mlxsw_reg_spvid_pvid_set(payload, pvid);
 848 }
 849 
 850 /* SPVM - Switch Port VLAN Membership
 851  * ----------------------------------
 852  * The Switch Port VLAN Membership register configures the VLAN membership
 853  * of a port in a VLAN denoted by VID. VLAN membership is managed per
 854  * virtual port. The register can be used to add and remove VID(s) from a port.
 855  */
 856 #define MLXSW_REG_SPVM_ID 0x200F
 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255
 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN +   \
 861                     MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
 862 
 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
 864 
 865 /* reg_spvm_pt
 866  * Priority tagged. If this bit is set, packets forwarded to the port with
 867  * untagged VLAN membership (u bit is set) will be tagged with priority tag
 868  * (VID=0)
 869  * Access: RW
 870  */
 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
 872 
 873 /* reg_spvm_pte
 874  * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
 875  * the pt bit will NOT be updated. To update the pt bit, pte must be set.
 876  * Access: WO
 877  */
 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
 879 
 880 /* reg_spvm_local_port
 881  * Local port number.
 882  * Access: Index
 883  */
 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
 885 
 886 /* reg_spvm_sub_port
 887  * Virtual port within the physical port.
 888  * Should be set to 0 when virtual ports are not enabled on the port.
 889  * Access: Index
 890  */
 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
 892 
 893 /* reg_spvm_num_rec
 894  * Number of records to update. Each record contains: i, e, u, vid.
 895  * Access: OP
 896  */
 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
 898 
 899 /* reg_spvm_rec_i
 900  * Ingress membership in VLAN ID.
 901  * Access: Index
 902  */
 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
 904                      MLXSW_REG_SPVM_BASE_LEN, 14, 1,
 905                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 906 
 907 /* reg_spvm_rec_e
 908  * Egress membership in VLAN ID.
 909  * Access: Index
 910  */
 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
 912                      MLXSW_REG_SPVM_BASE_LEN, 13, 1,
 913                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 914 
 915 /* reg_spvm_rec_u
 916  * Untagged - port is an untagged member - egress transmission uses untagged
 917  * frames on VID<n>
 918  * Access: Index
 919  */
 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
 921                      MLXSW_REG_SPVM_BASE_LEN, 12, 1,
 922                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 923 
 924 /* reg_spvm_rec_vid
 925  * Egress membership in VLAN ID.
 926  * Access: Index
 927  */
 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
 929                      MLXSW_REG_SPVM_BASE_LEN, 0, 12,
 930                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 931 
 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
 933                                        u16 vid_begin, u16 vid_end,
 934                                        bool is_member, bool untagged)
 935 {
 936         int size = vid_end - vid_begin + 1;
 937         int i;
 938 
 939         MLXSW_REG_ZERO(spvm, payload);
 940         mlxsw_reg_spvm_local_port_set(payload, local_port);
 941         mlxsw_reg_spvm_num_rec_set(payload, size);
 942 
 943         for (i = 0; i < size; i++) {
 944                 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
 945                 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
 946                 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
 947                 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
 948         }
 949 }
 950 
 951 /* SPAFT - Switch Port Acceptable Frame Types
 952  * ------------------------------------------
 953  * The Switch Port Acceptable Frame Types register configures the frame
 954  * admittance of the port.
 955  */
 956 #define MLXSW_REG_SPAFT_ID 0x2010
 957 #define MLXSW_REG_SPAFT_LEN 0x08
 958 
 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
 960 
 961 /* reg_spaft_local_port
 962  * Local port number.
 963  * Access: Index
 964  *
 965  * Note: CPU port is not supported (all tag types are allowed).
 966  */
 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
 968 
 969 /* reg_spaft_sub_port
 970  * Virtual port within the physical port.
 971  * Should be set to 0 when virtual ports are not enabled on the port.
 972  * Access: RW
 973  */
 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
 975 
 976 /* reg_spaft_allow_untagged
 977  * When set, untagged frames on the ingress are allowed (default).
 978  * Access: RW
 979  */
 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
 981 
 982 /* reg_spaft_allow_prio_tagged
 983  * When set, priority tagged frames on the ingress are allowed (default).
 984  * Access: RW
 985  */
 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
 987 
 988 /* reg_spaft_allow_tagged
 989  * When set, tagged frames on the ingress are allowed (default).
 990  * Access: RW
 991  */
 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
 993 
 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
 995                                         bool allow_untagged)
 996 {
 997         MLXSW_REG_ZERO(spaft, payload);
 998         mlxsw_reg_spaft_local_port_set(payload, local_port);
 999         mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1000         mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
1001         mlxsw_reg_spaft_allow_tagged_set(payload, true);
1002 }
1003 
1004 /* SFGC - Switch Flooding Group Configuration
1005  * ------------------------------------------
1006  * The following register controls the association of flooding tables and MIDs
1007  * to packet types used for flooding.
1008  */
1009 #define MLXSW_REG_SFGC_ID 0x2011
1010 #define MLXSW_REG_SFGC_LEN 0x10
1011 
1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1013 
1014 enum mlxsw_reg_sfgc_type {
1015         MLXSW_REG_SFGC_TYPE_BROADCAST,
1016         MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1017         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1018         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1019         MLXSW_REG_SFGC_TYPE_RESERVED,
1020         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1021         MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1022         MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1023         MLXSW_REG_SFGC_TYPE_MAX,
1024 };
1025 
1026 /* reg_sfgc_type
1027  * The traffic type to reach the flooding table.
1028  * Access: Index
1029  */
1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1031 
1032 enum mlxsw_reg_sfgc_bridge_type {
1033         MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
1034         MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
1035 };
1036 
1037 /* reg_sfgc_bridge_type
1038  * Access: Index
1039  *
1040  * Note: SwitchX-2 only supports 802.1Q mode.
1041  */
1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1043 
1044 enum mlxsw_flood_table_type {
1045         MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1046         MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1047         MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1048         MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1049         MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1050 };
1051 
1052 /* reg_sfgc_table_type
1053  * See mlxsw_flood_table_type
1054  * Access: RW
1055  *
1056  * Note: FID offset and FID types are not supported in SwitchX-2.
1057  */
1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1059 
1060 /* reg_sfgc_flood_table
1061  * Flooding table index to associate with the specific type on the specific
1062  * switch partition.
1063  * Access: RW
1064  */
1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1066 
1067 /* reg_sfgc_mid
1068  * The multicast ID for the swid. Not supported for Spectrum
1069  * Access: RW
1070  */
1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1072 
1073 /* reg_sfgc_counter_set_type
1074  * Counter Set Type for flow counters.
1075  * Access: RW
1076  */
1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1078 
1079 /* reg_sfgc_counter_index
1080  * Counter Index for flow counters.
1081  * Access: RW
1082  */
1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1084 
1085 static inline void
1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1087                     enum mlxsw_reg_sfgc_bridge_type bridge_type,
1088                     enum mlxsw_flood_table_type table_type,
1089                     unsigned int flood_table)
1090 {
1091         MLXSW_REG_ZERO(sfgc, payload);
1092         mlxsw_reg_sfgc_type_set(payload, type);
1093         mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1094         mlxsw_reg_sfgc_table_type_set(payload, table_type);
1095         mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1096         mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1097 }
1098 
1099 /* SFTR - Switch Flooding Table Register
1100  * -------------------------------------
1101  * The switch flooding table is used for flooding packet replication. The table
1102  * defines a bit mask of ports for packet replication.
1103  */
1104 #define MLXSW_REG_SFTR_ID 0x2012
1105 #define MLXSW_REG_SFTR_LEN 0x420
1106 
1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
1108 
1109 /* reg_sftr_swid
1110  * Switch partition ID with which to associate the port.
1111  * Access: Index
1112  */
1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1114 
1115 /* reg_sftr_flood_table
1116  * Flooding table index to associate with the specific type on the specific
1117  * switch partition.
1118  * Access: Index
1119  */
1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1121 
1122 /* reg_sftr_index
1123  * Index. Used as an index into the Flooding Table in case the table is
1124  * configured to use VID / FID or FID Offset.
1125  * Access: Index
1126  */
1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1128 
1129 /* reg_sftr_table_type
1130  * See mlxsw_flood_table_type
1131  * Access: RW
1132  */
1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1134 
1135 /* reg_sftr_range
1136  * Range of entries to update
1137  * Access: Index
1138  */
1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1140 
1141 /* reg_sftr_port
1142  * Local port membership (1 bit per port).
1143  * Access: RW
1144  */
1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1146 
1147 /* reg_sftr_cpu_port_mask
1148  * CPU port mask (1 bit per port).
1149  * Access: W
1150  */
1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1152 
1153 static inline void mlxsw_reg_sftr_pack(char *payload,
1154                                        unsigned int flood_table,
1155                                        unsigned int index,
1156                                        enum mlxsw_flood_table_type table_type,
1157                                        unsigned int range, u8 port, bool set)
1158 {
1159         MLXSW_REG_ZERO(sftr, payload);
1160         mlxsw_reg_sftr_swid_set(payload, 0);
1161         mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1162         mlxsw_reg_sftr_index_set(payload, index);
1163         mlxsw_reg_sftr_table_type_set(payload, table_type);
1164         mlxsw_reg_sftr_range_set(payload, range);
1165         mlxsw_reg_sftr_port_set(payload, port, set);
1166         mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1167 }
1168 
1169 /* SFDF - Switch Filtering DB Flush
1170  * --------------------------------
1171  * The switch filtering DB flush register is used to flush the FDB.
1172  * Note that FDB notifications are flushed as well.
1173  */
1174 #define MLXSW_REG_SFDF_ID 0x2013
1175 #define MLXSW_REG_SFDF_LEN 0x14
1176 
1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1178 
1179 /* reg_sfdf_swid
1180  * Switch partition ID.
1181  * Access: Index
1182  */
1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1184 
1185 enum mlxsw_reg_sfdf_flush_type {
1186         MLXSW_REG_SFDF_FLUSH_PER_SWID,
1187         MLXSW_REG_SFDF_FLUSH_PER_FID,
1188         MLXSW_REG_SFDF_FLUSH_PER_PORT,
1189         MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1190         MLXSW_REG_SFDF_FLUSH_PER_LAG,
1191         MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1192         MLXSW_REG_SFDF_FLUSH_PER_NVE,
1193         MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1194 };
1195 
1196 /* reg_sfdf_flush_type
1197  * Flush type.
1198  * 0 - All SWID dynamic entries are flushed.
1199  * 1 - All FID dynamic entries are flushed.
1200  * 2 - All dynamic entries pointing to port are flushed.
1201  * 3 - All FID dynamic entries pointing to port are flushed.
1202  * 4 - All dynamic entries pointing to LAG are flushed.
1203  * 5 - All FID dynamic entries pointing to LAG are flushed.
1204  * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1205  *     flushed.
1206  * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1207  *     flushed, per FID.
1208  * Access: RW
1209  */
1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1211 
1212 /* reg_sfdf_flush_static
1213  * Static.
1214  * 0 - Flush only dynamic entries.
1215  * 1 - Flush both dynamic and static entries.
1216  * Access: RW
1217  */
1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1219 
1220 static inline void mlxsw_reg_sfdf_pack(char *payload,
1221                                        enum mlxsw_reg_sfdf_flush_type type)
1222 {
1223         MLXSW_REG_ZERO(sfdf, payload);
1224         mlxsw_reg_sfdf_flush_type_set(payload, type);
1225         mlxsw_reg_sfdf_flush_static_set(payload, true);
1226 }
1227 
1228 /* reg_sfdf_fid
1229  * FID to flush.
1230  * Access: RW
1231  */
1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1233 
1234 /* reg_sfdf_system_port
1235  * Port to flush.
1236  * Access: RW
1237  */
1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1239 
1240 /* reg_sfdf_port_fid_system_port
1241  * Port to flush, pointed to by FID.
1242  * Access: RW
1243  */
1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1245 
1246 /* reg_sfdf_lag_id
1247  * LAG ID to flush.
1248  * Access: RW
1249  */
1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1251 
1252 /* reg_sfdf_lag_fid_lag_id
1253  * LAG ID to flush, pointed to by FID.
1254  * Access: RW
1255  */
1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1257 
1258 /* SLDR - Switch LAG Descriptor Register
1259  * -----------------------------------------
1260  * The switch LAG descriptor register is populated by LAG descriptors.
1261  * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1262  * max_lag-1.
1263  */
1264 #define MLXSW_REG_SLDR_ID 0x2014
1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1266 
1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1268 
1269 enum mlxsw_reg_sldr_op {
1270         /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1271         MLXSW_REG_SLDR_OP_LAG_CREATE,
1272         MLXSW_REG_SLDR_OP_LAG_DESTROY,
1273         /* Ports that appear in the list have the Distributor enabled */
1274         MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1275         /* Removes ports from the disributor list */
1276         MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1277 };
1278 
1279 /* reg_sldr_op
1280  * Operation.
1281  * Access: RW
1282  */
1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1284 
1285 /* reg_sldr_lag_id
1286  * LAG identifier. The lag_id is the index into the LAG descriptor table.
1287  * Access: Index
1288  */
1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1290 
1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1292 {
1293         MLXSW_REG_ZERO(sldr, payload);
1294         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1295         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1296 }
1297 
1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1299 {
1300         MLXSW_REG_ZERO(sldr, payload);
1301         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1302         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1303 }
1304 
1305 /* reg_sldr_num_ports
1306  * The number of member ports of the LAG.
1307  * Reserved for Create / Destroy operations
1308  * For Add / Remove operations - indicates the number of ports in the list.
1309  * Access: RW
1310  */
1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1312 
1313 /* reg_sldr_system_port
1314  * System port.
1315  * Access: RW
1316  */
1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1318 
1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1320                                                     u8 local_port)
1321 {
1322         MLXSW_REG_ZERO(sldr, payload);
1323         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1324         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1325         mlxsw_reg_sldr_num_ports_set(payload, 1);
1326         mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1327 }
1328 
1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1330                                                        u8 local_port)
1331 {
1332         MLXSW_REG_ZERO(sldr, payload);
1333         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1334         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1335         mlxsw_reg_sldr_num_ports_set(payload, 1);
1336         mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1337 }
1338 
1339 /* SLCR - Switch LAG Configuration 2 Register
1340  * -------------------------------------------
1341  * The Switch LAG Configuration register is used for configuring the
1342  * LAG properties of the switch.
1343  */
1344 #define MLXSW_REG_SLCR_ID 0x2015
1345 #define MLXSW_REG_SLCR_LEN 0x10
1346 
1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1348 
1349 enum mlxsw_reg_slcr_pp {
1350         /* Global Configuration (for all ports) */
1351         MLXSW_REG_SLCR_PP_GLOBAL,
1352         /* Per port configuration, based on local_port field */
1353         MLXSW_REG_SLCR_PP_PER_PORT,
1354 };
1355 
1356 /* reg_slcr_pp
1357  * Per Port Configuration
1358  * Note: Reading at Global mode results in reading port 1 configuration.
1359  * Access: Index
1360  */
1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1362 
1363 /* reg_slcr_local_port
1364  * Local port number
1365  * Supported from CPU port
1366  * Not supported from router port
1367  * Reserved when pp = Global Configuration
1368  * Access: Index
1369  */
1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1371 
1372 enum mlxsw_reg_slcr_type {
1373         MLXSW_REG_SLCR_TYPE_CRC, /* default */
1374         MLXSW_REG_SLCR_TYPE_XOR,
1375         MLXSW_REG_SLCR_TYPE_RANDOM,
1376 };
1377 
1378 /* reg_slcr_type
1379  * Hash type
1380  * Access: RW
1381  */
1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1383 
1384 /* Ingress port */
1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT         BIT(0)
1386 /* SMAC - for IPv4 and IPv6 packets */
1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP         BIT(1)
1388 /* SMAC - for non-IP packets */
1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP      BIT(2)
1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1391         (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1392          MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1393 /* DMAC - for IPv4 and IPv6 packets */
1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP         BIT(3)
1395 /* DMAC - for non-IP packets */
1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP      BIT(4)
1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1398         (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1399          MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1400 /* Ethertype - for IPv4 and IPv6 packets */
1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP    BIT(5)
1402 /* Ethertype - for non-IP packets */
1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1405         (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1406          MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1407 /* VLAN ID - for IPv4 and IPv6 packets */
1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP       BIT(7)
1409 /* VLAN ID - for non-IP packets */
1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP    BIT(8)
1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1412         (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1413          MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1414 /* Source IP address (can be IPv4 or IPv6) */
1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP             BIT(9)
1416 /* Destination IP address (can be IPv4 or IPv6) */
1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP             BIT(10)
1418 /* TCP/UDP source port */
1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT           BIT(11)
1420 /* TCP/UDP destination port*/
1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT           BIT(12)
1422 /* IPv4 Protocol/IPv6 Next Header */
1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO         BIT(13)
1424 /* IPv6 Flow label */
1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL       BIT(14)
1426 /* SID - FCoE source ID */
1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID        BIT(15)
1428 /* DID - FCoE destination ID */
1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID        BIT(16)
1430 /* OXID - FCoE originator exchange ID */
1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID       BIT(17)
1432 /* Destination QP number - for RoCE packets */
1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP        BIT(19)
1434 
1435 /* reg_slcr_lag_hash
1436  * LAG hashing configuration. This is a bitmask, in which each set
1437  * bit includes the corresponding item in the LAG hash calculation.
1438  * The default lag_hash contains SMAC, DMAC, VLANID and
1439  * Ethertype (for all packet types).
1440  * Access: RW
1441  */
1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1443 
1444 /* reg_slcr_seed
1445  * LAG seed value. The seed is the same for all ports.
1446  * Access: RW
1447  */
1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1449 
1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1451 {
1452         MLXSW_REG_ZERO(slcr, payload);
1453         mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1454         mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1455         mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1456         mlxsw_reg_slcr_seed_set(payload, seed);
1457 }
1458 
1459 /* SLCOR - Switch LAG Collector Register
1460  * -------------------------------------
1461  * The Switch LAG Collector register controls the Local Port membership
1462  * in a LAG and enablement of the collector.
1463  */
1464 #define MLXSW_REG_SLCOR_ID 0x2016
1465 #define MLXSW_REG_SLCOR_LEN 0x10
1466 
1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1468 
1469 enum mlxsw_reg_slcor_col {
1470         /* Port is added with collector disabled */
1471         MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1472         MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1473         MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1474         MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1475 };
1476 
1477 /* reg_slcor_col
1478  * Collector configuration
1479  * Access: RW
1480  */
1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1482 
1483 /* reg_slcor_local_port
1484  * Local port number
1485  * Not supported for CPU port
1486  * Access: Index
1487  */
1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1489 
1490 /* reg_slcor_lag_id
1491  * LAG Identifier. Index into the LAG descriptor table.
1492  * Access: Index
1493  */
1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1495 
1496 /* reg_slcor_port_index
1497  * Port index in the LAG list. Only valid on Add Port to LAG col.
1498  * Valid range is from 0 to cap_max_lag_members-1
1499  * Access: RW
1500  */
1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1502 
1503 static inline void mlxsw_reg_slcor_pack(char *payload,
1504                                         u8 local_port, u16 lag_id,
1505                                         enum mlxsw_reg_slcor_col col)
1506 {
1507         MLXSW_REG_ZERO(slcor, payload);
1508         mlxsw_reg_slcor_col_set(payload, col);
1509         mlxsw_reg_slcor_local_port_set(payload, local_port);
1510         mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1511 }
1512 
1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1514                                                  u8 local_port, u16 lag_id,
1515                                                  u8 port_index)
1516 {
1517         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1518                              MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1519         mlxsw_reg_slcor_port_index_set(payload, port_index);
1520 }
1521 
1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1523                                                     u8 local_port, u16 lag_id)
1524 {
1525         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1526                              MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1527 }
1528 
1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1530                                                    u8 local_port, u16 lag_id)
1531 {
1532         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1533                              MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1534 }
1535 
1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1537                                                     u8 local_port, u16 lag_id)
1538 {
1539         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1540                              MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1541 }
1542 
1543 /* SPMLR - Switch Port MAC Learning Register
1544  * -----------------------------------------
1545  * Controls the Switch MAC learning policy per port.
1546  */
1547 #define MLXSW_REG_SPMLR_ID 0x2018
1548 #define MLXSW_REG_SPMLR_LEN 0x8
1549 
1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1551 
1552 /* reg_spmlr_local_port
1553  * Local port number.
1554  * Access: Index
1555  */
1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1557 
1558 /* reg_spmlr_sub_port
1559  * Virtual port within the physical port.
1560  * Should be set to 0 when virtual ports are not enabled on the port.
1561  * Access: Index
1562  */
1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1564 
1565 enum mlxsw_reg_spmlr_learn_mode {
1566         MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1567         MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1568         MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1569 };
1570 
1571 /* reg_spmlr_learn_mode
1572  * Learning mode on the port.
1573  * 0 - Learning disabled.
1574  * 2 - Learning enabled.
1575  * 3 - Security mode.
1576  *
1577  * In security mode the switch does not learn MACs on the port, but uses the
1578  * SMAC to see if it exists on another ingress port. If so, the packet is
1579  * classified as a bad packet and is discarded unless the software registers
1580  * to receive port security error packets usign HPKT.
1581  */
1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1583 
1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1585                                         enum mlxsw_reg_spmlr_learn_mode mode)
1586 {
1587         MLXSW_REG_ZERO(spmlr, payload);
1588         mlxsw_reg_spmlr_local_port_set(payload, local_port);
1589         mlxsw_reg_spmlr_sub_port_set(payload, 0);
1590         mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1591 }
1592 
1593 /* SVFA - Switch VID to FID Allocation Register
1594  * --------------------------------------------
1595  * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1596  * virtualized ports.
1597  */
1598 #define MLXSW_REG_SVFA_ID 0x201C
1599 #define MLXSW_REG_SVFA_LEN 0x10
1600 
1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1602 
1603 /* reg_svfa_swid
1604  * Switch partition ID.
1605  * Access: Index
1606  */
1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1608 
1609 /* reg_svfa_local_port
1610  * Local port number.
1611  * Access: Index
1612  *
1613  * Note: Reserved for 802.1Q FIDs.
1614  */
1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1616 
1617 enum mlxsw_reg_svfa_mt {
1618         MLXSW_REG_SVFA_MT_VID_TO_FID,
1619         MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1620 };
1621 
1622 /* reg_svfa_mapping_table
1623  * Mapping table:
1624  * 0 - VID to FID
1625  * 1 - {Port, VID} to FID
1626  * Access: Index
1627  *
1628  * Note: Reserved for SwitchX-2.
1629  */
1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1631 
1632 /* reg_svfa_v
1633  * Valid.
1634  * Valid if set.
1635  * Access: RW
1636  *
1637  * Note: Reserved for SwitchX-2.
1638  */
1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1640 
1641 /* reg_svfa_fid
1642  * Filtering ID.
1643  * Access: RW
1644  */
1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1646 
1647 /* reg_svfa_vid
1648  * VLAN ID.
1649  * Access: Index
1650  */
1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1652 
1653 /* reg_svfa_counter_set_type
1654  * Counter set type for flow counters.
1655  * Access: RW
1656  *
1657  * Note: Reserved for SwitchX-2.
1658  */
1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1660 
1661 /* reg_svfa_counter_index
1662  * Counter index for flow counters.
1663  * Access: RW
1664  *
1665  * Note: Reserved for SwitchX-2.
1666  */
1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1668 
1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1670                                        enum mlxsw_reg_svfa_mt mt, bool valid,
1671                                        u16 fid, u16 vid)
1672 {
1673         MLXSW_REG_ZERO(svfa, payload);
1674         local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1675         mlxsw_reg_svfa_swid_set(payload, 0);
1676         mlxsw_reg_svfa_local_port_set(payload, local_port);
1677         mlxsw_reg_svfa_mapping_table_set(payload, mt);
1678         mlxsw_reg_svfa_v_set(payload, valid);
1679         mlxsw_reg_svfa_fid_set(payload, fid);
1680         mlxsw_reg_svfa_vid_set(payload, vid);
1681 }
1682 
1683 /* SVPE - Switch Virtual-Port Enabling Register
1684  * --------------------------------------------
1685  * Enables port virtualization.
1686  */
1687 #define MLXSW_REG_SVPE_ID 0x201E
1688 #define MLXSW_REG_SVPE_LEN 0x4
1689 
1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1691 
1692 /* reg_svpe_local_port
1693  * Local port number
1694  * Access: Index
1695  *
1696  * Note: CPU port is not supported (uses VLAN mode only).
1697  */
1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1699 
1700 /* reg_svpe_vp_en
1701  * Virtual port enable.
1702  * 0 - Disable, VLAN mode (VID to FID).
1703  * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1704  * Access: RW
1705  */
1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1707 
1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1709                                        bool enable)
1710 {
1711         MLXSW_REG_ZERO(svpe, payload);
1712         mlxsw_reg_svpe_local_port_set(payload, local_port);
1713         mlxsw_reg_svpe_vp_en_set(payload, enable);
1714 }
1715 
1716 /* SFMR - Switch FID Management Register
1717  * -------------------------------------
1718  * Creates and configures FIDs.
1719  */
1720 #define MLXSW_REG_SFMR_ID 0x201F
1721 #define MLXSW_REG_SFMR_LEN 0x18
1722 
1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1724 
1725 enum mlxsw_reg_sfmr_op {
1726         MLXSW_REG_SFMR_OP_CREATE_FID,
1727         MLXSW_REG_SFMR_OP_DESTROY_FID,
1728 };
1729 
1730 /* reg_sfmr_op
1731  * Operation.
1732  * 0 - Create or edit FID.
1733  * 1 - Destroy FID.
1734  * Access: WO
1735  */
1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1737 
1738 /* reg_sfmr_fid
1739  * Filtering ID.
1740  * Access: Index
1741  */
1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1743 
1744 /* reg_sfmr_fid_offset
1745  * FID offset.
1746  * Used to point into the flooding table selected by SFGC register if
1747  * the table is of type FID-Offset. Otherwise, this field is reserved.
1748  * Access: RW
1749  */
1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1751 
1752 /* reg_sfmr_vtfp
1753  * Valid Tunnel Flood Pointer.
1754  * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1755  * Access: RW
1756  *
1757  * Note: Reserved for 802.1Q FIDs.
1758  */
1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1760 
1761 /* reg_sfmr_nve_tunnel_flood_ptr
1762  * Underlay Flooding and BC Pointer.
1763  * Used as a pointer to the first entry of the group based link lists of
1764  * flooding or BC entries (for NVE tunnels).
1765  * Access: RW
1766  */
1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1768 
1769 /* reg_sfmr_vv
1770  * VNI Valid.
1771  * If not set, then vni is reserved.
1772  * Access: RW
1773  *
1774  * Note: Reserved for 802.1Q FIDs.
1775  */
1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1777 
1778 /* reg_sfmr_vni
1779  * Virtual Network Identifier.
1780  * Access: RW
1781  *
1782  * Note: A given VNI can only be assigned to one FID.
1783  */
1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1785 
1786 static inline void mlxsw_reg_sfmr_pack(char *payload,
1787                                        enum mlxsw_reg_sfmr_op op, u16 fid,
1788                                        u16 fid_offset)
1789 {
1790         MLXSW_REG_ZERO(sfmr, payload);
1791         mlxsw_reg_sfmr_op_set(payload, op);
1792         mlxsw_reg_sfmr_fid_set(payload, fid);
1793         mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1794         mlxsw_reg_sfmr_vtfp_set(payload, false);
1795         mlxsw_reg_sfmr_vv_set(payload, false);
1796 }
1797 
1798 /* SPVMLR - Switch Port VLAN MAC Learning Register
1799  * -----------------------------------------------
1800  * Controls the switch MAC learning policy per {Port, VID}.
1801  */
1802 #define MLXSW_REG_SPVMLR_ID 0x2020
1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1807                               MLXSW_REG_SPVMLR_REC_LEN * \
1808                               MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1809 
1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1811 
1812 /* reg_spvmlr_local_port
1813  * Local ingress port.
1814  * Access: Index
1815  *
1816  * Note: CPU port is not supported.
1817  */
1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1819 
1820 /* reg_spvmlr_num_rec
1821  * Number of records to update.
1822  * Access: OP
1823  */
1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1825 
1826 /* reg_spvmlr_rec_learn_enable
1827  * 0 - Disable learning for {Port, VID}.
1828  * 1 - Enable learning for {Port, VID}.
1829  * Access: RW
1830  */
1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1832                      31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1833 
1834 /* reg_spvmlr_rec_vid
1835  * VLAN ID to be added/removed from port or for querying.
1836  * Access: Index
1837  */
1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1839                      MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1840 
1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1842                                          u16 vid_begin, u16 vid_end,
1843                                          bool learn_enable)
1844 {
1845         int num_rec = vid_end - vid_begin + 1;
1846         int i;
1847 
1848         WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1849 
1850         MLXSW_REG_ZERO(spvmlr, payload);
1851         mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1852         mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1853 
1854         for (i = 0; i < num_rec; i++) {
1855                 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1856                 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1857         }
1858 }
1859 
1860 /* CWTP - Congetion WRED ECN TClass Profile
1861  * ----------------------------------------
1862  * Configures the profiles for queues of egress port and traffic class
1863  */
1864 #define MLXSW_REG_CWTP_ID 0x2802
1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28
1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
1867 #define MLXSW_REG_CWTP_LEN 0x40
1868 
1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
1870 
1871 /* reg_cwtp_local_port
1872  * Local port number
1873  * Not supported for CPU port
1874  * Access: Index
1875  */
1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
1877 
1878 /* reg_cwtp_traffic_class
1879  * Traffic Class to configure
1880  * Access: Index
1881  */
1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
1883 
1884 /* reg_cwtp_profile_min
1885  * Minimum Average Queue Size of the profile in cells.
1886  * Access: RW
1887  */
1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
1889                      0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
1890 
1891 /* reg_cwtp_profile_percent
1892  * Percentage of WRED and ECN marking for maximum Average Queue size
1893  * Range is 0 to 100, units of integer percentage
1894  * Access: RW
1895  */
1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
1897                      24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1898 
1899 /* reg_cwtp_profile_max
1900  * Maximum Average Queue size of the profile in cells
1901  * Access: RW
1902  */
1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
1904                      0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1905 
1906 #define MLXSW_REG_CWTP_MIN_VALUE 64
1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2
1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
1909 
1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
1911                                        u8 traffic_class)
1912 {
1913         int i;
1914 
1915         MLXSW_REG_ZERO(cwtp, payload);
1916         mlxsw_reg_cwtp_local_port_set(payload, local_port);
1917         mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
1918 
1919         for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
1920                 mlxsw_reg_cwtp_profile_min_set(payload, i,
1921                                                MLXSW_REG_CWTP_MIN_VALUE);
1922                 mlxsw_reg_cwtp_profile_max_set(payload, i,
1923                                                MLXSW_REG_CWTP_MIN_VALUE);
1924         }
1925 }
1926 
1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
1928 
1929 static inline void
1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
1931                             u32 probability)
1932 {
1933         u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
1934 
1935         mlxsw_reg_cwtp_profile_min_set(payload, index, min);
1936         mlxsw_reg_cwtp_profile_max_set(payload, index, max);
1937         mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
1938 }
1939 
1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping
1941  * ---------------------------------------------------
1942  * The CWTPM register maps each egress port and traffic class to profile num.
1943  */
1944 #define MLXSW_REG_CWTPM_ID 0x2803
1945 #define MLXSW_REG_CWTPM_LEN 0x44
1946 
1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
1948 
1949 /* reg_cwtpm_local_port
1950  * Local port number
1951  * Not supported for CPU port
1952  * Access: Index
1953  */
1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
1955 
1956 /* reg_cwtpm_traffic_class
1957  * Traffic Class to configure
1958  * Access: Index
1959  */
1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
1961 
1962 /* reg_cwtpm_ew
1963  * Control enablement of WRED for traffic class:
1964  * 0 - Disable
1965  * 1 - Enable
1966  * Access: RW
1967  */
1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
1969 
1970 /* reg_cwtpm_ee
1971  * Control enablement of ECN for traffic class:
1972  * 0 - Disable
1973  * 1 - Enable
1974  * Access: RW
1975  */
1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
1977 
1978 /* reg_cwtpm_tcp_g
1979  * TCP Green Profile.
1980  * Index of the profile within {port, traffic class} to use.
1981  * 0 for disabling both WRED and ECN for this type of traffic.
1982  * Access: RW
1983  */
1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
1985 
1986 /* reg_cwtpm_tcp_y
1987  * TCP Yellow Profile.
1988  * Index of the profile within {port, traffic class} to use.
1989  * 0 for disabling both WRED and ECN for this type of traffic.
1990  * Access: RW
1991  */
1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
1993 
1994 /* reg_cwtpm_tcp_r
1995  * TCP Red Profile.
1996  * Index of the profile within {port, traffic class} to use.
1997  * 0 for disabling both WRED and ECN for this type of traffic.
1998  * Access: RW
1999  */
2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2001 
2002 /* reg_cwtpm_ntcp_g
2003  * Non-TCP Green Profile.
2004  * Index of the profile within {port, traffic class} to use.
2005  * 0 for disabling both WRED and ECN for this type of traffic.
2006  * Access: RW
2007  */
2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2009 
2010 /* reg_cwtpm_ntcp_y
2011  * Non-TCP Yellow Profile.
2012  * Index of the profile within {port, traffic class} to use.
2013  * 0 for disabling both WRED and ECN for this type of traffic.
2014  * Access: RW
2015  */
2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2017 
2018 /* reg_cwtpm_ntcp_r
2019  * Non-TCP Red Profile.
2020  * Index of the profile within {port, traffic class} to use.
2021  * 0 for disabling both WRED and ECN for this type of traffic.
2022  * Access: RW
2023  */
2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2025 
2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0
2027 
2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
2029                                         u8 traffic_class, u8 profile,
2030                                         bool wred, bool ecn)
2031 {
2032         MLXSW_REG_ZERO(cwtpm, payload);
2033         mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2034         mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2035         mlxsw_reg_cwtpm_ew_set(payload, wred);
2036         mlxsw_reg_cwtpm_ee_set(payload, ecn);
2037         mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2038         mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2039         mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2040         mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2041         mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2042         mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2043 }
2044 
2045 /* PGCR - Policy-Engine General Configuration Register
2046  * ---------------------------------------------------
2047  * This register configures general Policy-Engine settings.
2048  */
2049 #define MLXSW_REG_PGCR_ID 0x3001
2050 #define MLXSW_REG_PGCR_LEN 0x20
2051 
2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2053 
2054 /* reg_pgcr_default_action_pointer_base
2055  * Default action pointer base. Each region has a default action pointer
2056  * which is equal to default_action_pointer_base + region_id.
2057  * Access: RW
2058  */
2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2060 
2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2062 {
2063         MLXSW_REG_ZERO(pgcr, payload);
2064         mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2065 }
2066 
2067 /* PPBT - Policy-Engine Port Binding Table
2068  * ---------------------------------------
2069  * This register is used for configuration of the Port Binding Table.
2070  */
2071 #define MLXSW_REG_PPBT_ID 0x3002
2072 #define MLXSW_REG_PPBT_LEN 0x14
2073 
2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2075 
2076 enum mlxsw_reg_pxbt_e {
2077         MLXSW_REG_PXBT_E_IACL,
2078         MLXSW_REG_PXBT_E_EACL,
2079 };
2080 
2081 /* reg_ppbt_e
2082  * Access: Index
2083  */
2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2085 
2086 enum mlxsw_reg_pxbt_op {
2087         MLXSW_REG_PXBT_OP_BIND,
2088         MLXSW_REG_PXBT_OP_UNBIND,
2089 };
2090 
2091 /* reg_ppbt_op
2092  * Access: RW
2093  */
2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2095 
2096 /* reg_ppbt_local_port
2097  * Local port. Not including CPU port.
2098  * Access: Index
2099  */
2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
2101 
2102 /* reg_ppbt_g
2103  * group - When set, the binding is of an ACL group. When cleared,
2104  * the binding is of an ACL.
2105  * Must be set to 1 for Spectrum.
2106  * Access: RW
2107  */
2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2109 
2110 /* reg_ppbt_acl_info
2111  * ACL/ACL group identifier. If the g bit is set, this field should hold
2112  * the acl_group_id, else it should hold the acl_id.
2113  * Access: RW
2114  */
2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2116 
2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2118                                        enum mlxsw_reg_pxbt_op op,
2119                                        u8 local_port, u16 acl_info)
2120 {
2121         MLXSW_REG_ZERO(ppbt, payload);
2122         mlxsw_reg_ppbt_e_set(payload, e);
2123         mlxsw_reg_ppbt_op_set(payload, op);
2124         mlxsw_reg_ppbt_local_port_set(payload, local_port);
2125         mlxsw_reg_ppbt_g_set(payload, true);
2126         mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2127 }
2128 
2129 /* PACL - Policy-Engine ACL Register
2130  * ---------------------------------
2131  * This register is used for configuration of the ACL.
2132  */
2133 #define MLXSW_REG_PACL_ID 0x3004
2134 #define MLXSW_REG_PACL_LEN 0x70
2135 
2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2137 
2138 /* reg_pacl_v
2139  * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2140  * while the ACL is bounded to either a port, VLAN or ACL rule.
2141  * Access: RW
2142  */
2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2144 
2145 /* reg_pacl_acl_id
2146  * An identifier representing the ACL (managed by software)
2147  * Range 0 .. cap_max_acl_regions - 1
2148  * Access: Index
2149  */
2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2151 
2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2153 
2154 /* reg_pacl_tcam_region_info
2155  * Opaque object that represents a TCAM region.
2156  * Obtained through PTAR register.
2157  * Access: RW
2158  */
2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2160                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2161 
2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2163                                        bool valid, const char *tcam_region_info)
2164 {
2165         MLXSW_REG_ZERO(pacl, payload);
2166         mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2167         mlxsw_reg_pacl_v_set(payload, valid);
2168         mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2169 }
2170 
2171 /* PAGT - Policy-Engine ACL Group Table
2172  * ------------------------------------
2173  * This register is used for configuration of the ACL Group Table.
2174  */
2175 #define MLXSW_REG_PAGT_ID 0x3005
2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30
2177 #define MLXSW_REG_PAGT_ACL_LEN 4
2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2180                 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2181 
2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2183 
2184 /* reg_pagt_size
2185  * Number of ACLs in the group.
2186  * Size 0 invalidates a group.
2187  * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2188  * Total number of ACLs in all groups must be lower or equal
2189  * to cap_max_acl_tot_groups
2190  * Note: a group which is binded must not be invalidated
2191  * Access: Index
2192  */
2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2194 
2195 /* reg_pagt_acl_group_id
2196  * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2197  * the ACL Group identifier (managed by software).
2198  * Access: Index
2199  */
2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2201 
2202 /* reg_pagt_multi
2203  * Multi-ACL
2204  * 0 - This ACL is the last ACL in the multi-ACL
2205  * 1 - This ACL is part of a multi-ACL
2206  * Access: RW
2207  */
2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2209 
2210 /* reg_pagt_acl_id
2211  * ACL identifier
2212  * Access: RW
2213  */
2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2215 
2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2217 {
2218         MLXSW_REG_ZERO(pagt, payload);
2219         mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2220 }
2221 
2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2223                                               u16 acl_id, bool multi)
2224 {
2225         u8 size = mlxsw_reg_pagt_size_get(payload);
2226 
2227         if (index >= size)
2228                 mlxsw_reg_pagt_size_set(payload, index + 1);
2229         mlxsw_reg_pagt_multi_set(payload, index, multi);
2230         mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2231 }
2232 
2233 /* PTAR - Policy-Engine TCAM Allocation Register
2234  * ---------------------------------------------
2235  * This register is used for allocation of regions in the TCAM.
2236  * Note: Query method is not supported on this register.
2237  */
2238 #define MLXSW_REG_PTAR_ID 0x3006
2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20
2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1
2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2243                 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2244 
2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2246 
2247 enum mlxsw_reg_ptar_op {
2248         /* allocate a TCAM region */
2249         MLXSW_REG_PTAR_OP_ALLOC,
2250         /* resize a TCAM region */
2251         MLXSW_REG_PTAR_OP_RESIZE,
2252         /* deallocate TCAM region */
2253         MLXSW_REG_PTAR_OP_FREE,
2254         /* test allocation */
2255         MLXSW_REG_PTAR_OP_TEST,
2256 };
2257 
2258 /* reg_ptar_op
2259  * Access: OP
2260  */
2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2262 
2263 /* reg_ptar_action_set_type
2264  * Type of action set to be used on this region.
2265  * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2266  * Access: WO
2267  */
2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2269 
2270 enum mlxsw_reg_ptar_key_type {
2271         MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2272         MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2273 };
2274 
2275 /* reg_ptar_key_type
2276  * TCAM key type for the region.
2277  * Access: WO
2278  */
2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2280 
2281 /* reg_ptar_region_size
2282  * TCAM region size. When allocating/resizing this is the requested size,
2283  * the response is the actual size. Note that actual size may be
2284  * larger than requested.
2285  * Allowed range 1 .. cap_max_rules-1
2286  * Reserved during op deallocate.
2287  * Access: WO
2288  */
2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2290 
2291 /* reg_ptar_region_id
2292  * Region identifier
2293  * Range 0 .. cap_max_regions-1
2294  * Access: Index
2295  */
2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2297 
2298 /* reg_ptar_tcam_region_info
2299  * Opaque object that represents the TCAM region.
2300  * Returned when allocating a region.
2301  * Provided by software for ACL generation and region deallocation and resize.
2302  * Access: RW
2303  */
2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2305                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2306 
2307 /* reg_ptar_flexible_key_id
2308  * Identifier of the Flexible Key.
2309  * Only valid if key_type == "FLEX_KEY"
2310  * The key size will be rounded up to one of the following values:
2311  * 9B, 18B, 36B, 54B.
2312  * This field is reserved for in resize operation.
2313  * Access: WO
2314  */
2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2316                     MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2317 
2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2319                                        enum mlxsw_reg_ptar_key_type key_type,
2320                                        u16 region_size, u16 region_id,
2321                                        const char *tcam_region_info)
2322 {
2323         MLXSW_REG_ZERO(ptar, payload);
2324         mlxsw_reg_ptar_op_set(payload, op);
2325         mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */
2326         mlxsw_reg_ptar_key_type_set(payload, key_type);
2327         mlxsw_reg_ptar_region_size_set(payload, region_size);
2328         mlxsw_reg_ptar_region_id_set(payload, region_id);
2329         mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2330 }
2331 
2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2333                                               u16 key_id)
2334 {
2335         mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2336 }
2337 
2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2339 {
2340         mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2341 }
2342 
2343 /* PPBS - Policy-Engine Policy Based Switching Register
2344  * ----------------------------------------------------
2345  * This register retrieves and sets Policy Based Switching Table entries.
2346  */
2347 #define MLXSW_REG_PPBS_ID 0x300C
2348 #define MLXSW_REG_PPBS_LEN 0x14
2349 
2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2351 
2352 /* reg_ppbs_pbs_ptr
2353  * Index into the PBS table.
2354  * For Spectrum, the index points to the KVD Linear.
2355  * Access: Index
2356  */
2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2358 
2359 /* reg_ppbs_system_port
2360  * Unique port identifier for the final destination of the packet.
2361  * Access: RW
2362  */
2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2364 
2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2366                                        u16 system_port)
2367 {
2368         MLXSW_REG_ZERO(ppbs, payload);
2369         mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2370         mlxsw_reg_ppbs_system_port_set(payload, system_port);
2371 }
2372 
2373 /* PRCR - Policy-Engine Rules Copy Register
2374  * ----------------------------------------
2375  * This register is used for accessing rules within a TCAM region.
2376  */
2377 #define MLXSW_REG_PRCR_ID 0x300D
2378 #define MLXSW_REG_PRCR_LEN 0x40
2379 
2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2381 
2382 enum mlxsw_reg_prcr_op {
2383         /* Move rules. Moves the rules from "tcam_region_info" starting
2384          * at offset "offset" to "dest_tcam_region_info"
2385          * at offset "dest_offset."
2386          */
2387         MLXSW_REG_PRCR_OP_MOVE,
2388         /* Copy rules. Copies the rules from "tcam_region_info" starting
2389          * at offset "offset" to "dest_tcam_region_info"
2390          * at offset "dest_offset."
2391          */
2392         MLXSW_REG_PRCR_OP_COPY,
2393 };
2394 
2395 /* reg_prcr_op
2396  * Access: OP
2397  */
2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2399 
2400 /* reg_prcr_offset
2401  * Offset within the source region to copy/move from.
2402  * Access: Index
2403  */
2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2405 
2406 /* reg_prcr_size
2407  * The number of rules to copy/move.
2408  * Access: WO
2409  */
2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2411 
2412 /* reg_prcr_tcam_region_info
2413  * Opaque object that represents the source TCAM region.
2414  * Access: Index
2415  */
2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2417                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2418 
2419 /* reg_prcr_dest_offset
2420  * Offset within the source region to copy/move to.
2421  * Access: Index
2422  */
2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2424 
2425 /* reg_prcr_dest_tcam_region_info
2426  * Opaque object that represents the destination TCAM region.
2427  * Access: Index
2428  */
2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2430                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2431 
2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2433                                        const char *src_tcam_region_info,
2434                                        u16 src_offset,
2435                                        const char *dest_tcam_region_info,
2436                                        u16 dest_offset, u16 size)
2437 {
2438         MLXSW_REG_ZERO(prcr, payload);
2439         mlxsw_reg_prcr_op_set(payload, op);
2440         mlxsw_reg_prcr_offset_set(payload, src_offset);
2441         mlxsw_reg_prcr_size_set(payload, size);
2442         mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2443                                                   src_tcam_region_info);
2444         mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2445         mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2446                                                        dest_tcam_region_info);
2447 }
2448 
2449 /* PEFA - Policy-Engine Extended Flexible Action Register
2450  * ------------------------------------------------------
2451  * This register is used for accessing an extended flexible action entry
2452  * in the central KVD Linear Database.
2453  */
2454 #define MLXSW_REG_PEFA_ID 0x300F
2455 #define MLXSW_REG_PEFA_LEN 0xB0
2456 
2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2458 
2459 /* reg_pefa_index
2460  * Index in the KVD Linear Centralized Database.
2461  * Access: Index
2462  */
2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2464 
2465 /* reg_pefa_a
2466  * Index in the KVD Linear Centralized Database.
2467  * Activity
2468  * For a new entry: set if ca=0, clear if ca=1
2469  * Set if a packet lookup has hit on the specific entry
2470  * Access: RO
2471  */
2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2473 
2474 /* reg_pefa_ca
2475  * Clear activity
2476  * When write: activity is according to this field
2477  * When read: after reading the activity is cleared according to ca
2478  * Access: OP
2479  */
2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2481 
2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2483 
2484 /* reg_pefa_flex_action_set
2485  * Action-set to perform when rule is matched.
2486  * Must be zero padded if action set is shorter.
2487  * Access: RW
2488  */
2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2490 
2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2492                                        const char *flex_action_set)
2493 {
2494         MLXSW_REG_ZERO(pefa, payload);
2495         mlxsw_reg_pefa_index_set(payload, index);
2496         mlxsw_reg_pefa_ca_set(payload, ca);
2497         if (flex_action_set)
2498                 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2499                                                          flex_action_set);
2500 }
2501 
2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2503 {
2504         *p_a = mlxsw_reg_pefa_a_get(payload);
2505 }
2506 
2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register
2508  * --------------------------------------------------------------
2509  * This register is used for binding Multicast router to an ACL group
2510  * that serves the MC router.
2511  * This register is not supported by SwitchX/-2 and Spectrum.
2512  */
2513 #define MLXSW_REG_PEMRBT_ID 0x3014
2514 #define MLXSW_REG_PEMRBT_LEN 0x14
2515 
2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
2517 
2518 enum mlxsw_reg_pemrbt_protocol {
2519         MLXSW_REG_PEMRBT_PROTO_IPV4,
2520         MLXSW_REG_PEMRBT_PROTO_IPV6,
2521 };
2522 
2523 /* reg_pemrbt_protocol
2524  * Access: Index
2525  */
2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
2527 
2528 /* reg_pemrbt_group_id
2529  * ACL group identifier.
2530  * Range 0..cap_max_acl_groups-1
2531  * Access: RW
2532  */
2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
2534 
2535 static inline void
2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
2537                       u16 group_id)
2538 {
2539         MLXSW_REG_ZERO(pemrbt, payload);
2540         mlxsw_reg_pemrbt_protocol_set(payload, protocol);
2541         mlxsw_reg_pemrbt_group_id_set(payload, group_id);
2542 }
2543 
2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2545  * -----------------------------------------------------
2546  * This register is used for accessing rules within a TCAM region.
2547  * It is a new version of PTCE in order to support wider key,
2548  * mask and action within a TCAM region. This register is not supported
2549  * by SwitchX and SwitchX-2.
2550  */
2551 #define MLXSW_REG_PTCE2_ID 0x3017
2552 #define MLXSW_REG_PTCE2_LEN 0x1D8
2553 
2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2555 
2556 /* reg_ptce2_v
2557  * Valid.
2558  * Access: RW
2559  */
2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2561 
2562 /* reg_ptce2_a
2563  * Activity. Set if a packet lookup has hit on the specific entry.
2564  * To clear the "a" bit, use "clear activity" op or "clear on read" op.
2565  * Access: RO
2566  */
2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2568 
2569 enum mlxsw_reg_ptce2_op {
2570         /* Read operation. */
2571         MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2572         /* clear on read operation. Used to read entry
2573          * and clear Activity bit.
2574          */
2575         MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2576         /* Write operation. Used to write a new entry to the table.
2577          * All R/W fields are relevant for new entry. Activity bit is set
2578          * for new entries - Note write with v = 0 will delete the entry.
2579          */
2580         MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2581         /* Update action. Only action set will be updated. */
2582         MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2583         /* Clear activity. A bit is cleared for the entry. */
2584         MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2585 };
2586 
2587 /* reg_ptce2_op
2588  * Access: OP
2589  */
2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2591 
2592 /* reg_ptce2_offset
2593  * Access: Index
2594  */
2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2596 
2597 /* reg_ptce2_priority
2598  * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
2599  * Note: priority does not have to be unique per rule.
2600  * Within a region, higher priority should have lower offset (no limitation
2601  * between regions in a multi-region).
2602  * Access: RW
2603  */
2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2605 
2606 /* reg_ptce2_tcam_region_info
2607  * Opaque object that represents the TCAM region.
2608  * Access: Index
2609  */
2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2611                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2612 
2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2614 
2615 /* reg_ptce2_flex_key_blocks
2616  * ACL Key.
2617  * Access: RW
2618  */
2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2620                MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2621 
2622 /* reg_ptce2_mask
2623  * mask- in the same size as key. A bit that is set directs the TCAM
2624  * to compare the corresponding bit in key. A bit that is clear directs
2625  * the TCAM to ignore the corresponding bit in key.
2626  * Access: RW
2627  */
2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2629                MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2630 
2631 /* reg_ptce2_flex_action_set
2632  * ACL action set.
2633  * Access: RW
2634  */
2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2636                MLXSW_REG_FLEX_ACTION_SET_LEN);
2637 
2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2639                                         enum mlxsw_reg_ptce2_op op,
2640                                         const char *tcam_region_info,
2641                                         u16 offset, u32 priority)
2642 {
2643         MLXSW_REG_ZERO(ptce2, payload);
2644         mlxsw_reg_ptce2_v_set(payload, valid);
2645         mlxsw_reg_ptce2_op_set(payload, op);
2646         mlxsw_reg_ptce2_offset_set(payload, offset);
2647         mlxsw_reg_ptce2_priority_set(payload, priority);
2648         mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2649 }
2650 
2651 /* PERPT - Policy-Engine ERP Table Register
2652  * ----------------------------------------
2653  * This register adds and removes eRPs from the eRP table.
2654  */
2655 #define MLXSW_REG_PERPT_ID 0x3021
2656 #define MLXSW_REG_PERPT_LEN 0x80
2657 
2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2659 
2660 /* reg_perpt_erpt_bank
2661  * eRP table bank.
2662  * Range 0 .. cap_max_erp_table_banks - 1
2663  * Access: Index
2664  */
2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2666 
2667 /* reg_perpt_erpt_index
2668  * Index to eRP table within the eRP bank.
2669  * Range is 0 .. cap_max_erp_table_bank_size - 1
2670  * Access: Index
2671  */
2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2673 
2674 enum mlxsw_reg_perpt_key_size {
2675         MLXSW_REG_PERPT_KEY_SIZE_2KB,
2676         MLXSW_REG_PERPT_KEY_SIZE_4KB,
2677         MLXSW_REG_PERPT_KEY_SIZE_8KB,
2678         MLXSW_REG_PERPT_KEY_SIZE_12KB,
2679 };
2680 
2681 /* reg_perpt_key_size
2682  * Access: OP
2683  */
2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2685 
2686 /* reg_perpt_bf_bypass
2687  * 0 - The eRP is used only if bloom filter state is set for the given
2688  * rule.
2689  * 1 - The eRP is used regardless of bloom filter state.
2690  * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
2691  * Access: RW
2692  */
2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2694 
2695 /* reg_perpt_erp_id
2696  * eRP ID for use by the rules.
2697  * Access: RW
2698  */
2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2700 
2701 /* reg_perpt_erpt_base_bank
2702  * Base eRP table bank, points to head of erp_vector
2703  * Range is 0 .. cap_max_erp_table_banks - 1
2704  * Access: OP
2705  */
2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2707 
2708 /* reg_perpt_erpt_base_index
2709  * Base index to eRP table within the eRP bank
2710  * Range is 0 .. cap_max_erp_table_bank_size - 1
2711  * Access: OP
2712  */
2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2714 
2715 /* reg_perpt_erp_index_in_vector
2716  * eRP index in the vector.
2717  * Access: OP
2718  */
2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2720 
2721 /* reg_perpt_erp_vector
2722  * eRP vector.
2723  * Access: OP
2724  */
2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2726 
2727 /* reg_perpt_mask
2728  * Mask
2729  * 0 - A-TCAM will ignore the bit in key
2730  * 1 - A-TCAM will compare the bit in key
2731  * Access: RW
2732  */
2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2734 
2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
2736                                                    unsigned long *erp_vector,
2737                                                    unsigned long size)
2738 {
2739         unsigned long bit;
2740 
2741         for_each_set_bit(bit, erp_vector, size)
2742                 mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
2743 }
2744 
2745 static inline void
2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
2747                      enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
2748                      u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
2749                      char *mask)
2750 {
2751         MLXSW_REG_ZERO(perpt, payload);
2752         mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
2753         mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
2754         mlxsw_reg_perpt_key_size_set(payload, key_size);
2755         mlxsw_reg_perpt_bf_bypass_set(payload, false);
2756         mlxsw_reg_perpt_erp_id_set(payload, erp_id);
2757         mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
2758         mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
2759         mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
2760         mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
2761 }
2762 
2763 /* PERAR - Policy-Engine Region Association Register
2764  * -------------------------------------------------
2765  * This register associates a hw region for region_id's. Changing on the fly
2766  * is supported by the device.
2767  */
2768 #define MLXSW_REG_PERAR_ID 0x3026
2769 #define MLXSW_REG_PERAR_LEN 0x08
2770 
2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
2772 
2773 /* reg_perar_region_id
2774  * Region identifier
2775  * Range 0 .. cap_max_regions-1
2776  * Access: Index
2777  */
2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
2779 
2780 static inline unsigned int
2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
2782 {
2783         return DIV_ROUND_UP(block_num, 4);
2784 }
2785 
2786 /* reg_perar_hw_region
2787  * HW Region
2788  * Range 0 .. cap_max_regions-1
2789  * Default: hw_region = region_id
2790  * For a 8 key block region, 2 consecutive regions are used
2791  * For a 12 key block region, 3 consecutive regions are used
2792  * Access: RW
2793  */
2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
2795 
2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
2797                                         u16 hw_region)
2798 {
2799         MLXSW_REG_ZERO(perar, payload);
2800         mlxsw_reg_perar_region_id_set(payload, region_id);
2801         mlxsw_reg_perar_hw_region_set(payload, hw_region);
2802 }
2803 
2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
2805  * -----------------------------------------------------
2806  * This register is a new version of PTCE-V2 in order to support the
2807  * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
2808  */
2809 #define MLXSW_REG_PTCE3_ID 0x3027
2810 #define MLXSW_REG_PTCE3_LEN 0xF0
2811 
2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
2813 
2814 /* reg_ptce3_v
2815  * Valid.
2816  * Access: RW
2817  */
2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
2819 
2820 enum mlxsw_reg_ptce3_op {
2821         /* Write operation. Used to write a new entry to the table.
2822          * All R/W fields are relevant for new entry. Activity bit is set
2823          * for new entries. Write with v = 0 will delete the entry. Must
2824          * not be used if an entry exists.
2825          */
2826          MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
2827          /* Update operation */
2828          MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
2829          /* Read operation */
2830          MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
2831 };
2832 
2833 /* reg_ptce3_op
2834  * Access: OP
2835  */
2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
2837 
2838 /* reg_ptce3_priority
2839  * Priority of the rule. Higher values win.
2840  * For Spectrum-2 range is 1..cap_kvd_size - 1
2841  * Note: Priority does not have to be unique per rule.
2842  * Access: RW
2843  */
2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
2845 
2846 /* reg_ptce3_tcam_region_info
2847  * Opaque object that represents the TCAM region.
2848  * Access: Index
2849  */
2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
2851                MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2852 
2853 /* reg_ptce3_flex2_key_blocks
2854  * ACL key. The key must be masked according to eRP (if exists) or
2855  * according to master mask.
2856  * Access: Index
2857  */
2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
2859                MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2860 
2861 /* reg_ptce3_erp_id
2862  * eRP ID.
2863  * Access: Index
2864  */
2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
2866 
2867 /* reg_ptce3_delta_start
2868  * Start point of delta_value and delta_mask, in bits. Must not exceed
2869  * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
2870  * Access: Index
2871  */
2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
2873 
2874 /* reg_ptce3_delta_mask
2875  * Delta mask.
2876  * 0 - Ignore relevant bit in delta_value
2877  * 1 - Compare relevant bit in delta_value
2878  * Delta mask must not be set for reserved fields in the key blocks.
2879  * Note: No delta when no eRPs. Thus, for regions with
2880  * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
2881  * Access: Index
2882  */
2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
2884 
2885 /* reg_ptce3_delta_value
2886  * Delta value.
2887  * Bits which are masked by delta_mask must be 0.
2888  * Access: Index
2889  */
2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
2891 
2892 /* reg_ptce3_prune_vector
2893  * Pruning vector relative to the PERPT.erp_id.
2894  * Used for reducing lookups.
2895  * 0 - NEED: Do a lookup using the eRP.
2896  * 1 - PRUNE: Do not perform a lookup using the eRP.
2897  * Maybe be modified by PEAPBL and PEAPBM.
2898  * Note: In Spectrum-2, a region of 8 key blocks must be set to either
2899  * all 1's or all 0's.
2900  * Access: RW
2901  */
2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
2903 
2904 /* reg_ptce3_prune_ctcam
2905  * Pruning on C-TCAM. Used for reducing lookups.
2906  * 0 - NEED: Do a lookup in the C-TCAM.
2907  * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
2908  * Access: RW
2909  */
2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
2911 
2912 /* reg_ptce3_large_exists
2913  * Large entry key ID exists.
2914  * Within the region:
2915  * 0 - SINGLE: The large_entry_key_id is not currently in use.
2916  * For rule insert: The MSB of the key (blocks 6..11) will be added.
2917  * For rule delete: The MSB of the key will be removed.
2918  * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
2919  * For rule insert: The MSB of the key (blocks 6..11) will not be added.
2920  * For rule delete: The MSB of the key will not be removed.
2921  * Access: WO
2922  */
2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
2924 
2925 /* reg_ptce3_large_entry_key_id
2926  * Large entry key ID.
2927  * A key for 12 key blocks rules. Reserved when region has less than 12 key
2928  * blocks. Must be different for different keys which have the same common
2929  * 6 key blocks (MSB, blocks 6..11) key within a region.
2930  * Range is 0..cap_max_pe_large_key_id - 1
2931  * Access: RW
2932  */
2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
2934 
2935 /* reg_ptce3_action_pointer
2936  * Pointer to action.
2937  * Range is 0..cap_max_kvd_action_sets - 1
2938  * Access: RW
2939  */
2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
2941 
2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
2943                                         enum mlxsw_reg_ptce3_op op,
2944                                         u32 priority,
2945                                         const char *tcam_region_info,
2946                                         const char *key, u8 erp_id,
2947                                         u16 delta_start, u8 delta_mask,
2948                                         u8 delta_value, bool large_exists,
2949                                         u32 lkey_id, u32 action_pointer)
2950 {
2951         MLXSW_REG_ZERO(ptce3, payload);
2952         mlxsw_reg_ptce3_v_set(payload, valid);
2953         mlxsw_reg_ptce3_op_set(payload, op);
2954         mlxsw_reg_ptce3_priority_set(payload, priority);
2955         mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
2956         mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
2957         mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
2958         mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
2959         mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
2960         mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
2961         mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
2962         mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
2963         mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
2964 }
2965 
2966 /* PERCR - Policy-Engine Region Configuration Register
2967  * ---------------------------------------------------
2968  * This register configures the region parameters. The region_id must be
2969  * allocated.
2970  */
2971 #define MLXSW_REG_PERCR_ID 0x302A
2972 #define MLXSW_REG_PERCR_LEN 0x80
2973 
2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
2975 
2976 /* reg_percr_region_id
2977  * Region identifier.
2978  * Range 0..cap_max_regions-1
2979  * Access: Index
2980  */
2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
2982 
2983 /* reg_percr_atcam_ignore_prune
2984  * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
2985  * Access: RW
2986  */
2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
2988 
2989 /* reg_percr_ctcam_ignore_prune
2990  * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
2991  * Access: RW
2992  */
2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
2994 
2995 /* reg_percr_bf_bypass
2996  * Bloom filter bypass.
2997  * 0 - Bloom filter is used (default)
2998  * 1 - Bloom filter is bypassed. The bypass is an OR condition of
2999  * region_id or eRP. See PERPT.bf_bypass
3000  * Access: RW
3001  */
3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3003 
3004 /* reg_percr_master_mask
3005  * Master mask. Logical OR mask of all masks of all rules of a region
3006  * (both A-TCAM and C-TCAM). When there are no eRPs
3007  * (erpt_pointer_valid = 0), then this provides the mask.
3008  * Access: RW
3009  */
3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3011 
3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3013 {
3014         MLXSW_REG_ZERO(percr, payload);
3015         mlxsw_reg_percr_region_id_set(payload, region_id);
3016         mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3017         mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3018         mlxsw_reg_percr_bf_bypass_set(payload, false);
3019 }
3020 
3021 /* PERERP - Policy-Engine Region eRP Register
3022  * ------------------------------------------
3023  * This register configures the region eRP. The region_id must be
3024  * allocated.
3025  */
3026 #define MLXSW_REG_PERERP_ID 0x302B
3027 #define MLXSW_REG_PERERP_LEN 0x1C
3028 
3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3030 
3031 /* reg_pererp_region_id
3032  * Region identifier.
3033  * Range 0..cap_max_regions-1
3034  * Access: Index
3035  */
3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3037 
3038 /* reg_pererp_ctcam_le
3039  * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
3040  * Access: RW
3041  */
3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3043 
3044 /* reg_pererp_erpt_pointer_valid
3045  * erpt_pointer is valid.
3046  * Access: RW
3047  */
3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3049 
3050 /* reg_pererp_erpt_bank_pointer
3051  * Pointer to eRP table bank. May be modified at any time.
3052  * Range 0..cap_max_erp_table_banks-1
3053  * Reserved when erpt_pointer_valid = 0
3054  */
3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3056 
3057 /* reg_pererp_erpt_pointer
3058  * Pointer to eRP table within the eRP bank. Can be changed for an
3059  * existing region.
3060  * Range 0..cap_max_erp_table_size-1
3061  * Reserved when erpt_pointer_valid = 0
3062  * Access: RW
3063  */
3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3065 
3066 /* reg_pererp_erpt_vector
3067  * Vector of allowed eRP indexes starting from erpt_pointer within the
3068  * erpt_bank_pointer. Next entries will be in next bank.
3069  * Note that eRP index is used and not eRP ID.
3070  * Reserved when erpt_pointer_valid = 0
3071  * Access: RW
3072  */
3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3074 
3075 /* reg_pererp_master_rp_id
3076  * Master RP ID. When there are no eRPs, then this provides the eRP ID
3077  * for the lookup. Can be changed for an existing region.
3078  * Reserved when erpt_pointer_valid = 1
3079  * Access: RW
3080  */
3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3082 
3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3084                                                     unsigned long *erp_vector,
3085                                                     unsigned long size)
3086 {
3087         unsigned long bit;
3088 
3089         for_each_set_bit(bit, erp_vector, size)
3090                 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3091 }
3092 
3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3094                                          bool ctcam_le, bool erpt_pointer_valid,
3095                                          u8 erpt_bank_pointer, u8 erpt_pointer,
3096                                          u8 master_rp_id)
3097 {
3098         MLXSW_REG_ZERO(pererp, payload);
3099         mlxsw_reg_pererp_region_id_set(payload, region_id);
3100         mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3101         mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3102         mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3103         mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3104         mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3105 }
3106 
3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register
3108  * ----------------------------------------------------------------
3109  * This register configures the Bloom filter entries.
3110  */
3111 #define MLXSW_REG_PEABFE_ID 0x3022
3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10
3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3116                               MLXSW_REG_PEABFE_BF_REC_LEN * \
3117                               MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3118 
3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3120 
3121 /* reg_peabfe_size
3122  * Number of BF entries to be updated.
3123  * Range 1..256
3124  * Access: Op
3125  */
3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3127 
3128 /* reg_peabfe_bf_entry_state
3129  * Bloom filter state
3130  * 0 - Clear
3131  * 1 - Set
3132  * Access: RW
3133  */
3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3135                      MLXSW_REG_PEABFE_BASE_LEN, 31, 1,
3136                      MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3137 
3138 /* reg_peabfe_bf_entry_bank
3139  * Bloom filter bank ID
3140  * Range 0..cap_max_erp_table_banks-1
3141  * Access: Index
3142  */
3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3144                      MLXSW_REG_PEABFE_BASE_LEN, 24, 4,
3145                      MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3146 
3147 /* reg_peabfe_bf_entry_index
3148  * Bloom filter entry index
3149  * Range 0..2^cap_max_bf_log-1
3150  * Access: Index
3151  */
3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3153                      MLXSW_REG_PEABFE_BASE_LEN, 0, 24,
3154                      MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3155 
3156 static inline void mlxsw_reg_peabfe_pack(char *payload)
3157 {
3158         MLXSW_REG_ZERO(peabfe, payload);
3159 }
3160 
3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3162                                              u8 state, u8 bank, u32 bf_index)
3163 {
3164         u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3165 
3166         if (rec_index >= num_rec)
3167                 mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3168         mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3169         mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3170         mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3171 }
3172 
3173 /* IEDR - Infrastructure Entry Delete Register
3174  * ----------------------------------------------------
3175  * This register is used for deleting entries from the entry tables.
3176  * It is legitimate to attempt to delete a nonexisting entry (the device will
3177  * respond as a good flow).
3178  */
3179 #define MLXSW_REG_IEDR_ID 0x3804
3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN +   \
3184                             MLXSW_REG_IEDR_REC_LEN *    \
3185                             MLXSW_REG_IEDR_REC_MAX_COUNT)
3186 
3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3188 
3189 /* reg_iedr_num_rec
3190  * Number of records.
3191  * Access: OP
3192  */
3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3194 
3195 /* reg_iedr_rec_type
3196  * Resource type.
3197  * Access: OP
3198  */
3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3200                      MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3201 
3202 /* reg_iedr_rec_size
3203  * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
3204  * Access: OP
3205  */
3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11,
3207                      MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3208 
3209 /* reg_iedr_rec_index_start
3210  * Resource index start.
3211  * Access: OP
3212  */
3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3214                      MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3215 
3216 static inline void mlxsw_reg_iedr_pack(char *payload)
3217 {
3218         MLXSW_REG_ZERO(iedr, payload);
3219 }
3220 
3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3222                                            u8 rec_type, u16 rec_size,
3223                                            u32 rec_index_start)
3224 {
3225         u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3226 
3227         if (rec_index >= num_rec)
3228                 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3229         mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3230         mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3231         mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3232 }
3233 
3234 /* QPTS - QoS Priority Trust State Register
3235  * ----------------------------------------
3236  * This register controls the port policy to calculate the switch priority and
3237  * packet color based on incoming packet fields.
3238  */
3239 #define MLXSW_REG_QPTS_ID 0x4002
3240 #define MLXSW_REG_QPTS_LEN 0x8
3241 
3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3243 
3244 /* reg_qpts_local_port
3245  * Local port number.
3246  * Access: Index
3247  *
3248  * Note: CPU port is supported.
3249  */
3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8);
3251 
3252 enum mlxsw_reg_qpts_trust_state {
3253         MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3254         MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3255 };
3256 
3257 /* reg_qpts_trust_state
3258  * Trust state for a given port.
3259  * Access: RW
3260  */
3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3262 
3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3264                                        enum mlxsw_reg_qpts_trust_state ts)
3265 {
3266         MLXSW_REG_ZERO(qpts, payload);
3267 
3268         mlxsw_reg_qpts_local_port_set(payload, local_port);
3269         mlxsw_reg_qpts_trust_state_set(payload, ts);
3270 }
3271 
3272 /* QPCR - QoS Policer Configuration Register
3273  * -----------------------------------------
3274  * The QPCR register is used to create policers - that limit
3275  * the rate of bytes or packets via some trap group.
3276  */
3277 #define MLXSW_REG_QPCR_ID 0x4004
3278 #define MLXSW_REG_QPCR_LEN 0x28
3279 
3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3281 
3282 enum mlxsw_reg_qpcr_g {
3283         MLXSW_REG_QPCR_G_GLOBAL = 2,
3284         MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3285 };
3286 
3287 /* reg_qpcr_g
3288  * The policer type.
3289  * Access: Index
3290  */
3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3292 
3293 /* reg_qpcr_pid
3294  * Policer ID.
3295  * Access: Index
3296  */
3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3298 
3299 /* reg_qpcr_color_aware
3300  * Is the policer aware of colors.
3301  * Must be 0 (unaware) for cpu port.
3302  * Access: RW for unbounded policer. RO for bounded policer.
3303  */
3304 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3305 
3306 /* reg_qpcr_bytes
3307  * Is policer limit is for bytes per sec or packets per sec.
3308  * 0 - packets
3309  * 1 - bytes
3310  * Access: RW for unbounded policer. RO for bounded policer.
3311  */
3312 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3313 
3314 enum mlxsw_reg_qpcr_ir_units {
3315         MLXSW_REG_QPCR_IR_UNITS_M,
3316         MLXSW_REG_QPCR_IR_UNITS_K,
3317 };
3318 
3319 /* reg_qpcr_ir_units
3320  * Policer's units for cir and eir fields (for bytes limits only)
3321  * 1 - 10^3
3322  * 0 - 10^6
3323  * Access: OP
3324  */
3325 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3326 
3327 enum mlxsw_reg_qpcr_rate_type {
3328         MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3329         MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3330 };
3331 
3332 /* reg_qpcr_rate_type
3333  * Policer can have one limit (single rate) or 2 limits with specific operation
3334  * for packets that exceed the lower rate but not the upper one.
3335  * (For cpu port must be single rate)
3336  * Access: RW for unbounded policer. RO for bounded policer.
3337  */
3338 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3339 
3340 /* reg_qpc_cbs
3341  * Policer's committed burst size.
3342  * The policer is working with time slices of 50 nano sec. By default every
3343  * slice is granted the proportionate share of the committed rate. If we want to
3344  * allow a slice to exceed that share (while still keeping the rate per sec) we
3345  * can allow burst. The burst size is between the default proportionate share
3346  * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3347  * committed rate will result in exceeding the rate). The burst size must be a
3348  * log of 2 and will be determined by 2^cbs.
3349  * Access: RW
3350  */
3351 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3352 
3353 /* reg_qpcr_cir
3354  * Policer's committed rate.
3355  * The rate used for sungle rate, the lower rate for double rate.
3356  * For bytes limits, the rate will be this value * the unit from ir_units.
3357  * (Resolution error is up to 1%).
3358  * Access: RW
3359  */
3360 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3361 
3362 /* reg_qpcr_eir
3363  * Policer's exceed rate.
3364  * The higher rate for double rate, reserved for single rate.
3365  * Lower rate for double rate policer.
3366  * For bytes limits, the rate will be this value * the unit from ir_units.
3367  * (Resolution error is up to 1%).
3368  * Access: RW
3369  */
3370 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3371 
3372 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3373 
3374 /* reg_qpcr_exceed_action.
3375  * What to do with packets between the 2 limits for double rate.
3376  * Access: RW for unbounded policer. RO for bounded policer.
3377  */
3378 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3379 
3380 enum mlxsw_reg_qpcr_action {
3381         /* Discard */
3382         MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3383         /* Forward and set color to red.
3384          * If the packet is intended to cpu port, it will be dropped.
3385          */
3386         MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3387 };
3388 
3389 /* reg_qpcr_violate_action
3390  * What to do with packets that cross the cir limit (for single rate) or the eir
3391  * limit (for double rate).
3392  * Access: RW for unbounded policer. RO for bounded policer.
3393  */
3394 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3395 
3396 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3397                                        enum mlxsw_reg_qpcr_ir_units ir_units,
3398                                        bool bytes, u32 cir, u16 cbs)
3399 {
3400         MLXSW_REG_ZERO(qpcr, payload);
3401         mlxsw_reg_qpcr_pid_set(payload, pid);
3402         mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3403         mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3404         mlxsw_reg_qpcr_violate_action_set(payload,
3405                                           MLXSW_REG_QPCR_ACTION_DISCARD);
3406         mlxsw_reg_qpcr_cir_set(payload, cir);
3407         mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3408         mlxsw_reg_qpcr_bytes_set(payload, bytes);
3409         mlxsw_reg_qpcr_cbs_set(payload, cbs);
3410 }
3411 
3412 /* QTCT - QoS Switch Traffic Class Table
3413  * -------------------------------------
3414  * Configures the mapping between the packet switch priority and the
3415  * traffic class on the transmit port.
3416  */
3417 #define MLXSW_REG_QTCT_ID 0x400A
3418 #define MLXSW_REG_QTCT_LEN 0x08
3419 
3420 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3421 
3422 /* reg_qtct_local_port
3423  * Local port number.
3424  * Access: Index
3425  *
3426  * Note: CPU port is not supported.
3427  */
3428 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
3429 
3430 /* reg_qtct_sub_port
3431  * Virtual port within the physical port.
3432  * Should be set to 0 when virtual ports are not enabled on the port.
3433  * Access: Index
3434  */
3435 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3436 
3437 /* reg_qtct_switch_prio
3438  * Switch priority.
3439  * Access: Index
3440  */
3441 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3442 
3443 /* reg_qtct_tclass
3444  * Traffic class.
3445  * Default values:
3446  * switch_prio 0 : tclass 1
3447  * switch_prio 1 : tclass 0
3448  * switch_prio i : tclass i, for i > 1
3449  * Access: RW
3450  */
3451 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3452 
3453 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3454                                        u8 switch_prio, u8 tclass)
3455 {
3456         MLXSW_REG_ZERO(qtct, payload);
3457         mlxsw_reg_qtct_local_port_set(payload, local_port);
3458         mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3459         mlxsw_reg_qtct_tclass_set(payload, tclass);
3460 }
3461 
3462 /* QEEC - QoS ETS Element Configuration Register
3463  * ---------------------------------------------
3464  * Configures the ETS elements.
3465  */
3466 #define MLXSW_REG_QEEC_ID 0x400D
3467 #define MLXSW_REG_QEEC_LEN 0x20
3468 
3469 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3470 
3471 /* reg_qeec_local_port
3472  * Local port number.
3473  * Access: Index
3474  *
3475  * Note: CPU port is supported.
3476  */
3477 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3478 
3479 enum mlxsw_reg_qeec_hr {
3480         MLXSW_REG_QEEC_HIERARCY_PORT,
3481         MLXSW_REG_QEEC_HIERARCY_GROUP,
3482         MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3483         MLXSW_REG_QEEC_HIERARCY_TC,
3484 };
3485 
3486 /* reg_qeec_element_hierarchy
3487  * 0 - Port
3488  * 1 - Group
3489  * 2 - Subgroup
3490  * 3 - Traffic Class
3491  * Access: Index
3492  */
3493 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3494 
3495 /* reg_qeec_element_index
3496  * The index of the element in the hierarchy.
3497  * Access: Index
3498  */
3499 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3500 
3501 /* reg_qeec_next_element_index
3502  * The index of the next (lower) element in the hierarchy.
3503  * Access: RW
3504  *
3505  * Note: Reserved for element_hierarchy 0.
3506  */
3507 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3508 
3509 /* reg_qeec_mise
3510  * Min shaper configuration enable. Enables configuration of the min
3511  * shaper on this ETS element
3512  * 0 - Disable
3513  * 1 - Enable
3514  * Access: RW
3515  */
3516 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3517 
3518 /* reg_qeec_ptps
3519  * PTP shaper
3520  * 0: regular shaper mode
3521  * 1: PTP oriented shaper
3522  * Allowed only for hierarchy 0
3523  * Not supported for CPU port
3524  * Note that ptps mode may affect the shaper rates of all hierarchies
3525  * Supported only on Spectrum-1
3526  * Access: RW
3527  */
3528 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
3529 
3530 enum {
3531         MLXSW_REG_QEEC_BYTES_MODE,
3532         MLXSW_REG_QEEC_PACKETS_MODE,
3533 };
3534 
3535 /* reg_qeec_pb
3536  * Packets or bytes mode.
3537  * 0 - Bytes mode
3538  * 1 - Packets mode
3539  * Access: RW
3540  *
3541  * Note: Used for max shaper configuration. For Spectrum, packets mode
3542  * is supported only for traffic classes of CPU port.
3543  */
3544 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3545 
3546 /* The smallest permitted min shaper rate. */
3547 #define MLXSW_REG_QEEC_MIS_MIN  200000          /* Kbps */
3548 
3549 /* reg_qeec_min_shaper_rate
3550  * Min shaper information rate.
3551  * For CPU port, can only be configured for port hierarchy.
3552  * When in bytes mode, value is specified in units of 1000bps.
3553  * Access: RW
3554  */
3555 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3556 
3557 /* reg_qeec_mase
3558  * Max shaper configuration enable. Enables configuration of the max
3559  * shaper on this ETS element.
3560  * 0 - Disable
3561  * 1 - Enable
3562  * Access: RW
3563  */
3564 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3565 
3566 /* A large max rate will disable the max shaper. */
3567 #define MLXSW_REG_QEEC_MAS_DIS  200000000       /* Kbps */
3568 
3569 /* reg_qeec_max_shaper_rate
3570  * Max shaper information rate.
3571  * For CPU port, can only be configured for port hierarchy.
3572  * When in bytes mode, value is specified in units of 1000bps.
3573  * Access: RW
3574  */
3575 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
3576 
3577 /* reg_qeec_de
3578  * DWRR configuration enable. Enables configuration of the dwrr and
3579  * dwrr_weight.
3580  * 0 - Disable
3581  * 1 - Enable
3582  * Access: RW
3583  */
3584 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3585 
3586 /* reg_qeec_dwrr
3587  * Transmission selection algorithm to use on the link going down from
3588  * the ETS element.
3589  * 0 - Strict priority
3590  * 1 - DWRR
3591  * Access: RW
3592  */
3593 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3594 
3595 /* reg_qeec_dwrr_weight
3596  * DWRR weight on the link going down from the ETS element. The
3597  * percentage of bandwidth guaranteed to an ETS element within
3598  * its hierarchy. The sum of all weights across all ETS elements
3599  * within one hierarchy should be equal to 100. Reserved when
3600  * transmission selection algorithm is strict priority.
3601  * Access: RW
3602  */
3603 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3604 
3605 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3606                                        enum mlxsw_reg_qeec_hr hr, u8 index,
3607                                        u8 next_index)
3608 {
3609         MLXSW_REG_ZERO(qeec, payload);
3610         mlxsw_reg_qeec_local_port_set(payload, local_port);
3611         mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3612         mlxsw_reg_qeec_element_index_set(payload, index);
3613         mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3614 }
3615 
3616 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port,
3617                                             bool ptps)
3618 {
3619         MLXSW_REG_ZERO(qeec, payload);
3620         mlxsw_reg_qeec_local_port_set(payload, local_port);
3621         mlxsw_reg_qeec_element_hierarchy_set(payload,
3622                                              MLXSW_REG_QEEC_HIERARCY_PORT);
3623         mlxsw_reg_qeec_ptps_set(payload, ptps);
3624 }
3625 
3626 /* QRWE - QoS ReWrite Enable
3627  * -------------------------
3628  * This register configures the rewrite enable per receive port.
3629  */
3630 #define MLXSW_REG_QRWE_ID 0x400F
3631 #define MLXSW_REG_QRWE_LEN 0x08
3632 
3633 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3634 
3635 /* reg_qrwe_local_port
3636  * Local port number.
3637  * Access: Index
3638  *
3639  * Note: CPU port is supported. No support for router port.
3640  */
3641 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8);
3642 
3643 /* reg_qrwe_dscp
3644  * Whether to enable DSCP rewrite (default is 0, don't rewrite).
3645  * Access: RW
3646  */
3647 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3648 
3649 /* reg_qrwe_pcp
3650  * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
3651  * Access: RW
3652  */
3653 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3654 
3655 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3656                                        bool rewrite_pcp, bool rewrite_dscp)
3657 {
3658         MLXSW_REG_ZERO(qrwe, payload);
3659         mlxsw_reg_qrwe_local_port_set(payload, local_port);
3660         mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3661         mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3662 }
3663 
3664 /* QPDSM - QoS Priority to DSCP Mapping
3665  * ------------------------------------
3666  * QoS Priority to DSCP Mapping Register
3667  */
3668 #define MLXSW_REG_QPDSM_ID 0x4011
3669 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
3670 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
3671 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3672 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN +                 \
3673                              MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN *       \
3674                              MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3675 
3676 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3677 
3678 /* reg_qpdsm_local_port
3679  * Local Port. Supported for data packets from CPU port.
3680  * Access: Index
3681  */
3682 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8);
3683 
3684 /* reg_qpdsm_prio_entry_color0_e
3685  * Enable update of the entry for color 0 and a given port.
3686  * Access: WO
3687  */
3688 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
3689                      MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
3690                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3691 
3692 /* reg_qpdsm_prio_entry_color0_dscp
3693  * DSCP field in the outer label of the packet for color 0 and a given port.
3694  * Reserved when e=0.
3695  * Access: RW
3696  */
3697 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
3698                      MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
3699                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3700 
3701 /* reg_qpdsm_prio_entry_color1_e
3702  * Enable update of the entry for color 1 and a given port.
3703  * Access: WO
3704  */
3705 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
3706                      MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
3707                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3708 
3709 /* reg_qpdsm_prio_entry_color1_dscp
3710  * DSCP field in the outer label of the packet for color 1 and a given port.
3711  * Reserved when e=0.
3712  * Access: RW
3713  */
3714 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
3715                      MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
3716                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3717 
3718 /* reg_qpdsm_prio_entry_color2_e
3719  * Enable update of the entry for color 2 and a given port.
3720  * Access: WO
3721  */
3722 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
3723                      MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
3724                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3725 
3726 /* reg_qpdsm_prio_entry_color2_dscp
3727  * DSCP field in the outer label of the packet for color 2 and a given port.
3728  * Reserved when e=0.
3729  * Access: RW
3730  */
3731 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
3732                      MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
3733                      MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3734 
3735 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
3736 {
3737         MLXSW_REG_ZERO(qpdsm, payload);
3738         mlxsw_reg_qpdsm_local_port_set(payload, local_port);
3739 }
3740 
3741 static inline void
3742 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
3743 {
3744         mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
3745         mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
3746         mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
3747         mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
3748         mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
3749         mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
3750 }
3751 
3752 /* QPDPM - QoS Port DSCP to Priority Mapping Register
3753  * --------------------------------------------------
3754  * This register controls the mapping from DSCP field to
3755  * Switch Priority for IP packets.
3756  */
3757 #define MLXSW_REG_QPDPM_ID 0x4013
3758 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
3759 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
3760 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
3761 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN +                 \
3762                              MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN *       \
3763                              MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
3764 
3765 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
3766 
3767 /* reg_qpdpm_local_port
3768  * Local Port. Supported for data packets from CPU port.
3769  * Access: Index
3770  */
3771 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8);
3772 
3773 /* reg_qpdpm_dscp_e
3774  * Enable update of the specific entry. When cleared, the switch_prio and color
3775  * fields are ignored and the previous switch_prio and color values are
3776  * preserved.
3777  * Access: WO
3778  */
3779 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
3780                      MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3781 
3782 /* reg_qpdpm_dscp_prio
3783  * The new Switch Priority value for the relevant DSCP value.
3784  * Access: RW
3785  */
3786 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
3787                      MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
3788                      MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3789 
3790 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
3791 {
3792         MLXSW_REG_ZERO(qpdpm, payload);
3793         mlxsw_reg_qpdpm_local_port_set(payload, local_port);
3794 }
3795 
3796 static inline void
3797 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
3798 {
3799         mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
3800         mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
3801 }
3802 
3803 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
3804  * ------------------------------------------------------------------
3805  * This register configures if the Switch Priority to Traffic Class mapping is
3806  * based on Multicast packet indication. If so, then multicast packets will get
3807  * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
3808  * QTCT.
3809  * By default, Switch Priority to Traffic Class mapping is not based on
3810  * Multicast packet indication.
3811  */
3812 #define MLXSW_REG_QTCTM_ID 0x401A
3813 #define MLXSW_REG_QTCTM_LEN 0x08
3814 
3815 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
3816 
3817 /* reg_qtctm_local_port
3818  * Local port number.
3819  * No support for CPU port.
3820  * Access: Index
3821  */
3822 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8);
3823 
3824 /* reg_qtctm_mc
3825  * Multicast Mode
3826  * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
3827  * indication (default is 0, not based on Multicast packet indication).
3828  */
3829 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
3830 
3831 static inline void
3832 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
3833 {
3834         MLXSW_REG_ZERO(qtctm, payload);
3835         mlxsw_reg_qtctm_local_port_set(payload, local_port);
3836         mlxsw_reg_qtctm_mc_set(payload, mc);
3837 }
3838 
3839 /* QPSC - QoS PTP Shaper Configuration Register
3840  * --------------------------------------------
3841  * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1.
3842  * Supported only on Spectrum-1.
3843  */
3844 #define MLXSW_REG_QPSC_ID 0x401B
3845 #define MLXSW_REG_QPSC_LEN 0x28
3846 
3847 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);
3848 
3849 enum mlxsw_reg_qpsc_port_speed {
3850         MLXSW_REG_QPSC_PORT_SPEED_100M,
3851         MLXSW_REG_QPSC_PORT_SPEED_1G,
3852         MLXSW_REG_QPSC_PORT_SPEED_10G,
3853         MLXSW_REG_QPSC_PORT_SPEED_25G,
3854 };
3855 
3856 /* reg_qpsc_port_speed
3857  * Port speed.
3858  * Access: Index
3859  */
3860 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
3861 
3862 /* reg_qpsc_shaper_time_exp
3863  * The base-time-interval for updating the shapers tokens (for all hierarchies).
3864  * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
3865  * shaper_rate = 64bit * shaper_inc / shaper_update_rate
3866  * Access: RW
3867  */
3868 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
3869 
3870 /* reg_qpsc_shaper_time_mantissa
3871  * The base-time-interval for updating the shapers tokens (for all hierarchies).
3872  * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
3873  * shaper_rate = 64bit * shaper_inc / shaper_update_rate
3874  * Access: RW
3875  */
3876 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
3877 
3878 /* reg_qpsc_shaper_inc
3879  * Number of tokens added to shaper on each update.
3880  * Units of 8B.
3881  * Access: RW
3882  */
3883 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
3884 
3885 /* reg_qpsc_shaper_bs
3886  * Max shaper Burst size.
3887  * Burst size is 2 ^ max_shaper_bs * 512 [bits]
3888  * Range is: 5..25 (from 2KB..2GB)
3889  * Access: RW
3890  */
3891 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
3892 
3893 /* reg_qpsc_ptsc_we
3894  * Write enable to port_to_shaper_credits.
3895  * Access: WO
3896  */
3897 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
3898 
3899 /* reg_qpsc_port_to_shaper_credits
3900  * For split ports: range 1..57
3901  * For non-split ports: range 1..112
3902  * Written only when ptsc_we is set.
3903  * Access: RW
3904  */
3905 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
3906 
3907 /* reg_qpsc_ing_timestamp_inc
3908  * Ingress timestamp increment.
3909  * 2's complement.
3910  * The timestamp of MTPPTR at ingress will be incremented by this value. Global
3911  * value for all ports.
3912  * Same units as used by MTPPTR.
3913  * Access: RW
3914  */
3915 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
3916 
3917 /* reg_qpsc_egr_timestamp_inc
3918  * Egress timestamp increment.
3919  * 2's complement.
3920  * The timestamp of MTPPTR at egress will be incremented by this value. Global
3921  * value for all ports.
3922  * Same units as used by MTPPTR.
3923  * Access: RW
3924  */
3925 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
3926 
3927 static inline void
3928 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,
3929                     u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,
3930                     u8 shaper_bs, u8 port_to_shaper_credits,
3931                     int ing_timestamp_inc, int egr_timestamp_inc)
3932 {
3933         MLXSW_REG_ZERO(qpsc, payload);
3934         mlxsw_reg_qpsc_port_speed_set(payload, port_speed);
3935         mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp);
3936         mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa);
3937         mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc);
3938         mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs);
3939         mlxsw_reg_qpsc_ptsc_we_set(payload, true);
3940         mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits);
3941         mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc);
3942         mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc);
3943 }
3944 
3945 /* PMLP - Ports Module to Local Port Register
3946  * ------------------------------------------
3947  * Configures the assignment of modules to local ports.
3948  */
3949 #define MLXSW_REG_PMLP_ID 0x5002
3950 #define MLXSW_REG_PMLP_LEN 0x40
3951 
3952 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
3953 
3954 /* reg_pmlp_rxtx
3955  * 0 - Tx value is used for both Tx and Rx.
3956  * 1 - Rx value is taken from a separte field.
3957  * Access: RW
3958  */
3959 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
3960 
3961 /* reg_pmlp_local_port
3962  * Local port number.
3963  * Access: Index
3964  */
3965 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
3966 
3967 /* reg_pmlp_width
3968  * 0 - Unmap local port.
3969  * 1 - Lane 0 is used.
3970  * 2 - Lanes 0 and 1 are used.
3971  * 4 - Lanes 0, 1, 2 and 3 are used.
3972  * Access: RW
3973  */
3974 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
3975 
3976 /* reg_pmlp_module
3977  * Module number.
3978  * Access: RW
3979  */
3980 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
3981 
3982 /* reg_pmlp_tx_lane
3983  * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
3984  * Access: RW
3985  */
3986 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
3987 
3988 /* reg_pmlp_rx_lane
3989  * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
3990  * equal to Tx lane.
3991  * Access: RW
3992  */
3993 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
3994 
3995 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
3996 {
3997         MLXSW_REG_ZERO(pmlp, payload);
3998         mlxsw_reg_pmlp_local_port_set(payload, local_port);
3999 }
4000 
4001 /* PMTU - Port MTU Register
4002  * ------------------------
4003  * Configures and reports the port MTU.
4004  */
4005 #define MLXSW_REG_PMTU_ID 0x5003
4006 #define MLXSW_REG_PMTU_LEN 0x10
4007 
4008 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
4009 
4010 /* reg_pmtu_local_port
4011  * Local port number.
4012  * Access: Index
4013  */
4014 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
4015 
4016 /* reg_pmtu_max_mtu
4017  * Maximum MTU.
4018  * When port type (e.g. Ethernet) is configured, the relevant MTU is
4019  * reported, otherwise the minimum between the max_mtu of the different
4020  * types is reported.
4021  * Access: RO
4022  */
4023 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
4024 
4025 /* reg_pmtu_admin_mtu
4026  * MTU value to set port to. Must be smaller or equal to max_mtu.
4027  * Note: If port type is Infiniband, then port must be disabled, when its
4028  * MTU is set.
4029  * Access: RW
4030  */
4031 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
4032 
4033 /* reg_pmtu_oper_mtu
4034  * The actual MTU configured on the port. Packets exceeding this size
4035  * will be dropped.
4036  * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
4037  * oper_mtu might be smaller than admin_mtu.
4038  * Access: RO
4039  */
4040 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4041 
4042 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
4043                                        u16 new_mtu)
4044 {
4045         MLXSW_REG_ZERO(pmtu, payload);
4046         mlxsw_reg_pmtu_local_port_set(payload, local_port);
4047         mlxsw_reg_pmtu_max_mtu_set(payload, 0);
4048         mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
4049         mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
4050 }
4051 
4052 /* PTYS - Port Type and Speed Register
4053  * -----------------------------------
4054  * Configures and reports the port speed type.
4055  *
4056  * Note: When set while the link is up, the changes will not take effect
4057  * until the port transitions from down to up state.
4058  */
4059 #define MLXSW_REG_PTYS_ID 0x5004
4060 #define MLXSW_REG_PTYS_LEN 0x40
4061 
4062 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
4063 
4064 /* an_disable_admin
4065  * Auto negotiation disable administrative configuration
4066  * 0 - Device doesn't support AN disable.
4067  * 1 - Device supports AN disable.
4068  * Access: RW
4069  */
4070 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
4071 
4072 /* reg_ptys_local_port
4073  * Local port number.
4074  * Access: Index
4075  */
4076 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
4077 
4078 #define MLXSW_REG_PTYS_PROTO_MASK_IB    BIT(0)
4079 #define MLXSW_REG_PTYS_PROTO_MASK_ETH   BIT(2)
4080 
4081 /* reg_ptys_proto_mask
4082  * Protocol mask. Indicates which protocol is used.
4083  * 0 - Infiniband.
4084  * 1 - Fibre Channel.
4085  * 2 - Ethernet.
4086  * Access: Index
4087  */
4088 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
4089 
4090 enum {
4091         MLXSW_REG_PTYS_AN_STATUS_NA,
4092         MLXSW_REG_PTYS_AN_STATUS_OK,
4093         MLXSW_REG_PTYS_AN_STATUS_FAIL,
4094 };
4095 
4096 /* reg_ptys_an_status
4097  * Autonegotiation status.
4098  * Access: RO
4099  */
4100 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
4101 
4102 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M                         BIT(0)
4103 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII                   BIT(1)
4104 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII                 BIT(2)
4105 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R                           BIT(3)
4106 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G                     BIT(4)
4107 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G                BIT(5)
4108 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR             BIT(6)
4109 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2    BIT(7)
4110 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR      BIT(8)
4111 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4            BIT(9)
4112 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2         BIT(10)
4113 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4         BIT(12)
4114 
4115 /* reg_ptys_ext_eth_proto_cap
4116  * Extended Ethernet port supported speeds and protocols.
4117  * Access: RO
4118  */
4119 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4120 
4121 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII                  BIT(0)
4122 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX            BIT(1)
4123 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4            BIT(2)
4124 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4            BIT(3)
4125 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR             BIT(4)
4126 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2            BIT(5)
4127 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4            BIT(6)
4128 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4            BIT(7)
4129 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR             BIT(12)
4130 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR             BIT(13)
4131 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR          BIT(14)
4132 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4            BIT(15)
4133 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4        BIT(16)
4134 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2            BIT(18)
4135 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4            BIT(19)
4136 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4           BIT(20)
4137 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4           BIT(21)
4138 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4           BIT(22)
4139 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4       BIT(23)
4140 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX             BIT(24)
4141 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T              BIT(25)
4142 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T              BIT(26)
4143 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR             BIT(27)
4144 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR             BIT(28)
4145 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR             BIT(29)
4146 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2            BIT(30)
4147 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2            BIT(31)
4148 
4149 /* reg_ptys_eth_proto_cap
4150  * Ethernet port supported speeds and protocols.
4151  * Access: RO
4152  */
4153 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4154 
4155 /* reg_ptys_ib_link_width_cap
4156  * IB port supported widths.
4157  * Access: RO
4158  */
4159 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
4160 
4161 #define MLXSW_REG_PTYS_IB_SPEED_SDR     BIT(0)
4162 #define MLXSW_REG_PTYS_IB_SPEED_DDR     BIT(1)
4163 #define MLXSW_REG_PTYS_IB_SPEED_QDR     BIT(2)
4164 #define MLXSW_REG_PTYS_IB_SPEED_FDR10   BIT(3)
4165 #define MLXSW_REG_PTYS_IB_SPEED_FDR     BIT(4)
4166 #define MLXSW_REG_PTYS_IB_SPEED_EDR     BIT(5)
4167 
4168 /* reg_ptys_ib_proto_cap
4169  * IB port supported speeds and protocols.
4170  * Access: RO
4171  */
4172 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
4173 
4174 /* reg_ptys_ext_eth_proto_admin
4175  * Extended speed and protocol to set port to.
4176  * Access: RW
4177  */
4178 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4179 
4180 /* reg_ptys_eth_proto_admin
4181  * Speed and protocol to set port to.
4182  * Access: RW
4183  */
4184 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4185 
4186 /* reg_ptys_ib_link_width_admin
4187  * IB width to set port to.
4188  * Access: RW
4189  */
4190 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
4191 
4192 /* reg_ptys_ib_proto_admin
4193  * IB speeds and protocols to set port to.
4194  * Access: RW
4195  */
4196 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
4197 
4198 /* reg_ptys_ext_eth_proto_oper
4199  * The extended current speed and protocol configured for the port.
4200  * Access: RO
4201  */
4202 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4203 
4204 /* reg_ptys_eth_proto_oper
4205  * The current speed and protocol configured for the port.
4206  * Access: RO
4207  */
4208 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4209 
4210 /* reg_ptys_ib_link_width_oper
4211  * The current IB width to set port to.
4212  * Access: RO
4213  */
4214 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
4215 
4216 /* reg_ptys_ib_proto_oper
4217  * The current IB speed and protocol.
4218  * Access: RO
4219  */
4220 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
4221 
4222 enum mlxsw_reg_ptys_connector_type {
4223         MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4224         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4225         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4226         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4227         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4228         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4229         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4230         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4231         MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4232 };
4233 
4234 /* reg_ptys_connector_type
4235  * Connector type indication.
4236  * Access: RO
4237  */
4238 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4239 
4240 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
4241                                            u32 proto_admin, bool autoneg)
4242 {
4243         MLXSW_REG_ZERO(ptys, payload);
4244         mlxsw_reg_ptys_local_port_set(payload, local_port);
4245         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4246         mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4247         mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4248 }
4249 
4250 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port,
4251                                                u32 proto_admin, bool autoneg)
4252 {
4253         MLXSW_REG_ZERO(ptys, payload);
4254         mlxsw_reg_ptys_local_port_set(payload, local_port);
4255         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4256         mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4257         mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4258 }
4259 
4260 static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4261                                              u32 *p_eth_proto_cap,
4262                                              u32 *p_eth_proto_admin,
4263                                              u32 *p_eth_proto_oper)
4264 {
4265         if (p_eth_proto_cap)
4266                 *p_eth_proto_cap =
4267                         mlxsw_reg_ptys_eth_proto_cap_get(payload);
4268         if (p_eth_proto_admin)
4269                 *p_eth_proto_admin =
4270                         mlxsw_reg_ptys_eth_proto_admin_get(payload);
4271         if (p_eth_proto_oper)
4272                 *p_eth_proto_oper =
4273                         mlxsw_reg_ptys_eth_proto_oper_get(payload);
4274 }
4275 
4276 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4277                                                  u32 *p_eth_proto_cap,
4278                                                  u32 *p_eth_proto_admin,
4279                                                  u32 *p_eth_proto_oper)
4280 {
4281         if (p_eth_proto_cap)
4282                 *p_eth_proto_cap =
4283                         mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4284         if (p_eth_proto_admin)
4285                 *p_eth_proto_admin =
4286                         mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4287         if (p_eth_proto_oper)
4288                 *p_eth_proto_oper =
4289                         mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4290 }
4291 
4292 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
4293                                           u16 proto_admin, u16 link_width)
4294 {
4295         MLXSW_REG_ZERO(ptys, payload);
4296         mlxsw_reg_ptys_local_port_set(payload, local_port);
4297         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4298         mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4299         mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4300 }
4301 
4302 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
4303                                             u16 *p_ib_link_width_cap,
4304                                             u16 *p_ib_proto_oper,
4305                                             u16 *p_ib_link_width_oper)
4306 {
4307         if (p_ib_proto_cap)
4308                 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
4309         if (p_ib_link_width_cap)
4310                 *p_ib_link_width_cap =
4311                         mlxsw_reg_ptys_ib_link_width_cap_get(payload);
4312         if (p_ib_proto_oper)
4313                 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
4314         if (p_ib_link_width_oper)
4315                 *p_ib_link_width_oper =
4316                         mlxsw_reg_ptys_ib_link_width_oper_get(payload);
4317 }
4318 
4319 /* PPAD - Port Physical Address Register
4320  * -------------------------------------
4321  * The PPAD register configures the per port physical MAC address.
4322  */
4323 #define MLXSW_REG_PPAD_ID 0x5005
4324 #define MLXSW_REG_PPAD_LEN 0x10
4325 
4326 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4327 
4328 /* reg_ppad_single_base_mac
4329  * 0: base_mac, local port should be 0 and mac[7:0] is
4330  * reserved. HW will set incremental
4331  * 1: single_mac - mac of the local_port
4332  * Access: RW
4333  */
4334 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4335 
4336 /* reg_ppad_local_port
4337  * port number, if single_base_mac = 0 then local_port is reserved
4338  * Access: RW
4339  */
4340 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
4341 
4342 /* reg_ppad_mac
4343  * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
4344  * If single_base_mac = 1 - the per port MAC address
4345  * Access: RW
4346  */
4347 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4348 
4349 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4350                                        u8 local_port)
4351 {
4352         MLXSW_REG_ZERO(ppad, payload);
4353         mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4354         mlxsw_reg_ppad_local_port_set(payload, local_port);
4355 }
4356 
4357 /* PAOS - Ports Administrative and Operational Status Register
4358  * -----------------------------------------------------------
4359  * Configures and retrieves per port administrative and operational status.
4360  */
4361 #define MLXSW_REG_PAOS_ID 0x5006
4362 #define MLXSW_REG_PAOS_LEN 0x10
4363 
4364 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4365 
4366 /* reg_paos_swid
4367  * Switch partition ID with which to associate the port.
4368  * Note: while external ports uses unique local port numbers (and thus swid is
4369  * redundant), router ports use the same local port number where swid is the
4370  * only indication for the relevant port.
4371  * Access: Index
4372  */
4373 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4374 
4375 /* reg_paos_local_port
4376  * Local port number.
4377  * Access: Index
4378  */
4379 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
4380 
4381 /* reg_paos_admin_status
4382  * Port administrative state (the desired state of the port):
4383  * 1 - Up.
4384  * 2 - Down.
4385  * 3 - Up once. This means that in case of link failure, the port won't go
4386  *     into polling mode, but will wait to be re-enabled by software.
4387  * 4 - Disabled by system. Can only be set by hardware.
4388  * Access: RW
4389  */
4390 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4391 
4392 /* reg_paos_oper_status
4393  * Port operational state (the current state):
4394  * 1 - Up.
4395  * 2 - Down.
4396  * 3 - Down by port failure. This means that the device will not let the
4397  *     port up again until explicitly specified by software.
4398  * Access: RO
4399  */
4400 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4401 
4402 /* reg_paos_ase
4403  * Admin state update enabled.
4404  * Access: WO
4405  */
4406 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4407 
4408 /* reg_paos_ee
4409  * Event update enable. If this bit is set, event generation will be
4410  * updated based on the e field.
4411  * Access: WO
4412  */
4413 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4414 
4415 /* reg_paos_e
4416  * Event generation on operational state change:
4417  * 0 - Do not generate event.
4418  * 1 - Generate Event.
4419  * 2 - Generate Single Event.
4420  * Access: RW
4421  */
4422 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4423 
4424 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
4425                                        enum mlxsw_port_admin_status status)
4426 {
4427         MLXSW_REG_ZERO(paos, payload);
4428         mlxsw_reg_paos_swid_set(payload, 0);
4429         mlxsw_reg_paos_local_port_set(payload, local_port);
4430         mlxsw_reg_paos_admin_status_set(payload, status);
4431         mlxsw_reg_paos_oper_status_set(payload, 0);
4432         mlxsw_reg_paos_ase_set(payload, 1);
4433         mlxsw_reg_paos_ee_set(payload, 1);
4434         mlxsw_reg_paos_e_set(payload, 1);
4435 }
4436 
4437 /* PFCC - Ports Flow Control Configuration Register
4438  * ------------------------------------------------
4439  * Configures and retrieves the per port flow control configuration.
4440  */
4441 #define MLXSW_REG_PFCC_ID 0x5007
4442 #define MLXSW_REG_PFCC_LEN 0x20
4443 
4444 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4445 
4446 /* reg_pfcc_local_port
4447  * Local port number.
4448  * Access: Index
4449  */
4450 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
4451 
4452 /* reg_pfcc_pnat
4453  * Port number access type. Determines the way local_port is interpreted:
4454  * 0 - Local port number.
4455  * 1 - IB / label port number.
4456  * Access: Index
4457  */
4458 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4459 
4460 /* reg_pfcc_shl_cap
4461  * Send to higher layers capabilities:
4462  * 0 - No capability of sending Pause and PFC frames to higher layers.
4463  * 1 - Device has capability of sending Pause and PFC frames to higher
4464  *     layers.
4465  * Access: RO
4466  */
4467 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4468 
4469 /* reg_pfcc_shl_opr
4470  * Send to higher layers operation:
4471  * 0 - Pause and PFC frames are handled by the port (default).
4472  * 1 - Pause and PFC frames are handled by the port and also sent to
4473  *     higher layers. Only valid if shl_cap = 1.
4474  * Access: RW
4475  */
4476 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4477 
4478 /* reg_pfcc_ppan
4479  * Pause policy auto negotiation.
4480  * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
4481  * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
4482  *     based on the auto-negotiation resolution.
4483  * Access: RW
4484  *
4485  * Note: The auto-negotiation advertisement is set according to pptx and
4486  * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
4487  */
4488 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4489 
4490 /* reg_pfcc_prio_mask_tx
4491  * Bit per priority indicating if Tx flow control policy should be
4492  * updated based on bit pfctx.
4493  * Access: WO
4494  */
4495 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4496 
4497 /* reg_pfcc_prio_mask_rx
4498  * Bit per priority indicating if Rx flow control policy should be
4499  * updated based on bit pfcrx.
4500  * Access: WO
4501  */
4502 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4503 
4504 /* reg_pfcc_pptx
4505  * Admin Pause policy on Tx.
4506  * 0 - Never generate Pause frames (default).
4507  * 1 - Generate Pause frames according to Rx buffer threshold.
4508  * Access: RW
4509  */
4510 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4511 
4512 /* reg_pfcc_aptx
4513  * Active (operational) Pause policy on Tx.
4514  * 0 - Never generate Pause frames.
4515  * 1 - Generate Pause frames according to Rx buffer threshold.
4516  * Access: RO
4517  */
4518 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4519 
4520 /* reg_pfcc_pfctx
4521  * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
4522  * 0 - Never generate priority Pause frames on the specified priority
4523  *     (default).
4524  * 1 - Generate priority Pause frames according to Rx buffer threshold on
4525  *     the specified priority.
4526  * Access: RW
4527  *
4528  * Note: pfctx and pptx must be mutually exclusive.
4529  */
4530 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4531 
4532 /* reg_pfcc_pprx
4533  * Admin Pause policy on Rx.
4534  * 0 - Ignore received Pause frames (default).
4535  * 1 - Respect received Pause frames.
4536  * Access: RW
4537  */
4538 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4539 
4540 /* reg_pfcc_aprx
4541  * Active (operational) Pause policy on Rx.
4542  * 0 - Ignore received Pause frames.
4543  * 1 - Respect received Pause frames.
4544  * Access: RO
4545  */
4546 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4547 
4548 /* reg_pfcc_pfcrx
4549  * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
4550  * 0 - Ignore incoming priority Pause frames on the specified priority
4551  *     (default).
4552  * 1 - Respect incoming priority Pause frames on the specified priority.
4553  * Access: RW
4554  */
4555 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4556 
4557 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4558 
4559 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4560 {
4561         mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4562         mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4563         mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4564         mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4565 }
4566 
4567 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4568 {
4569         MLXSW_REG_ZERO(pfcc, payload);
4570         mlxsw_reg_pfcc_local_port_set(payload, local_port);
4571 }
4572 
4573 /* PPCNT - Ports Performance Counters Register
4574  * -------------------------------------------
4575  * The PPCNT register retrieves per port performance counters.
4576  */
4577 #define MLXSW_REG_PPCNT_ID 0x5008
4578 #define MLXSW_REG_PPCNT_LEN 0x100
4579 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4580 
4581 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4582 
4583 /* reg_ppcnt_swid
4584  * For HCA: must be always 0.
4585  * Switch partition ID to associate port with.
4586  * Switch partitions are numbered from 0 to 7 inclusively.
4587  * Switch partition 254 indicates stacking ports.
4588  * Switch partition 255 indicates all switch partitions.
4589  * Only valid on Set() operation with local_port=255.
4590  * Access: Index
4591  */
4592 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4593 
4594 /* reg_ppcnt_local_port
4595  * Local port number.
4596  * 255 indicates all ports on the device, and is only allowed
4597  * for Set() operation.
4598  * Access: Index
4599  */
4600 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
4601 
4602 /* reg_ppcnt_pnat
4603  * Port number access type:
4604  * 0 - Local port number
4605  * 1 - IB port number
4606  * Access: Index
4607  */
4608 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4609 
4610 enum mlxsw_reg_ppcnt_grp {
4611         MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4612         MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
4613         MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4614         MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
4615         MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4616         MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
4617         MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4618         MLXSW_REG_PPCNT_TC_CNT = 0x11,
4619         MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
4620 };
4621 
4622 /* reg_ppcnt_grp
4623  * Performance counter group.
4624  * Group 63 indicates all groups. Only valid on Set() operation with
4625  * clr bit set.
4626  * 0x0: IEEE 802.3 Counters
4627  * 0x1: RFC 2863 Counters
4628  * 0x2: RFC 2819 Counters
4629  * 0x3: RFC 3635 Counters
4630  * 0x5: Ethernet Extended Counters
4631  * 0x6: Ethernet Discard Counters
4632  * 0x8: Link Level Retransmission Counters
4633  * 0x10: Per Priority Counters
4634  * 0x11: Per Traffic Class Counters
4635  * 0x12: Physical Layer Counters
4636  * 0x13: Per Traffic Class Congestion Counters
4637  * Access: Index
4638  */
4639 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4640 
4641 /* reg_ppcnt_clr
4642  * Clear counters. Setting the clr bit will reset the counter value
4643  * for all counters in the counter group. This bit can be set
4644  * for both Set() and Get() operation.
4645  * Access: OP
4646  */
4647 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4648 
4649 /* reg_ppcnt_prio_tc
4650  * Priority for counter set that support per priority, valid values: 0-7.
4651  * Traffic class for counter set that support per traffic class,
4652  * valid values: 0- cap_max_tclass-1 .
4653  * For HCA: cap_max_tclass is always 8.
4654  * Otherwise must be 0.
4655  * Access: Index
4656  */
4657 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
4658 
4659 /* Ethernet IEEE 802.3 Counter Group */
4660 
4661 /* reg_ppcnt_a_frames_transmitted_ok
4662  * Access: RO
4663  */
4664 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
4665              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4666 
4667 /* reg_ppcnt_a_frames_received_ok
4668  * Access: RO
4669  */
4670 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
4671              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4672 
4673 /* reg_ppcnt_a_frame_check_sequence_errors
4674  * Access: RO
4675  */
4676 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
4677              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4678 
4679 /* reg_ppcnt_a_alignment_errors
4680  * Access: RO
4681  */
4682 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
4683              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4684 
4685 /* reg_ppcnt_a_octets_transmitted_ok
4686  * Access: RO
4687  */
4688 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
4689              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4690 
4691 /* reg_ppcnt_a_octets_received_ok
4692  * Access: RO
4693  */
4694 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
4695              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4696 
4697 /* reg_ppcnt_a_multicast_frames_xmitted_ok
4698  * Access: RO
4699  */
4700 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
4701              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4702 
4703 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
4704  * Access: RO
4705  */
4706 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
4707              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4708 
4709 /* reg_ppcnt_a_multicast_frames_received_ok
4710  * Access: RO
4711  */
4712 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
4713              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4714 
4715 /* reg_ppcnt_a_broadcast_frames_received_ok
4716  * Access: RO
4717  */
4718 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
4719              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4720 
4721 /* reg_ppcnt_a_in_range_length_errors
4722  * Access: RO
4723  */
4724 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
4725              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4726 
4727 /* reg_ppcnt_a_out_of_range_length_field
4728  * Access: RO
4729  */
4730 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
4731              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4732 
4733 /* reg_ppcnt_a_frame_too_long_errors
4734  * Access: RO
4735  */
4736 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
4737              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4738 
4739 /* reg_ppcnt_a_symbol_error_during_carrier
4740  * Access: RO
4741  */
4742 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
4743              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4744 
4745 /* reg_ppcnt_a_mac_control_frames_transmitted
4746  * Access: RO
4747  */
4748 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
4749              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4750 
4751 /* reg_ppcnt_a_mac_control_frames_received
4752  * Access: RO
4753  */
4754 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
4755              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4756 
4757 /* reg_ppcnt_a_unsupported_opcodes_received
4758  * Access: RO
4759  */
4760 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
4761              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4762 
4763 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
4764  * Access: RO
4765  */
4766 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
4767              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4768 
4769 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
4770  * Access: RO
4771  */
4772 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
4773              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4774 
4775 /* Ethernet RFC 2863 Counter Group */
4776 
4777 /* reg_ppcnt_if_in_discards
4778  * Access: RO
4779  */
4780 MLXSW_ITEM64(reg, ppcnt, if_in_discards,
4781              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4782 
4783 /* reg_ppcnt_if_out_discards
4784  * Access: RO
4785  */
4786 MLXSW_ITEM64(reg, ppcnt, if_out_discards,
4787              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4788 
4789 /* reg_ppcnt_if_out_errors
4790  * Access: RO
4791  */
4792 MLXSW_ITEM64(reg, ppcnt, if_out_errors,
4793              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4794 
4795 /* Ethernet RFC 2819 Counter Group */
4796 
4797 /* reg_ppcnt_ether_stats_undersize_pkts
4798  * Access: RO
4799  */
4800 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
4801              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4802 
4803 /* reg_ppcnt_ether_stats_oversize_pkts
4804  * Access: RO
4805  */
4806 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
4807              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4808 
4809 /* reg_ppcnt_ether_stats_fragments
4810  * Access: RO
4811  */
4812 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
4813              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4814 
4815 /* reg_ppcnt_ether_stats_pkts64octets
4816  * Access: RO
4817  */
4818 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
4819              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4820 
4821 /* reg_ppcnt_ether_stats_pkts65to127octets
4822  * Access: RO
4823  */
4824 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
4825              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4826 
4827 /* reg_ppcnt_ether_stats_pkts128to255octets
4828  * Access: RO
4829  */
4830 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
4831              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4832 
4833 /* reg_ppcnt_ether_stats_pkts256to511octets
4834  * Access: RO
4835  */
4836 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
4837              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4838 
4839 /* reg_ppcnt_ether_stats_pkts512to1023octets
4840  * Access: RO
4841  */
4842 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
4843              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4844 
4845 /* reg_ppcnt_ether_stats_pkts1024to1518octets
4846  * Access: RO
4847  */
4848 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
4849              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4850 
4851 /* reg_ppcnt_ether_stats_pkts1519to2047octets
4852  * Access: RO
4853  */
4854 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
4855              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4856 
4857 /* reg_ppcnt_ether_stats_pkts2048to4095octets
4858  * Access: RO
4859  */
4860 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
4861              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4862 
4863 /* reg_ppcnt_ether_stats_pkts4096to8191octets
4864  * Access: RO
4865  */
4866 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
4867              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
4868 
4869 /* reg_ppcnt_ether_stats_pkts8192to10239octets
4870  * Access: RO
4871  */
4872 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
4873              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
4874 
4875 /* Ethernet RFC 3635 Counter Group */
4876 
4877 /* reg_ppcnt_dot3stats_fcs_errors
4878  * Access: RO
4879  */
4880 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
4881              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4882 
4883 /* reg_ppcnt_dot3stats_symbol_errors
4884  * Access: RO
4885  */
4886 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
4887              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4888 
4889 /* reg_ppcnt_dot3control_in_unknown_opcodes
4890  * Access: RO
4891  */
4892 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
4893              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4894 
4895 /* reg_ppcnt_dot3in_pause_frames
4896  * Access: RO
4897  */
4898 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
4899              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4900 
4901 /* Ethernet Extended Counter Group Counters */
4902 
4903 /* reg_ppcnt_ecn_marked
4904  * Access: RO
4905  */
4906 MLXSW_ITEM64(reg, ppcnt, ecn_marked,
4907              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4908 
4909 /* Ethernet Discard Counter Group Counters */
4910 
4911 /* reg_ppcnt_ingress_general
4912  * Access: RO
4913  */
4914 MLXSW_ITEM64(reg, ppcnt, ingress_general,
4915              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4916 
4917 /* reg_ppcnt_ingress_policy_engine
4918  * Access: RO
4919  */
4920 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
4921              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4922 
4923 /* reg_ppcnt_ingress_vlan_membership
4924  * Access: RO
4925  */
4926 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
4927              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4928 
4929 /* reg_ppcnt_ingress_tag_frame_type
4930  * Access: RO
4931  */
4932 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
4933              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4934 
4935 /* reg_ppcnt_egress_vlan_membership
4936  * Access: RO
4937  */
4938 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
4939              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4940 
4941 /* reg_ppcnt_loopback_filter
4942  * Access: RO
4943  */
4944 MLXSW_ITEM64(reg, ppcnt, loopback_filter,
4945              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4946 
4947 /* reg_ppcnt_egress_general
4948  * Access: RO
4949  */
4950 MLXSW_ITEM64(reg, ppcnt, egress_general,
4951              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4952 
4953 /* reg_ppcnt_egress_hoq
4954  * Access: RO
4955  */
4956 MLXSW_ITEM64(reg, ppcnt, egress_hoq,
4957              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4958 
4959 /* reg_ppcnt_egress_policy_engine
4960  * Access: RO
4961  */
4962 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
4963              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4964 
4965 /* reg_ppcnt_ingress_tx_link_down
4966  * Access: RO
4967  */
4968 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
4969              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4970 
4971 /* reg_ppcnt_egress_stp_filter
4972  * Access: RO
4973  */
4974 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
4975              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4976 
4977 /* reg_ppcnt_egress_sll
4978  * Access: RO
4979  */
4980 MLXSW_ITEM64(reg, ppcnt, egress_sll,
4981              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4982 
4983 /* Ethernet Per Priority Group Counters */
4984 
4985 /* reg_ppcnt_rx_octets
4986  * Access: RO
4987  */
4988 MLXSW_ITEM64(reg, ppcnt, rx_octets,
4989              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4990 
4991 /* reg_ppcnt_rx_frames
4992  * Access: RO
4993  */
4994 MLXSW_ITEM64(reg, ppcnt, rx_frames,
4995              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4996 
4997 /* reg_ppcnt_tx_octets
4998  * Access: RO
4999  */
5000 MLXSW_ITEM64(reg, ppcnt, tx_octets,
5001              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5002 
5003 /* reg_ppcnt_tx_frames
5004  * Access: RO
5005  */
5006 MLXSW_ITEM64(reg, ppcnt, tx_frames,
5007              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5008 
5009 /* reg_ppcnt_rx_pause
5010  * Access: RO
5011  */
5012 MLXSW_ITEM64(reg, ppcnt, rx_pause,
5013              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5014 
5015 /* reg_ppcnt_rx_pause_duration
5016  * Access: RO
5017  */
5018 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
5019              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5020 
5021 /* reg_ppcnt_tx_pause
5022  * Access: RO
5023  */
5024 MLXSW_ITEM64(reg, ppcnt, tx_pause,
5025              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5026 
5027 /* reg_ppcnt_tx_pause_duration
5028  * Access: RO
5029  */
5030 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
5031              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5032 
5033 /* reg_ppcnt_rx_pause_transition
5034  * Access: RO
5035  */
5036 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
5037              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5038 
5039 /* Ethernet Per Traffic Group Counters */
5040 
5041 /* reg_ppcnt_tc_transmit_queue
5042  * Contains the transmit queue depth in cells of traffic class
5043  * selected by prio_tc and the port selected by local_port.
5044  * The field cannot be cleared.
5045  * Access: RO
5046  */
5047 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
5048              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5049 
5050 /* reg_ppcnt_tc_no_buffer_discard_uc
5051  * The number of unicast packets dropped due to lack of shared
5052  * buffer resources.
5053  * Access: RO
5054  */
5055 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
5056              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5057 
5058 /* Ethernet Per Traffic Class Congestion Group Counters */
5059 
5060 /* reg_ppcnt_wred_discard
5061  * Access: RO
5062  */
5063 MLXSW_ITEM64(reg, ppcnt, wred_discard,
5064              MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5065 
5066 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
5067                                         enum mlxsw_reg_ppcnt_grp grp,
5068                                         u8 prio_tc)
5069 {
5070         MLXSW_REG_ZERO(ppcnt, payload);
5071         mlxsw_reg_ppcnt_swid_set(payload, 0);
5072         mlxsw_reg_ppcnt_local_port_set(payload, local_port);
5073         mlxsw_reg_ppcnt_pnat_set(payload, 0);
5074         mlxsw_reg_ppcnt_grp_set(payload, grp);
5075         mlxsw_reg_ppcnt_clr_set(payload, 0);
5076         mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
5077 }
5078 
5079 /* PLIB - Port Local to InfiniBand Port
5080  * ------------------------------------
5081  * The PLIB register performs mapping from Local Port into InfiniBand Port.
5082  */
5083 #define MLXSW_REG_PLIB_ID 0x500A
5084 #define MLXSW_REG_PLIB_LEN 0x10
5085 
5086 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
5087 
5088 /* reg_plib_local_port
5089  * Local port number.
5090  * Access: Index
5091  */
5092 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8);
5093 
5094 /* reg_plib_ib_port
5095  * InfiniBand port remapping for local_port.
5096  * Access: RW
5097  */
5098 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
5099 
5100 /* PPTB - Port Prio To Buffer Register
5101  * -----------------------------------
5102  * Configures the switch priority to buffer table.
5103  */
5104 #define MLXSW_REG_PPTB_ID 0x500B
5105 #define MLXSW_REG_PPTB_LEN 0x10
5106 
5107 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
5108 
5109 enum {
5110         MLXSW_REG_PPTB_MM_UM,
5111         MLXSW_REG_PPTB_MM_UNICAST,
5112         MLXSW_REG_PPTB_MM_MULTICAST,
5113 };
5114 
5115 /* reg_pptb_mm
5116  * Mapping mode.
5117  * 0 - Map both unicast and multicast packets to the same buffer.
5118  * 1 - Map only unicast packets.
5119  * 2 - Map only multicast packets.
5120  * Access: Index
5121  *
5122  * Note: SwitchX-2 only supports the first option.
5123  */
5124 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
5125 
5126 /* reg_pptb_local_port
5127  * Local port number.
5128  * Access: Index
5129  */
5130 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
5131 
5132 /* reg_pptb_um
5133  * Enables the update of the untagged_buf field.
5134  * Access: RW
5135  */
5136 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5137 
5138 /* reg_pptb_pm
5139  * Enables the update of the prio_to_buff field.
5140  * Bit <i> is a flag for updating the mapping for switch priority <i>.
5141  * Access: RW
5142  */
5143 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5144 
5145 /* reg_pptb_prio_to_buff
5146  * Mapping of switch priority <i> to one of the allocated receive port
5147  * buffers.
5148  * Access: RW
5149  */
5150 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5151 
5152 /* reg_pptb_pm_msb
5153  * Enables the update of the prio_to_buff field.
5154  * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
5155  * Access: RW
5156  */
5157 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5158 
5159 /* reg_pptb_untagged_buff
5160  * Mapping of untagged frames to one of the allocated receive port buffers.
5161  * Access: RW
5162  *
5163  * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
5164  * Spectrum, as it maps untagged packets based on the default switch priority.
5165  */
5166 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5167 
5168 /* reg_pptb_prio_to_buff_msb
5169  * Mapping of switch priority <i+8> to one of the allocated receive port
5170  * buffers.
5171  * Access: RW
5172  */
5173 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5174 
5175 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5176 
5177 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
5178 {
5179         MLXSW_REG_ZERO(pptb, payload);
5180         mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5181         mlxsw_reg_pptb_local_port_set(payload, local_port);
5182         mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5183         mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5184 }
5185 
5186 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
5187                                                     u8 buff)
5188 {
5189         mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
5190         mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
5191 }
5192 
5193 /* PBMC - Port Buffer Management Control Register
5194  * ----------------------------------------------
5195  * The PBMC register configures and retrieves the port packet buffer
5196  * allocation for different Prios, and the Pause threshold management.
5197  */
5198 #define MLXSW_REG_PBMC_ID 0x500C
5199 #define MLXSW_REG_PBMC_LEN 0x6C
5200 
5201 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
5202 
5203 /* reg_pbmc_local_port
5204  * Local port number.
5205  * Access: Index
5206  */
5207 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
5208 
5209 /* reg_pbmc_xoff_timer_value
5210  * When device generates a pause frame, it uses this value as the pause
5211  * timer (time for the peer port to pause in quota-512 bit time).
5212  * Access: RW
5213  */
5214 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5215 
5216 /* reg_pbmc_xoff_refresh
5217  * The time before a new pause frame should be sent to refresh the pause RW
5218  * state. Using the same units as xoff_timer_value above (in quota-512 bit
5219  * time).
5220  * Access: RW
5221  */
5222 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5223 
5224 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
5225 
5226 /* reg_pbmc_buf_lossy
5227  * The field indicates if the buffer is lossy.
5228  * 0 - Lossless
5229  * 1 - Lossy
5230  * Access: RW
5231  */
5232 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5233 
5234 /* reg_pbmc_buf_epsb
5235  * Eligible for Port Shared buffer.
5236  * If epsb is set, packets assigned to buffer are allowed to insert the port
5237  * shared buffer.
5238  * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
5239  * Access: RW
5240  */
5241 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5242 
5243 /* reg_pbmc_buf_size
5244  * The part of the packet buffer array is allocated for the specific buffer.
5245  * Units are represented in cells.
5246  * Access: RW
5247  */
5248 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5249 
5250 /* reg_pbmc_buf_xoff_threshold
5251  * Once the amount of data in the buffer goes above this value, device
5252  * starts sending PFC frames for all priorities associated with the
5253  * buffer. Units are represented in cells. Reserved in case of lossy
5254  * buffer.
5255  * Access: RW
5256  *
5257  * Note: In Spectrum, reserved for buffer[9].
5258  */
5259 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5260                      0x08, 0x04, false);
5261 
5262 /* reg_pbmc_buf_xon_threshold
5263  * When the amount of data in the buffer goes below this value, device
5264  * stops sending PFC frames for the priorities associated with the
5265  * buffer. Units are represented in cells. Reserved in case of lossy
5266  * buffer.
5267  * Access: RW
5268  *
5269  * Note: In Spectrum, reserved for buffer[9].
5270  */
5271 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5272                      0x08, 0x04, false);
5273 
5274 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
5275                                        u16 xoff_timer_value, u16 xoff_refresh)
5276 {
5277         MLXSW_REG_ZERO(pbmc, payload);
5278         mlxsw_reg_pbmc_local_port_set(payload, local_port);
5279         mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5280         mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5281 }
5282 
5283 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
5284                                                     int buf_index,
5285                                                     u16 size)
5286 {
5287         mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
5288         mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5289         mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5290 }
5291 
5292 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
5293                                                        int buf_index, u16 size,
5294                                                        u16 threshold)
5295 {
5296         mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
5297         mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5298         mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5299         mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
5300         mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
5301 }
5302 
5303 /* PSPA - Port Switch Partition Allocation
5304  * ---------------------------------------
5305  * Controls the association of a port with a switch partition and enables
5306  * configuring ports as stacking ports.
5307  */
5308 #define MLXSW_REG_PSPA_ID 0x500D
5309 #define MLXSW_REG_PSPA_LEN 0x8
5310 
5311 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
5312 
5313 /* reg_pspa_swid
5314  * Switch partition ID.
5315  * Access: RW
5316  */
5317 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5318 
5319 /* reg_pspa_local_port
5320  * Local port number.
5321  * Access: Index
5322  */
5323 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
5324 
5325 /* reg_pspa_sub_port
5326  * Virtual port within the local port. Set to 0 when virtual ports are
5327  * disabled on the local port.
5328  * Access: Index
5329  */
5330 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5331 
5332 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
5333 {
5334         MLXSW_REG_ZERO(pspa, payload);
5335         mlxsw_reg_pspa_swid_set(payload, swid);
5336         mlxsw_reg_pspa_local_port_set(payload, local_port);
5337         mlxsw_reg_pspa_sub_port_set(payload, 0);
5338 }
5339 
5340 /* PPLR - Port Physical Loopback Register
5341  * --------------------------------------
5342  * This register allows configuration of the port's loopback mode.
5343  */
5344 #define MLXSW_REG_PPLR_ID 0x5018
5345 #define MLXSW_REG_PPLR_LEN 0x8
5346 
5347 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
5348 
5349 /* reg_pplr_local_port
5350  * Local port number.
5351  * Access: Index
5352  */
5353 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8);
5354 
5355 /* Phy local loopback. When set the port's egress traffic is looped back
5356  * to the receiver and the port transmitter is disabled.
5357  */
5358 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5359 
5360 /* reg_pplr_lb_en
5361  * Loopback enable.
5362  * Access: RW
5363  */
5364 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5365 
5366 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port,
5367                                        bool phy_local)
5368 {
5369         MLXSW_REG_ZERO(pplr, payload);
5370         mlxsw_reg_pplr_local_port_set(payload, local_port);
5371         mlxsw_reg_pplr_lb_en_set(payload,
5372                                  phy_local ?
5373                                  MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5374 }
5375 
5376 /* HTGT - Host Trap Group Table
5377  * ----------------------------
5378  * Configures the properties for forwarding to CPU.
5379  */
5380 #define MLXSW_REG_HTGT_ID 0x7002
5381 #define MLXSW_REG_HTGT_LEN 0x20
5382 
5383 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
5384 
5385 /* reg_htgt_swid
5386  * Switch partition ID.
5387  * Access: Index
5388  */
5389 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
5390 
5391 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0      /* For locally attached CPU */
5392 
5393 /* reg_htgt_type
5394  * CPU path type.
5395  * Access: RW
5396  */
5397 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
5398 
5399 enum mlxsw_reg_htgt_trap_group {
5400         MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
5401         MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
5402         MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
5403         MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
5404         MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
5405         MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
5406         MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
5407         MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
5408         MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
5409         MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
5410         MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
5411         MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
5412         MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS,
5413         MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
5414         MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
5415         MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
5416         MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
5417         MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF,
5418         MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
5419         MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
5420         MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
5421         MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
5422         MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
5423         MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
5424         MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP,
5425 
5426         __MLXSW_REG_HTGT_TRAP_GROUP_MAX,
5427         MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1
5428 };
5429 
5430 enum mlxsw_reg_htgt_discard_trap_group {
5431         MLXSW_REG_HTGT_DISCARD_TRAP_GROUP_BASE = MLXSW_REG_HTGT_TRAP_GROUP_MAX,
5432         MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS,
5433 };
5434 
5435 /* reg_htgt_trap_group
5436  * Trap group number. User defined number specifying which trap groups
5437  * should be forwarded to the CPU. The mapping between trap IDs and trap
5438  * groups is configured using HPKT register.
5439  * Access: Index
5440  */
5441 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
5442 
5443 enum {
5444         MLXSW_REG_HTGT_POLICER_DISABLE,
5445         MLXSW_REG_HTGT_POLICER_ENABLE,
5446 };
5447 
5448 /* reg_htgt_pide
5449  * Enable policer ID specified using 'pid' field.
5450  * Access: RW
5451  */
5452 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
5453 
5454 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff
5455 
5456 /* reg_htgt_pid
5457  * Policer ID for the trap group.
5458  * Access: RW
5459  */
5460 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
5461 
5462 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
5463 
5464 /* reg_htgt_mirror_action
5465  * Mirror action to use.
5466  * 0 - Trap to CPU.
5467  * 1 - Trap to CPU and mirror to a mirroring agent.
5468  * 2 - Mirror to a mirroring agent and do not trap to CPU.
5469  * Access: RW
5470  *
5471  * Note: Mirroring to a mirroring agent is only supported in Spectrum.
5472  */
5473 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
5474 
5475 /* reg_htgt_mirroring_agent
5476  * Mirroring agent.
5477  * Access: RW
5478  */
5479 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
5480 
5481 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
5482 
5483 /* reg_htgt_priority
5484  * Trap group priority.
5485  * In case a packet matches multiple classification rules, the packet will
5486  * only be trapped once, based on the trap ID associated with the group (via
5487  * register HPKT) with the highest priority.
5488  * Supported values are 0-7, with 7 represnting the highest priority.
5489  * Access: RW
5490  *
5491  * Note: In SwitchX-2 this field is ignored and the priority value is replaced
5492  * by the 'trap_group' field.
5493  */
5494 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
5495 
5496 #define MLXSW_REG_HTGT_DEFAULT_TC 7
5497 
5498 /* reg_htgt_local_path_cpu_tclass
5499  * CPU ingress traffic class for the trap group.
5500  * Access: RW
5501  */
5502 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
5503 
5504 enum mlxsw_reg_htgt_local_path_rdq {
5505         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
5506         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
5507         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
5508         MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
5509 };
5510 /* reg_htgt_local_path_rdq
5511  * Receive descriptor queue (RDQ) to use for the trap group.
5512  * Access: RW
5513  */
5514 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
5515 
5516 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
5517                                        u8 priority, u8 tc)
5518 {
5519         MLXSW_REG_ZERO(htgt, payload);
5520 
5521         if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
5522                 mlxsw_reg_htgt_pide_set(payload,
5523                                         MLXSW_REG_HTGT_POLICER_DISABLE);
5524         } else {
5525                 mlxsw_reg_htgt_pide_set(payload,
5526                                         MLXSW_REG_HTGT_POLICER_ENABLE);
5527                 mlxsw_reg_htgt_pid_set(payload, policer_id);
5528         }
5529 
5530         mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
5531         mlxsw_reg_htgt_trap_group_set(payload, group);
5532         mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
5533         mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
5534         mlxsw_reg_htgt_priority_set(payload, priority);
5535         mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
5536         mlxsw_reg_htgt_local_path_rdq_set(payload, group);
5537 }
5538 
5539 /* HPKT - Host Packet Trap
5540  * -----------------------
5541  * Configures trap IDs inside trap groups.
5542  */
5543 #define MLXSW_REG_HPKT_ID 0x7003
5544 #define MLXSW_REG_HPKT_LEN 0x10
5545 
5546 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
5547 
5548 enum {
5549         MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
5550         MLXSW_REG_HPKT_ACK_REQUIRED,
5551 };
5552 
5553 /* reg_hpkt_ack
5554  * Require acknowledgements from the host for events.
5555  * If set, then the device will wait for the event it sent to be acknowledged
5556  * by the host. This option is only relevant for event trap IDs.
5557  * Access: RW
5558  *
5559  * Note: Currently not supported by firmware.
5560  */
5561 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
5562 
5563 enum mlxsw_reg_hpkt_action {
5564         MLXSW_REG_HPKT_ACTION_FORWARD,
5565         MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
5566         MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
5567         MLXSW_REG_HPKT_ACTION_DISCARD,
5568         MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
5569         MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
5570         MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU,
5571         MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15,
5572 };
5573 
5574 /* reg_hpkt_action
5575  * Action to perform on packet when trapped.
5576  * 0 - No action. Forward to CPU based on switching rules.
5577  * 1 - Trap to CPU (CPU receives sole copy).
5578  * 2 - Mirror to CPU (CPU receives a replica of the packet).
5579  * 3 - Discard.
5580  * 4 - Soft discard (allow other traps to act on the packet).
5581  * 5 - Trap and soft discard (allow other traps to overwrite this trap).
5582  * 6 - Trap to CPU (CPU receives sole copy) and count it as error.
5583  * 15 - Restore the firmware's default action.
5584  * Access: RW
5585  *
5586  * Note: Must be set to 0 (forward) for event trap IDs, as they are already
5587  * addressed to the CPU.
5588  */
5589 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
5590 
5591 /* reg_hpkt_trap_group
5592  * Trap group to associate the trap with.
5593  * Access: RW
5594  */
5595 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
5596 
5597 /* reg_hpkt_trap_id
5598  * Trap ID.
5599  * Access: Index
5600  *
5601  * Note: A trap ID can only be associated with a single trap group. The device
5602  * will associate the trap ID with the last trap group configured.
5603  */
5604 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
5605 
5606 enum {
5607         MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
5608         MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
5609         MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
5610 };
5611 
5612 /* reg_hpkt_ctrl
5613  * Configure dedicated buffer resources for control packets.
5614  * Ignored by SwitchX-2.
5615  * 0 - Keep factory defaults.
5616  * 1 - Do not use control buffer for this trap ID.
5617  * 2 - Use control buffer for this trap ID.
5618  * Access: RW
5619  */
5620 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
5621 
5622 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
5623                                        enum mlxsw_reg_htgt_trap_group trap_group,
5624                                        bool is_ctrl)
5625 {
5626         MLXSW_REG_ZERO(hpkt, payload);
5627         mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
5628         mlxsw_reg_hpkt_action_set(payload, action);
5629         mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
5630         mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
5631         mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
5632                                 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
5633                                 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
5634 }
5635 
5636 /* RGCR - Router General Configuration Register
5637  * --------------------------------------------
5638  * The register is used for setting up the router configuration.
5639  */
5640 #define MLXSW_REG_RGCR_ID 0x8001
5641 #define MLXSW_REG_RGCR_LEN 0x28
5642 
5643 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
5644 
5645 /* reg_rgcr_ipv4_en
5646  * IPv4 router enable.
5647  * Access: RW
5648  */
5649 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
5650 
5651 /* reg_rgcr_ipv6_en
5652  * IPv6 router enable.
5653  * Access: RW
5654  */
5655 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
5656 
5657 /* reg_rgcr_max_router_interfaces
5658  * Defines the maximum number of active router interfaces for all virtual
5659  * routers.
5660  * Access: RW
5661  */
5662 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
5663 
5664 /* reg_rgcr_usp
5665  * Update switch priority and packet color.
5666  * 0 - Preserve the value of Switch Priority and packet color.
5667  * 1 - Recalculate the value of Switch Priority and packet color.
5668  * Access: RW
5669  *
5670  * Note: Not supported by SwitchX and SwitchX-2.
5671  */
5672 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
5673 
5674 /* reg_rgcr_pcp_rw
5675  * Indicates how to handle the pcp_rewrite_en value:
5676  * 0 - Preserve the value of pcp_rewrite_en.
5677  * 2 - Disable PCP rewrite.
5678  * 3 - Enable PCP rewrite.
5679  * Access: RW
5680  *
5681  * Note: Not supported by SwitchX and SwitchX-2.
5682  */
5683 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
5684 
5685 /* reg_rgcr_activity_dis
5686  * Activity disable:
5687  * 0 - Activity will be set when an entry is hit (default).
5688  * 1 - Activity will not be set when an entry is hit.
5689  *
5690  * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
5691  * (RALUE).
5692  * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
5693  * Entry (RAUHT).
5694  * Bits 2:7 are reserved.
5695  * Access: RW
5696  *
5697  * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
5698  */
5699 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
5700 
5701 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
5702                                        bool ipv6_en)
5703 {
5704         MLXSW_REG_ZERO(rgcr, payload);
5705         mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
5706         mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
5707 }
5708 
5709 /* RITR - Router Interface Table Register
5710  * --------------------------------------
5711  * The register is used to configure the router interface table.
5712  */
5713 #define MLXSW_REG_RITR_ID 0x8002
5714 #define MLXSW_REG_RITR_LEN 0x40
5715 
5716 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
5717 
5718 /* reg_ritr_enable
5719  * Enables routing on the router interface.
5720  * Access: RW
5721  */
5722 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
5723 
5724 /* reg_ritr_ipv4
5725  * IPv4 routing enable. Enables routing of IPv4 traffic on the router
5726  * interface.
5727  * Access: RW
5728  */
5729 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
5730 
5731 /* reg_ritr_ipv6
5732  * IPv6 routing enable. Enables routing of IPv6 traffic on the router
5733  * interface.
5734  * Access: RW
5735  */
5736 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
5737 
5738 /* reg_ritr_ipv4_mc
5739  * IPv4 multicast routing enable.
5740  * Access: RW
5741  */
5742 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
5743 
5744 /* reg_ritr_ipv6_mc
5745  * IPv6 multicast routing enable.
5746  * Access: RW
5747  */
5748 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
5749 
5750 enum mlxsw_reg_ritr_if_type {
5751         /* VLAN interface. */
5752         MLXSW_REG_RITR_VLAN_IF,
5753         /* FID interface. */
5754         MLXSW_REG_RITR_FID_IF,
5755         /* Sub-port interface. */
5756         MLXSW_REG_RITR_SP_IF,
5757         /* Loopback Interface. */
5758         MLXSW_REG_RITR_LOOPBACK_IF,
5759 };
5760 
5761 /* reg_ritr_type
5762  * Router interface type as per enum mlxsw_reg_ritr_if_type.
5763  * Access: RW
5764  */
5765 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
5766 
5767 enum {
5768         MLXSW_REG_RITR_RIF_CREATE,
5769         MLXSW_REG_RITR_RIF_DEL,
5770 };
5771 
5772 /* reg_ritr_op
5773  * Opcode:
5774  * 0 - Create or edit RIF.
5775  * 1 - Delete RIF.
5776  * Reserved for SwitchX-2. For Spectrum, editing of interface properties
5777  * is not supported. An interface must be deleted and re-created in order
5778  * to update properties.
5779  * Access: WO
5780  */
5781 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
5782 
5783 /* reg_ritr_rif
5784  * Router interface index. A pointer to the Router Interface Table.
5785  * Access: Index
5786  */
5787 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
5788 
5789 /* reg_ritr_ipv4_fe
5790  * IPv4 Forwarding Enable.
5791  * Enables routing of IPv4 traffic on the router interface. When disabled,
5792  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5793  * Not supported in SwitchX-2.
5794  * Access: RW
5795  */
5796 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
5797 
5798 /* reg_ritr_ipv6_fe
5799  * IPv6 Forwarding Enable.
5800  * Enables routing of IPv6 traffic on the router interface. When disabled,
5801  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5802  * Not supported in SwitchX-2.
5803  * Access: RW
5804  */
5805 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
5806 
5807 /* reg_ritr_ipv4_mc_fe
5808  * IPv4 Multicast Forwarding Enable.
5809  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5810  * will be enabled.
5811  * Access: RW
5812  */
5813 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
5814 
5815 /* reg_ritr_ipv6_mc_fe
5816  * IPv6 Multicast Forwarding Enable.
5817  * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5818  * will be enabled.
5819  * Access: RW
5820  */
5821 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
5822 
5823 /* reg_ritr_lb_en
5824  * Loop-back filter enable for unicast packets.
5825  * If the flag is set then loop-back filter for unicast packets is
5826  * implemented on the RIF. Multicast packets are always subject to
5827  * loop-back filtering.
5828  * Access: RW
5829  */
5830 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
5831 
5832 /* reg_ritr_virtual_router
5833  * Virtual router ID associated with the router interface.
5834  * Access: RW
5835  */
5836 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
5837 
5838 /* reg_ritr_mtu
5839  * Router interface MTU.
5840  * Access: RW
5841  */
5842 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
5843 
5844 /* reg_ritr_if_swid
5845  * Switch partition ID.
5846  * Access: RW
5847  */
5848 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
5849 
5850 /* reg_ritr_if_mac
5851  * Router interface MAC address.
5852  * In Spectrum, all MAC addresses must have the same 38 MSBits.
5853  * Access: RW
5854  */
5855 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
5856 
5857 /* reg_ritr_if_vrrp_id_ipv6
5858  * VRRP ID for IPv6
5859  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5860  * Access: RW
5861  */
5862 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
5863 
5864 /* reg_ritr_if_vrrp_id_ipv4
5865  * VRRP ID for IPv4
5866  * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5867  * Access: RW
5868  */
5869 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
5870 
5871 /* VLAN Interface */
5872 
5873 /* reg_ritr_vlan_if_vid
5874  * VLAN ID.
5875  * Access: RW
5876  */
5877 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
5878 
5879 /* FID Interface */
5880 
5881 /* reg_ritr_fid_if_fid
5882  * Filtering ID. Used to connect a bridge to the router. Only FIDs from
5883  * the vFID range are supported.
5884  * Access: RW
5885  */
5886 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
5887 
5888 static inline void mlxsw_reg_ritr_fid_set(char *payload,
5889                                           enum mlxsw_reg_ritr_if_type rif_type,
5890                                           u16 fid)
5891 {
5892         if (rif_type == MLXSW_REG_RITR_FID_IF)
5893                 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
5894         else
5895                 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
5896 }
5897 
5898 /* Sub-port Interface */
5899 
5900 /* reg_ritr_sp_if_lag
5901  * LAG indication. When this bit is set the system_port field holds the
5902  * LAG identifier.
5903  * Access: RW
5904  */
5905 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
5906 
5907 /* reg_ritr_sp_system_port
5908  * Port unique indentifier. When lag bit is set, this field holds the
5909  * lag_id in bits 0:9.
5910  * Access: RW
5911  */
5912 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
5913 
5914 /* reg_ritr_sp_if_vid
5915  * VLAN ID.
5916  * Access: RW
5917  */
5918 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
5919 
5920 /* Loopback Interface */
5921 
5922 enum mlxsw_reg_ritr_loopback_protocol {
5923         /* IPinIP IPv4 underlay Unicast */
5924         MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
5925         /* IPinIP IPv6 underlay Unicast */
5926         MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
5927         /* IPinIP generic - used for Spectrum-2 underlay RIF */
5928         MLXSW_REG_RITR_LOOPBACK_GENERIC,
5929 };
5930 
5931 /* reg_ritr_loopback_protocol
5932  * Access: RW
5933  */
5934 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
5935 
5936 enum mlxsw_reg_ritr_loopback_ipip_type {
5937         /* Tunnel is IPinIP. */
5938         MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
5939         /* Tunnel is GRE, no key. */
5940         MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
5941         /* Tunnel is GRE, with a key. */
5942         MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
5943 };
5944 
5945 /* reg_ritr_loopback_ipip_type
5946  * Encapsulation type.
5947  * Access: RW
5948  */
5949 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
5950 
5951 enum mlxsw_reg_ritr_loopback_ipip_options {
5952         /* The key is defined by gre_key. */
5953         MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
5954 };
5955 
5956 /* reg_ritr_loopback_ipip_options
5957  * Access: RW
5958  */
5959 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
5960 
5961 /* reg_ritr_loopback_ipip_uvr
5962  * Underlay Virtual Router ID.
5963  * Range is 0..cap_max_virtual_routers-1.
5964  * Reserved for Spectrum-2.
5965  * Access: RW
5966  */
5967 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
5968 
5969 /* reg_ritr_loopback_ipip_underlay_rif
5970  * Underlay ingress router interface.
5971  * Reserved for Spectrum.
5972  * Access: RW
5973  */
5974 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
5975 
5976 /* reg_ritr_loopback_ipip_usip*
5977  * Encapsulation Underlay source IP.
5978  * Access: RW
5979  */
5980 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
5981 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
5982 
5983 /* reg_ritr_loopback_ipip_gre_key
5984  * GRE Key.
5985  * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.
5986  * Access: RW
5987  */
5988 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
5989 
5990 /* Shared between ingress/egress */
5991 enum mlxsw_reg_ritr_counter_set_type {
5992         /* No Count. */
5993         MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
5994         /* Basic. Used for router interfaces, counting the following:
5995          *      - Error and Discard counters.
5996          *      - Unicast, Multicast and Broadcast counters. Sharing the
5997          *        same set of counters for the different type of traffic
5998          *        (IPv4, IPv6 and mpls).
5999          */
6000         MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
6001 };
6002 
6003 /* reg_ritr_ingress_counter_index
6004  * Counter Index for flow counter.
6005  * Access: RW
6006  */
6007 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
6008 
6009 /* reg_ritr_ingress_counter_set_type
6010  * Igress Counter Set Type for router interface counter.
6011  * Access: RW
6012  */
6013 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
6014 
6015 /* reg_ritr_egress_counter_index
6016  * Counter Index for flow counter.
6017  * Access: RW
6018  */
6019 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
6020 
6021 /* reg_ritr_egress_counter_set_type
6022  * Egress Counter Set Type for router interface counter.
6023  * Access: RW
6024  */
6025 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
6026 
6027 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
6028                                                bool enable, bool egress)
6029 {
6030         enum mlxsw_reg_ritr_counter_set_type set_type;
6031 
6032         if (enable)
6033                 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
6034         else
6035                 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
6036         mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
6037 
6038         if (egress)
6039                 mlxsw_reg_ritr_egress_counter_index_set(payload, index);
6040         else
6041                 mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
6042 }
6043 
6044 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
6045 {
6046         MLXSW_REG_ZERO(ritr, payload);
6047         mlxsw_reg_ritr_rif_set(payload, rif);
6048 }
6049 
6050 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
6051                                              u16 system_port, u16 vid)
6052 {
6053         mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
6054         mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
6055         mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
6056 }
6057 
6058 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
6059                                        enum mlxsw_reg_ritr_if_type type,
6060                                        u16 rif, u16 vr_id, u16 mtu)
6061 {
6062         bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
6063 
6064         MLXSW_REG_ZERO(ritr, payload);
6065         mlxsw_reg_ritr_enable_set(payload, enable);
6066         mlxsw_reg_ritr_ipv4_set(payload, 1);
6067         mlxsw_reg_ritr_ipv6_set(payload, 1);
6068         mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
6069         mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
6070         mlxsw_reg_ritr_type_set(payload, type);
6071         mlxsw_reg_ritr_op_set(payload, op);
6072         mlxsw_reg_ritr_rif_set(payload, rif);
6073         mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
6074         mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
6075         mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
6076         mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
6077         mlxsw_reg_ritr_lb_en_set(payload, 1);
6078         mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
6079         mlxsw_reg_ritr_mtu_set(payload, mtu);
6080 }
6081 
6082 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
6083 {
6084         mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
6085 }
6086 
6087 static inline void
6088 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
6089                             enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6090                             enum mlxsw_reg_ritr_loopback_ipip_options options,
6091                             u16 uvr_id, u16 underlay_rif, u32 gre_key)
6092 {
6093         mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
6094         mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
6095         mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
6096         mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
6097         mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
6098 }
6099 
6100 static inline void
6101 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
6102                             enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6103                             enum mlxsw_reg_ritr_loopback_ipip_options options,
6104                             u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
6105 {
6106         mlxsw_reg_ritr_loopback_protocol_set(payload,
6107                                     MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
6108         mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
6109                                                  uvr_id, underlay_rif, gre_key);
6110         mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
6111 }
6112 
6113 /* RTAR - Router TCAM Allocation Register
6114  * --------------------------------------
6115  * This register is used for allocation of regions in the TCAM table.
6116  */
6117 #define MLXSW_REG_RTAR_ID 0x8004
6118 #define MLXSW_REG_RTAR_LEN 0x20
6119 
6120 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
6121 
6122 enum mlxsw_reg_rtar_op {
6123         MLXSW_REG_RTAR_OP_ALLOCATE,
6124         MLXSW_REG_RTAR_OP_RESIZE,
6125         MLXSW_REG_RTAR_OP_DEALLOCATE,
6126 };
6127 
6128 /* reg_rtar_op
6129  * Access: WO
6130  */
6131 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
6132 
6133 enum mlxsw_reg_rtar_key_type {
6134         MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
6135         MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
6136 };
6137 
6138 /* reg_rtar_key_type
6139  * TCAM key type for the region.
6140  * Access: WO
6141  */
6142 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
6143 
6144 /* reg_rtar_region_size
6145  * TCAM region size. When allocating/resizing this is the requested
6146  * size, the response is the actual size.
6147  * Note: Actual size may be larger than requested.
6148  * Reserved for op = Deallocate
6149  * Access: WO
6150  */
6151 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
6152 
6153 static inline void mlxsw_reg_rtar_pack(char *payload,
6154                                        enum mlxsw_reg_rtar_op op,
6155                                        enum mlxsw_reg_rtar_key_type key_type,
6156                                        u16 region_size)
6157 {
6158         MLXSW_REG_ZERO(rtar, payload);
6159         mlxsw_reg_rtar_op_set(payload, op);
6160         mlxsw_reg_rtar_key_type_set(payload, key_type);
6161         mlxsw_reg_rtar_region_size_set(payload, region_size);
6162 }
6163 
6164 /* RATR - Router Adjacency Table Register
6165  * --------------------------------------
6166  * The RATR register is used to configure the Router Adjacency (next-hop)
6167  * Table.
6168  */
6169 #define MLXSW_REG_RATR_ID 0x8008
6170 #define MLXSW_REG_RATR_LEN 0x2C
6171 
6172 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
6173 
6174 enum mlxsw_reg_ratr_op {
6175         /* Read */
6176         MLXSW_REG_RATR_OP_QUERY_READ = 0,
6177         /* Read and clear activity */
6178         MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
6179         /* Write Adjacency entry */
6180         MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
6181         /* Write Adjacency entry only if the activity is cleared.
6182          * The write may not succeed if the activity is set. There is not
6183          * direct feedback if the write has succeeded or not, however
6184          * the get will reveal the actual entry (SW can compare the get
6185          * response to the set command).
6186          */
6187         MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
6188 };
6189 
6190 /* reg_ratr_op
6191  * Note that Write operation may also be used for updating
6192  * counter_set_type and counter_index. In this case all other
6193  * fields must not be updated.
6194  * Access: OP
6195  */
6196 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
6197 
6198 /* reg_ratr_v
6199  * Valid bit. Indicates if the adjacency entry is valid.
6200  * Note: the device may need some time before reusing an invalidated
6201  * entry. During this time the entry can not be reused. It is
6202  * recommended to use another entry before reusing an invalidated
6203  * entry (e.g. software can put it at the end of the list for
6204  * reusing). Trying to access an invalidated entry not yet cleared
6205  * by the device results with failure indicating "Try Again" status.
6206  * When valid is '0' then egress_router_interface,trap_action,
6207  * adjacency_parameters and counters are reserved
6208  * Access: RW
6209  */
6210 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
6211 
6212 /* reg_ratr_a
6213  * Activity. Set for new entries. Set if a packet lookup has hit on
6214  * the specific entry. To clear the a bit, use "clear activity".
6215  * Access: RO
6216  */
6217 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
6218 
6219 enum mlxsw_reg_ratr_type {
6220         /* Ethernet */
6221         MLXSW_REG_RATR_TYPE_ETHERNET,
6222         /* IPoIB Unicast without GRH.
6223          * Reserved for Spectrum.
6224          */
6225         MLXSW_REG_RATR_TYPE_IPOIB_UC,
6226         /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast
6227          * adjacency).
6228          * Reserved for Spectrum.
6229          */
6230         MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
6231         /* IPoIB Multicast.
6232          * Reserved for Spectrum.
6233          */
6234         MLXSW_REG_RATR_TYPE_IPOIB_MC,
6235         /* MPLS.
6236          * Reserved for SwitchX/-2.
6237          */
6238         MLXSW_REG_RATR_TYPE_MPLS,
6239         /* IPinIP Encap.
6240          * Reserved for SwitchX/-2.
6241          */
6242         MLXSW_REG_RATR_TYPE_IPIP,
6243 };
6244 
6245 /* reg_ratr_type
6246  * Adjacency entry type.
6247  * Access: RW
6248  */
6249 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
6250 
6251 /* reg_ratr_adjacency_index_low
6252  * Bits 15:0 of index into the adjacency table.
6253  * For SwitchX and SwitchX-2, the adjacency table is linear and
6254  * used for adjacency entries only.
6255  * For Spectrum, the index is to the KVD linear.
6256  * Access: Index
6257  */
6258 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
6259 
6260 /* reg_ratr_egress_router_interface
6261  * Range is 0 .. cap_max_router_interfaces - 1
6262  * Access: RW
6263  */
6264 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
6265 
6266 enum mlxsw_reg_ratr_trap_action {
6267         MLXSW_REG_RATR_TRAP_ACTION_NOP,
6268         MLXSW_REG_RATR_TRAP_ACTION_TRAP,
6269         MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
6270         MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
6271         MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
6272 };
6273 
6274 /* reg_ratr_trap_action
6275  * see mlxsw_reg_ratr_trap_action
6276  * Access: RW
6277  */
6278 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
6279 
6280 /* reg_ratr_adjacency_index_high
6281  * Bits 23:16 of the adjacency_index.
6282  * Access: Index
6283  */
6284 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
6285 
6286 enum mlxsw_reg_ratr_trap_id {
6287         MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
6288         MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
6289 };
6290 
6291 /* reg_ratr_trap_id
6292  * Trap ID to be reported to CPU.
6293  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
6294  * For trap_action of NOP, MIRROR and DISCARD_ERROR
6295  * Access: RW
6296  */
6297 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
6298 
6299 /* reg_ratr_eth_destination_mac
6300  * MAC address of the destination next-hop.
6301  * Access: RW
6302  */
6303 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
6304 
6305 enum mlxsw_reg_ratr_ipip_type {
6306         /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
6307         MLXSW_REG_RATR_IPIP_TYPE_IPV4,
6308         /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
6309         MLXSW_REG_RATR_IPIP_TYPE_IPV6,
6310 };
6311 
6312 /* reg_ratr_ipip_type
6313  * Underlay destination ip type.
6314  * Note: the type field must match the protocol of the router interface.
6315  * Access: RW
6316  */
6317 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
6318 
6319 /* reg_ratr_ipip_ipv4_udip
6320  * Underlay ipv4 dip.
6321  * Reserved when ipip_type is IPv6.
6322  * Access: RW
6323  */
6324 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
6325 
6326 /* reg_ratr_ipip_ipv6_ptr
6327  * Pointer to IPv6 underlay destination ip address.
6328  * For Spectrum: Pointer to KVD linear space.
6329  * Access: RW
6330  */
6331 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
6332 
6333 enum mlxsw_reg_flow_counter_set_type {
6334         /* No count */
6335         MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6336         /* Count packets and bytes */
6337         MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
6338         /* Count only packets */
6339         MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
6340 };
6341 
6342 /* reg_ratr_counter_set_type
6343  * Counter set type for flow counters
6344  * Access: RW
6345  */
6346 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
6347 
6348 /* reg_ratr_counter_index
6349  * Counter index for flow counters
6350  * Access: RW
6351  */
6352 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
6353 
6354 static inline void
6355 mlxsw_reg_ratr_pack(char *payload,
6356                     enum mlxsw_reg_ratr_op op, bool valid,
6357                     enum mlxsw_reg_ratr_type type,
6358                     u32 adjacency_index, u16 egress_rif)
6359 {
6360         MLXSW_REG_ZERO(ratr, payload);
6361         mlxsw_reg_ratr_op_set(payload, op);
6362         mlxsw_reg_ratr_v_set(payload, valid);
6363         mlxsw_reg_ratr_type_set(payload, type);
6364         mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
6365         mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
6366         mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
6367 }
6368 
6369 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
6370                                                  const char *dest_mac)
6371 {
6372         mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
6373 }
6374 
6375 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
6376 {
6377         mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
6378         mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
6379 }
6380 
6381 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
6382                                                bool counter_enable)
6383 {
6384         enum mlxsw_reg_flow_counter_set_type set_type;
6385 
6386         if (counter_enable)
6387                 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
6388         else
6389                 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
6390 
6391         mlxsw_reg_ratr_counter_index_set(payload, counter_index);
6392         mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
6393 }
6394 
6395 /* RDPM - Router DSCP to Priority Mapping
6396  * --------------------------------------
6397  * Controls the mapping from DSCP field to switch priority on routed packets
6398  */
6399 #define MLXSW_REG_RDPM_ID 0x8009
6400 #define MLXSW_REG_RDPM_BASE_LEN 0x00
6401 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
6402 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
6403 #define MLXSW_REG_RDPM_LEN 0x40
6404 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
6405                                    MLXSW_REG_RDPM_LEN - \
6406                                    MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
6407 
6408 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
6409 
6410 /* reg_dscp_entry_e
6411  * Enable update of the specific entry
6412  * Access: Index
6413  */
6414 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
6415                     -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6416 
6417 /* reg_dscp_entry_prio
6418  * Switch Priority
6419  * Access: RW
6420  */
6421 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
6422                     -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6423 
6424 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
6425                                        u8 prio)
6426 {
6427         mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
6428         mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
6429 }
6430 
6431 /* RICNT - Router Interface Counter Register
6432  * -----------------------------------------
6433  * The RICNT register retrieves per port performance counters
6434  */
6435 #define MLXSW_REG_RICNT_ID 0x800B
6436 #define MLXSW_REG_RICNT_LEN 0x100
6437 
6438 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
6439 
6440 /* reg_ricnt_counter_index
6441  * Counter index
6442  * Access: RW
6443  */
6444 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
6445 
6446 enum mlxsw_reg_ricnt_counter_set_type {
6447         /* No Count. */
6448         MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6449         /* Basic. Used for router interfaces, counting the following:
6450          *      - Error and Discard counters.
6451          *      - Unicast, Multicast and Broadcast counters. Sharing the
6452          *        same set of counters for the different type of traffic
6453          *        (IPv4, IPv6 and mpls).
6454          */
6455         MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
6456 };
6457 
6458 /* reg_ricnt_counter_set_type
6459  * Counter Set Type for router interface counter
6460  * Access: RW
6461  */
6462 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
6463 
6464 enum mlxsw_reg_ricnt_opcode {
6465         /* Nop. Supported only for read access*/
6466         MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
6467         /* Clear. Setting the clr bit will reset the counter value for
6468          * all counters of the specified Router Interface.
6469          */
6470         MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
6471 };
6472 
6473 /* reg_ricnt_opcode
6474  * Opcode
6475  * Access: RW
6476  */
6477 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
6478 
6479 /* reg_ricnt_good_unicast_packets
6480  * good unicast packets.
6481  * Access: RW
6482  */
6483 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
6484 
6485 /* reg_ricnt_good_multicast_packets
6486  * good multicast packets.
6487  * Access: RW
6488  */
6489 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
6490 
6491 /* reg_ricnt_good_broadcast_packets
6492  * good broadcast packets
6493  * Access: RW
6494  */
6495 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
6496 
6497 /* reg_ricnt_good_unicast_bytes
6498  * A count of L3 data and padding octets not including L2 headers
6499  * for good unicast frames.
6500  * Access: RW
6501  */
6502 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
6503 
6504 /* reg_ricnt_good_multicast_bytes
6505  * A count of L3 data and padding octets not including L2 headers
6506  * for good multicast frames.
6507  * Access: RW
6508  */
6509 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
6510 
6511 /* reg_ritr_good_broadcast_bytes
6512  * A count of L3 data and padding octets not including L2 headers
6513  * for good broadcast frames.
6514  * Access: RW
6515  */
6516 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
6517 
6518 /* reg_ricnt_error_packets
6519  * A count of errored frames that do not pass the router checks.
6520  * Access: RW
6521  */
6522 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
6523 
6524 /* reg_ricnt_discrad_packets
6525  * A count of non-errored frames that do not pass the router checks.
6526  * Access: RW
6527  */
6528 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
6529 
6530 /* reg_ricnt_error_bytes
6531  * A count of L3 data and padding octets not including L2 headers
6532  * for errored frames.
6533  * Access: RW
6534  */
6535 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
6536 
6537 /* reg_ricnt_discard_bytes
6538  * A count of L3 data and padding octets not including L2 headers
6539  * for non-errored frames that do not pass the router checks.
6540  * Access: RW
6541  */
6542 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
6543 
6544 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
6545                                         enum mlxsw_reg_ricnt_opcode op)
6546 {
6547         MLXSW_REG_ZERO(ricnt, payload);
6548         mlxsw_reg_ricnt_op_set(payload, op);
6549         mlxsw_reg_ricnt_counter_index_set(payload, index);
6550         mlxsw_reg_ricnt_counter_set_type_set(payload,
6551                                              MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
6552 }
6553 
6554 /* RRCR - Router Rules Copy Register Layout
6555  * ----------------------------------------
6556  * This register is used for moving and copying route entry rules.
6557  */
6558 #define MLXSW_REG_RRCR_ID 0x800F
6559 #define MLXSW_REG_RRCR_LEN 0x24
6560 
6561 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
6562 
6563 enum mlxsw_reg_rrcr_op {
6564         /* Move rules */
6565         MLXSW_REG_RRCR_OP_MOVE,
6566         /* Copy rules */
6567         MLXSW_REG_RRCR_OP_COPY,
6568 };
6569 
6570 /* reg_rrcr_op
6571  * Access: WO
6572  */
6573 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
6574 
6575 /* reg_rrcr_offset
6576  * Offset within the region from which to copy/move.
6577  * Access: Index
6578  */
6579 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
6580 
6581 /* reg_rrcr_size
6582  * The number of rules to copy/move.
6583  * Access: WO
6584  */
6585 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
6586 
6587 /* reg_rrcr_table_id
6588  * Identifier of the table on which to perform the operation. Encoding is the
6589  * same as in RTAR.key_type
6590  * Access: Index
6591  */
6592 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
6593 
6594 /* reg_rrcr_dest_offset
6595  * Offset within the region to which to copy/move
6596  * Access: Index
6597  */
6598 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
6599 
6600 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
6601                                        u16 offset, u16 size,
6602                                        enum mlxsw_reg_rtar_key_type table_id,
6603                                        u16 dest_offset)
6604 {
6605         MLXSW_REG_ZERO(rrcr, payload);
6606         mlxsw_reg_rrcr_op_set(payload, op);
6607         mlxsw_reg_rrcr_offset_set(payload, offset);
6608         mlxsw_reg_rrcr_size_set(payload, size);
6609         mlxsw_reg_rrcr_table_id_set(payload, table_id);
6610         mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
6611 }
6612 
6613 /* RALTA - Router Algorithmic LPM Tree Allocation Register
6614  * -------------------------------------------------------
6615  * RALTA is used to allocate the LPM trees of the SHSPM method.
6616  */
6617 #define MLXSW_REG_RALTA_ID 0x8010
6618 #define MLXSW_REG_RALTA_LEN 0x04
6619 
6620 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
6621 
6622 /* reg_ralta_op
6623  * opcode (valid for Write, must be 0 on Read)
6624  * 0 - allocate a tree
6625  * 1 - deallocate a tree
6626  * Access: OP
6627  */
6628 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
6629 
6630 enum mlxsw_reg_ralxx_protocol {
6631         MLXSW_REG_RALXX_PROTOCOL_IPV4,
6632         MLXSW_REG_RALXX_PROTOCOL_IPV6,
6633 };
6634 
6635 /* reg_ralta_protocol
6636  * Protocol.
6637  * Deallocation opcode: Reserved.
6638  * Access: RW
6639  */
6640 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
6641 
6642 /* reg_ralta_tree_id
6643  * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
6644  * the tree identifier (managed by software).
6645  * Note that tree_id 0 is allocated for a default-route tree.
6646  * Access: Index
6647  */
6648 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
6649 
6650 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
6651                                         enum mlxsw_reg_ralxx_protocol protocol,
6652                                         u8 tree_id)
6653 {
6654         MLXSW_REG_ZERO(ralta, payload);
6655         mlxsw_reg_ralta_op_set(payload, !alloc);
6656         mlxsw_reg_ralta_protocol_set(payload, protocol);
6657         mlxsw_reg_ralta_tree_id_set(payload, tree_id);
6658 }
6659 
6660 /* RALST - Router Algorithmic LPM Structure Tree Register
6661  * ------------------------------------------------------
6662  * RALST is used to set and query the structure of an LPM tree.
6663  * The structure of the tree must be sorted as a sorted binary tree, while
6664  * each node is a bin that is tagged as the length of the prefixes the lookup
6665  * will refer to. Therefore, bin X refers to a set of entries with prefixes
6666  * of X bits to match with the destination address. The bin 0 indicates
6667  * the default action, when there is no match of any prefix.
6668  */
6669 #define MLXSW_REG_RALST_ID 0x8011
6670 #define MLXSW_REG_RALST_LEN 0x104
6671 
6672 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
6673 
6674 /* reg_ralst_root_bin
6675  * The bin number of the root bin.
6676  * 0<root_bin=<(length of IP address)
6677  * For a default-route tree configure 0xff
6678  * Access: RW
6679  */
6680 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
6681 
6682 /* reg_ralst_tree_id
6683  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6684  * Access: Index
6685  */
6686 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
6687 
6688 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
6689 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
6690 #define MLXSW_REG_RALST_BIN_COUNT 128
6691 
6692 /* reg_ralst_left_child_bin
6693  * Holding the children of the bin according to the stored tree's structure.
6694  * For trees composed of less than 4 blocks, the bins in excess are reserved.
6695  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6696  * Access: RW
6697  */
6698 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
6699 
6700 /* reg_ralst_right_child_bin
6701  * Holding the children of the bin according to the stored tree's structure.
6702  * For trees composed of less than 4 blocks, the bins in excess are reserved.
6703  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6704  * Access: RW
6705  */
6706 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
6707                      false);
6708 
6709 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
6710 {
6711         MLXSW_REG_ZERO(ralst, payload);
6712 
6713         /* Initialize all bins to have no left or right child */
6714         memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
6715                MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
6716 
6717         mlxsw_reg_ralst_root_bin_set(payload, root_bin);
6718         mlxsw_reg_ralst_tree_id_set(payload, tree_id);
6719 }
6720 
6721 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
6722                                             u8 left_child_bin,
6723                                             u8 right_child_bin)
6724 {
6725         int bin_index = bin_number - 1;
6726 
6727         mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
6728         mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
6729                                             right_child_bin);
6730 }
6731 
6732 /* RALTB - Router Algorithmic LPM Tree Binding Register
6733  * ----------------------------------------------------
6734  * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
6735  */
6736 #define MLXSW_REG_RALTB_ID 0x8012
6737 #define MLXSW_REG_RALTB_LEN 0x04
6738 
6739 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
6740 
6741 /* reg_raltb_virtual_router
6742  * Virtual Router ID
6743  * Range is 0..cap_max_virtual_routers-1
6744  * Access: Index
6745  */
6746 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
6747 
6748 /* reg_raltb_protocol
6749  * Protocol.
6750  * Access: Index
6751  */
6752 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
6753 
6754 /* reg_raltb_tree_id
6755  * Tree to be used for the {virtual_router, protocol}
6756  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6757  * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
6758  * Access: RW
6759  */
6760 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
6761 
6762 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
6763                                         enum mlxsw_reg_ralxx_protocol protocol,
6764                                         u8 tree_id)
6765 {
6766         MLXSW_REG_ZERO(raltb, payload);
6767         mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
6768         mlxsw_reg_raltb_protocol_set(payload, protocol);
6769         mlxsw_reg_raltb_tree_id_set(payload, tree_id);
6770 }
6771 
6772 /* RALUE - Router Algorithmic LPM Unicast Entry Register
6773  * -----------------------------------------------------
6774  * RALUE is used to configure and query LPM entries that serve
6775  * the Unicast protocols.
6776  */
6777 #define MLXSW_REG_RALUE_ID 0x8013
6778 #define MLXSW_REG_RALUE_LEN 0x38
6779 
6780 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
6781 
6782 /* reg_ralue_protocol
6783  * Protocol.
6784  * Access: Index
6785  */
6786 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
6787 
6788 enum mlxsw_reg_ralue_op {
6789         /* Read operation. If entry doesn't exist, the operation fails. */
6790         MLXSW_REG_RALUE_OP_QUERY_READ = 0,
6791         /* Clear on read operation. Used to read entry and
6792          * clear Activity bit.
6793          */
6794         MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
6795         /* Write operation. Used to write a new entry to the table. All RW
6796          * fields are written for new entry. Activity bit is set
6797          * for new entries.
6798          */
6799         MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
6800         /* Update operation. Used to update an existing route entry and
6801          * only update the RW fields that are detailed in the field
6802          * op_u_mask. If entry doesn't exist, the operation fails.
6803          */
6804         MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
6805         /* Clear activity. The Activity bit (the field a) is cleared
6806          * for the entry.
6807          */
6808         MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
6809         /* Delete operation. Used to delete an existing entry. If entry
6810          * doesn't exist, the operation fails.
6811          */
6812         MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
6813 };
6814 
6815 /* reg_ralue_op
6816  * Operation.
6817  * Access: OP
6818  */
6819 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
6820 
6821 /* reg_ralue_a
6822  * Activity. Set for new entries. Set if a packet lookup has hit on the
6823  * specific entry, only if the entry is a route. To clear the a bit, use
6824  * "clear activity" op.
6825  * Enabled by activity_dis in RGCR
6826  * Access: RO
6827  */
6828 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
6829 
6830 /* reg_ralue_virtual_router
6831  * Virtual Router ID
6832  * Range is 0..cap_max_virtual_routers-1
6833  * Access: Index
6834  */
6835 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
6836 
6837 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE    BIT(0)
6838 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN       BIT(1)
6839 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION        BIT(2)
6840 
6841 /* reg_ralue_op_u_mask
6842  * opcode update mask.
6843  * On read operation, this field is reserved.
6844  * This field is valid for update opcode, otherwise - reserved.
6845  * This field is a bitmask of the fields that should be updated.
6846  * Access: WO
6847  */
6848 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
6849 
6850 /* reg_ralue_prefix_len
6851  * Number of bits in the prefix of the LPM route.
6852  * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
6853  * two entries in the physical HW table.
6854  * Access: Index
6855  */
6856 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
6857 
6858 /* reg_ralue_dip*
6859  * The prefix of the route or of the marker that the object of the LPM
6860  * is compared with. The most significant bits of the dip are the prefix.
6861  * The least significant bits must be '0' if the prefix_len is smaller
6862  * than 128 for IPv6 or smaller than 32 for IPv4.
6863  * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
6864  * Access: Index
6865  */
6866 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
6867 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
6868 
6869 enum mlxsw_reg_ralue_entry_type {
6870         MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
6871         MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
6872         MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
6873 };
6874 
6875 /* reg_ralue_entry_type
6876  * Entry type.
6877  * Note - for Marker entries, the action_type and action fields are reserved.
6878  * Access: RW
6879  */
6880 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
6881 
6882 /* reg_ralue_bmp_len
6883  * The best match prefix length in the case that there is no match for
6884  * longer prefixes.
6885  * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
6886  * Note for any update operation with entry_type modification this
6887  * field must be set.
6888  * Access: RW
6889  */
6890 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
6891 
6892 enum mlxsw_reg_ralue_action_type {
6893         MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
6894         MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
6895         MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
6896 };
6897 
6898 /* reg_ralue_action_type
6899  * Action Type
6900  * Indicates how the IP address is connected.
6901  * It can be connected to a local subnet through local_erif or can be
6902  * on a remote subnet connected through a next-hop router,
6903  * or transmitted to the CPU.
6904  * Reserved when entry_type = MARKER_ENTRY
6905  * Access: RW
6906  */
6907 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
6908 
6909 enum mlxsw_reg_ralue_trap_action {
6910         MLXSW_REG_RALUE_TRAP_ACTION_NOP,
6911         MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
6912         MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
6913         MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
6914         MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
6915 };
6916 
6917 /* reg_ralue_trap_action
6918  * Trap action.
6919  * For IP2ME action, only NOP and MIRROR are possible.
6920  * Access: RW
6921  */
6922 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
6923 
6924 /* reg_ralue_trap_id
6925  * Trap ID to be reported to CPU.
6926  * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
6927  * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
6928  * Access: RW
6929  */
6930 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
6931 
6932 /* reg_ralue_adjacency_index
6933  * Points to the first entry of the group-based ECMP.
6934  * Only relevant in case of REMOTE action.
6935  * Access: RW
6936  */
6937 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
6938 
6939 /* reg_ralue_ecmp_size
6940  * Amount of sequential entries starting
6941  * from the adjacency_index (the number of ECMPs).
6942  * The valid range is 1-64, 512, 1024, 2048 and 4096.
6943  * Reserved when trap_action is TRAP or DISCARD_ERROR.
6944  * Only relevant in case of REMOTE action.
6945  * Access: RW
6946  */
6947 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
6948 
6949 /* reg_ralue_local_erif
6950  * Egress Router Interface.
6951  * Only relevant in case of LOCAL action.
6952  * Access: RW
6953  */
6954 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
6955 
6956 /* reg_ralue_ip2me_v
6957  * Valid bit for the tunnel_ptr field.
6958  * If valid = 0 then trap to CPU as IP2ME trap ID.
6959  * If valid = 1 and the packet format allows NVE or IPinIP tunnel
6960  * decapsulation then tunnel decapsulation is done.
6961  * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
6962  * decapsulation then trap as IP2ME trap ID.
6963  * Only relevant in case of IP2ME action.
6964  * Access: RW
6965  */
6966 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
6967 
6968 /* reg_ralue_ip2me_tunnel_ptr
6969  * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
6970  * For Spectrum, pointer to KVD Linear.
6971  * Only relevant in case of IP2ME action.
6972  * Access: RW
6973  */
6974 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
6975 
6976 static inline void mlxsw_reg_ralue_pack(char *payload,
6977                                         enum mlxsw_reg_ralxx_protocol protocol,
6978                                         enum mlxsw_reg_ralue_op op,
6979                                         u16 virtual_router, u8 prefix_len)
6980 {
6981         MLXSW_REG_ZERO(ralue, payload);
6982         mlxsw_reg_ralue_protocol_set(payload, protocol);
6983         mlxsw_reg_ralue_op_set(payload, op);
6984         mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
6985         mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
6986         mlxsw_reg_ralue_entry_type_set(payload,
6987                                        MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
6988         mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
6989 }
6990 
6991 static inline void mlxsw_reg_ralue_pack4(char *payload,
6992                                          enum mlxsw_reg_ralxx_protocol protocol,
6993                                          enum mlxsw_reg_ralue_op op,
6994                                          u16 virtual_router, u8 prefix_len,
6995                                          u32 dip)
6996 {
6997         mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6998         mlxsw_reg_ralue_dip4_set(payload, dip);
6999 }
7000 
7001 static inline void mlxsw_reg_ralue_pack6(char *payload,
7002                                          enum mlxsw_reg_ralxx_protocol protocol,
7003                                          enum mlxsw_reg_ralue_op op,
7004                                          u16 virtual_router, u8 prefix_len,
7005                                          const void *dip)
7006 {
7007         mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
7008         mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
7009 }
7010 
7011 static inline void
7012 mlxsw_reg_ralue_act_remote_pack(char *payload,
7013                                 enum mlxsw_reg_ralue_trap_action trap_action,
7014                                 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
7015 {
7016         mlxsw_reg_ralue_action_type_set(payload,
7017                                         MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
7018         mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7019         mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7020         mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
7021         mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
7022 }
7023 
7024 static inline void
7025 mlxsw_reg_ralue_act_local_pack(char *payload,
7026                                enum mlxsw_reg_ralue_trap_action trap_action,
7027                                u16 trap_id, u16 local_erif)
7028 {
7029         mlxsw_reg_ralue_action_type_set(payload,
7030                                         MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
7031         mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7032         mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7033         mlxsw_reg_ralue_local_erif_set(payload, local_erif);
7034 }
7035 
7036 static inline void
7037 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
7038 {
7039         mlxsw_reg_ralue_action_type_set(payload,
7040                                         MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7041 }
7042 
7043 static inline void
7044 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
7045 {
7046         mlxsw_reg_ralue_action_type_set(payload,
7047                                         MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7048         mlxsw_reg_ralue_ip2me_v_set(payload, 1);
7049         mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
7050 }
7051 
7052 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
7053  * ----------------------------------------------------------
7054  * The RAUHT register is used to configure and query the Unicast Host table in
7055  * devices that implement the Algorithmic LPM.
7056  */
7057 #define MLXSW_REG_RAUHT_ID 0x8014
7058 #define MLXSW_REG_RAUHT_LEN 0x74
7059 
7060 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
7061 
7062 enum mlxsw_reg_rauht_type {
7063         MLXSW_REG_RAUHT_TYPE_IPV4,
7064         MLXSW_REG_RAUHT_TYPE_IPV6,
7065 };
7066 
7067 /* reg_rauht_type
7068  * Access: Index
7069  */
7070 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
7071 
7072 enum mlxsw_reg_rauht_op {
7073         MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
7074         /* Read operation */
7075         MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
7076         /* Clear on read operation. Used to read entry and clear
7077          * activity bit.
7078          */
7079         MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
7080         /* Add. Used to write a new entry to the table. All R/W fields are
7081          * relevant for new entry. Activity bit is set for new entries.
7082          */
7083         MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
7084         /* Update action. Used to update an existing route entry and
7085          * only update the following fields:
7086          * trap_action, trap_id, mac, counter_set_type, counter_index
7087          */
7088         MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
7089         /* Clear activity. A bit is cleared for the entry. */
7090         MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
7091         /* Delete entry */
7092         MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
7093         /* Delete all host entries on a RIF. In this command, dip
7094          * field is reserved.
7095          */
7096 };
7097 
7098 /* reg_rauht_op
7099  * Access: OP
7100  */
7101 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
7102 
7103 /* reg_rauht_a
7104  * Activity. Set for new entries. Set if a packet lookup has hit on
7105  * the specific entry.
7106  * To clear the a bit, use "clear activity" op.
7107  * Enabled by activity_dis in RGCR
7108  * Access: RO
7109  */
7110 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
7111 
7112 /* reg_rauht_rif
7113  * Router Interface
7114  * Access: Index
7115  */
7116 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
7117 
7118 /* reg_rauht_dip*
7119  * Destination address.
7120  * Access: Index
7121  */
7122 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
7123 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
7124 
7125 enum mlxsw_reg_rauht_trap_action {
7126         MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
7127         MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
7128         MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
7129         MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
7130         MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
7131 };
7132 
7133 /* reg_rauht_trap_action
7134  * Access: RW
7135  */
7136 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
7137 
7138 enum mlxsw_reg_rauht_trap_id {
7139         MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
7140         MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
7141 };
7142 
7143 /* reg_rauht_trap_id
7144  * Trap ID to be reported to CPU.
7145  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
7146  * For trap_action of NOP, MIRROR and DISCARD_ERROR,
7147  * trap_id is reserved.
7148  * Access: RW
7149  */
7150 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
7151 
7152 /* reg_rauht_counter_set_type
7153  * Counter set type for flow counters
7154  * Access: RW
7155  */
7156 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
7157 
7158 /* reg_rauht_counter_index
7159  * Counter index for flow counters
7160  * Access: RW
7161  */
7162 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
7163 
7164 /* reg_rauht_mac
7165  * MAC address.
7166  * Access: RW
7167  */
7168 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
7169 
7170 static inline void mlxsw_reg_rauht_pack(char *payload,
7171                                         enum mlxsw_reg_rauht_op op, u16 rif,
7172                                         const char *mac)
7173 {
7174         MLXSW_REG_ZERO(rauht, payload);
7175         mlxsw_reg_rauht_op_set(payload, op);
7176         mlxsw_reg_rauht_rif_set(payload, rif);
7177         mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
7178 }
7179 
7180 static inline void mlxsw_reg_rauht_pack4(char *payload,
7181                                          enum mlxsw_reg_rauht_op op, u16 rif,
7182                                          const char *mac, u32 dip)
7183 {
7184         mlxsw_reg_rauht_pack(payload, op, rif, mac);
7185         mlxsw_reg_rauht_dip4_set(payload, dip);
7186 }
7187 
7188 static inline void mlxsw_reg_rauht_pack6(char *payload,
7189                                          enum mlxsw_reg_rauht_op op, u16 rif,
7190                                          const char *mac, const char *dip)
7191 {
7192         mlxsw_reg_rauht_pack(payload, op, rif, mac);
7193         mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
7194         mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
7195 }
7196 
7197 static inline void mlxsw_reg_rauht_pack_counter(char *payload,
7198                                                 u64 counter_index)
7199 {
7200         mlxsw_reg_rauht_counter_index_set(payload, counter_index);
7201         mlxsw_reg_rauht_counter_set_type_set(payload,
7202                                              MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
7203 }
7204 
7205 /* RALEU - Router Algorithmic LPM ECMP Update Register
7206  * ---------------------------------------------------
7207  * The register enables updating the ECMP section in the action for multiple
7208  * LPM Unicast entries in a single operation. The update is executed to
7209  * all entries of a {virtual router, protocol} tuple using the same ECMP group.
7210  */
7211 #define MLXSW_REG_RALEU_ID 0x8015
7212 #define MLXSW_REG_RALEU_LEN 0x28
7213 
7214 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
7215 
7216 /* reg_raleu_protocol
7217  * Protocol.
7218  * Access: Index
7219  */
7220 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
7221 
7222 /* reg_raleu_virtual_router
7223  * Virtual Router ID
7224  * Range is 0..cap_max_virtual_routers-1
7225  * Access: Index
7226  */
7227 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
7228 
7229 /* reg_raleu_adjacency_index
7230  * Adjacency Index used for matching on the existing entries.
7231  * Access: Index
7232  */
7233 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
7234 
7235 /* reg_raleu_ecmp_size
7236  * ECMP Size used for matching on the existing entries.
7237  * Access: Index
7238  */
7239 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
7240 
7241 /* reg_raleu_new_adjacency_index
7242  * New Adjacency Index.
7243  * Access: WO
7244  */
7245 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
7246 
7247 /* reg_raleu_new_ecmp_size
7248  * New ECMP Size.
7249  * Access: WO
7250  */
7251 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
7252 
7253 static inline void mlxsw_reg_raleu_pack(char *payload,
7254                                         enum mlxsw_reg_ralxx_protocol protocol,
7255                                         u16 virtual_router,
7256                                         u32 adjacency_index, u16 ecmp_size,
7257                                         u32 new_adjacency_index,
7258                                         u16 new_ecmp_size)
7259 {
7260         MLXSW_REG_ZERO(raleu, payload);
7261         mlxsw_reg_raleu_protocol_set(payload, protocol);
7262         mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
7263         mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
7264         mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
7265         mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
7266         mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
7267 }
7268 
7269 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
7270  * ----------------------------------------------------------------
7271  * The RAUHTD register allows dumping entries from the Router Unicast Host
7272  * Table. For a given session an entry is dumped no more than one time. The
7273  * first RAUHTD access after reset is a new session. A session ends when the
7274  * num_rec response is smaller than num_rec request or for IPv4 when the
7275  * num_entries is smaller than 4. The clear activity affect the current session
7276  * or the last session if a new session has not started.
7277  */
7278 #define MLXSW_REG_RAUHTD_ID 0x8018
7279 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
7280 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
7281 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
7282 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
7283                 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
7284 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
7285 
7286 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
7287 
7288 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
7289 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
7290 
7291 /* reg_rauhtd_filter_fields
7292  * if a bit is '0' then the relevant field is ignored and dump is done
7293  * regardless of the field value
7294  * Bit0 - filter by activity: entry_a
7295  * Bit3 - filter by entry rip: entry_rif
7296  * Access: Index
7297  */
7298 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
7299 
7300 enum mlxsw_reg_rauhtd_op {
7301         MLXSW_REG_RAUHTD_OP_DUMP,
7302         MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
7303 };
7304 
7305 /* reg_rauhtd_op
7306  * Access: OP
7307  */
7308 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
7309 
7310 /* reg_rauhtd_num_rec
7311  * At request: number of records requested
7312  * At response: number of records dumped
7313  * For IPv4, each record has 4 entries at request and up to 4 entries
7314  * at response
7315  * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
7316  * Access: Index
7317  */
7318 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
7319 
7320 /* reg_rauhtd_entry_a
7321  * Dump only if activity has value of entry_a
7322  * Reserved if filter_fields bit0 is '0'
7323  * Access: Index
7324  */
7325 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
7326 
7327 enum mlxsw_reg_rauhtd_type {
7328         MLXSW_REG_RAUHTD_TYPE_IPV4,
7329         MLXSW_REG_RAUHTD_TYPE_IPV6,
7330 };
7331 
7332 /* reg_rauhtd_type
7333  * Dump only if record type is:
7334  * 0 - IPv4
7335  * 1 - IPv6
7336  * Access: Index
7337  */
7338 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
7339 
7340 /* reg_rauhtd_entry_rif
7341  * Dump only if RIF has value of entry_rif
7342  * Reserved if filter_fields bit3 is '0'
7343  * Access: Index
7344  */
7345 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
7346 
7347 static inline void mlxsw_reg_rauhtd_pack(char *payload,
7348                                          enum mlxsw_reg_rauhtd_type type)
7349 {
7350         MLXSW_REG_ZERO(rauhtd, payload);
7351         mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
7352         mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
7353         mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
7354         mlxsw_reg_rauhtd_entry_a_set(payload, 1);
7355         mlxsw_reg_rauhtd_type_set(payload, type);
7356 }
7357 
7358 /* reg_rauhtd_ipv4_rec_num_entries
7359  * Number of valid entries in this record:
7360  * 0 - 1 valid entry
7361  * 1 - 2 valid entries
7362  * 2 - 3 valid entries
7363  * 3 - 4 valid entries
7364  * Access: RO
7365  */
7366 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
7367                      MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
7368                      MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7369 
7370 /* reg_rauhtd_rec_type
7371  * Record type.
7372  * 0 - IPv4
7373  * 1 - IPv6
7374  * Access: RO
7375  */
7376 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
7377                      MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7378 
7379 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
7380 
7381 /* reg_rauhtd_ipv4_ent_a
7382  * Activity. Set for new entries. Set if a packet lookup has hit on the
7383  * specific entry.
7384  * Access: RO
7385  */
7386 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7387                      MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7388 
7389 /* reg_rauhtd_ipv4_ent_rif
7390  * Router interface.
7391  * Access: RO
7392  */
7393 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7394                      16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7395 
7396 /* reg_rauhtd_ipv4_ent_dip
7397  * Destination IPv4 address.
7398  * Access: RO
7399  */
7400 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7401                      32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
7402 
7403 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
7404 
7405 /* reg_rauhtd_ipv6_ent_a
7406  * Activity. Set for new entries. Set if a packet lookup has hit on the
7407  * specific entry.
7408  * Access: RO
7409  */
7410 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7411                      MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7412 
7413 /* reg_rauhtd_ipv6_ent_rif
7414  * Router interface.
7415  * Access: RO
7416  */
7417 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7418                      16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7419 
7420 /* reg_rauhtd_ipv6_ent_dip
7421  * Destination IPv6 address.
7422  * Access: RO
7423  */
7424 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
7425                        16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
7426 
7427 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
7428                                                     int ent_index, u16 *p_rif,
7429                                                     u32 *p_dip)
7430 {
7431         *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
7432         *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
7433 }
7434 
7435 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
7436                                                     int rec_index, u16 *p_rif,
7437                                                     char *p_dip)
7438 {
7439         *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
7440         mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
7441 }
7442 
7443 /* RTDP - Routing Tunnel Decap Properties Register
7444  * -----------------------------------------------
7445  * The RTDP register is used for configuring the tunnel decap properties of NVE
7446  * and IPinIP.
7447  */
7448 #define MLXSW_REG_RTDP_ID 0x8020
7449 #define MLXSW_REG_RTDP_LEN 0x44
7450 
7451 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
7452 
7453 enum mlxsw_reg_rtdp_type {
7454         MLXSW_REG_RTDP_TYPE_NVE,
7455         MLXSW_REG_RTDP_TYPE_IPIP,
7456 };
7457 
7458 /* reg_rtdp_type
7459  * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.
7460  * Access: RW
7461  */
7462 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
7463 
7464 /* reg_rtdp_tunnel_index
7465  * Index to the Decap entry.
7466  * For Spectrum, Index to KVD Linear.
7467  * Access: Index
7468  */
7469 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
7470 
7471 /* reg_rtdp_egress_router_interface
7472  * Underlay egress router interface.
7473  * Valid range is from 0 to cap_max_router_interfaces - 1
7474  * Access: RW
7475  */
7476 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
7477 
7478 /* IPinIP */
7479 
7480 /* reg_rtdp_ipip_irif
7481  * Ingress Router Interface for the overlay router
7482  * Access: RW
7483  */
7484 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
7485 
7486 enum mlxsw_reg_rtdp_ipip_sip_check {
7487         /* No sip checks. */
7488         MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
7489         /* Filter packet if underlay is not IPv4 or if underlay SIP does not
7490          * equal ipv4_usip.
7491          */
7492         MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
7493         /* Filter packet if underlay is not IPv6 or if underlay SIP does not
7494          * equal ipv6_usip.
7495          */
7496         MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
7497 };
7498 
7499 /* reg_rtdp_ipip_sip_check
7500  * SIP check to perform. If decapsulation failed due to these configurations
7501  * then trap_id is IPIP_DECAP_ERROR.
7502  * Access: RW
7503  */
7504 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
7505 
7506 /* If set, allow decapsulation of IPinIP (without GRE). */
7507 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP       BIT(0)
7508 /* If set, allow decapsulation of IPinGREinIP without a key. */
7509 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE        BIT(1)
7510 /* If set, allow decapsulation of IPinGREinIP with a key. */
7511 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY    BIT(2)
7512 
7513 /* reg_rtdp_ipip_type_check
7514  * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to
7515  * these configurations then trap_id is IPIP_DECAP_ERROR.
7516  * Access: RW
7517  */
7518 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
7519 
7520 /* reg_rtdp_ipip_gre_key_check
7521  * Whether GRE key should be checked. When check is enabled:
7522  * - A packet received as IPinIP (without GRE) will always pass.
7523  * - A packet received as IPinGREinIP without a key will not pass the check.
7524  * - A packet received as IPinGREinIP with a key will pass the check only if the
7525  *   key in the packet is equal to expected_gre_key.
7526  * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.
7527  * Access: RW
7528  */
7529 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
7530 
7531 /* reg_rtdp_ipip_ipv4_usip
7532  * Underlay IPv4 address for ipv4 source address check.
7533  * Reserved when sip_check is not '1'.
7534  * Access: RW
7535  */
7536 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
7537 
7538 /* reg_rtdp_ipip_ipv6_usip_ptr
7539  * This field is valid when sip_check is "sipv6 check explicitly". This is a
7540  * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index
7541  * is to the KVD linear.
7542  * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.
7543  * Access: RW
7544  */
7545 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
7546 
7547 /* reg_rtdp_ipip_expected_gre_key
7548  * GRE key for checking.
7549  * Reserved when gre_key_check is '0'.
7550  * Access: RW
7551  */
7552 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
7553 
7554 static inline void mlxsw_reg_rtdp_pack(char *payload,
7555                                        enum mlxsw_reg_rtdp_type type,
7556                                        u32 tunnel_index)
7557 {
7558         MLXSW_REG_ZERO(rtdp, payload);
7559         mlxsw_reg_rtdp_type_set(payload, type);
7560         mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
7561 }
7562 
7563 static inline void
7564 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
7565                           enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
7566                           unsigned int type_check, bool gre_key_check,
7567                           u32 ipv4_usip, u32 expected_gre_key)
7568 {
7569         mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
7570         mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
7571         mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
7572         mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
7573         mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
7574         mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
7575 }
7576 
7577 /* RIGR-V2 - Router Interface Group Register Version 2
7578  * ---------------------------------------------------
7579  * The RIGR_V2 register is used to add, remove and query egress interface list
7580  * of a multicast forwarding entry.
7581  */
7582 #define MLXSW_REG_RIGR2_ID 0x8023
7583 #define MLXSW_REG_RIGR2_LEN 0xB0
7584 
7585 #define MLXSW_REG_RIGR2_MAX_ERIFS 32
7586 
7587 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
7588 
7589 /* reg_rigr2_rigr_index
7590  * KVD Linear index.
7591  * Access: Index
7592  */
7593 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
7594 
7595 /* reg_rigr2_vnext
7596  * Next RIGR Index is valid.
7597  * Access: RW
7598  */
7599 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
7600 
7601 /* reg_rigr2_next_rigr_index
7602  * Next RIGR Index. The index is to the KVD linear.
7603  * Reserved when vnxet = '0'.
7604  * Access: RW
7605  */
7606 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
7607 
7608 /* reg_rigr2_vrmid
7609  * RMID Index is valid.
7610  * Access: RW
7611  */
7612 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
7613 
7614 /* reg_rigr2_rmid_index
7615  * RMID Index.
7616  * Range 0 .. max_mid - 1
7617  * Reserved when vrmid = '0'.
7618  * The index is to the Port Group Table (PGT)
7619  * Access: RW
7620  */
7621 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
7622 
7623 /* reg_rigr2_erif_entry_v
7624  * Egress Router Interface is valid.
7625  * Note that low-entries must be set if high-entries are set. For
7626  * example: if erif_entry[2].v is set then erif_entry[1].v and
7627  * erif_entry[0].v must be set.
7628  * Index can be from 0 to cap_mc_erif_list_entries-1
7629  * Access: RW
7630  */
7631 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
7632 
7633 /* reg_rigr2_erif_entry_erif
7634  * Egress Router Interface.
7635  * Valid range is from 0 to cap_max_router_interfaces - 1
7636  * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1
7637  * Access: RW
7638  */
7639 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
7640 
7641 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
7642                                         bool vnext, u32 next_rigr_index)
7643 {
7644         MLXSW_REG_ZERO(rigr2, payload);
7645         mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
7646         mlxsw_reg_rigr2_vnext_set(payload, vnext);
7647         mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
7648         mlxsw_reg_rigr2_vrmid_set(payload, 0);
7649         mlxsw_reg_rigr2_rmid_index_set(payload, 0);
7650 }
7651 
7652 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
7653                                                    bool v, u16 erif)
7654 {
7655         mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
7656         mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
7657 }
7658 
7659 /* RECR-V2 - Router ECMP Configuration Version 2 Register
7660  * ------------------------------------------------------
7661  */
7662 #define MLXSW_REG_RECR2_ID 0x8025
7663 #define MLXSW_REG_RECR2_LEN 0x38
7664 
7665 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
7666 
7667 /* reg_recr2_pp
7668  * Per-port configuration
7669  * Access: Index
7670  */
7671 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
7672 
7673 /* reg_recr2_sh
7674  * Symmetric hash
7675  * Access: RW
7676  */
7677 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
7678 
7679 /* reg_recr2_seed
7680  * Seed
7681  * Access: RW
7682  */
7683 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
7684 
7685 enum {
7686         /* Enable IPv4 fields if packet is not TCP and not UDP */
7687         MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3,
7688         /* Enable IPv4 fields if packet is TCP or UDP */
7689         MLXSW_REG_RECR2_IPV4_EN_TCP_UDP         = 4,
7690         /* Enable IPv6 fields if packet is not TCP and not UDP */
7691         MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5,
7692         /* Enable IPv6 fields if packet is TCP or UDP */
7693         MLXSW_REG_RECR2_IPV6_EN_TCP_UDP         = 6,
7694         /* Enable TCP/UDP header fields if packet is IPv4 */
7695         MLXSW_REG_RECR2_TCP_UDP_EN_IPV4         = 7,
7696         /* Enable TCP/UDP header fields if packet is IPv6 */
7697         MLXSW_REG_RECR2_TCP_UDP_EN_IPV6         = 8,
7698 };
7699 
7700 /* reg_recr2_outer_header_enables
7701  * Bit mask where each bit enables a specific layer to be included in
7702  * the hash calculation.
7703  * Access: RW
7704  */
7705 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
7706 
7707 enum {
7708         /* IPv4 Source IP */
7709         MLXSW_REG_RECR2_IPV4_SIP0                       = 9,
7710         MLXSW_REG_RECR2_IPV4_SIP3                       = 12,
7711         /* IPv4 Destination IP */
7712         MLXSW_REG_RECR2_IPV4_DIP0                       = 13,
7713         MLXSW_REG_RECR2_IPV4_DIP3                       = 16,
7714         /* IP Protocol */
7715         MLXSW_REG_RECR2_IPV4_PROTOCOL                   = 17,
7716         /* IPv6 Source IP */
7717         MLXSW_REG_RECR2_IPV6_SIP0_7                     = 21,
7718         MLXSW_REG_RECR2_IPV6_SIP8                       = 29,
7719         MLXSW_REG_RECR2_IPV6_SIP15                      = 36,
7720         /* IPv6 Destination IP */
7721         MLXSW_REG_RECR2_IPV6_DIP0_7                     = 37,
7722         MLXSW_REG_RECR2_IPV6_DIP8                       = 45,
7723         MLXSW_REG_RECR2_IPV6_DIP15                      = 52,
7724         /* IPv6 Next Header */
7725         MLXSW_REG_RECR2_IPV6_NEXT_HEADER                = 53,
7726         /* IPv6 Flow Label */
7727         MLXSW_REG_RECR2_IPV6_FLOW_LABEL                 = 57,
7728         /* TCP/UDP Source Port */
7729         MLXSW_REG_RECR2_TCP_UDP_SPORT                   = 74,
7730         /* TCP/UDP Destination Port */
7731         MLXSW_REG_RECR2_TCP_UDP_DPORT                   = 75,
7732 };
7733 
7734 /* reg_recr2_outer_header_fields_enable
7735  * Packet fields to enable for ECMP hash subject to outer_header_enable.
7736  * Access: RW
7737  */
7738 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
7739 
7740 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload)
7741 {
7742         int i;
7743 
7744         for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++)
7745                 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7746                                                                true);
7747 }
7748 
7749 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload)
7750 {
7751         int i;
7752 
7753         for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++)
7754                 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7755                                                                true);
7756 }
7757 
7758 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload)
7759 {
7760         int i = MLXSW_REG_RECR2_IPV6_SIP0_7;
7761 
7762         mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7763 
7764         i = MLXSW_REG_RECR2_IPV6_SIP8;
7765         for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++)
7766                 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7767                                                                true);
7768 }
7769 
7770 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload)
7771 {
7772         int i = MLXSW_REG_RECR2_IPV6_DIP0_7;
7773 
7774         mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7775 
7776         i = MLXSW_REG_RECR2_IPV6_DIP8;
7777         for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++)
7778                 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7779                                                                true);
7780 }
7781 
7782 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
7783 {
7784         MLXSW_REG_ZERO(recr2, payload);
7785         mlxsw_reg_recr2_pp_set(payload, false);
7786         mlxsw_reg_recr2_sh_set(payload, true);
7787         mlxsw_reg_recr2_seed_set(payload, seed);
7788 }
7789 
7790 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register
7791  * --------------------------------------------------------------
7792  * The RMFT_V2 register is used to configure and query the multicast table.
7793  */
7794 #define MLXSW_REG_RMFT2_ID 0x8027
7795 #define MLXSW_REG_RMFT2_LEN 0x174
7796 
7797 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
7798 
7799 /* reg_rmft2_v
7800  * Valid
7801  * Access: RW
7802  */
7803 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
7804 
7805 enum mlxsw_reg_rmft2_type {
7806         MLXSW_REG_RMFT2_TYPE_IPV4,
7807         MLXSW_REG_RMFT2_TYPE_IPV6
7808 };
7809 
7810 /* reg_rmft2_type
7811  * Access: Index
7812  */
7813 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
7814 
7815 enum mlxsw_sp_reg_rmft2_op {
7816         /* For Write:
7817          * Write operation. Used to write a new entry to the table. All RW
7818          * fields are relevant for new entry. Activity bit is set for new
7819          * entries - Note write with v (Valid) 0 will delete the entry.
7820          * For Query:
7821          * Read operation
7822          */
7823         MLXSW_REG_RMFT2_OP_READ_WRITE,
7824 };
7825 
7826 /* reg_rmft2_op
7827  * Operation.
7828  * Access: OP
7829  */
7830 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
7831 
7832 /* reg_rmft2_a
7833  * Activity. Set for new entries. Set if a packet lookup has hit on the specific
7834  * entry.
7835  * Access: RO
7836  */
7837 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
7838 
7839 /* reg_rmft2_offset
7840  * Offset within the multicast forwarding table to write to.
7841  * Access: Index
7842  */
7843 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
7844 
7845 /* reg_rmft2_virtual_router
7846  * Virtual Router ID. Range from 0..cap_max_virtual_routers-1
7847  * Access: RW
7848  */
7849 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
7850 
7851 enum mlxsw_reg_rmft2_irif_mask {
7852         MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
7853         MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
7854 };
7855 
7856 /* reg_rmft2_irif_mask
7857  * Ingress RIF mask.
7858  * Access: RW
7859  */
7860 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
7861 
7862 /* reg_rmft2_irif
7863  * Ingress RIF index.
7864  * Access: RW
7865  */
7866 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
7867 
7868 /* reg_rmft2_dip{4,6}
7869  * Destination IPv4/6 address
7870  * Access: RW
7871  */
7872 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
7873 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
7874 
7875 /* reg_rmft2_dip{4,6}_mask
7876  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7877  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7878  * Access: RW
7879  */
7880 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
7881 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
7882 
7883 /* reg_rmft2_sip{4,6}
7884  * Source IPv4/6 address
7885  * Access: RW
7886  */
7887 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
7888 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
7889 
7890 /* reg_rmft2_sip{4,6}_mask
7891  * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7892  * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7893  * Access: RW
7894  */
7895 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
7896 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
7897 
7898 /* reg_rmft2_flexible_action_set
7899  * ACL action set. The only supported action types in this field and in any
7900  * action-set pointed from here are as follows:
7901  * 00h: ACTION_NULL
7902  * 01h: ACTION_MAC_TTL, only TTL configuration is supported.
7903  * 03h: ACTION_TRAP
7904  * 06h: ACTION_QOS
7905  * 08h: ACTION_POLICING_MONITORING
7906  * 10h: ACTION_ROUTER_MC
7907  * Access: RW
7908  */
7909 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
7910                MLXSW_REG_FLEX_ACTION_SET_LEN);
7911 
7912 static inline void
7913 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
7914                             u16 virtual_router,
7915                             enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7916                             const char *flex_action_set)
7917 {
7918         MLXSW_REG_ZERO(rmft2, payload);
7919         mlxsw_reg_rmft2_v_set(payload, v);
7920         mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
7921         mlxsw_reg_rmft2_offset_set(payload, offset);
7922         mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
7923         mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
7924         mlxsw_reg_rmft2_irif_set(payload, irif);
7925         if (flex_action_set)
7926                 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
7927                                                               flex_action_set);
7928 }
7929 
7930 static inline void
7931 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7932                           enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7933                           u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
7934                           const char *flexible_action_set)
7935 {
7936         mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7937                                     irif_mask, irif, flexible_action_set);
7938         mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
7939         mlxsw_reg_rmft2_dip4_set(payload, dip4);
7940         mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
7941         mlxsw_reg_rmft2_sip4_set(payload, sip4);
7942         mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
7943 }
7944 
7945 static inline void
7946 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7947                           enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7948                           struct in6_addr dip6, struct in6_addr dip6_mask,
7949                           struct in6_addr sip6, struct in6_addr sip6_mask,
7950                           const char *flexible_action_set)
7951 {
7952         mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7953                                     irif_mask, irif, flexible_action_set);
7954         mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
7955         mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
7956         mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
7957         mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
7958         mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
7959 }
7960 
7961 /* MFCR - Management Fan Control Register
7962  * --------------------------------------
7963  * This register controls the settings of the Fan Speed PWM mechanism.
7964  */
7965 #define MLXSW_REG_MFCR_ID 0x9001
7966 #define MLXSW_REG_MFCR_LEN 0x08
7967 
7968 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
7969 
7970 enum mlxsw_reg_mfcr_pwm_frequency {
7971         MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
7972         MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
7973         MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
7974         MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
7975         MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
7976         MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
7977         MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
7978         MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
7979 };
7980 
7981 /* reg_mfcr_pwm_frequency
7982  * Controls the frequency of the PWM signal.
7983  * Access: RW
7984  */
7985 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
7986 
7987 #define MLXSW_MFCR_TACHOS_MAX 10
7988 
7989 /* reg_mfcr_tacho_active
7990  * Indicates which of the tachometer is active (bit per tachometer).
7991  * Access: RO
7992  */
7993 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
7994 
7995 #define MLXSW_MFCR_PWMS_MAX 5
7996 
7997 /* reg_mfcr_pwm_active
7998  * Indicates which of the PWM control is active (bit per PWM).
7999  * Access: RO
8000  */
8001 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
8002 
8003 static inline void
8004 mlxsw_reg_mfcr_pack(char *payload,
8005                     enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
8006 {
8007         MLXSW_REG_ZERO(mfcr, payload);
8008         mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
8009 }
8010 
8011 static inline void
8012 mlxsw_reg_mfcr_unpack(char *payload,
8013                       enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
8014                       u16 *p_tacho_active, u8 *p_pwm_active)
8015 {
8016         *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
8017         *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
8018         *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
8019 }
8020 
8021 /* MFSC - Management Fan Speed Control Register
8022  * --------------------------------------------
8023  * This register controls the settings of the Fan Speed PWM mechanism.
8024  */
8025 #define MLXSW_REG_MFSC_ID 0x9002
8026 #define MLXSW_REG_MFSC_LEN 0x08
8027 
8028 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
8029 
8030 /* reg_mfsc_pwm
8031  * Fan pwm to control / monitor.
8032  * Access: Index
8033  */
8034 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
8035 
8036 /* reg_mfsc_pwm_duty_cycle
8037  * Controls the duty cycle of the PWM. Value range from 0..255 to
8038  * represent duty cycle of 0%...100%.
8039  * Access: RW
8040  */
8041 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
8042 
8043 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
8044                                        u8 pwm_duty_cycle)
8045 {
8046         MLXSW_REG_ZERO(mfsc, payload);
8047         mlxsw_reg_mfsc_pwm_set(payload, pwm);
8048         mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
8049 }
8050 
8051 /* MFSM - Management Fan Speed Measurement
8052  * ---------------------------------------
8053  * This register controls the settings of the Tacho measurements and
8054  * enables reading the Tachometer measurements.
8055  */
8056 #define MLXSW_REG_MFSM_ID 0x9003
8057 #define MLXSW_REG_MFSM_LEN 0x08
8058 
8059 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
8060 
8061 /* reg_mfsm_tacho
8062  * Fan tachometer index.
8063  * Access: Index
8064  */
8065 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
8066 
8067 /* reg_mfsm_rpm
8068  * Fan speed (round per minute).
8069  * Access: RO
8070  */
8071 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
8072 
8073 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
8074 {
8075         MLXSW_REG_ZERO(mfsm, payload);
8076         mlxsw_reg_mfsm_tacho_set(payload, tacho);
8077 }
8078 
8079 /* MFSL - Management Fan Speed Limit Register
8080  * ------------------------------------------
8081  * The Fan Speed Limit register is used to configure the fan speed
8082  * event / interrupt notification mechanism. Fan speed threshold are
8083  * defined for both under-speed and over-speed.
8084  */
8085 #define MLXSW_REG_MFSL_ID 0x9004
8086 #define MLXSW_REG_MFSL_LEN 0x0C
8087 
8088 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
8089 
8090 /* reg_mfsl_tacho
8091  * Fan tachometer index.
8092  * Access: Index
8093  */
8094 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
8095 
8096 /* reg_mfsl_tach_min
8097  * Tachometer minimum value (minimum RPM).
8098  * Access: RW
8099  */
8100 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
8101 
8102 /* reg_mfsl_tach_max
8103  * Tachometer maximum value (maximum RPM).
8104  * Access: RW
8105  */
8106 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
8107 
8108 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
8109                                        u16 tach_min, u16 tach_max)
8110 {
8111         MLXSW_REG_ZERO(mfsl, payload);
8112         mlxsw_reg_mfsl_tacho_set(payload, tacho);
8113         mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
8114         mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
8115 }
8116 
8117 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
8118                                          u16 *p_tach_min, u16 *p_tach_max)
8119 {
8120         if (p_tach_min)
8121                 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
8122 
8123         if (p_tach_max)
8124                 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
8125 }
8126 
8127 /* FORE - Fan Out of Range Event Register
8128  * --------------------------------------
8129  * This register reports the status of the controlled fans compared to the
8130  * range defined by the MFSL register.
8131  */
8132 #define MLXSW_REG_FORE_ID 0x9007
8133 #define MLXSW_REG_FORE_LEN 0x0C
8134 
8135 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
8136 
8137 /* fan_under_limit
8138  * Fan speed is below the low limit defined in MFSL register. Each bit relates
8139  * to a single tachometer and indicates the specific tachometer reading is
8140  * below the threshold.
8141  * Access: RO
8142  */
8143 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
8144 
8145 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
8146                                          bool *fault)
8147 {
8148         u16 limit;
8149 
8150         if (fault) {
8151                 limit = mlxsw_reg_fore_fan_under_limit_get(payload);
8152                 *fault = limit & BIT(tacho);
8153         }
8154 }
8155 
8156 /* MTCAP - Management Temperature Capabilities
8157  * -------------------------------------------
8158  * This register exposes the capabilities of the device and
8159  * system temperature sensing.
8160  */
8161 #define MLXSW_REG_MTCAP_ID 0x9009
8162 #define MLXSW_REG_MTCAP_LEN 0x08
8163 
8164 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
8165 
8166 /* reg_mtcap_sensor_count
8167  * Number of sensors supported by the device.
8168  * This includes the QSFP module sensors (if exists in the QSFP module).
8169  * Access: RO
8170  */
8171 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
8172 
8173 /* MTMP - Management Temperature
8174  * -----------------------------
8175  * This register controls the settings of the temperature measurements
8176  * and enables reading the temperature measurements. Note that temperature
8177  * is in 0.125 degrees Celsius.
8178  */
8179 #define MLXSW_REG_MTMP_ID 0x900A
8180 #define MLXSW_REG_MTMP_LEN 0x20
8181 
8182 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
8183 
8184 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64
8185 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256
8186 /* reg_mtmp_sensor_index
8187  * Sensors index to access.
8188  * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
8189  * (module 0 is mapped to sensor_index 64).
8190  * Access: Index
8191  */
8192 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
8193 
8194 /* Convert to milli degrees Celsius */
8195 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \
8196                                           ((v_) >= 0) ? ((v_) * 125) : \
8197                                           ((s16)((GENMASK(15, 0) + (v_) + 1) \
8198                                            * 125)); })
8199 
8200 /* reg_mtmp_temperature
8201  * Temperature reading from the sensor. Reading is in 0.125 Celsius
8202  * degrees units.
8203  * Access: RO
8204  */
8205 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
8206 
8207 /* reg_mtmp_mte
8208  * Max Temperature Enable - enables measuring the max temperature on a sensor.
8209  * Access: RW
8210  */
8211 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
8212 
8213 /* reg_mtmp_mtr
8214  * Max Temperature Reset - clears the value of the max temperature register.
8215  * Access: WO
8216  */
8217 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
8218 
8219 /* reg_mtmp_max_temperature
8220  * The highest measured temperature from the sensor.
8221  * When the bit mte is cleared, the field max_temperature is reserved.
8222  * Access: RO
8223  */
8224 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
8225 
8226 /* reg_mtmp_tee
8227  * Temperature Event Enable.
8228  * 0 - Do not generate event
8229  * 1 - Generate event
8230  * 2 - Generate single event
8231  * Access: RW
8232  */
8233 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
8234 
8235 #define MLXSW_REG_MTMP_THRESH_HI 0x348  /* 105 Celsius */
8236 
8237 /* reg_mtmp_temperature_threshold_hi
8238  * High threshold for Temperature Warning Event. In 0.125 Celsius.
8239  * Access: RW
8240  */
8241 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
8242 
8243 /* reg_mtmp_temperature_threshold_lo
8244  * Low threshold for Temperature Warning Event. In 0.125 Celsius.
8245  * Access: RW
8246  */
8247 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
8248 
8249 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
8250 
8251 /* reg_mtmp_sensor_name
8252  * Sensor Name
8253  * Access: RO
8254  */
8255 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
8256 
8257 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index,
8258                                        bool max_temp_enable,
8259                                        bool max_temp_reset)
8260 {
8261         MLXSW_REG_ZERO(mtmp, payload);
8262         mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
8263         mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
8264         mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
8265         mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
8266                                                     MLXSW_REG_MTMP_THRESH_HI);
8267 }
8268 
8269 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp,
8270                                          int *p_max_temp, char *sensor_name)
8271 {
8272         s16 temp;
8273 
8274         if (p_temp) {
8275                 temp = mlxsw_reg_mtmp_temperature_get(payload);
8276                 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8277         }
8278         if (p_max_temp) {
8279                 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
8280                 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8281         }
8282         if (sensor_name)
8283                 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
8284 }
8285 
8286 /* MTBR - Management Temperature Bulk Register
8287  * -------------------------------------------
8288  * This register is used for bulk temperature reading.
8289  */
8290 #define MLXSW_REG_MTBR_ID 0x900F
8291 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */
8292 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */
8293 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */
8294 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN +   \
8295                             MLXSW_REG_MTBR_REC_LEN *    \
8296                             MLXSW_REG_MTBR_REC_MAX_COUNT)
8297 
8298 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
8299 
8300 /* reg_mtbr_base_sensor_index
8301  * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors,
8302  * 64-127 are mapped to the SFP+/QSFP modules sequentially).
8303  * Access: Index
8304  */
8305 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
8306 
8307 /* reg_mtbr_num_rec
8308  * Request: Number of records to read
8309  * Response: Number of records read
8310  * See above description for more details.
8311  * Range 1..255
8312  * Access: RW
8313  */
8314 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
8315 
8316 /* reg_mtbr_rec_max_temp
8317  * The highest measured temperature from the sensor.
8318  * When the bit mte is cleared, the field max_temperature is reserved.
8319  * Access: RO
8320  */
8321 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
8322                      16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8323 
8324 /* reg_mtbr_rec_temp
8325  * Temperature reading from the sensor. Reading is in 0..125 Celsius
8326  * degrees units.
8327  * Access: RO
8328  */
8329 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
8330                      MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8331 
8332 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index,
8333                                        u8 num_rec)
8334 {
8335         MLXSW_REG_ZERO(mtbr, payload);
8336         mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
8337         mlxsw_reg_mtbr_num_rec_set(payload, num_rec);
8338 }
8339 
8340 /* Error codes from temperatute reading */
8341 enum mlxsw_reg_mtbr_temp_status {
8342         MLXSW_REG_MTBR_NO_CONN          = 0x8000,
8343         MLXSW_REG_MTBR_NO_TEMP_SENS     = 0x8001,
8344         MLXSW_REG_MTBR_INDEX_NA         = 0x8002,
8345         MLXSW_REG_MTBR_BAD_SENS_INFO    = 0x8003,
8346 };
8347 
8348 /* Base index for reading modules temperature */
8349 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
8350 
8351 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
8352                                               u16 *p_temp, u16 *p_max_temp)
8353 {
8354         if (p_temp)
8355                 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
8356         if (p_max_temp)
8357                 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
8358 }
8359 
8360 /* MCIA - Management Cable Info Access
8361  * -----------------------------------
8362  * MCIA register is used to access the SFP+ and QSFP connector's EPROM.
8363  */
8364 
8365 #define MLXSW_REG_MCIA_ID 0x9014
8366 #define MLXSW_REG_MCIA_LEN 0x40
8367 
8368 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
8369 
8370 /* reg_mcia_l
8371  * Lock bit. Setting this bit will lock the access to the specific
8372  * cable. Used for updating a full page in a cable EPROM. Any access
8373  * other then subsequence writes will fail while the port is locked.
8374  * Access: RW
8375  */
8376 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
8377 
8378 /* reg_mcia_module
8379  * Module number.
8380  * Access: Index
8381  */
8382 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
8383 
8384 /* reg_mcia_status
8385  * Module status.
8386  * Access: RO
8387  */
8388 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
8389 
8390 /* reg_mcia_i2c_device_address
8391  * I2C device address.
8392  * Access: RW
8393  */
8394 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
8395 
8396 /* reg_mcia_page_number
8397  * Page number.
8398  * Access: RW
8399  */
8400 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
8401 
8402 /* reg_mcia_device_address
8403  * Device address.
8404  * Access: RW
8405  */
8406 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
8407 
8408 /* reg_mcia_size
8409  * Number of bytes to read/write (up to 48 bytes).
8410  * Access: RW
8411  */
8412 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
8413 
8414 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH       256
8415 #define MLXSW_REG_MCIA_EEPROM_SIZE              48
8416 #define MLXSW_REG_MCIA_I2C_ADDR_LOW             0x50
8417 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH            0x51
8418 #define MLXSW_REG_MCIA_PAGE0_LO_OFF             0xa0
8419 #define MLXSW_REG_MCIA_TH_ITEM_SIZE             2
8420 #define MLXSW_REG_MCIA_TH_PAGE_NUM              3
8421 #define MLXSW_REG_MCIA_PAGE0_LO                 0
8422 #define MLXSW_REG_MCIA_TH_PAGE_OFF              0x80
8423 
8424 enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
8425         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC  = 0x00,
8426         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436   = 0x01,
8427         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636   = 0x03,
8428 };
8429 
8430 enum mlxsw_reg_mcia_eeprom_module_info_id {
8431         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP        = 0x03,
8432         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP       = 0x0C,
8433         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS  = 0x0D,
8434         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28     = 0x11,
8435         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD    = 0x18,
8436 };
8437 
8438 enum mlxsw_reg_mcia_eeprom_module_info {
8439         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
8440         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
8441         MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
8442 };
8443 
8444 /* reg_mcia_eeprom
8445  * Bytes to read/write.
8446  * Access: RW
8447  */
8448 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE);
8449 
8450 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
8451                                        u8 page_number, u16 device_addr,
8452                                        u8 size, u8 i2c_device_addr)
8453 {
8454         MLXSW_REG_ZERO(mcia, payload);
8455         mlxsw_reg_mcia_module_set(payload, module);
8456         mlxsw_reg_mcia_l_set(payload, lock);
8457         mlxsw_reg_mcia_page_number_set(payload, page_number);
8458         mlxsw_reg_mcia_device_address_set(payload, device_addr);
8459         mlxsw_reg_mcia_size_set(payload, size);
8460         mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
8461 }
8462 
8463 /* MPAT - Monitoring Port Analyzer Table
8464  * -------------------------------------
8465  * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
8466  * For an enabled analyzer, all fields except e (enable) cannot be modified.
8467  */
8468 #define MLXSW_REG_MPAT_ID 0x901A
8469 #define MLXSW_REG_MPAT_LEN 0x78
8470 
8471 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
8472 
8473 /* reg_mpat_pa_id
8474  * Port Analyzer ID.
8475  * Access: Index
8476  */
8477 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
8478 
8479 /* reg_mpat_system_port
8480  * A unique port identifier for the final destination of the packet.
8481  * Access: RW
8482  */
8483 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
8484 
8485 /* reg_mpat_e
8486  * Enable. Indicating the Port Analyzer is enabled.
8487  * Access: RW
8488  */
8489 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
8490 
8491 /* reg_mpat_qos
8492  * Quality Of Service Mode.
8493  * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
8494  * PCP, DEI, DSCP or VL) are configured.
8495  * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
8496  * same as in the original packet that has triggered the mirroring. For
8497  * SPAN also the pcp,dei are maintained.
8498  * Access: RW
8499  */
8500 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
8501 
8502 /* reg_mpat_be
8503  * Best effort mode. Indicates mirroring traffic should not cause packet
8504  * drop or back pressure, but will discard the mirrored packets. Mirrored
8505  * packets will be forwarded on a best effort manner.
8506  * 0: Do not discard mirrored packets
8507  * 1: Discard mirrored packets if causing congestion
8508  * Access: RW
8509  */
8510 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
8511 
8512 enum mlxsw_reg_mpat_span_type {
8513         /* Local SPAN Ethernet.
8514          * The original packet is not encapsulated.
8515          */
8516         MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
8517 
8518         /* Remote SPAN Ethernet VLAN.
8519          * The packet is forwarded to the monitoring port on the monitoring
8520          * VLAN.
8521          */
8522         MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
8523 
8524         /* Encapsulated Remote SPAN Ethernet L3 GRE.
8525          * The packet is encapsulated with GRE header.
8526          */
8527         MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
8528 };
8529 
8530 /* reg_mpat_span_type
8531  * SPAN type.
8532  * Access: RW
8533  */
8534 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
8535 
8536 /* Remote SPAN - Ethernet VLAN
8537  * - - - - - - - - - - - - - -
8538  */
8539 
8540 /* reg_mpat_eth_rspan_vid
8541  * Encapsulation header VLAN ID.
8542  * Access: RW
8543  */
8544 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
8545 
8546 /* Encapsulated Remote SPAN - Ethernet L2
8547  * - - - - - - - - - - - - - - - - - - -
8548  */
8549 
8550 enum mlxsw_reg_mpat_eth_rspan_version {
8551         MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
8552 };
8553 
8554 /* reg_mpat_eth_rspan_version
8555  * RSPAN mirror header version.
8556  * Access: RW
8557  */
8558 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
8559 
8560 /* reg_mpat_eth_rspan_mac
8561  * Destination MAC address.
8562  * Access: RW
8563  */
8564 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
8565 
8566 /* reg_mpat_eth_rspan_tp
8567  * Tag Packet. Indicates whether the mirroring header should be VLAN tagged.
8568  * Access: RW
8569  */
8570 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
8571 
8572 /* Encapsulated Remote SPAN - Ethernet L3
8573  * - - - - - - - - - - - - - - - - - - -
8574  */
8575 
8576 enum mlxsw_reg_mpat_eth_rspan_protocol {
8577         MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
8578         MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
8579 };
8580 
8581 /* reg_mpat_eth_rspan_protocol
8582  * SPAN encapsulation protocol.
8583  * Access: RW
8584  */
8585 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
8586 
8587 /* reg_mpat_eth_rspan_ttl
8588  * Encapsulation header Time-to-Live/HopLimit.
8589  * Access: RW
8590  */
8591 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
8592 
8593 /* reg_mpat_eth_rspan_smac
8594  * Source MAC address
8595  * Access: RW
8596  */
8597 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
8598 
8599 /* reg_mpat_eth_rspan_dip*
8600  * Destination IP address. The IP version is configured by protocol.
8601  * Access: RW
8602  */
8603 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
8604 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
8605 
8606 /* reg_mpat_eth_rspan_sip*
8607  * Source IP address. The IP version is configured by protocol.
8608  * Access: RW
8609  */
8610 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
8611 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
8612 
8613 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
8614                                        u16 system_port, bool e,
8615                                        enum mlxsw_reg_mpat_span_type span_type)
8616 {
8617         MLXSW_REG_ZERO(mpat, payload);
8618         mlxsw_reg_mpat_pa_id_set(payload, pa_id);
8619         mlxsw_reg_mpat_system_port_set(payload, system_port);
8620         mlxsw_reg_mpat_e_set(payload, e);
8621         mlxsw_reg_mpat_qos_set(payload, 1);
8622         mlxsw_reg_mpat_be_set(payload, 1);
8623         mlxsw_reg_mpat_span_type_set(payload, span_type);
8624 }
8625 
8626 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
8627 {
8628         mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
8629 }
8630 
8631 static inline void
8632 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
8633                                  enum mlxsw_reg_mpat_eth_rspan_version version,
8634                                  const char *mac,
8635                                  bool tp)
8636 {
8637         mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
8638         mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
8639         mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
8640 }
8641 
8642 static inline void
8643 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
8644                                       const char *smac,
8645                                       u32 sip, u32 dip)
8646 {
8647         mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8648         mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8649         mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8650                                     MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
8651         mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
8652         mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
8653 }
8654 
8655 static inline void
8656 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
8657                                       const char *smac,
8658                                       struct in6_addr sip, struct in6_addr dip)
8659 {
8660         mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8661         mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8662         mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8663                                     MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
8664         mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
8665         mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
8666 }
8667 
8668 /* MPAR - Monitoring Port Analyzer Register
8669  * ----------------------------------------
8670  * MPAR register is used to query and configure the port analyzer port mirroring
8671  * properties.
8672  */
8673 #define MLXSW_REG_MPAR_ID 0x901B
8674 #define MLXSW_REG_MPAR_LEN 0x08
8675 
8676 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
8677 
8678 /* reg_mpar_local_port
8679  * The local port to mirror the packets from.
8680  * Access: Index
8681  */
8682 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
8683 
8684 enum mlxsw_reg_mpar_i_e {
8685         MLXSW_REG_MPAR_TYPE_EGRESS,
8686         MLXSW_REG_MPAR_TYPE_INGRESS,
8687 };
8688 
8689 /* reg_mpar_i_e
8690  * Ingress/Egress
8691  * Access: Index
8692  */
8693 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
8694 
8695 /* reg_mpar_enable
8696  * Enable mirroring
8697  * By default, port mirroring is disabled for all ports.
8698  * Access: RW
8699  */
8700 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
8701 
8702 /* reg_mpar_pa_id
8703  * Port Analyzer ID.
8704  * Access: RW
8705  */
8706 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
8707 
8708 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
8709                                        enum mlxsw_reg_mpar_i_e i_e,
8710                                        bool enable, u8 pa_id)
8711 {
8712         MLXSW_REG_ZERO(mpar, payload);
8713         mlxsw_reg_mpar_local_port_set(payload, local_port);
8714         mlxsw_reg_mpar_enable_set(payload, enable);
8715         mlxsw_reg_mpar_i_e_set(payload, i_e);
8716         mlxsw_reg_mpar_pa_id_set(payload, pa_id);
8717 }
8718 
8719 /* MGIR - Management General Information Register
8720  * ----------------------------------------------
8721  * MGIR register allows software to query the hardware and firmware general
8722  * information.
8723  */
8724 #define MLXSW_REG_MGIR_ID 0x9020
8725 #define MLXSW_REG_MGIR_LEN 0x9C
8726 
8727 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
8728 
8729 /* reg_mgir_hw_info_device_hw_revision
8730  * Access: RO
8731  */
8732 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
8733 
8734 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
8735 
8736 /* reg_mgir_fw_info_psid
8737  * PSID (ASCII string).
8738  * Access: RO
8739  */
8740 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
8741 
8742 /* reg_mgir_fw_info_extended_major
8743  * Access: RO
8744  */
8745 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
8746 
8747 /* reg_mgir_fw_info_extended_minor
8748  * Access: RO
8749  */
8750 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
8751 
8752 /* reg_mgir_fw_info_extended_sub_minor
8753  * Access: RO
8754  */
8755 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
8756 
8757 static inline void mlxsw_reg_mgir_pack(char *payload)
8758 {
8759         MLXSW_REG_ZERO(mgir, payload);
8760 }
8761 
8762 static inline void
8763 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,
8764                       u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)
8765 {
8766         *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
8767         mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
8768         *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
8769         *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
8770         *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
8771 }
8772 
8773 /* MRSR - Management Reset and Shutdown Register
8774  * ---------------------------------------------
8775  * MRSR register is used to reset or shutdown the switch or
8776  * the entire system (when applicable).
8777  */
8778 #define MLXSW_REG_MRSR_ID 0x9023
8779 #define MLXSW_REG_MRSR_LEN 0x08
8780 
8781 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
8782 
8783 /* reg_mrsr_command
8784  * Reset/shutdown command
8785  * 0 - do nothing
8786  * 1 - software reset
8787  * Access: WO
8788  */
8789 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
8790 
8791 static inline void mlxsw_reg_mrsr_pack(char *payload)
8792 {
8793         MLXSW_REG_ZERO(mrsr, payload);
8794         mlxsw_reg_mrsr_command_set(payload, 1);
8795 }
8796 
8797 /* MLCR - Management LED Control Register
8798  * --------------------------------------
8799  * Controls the system LEDs.
8800  */
8801 #define MLXSW_REG_MLCR_ID 0x902B
8802 #define MLXSW_REG_MLCR_LEN 0x0C
8803 
8804 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
8805 
8806 /* reg_mlcr_local_port
8807  * Local port number.
8808  * Access: RW
8809  */
8810 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
8811 
8812 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
8813 
8814 /* reg_mlcr_beacon_duration
8815  * Duration of the beacon to be active, in seconds.
8816  * 0x0 - Will turn off the beacon.
8817  * 0xFFFF - Will turn on the beacon until explicitly turned off.
8818  * Access: RW
8819  */
8820 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
8821 
8822 /* reg_mlcr_beacon_remain
8823  * Remaining duration of the beacon, in seconds.
8824  * 0xFFFF indicates an infinite amount of time.
8825  * Access: RO
8826  */
8827 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
8828 
8829 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
8830                                        bool active)
8831 {
8832         MLXSW_REG_ZERO(mlcr, payload);
8833         mlxsw_reg_mlcr_local_port_set(payload, local_port);
8834         mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
8835                                            MLXSW_REG_MLCR_DURATION_MAX : 0);
8836 }
8837 
8838 /* MTPPS - Management Pulse Per Second Register
8839  * --------------------------------------------
8840  * This register provides the device PPS capabilities, configure the PPS in and
8841  * out modules and holds the PPS in time stamp.
8842  */
8843 #define MLXSW_REG_MTPPS_ID 0x9053
8844 #define MLXSW_REG_MTPPS_LEN 0x3C
8845 
8846 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
8847 
8848 /* reg_mtpps_enable
8849  * Enables the PPS functionality the specific pin.
8850  * A boolean variable.
8851  * Access: RW
8852  */
8853 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
8854 
8855 enum mlxsw_reg_mtpps_pin_mode {
8856         MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
8857 };
8858 
8859 /* reg_mtpps_pin_mode
8860  * Pin mode to be used. The mode must comply with the supported modes of the
8861  * requested pin.
8862  * Access: RW
8863  */
8864 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
8865 
8866 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN      7
8867 
8868 /* reg_mtpps_pin
8869  * Pin to be configured or queried out of the supported pins.
8870  * Access: Index
8871  */
8872 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
8873 
8874 /* reg_mtpps_time_stamp
8875  * When pin_mode = pps_in, the latched device time when it was triggered from
8876  * the external GPIO pin.
8877  * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target
8878  * time to generate next output signal.
8879  * Time is in units of device clock.
8880  * Access: RW
8881  */
8882 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
8883 
8884 static inline void
8885 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
8886 {
8887         MLXSW_REG_ZERO(mtpps, payload);
8888         mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
8889         mlxsw_reg_mtpps_pin_mode_set(payload,
8890                                      MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
8891         mlxsw_reg_mtpps_enable_set(payload, true);
8892         mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
8893 }
8894 
8895 /* MTUTC - Management UTC Register
8896  * -------------------------------
8897  * Configures the HW UTC counter.
8898  */
8899 #define MLXSW_REG_MTUTC_ID 0x9055
8900 #define MLXSW_REG_MTUTC_LEN 0x1C
8901 
8902 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
8903 
8904 enum mlxsw_reg_mtutc_operation {
8905         MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
8906         MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
8907 };
8908 
8909 /* reg_mtutc_operation
8910  * Operation.
8911  * Access: OP
8912  */
8913 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
8914 
8915 /* reg_mtutc_freq_adjustment
8916  * Frequency adjustment: Every PPS the HW frequency will be
8917  * adjusted by this value. Units of HW clock, where HW counts
8918  * 10^9 HW clocks for 1 HW second.
8919  * Access: RW
8920  */
8921 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
8922 
8923 /* reg_mtutc_utc_sec
8924  * UTC seconds.
8925  * Access: WO
8926  */
8927 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
8928 
8929 static inline void
8930 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
8931                      u32 freq_adj, u32 utc_sec)
8932 {
8933         MLXSW_REG_ZERO(mtutc, payload);
8934         mlxsw_reg_mtutc_operation_set(payload, oper);
8935         mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
8936         mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
8937 }
8938 
8939 /* MCQI - Management Component Query Information
8940  * ---------------------------------------------
8941  * This register allows querying information about firmware components.
8942  */
8943 #define MLXSW_REG_MCQI_ID 0x9061
8944 #define MLXSW_REG_MCQI_BASE_LEN 0x18
8945 #define MLXSW_REG_MCQI_CAP_LEN 0x14
8946 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
8947 
8948 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
8949 
8950 /* reg_mcqi_component_index
8951  * Index of the accessed component.
8952  * Access: Index
8953  */
8954 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
8955 
8956 enum mlxfw_reg_mcqi_info_type {
8957         MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
8958 };
8959 
8960 /* reg_mcqi_info_type
8961  * Component properties set.
8962  * Access: RW
8963  */
8964 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
8965 
8966 /* reg_mcqi_offset
8967  * The requested/returned data offset from the section start, given in bytes.
8968  * Must be DWORD aligned.
8969  * Access: RW
8970  */
8971 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
8972 
8973 /* reg_mcqi_data_size
8974  * The requested/returned data size, given in bytes. If data_size is not DWORD
8975  * aligned, the last bytes are zero padded.
8976  * Access: RW
8977  */
8978 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
8979 
8980 /* reg_mcqi_cap_max_component_size
8981  * Maximum size for this component, given in bytes.
8982  * Access: RO
8983  */
8984 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
8985 
8986 /* reg_mcqi_cap_log_mcda_word_size
8987  * Log 2 of the access word size in bytes. Read and write access must be aligned
8988  * to the word size. Write access must be done for an integer number of words.
8989  * Access: RO
8990  */
8991 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
8992 
8993 /* reg_mcqi_cap_mcda_max_write_size
8994  * Maximal write size for MCDA register
8995  * Access: RO
8996  */
8997 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
8998 
8999 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
9000 {
9001         MLXSW_REG_ZERO(mcqi, payload);
9002         mlxsw_reg_mcqi_component_index_set(payload, component_index);
9003         mlxsw_reg_mcqi_info_type_set(payload,
9004                                      MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
9005         mlxsw_reg_mcqi_offset_set(payload, 0);
9006         mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
9007 }
9008 
9009 static inline void mlxsw_reg_mcqi_unpack(char *payload,
9010                                          u32 *p_cap_max_component_size,
9011                                          u8 *p_cap_log_mcda_word_size,
9012                                          u16 *p_cap_mcda_max_write_size)
9013 {
9014         *p_cap_max_component_size =
9015                 mlxsw_reg_mcqi_cap_max_component_size_get(payload);
9016         *p_cap_log_mcda_word_size =
9017                 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
9018         *p_cap_mcda_max_write_size =
9019                 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
9020 }
9021 
9022 /* MCC - Management Component Control
9023  * ----------------------------------
9024  * Controls the firmware component and updates the FSM.
9025  */
9026 #define MLXSW_REG_MCC_ID 0x9062
9027 #define MLXSW_REG_MCC_LEN 0x1C
9028 
9029 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
9030 
9031 enum mlxsw_reg_mcc_instruction {
9032         MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
9033         MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
9034         MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
9035         MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
9036         MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
9037         MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
9038 };
9039 
9040 /* reg_mcc_instruction
9041  * Command to be executed by the FSM.
9042  * Applicable for write operation only.
9043  * Access: RW
9044  */
9045 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
9046 
9047 /* reg_mcc_component_index
9048  * Index of the accessed component. Applicable only for commands that
9049  * refer to components. Otherwise, this field is reserved.
9050  * Access: Index
9051  */
9052 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
9053 
9054 /* reg_mcc_update_handle
9055  * Token representing the current flow executed by the FSM.
9056  * Access: WO
9057  */
9058 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
9059 
9060 /* reg_mcc_error_code
9061  * Indicates the successful completion of the instruction, or the reason it
9062  * failed
9063  * Access: RO
9064  */
9065 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
9066 
9067 /* reg_mcc_control_state
9068  * Current FSM state
9069  * Access: RO
9070  */
9071 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
9072 
9073 /* reg_mcc_component_size
9074  * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
9075  * the size may shorten the update time. Value 0x0 means that size is
9076  * unspecified.
9077  * Access: WO
9078  */
9079 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
9080 
9081 static inline void mlxsw_reg_mcc_pack(char *payload,
9082                                       enum mlxsw_reg_mcc_instruction instr,
9083                                       u16 component_index, u32 update_handle,
9084                                       u32 component_size)
9085 {
9086         MLXSW_REG_ZERO(mcc, payload);
9087         mlxsw_reg_mcc_instruction_set(payload, instr);
9088         mlxsw_reg_mcc_component_index_set(payload, component_index);
9089         mlxsw_reg_mcc_update_handle_set(payload, update_handle);
9090         mlxsw_reg_mcc_component_size_set(payload, component_size);
9091 }
9092 
9093 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
9094                                         u8 *p_error_code, u8 *p_control_state)
9095 {
9096         if (p_update_handle)
9097                 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
9098         if (p_error_code)
9099                 *p_error_code = mlxsw_reg_mcc_error_code_get(payload);
9100         if (p_control_state)
9101                 *p_control_state = mlxsw_reg_mcc_control_state_get(payload);
9102 }
9103 
9104 /* MCDA - Management Component Data Access
9105  * ---------------------------------------
9106  * This register allows reading and writing a firmware component.
9107  */
9108 #define MLXSW_REG_MCDA_ID 0x9063
9109 #define MLXSW_REG_MCDA_BASE_LEN 0x10
9110 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
9111 #define MLXSW_REG_MCDA_LEN \
9112                 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
9113 
9114 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
9115 
9116 /* reg_mcda_update_handle
9117  * Token representing the current flow executed by the FSM.
9118  * Access: RW
9119  */
9120 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
9121 
9122 /* reg_mcda_offset
9123  * Offset of accessed address relative to component start. Accesses must be in
9124  * accordance to log_mcda_word_size in MCQI reg.
9125  * Access: RW
9126  */
9127 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
9128 
9129 /* reg_mcda_size
9130  * Size of the data accessed, given in bytes.
9131  * Access: RW
9132  */
9133 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
9134 
9135 /* reg_mcda_data
9136  * Data block accessed.
9137  * Access: RW
9138  */
9139 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
9140 
9141 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
9142                                        u32 offset, u16 size, u8 *data)
9143 {
9144         int i;
9145 
9146         MLXSW_REG_ZERO(mcda, payload);
9147         mlxsw_reg_mcda_update_handle_set(payload, update_handle);
9148         mlxsw_reg_mcda_offset_set(payload, offset);
9149         mlxsw_reg_mcda_size_set(payload, size);
9150 
9151         for (i = 0; i < size / 4; i++)
9152                 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
9153 }
9154 
9155 /* MPSC - Monitoring Packet Sampling Configuration Register
9156  * --------------------------------------------------------
9157  * MPSC Register is used to configure the Packet Sampling mechanism.
9158  */
9159 #define MLXSW_REG_MPSC_ID 0x9080
9160 #define MLXSW_REG_MPSC_LEN 0x1C
9161 
9162 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
9163 
9164 /* reg_mpsc_local_port
9165  * Local port number
9166  * Not supported for CPU port
9167  * Access: Index
9168  */
9169 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8);
9170 
9171 /* reg_mpsc_e
9172  * Enable sampling on port local_port
9173  * Access: RW
9174  */
9175 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
9176 
9177 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
9178 
9179 /* reg_mpsc_rate
9180  * Sampling rate = 1 out of rate packets (with randomization around
9181  * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
9182  * Access: RW
9183  */
9184 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
9185 
9186 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
9187                                        u32 rate)
9188 {
9189         MLXSW_REG_ZERO(mpsc, payload);
9190         mlxsw_reg_mpsc_local_port_set(payload, local_port);
9191         mlxsw_reg_mpsc_e_set(payload, e);
9192         mlxsw_reg_mpsc_rate_set(payload, rate);
9193 }
9194 
9195 /* MGPC - Monitoring General Purpose Counter Set Register
9196  * The MGPC register retrieves and sets the General Purpose Counter Set.
9197  */
9198 #define MLXSW_REG_MGPC_ID 0x9081
9199 #define MLXSW_REG_MGPC_LEN 0x18
9200 
9201 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
9202 
9203 /* reg_mgpc_counter_set_type
9204  * Counter set type.
9205  * Access: OP
9206  */
9207 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
9208 
9209 /* reg_mgpc_counter_index
9210  * Counter index.
9211  * Access: Index
9212  */
9213 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
9214 
9215 enum mlxsw_reg_mgpc_opcode {
9216         /* Nop */
9217         MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
9218         /* Clear counters */
9219         MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
9220 };
9221 
9222 /* reg_mgpc_opcode
9223  * Opcode.
9224  * Access: OP
9225  */
9226 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
9227 
9228 /* reg_mgpc_byte_counter
9229  * Byte counter value.
9230  * Access: RW
9231  */
9232 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
9233 
9234 /* reg_mgpc_packet_counter
9235  * Packet counter value.
9236  * Access: RW
9237  */
9238 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
9239 
9240 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
9241                                        enum mlxsw_reg_mgpc_opcode opcode,
9242                                        enum mlxsw_reg_flow_counter_set_type set_type)
9243 {
9244         MLXSW_REG_ZERO(mgpc, payload);
9245         mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
9246         mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
9247         mlxsw_reg_mgpc_opcode_set(payload, opcode);
9248 }
9249 
9250 /* MPRS - Monitoring Parsing State Register
9251  * ----------------------------------------
9252  * The MPRS register is used for setting up the parsing for hash,
9253  * policy-engine and routing.
9254  */
9255 #define MLXSW_REG_MPRS_ID 0x9083
9256 #define MLXSW_REG_MPRS_LEN 0x14
9257 
9258 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
9259 
9260 /* reg_mprs_parsing_depth
9261  * Minimum parsing depth.
9262  * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
9263  * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
9264  * Access: RW
9265  */
9266 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
9267 
9268 /* reg_mprs_parsing_en
9269  * Parsing enable.
9270  * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
9271  * NVGRE. Default is enabled. Reserved when SwitchX-2.
9272  * Access: RW
9273  */
9274 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
9275 
9276 /* reg_mprs_vxlan_udp_dport
9277  * VxLAN UDP destination port.
9278  * Used for identifying VxLAN packets and for dport field in
9279  * encapsulation. Default is 4789.
9280  * Access: RW
9281  */
9282 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
9283 
9284 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
9285                                        u16 vxlan_udp_dport)
9286 {
9287         MLXSW_REG_ZERO(mprs, payload);
9288         mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
9289         mlxsw_reg_mprs_parsing_en_set(payload, true);
9290         mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
9291 }
9292 
9293 /* MOGCR - Monitoring Global Configuration Register
9294  * ------------------------------------------------
9295  */
9296 #define MLXSW_REG_MOGCR_ID 0x9086
9297 #define MLXSW_REG_MOGCR_LEN 0x20
9298 
9299 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
9300 
9301 /* reg_mogcr_ptp_iftc
9302  * PTP Ingress FIFO Trap Clear
9303  * The PTP_ING_FIFO trap provides MTPPTR with clr according
9304  * to this value. Default 0.
9305  * Reserved when IB switches and when SwitchX/-2, Spectrum-2
9306  * Access: RW
9307  */
9308 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
9309 
9310 /* reg_mogcr_ptp_eftc
9311  * PTP Egress FIFO Trap Clear
9312  * The PTP_EGR_FIFO trap provides MTPPTR with clr according
9313  * to this value. Default 0.
9314  * Reserved when IB switches and when SwitchX/-2, Spectrum-2
9315  * Access: RW
9316  */
9317 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
9318 
9319 /* MTPPPC - Time Precision Packet Port Configuration
9320  * -------------------------------------------------
9321  * This register serves for configuration of which PTP messages should be
9322  * timestamped. This is a global configuration, despite the register name.
9323  *
9324  * Reserved when Spectrum-2.
9325  */
9326 #define MLXSW_REG_MTPPPC_ID 0x9090
9327 #define MLXSW_REG_MTPPPC_LEN 0x28
9328 
9329 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
9330 
9331 /* reg_mtpppc_ing_timestamp_message_type
9332  * Bitwise vector of PTP message types to timestamp at ingress.
9333  * MessageType field as defined by IEEE 1588
9334  * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
9335  * Default all 0
9336  * Access: RW
9337  */
9338 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
9339 
9340 /* reg_mtpppc_egr_timestamp_message_type
9341  * Bitwise vector of PTP message types to timestamp at egress.
9342  * MessageType field as defined by IEEE 1588
9343  * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
9344  * Default all 0
9345  * Access: RW
9346  */
9347 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
9348 
9349 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
9350 {
9351         MLXSW_REG_ZERO(mtpppc, payload);
9352         mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
9353         mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
9354 }
9355 
9356 /* MTPPTR - Time Precision Packet Timestamping Reading
9357  * ---------------------------------------------------
9358  * The MTPPTR is used for reading the per port PTP timestamp FIFO.
9359  * There is a trap for packets which are latched to the timestamp FIFO, thus the
9360  * SW knows which FIFO to read. Note that packets enter the FIFO before been
9361  * trapped. The sequence number is used to synchronize the timestamp FIFO
9362  * entries and the trapped packets.
9363  * Reserved when Spectrum-2.
9364  */
9365 
9366 #define MLXSW_REG_MTPPTR_ID 0x9091
9367 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */
9368 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */
9369 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
9370 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN +               \
9371                     MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
9372 
9373 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
9374 
9375 /* reg_mtpptr_local_port
9376  * Not supported for CPU port.
9377  * Access: Index
9378  */
9379 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8);
9380 
9381 enum mlxsw_reg_mtpptr_dir {
9382         MLXSW_REG_MTPPTR_DIR_INGRESS,
9383         MLXSW_REG_MTPPTR_DIR_EGRESS,
9384 };
9385 
9386 /* reg_mtpptr_dir
9387  * Direction.
9388  * Access: Index
9389  */
9390 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
9391 
9392 /* reg_mtpptr_clr
9393  * Clear the records.
9394  * Access: OP
9395  */
9396 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
9397 
9398 /* reg_mtpptr_num_rec
9399  * Number of valid records in the response
9400  * Range 0.. cap_ptp_timestamp_fifo
9401  * Access: RO
9402  */
9403 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
9404 
9405 /* reg_mtpptr_rec_message_type
9406  * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
9407  * (e.g. Bit0: Sync, Bit1: Delay_Req)
9408  * Access: RO
9409  */
9410 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
9411                      MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
9412                      MLXSW_REG_MTPPTR_REC_LEN, 0, false);
9413 
9414 /* reg_mtpptr_rec_domain_number
9415  * DomainNumber field as defined by IEEE 1588
9416  * Access: RO
9417  */
9418 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
9419                      MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
9420                      MLXSW_REG_MTPPTR_REC_LEN, 0, false);
9421 
9422 /* reg_mtpptr_rec_sequence_id
9423  * SequenceId field as defined by IEEE 1588
9424  * Access: RO
9425  */
9426 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
9427                      MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
9428                      MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
9429 
9430 /* reg_mtpptr_rec_timestamp_high
9431  * Timestamp of when the PTP packet has passed through the port Units of PLL
9432  * clock time.
9433  * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec.
9434  * Access: RO
9435  */
9436 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
9437                      MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
9438                      MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
9439 
9440 /* reg_mtpptr_rec_timestamp_low
9441  * See rec_timestamp_high.
9442  * Access: RO
9443  */
9444 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
9445                      MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
9446                      MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
9447 
9448 static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
9449                                            unsigned int rec,
9450                                            u8 *p_message_type,
9451                                            u8 *p_domain_number,
9452                                            u16 *p_sequence_id,
9453                                            u64 *p_timestamp)
9454 {
9455         u32 timestamp_high, timestamp_low;
9456 
9457         *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
9458         *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
9459         *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
9460         timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
9461         timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
9462         *p_timestamp = (u64)timestamp_high << 32 | timestamp_low;
9463 }
9464 
9465 /* MTPTPT - Monitoring Precision Time Protocol Trap Register
9466  * ---------------------------------------------------------
9467  * This register is used for configuring under which trap to deliver PTP
9468  * packets depending on type of the packet.
9469  */
9470 #define MLXSW_REG_MTPTPT_ID 0x9092
9471 #define MLXSW_REG_MTPTPT_LEN 0x08
9472 
9473 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
9474 
9475 enum mlxsw_reg_mtptpt_trap_id {
9476         MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
9477         MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
9478 };
9479 
9480 /* reg_mtptpt_trap_id
9481  * Trap id.
9482  * Access: Index
9483  */
9484 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
9485 
9486 /* reg_mtptpt_message_type
9487  * Bitwise vector of PTP message types to trap. This is a necessary but
9488  * non-sufficient condition since need to enable also per port. See MTPPPC.
9489  * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g.
9490  * Bit0: Sync, Bit1: Delay_Req)
9491  */
9492 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
9493 
9494 static inline void mlxsw_reg_mtptptp_pack(char *payload,
9495                                           enum mlxsw_reg_mtptpt_trap_id trap_id,
9496                                           u16 message_type)
9497 {
9498         MLXSW_REG_ZERO(mtptpt, payload);
9499         mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
9500         mlxsw_reg_mtptpt_message_type_set(payload, message_type);
9501 }
9502 
9503 /* MGPIR - Management General Peripheral Information Register
9504  * ----------------------------------------------------------
9505  * MGPIR register allows software to query the hardware and
9506  * firmware general information of peripheral entities.
9507  */
9508 #define MLXSW_REG_MGPIR_ID 0x9100
9509 #define MLXSW_REG_MGPIR_LEN 0xA0
9510 
9511 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);
9512 
9513 enum mlxsw_reg_mgpir_device_type {
9514         MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,
9515         MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,
9516 };
9517 
9518 /* device_type
9519  * Access: RO
9520  */
9521 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
9522 
9523 /* devices_per_flash
9524  * Number of devices of device_type per flash (can be shared by few devices).
9525  * Access: RO
9526  */
9527 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
9528 
9529 /* num_of_devices
9530  * Number of devices of device_type.
9531  * Access: RO
9532  */
9533 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
9534 
9535 static inline void mlxsw_reg_mgpir_pack(char *payload)
9536 {
9537         MLXSW_REG_ZERO(mgpir, payload);
9538 }
9539 
9540 static inline void
9541 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
9542                        enum mlxsw_reg_mgpir_device_type *device_type,
9543                        u8 *devices_per_flash)
9544 {
9545         if (num_of_devices)
9546                 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);
9547         if (device_type)
9548                 *device_type = mlxsw_reg_mgpir_device_type_get(payload);
9549         if (devices_per_flash)
9550                 *devices_per_flash =
9551                                 mlxsw_reg_mgpir_devices_per_flash_get(payload);
9552 }
9553 
9554 /* TNGCR - Tunneling NVE General Configuration Register
9555  * ----------------------------------------------------
9556  * The TNGCR register is used for setting up the NVE Tunneling configuration.
9557  */
9558 #define MLXSW_REG_TNGCR_ID 0xA001
9559 #define MLXSW_REG_TNGCR_LEN 0x44
9560 
9561 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
9562 
9563 enum mlxsw_reg_tngcr_type {
9564         MLXSW_REG_TNGCR_TYPE_VXLAN,
9565         MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
9566         MLXSW_REG_TNGCR_TYPE_GENEVE,
9567         MLXSW_REG_TNGCR_TYPE_NVGRE,
9568 };
9569 
9570 /* reg_tngcr_type
9571  * Tunnel type for encapsulation and decapsulation. The types are mutually
9572  * exclusive.
9573  * Note: For Spectrum the NVE parsing must be enabled in MPRS.
9574  * Access: RW
9575  */
9576 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
9577 
9578 /* reg_tngcr_nve_valid
9579  * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.
9580  * Access: RW
9581  */
9582 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
9583 
9584 /* reg_tngcr_nve_ttl_uc
9585  * The TTL for NVE tunnel encapsulation underlay unicast packets.
9586  * Access: RW
9587  */
9588 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
9589 
9590 /* reg_tngcr_nve_ttl_mc
9591  * The TTL for NVE tunnel encapsulation underlay multicast packets.
9592  * Access: RW
9593  */
9594 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
9595 
9596 enum {
9597         /* Do not copy flow label. Calculate flow label using nve_flh. */
9598         MLXSW_REG_TNGCR_FL_NO_COPY,
9599         /* Copy flow label from inner packet if packet is IPv6 and
9600          * encapsulation is by IPv6. Otherwise, calculate flow label using
9601          * nve_flh.
9602          */
9603         MLXSW_REG_TNGCR_FL_COPY,
9604 };
9605 
9606 /* reg_tngcr_nve_flc
9607  * For NVE tunnel encapsulation: Flow label copy from inner packet.
9608  * Access: RW
9609  */
9610 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
9611 
9612 enum {
9613         /* Flow label is static. In Spectrum this means '0'. Spectrum-2
9614          * uses {nve_fl_prefix, nve_fl_suffix}.
9615          */
9616         MLXSW_REG_TNGCR_FL_NO_HASH,
9617         /* 8 LSBs of the flow label are calculated from ECMP hash of the
9618          * inner packet. 12 MSBs are configured by nve_fl_prefix.
9619          */
9620         MLXSW_REG_TNGCR_FL_HASH,
9621 };
9622 
9623 /* reg_tngcr_nve_flh
9624  * NVE flow label hash.
9625  * Access: RW
9626  */
9627 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
9628 
9629 /* reg_tngcr_nve_fl_prefix
9630  * NVE flow label prefix. Constant 12 MSBs of the flow label.
9631  * Access: RW
9632  */
9633 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
9634 
9635 /* reg_tngcr_nve_fl_suffix
9636  * NVE flow label suffix. Constant 8 LSBs of the flow label.
9637  * Reserved when nve_flh=1 and for Spectrum.
9638  * Access: RW
9639  */
9640 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
9641 
9642 enum {
9643         /* Source UDP port is fixed (default '0') */
9644         MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
9645         /* Source UDP port is calculated based on hash */
9646         MLXSW_REG_TNGCR_UDP_SPORT_HASH,
9647 };
9648 
9649 /* reg_tngcr_nve_udp_sport_type
9650  * NVE UDP source port type.
9651  * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).
9652  * When the source UDP port is calculated based on hash, then the 8 LSBs
9653  * are calculated from hash the 8 MSBs are configured by
9654  * nve_udp_sport_prefix.
9655  * Access: RW
9656  */
9657 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
9658 
9659 /* reg_tngcr_nve_udp_sport_prefix
9660  * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.
9661  * Reserved when NVE type is NVGRE.
9662  * Access: RW
9663  */
9664 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
9665 
9666 /* reg_tngcr_nve_group_size_mc
9667  * The amount of sequential linked lists of MC entries. The first linked
9668  * list is configured by SFD.underlay_mc_ptr.
9669  * Valid values: 1, 2, 4, 8, 16, 32, 64
9670  * The linked list are configured by TNUMT.
9671  * The hash is set by LAG hash.
9672  * Access: RW
9673  */
9674 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
9675 
9676 /* reg_tngcr_nve_group_size_flood
9677  * The amount of sequential linked lists of flooding entries. The first
9678  * linked list is configured by SFMR.nve_tunnel_flood_ptr
9679  * Valid values: 1, 2, 4, 8, 16, 32, 64
9680  * The linked list are configured by TNUMT.
9681  * The hash is set by LAG hash.
9682  * Access: RW
9683  */
9684 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
9685 
9686 /* reg_tngcr_learn_enable
9687  * During decapsulation, whether to learn from NVE port.
9688  * Reserved when Spectrum-2. See TNPC.
9689  * Access: RW
9690  */
9691 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
9692 
9693 /* reg_tngcr_underlay_virtual_router
9694  * Underlay virtual router.
9695  * Reserved when Spectrum-2.
9696  * Access: RW
9697  */
9698 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
9699 
9700 /* reg_tngcr_underlay_rif
9701  * Underlay ingress router interface. RIF type should be loopback generic.
9702  * Reserved when Spectrum.
9703  * Access: RW
9704  */
9705 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
9706 
9707 /* reg_tngcr_usipv4
9708  * Underlay source IPv4 address of the NVE.
9709  * Access: RW
9710  */
9711 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
9712 
9713 /* reg_tngcr_usipv6
9714  * Underlay source IPv6 address of the NVE. For Spectrum, must not be
9715  * modified under traffic of NVE tunneling encapsulation.
9716  * Access: RW
9717  */
9718 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
9719 
9720 static inline void mlxsw_reg_tngcr_pack(char *payload,
9721                                         enum mlxsw_reg_tngcr_type type,
9722                                         bool valid, u8 ttl)
9723 {
9724         MLXSW_REG_ZERO(tngcr, payload);
9725         mlxsw_reg_tngcr_type_set(payload, type);
9726         mlxsw_reg_tngcr_nve_valid_set(payload, valid);
9727         mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
9728         mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
9729         mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
9730         mlxsw_reg_tngcr_nve_flh_set(payload, 0);
9731         mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
9732                                                MLXSW_REG_TNGCR_UDP_SPORT_HASH);
9733         mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
9734         mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
9735         mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
9736 }
9737 
9738 /* TNUMT - Tunneling NVE Underlay Multicast Table Register
9739  * -------------------------------------------------------
9740  * The TNUMT register is for building the underlay MC table. It is used
9741  * for MC, flooding and BC traffic into the NVE tunnel.
9742  */
9743 #define MLXSW_REG_TNUMT_ID 0xA003
9744 #define MLXSW_REG_TNUMT_LEN 0x20
9745 
9746 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
9747 
9748 enum mlxsw_reg_tnumt_record_type {
9749         MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
9750         MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
9751         MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
9752 };
9753 
9754 /* reg_tnumt_record_type
9755  * Record type.
9756  * Access: RW
9757  */
9758 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
9759 
9760 enum mlxsw_reg_tnumt_tunnel_port {
9761         MLXSW_REG_TNUMT_TUNNEL_PORT_NVE,
9762         MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS,
9763         MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0,
9764         MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1,
9765 };
9766 
9767 /* reg_tnumt_tunnel_port
9768  * Tunnel port.
9769  * Access: RW
9770  */
9771 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
9772 
9773 /* reg_tnumt_underlay_mc_ptr
9774  * Index to the underlay multicast table.
9775  * For Spectrum the index is to the KVD linear.
9776  * Access: Index
9777  */
9778 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
9779 
9780 /* reg_tnumt_vnext
9781  * The next_underlay_mc_ptr is valid.
9782  * Access: RW
9783  */
9784 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
9785 
9786 /* reg_tnumt_next_underlay_mc_ptr
9787  * The next index to the underlay multicast table.
9788  * Access: RW
9789  */
9790 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
9791 
9792 /* reg_tnumt_record_size
9793  * Number of IP addresses in the record.
9794  * Range is 1..cap_max_nve_mc_entries_ipv{4,6}
9795  * Access: RW
9796  */
9797 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
9798 
9799 /* reg_tnumt_udip
9800  * The underlay IPv4 addresses. udip[i] is reserved if i >= size
9801  * Access: RW
9802  */
9803 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
9804 
9805 /* reg_tnumt_udip_ptr
9806  * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if
9807  * i >= size. The IPv6 addresses are configured by RIPS.
9808  * Access: RW
9809  */
9810 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
9811 
9812 static inline void mlxsw_reg_tnumt_pack(char *payload,
9813                                         enum mlxsw_reg_tnumt_record_type type,
9814                                         enum mlxsw_reg_tnumt_tunnel_port tport,
9815                                         u32 underlay_mc_ptr, bool vnext,
9816                                         u32 next_underlay_mc_ptr,
9817                                         u8 record_size)
9818 {
9819         MLXSW_REG_ZERO(tnumt, payload);
9820         mlxsw_reg_tnumt_record_type_set(payload, type);
9821         mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
9822         mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
9823         mlxsw_reg_tnumt_vnext_set(payload, vnext);
9824         mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
9825         mlxsw_reg_tnumt_record_size_set(payload, record_size);
9826 }
9827 
9828 /* TNQCR - Tunneling NVE QoS Configuration Register
9829  * ------------------------------------------------
9830  * The TNQCR register configures how QoS is set in encapsulation into the
9831  * underlay network.
9832  */
9833 #define MLXSW_REG_TNQCR_ID 0xA010
9834 #define MLXSW_REG_TNQCR_LEN 0x0C
9835 
9836 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
9837 
9838 /* reg_tnqcr_enc_set_dscp
9839  * For encapsulation: How to set DSCP field:
9840  * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay
9841  * (outer) IP header. If there is no IP header, use TNQDR.dscp
9842  * 1 - Set the DSCP field as TNQDR.dscp
9843  * Access: RW
9844  */
9845 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
9846 
9847 static inline void mlxsw_reg_tnqcr_pack(char *payload)
9848 {
9849         MLXSW_REG_ZERO(tnqcr, payload);
9850         mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
9851 }
9852 
9853 /* TNQDR - Tunneling NVE QoS Default Register
9854  * ------------------------------------------
9855  * The TNQDR register configures the default QoS settings for NVE
9856  * encapsulation.
9857  */
9858 #define MLXSW_REG_TNQDR_ID 0xA011
9859 #define MLXSW_REG_TNQDR_LEN 0x08
9860 
9861 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
9862 
9863 /* reg_tnqdr_local_port
9864  * Local port number (receive port). CPU port is supported.
9865  * Access: Index
9866  */
9867 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
9868 
9869 /* reg_tnqdr_dscp
9870  * For encapsulation, the default DSCP.
9871  * Access: RW
9872  */
9873 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
9874 
9875 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
9876 {
9877         MLXSW_REG_ZERO(tnqdr, payload);
9878         mlxsw_reg_tnqdr_local_port_set(payload, local_port);
9879         mlxsw_reg_tnqdr_dscp_set(payload, 0);
9880 }
9881 
9882 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
9883  * --------------------------------------------------------
9884  * The TNEEM register maps ECN of the IP header at the ingress to the
9885  * encapsulation to the ECN of the underlay network.
9886  */
9887 #define MLXSW_REG_TNEEM_ID 0xA012
9888 #define MLXSW_REG_TNEEM_LEN 0x0C
9889 
9890 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
9891 
9892 /* reg_tneem_overlay_ecn
9893  * ECN of the IP header in the overlay network.
9894  * Access: Index
9895  */
9896 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
9897 
9898 /* reg_tneem_underlay_ecn
9899  * ECN of the IP header in the underlay network.
9900  * Access: RW
9901  */
9902 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
9903 
9904 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
9905                                         u8 underlay_ecn)
9906 {
9907         MLXSW_REG_ZERO(tneem, payload);
9908         mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
9909         mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
9910 }
9911 
9912 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register
9913  * --------------------------------------------------------
9914  * The TNDEM register configures the actions that are done in the
9915  * decapsulation.
9916  */
9917 #define MLXSW_REG_TNDEM_ID 0xA013
9918 #define MLXSW_REG_TNDEM_LEN 0x0C
9919 
9920 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
9921 
9922 /* reg_tndem_underlay_ecn
9923  * ECN field of the IP header in the underlay network.
9924  * Access: Index
9925  */
9926 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
9927 
9928 /* reg_tndem_overlay_ecn
9929  * ECN field of the IP header in the overlay network.
9930  * Access: Index
9931  */
9932 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
9933 
9934 /* reg_tndem_eip_ecn
9935  * Egress IP ECN. ECN field of the IP header of the packet which goes out
9936  * from the decapsulation.
9937  * Access: RW
9938  */
9939 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
9940 
9941 /* reg_tndem_trap_en
9942  * Trap enable:
9943  * 0 - No trap due to decap ECN
9944  * 1 - Trap enable with trap_id
9945  * Access: RW
9946  */
9947 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
9948 
9949 /* reg_tndem_trap_id
9950  * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
9951  * Reserved when trap_en is '0'.
9952  * Access: RW
9953  */
9954 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
9955 
9956 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
9957                                         u8 overlay_ecn, u8 ecn, bool trap_en,
9958                                         u16 trap_id)
9959 {
9960         MLXSW_REG_ZERO(tndem, payload);
9961         mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
9962         mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
9963         mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
9964         mlxsw_reg_tndem_trap_en_set(payload, trap_en);
9965         mlxsw_reg_tndem_trap_id_set(payload, trap_id);
9966 }
9967 
9968 /* TNPC - Tunnel Port Configuration Register
9969  * -----------------------------------------
9970  * The TNPC register is used for tunnel port configuration.
9971  * Reserved when Spectrum.
9972  */
9973 #define MLXSW_REG_TNPC_ID 0xA020
9974 #define MLXSW_REG_TNPC_LEN 0x18
9975 
9976 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
9977 
9978 enum mlxsw_reg_tnpc_tunnel_port {
9979         MLXSW_REG_TNPC_TUNNEL_PORT_NVE,
9980         MLXSW_REG_TNPC_TUNNEL_PORT_VPLS,
9981         MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0,
9982         MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1,
9983 };
9984 
9985 /* reg_tnpc_tunnel_port
9986  * Tunnel port.
9987  * Access: Index
9988  */
9989 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
9990 
9991 /* reg_tnpc_learn_enable_v6
9992  * During IPv6 underlay decapsulation, whether to learn from tunnel port.
9993  * Access: RW
9994  */
9995 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
9996 
9997 /* reg_tnpc_learn_enable_v4
9998  * During IPv4 underlay decapsulation, whether to learn from tunnel port.
9999  * Access: RW
10000  */
10001 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
10002 
10003 static inline void mlxsw_reg_tnpc_pack(char *payload,
10004                                        enum mlxsw_reg_tnpc_tunnel_port tport,
10005                                        bool learn_enable)
10006 {
10007         MLXSW_REG_ZERO(tnpc, payload);
10008         mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
10009         mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
10010         mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
10011 }
10012 
10013 /* TIGCR - Tunneling IPinIP General Configuration Register
10014  * -------------------------------------------------------
10015  * The TIGCR register is used for setting up the IPinIP Tunnel configuration.
10016  */
10017 #define MLXSW_REG_TIGCR_ID 0xA801
10018 #define MLXSW_REG_TIGCR_LEN 0x10
10019 
10020 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
10021 
10022 /* reg_tigcr_ipip_ttlc
10023  * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet
10024  * header.
10025  * Access: RW
10026  */
10027 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
10028 
10029 /* reg_tigcr_ipip_ttl_uc
10030  * The TTL for IPinIP Tunnel encapsulation of unicast packets if
10031  * reg_tigcr_ipip_ttlc is unset.
10032  * Access: RW
10033  */
10034 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
10035 
10036 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
10037 {
10038         MLXSW_REG_ZERO(tigcr, payload);
10039         mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
10040         mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
10041 }
10042 
10043 /* SBPR - Shared Buffer Pools Register
10044  * -----------------------------------
10045  * The SBPR configures and retrieves the shared buffer pools and configuration.
10046  */
10047 #define MLXSW_REG_SBPR_ID 0xB001
10048 #define MLXSW_REG_SBPR_LEN 0x14
10049 
10050 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
10051 
10052 /* shared direstion enum for SBPR, SBCM, SBPM */
10053 enum mlxsw_reg_sbxx_dir {
10054         MLXSW_REG_SBXX_DIR_INGRESS,
10055         MLXSW_REG_SBXX_DIR_EGRESS,
10056 };
10057 
10058 /* reg_sbpr_dir
10059  * Direction.
10060  * Access: Index
10061  */
10062 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
10063 
10064 /* reg_sbpr_pool
10065  * Pool index.
10066  * Access: Index
10067  */
10068 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
10069 
10070 /* reg_sbpr_infi_size
10071  * Size is infinite.
10072  * Access: RW
10073  */
10074 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
10075 
10076 /* reg_sbpr_size
10077  * Pool size in buffer cells.
10078  * Reserved when infi_size = 1.
10079  * Access: RW
10080  */
10081 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
10082 
10083 enum mlxsw_reg_sbpr_mode {
10084         MLXSW_REG_SBPR_MODE_STATIC,
10085         MLXSW_REG_SBPR_MODE_DYNAMIC,
10086 };
10087 
10088 /* reg_sbpr_mode
10089  * Pool quota calculation mode.
10090  * Access: RW
10091  */
10092 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
10093 
10094 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
10095                                        enum mlxsw_reg_sbxx_dir dir,
10096                                        enum mlxsw_reg_sbpr_mode mode, u32 size,
10097                                        bool infi_size)
10098 {
10099         MLXSW_REG_ZERO(sbpr, payload);
10100         mlxsw_reg_sbpr_pool_set(payload, pool);
10101         mlxsw_reg_sbpr_dir_set(payload, dir);
10102         mlxsw_reg_sbpr_mode_set(payload, mode);
10103         mlxsw_reg_sbpr_size_set(payload, size);
10104         mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
10105 }
10106 
10107 /* SBCM - Shared Buffer Class Management Register
10108  * ----------------------------------------------
10109  * The SBCM register configures and retrieves the shared buffer allocation
10110  * and configuration according to Port-PG, including the binding to pool
10111  * and definition of the associated quota.
10112  */
10113 #define MLXSW_REG_SBCM_ID 0xB002
10114 #define MLXSW_REG_SBCM_LEN 0x28
10115 
10116 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
10117 
10118 /* reg_sbcm_local_port
10119  * Local port number.
10120  * For Ingress: excludes CPU port and Router port
10121  * For Egress: excludes IP Router
10122  * Access: Index
10123  */
10124 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
10125 
10126 /* reg_sbcm_pg_buff
10127  * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
10128  * For PG buffer: range is 0..cap_max_pg_buffers - 1
10129  * For traffic class: range is 0..cap_max_tclass - 1
10130  * Note that when traffic class is in MC aware mode then the traffic
10131  * classes which are MC aware cannot be configured.
10132  * Access: Index
10133  */
10134 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
10135 
10136 /* reg_sbcm_dir
10137  * Direction.
10138  * Access: Index
10139  */
10140 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
10141 
10142 /* reg_sbcm_min_buff
10143  * Minimum buffer size for the limiter, in cells.
10144  * Access: RW
10145  */
10146 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
10147 
10148 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
10149 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
10150 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
10151 
10152 /* reg_sbcm_infi_max
10153  * Max buffer is infinite.
10154  * Access: RW
10155  */
10156 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
10157 
10158 /* reg_sbcm_max_buff
10159  * When the pool associated to the port-pg/tclass is configured to
10160  * static, Maximum buffer size for the limiter configured in cells.
10161  * When the pool associated to the port-pg/tclass is configured to
10162  * dynamic, the max_buff holds the "alpha" parameter, supporting
10163  * the following values:
10164  * 0: 0
10165  * i: (1/128)*2^(i-1), for i=1..14
10166  * 0xFF: Infinity
10167  * Reserved when infi_max = 1.
10168  * Access: RW
10169  */
10170 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
10171 
10172 /* reg_sbcm_pool
10173  * Association of the port-priority to a pool.
10174  * Access: RW
10175  */
10176 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
10177 
10178 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
10179                                        enum mlxsw_reg_sbxx_dir dir,
10180                                        u32 min_buff, u32 max_buff,
10181                                        bool infi_max, u8 pool)
10182 {
10183         MLXSW_REG_ZERO(sbcm, payload);
10184         mlxsw_reg_sbcm_local_port_set(payload, local_port);
10185         mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
10186         mlxsw_reg_sbcm_dir_set(payload, dir);
10187         mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
10188         mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
10189         mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
10190         mlxsw_reg_sbcm_pool_set(payload, pool);
10191 }
10192 
10193 /* SBPM - Shared Buffer Port Management Register
10194  * ---------------------------------------------
10195  * The SBPM register configures and retrieves the shared buffer allocation
10196  * and configuration according to Port-Pool, including the definition
10197  * of the associated quota.
10198  */
10199 #define MLXSW_REG_SBPM_ID 0xB003
10200 #define MLXSW_REG_SBPM_LEN 0x28
10201 
10202 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
10203 
10204 /* reg_sbpm_local_port
10205  * Local port number.
10206  * For Ingress: excludes CPU port and Router port
10207  * For Egress: excludes IP Router
10208  * Access: Index
10209  */
10210 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
10211 
10212 /* reg_sbpm_pool
10213  * The pool associated to quota counting on the local_port.
10214  * Access: Index
10215  */
10216 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
10217 
10218 /* reg_sbpm_dir
10219  * Direction.
10220  * Access: Index
10221  */
10222 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
10223 
10224 /* reg_sbpm_buff_occupancy
10225  * Current buffer occupancy in cells.
10226  * Access: RO
10227  */
10228 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
10229 
10230 /* reg_sbpm_clr
10231  * Clear Max Buffer Occupancy
10232  * When this bit is set, max_buff_occupancy field is cleared (and a
10233  * new max value is tracked from the time the clear was performed).
10234  * Access: OP
10235  */
10236 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
10237 
10238 /* reg_sbpm_max_buff_occupancy
10239  * Maximum value of buffer occupancy in cells monitored. Cleared by
10240  * writing to the clr field.
10241  * Access: RO
10242  */
10243 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
10244 
10245 /* reg_sbpm_min_buff
10246  * Minimum buffer size for the limiter, in cells.
10247  * Access: RW
10248  */
10249 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
10250 
10251 /* reg_sbpm_max_buff
10252  * When the pool associated to the port-pg/tclass is configured to
10253  * static, Maximum buffer size for the limiter configured in cells.
10254  * When the pool associated to the port-pg/tclass is configured to
10255  * dynamic, the max_buff holds the "alpha" parameter, supporting
10256  * the following values:
10257  * 0: 0
10258  * i: (1/128)*2^(i-1), for i=1..14
10259  * 0xFF: Infinity
10260  * Access: RW
10261  */
10262 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
10263 
10264 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
10265                                        enum mlxsw_reg_sbxx_dir dir, bool clr,
10266                                        u32 min_buff, u32 max_buff)
10267 {
10268         MLXSW_REG_ZERO(sbpm, payload);
10269         mlxsw_reg_sbpm_local_port_set(payload, local_port);
10270         mlxsw_reg_sbpm_pool_set(payload, pool);
10271         mlxsw_reg_sbpm_dir_set(payload, dir);
10272         mlxsw_reg_sbpm_clr_set(payload, clr);
10273         mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
10274         mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
10275 }
10276 
10277 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
10278                                          u32 *p_max_buff_occupancy)
10279 {
10280         *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
10281         *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
10282 }
10283 
10284 /* SBMM - Shared Buffer Multicast Management Register
10285  * --------------------------------------------------
10286  * The SBMM register configures and retrieves the shared buffer allocation
10287  * and configuration for MC packets according to Switch-Priority, including
10288  * the binding to pool and definition of the associated quota.
10289  */
10290 #define MLXSW_REG_SBMM_ID 0xB004
10291 #define MLXSW_REG_SBMM_LEN 0x28
10292 
10293 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
10294 
10295 /* reg_sbmm_prio
10296  * Switch Priority.
10297  * Access: Index
10298  */
10299 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
10300 
10301 /* reg_sbmm_min_buff
10302  * Minimum buffer size for the limiter, in cells.
10303  * Access: RW
10304  */
10305 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
10306 
10307 /* reg_sbmm_max_buff
10308  * When the pool associated to the port-pg/tclass is configured to
10309  * static, Maximum buffer size for the limiter configured in cells.
10310  * When the pool associated to the port-pg/tclass is configured to
10311  * dynamic, the max_buff holds the "alpha" parameter, supporting
10312  * the following values:
10313  * 0: 0
10314  * i: (1/128)*2^(i-1), for i=1..14
10315  * 0xFF: Infinity
10316  * Access: RW
10317  */
10318 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
10319 
10320 /* reg_sbmm_pool
10321  * Association of the port-priority to a pool.
10322  * Access: RW
10323  */
10324 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
10325 
10326 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
10327                                        u32 max_buff, u8 pool)
10328 {
10329         MLXSW_REG_ZERO(sbmm, payload);
10330         mlxsw_reg_sbmm_prio_set(payload, prio);
10331         mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
10332         mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
10333         mlxsw_reg_sbmm_pool_set(payload, pool);
10334 }
10335 
10336 /* SBSR - Shared Buffer Status Register
10337  * ------------------------------------
10338  * The SBSR register retrieves the shared buffer occupancy according to
10339  * Port-Pool. Note that this register enables reading a large amount of data.
10340  * It is the user's responsibility to limit the amount of data to ensure the
10341  * response can match the maximum transfer unit. In case the response exceeds
10342  * the maximum transport unit, it will be truncated with no special notice.
10343  */
10344 #define MLXSW_REG_SBSR_ID 0xB005
10345 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
10346 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
10347 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
10348 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN +   \
10349                             MLXSW_REG_SBSR_REC_LEN *    \
10350                             MLXSW_REG_SBSR_REC_MAX_COUNT)
10351 
10352 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
10353 
10354 /* reg_sbsr_clr
10355  * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
10356  * field is cleared (and a new max value is tracked from the time the clear
10357  * was performed).
10358  * Access: OP
10359  */
10360 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
10361 
10362 /* reg_sbsr_ingress_port_mask
10363  * Bit vector for all ingress network ports.
10364  * Indicates which of the ports (for which the relevant bit is set)
10365  * are affected by the set operation. Configuration of any other port
10366  * does not change.
10367  * Access: Index
10368  */
10369 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
10370 
10371 /* reg_sbsr_pg_buff_mask
10372  * Bit vector for all switch priority groups.
10373  * Indicates which of the priorities (for which the relevant bit is set)
10374  * are affected by the set operation. Configuration of any other priority
10375  * does not change.
10376  * Range is 0..cap_max_pg_buffers - 1
10377  * Access: Index
10378  */
10379 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
10380 
10381 /* reg_sbsr_egress_port_mask
10382  * Bit vector for all egress network ports.
10383  * Indicates which of the ports (for which the relevant bit is set)
10384  * are affected by the set operation. Configuration of any other port
10385  * does not change.
10386  * Access: Index
10387  */
10388 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
10389 
10390 /* reg_sbsr_tclass_mask
10391  * Bit vector for all traffic classes.
10392  * Indicates which of the traffic classes (for which the relevant bit is
10393  * set) are affected by the set operation. Configuration of any other
10394  * traffic class does not change.
10395  * Range is 0..cap_max_tclass - 1
10396  * Access: Index
10397  */
10398 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
10399 
10400 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
10401 {
10402         MLXSW_REG_ZERO(sbsr, payload);
10403         mlxsw_reg_sbsr_clr_set(payload, clr);
10404 }
10405 
10406 /* reg_sbsr_rec_buff_occupancy
10407  * Current buffer occupancy in cells.
10408  * Access: RO
10409  */
10410 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
10411                      0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
10412 
10413 /* reg_sbsr_rec_max_buff_occupancy
10414  * Maximum value of buffer occupancy in cells monitored. Cleared by
10415  * writing to the clr field.
10416  * Access: RO
10417  */
10418 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
10419                      0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
10420 
10421 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
10422                                              u32 *p_buff_occupancy,
10423                                              u32 *p_max_buff_occupancy)
10424 {
10425         *p_buff_occupancy =
10426                 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
10427         *p_max_buff_occupancy =
10428                 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
10429 }
10430 
10431 /* SBIB - Shared Buffer Internal Buffer Register
10432  * ---------------------------------------------
10433  * The SBIB register configures per port buffers for internal use. The internal
10434  * buffers consume memory on the port buffers (note that the port buffers are
10435  * used also by PBMC).
10436  *
10437  * For Spectrum this is used for egress mirroring.
10438  */
10439 #define MLXSW_REG_SBIB_ID 0xB006
10440 #define MLXSW_REG_SBIB_LEN 0x10
10441 
10442 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
10443 
10444 /* reg_sbib_local_port
10445  * Local port number
10446  * Not supported for CPU port and router port
10447  * Access: Index
10448  */
10449 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
10450 
10451 /* reg_sbib_buff_size
10452  * Units represented in cells
10453  * Allowed range is 0 to (cap_max_headroom_size - 1)
10454  * Default is 0
10455  * Access: RW
10456  */
10457 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
10458 
10459 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
10460                                        u32 buff_size)
10461 {
10462         MLXSW_REG_ZERO(sbib, payload);
10463         mlxsw_reg_sbib_local_port_set(payload, local_port);
10464         mlxsw_reg_sbib_buff_size_set(payload, buff_size);
10465 }
10466 
10467 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
10468         MLXSW_REG(sgcr),
10469         MLXSW_REG(spad),
10470         MLXSW_REG(smid),
10471         MLXSW_REG(sspr),
10472         MLXSW_REG(sfdat),
10473         MLXSW_REG(sfd),
10474         MLXSW_REG(sfn),
10475         MLXSW_REG(spms),
10476         MLXSW_REG(spvid),
10477         MLXSW_REG(spvm),
10478         MLXSW_REG(spaft),
10479         MLXSW_REG(sfgc),
10480         MLXSW_REG(sftr),
10481         MLXSW_REG(sfdf),
10482         MLXSW_REG(sldr),
10483         MLXSW_REG(slcr),
10484         MLXSW_REG(slcor),
10485         MLXSW_REG(spmlr),
10486         MLXSW_REG(svfa),
10487         MLXSW_REG(svpe),
10488         MLXSW_REG(sfmr),
10489         MLXSW_REG(spvmlr),
10490         MLXSW_REG(cwtp),
10491         MLXSW_REG(cwtpm),
10492         MLXSW_REG(pgcr),
10493         MLXSW_REG(ppbt),
10494         MLXSW_REG(pacl),
10495         MLXSW_REG(pagt),
10496         MLXSW_REG(ptar),
10497         MLXSW_REG(ppbs),
10498         MLXSW_REG(prcr),
10499         MLXSW_REG(pefa),
10500         MLXSW_REG(pemrbt),
10501         MLXSW_REG(ptce2),
10502         MLXSW_REG(perpt),
10503         MLXSW_REG(peabfe),
10504         MLXSW_REG(perar),
10505         MLXSW_REG(ptce3),
10506         MLXSW_REG(percr),
10507         MLXSW_REG(pererp),
10508         MLXSW_REG(iedr),
10509         MLXSW_REG(qpts),
10510         MLXSW_REG(qpcr),
10511         MLXSW_REG(qtct),
10512         MLXSW_REG(qeec),
10513         MLXSW_REG(qrwe),
10514         MLXSW_REG(qpdsm),
10515         MLXSW_REG(qpdpm),
10516         MLXSW_REG(qtctm),
10517         MLXSW_REG(qpsc),
10518         MLXSW_REG(pmlp),
10519         MLXSW_REG(pmtu),
10520         MLXSW_REG(ptys),
10521         MLXSW_REG(ppad),
10522         MLXSW_REG(paos),
10523         MLXSW_REG(pfcc),
10524         MLXSW_REG(ppcnt),
10525         MLXSW_REG(plib),
10526         MLXSW_REG(pptb),
10527         MLXSW_REG(pbmc),
10528         MLXSW_REG(pspa),
10529         MLXSW_REG(pplr),
10530         MLXSW_REG(htgt),
10531         MLXSW_REG(hpkt),
10532         MLXSW_REG(rgcr),
10533         MLXSW_REG(ritr),
10534         MLXSW_REG(rtar),
10535         MLXSW_REG(ratr),
10536         MLXSW_REG(rtdp),
10537         MLXSW_REG(rdpm),
10538         MLXSW_REG(ricnt),
10539         MLXSW_REG(rrcr),
10540         MLXSW_REG(ralta),
10541         MLXSW_REG(ralst),
10542         MLXSW_REG(raltb),
10543         MLXSW_REG(ralue),
10544         MLXSW_REG(rauht),
10545         MLXSW_REG(raleu),
10546         MLXSW_REG(rauhtd),
10547         MLXSW_REG(rigr2),
10548         MLXSW_REG(recr2),
10549         MLXSW_REG(rmft2),
10550         MLXSW_REG(mfcr),
10551         MLXSW_REG(mfsc),
10552         MLXSW_REG(mfsm),
10553         MLXSW_REG(mfsl),
10554         MLXSW_REG(fore),
10555         MLXSW_REG(mtcap),
10556         MLXSW_REG(mtmp),
10557         MLXSW_REG(mtbr),
10558         MLXSW_REG(mcia),
10559         MLXSW_REG(mpat),
10560         MLXSW_REG(mpar),
10561         MLXSW_REG(mgir),
10562         MLXSW_REG(mrsr),
10563         MLXSW_REG(mlcr),
10564         MLXSW_REG(mtpps),
10565         MLXSW_REG(mtutc),
10566         MLXSW_REG(mpsc),
10567         MLXSW_REG(mcqi),
10568         MLXSW_REG(mcc),
10569         MLXSW_REG(mcda),
10570         MLXSW_REG(mgpc),
10571         MLXSW_REG(mprs),
10572         MLXSW_REG(mogcr),
10573         MLXSW_REG(mtpppc),
10574         MLXSW_REG(mtpptr),
10575         MLXSW_REG(mtptpt),
10576         MLXSW_REG(mgpir),
10577         MLXSW_REG(tngcr),
10578         MLXSW_REG(tnumt),
10579         MLXSW_REG(tnqcr),
10580         MLXSW_REG(tnqdr),
10581         MLXSW_REG(tneem),
10582         MLXSW_REG(tndem),
10583         MLXSW_REG(tnpc),
10584         MLXSW_REG(tigcr),
10585         MLXSW_REG(sbpr),
10586         MLXSW_REG(sbcm),
10587         MLXSW_REG(sbpm),
10588         MLXSW_REG(sbmm),
10589         MLXSW_REG(sbsr),
10590         MLXSW_REG(sbib),
10591 };
10592 
10593 static inline const char *mlxsw_reg_id_str(u16 reg_id)
10594 {
10595         const struct mlxsw_reg_info *reg_info;
10596         int i;
10597 
10598         for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
10599                 reg_info = mlxsw_reg_infos[i];
10600                 if (reg_info->id == reg_id)
10601                         return reg_info->name;
10602         }
10603         return "*UNKNOWN*";
10604 }
10605 
10606 /* PUDE - Port Up / Down Event
10607  * ---------------------------
10608  * Reports the operational state change of a port.
10609  */
10610 #define MLXSW_REG_PUDE_LEN 0x10
10611 
10612 /* reg_pude_swid
10613  * Switch partition ID with which to associate the port.
10614  * Access: Index
10615  */
10616 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
10617 
10618 /* reg_pude_local_port
10619  * Local port number.
10620  * Access: Index
10621  */
10622 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
10623 
10624 /* reg_pude_admin_status
10625  * Port administrative state (the desired state).
10626  * 1 - Up.
10627  * 2 - Down.
10628  * 3 - Up once. This means that in case of link failure, the port won't go
10629  *     into polling mode, but will wait to be re-enabled by software.
10630  * 4 - Disabled by system. Can only be set by hardware.
10631  * Access: RO
10632  */
10633 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
10634 
10635 /* reg_pude_oper_status
10636  * Port operatioanl state.
10637  * 1 - Up.
10638  * 2 - Down.
10639  * 3 - Down by port failure. This means that the device will not let the
10640  *     port up again until explicitly specified by software.
10641  * Access: RO
10642  */
10643 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
10644 
10645 #endif
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root/drivers/net/ethernet/mellanox/mlxsw/reg.h

INCLUDED FROM

DEFINITIONS
