1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3
4 #ifndef _MLXSW_CMD_H
5 #define _MLXSW_CMD_H
6
7 #include "item.h"
8
9 #define MLXSW_CMD_MBOX_SIZE 4096
10
11 static inline char *mlxsw_cmd_mbox_alloc(void)
12 {
13 return kzalloc(MLXSW_CMD_MBOX_SIZE, GFP_KERNEL);
14 }
15
16 static inline void mlxsw_cmd_mbox_free(char *mbox)
17 {
18 kfree(mbox);
19 }
20
21 static inline void mlxsw_cmd_mbox_zero(char *mbox)
22 {
23 memset(mbox, 0, MLXSW_CMD_MBOX_SIZE);
24 }
25
26 struct mlxsw_core;
27
28 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod,
29 u32 in_mod, bool out_mbox_direct, bool reset_ok,
30 char *in_mbox, size_t in_mbox_size,
31 char *out_mbox, size_t out_mbox_size);
32
33 static inline int mlxsw_cmd_exec_in(struct mlxsw_core *mlxsw_core, u16 opcode,
34 u8 opcode_mod, u32 in_mod, char *in_mbox,
35 size_t in_mbox_size)
36 {
37 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false,
38 false, in_mbox, in_mbox_size, NULL, 0);
39 }
40
41 static inline int mlxsw_cmd_exec_out(struct mlxsw_core *mlxsw_core, u16 opcode,
42 u8 opcode_mod, u32 in_mod,
43 bool out_mbox_direct,
44 char *out_mbox, size_t out_mbox_size)
45 {
46 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod,
47 out_mbox_direct, false, NULL, 0,
48 out_mbox, out_mbox_size);
49 }
50
51 static inline int mlxsw_cmd_exec_none(struct mlxsw_core *mlxsw_core, u16 opcode,
52 u8 opcode_mod, u32 in_mod)
53 {
54 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false,
55 false, NULL, 0, NULL, 0);
56 }
57
58 enum mlxsw_cmd_opcode {
59 MLXSW_CMD_OPCODE_QUERY_FW = 0x004,
60 MLXSW_CMD_OPCODE_QUERY_BOARDINFO = 0x006,
61 MLXSW_CMD_OPCODE_QUERY_AQ_CAP = 0x003,
62 MLXSW_CMD_OPCODE_MAP_FA = 0xFFF,
63 MLXSW_CMD_OPCODE_UNMAP_FA = 0xFFE,
64 MLXSW_CMD_OPCODE_CONFIG_PROFILE = 0x100,
65 MLXSW_CMD_OPCODE_ACCESS_REG = 0x040,
66 MLXSW_CMD_OPCODE_SW2HW_DQ = 0x201,
67 MLXSW_CMD_OPCODE_HW2SW_DQ = 0x202,
68 MLXSW_CMD_OPCODE_2ERR_DQ = 0x01E,
69 MLXSW_CMD_OPCODE_QUERY_DQ = 0x022,
70 MLXSW_CMD_OPCODE_SW2HW_CQ = 0x016,
71 MLXSW_CMD_OPCODE_HW2SW_CQ = 0x017,
72 MLXSW_CMD_OPCODE_QUERY_CQ = 0x018,
73 MLXSW_CMD_OPCODE_SW2HW_EQ = 0x013,
74 MLXSW_CMD_OPCODE_HW2SW_EQ = 0x014,
75 MLXSW_CMD_OPCODE_QUERY_EQ = 0x015,
76 MLXSW_CMD_OPCODE_QUERY_RESOURCES = 0x101,
77 };
78
79 static inline const char *mlxsw_cmd_opcode_str(u16 opcode)
80 {
81 switch (opcode) {
82 case MLXSW_CMD_OPCODE_QUERY_FW:
83 return "QUERY_FW";
84 case MLXSW_CMD_OPCODE_QUERY_BOARDINFO:
85 return "QUERY_BOARDINFO";
86 case MLXSW_CMD_OPCODE_QUERY_AQ_CAP:
87 return "QUERY_AQ_CAP";
88 case MLXSW_CMD_OPCODE_MAP_FA:
89 return "MAP_FA";
90 case MLXSW_CMD_OPCODE_UNMAP_FA:
91 return "UNMAP_FA";
92 case MLXSW_CMD_OPCODE_CONFIG_PROFILE:
93 return "CONFIG_PROFILE";
94 case MLXSW_CMD_OPCODE_ACCESS_REG:
95 return "ACCESS_REG";
96 case MLXSW_CMD_OPCODE_SW2HW_DQ:
97 return "SW2HW_DQ";
98 case MLXSW_CMD_OPCODE_HW2SW_DQ:
99 return "HW2SW_DQ";
100 case MLXSW_CMD_OPCODE_2ERR_DQ:
101 return "2ERR_DQ";
102 case MLXSW_CMD_OPCODE_QUERY_DQ:
103 return "QUERY_DQ";
104 case MLXSW_CMD_OPCODE_SW2HW_CQ:
105 return "SW2HW_CQ";
106 case MLXSW_CMD_OPCODE_HW2SW_CQ:
107 return "HW2SW_CQ";
108 case MLXSW_CMD_OPCODE_QUERY_CQ:
109 return "QUERY_CQ";
110 case MLXSW_CMD_OPCODE_SW2HW_EQ:
111 return "SW2HW_EQ";
112 case MLXSW_CMD_OPCODE_HW2SW_EQ:
113 return "HW2SW_EQ";
114 case MLXSW_CMD_OPCODE_QUERY_EQ:
115 return "QUERY_EQ";
116 case MLXSW_CMD_OPCODE_QUERY_RESOURCES:
117 return "QUERY_RESOURCES";
118 default:
119 return "*UNKNOWN*";
120 }
121 }
122
123 enum mlxsw_cmd_status {
124 /* Command execution succeeded. */
125 MLXSW_CMD_STATUS_OK = 0x00,
126 /* Internal error (e.g. bus error) occurred while processing command. */
127 MLXSW_CMD_STATUS_INTERNAL_ERR = 0x01,
128 /* Operation/command not supported or opcode modifier not supported. */
129 MLXSW_CMD_STATUS_BAD_OP = 0x02,
130 /* Parameter not supported, parameter out of range. */
131 MLXSW_CMD_STATUS_BAD_PARAM = 0x03,
132 /* System was not enabled or bad system state. */
133 MLXSW_CMD_STATUS_BAD_SYS_STATE = 0x04,
134 /* Attempt to access reserved or unallocated resource, or resource in
135 * inappropriate ownership.
136 */
137 MLXSW_CMD_STATUS_BAD_RESOURCE = 0x05,
138 /* Requested resource is currently executing a command. */
139 MLXSW_CMD_STATUS_RESOURCE_BUSY = 0x06,
140 /* Required capability exceeds device limits. */
141 MLXSW_CMD_STATUS_EXCEED_LIM = 0x08,
142 /* Resource is not in the appropriate state or ownership. */
143 MLXSW_CMD_STATUS_BAD_RES_STATE = 0x09,
144 /* Index out of range (might be beyond table size or attempt to
145 * access a reserved resource).
146 */
147 MLXSW_CMD_STATUS_BAD_INDEX = 0x0A,
148 /* NVMEM checksum/CRC failed. */
149 MLXSW_CMD_STATUS_BAD_NVMEM = 0x0B,
150 /* Device is currently running reset */
151 MLXSW_CMD_STATUS_RUNNING_RESET = 0x26,
152 /* Bad management packet (silently discarded). */
153 MLXSW_CMD_STATUS_BAD_PKT = 0x30,
154 };
155
156 static inline const char *mlxsw_cmd_status_str(u8 status)
157 {
158 switch (status) {
159 case MLXSW_CMD_STATUS_OK:
160 return "OK";
161 case MLXSW_CMD_STATUS_INTERNAL_ERR:
162 return "INTERNAL_ERR";
163 case MLXSW_CMD_STATUS_BAD_OP:
164 return "BAD_OP";
165 case MLXSW_CMD_STATUS_BAD_PARAM:
166 return "BAD_PARAM";
167 case MLXSW_CMD_STATUS_BAD_SYS_STATE:
168 return "BAD_SYS_STATE";
169 case MLXSW_CMD_STATUS_BAD_RESOURCE:
170 return "BAD_RESOURCE";
171 case MLXSW_CMD_STATUS_RESOURCE_BUSY:
172 return "RESOURCE_BUSY";
173 case MLXSW_CMD_STATUS_EXCEED_LIM:
174 return "EXCEED_LIM";
175 case MLXSW_CMD_STATUS_BAD_RES_STATE:
176 return "BAD_RES_STATE";
177 case MLXSW_CMD_STATUS_BAD_INDEX:
178 return "BAD_INDEX";
179 case MLXSW_CMD_STATUS_BAD_NVMEM:
180 return "BAD_NVMEM";
181 case MLXSW_CMD_STATUS_RUNNING_RESET:
182 return "RUNNING_RESET";
183 case MLXSW_CMD_STATUS_BAD_PKT:
184 return "BAD_PKT";
185 default:
186 return "*UNKNOWN*";
187 }
188 }
189
190 /* QUERY_FW - Query Firmware
191 * -------------------------
192 * OpMod == 0, INMmod == 0
193 * -----------------------
194 * The QUERY_FW command retrieves information related to firmware, command
195 * interface version and the amount of resources that should be allocated to
196 * the firmware.
197 */
198
199 static inline int mlxsw_cmd_query_fw(struct mlxsw_core *mlxsw_core,
200 char *out_mbox)
201 {
202 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_FW,
203 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE);
204 }
205
206 /* cmd_mbox_query_fw_fw_pages
207 * Amount of physical memory to be allocatedfor firmware usage in 4KB pages.
208 */
209 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16);
210
211 /* cmd_mbox_query_fw_fw_rev_major
212 * Firmware Revision - Major
213 */
214 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16);
215
216 /* cmd_mbox_query_fw_fw_rev_subminor
217 * Firmware Sub-minor version (Patch level)
218 */
219 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16);
220
221 /* cmd_mbox_query_fw_fw_rev_minor
222 * Firmware Revision - Minor
223 */
224 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16);
225
226 /* cmd_mbox_query_fw_core_clk
227 * Internal Clock Frequency (in MHz)
228 */
229 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16);
230
231 /* cmd_mbox_query_fw_cmd_interface_rev
232 * Command Interface Interpreter Revision ID. This number is bumped up
233 * every time a non-backward-compatible change is done for the command
234 * interface. The current cmd_interface_rev is 1.
235 */
236 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16);
237
238 /* cmd_mbox_query_fw_dt
239 * If set, Debug Trace is supported
240 */
241 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1);
242
243 /* cmd_mbox_query_fw_api_version
244 * Indicates the version of the API, to enable software querying
245 * for compatibility. The current api_version is 1.
246 */
247 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16);
248
249 /* cmd_mbox_query_fw_fw_hour
250 * Firmware timestamp - hour
251 */
252 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8);
253
254 /* cmd_mbox_query_fw_fw_minutes
255 * Firmware timestamp - minutes
256 */
257 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8);
258
259 /* cmd_mbox_query_fw_fw_seconds
260 * Firmware timestamp - seconds
261 */
262 MLXSW_ITEM32(cmd_mbox, query_fw, fw_seconds, 0x10, 8, 8);
263
264 /* cmd_mbox_query_fw_fw_year
265 * Firmware timestamp - year
266 */
267 MLXSW_ITEM32(cmd_mbox, query_fw, fw_year, 0x14, 16, 16);
268
269 /* cmd_mbox_query_fw_fw_month
270 * Firmware timestamp - month
271 */
272 MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8);
273
274 /* cmd_mbox_query_fw_fw_day
275 * Firmware timestamp - day
276 */
277 MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8);
278
279 /* cmd_mbox_query_fw_clr_int_base_offset
280 * Clear Interrupt register's offset from clr_int_bar register
281 * in PCI address space.
282 */
283 MLXSW_ITEM64(cmd_mbox, query_fw, clr_int_base_offset, 0x20, 0, 64);
284
285 /* cmd_mbox_query_fw_clr_int_bar
286 * PCI base address register (BAR) where clr_int register is located.
287 * 00 - BAR 0-1 (64 bit BAR)
288 */
289 MLXSW_ITEM32(cmd_mbox, query_fw, clr_int_bar, 0x28, 30, 2);
290
291 /* cmd_mbox_query_fw_error_buf_offset
292 * Read Only buffer for internal error reports of offset
293 * from error_buf_bar register in PCI address space).
294 */
295 MLXSW_ITEM64(cmd_mbox, query_fw, error_buf_offset, 0x30, 0, 64);
296
297 /* cmd_mbox_query_fw_error_buf_size
298 * Internal error buffer size in DWORDs
299 */
300 MLXSW_ITEM32(cmd_mbox, query_fw, error_buf_size, 0x38, 0, 32);
301
302 /* cmd_mbox_query_fw_error_int_bar
303 * PCI base address register (BAR) where error buffer
304 * register is located.
305 * 00 - BAR 0-1 (64 bit BAR)
306 */
307 MLXSW_ITEM32(cmd_mbox, query_fw, error_int_bar, 0x3C, 30, 2);
308
309 /* cmd_mbox_query_fw_doorbell_page_offset
310 * Offset of the doorbell page
311 */
312 MLXSW_ITEM64(cmd_mbox, query_fw, doorbell_page_offset, 0x40, 0, 64);
313
314 /* cmd_mbox_query_fw_doorbell_page_bar
315 * PCI base address register (BAR) of the doorbell page
316 * 00 - BAR 0-1 (64 bit BAR)
317 */
318 MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2);
319
320 /* cmd_mbox_query_fw_free_running_clock_offset
321 * The offset of the free running clock page
322 */
323 MLXSW_ITEM64(cmd_mbox, query_fw, free_running_clock_offset, 0x50, 0, 64);
324
325 /* cmd_mbox_query_fw_fr_rn_clk_bar
326 * PCI base address register (BAR) of the free running clock page
327 * 0: BAR 0
328 * 1: 64 bit BAR
329 */
330 MLXSW_ITEM32(cmd_mbox, query_fw, fr_rn_clk_bar, 0x58, 30, 2);
331
332 /* QUERY_BOARDINFO - Query Board Information
333 * -----------------------------------------
334 * OpMod == 0 (N/A), INMmod == 0 (N/A)
335 * -----------------------------------
336 * The QUERY_BOARDINFO command retrieves adapter specific parameters.
337 */
338
339 static inline int mlxsw_cmd_boardinfo(struct mlxsw_core *mlxsw_core,
340 char *out_mbox)
341 {
342 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_BOARDINFO,
343 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE);
344 }
345
346 /* cmd_mbox_boardinfo_intapin
347 * When PCIe interrupt messages are being used, this value is used for clearing
348 * an interrupt. When using MSI-X, this register is not used.
349 */
350 MLXSW_ITEM32(cmd_mbox, boardinfo, intapin, 0x10, 24, 8);
351
352 /* cmd_mbox_boardinfo_vsd_vendor_id
353 * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor
354 * specifying/formatting the VSD. The vsd_vendor_id identifies the management
355 * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID
356 * format and encoding as long as they use their assigned vsd_vendor_id.
357 */
358 MLXSW_ITEM32(cmd_mbox, boardinfo, vsd_vendor_id, 0x1C, 0, 16);
359
360 /* cmd_mbox_boardinfo_vsd
361 * Vendor Specific Data. The VSD string that is burnt to the Flash
362 * with the firmware.
363 */
364 #define MLXSW_CMD_BOARDINFO_VSD_LEN 208
365 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, vsd, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN);
366
367 /* cmd_mbox_boardinfo_psid
368 * The PSID field is a 16-ascii (byte) character string which acts as
369 * the board ID. The PSID format is used in conjunction with
370 * Mellanox vsd_vendor_id (15B3h).
371 */
372 #define MLXSW_CMD_BOARDINFO_PSID_LEN 16
373 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, psid, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN);
374
375 /* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities
376 * -----------------------------------------------------
377 * OpMod == 0 (N/A), INMmod == 0 (N/A)
378 * -----------------------------------
379 * The QUERY_AQ_CAP command returns the device asynchronous queues
380 * capabilities supported.
381 */
382
383 static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core *mlxsw_core,
384 char *out_mbox)
385 {
386 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_AQ_CAP,
387 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE);
388 }
389
390 /* cmd_mbox_query_aq_cap_log_max_sdq_sz
391 * Log (base 2) of max WQEs allowed on SDQ.
392 */
393 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_sdq_sz, 0x00, 24, 8);
394
395 /* cmd_mbox_query_aq_cap_max_num_sdqs
396 * Maximum number of SDQs.
397 */
398 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_sdqs, 0x00, 0, 8);
399
400 /* cmd_mbox_query_aq_cap_log_max_rdq_sz
401 * Log (base 2) of max WQEs allowed on RDQ.
402 */
403 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8);
404
405 /* cmd_mbox_query_aq_cap_max_num_rdqs
406 * Maximum number of RDQs.
407 */
408 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8);
409
410 /* cmd_mbox_query_aq_cap_log_max_cq_sz
411 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv0 and CQEv1.
412 */
413 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8);
414
415 /* cmd_mbox_query_aq_cap_log_max_cqv2_sz
416 * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv2.
417 */
418 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cqv2_sz, 0x08, 16, 8);
419
420 /* cmd_mbox_query_aq_cap_max_num_cqs
421 * Maximum number of CQs.
422 */
423 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_cqs, 0x08, 0, 8);
424
425 /* cmd_mbox_query_aq_cap_log_max_eq_sz
426 * Log (base 2) of max EQEs allowed on EQ.
427 */
428 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_eq_sz, 0x0C, 24, 8);
429
430 /* cmd_mbox_query_aq_cap_max_num_eqs
431 * Maximum number of EQs.
432 */
433 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_eqs, 0x0C, 0, 8);
434
435 /* cmd_mbox_query_aq_cap_max_sg_sq
436 * The maximum S/G list elements in an DSQ. DSQ must not contain
437 * more S/G entries than indicated here.
438 */
439 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_sq, 0x10, 8, 8);
440
441 /* cmd_mbox_query_aq_cap_
442 * The maximum S/G list elements in an DRQ. DRQ must not contain
443 * more S/G entries than indicated here.
444 */
445 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_rq, 0x10, 0, 8);
446
447 /* MAP_FA - Map Firmware Area
448 * --------------------------
449 * OpMod == 0 (N/A), INMmod == Number of VPM entries
450 * -------------------------------------------------
451 * The MAP_FA command passes physical pages to the switch. These pages
452 * are used to store the device firmware. MAP_FA can be executed multiple
453 * times until all the firmware area is mapped (the size that should be
454 * mapped is retrieved through the QUERY_FW command). All required pages
455 * must be mapped to finish the initialization phase. Physical memory
456 * passed in this command must be pinned.
457 */
458
459 #define MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX 32
460
461 static inline int mlxsw_cmd_map_fa(struct mlxsw_core *mlxsw_core,
462 char *in_mbox, u32 vpm_entries_count)
463 {
464 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_MAP_FA,
465 0, vpm_entries_count,
466 in_mbox, MLXSW_CMD_MBOX_SIZE);
467 }
468
469 /* cmd_mbox_map_fa_pa
470 * Physical Address.
471 */
472 MLXSW_ITEM64_INDEXED(cmd_mbox, map_fa, pa, 0x00, 12, 52, 0x08, 0x00, true);
473
474 /* cmd_mbox_map_fa_log2size
475 * Log (base 2) of the size in 4KB pages of the physical and contiguous memory
476 * that starts at PA_L/H.
477 */
478 MLXSW_ITEM32_INDEXED(cmd_mbox, map_fa, log2size, 0x00, 0, 5, 0x08, 0x04, false);
479
480 /* UNMAP_FA - Unmap Firmware Area
481 * ------------------------------
482 * OpMod == 0 (N/A), INMmod == 0 (N/A)
483 * -----------------------------------
484 * The UNMAP_FA command unload the firmware and unmaps all the
485 * firmware area. After this command is completed the device will not access
486 * the pages that were mapped to the firmware area. After executing UNMAP_FA
487 * command, software reset must be done prior to execution of MAP_FW command.
488 */
489
490 static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core *mlxsw_core)
491 {
492 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_UNMAP_FA, 0, 0);
493 }
494
495 /* QUERY_RESOURCES - Query chip resources
496 * --------------------------------------
497 * OpMod == 0 (N/A) , INMmod is index
498 * ----------------------------------
499 * The QUERY_RESOURCES command retrieves information related to chip resources
500 * by resource ID. Every command returns 32 entries. INmod is being use as base.
501 * for example, index 1 will return entries 32-63. When the tables end and there
502 * are no more sources in the table, will return resource id 0xFFF to indicate
503 * it.
504 */
505
506 #define MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID 0xffff
507 #define MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES 100
508 #define MLXSW_CMD_QUERY_RESOURCES_PER_QUERY 32
509
510 static inline int mlxsw_cmd_query_resources(struct mlxsw_core *mlxsw_core,
511 char *out_mbox, int index)
512 {
513 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_RESOURCES,
514 0, index, false, out_mbox,
515 MLXSW_CMD_MBOX_SIZE);
516 }
517
518 /* cmd_mbox_query_resource_id
519 * The resource id. 0xFFFF indicates table's end.
520 */
521 MLXSW_ITEM32_INDEXED(cmd_mbox, query_resource, id, 0x00, 16, 16, 0x8, 0, false);
522
523 /* cmd_mbox_query_resource_data
524 * The resource
525 */
526 MLXSW_ITEM64_INDEXED(cmd_mbox, query_resource, data,
527 0x00, 0, 40, 0x8, 0, false);
528
529 /* CONFIG_PROFILE (Set) - Configure Switch Profile
530 * ------------------------------
531 * OpMod == 1 (Set), INMmod == 0 (N/A)
532 * -----------------------------------
533 * The CONFIG_PROFILE command sets the switch profile. The command can be
534 * executed on the device only once at startup in order to allocate and
535 * configure all switch resources and prepare it for operational mode.
536 * It is not possible to change the device profile after the chip is
537 * in operational mode.
538 * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate
539 * state therefore it is required to perform software reset to the device
540 * following an unsuccessful completion of the command. It is required
541 * to perform software reset to the device to change an existing profile.
542 */
543
544 static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core *mlxsw_core,
545 char *in_mbox)
546 {
547 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_CONFIG_PROFILE,
548 1, 0, in_mbox, MLXSW_CMD_MBOX_SIZE);
549 }
550
551 /* cmd_mbox_config_profile_set_max_vepa_channels
552 * Capability bit. Setting a bit to 1 configures the profile
553 * according to the mailbox contents.
554 */
555 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vepa_channels, 0x0C, 0, 1);
556
557 /* cmd_mbox_config_profile_set_max_lag
558 * Capability bit. Setting a bit to 1 configures the profile
559 * according to the mailbox contents.
560 */
561 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_lag, 0x0C, 1, 1);
562
563 /* cmd_mbox_config_profile_set_max_port_per_lag
564 * Capability bit. Setting a bit to 1 configures the profile
565 * according to the mailbox contents.
566 */
567 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_port_per_lag, 0x0C, 2, 1);
568
569 /* cmd_mbox_config_profile_set_max_mid
570 * Capability bit. Setting a bit to 1 configures the profile
571 * according to the mailbox contents.
572 */
573 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_mid, 0x0C, 3, 1);
574
575 /* cmd_mbox_config_profile_set_max_pgt
576 * Capability bit. Setting a bit to 1 configures the profile
577 * according to the mailbox contents.
578 */
579 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pgt, 0x0C, 4, 1);
580
581 /* cmd_mbox_config_profile_set_max_system_port
582 * Capability bit. Setting a bit to 1 configures the profile
583 * according to the mailbox contents.
584 */
585 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_system_port, 0x0C, 5, 1);
586
587 /* cmd_mbox_config_profile_set_max_vlan_groups
588 * Capability bit. Setting a bit to 1 configures the profile
589 * according to the mailbox contents.
590 */
591 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vlan_groups, 0x0C, 6, 1);
592
593 /* cmd_mbox_config_profile_set_max_regions
594 * Capability bit. Setting a bit to 1 configures the profile
595 * according to the mailbox contents.
596 */
597 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_regions, 0x0C, 7, 1);
598
599 /* cmd_mbox_config_profile_set_flood_mode
600 * Capability bit. Setting a bit to 1 configures the profile
601 * according to the mailbox contents.
602 */
603 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_mode, 0x0C, 8, 1);
604
605 /* cmd_mbox_config_profile_set_max_flood_tables
606 * Capability bit. Setting a bit to 1 configures the profile
607 * according to the mailbox contents.
608 */
609 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_tables, 0x0C, 9, 1);
610
611 /* cmd_mbox_config_profile_set_max_ib_mc
612 * Capability bit. Setting a bit to 1 configures the profile
613 * according to the mailbox contents.
614 */
615 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_ib_mc, 0x0C, 12, 1);
616
617 /* cmd_mbox_config_profile_set_max_pkey
618 * Capability bit. Setting a bit to 1 configures the profile
619 * according to the mailbox contents.
620 */
621 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pkey, 0x0C, 13, 1);
622
623 /* cmd_mbox_config_profile_set_adaptive_routing_group_cap
624 * Capability bit. Setting a bit to 1 configures the profile
625 * according to the mailbox contents.
626 */
627 MLXSW_ITEM32(cmd_mbox, config_profile,
628 set_adaptive_routing_group_cap, 0x0C, 14, 1);
629
630 /* cmd_mbox_config_profile_set_ar_sec
631 * Capability bit. Setting a bit to 1 configures the profile
632 * according to the mailbox contents.
633 */
634 MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1);
635
636 /* cmd_mbox_config_set_kvd_linear_size
637 * Capability bit. Setting a bit to 1 configures the profile
638 * according to the mailbox contents.
639 */
640 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_linear_size, 0x0C, 24, 1);
641
642 /* cmd_mbox_config_set_kvd_hash_single_size
643 * Capability bit. Setting a bit to 1 configures the profile
644 * according to the mailbox contents.
645 */
646 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_single_size, 0x0C, 25, 1);
647
648 /* cmd_mbox_config_set_kvd_hash_double_size
649 * Capability bit. Setting a bit to 1 configures the profile
650 * according to the mailbox contents.
651 */
652 MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1);
653
654 /* cmd_mbox_config_set_cqe_version
655 * Capability bit. Setting a bit to 1 configures the profile
656 * according to the mailbox contents.
657 */
658 MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1);
659
660 /* cmd_mbox_config_profile_max_vepa_channels
661 * Maximum number of VEPA channels per port (0 through 16)
662 * 0 - multi-channel VEPA is disabled
663 */
664 MLXSW_ITEM32(cmd_mbox, config_profile, max_vepa_channels, 0x10, 0, 8);
665
666 /* cmd_mbox_config_profile_max_lag
667 * Maximum number of LAG IDs requested.
668 */
669 MLXSW_ITEM32(cmd_mbox, config_profile, max_lag, 0x14, 0, 16);
670
671 /* cmd_mbox_config_profile_max_port_per_lag
672 * Maximum number of ports per LAG requested.
673 */
674 MLXSW_ITEM32(cmd_mbox, config_profile, max_port_per_lag, 0x18, 0, 16);
675
676 /* cmd_mbox_config_profile_max_mid
677 * Maximum Multicast IDs.
678 * Multicast IDs are allocated from 0 to max_mid-1
679 */
680 MLXSW_ITEM32(cmd_mbox, config_profile, max_mid, 0x1C, 0, 16);
681
682 /* cmd_mbox_config_profile_max_pgt
683 * Maximum records in the Port Group Table per Switch Partition.
684 * Port Group Table indexes are from 0 to max_pgt-1
685 */
686 MLXSW_ITEM32(cmd_mbox, config_profile, max_pgt, 0x20, 0, 16);
687
688 /* cmd_mbox_config_profile_max_system_port
689 * The maximum number of system ports that can be allocated.
690 */
691 MLXSW_ITEM32(cmd_mbox, config_profile, max_system_port, 0x24, 0, 16);
692
693 /* cmd_mbox_config_profile_max_vlan_groups
694 * Maximum number VLAN Groups for VLAN binding.
695 */
696 MLXSW_ITEM32(cmd_mbox, config_profile, max_vlan_groups, 0x28, 0, 12);
697
698 /* cmd_mbox_config_profile_max_regions
699 * Maximum number of TCAM Regions.
700 */
701 MLXSW_ITEM32(cmd_mbox, config_profile, max_regions, 0x2C, 0, 16);
702
703 /* cmd_mbox_config_profile_max_flood_tables
704 * Maximum number of single-entry flooding tables. Different flooding tables
705 * can be associated with different packet types.
706 */
707 MLXSW_ITEM32(cmd_mbox, config_profile, max_flood_tables, 0x30, 16, 4);
708
709 /* cmd_mbox_config_profile_max_vid_flood_tables
710 * Maximum number of per-vid flooding tables. Flooding tables are associated
711 * to the different packet types for the different switch partitions.
712 * Table size is 4K entries covering all VID space.
713 */
714 MLXSW_ITEM32(cmd_mbox, config_profile, max_vid_flood_tables, 0x30, 8, 4);
715
716 /* cmd_mbox_config_profile_flood_mode
717 * Flooding mode to use.
718 * 0-2 - Backward compatible modes for SwitchX devices.
719 * 3 - Mixed mode, where:
720 * max_flood_tables indicates the number of single-entry tables.
721 * max_vid_flood_tables indicates the number of per-VID tables.
722 * max_fid_offset_flood_tables indicates the number of FID-offset tables.
723 * max_fid_flood_tables indicates the number of per-FID tables.
724 */
725 MLXSW_ITEM32(cmd_mbox, config_profile, flood_mode, 0x30, 0, 2);
726
727 /* cmd_mbox_config_profile_max_fid_offset_flood_tables
728 * Maximum number of FID-offset flooding tables.
729 */
730 MLXSW_ITEM32(cmd_mbox, config_profile,
731 max_fid_offset_flood_tables, 0x34, 24, 4);
732
733 /* cmd_mbox_config_profile_fid_offset_flood_table_size
734 * The size (number of entries) of each FID-offset flood table.
735 */
736 MLXSW_ITEM32(cmd_mbox, config_profile,
737 fid_offset_flood_table_size, 0x34, 0, 16);
738
739 /* cmd_mbox_config_profile_max_fid_flood_tables
740 * Maximum number of per-FID flooding tables.
741 *
742 * Note: This flooding tables cover special FIDs only (vFIDs), starting at
743 * FID value 4K and higher.
744 */
745 MLXSW_ITEM32(cmd_mbox, config_profile, max_fid_flood_tables, 0x38, 24, 4);
746
747 /* cmd_mbox_config_profile_fid_flood_table_size
748 * The size (number of entries) of each per-FID table.
749 */
750 MLXSW_ITEM32(cmd_mbox, config_profile, fid_flood_table_size, 0x38, 0, 16);
751
752 /* cmd_mbox_config_profile_max_ib_mc
753 * Maximum number of multicast FDB records for InfiniBand
754 * FDB (in 512 chunks) per InfiniBand switch partition.
755 */
756 MLXSW_ITEM32(cmd_mbox, config_profile, max_ib_mc, 0x40, 0, 15);
757
758 /* cmd_mbox_config_profile_max_pkey
759 * Maximum per port PKEY table size (for PKEY enforcement)
760 */
761 MLXSW_ITEM32(cmd_mbox, config_profile, max_pkey, 0x44, 0, 15);
762
763 /* cmd_mbox_config_profile_ar_sec
764 * Primary/secondary capability
765 * Describes the number of adaptive routing sub-groups
766 * 0 - disable primary/secondary (single group)
767 * 1 - enable primary/secondary (2 sub-groups)
768 * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2
769 * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2
770 */
771 MLXSW_ITEM32(cmd_mbox, config_profile, ar_sec, 0x4C, 24, 2);
772
773 /* cmd_mbox_config_profile_adaptive_routing_group_cap
774 * Adaptive Routing Group Capability. Indicates the number of AR groups
775 * supported. Note that when Primary/secondary is enabled, each
776 * primary/secondary couple consumes 2 adaptive routing entries.
777 */
778 MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16);
779
780 /* cmd_mbox_config_profile_arn
781 * Adaptive Routing Notification Enable
782 * Not supported in SwitchX, SwitchX-2
783 */
784 MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1);
785
786 /* cmd_mbox_config_kvd_linear_size
787 * KVD Linear Size
788 * Valid for Spectrum only
789 * Allowed values are 128*N where N=0 or higher
790 */
791 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_linear_size, 0x54, 0, 24);
792
793 /* cmd_mbox_config_kvd_hash_single_size
794 * KVD Hash single-entries size
795 * Valid for Spectrum only
796 * Allowed values are 128*N where N=0 or higher
797 * Must be greater or equal to cap_min_kvd_hash_single_size
798 * Must be smaller or equal to cap_kvd_size - kvd_linear_size
799 */
800 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_single_size, 0x58, 0, 24);
801
802 /* cmd_mbox_config_kvd_hash_double_size
803 * KVD Hash double-entries size (units of single-size entries)
804 * Valid for Spectrum only
805 * Allowed values are 128*N where N=0 or higher
806 * Must be either 0 or greater or equal to cap_min_kvd_hash_double_size
807 * Must be smaller or equal to cap_kvd_size - kvd_linear_size
808 */
809 MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_double_size, 0x5C, 0, 24);
810
811 /* cmd_mbox_config_profile_swid_config_mask
812 * Modify Switch Partition Configuration mask. When set, the configu-
813 * ration value for the Switch Partition are taken from the mailbox.
814 * When clear, the current configuration values are used.
815 * Bit 0 - set type
816 * Bit 1 - properties
817 * Other - reserved
818 */
819 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_mask,
820 0x60, 24, 8, 0x08, 0x00, false);
821
822 /* cmd_mbox_config_profile_swid_config_type
823 * Switch Partition type.
824 * 0000 - disabled (Switch Partition does not exist)
825 * 0001 - InfiniBand
826 * 0010 - Ethernet
827 * 1000 - router port (SwitchX-2 only)
828 * Other - reserved
829 */
830 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type,
831 0x60, 20, 4, 0x08, 0x00, false);
832
833 /* cmd_mbox_config_profile_swid_config_properties
834 * Switch Partition properties.
835 */
836 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties,
837 0x60, 0, 8, 0x08, 0x00, false);
838
839 /* cmd_mbox_config_profile_cqe_version
840 * CQE version:
841 * 0: CQE version is 0
842 * 1: CQE version is either 1 or 2
843 * CQE ver 1 or 2 is configured by Completion Queue Context field cqe_ver.
844 */
845 MLXSW_ITEM32(cmd_mbox, config_profile, cqe_version, 0xB0, 0, 8);
846
847 /* ACCESS_REG - Access EMAD Supported Register
848 * ----------------------------------
849 * OpMod == 0 (N/A), INMmod == 0 (N/A)
850 * -------------------------------------
851 * The ACCESS_REG command supports accessing device registers. This access
852 * is mainly used for bootstrapping.
853 */
854
855 static inline int mlxsw_cmd_access_reg(struct mlxsw_core *mlxsw_core,
856 bool reset_ok,
857 char *in_mbox, char *out_mbox)
858 {
859 return mlxsw_cmd_exec(mlxsw_core, MLXSW_CMD_OPCODE_ACCESS_REG,
860 0, 0, false, reset_ok,
861 in_mbox, MLXSW_CMD_MBOX_SIZE,
862 out_mbox, MLXSW_CMD_MBOX_SIZE);
863 }
864
865 /* SW2HW_DQ - Software to Hardware DQ
866 * ----------------------------------
867 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
868 * INMmod == DQ number
869 * ----------------------------------------------
870 * The SW2HW_DQ command transitions a descriptor queue from software to
871 * hardware ownership. The command enables posting WQEs and ringing DoorBells
872 * on the descriptor queue.
873 */
874
875 static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core *mlxsw_core,
876 char *in_mbox, u32 dq_number,
877 u8 opcode_mod)
878 {
879 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_DQ,
880 opcode_mod, dq_number,
881 in_mbox, MLXSW_CMD_MBOX_SIZE);
882 }
883
884 enum {
885 MLXSW_CMD_OPCODE_MOD_SDQ = 0,
886 MLXSW_CMD_OPCODE_MOD_RDQ = 1,
887 };
888
889 static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core *mlxsw_core,
890 char *in_mbox, u32 dq_number)
891 {
892 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number,
893 MLXSW_CMD_OPCODE_MOD_SDQ);
894 }
895
896 static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core *mlxsw_core,
897 char *in_mbox, u32 dq_number)
898 {
899 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number,
900 MLXSW_CMD_OPCODE_MOD_RDQ);
901 }
902
903 /* cmd_mbox_sw2hw_dq_cq
904 * Number of the CQ that this Descriptor Queue reports completions to.
905 */
906 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8);
907
908 /* cmd_mbox_sw2hw_dq_sdq_tclass
909 * SDQ: CPU Egress TClass
910 * RDQ: Reserved
911 */
912 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_tclass, 0x00, 16, 6);
913
914 /* cmd_mbox_sw2hw_dq_log2_dq_sz
915 * Log (base 2) of the Descriptor Queue size in 4KB pages.
916 */
917 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, log2_dq_sz, 0x00, 0, 6);
918
919 /* cmd_mbox_sw2hw_dq_pa
920 * Physical Address.
921 */
922 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_dq, pa, 0x10, 12, 52, 0x08, 0x00, true);
923
924 /* HW2SW_DQ - Hardware to Software DQ
925 * ----------------------------------
926 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
927 * INMmod == DQ number
928 * ----------------------------------------------
929 * The HW2SW_DQ command transitions a descriptor queue from hardware to
930 * software ownership. Incoming packets on the DQ are silently discarded,
931 * SW should not post descriptors on nonoperational DQs.
932 */
933
934 static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core *mlxsw_core,
935 u32 dq_number, u8 opcode_mod)
936 {
937 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_DQ,
938 opcode_mod, dq_number);
939 }
940
941 static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core *mlxsw_core,
942 u32 dq_number)
943 {
944 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number,
945 MLXSW_CMD_OPCODE_MOD_SDQ);
946 }
947
948 static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core *mlxsw_core,
949 u32 dq_number)
950 {
951 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number,
952 MLXSW_CMD_OPCODE_MOD_RDQ);
953 }
954
955 /* 2ERR_DQ - To Error DQ
956 * ---------------------
957 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
958 * INMmod == DQ number
959 * ----------------------------------------------
960 * The 2ERR_DQ command transitions the DQ into the error state from the state
961 * in which it has been. While the command is executed, some in-process
962 * descriptors may complete. Once the DQ transitions into the error state,
963 * if there are posted descriptors on the RDQ/SDQ, the hardware writes
964 * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ.
965 * When the command is completed successfully, the DQ is already in
966 * the error state.
967 */
968
969 static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core *mlxsw_core,
970 u32 dq_number, u8 opcode_mod)
971 {
972 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ,
973 opcode_mod, dq_number);
974 }
975
976 static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core *mlxsw_core,
977 u32 dq_number)
978 {
979 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number,
980 MLXSW_CMD_OPCODE_MOD_SDQ);
981 }
982
983 static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core *mlxsw_core,
984 u32 dq_number)
985 {
986 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number,
987 MLXSW_CMD_OPCODE_MOD_RDQ);
988 }
989
990 /* QUERY_DQ - Query DQ
991 * ---------------------
992 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ)
993 * INMmod == DQ number
994 * ----------------------------------------------
995 * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware.
996 *
997 * Note: Output mailbox has the same format as SW2HW_DQ.
998 */
999
1000 static inline int __mlxsw_cmd_query_dq(struct mlxsw_core *mlxsw_core,
1001 char *out_mbox, u32 dq_number,
1002 u8 opcode_mod)
1003 {
1004 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ,
1005 opcode_mod, dq_number, false,
1006 out_mbox, MLXSW_CMD_MBOX_SIZE);
1007 }
1008
1009 static inline int mlxsw_cmd_query_sdq(struct mlxsw_core *mlxsw_core,
1010 char *out_mbox, u32 dq_number)
1011 {
1012 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number,
1013 MLXSW_CMD_OPCODE_MOD_SDQ);
1014 }
1015
1016 static inline int mlxsw_cmd_query_rdq(struct mlxsw_core *mlxsw_core,
1017 char *out_mbox, u32 dq_number)
1018 {
1019 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number,
1020 MLXSW_CMD_OPCODE_MOD_RDQ);
1021 }
1022
1023 /* SW2HW_CQ - Software to Hardware CQ
1024 * ----------------------------------
1025 * OpMod == 0 (N/A), INMmod == CQ number
1026 * -------------------------------------
1027 * The SW2HW_CQ command transfers ownership of a CQ context entry from software
1028 * to hardware. The command takes the CQ context entry from the input mailbox
1029 * and stores it in the CQC in the ownership of the hardware. The command fails
1030 * if the requested CQC entry is already in the ownership of the hardware.
1031 */
1032
1033 static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core,
1034 char *in_mbox, u32 cq_number)
1035 {
1036 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_CQ,
1037 0, cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE);
1038 }
1039
1040 enum mlxsw_cmd_mbox_sw2hw_cq_cqe_ver {
1041 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1,
1042 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2,
1043 };
1044
1045 /* cmd_mbox_sw2hw_cq_cqe_ver
1046 * CQE Version.
1047 */
1048 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cqe_ver, 0x00, 28, 4);
1049
1050 /* cmd_mbox_sw2hw_cq_c_eqn
1051 * Event Queue this CQ reports completion events to.
1052 */
1053 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1);
1054
1055 /* cmd_mbox_sw2hw_cq_st
1056 * Event delivery state machine
1057 * 0x0 - FIRED
1058 * 0x1 - ARMED (Request for Notification)
1059 */
1060 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1);
1061
1062 /* cmd_mbox_sw2hw_cq_log_cq_size
1063 * Log (base 2) of the CQ size (in entries).
1064 */
1065 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, log_cq_size, 0x00, 0, 4);
1066
1067 /* cmd_mbox_sw2hw_cq_producer_counter
1068 * Producer Counter. The counter is incremented for each CQE that is
1069 * written by the HW to the CQ.
1070 * Maintained by HW (valid for the QUERY_CQ command only)
1071 */
1072 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, producer_counter, 0x04, 0, 16);
1073
1074 /* cmd_mbox_sw2hw_cq_pa
1075 * Physical Address.
1076 */
1077 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_cq, pa, 0x10, 11, 53, 0x08, 0x00, true);
1078
1079 /* HW2SW_CQ - Hardware to Software CQ
1080 * ----------------------------------
1081 * OpMod == 0 (N/A), INMmod == CQ number
1082 * -------------------------------------
1083 * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware
1084 * to software. The CQC entry is invalidated as a result of this command.
1085 */
1086
1087 static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core *mlxsw_core,
1088 u32 cq_number)
1089 {
1090 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_CQ,
1091 0, cq_number);
1092 }
1093
1094 /* QUERY_CQ - Query CQ
1095 * ----------------------------------
1096 * OpMod == 0 (N/A), INMmod == CQ number
1097 * -------------------------------------
1098 * The QUERY_CQ command retrieves a snapshot of the current CQ context entry.
1099 * The command stores the snapshot in the output mailbox in the software format.
1100 * Note that the CQ context state and values are not affected by the QUERY_CQ
1101 * command. The QUERY_CQ command is for debug purposes only.
1102 *
1103 * Note: Output mailbox has the same format as SW2HW_CQ.
1104 */
1105
1106 static inline int mlxsw_cmd_query_cq(struct mlxsw_core *mlxsw_core,
1107 char *out_mbox, u32 cq_number)
1108 {
1109 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_CQ,
1110 0, cq_number, false,
1111 out_mbox, MLXSW_CMD_MBOX_SIZE);
1112 }
1113
1114 /* SW2HW_EQ - Software to Hardware EQ
1115 * ----------------------------------
1116 * OpMod == 0 (N/A), INMmod == EQ number
1117 * -------------------------------------
1118 * The SW2HW_EQ command transfers ownership of an EQ context entry from software
1119 * to hardware. The command takes the EQ context entry from the input mailbox
1120 * and stores it in the EQC in the ownership of the hardware. The command fails
1121 * if the requested EQC entry is already in the ownership of the hardware.
1122 */
1123
1124 static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core *mlxsw_core,
1125 char *in_mbox, u32 eq_number)
1126 {
1127 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_EQ,
1128 0, eq_number, in_mbox, MLXSW_CMD_MBOX_SIZE);
1129 }
1130
1131 /* cmd_mbox_sw2hw_eq_int_msix
1132 * When set, MSI-X cycles will be generated by this EQ.
1133 * When cleared, an interrupt will be generated by this EQ.
1134 */
1135 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, int_msix, 0x00, 24, 1);
1136
1137 /* cmd_mbox_sw2hw_eq_st
1138 * Event delivery state machine
1139 * 0x0 - FIRED
1140 * 0x1 - ARMED (Request for Notification)
1141 * 0x11 - Always ARMED
1142 * other - reserved
1143 */
1144 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, st, 0x00, 8, 2);
1145
1146 /* cmd_mbox_sw2hw_eq_log_eq_size
1147 * Log (base 2) of the EQ size (in entries).
1148 */
1149 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, log_eq_size, 0x00, 0, 4);
1150
1151 /* cmd_mbox_sw2hw_eq_producer_counter
1152 * Producer Counter. The counter is incremented for each EQE that is written
1153 * by the HW to the EQ.
1154 * Maintained by HW (valid for the QUERY_EQ command only)
1155 */
1156 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, producer_counter, 0x04, 0, 16);
1157
1158 /* cmd_mbox_sw2hw_eq_pa
1159 * Physical Address.
1160 */
1161 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_eq, pa, 0x10, 11, 53, 0x08, 0x00, true);
1162
1163 /* HW2SW_EQ - Hardware to Software EQ
1164 * ----------------------------------
1165 * OpMod == 0 (N/A), INMmod == EQ number
1166 * -------------------------------------
1167 */
1168
1169 static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core *mlxsw_core,
1170 u32 eq_number)
1171 {
1172 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_EQ,
1173 0, eq_number);
1174 }
1175
1176 /* QUERY_EQ - Query EQ
1177 * ----------------------------------
1178 * OpMod == 0 (N/A), INMmod == EQ number
1179 * -------------------------------------
1180 *
1181 * Note: Output mailbox has the same format as SW2HW_EQ.
1182 */
1183
1184 static inline int mlxsw_cmd_query_eq(struct mlxsw_core *mlxsw_core,
1185 char *out_mbox, u32 eq_number)
1186 {
1187 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_EQ,
1188 0, eq_number, false,
1189 out_mbox, MLXSW_CMD_MBOX_SIZE);
1190 }
1191
1192 #endif