root/drivers/net/ethernet/ibm/emac/core.h

INCLUDED FROM

DEFINITIONS

1. emac_rx_size
2. emac_rx_skb_size
3. emac_rx_sync_size
4. emac_has_feature
5. emac_xaht_base
6. emac_gaht_base
7. emac_iaht_base

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * drivers/net/ethernet/ibm/emac/core.h
   4  *
   5  * Driver for PowerPC 4xx on-chip ethernet controller.
   6  *
   7  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
   8  *                <benh@kernel.crashing.org>
   9  *
  10  * Based on the arch/ppc version of the driver:
  11  *
  12  * Copyright (c) 2004, 2005 Zultys Technologies.
  13  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  14  *
  15  * Based on original work by
  16  *      Armin Kuster <akuster@mvista.com>
  17  *      Johnnie Peters <jpeters@mvista.com>
  18  *      Copyright 2000, 2001 MontaVista Softare Inc.
  19  */
  20 #ifndef __IBM_NEWEMAC_CORE_H
  21 #define __IBM_NEWEMAC_CORE_H
  22 
  23 #include <linux/module.h>
  24 #include <linux/list.h>
  25 #include <linux/kernel.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/slab.h>
  32 
  33 #include <asm/io.h>
  34 #include <asm/dcr.h>
  35 
  36 #include "emac.h"
  37 #include "phy.h"
  38 #include "zmii.h"
  39 #include "rgmii.h"
  40 #include "mal.h"
  41 #include "tah.h"
  42 #include "debug.h"
  43 
  44 #define NUM_TX_BUFF                     CONFIG_IBM_EMAC_TXB
  45 #define NUM_RX_BUFF                     CONFIG_IBM_EMAC_RXB
  46 
  47 /* Simple sanity check */
  48 #if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
  49 #error Invalid number of buffer descriptors (greater than 256)
  50 #endif
  51 
  52 #define EMAC_MIN_MTU                    46
  53 
  54 /* Maximum L2 header length (VLAN tagged, no FCS) */
  55 #define EMAC_MTU_OVERHEAD               (6 * 2 + 2 + 4)
  56 
  57 /* RX BD size for the given MTU */
  58 static inline int emac_rx_size(int mtu)
  59 {
  60         if (mtu > ETH_DATA_LEN)
  61                 return MAL_MAX_RX_SIZE;
  62         else
  63                 return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
  64 }
  65 
  66 /* Size of RX skb for the given MTU */
  67 static inline int emac_rx_skb_size(int mtu)
  68 {
  69         int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
  70 
  71         return SKB_DATA_ALIGN(size + NET_IP_ALIGN) + NET_SKB_PAD;
  72 }
  73 
  74 /* RX DMA sync size */
  75 static inline int emac_rx_sync_size(int mtu)
  76 {
  77         return SKB_DATA_ALIGN(emac_rx_size(mtu) + NET_IP_ALIGN);
  78 }
  79 
  80 /* Driver statistcs is split into two parts to make it more cache friendly:
  81  *   - normal statistics (packet count, etc)
  82  *   - error statistics
  83  *
  84  * When statistics is requested by ethtool, these parts are concatenated,
  85  * normal one goes first.
  86  *
  87  * Please, keep these structures in sync with emac_stats_keys.
  88  */
  89 
  90 /* Normal TX/RX Statistics */
  91 struct emac_stats {
  92         u64 rx_packets;
  93         u64 rx_bytes;
  94         u64 tx_packets;
  95         u64 tx_bytes;
  96         u64 rx_packets_csum;
  97         u64 tx_packets_csum;
  98 };
  99 
 100 /* Error statistics */
 101 struct emac_error_stats {
 102         u64 tx_undo;
 103 
 104         /* Software RX Errors */
 105         u64 rx_dropped_stack;
 106         u64 rx_dropped_oom;
 107         u64 rx_dropped_error;
 108         u64 rx_dropped_resize;
 109         u64 rx_dropped_mtu;
 110         u64 rx_stopped;
 111         /* BD reported RX errors */
 112         u64 rx_bd_errors;
 113         u64 rx_bd_overrun;
 114         u64 rx_bd_bad_packet;
 115         u64 rx_bd_runt_packet;
 116         u64 rx_bd_short_event;
 117         u64 rx_bd_alignment_error;
 118         u64 rx_bd_bad_fcs;
 119         u64 rx_bd_packet_too_long;
 120         u64 rx_bd_out_of_range;
 121         u64 rx_bd_in_range;
 122         /* EMAC IRQ reported RX errors */
 123         u64 rx_parity;
 124         u64 rx_fifo_overrun;
 125         u64 rx_overrun;
 126         u64 rx_bad_packet;
 127         u64 rx_runt_packet;
 128         u64 rx_short_event;
 129         u64 rx_alignment_error;
 130         u64 rx_bad_fcs;
 131         u64 rx_packet_too_long;
 132         u64 rx_out_of_range;
 133         u64 rx_in_range;
 134 
 135         /* Software TX Errors */
 136         u64 tx_dropped;
 137         /* BD reported TX errors */
 138         u64 tx_bd_errors;
 139         u64 tx_bd_bad_fcs;
 140         u64 tx_bd_carrier_loss;
 141         u64 tx_bd_excessive_deferral;
 142         u64 tx_bd_excessive_collisions;
 143         u64 tx_bd_late_collision;
 144         u64 tx_bd_multple_collisions;
 145         u64 tx_bd_single_collision;
 146         u64 tx_bd_underrun;
 147         u64 tx_bd_sqe;
 148         /* EMAC IRQ reported TX errors */
 149         u64 tx_parity;
 150         u64 tx_underrun;
 151         u64 tx_sqe;
 152         u64 tx_errors;
 153 };
 154 
 155 #define EMAC_ETHTOOL_STATS_COUNT        ((sizeof(struct emac_stats) + \
 156                                           sizeof(struct emac_error_stats)) \
 157                                          / sizeof(u64))
 158 
 159 struct emac_instance {
 160         struct net_device               *ndev;
 161         struct emac_regs                __iomem *emacp;
 162         struct platform_device          *ofdev;
 163         struct device_node              **blist; /* bootlist entry */
 164 
 165         /* MAL linkage */
 166         u32                             mal_ph;
 167         struct platform_device          *mal_dev;
 168         u32                             mal_rx_chan;
 169         u32                             mal_tx_chan;
 170         struct mal_instance             *mal;
 171         struct mal_commac               commac;
 172 
 173         /* PHY infos */
 174         int                             phy_mode;
 175         u32                             phy_map;
 176         u32                             phy_address;
 177         u32                             phy_feat_exc;
 178         struct mii_phy                  phy;
 179         struct mutex                    link_lock;
 180         struct delayed_work             link_work;
 181         int                             link_polling;
 182 
 183         /* GPCS PHY infos */
 184         u32                             gpcs_address;
 185 
 186         /* Shared MDIO if any */
 187         u32                             mdio_ph;
 188         struct platform_device          *mdio_dev;
 189         struct emac_instance            *mdio_instance;
 190         struct mutex                    mdio_lock;
 191 
 192         /* Device-tree based phy configuration */
 193         struct mii_bus                  *mii_bus;
 194         struct phy_device               *phy_dev;
 195 
 196         /* ZMII infos if any */
 197         u32                             zmii_ph;
 198         u32                             zmii_port;
 199         struct platform_device          *zmii_dev;
 200 
 201         /* RGMII infos if any */
 202         u32                             rgmii_ph;
 203         u32                             rgmii_port;
 204         struct platform_device          *rgmii_dev;
 205 
 206         /* TAH infos if any */
 207         u32                             tah_ph;
 208         u32                             tah_port;
 209         struct platform_device          *tah_dev;
 210 
 211         /* IRQs */
 212         int                             wol_irq;
 213         int                             emac_irq;
 214 
 215         /* OPB bus frequency in Mhz */
 216         u32                             opb_bus_freq;
 217 
 218         /* Cell index within an ASIC (for clk mgmnt) */
 219         u32                             cell_index;
 220 
 221         /* Max supported MTU */
 222         u32                             max_mtu;
 223 
 224         /* Feature bits (from probe table) */
 225         unsigned int                    features;
 226 
 227         /* Tx and Rx fifo sizes & other infos in bytes */
 228         u32                             tx_fifo_size;
 229         u32                             tx_fifo_size_gige;
 230         u32                             rx_fifo_size;
 231         u32                             rx_fifo_size_gige;
 232         u32                             fifo_entry_size;
 233         u32                             mal_burst_size; /* move to MAL ? */
 234 
 235         /* IAHT and GAHT filter parameterization */
 236         u32                             xaht_slots_shift;
 237         u32                             xaht_width_shift;
 238 
 239         /* Descriptor management
 240          */
 241         struct mal_descriptor           *tx_desc;
 242         int                             tx_cnt;
 243         int                             tx_slot;
 244         int                             ack_slot;
 245 
 246         struct mal_descriptor           *rx_desc;
 247         int                             rx_slot;
 248         struct sk_buff                  *rx_sg_skb;     /* 1 */
 249         int                             rx_skb_size;
 250         int                             rx_sync_size;
 251 
 252         struct sk_buff                  *tx_skb[NUM_TX_BUFF];
 253         struct sk_buff                  *rx_skb[NUM_RX_BUFF];
 254 
 255         /* Stats
 256          */
 257         struct emac_error_stats         estats;
 258         struct emac_stats               stats;
 259 
 260         /* Misc
 261          */
 262         int                             reset_failed;
 263         int                             stop_timeout;   /* in us */
 264         int                             no_mcast;
 265         int                             mcast_pending;
 266         int                             opened;
 267         struct work_struct              reset_work;
 268         spinlock_t                      lock;
 269 };
 270 
 271 /*
 272  * Features of various EMAC implementations
 273  */
 274 
 275 /*
 276  * No flow control on 40x according to the original driver
 277  */
 278 #define EMAC_FTR_NO_FLOW_CONTROL_40x    0x00000001
 279 /*
 280  * Cell is an EMAC4
 281  */
 282 #define EMAC_FTR_EMAC4                  0x00000002
 283 /*
 284  * For the 440SPe, AMCC inexplicably changed the polarity of
 285  * the "operation complete" bit in the MII control register.
 286  */
 287 #define EMAC_FTR_STACR_OC_INVERT        0x00000004
 288 /*
 289  * Set if we have a TAH.
 290  */
 291 #define EMAC_FTR_HAS_TAH                0x00000008
 292 /*
 293  * Set if we have a ZMII.
 294  */
 295 #define EMAC_FTR_HAS_ZMII               0x00000010
 296 /*
 297  * Set if we have a RGMII.
 298  */
 299 #define EMAC_FTR_HAS_RGMII              0x00000020
 300 /*
 301  * Set if we have new type STACR with STAOPC
 302  */
 303 #define EMAC_FTR_HAS_NEW_STACR          0x00000040
 304 /*
 305  * Set if we need phy clock workaround for 440gx
 306  */
 307 #define EMAC_FTR_440GX_PHY_CLK_FIX      0x00000080
 308 /*
 309  * Set if we need phy clock workaround for 440ep or 440gr
 310  */
 311 #define EMAC_FTR_440EP_PHY_CLK_FIX      0x00000100
 312 /*
 313  * The 405EX and 460EX contain the EMAC4SYNC core
 314  */
 315 #define EMAC_FTR_EMAC4SYNC              0x00000200
 316 /*
 317  * Set if we need phy clock workaround for 460ex or 460gt
 318  */
 319 #define EMAC_FTR_460EX_PHY_CLK_FIX      0x00000400
 320 /*
 321  * APM821xx requires Jumbo frame size set explicitly
 322  */
 323 #define EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE      0x00000800
 324 /*
 325  * APM821xx does not support Half Duplex mode
 326  */
 327 #define EMAC_FTR_APM821XX_NO_HALF_DUPLEX        0x00001000
 328 
 329 /* Right now, we don't quite handle the always/possible masks on the
 330  * most optimal way as we don't have a way to say something like
 331  * always EMAC4. Patches welcome.
 332  */
 333 enum {
 334         EMAC_FTRS_ALWAYS        = 0,
 335 
 336         EMAC_FTRS_POSSIBLE      =
 337 #ifdef CONFIG_IBM_EMAC_EMAC4
 338             EMAC_FTR_EMAC4      | EMAC_FTR_EMAC4SYNC    |
 339             EMAC_FTR_HAS_NEW_STACR      |
 340             EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX |
 341 #endif
 342 #ifdef CONFIG_IBM_EMAC_TAH
 343             EMAC_FTR_HAS_TAH    |
 344 #endif
 345 #ifdef CONFIG_IBM_EMAC_ZMII
 346             EMAC_FTR_HAS_ZMII   |
 347 #endif
 348 #ifdef CONFIG_IBM_EMAC_RGMII
 349             EMAC_FTR_HAS_RGMII  |
 350 #endif
 351 #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL
 352             EMAC_FTR_NO_FLOW_CONTROL_40x |
 353 #endif
 354         EMAC_FTR_460EX_PHY_CLK_FIX |
 355         EMAC_FTR_440EP_PHY_CLK_FIX |
 356         EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
 357         EMAC_FTR_APM821XX_NO_HALF_DUPLEX,
 358 };
 359 
 360 static inline int emac_has_feature(struct emac_instance *dev,
 361                                    unsigned long feature)
 362 {
 363         return (EMAC_FTRS_ALWAYS & feature) ||
 364                (EMAC_FTRS_POSSIBLE & dev->features & feature);
 365 }
 366 
 367 /*
 368  * Various instances of the EMAC core have varying 1) number of
 369  * address match slots, 2) width of the registers for handling address
 370  * match slots, 3) number of registers for handling address match
 371  * slots and 4) base offset for those registers.
 372  *
 373  * These macros and inlines handle these differences based on
 374  * parameters supplied by the device structure which are, in turn,
 375  * initialized based on the "compatible" entry in the device tree.
 376  */
 377 
 378 #define EMAC4_XAHT_SLOTS_SHIFT          6
 379 #define EMAC4_XAHT_WIDTH_SHIFT          4
 380 
 381 #define EMAC4SYNC_XAHT_SLOTS_SHIFT      8
 382 #define EMAC4SYNC_XAHT_WIDTH_SHIFT      5
 383 
 384 /* The largest span between slots and widths above is 3 */
 385 #define EMAC_XAHT_MAX_REGS              (1 << 3)
 386 
 387 #define EMAC_XAHT_SLOTS(dev)            (1 << (dev)->xaht_slots_shift)
 388 #define EMAC_XAHT_WIDTH(dev)            (1 << (dev)->xaht_width_shift)
 389 #define EMAC_XAHT_REGS(dev)             (1 << ((dev)->xaht_slots_shift - \
 390                                                (dev)->xaht_width_shift))
 391 
 392 #define EMAC_XAHT_CRC_TO_SLOT(dev, crc)                 \
 393         ((EMAC_XAHT_SLOTS(dev) - 1) -                   \
 394          ((crc) >> ((sizeof (u32) * BITS_PER_BYTE) -    \
 395                     (dev)->xaht_slots_shift)))
 396 
 397 #define EMAC_XAHT_SLOT_TO_REG(dev, slot)                \
 398         ((slot) >> (dev)->xaht_width_shift)
 399 
 400 #define EMAC_XAHT_SLOT_TO_MASK(dev, slot)               \
 401         ((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >>      \
 402          ((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1)))
 403 
 404 static inline u32 *emac_xaht_base(struct emac_instance *dev)
 405 {
 406         struct emac_regs __iomem *p = dev->emacp;
 407         int offset;
 408 
 409         /* The first IAHT entry always is the base of the block of
 410          * IAHT and GAHT registers.
 411          */
 412         if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC))
 413                 offset = offsetof(struct emac_regs, u1.emac4sync.iaht1);
 414         else
 415                 offset = offsetof(struct emac_regs, u0.emac4.iaht1);
 416 
 417         return (u32 *)((ptrdiff_t)p + offset);
 418 }
 419 
 420 static inline u32 *emac_gaht_base(struct emac_instance *dev)
 421 {
 422         /* GAHT registers always come after an identical number of
 423          * IAHT registers.
 424          */
 425         return emac_xaht_base(dev) + EMAC_XAHT_REGS(dev);
 426 }
 427 
 428 static inline u32 *emac_iaht_base(struct emac_instance *dev)
 429 {
 430         /* IAHT registers always come before an identical number of
 431          * GAHT registers.
 432          */
 433         return emac_xaht_base(dev);
 434 }
 435 
 436 /* Ethtool get_regs complex data.
 437  * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
 438  * when available.
 439  *
 440  * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
 441  * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
 442  * Each register component is preceded with emac_ethtool_regs_subhdr.
 443  * Order of the optional headers follows their relative bit posititions
 444  * in emac_ethtool_regs_hdr.components
 445  */
 446 #define EMAC_ETHTOOL_REGS_ZMII          0x00000001
 447 #define EMAC_ETHTOOL_REGS_RGMII         0x00000002
 448 #define EMAC_ETHTOOL_REGS_TAH           0x00000004
 449 
 450 struct emac_ethtool_regs_hdr {
 451         u32 components;
 452 };
 453 
 454 struct emac_ethtool_regs_subhdr {
 455         u32 version;
 456         u32 index;
 457 };
 458 
 459 #define EMAC_ETHTOOL_REGS_VER           3
 460 #define EMAC4_ETHTOOL_REGS_VER          4
 461 #define EMAC4SYNC_ETHTOOL_REGS_VER      5
 462 
 463 #endif /* __IBM_NEWEMAC_CORE_H */