drivers/net/ethernet/freescale/dpaa/dpaa

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This source file includes following definitions.
bpool_buffer_raw_size
dpaa_netdev_init
dpaa_stop
dpaa_tx_timeout
dpaa_get_stats64
dpaa_setup_tc
dpaa_mac_dev_get
dpaa_set_mac_address
dpaa_set_rx_mode
dpaa_bpid2pool
dpaa_bpid2pool_use
dpaa_bpid2pool_map
dpaa_bp_alloc_pool
dpaa_bp_drain
dpaa_bp_free
dpaa_bps_free
dpaa_assign_wq
dpaa_fq_alloc
dpaa_alloc_all_fqs
dpaa_get_channel
dpaa_release_channel
dpaa_eth_add_channel
dpaa_eth_cgscn
dpaa_eth_cgr_init
dpaa_setup_ingress
dpaa_setup_egress
dpaa_fq_setup
dpaa_tx_fq_to_id
dpaa_fq_init
dpaa_fq_free_entry
dpaa_fq_free
dpaa_eth_init_tx_port
dpaa_eth_init_rx_port
dpaa_eth_init_ports
dpaa_bman_release
dpaa_release_sgt_members
dpaa_fd_release
count_ern
dpaa_enable_tx_csum
dpaa_bp_add_8_bufs
dpaa_bp_seed
dpaa_eth_refill_bpool
dpaa_eth_refill_bpools
dpaa_cleanup_tx_fd
rx_csum_offload
contig_fd_to_skb
sg_fd_to_skb
skb_to_contig_fd
skb_to_sg_fd
dpaa_xmit
dpaa_start_xmit
dpaa_rx_error
dpaa_tx_error
dpaa_eth_poll
dpaa_tx_conf
dpaa_eth_napi_schedule
rx_error_dqrr
rx_default_dqrr
conf_error_dqrr
conf_dflt_dqrr
egress_ern
dpaa_eth_napi_enable
dpaa_eth_napi_disable
dpaa_adjust_link
dpaa_phy_init
dpaa_open
dpaa_eth_stop
dpaa_ts_ioctl
dpaa_ioctl
dpaa_napi_add
dpaa_napi_del
dpaa_bp_free_pf
dpaa_bp_alloc
dpaa_ingress_cgr_init
dpaa_get_headroom
dpaa_eth_probe
dpaa_remove
dpaa_load
dpaa_unload
   1 /* Copyright 2008 - 2016 Freescale Semiconductor Inc.
   2  *
   3  * Redistribution and use in source and binary forms, with or without
   4  * modification, are permitted provided that the following conditions are met:
   5  *     * Redistributions of source code must retain the above copyright
   6  *       notice, this list of conditions and the following disclaimer.
   7  *     * Redistributions in binary form must reproduce the above copyright
   8  *       notice, this list of conditions and the following disclaimer in the
   9  *       documentation and/or other materials provided with the distribution.
  10  *     * Neither the name of Freescale Semiconductor nor the
  11  *       names of its contributors may be used to endorse or promote products
  12  *       derived from this software without specific prior written permission.
  13  *
  14  * ALTERNATIVELY, this software may be distributed under the terms of the
  15  * GNU General Public License ("GPL") as published by the Free Software
  16  * Foundation, either version 2 of that License or (at your option) any
  17  * later version.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  20  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30 
  31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  32 
  33 #include <linux/init.h>
  34 #include <linux/module.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/of_mdio.h>
  37 #include <linux/of_net.h>
  38 #include <linux/io.h>
  39 #include <linux/if_arp.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/icmp.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/udp.h>
  45 #include <linux/tcp.h>
  46 #include <linux/net.h>
  47 #include <linux/skbuff.h>
  48 #include <linux/etherdevice.h>
  49 #include <linux/if_ether.h>
  50 #include <linux/highmem.h>
  51 #include <linux/percpu.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/sort.h>
  54 #include <linux/phy_fixed.h>
  55 #include <soc/fsl/bman.h>
  56 #include <soc/fsl/qman.h>
  57 #include "fman.h"
  58 #include "fman_port.h"
  59 #include "mac.h"
  60 #include "dpaa_eth.h"
  61 
  62 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files
  63  * using trace events only need to #include <trace/events/sched.h>
  64  */
  65 #define CREATE_TRACE_POINTS
  66 #include "dpaa_eth_trace.h"
  67 
  68 static int debug = -1;
  69 module_param(debug, int, 0444);
  70 MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)");
  71 
  72 static u16 tx_timeout = 1000;
  73 module_param(tx_timeout, ushort, 0444);
  74 MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms");
  75 
  76 #define FM_FD_STAT_RX_ERRORS                                            \
  77         (FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL     | \
  78          FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \
  79          FM_FD_ERR_EXTRACTION | FM_FD_ERR_NO_SCHEME     | \
  80          FM_FD_ERR_PRS_TIMEOUT | FM_FD_ERR_PRS_ILL_INSTRUCT | \
  81          FM_FD_ERR_PRS_HDR_ERR)
  82 
  83 #define FM_FD_STAT_TX_ERRORS \
  84         (FM_FD_ERR_UNSUPPORTED_FORMAT | \
  85          FM_FD_ERR_LENGTH | FM_FD_ERR_DMA)
  86 
  87 #define DPAA_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
  88                           NETIF_MSG_LINK | NETIF_MSG_IFUP | \
  89                           NETIF_MSG_IFDOWN)
  90 
  91 #define DPAA_INGRESS_CS_THRESHOLD 0x10000000
  92 /* Ingress congestion threshold on FMan ports
  93  * The size in bytes of the ingress tail-drop threshold on FMan ports.
  94  * Traffic piling up above this value will be rejected by QMan and discarded
  95  * by FMan.
  96  */
  97 
  98 /* Size in bytes of the FQ taildrop threshold */
  99 #define DPAA_FQ_TD 0x200000
 100 
 101 #define DPAA_CS_THRESHOLD_1G 0x06000000
 102 /* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000
 103  * The size in bytes of the egress Congestion State notification threshold on
 104  * 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a
 105  * tight loop (e.g. by sending UDP datagrams at "while(1) speed"),
 106  * and the larger the frame size, the more acute the problem.
 107  * So we have to find a balance between these factors:
 108  * - avoiding the device staying congested for a prolonged time (risking
 109  *   the netdev watchdog to fire - see also the tx_timeout module param);
 110  * - affecting performance of protocols such as TCP, which otherwise
 111  *   behave well under the congestion notification mechanism;
 112  * - preventing the Tx cores from tightly-looping (as if the congestion
 113  *   threshold was too low to be effective);
 114  * - running out of memory if the CS threshold is set too high.
 115  */
 116 
 117 #define DPAA_CS_THRESHOLD_10G 0x10000000
 118 /* The size in bytes of the egress Congestion State notification threshold on
 119  * 10G ports, range 0x1000 .. 0x10000000
 120  */
 121 
 122 /* Largest value that the FQD's OAL field can hold */
 123 #define FSL_QMAN_MAX_OAL        127
 124 
 125 /* Default alignment for start of data in an Rx FD */
 126 #define DPAA_FD_DATA_ALIGNMENT  16
 127 
 128 /* The DPAA requires 256 bytes reserved and mapped for the SGT */
 129 #define DPAA_SGT_SIZE 256
 130 
 131 /* Values for the L3R field of the FM Parse Results
 132  */
 133 /* L3 Type field: First IP Present IPv4 */
 134 #define FM_L3_PARSE_RESULT_IPV4 0x8000
 135 /* L3 Type field: First IP Present IPv6 */
 136 #define FM_L3_PARSE_RESULT_IPV6 0x4000
 137 /* Values for the L4R field of the FM Parse Results */
 138 /* L4 Type field: UDP */
 139 #define FM_L4_PARSE_RESULT_UDP  0x40
 140 /* L4 Type field: TCP */
 141 #define FM_L4_PARSE_RESULT_TCP  0x20
 142 
 143 /* FD status field indicating whether the FM Parser has attempted to validate
 144  * the L4 csum of the frame.
 145  * Note that having this bit set doesn't necessarily imply that the checksum
 146  * is valid. One would have to check the parse results to find that out.
 147  */
 148 #define FM_FD_STAT_L4CV         0x00000004
 149 
 150 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
 151 #define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */
 152 
 153 #define FSL_DPAA_BPID_INV               0xff
 154 #define FSL_DPAA_ETH_MAX_BUF_COUNT      128
 155 #define FSL_DPAA_ETH_REFILL_THRESHOLD   80
 156 
 157 #define DPAA_TX_PRIV_DATA_SIZE  16
 158 #define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result)
 159 #define DPAA_TIME_STAMP_SIZE 8
 160 #define DPAA_HASH_RESULTS_SIZE 8
 161 #define DPAA_RX_PRIV_DATA_SIZE  (u16)(DPAA_TX_PRIV_DATA_SIZE + \
 162                                         dpaa_rx_extra_headroom)
 163 
 164 #define DPAA_ETH_PCD_RXQ_NUM    128
 165 
 166 #define DPAA_ENQUEUE_RETRIES    100000
 167 
 168 enum port_type {RX, TX};
 169 
 170 struct fm_port_fqs {
 171         struct dpaa_fq *tx_defq;
 172         struct dpaa_fq *tx_errq;
 173         struct dpaa_fq *rx_defq;
 174         struct dpaa_fq *rx_errq;
 175         struct dpaa_fq *rx_pcdq;
 176 };
 177 
 178 /* All the dpa bps in use at any moment */
 179 static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS];
 180 
 181 /* The raw buffer size must be cacheline aligned */
 182 #define DPAA_BP_RAW_SIZE 4096
 183 /* When using more than one buffer pool, the raw sizes are as follows:
 184  * 1 bp: 4KB
 185  * 2 bp: 2KB, 4KB
 186  * 3 bp: 1KB, 2KB, 4KB
 187  * 4 bp: 1KB, 2KB, 4KB, 8KB
 188  */
 189 static inline size_t bpool_buffer_raw_size(u8 index, u8 cnt)
 190 {
 191         size_t res = DPAA_BP_RAW_SIZE / 4;
 192         u8 i;
 193 
 194         for (i = (cnt < 3) ? cnt : 3; i < 3 + index; i++)
 195                 res *= 2;
 196         return res;
 197 }
 198 
 199 /* FMan-DMA requires 16-byte alignment for Rx buffers, but SKB_DATA_ALIGN is
 200  * even stronger (SMP_CACHE_BYTES-aligned), so we just get away with that,
 201  * via SKB_WITH_OVERHEAD(). We can't rely on netdev_alloc_frag() giving us
 202  * half-page-aligned buffers, so we reserve some more space for start-of-buffer
 203  * alignment.
 204  */
 205 #define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD((raw_size) - SMP_CACHE_BYTES)
 206 
 207 static int dpaa_max_frm;
 208 
 209 static int dpaa_rx_extra_headroom;
 210 
 211 #define dpaa_get_max_mtu()      \
 212         (dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN))
 213 
 214 static int dpaa_netdev_init(struct net_device *net_dev,
 215                             const struct net_device_ops *dpaa_ops,
 216                             u16 tx_timeout)
 217 {
 218         struct dpaa_priv *priv = netdev_priv(net_dev);
 219         struct device *dev = net_dev->dev.parent;
 220         struct dpaa_percpu_priv *percpu_priv;
 221         const u8 *mac_addr;
 222         int i, err;
 223 
 224         /* Although we access another CPU's private data here
 225          * we do it at initialization so it is safe
 226          */
 227         for_each_possible_cpu(i) {
 228                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
 229                 percpu_priv->net_dev = net_dev;
 230         }
 231 
 232         net_dev->netdev_ops = dpaa_ops;
 233         mac_addr = priv->mac_dev->addr;
 234 
 235         net_dev->mem_start = priv->mac_dev->res->start;
 236         net_dev->mem_end = priv->mac_dev->res->end;
 237 
 238         net_dev->min_mtu = ETH_MIN_MTU;
 239         net_dev->max_mtu = dpaa_get_max_mtu();
 240 
 241         net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
 242                                  NETIF_F_LLTX | NETIF_F_RXHASH);
 243 
 244         net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA;
 245         /* The kernels enables GSO automatically, if we declare NETIF_F_SG.
 246          * For conformity, we'll still declare GSO explicitly.
 247          */
 248         net_dev->features |= NETIF_F_GSO;
 249         net_dev->features |= NETIF_F_RXCSUM;
 250 
 251         net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
 252         /* we do not want shared skbs on TX */
 253         net_dev->priv_flags &= ~IFF_TX_SKB_SHARING;
 254 
 255         net_dev->features |= net_dev->hw_features;
 256         net_dev->vlan_features = net_dev->features;
 257 
 258         memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len);
 259         memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
 260 
 261         net_dev->ethtool_ops = &dpaa_ethtool_ops;
 262 
 263         net_dev->needed_headroom = priv->tx_headroom;
 264         net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
 265 
 266         /* start without the RUNNING flag, phylib controls it later */
 267         netif_carrier_off(net_dev);
 268 
 269         err = register_netdev(net_dev);
 270         if (err < 0) {
 271                 dev_err(dev, "register_netdev() = %d\n", err);
 272                 return err;
 273         }
 274 
 275         return 0;
 276 }
 277 
 278 static int dpaa_stop(struct net_device *net_dev)
 279 {
 280         struct mac_device *mac_dev;
 281         struct dpaa_priv *priv;
 282         int i, err, error;
 283 
 284         priv = netdev_priv(net_dev);
 285         mac_dev = priv->mac_dev;
 286 
 287         netif_tx_stop_all_queues(net_dev);
 288         /* Allow the Fman (Tx) port to process in-flight frames before we
 289          * try switching it off.
 290          */
 291         usleep_range(5000, 10000);
 292 
 293         err = mac_dev->stop(mac_dev);
 294         if (err < 0)
 295                 netif_err(priv, ifdown, net_dev, "mac_dev->stop() = %d\n",
 296                           err);
 297 
 298         for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
 299                 error = fman_port_disable(mac_dev->port[i]);
 300                 if (error)
 301                         err = error;
 302         }
 303 
 304         if (net_dev->phydev)
 305                 phy_disconnect(net_dev->phydev);
 306         net_dev->phydev = NULL;
 307 
 308         return err;
 309 }
 310 
 311 static void dpaa_tx_timeout(struct net_device *net_dev)
 312 {
 313         struct dpaa_percpu_priv *percpu_priv;
 314         const struct dpaa_priv  *priv;
 315 
 316         priv = netdev_priv(net_dev);
 317         percpu_priv = this_cpu_ptr(priv->percpu_priv);
 318 
 319         netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n",
 320                    jiffies_to_msecs(jiffies - dev_trans_start(net_dev)));
 321 
 322         percpu_priv->stats.tx_errors++;
 323 }
 324 
 325 /* Calculates the statistics for the given device by adding the statistics
 326  * collected by each CPU.
 327  */
 328 static void dpaa_get_stats64(struct net_device *net_dev,
 329                              struct rtnl_link_stats64 *s)
 330 {
 331         int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64);
 332         struct dpaa_priv *priv = netdev_priv(net_dev);
 333         struct dpaa_percpu_priv *percpu_priv;
 334         u64 *netstats = (u64 *)s;
 335         u64 *cpustats;
 336         int i, j;
 337 
 338         for_each_possible_cpu(i) {
 339                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
 340 
 341                 cpustats = (u64 *)&percpu_priv->stats;
 342 
 343                 /* add stats from all CPUs */
 344                 for (j = 0; j < numstats; j++)
 345                         netstats[j] += cpustats[j];
 346         }
 347 }
 348 
 349 static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
 350                          void *type_data)
 351 {
 352         struct dpaa_priv *priv = netdev_priv(net_dev);
 353         struct tc_mqprio_qopt *mqprio = type_data;
 354         u8 num_tc;
 355         int i;
 356 
 357         if (type != TC_SETUP_QDISC_MQPRIO)
 358                 return -EOPNOTSUPP;
 359 
 360         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
 361         num_tc = mqprio->num_tc;
 362 
 363         if (num_tc == priv->num_tc)
 364                 return 0;
 365 
 366         if (!num_tc) {
 367                 netdev_reset_tc(net_dev);
 368                 goto out;
 369         }
 370 
 371         if (num_tc > DPAA_TC_NUM) {
 372                 netdev_err(net_dev, "Too many traffic classes: max %d supported.\n",
 373                            DPAA_TC_NUM);
 374                 return -EINVAL;
 375         }
 376 
 377         netdev_set_num_tc(net_dev, num_tc);
 378 
 379         for (i = 0; i < num_tc; i++)
 380                 netdev_set_tc_queue(net_dev, i, DPAA_TC_TXQ_NUM,
 381                                     i * DPAA_TC_TXQ_NUM);
 382 
 383 out:
 384         priv->num_tc = num_tc ? : 1;
 385         netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
 386         return 0;
 387 }
 388 
 389 static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev)
 390 {
 391         struct dpaa_eth_data *eth_data;
 392         struct device *dpaa_dev;
 393         struct mac_device *mac_dev;
 394 
 395         dpaa_dev = &pdev->dev;
 396         eth_data = dpaa_dev->platform_data;
 397         if (!eth_data) {
 398                 dev_err(dpaa_dev, "eth_data missing\n");
 399                 return ERR_PTR(-ENODEV);
 400         }
 401         mac_dev = eth_data->mac_dev;
 402         if (!mac_dev) {
 403                 dev_err(dpaa_dev, "mac_dev missing\n");
 404                 return ERR_PTR(-EINVAL);
 405         }
 406 
 407         return mac_dev;
 408 }
 409 
 410 static int dpaa_set_mac_address(struct net_device *net_dev, void *addr)
 411 {
 412         const struct dpaa_priv *priv;
 413         struct mac_device *mac_dev;
 414         struct sockaddr old_addr;
 415         int err;
 416 
 417         priv = netdev_priv(net_dev);
 418 
 419         memcpy(old_addr.sa_data, net_dev->dev_addr,  ETH_ALEN);
 420 
 421         err = eth_mac_addr(net_dev, addr);
 422         if (err < 0) {
 423                 netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err);
 424                 return err;
 425         }
 426 
 427         mac_dev = priv->mac_dev;
 428 
 429         err = mac_dev->change_addr(mac_dev->fman_mac,
 430                                    (enet_addr_t *)net_dev->dev_addr);
 431         if (err < 0) {
 432                 netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n",
 433                           err);
 434                 /* reverting to previous address */
 435                 eth_mac_addr(net_dev, &old_addr);
 436 
 437                 return err;
 438         }
 439 
 440         return 0;
 441 }
 442 
 443 static void dpaa_set_rx_mode(struct net_device *net_dev)
 444 {
 445         const struct dpaa_priv  *priv;
 446         int err;
 447 
 448         priv = netdev_priv(net_dev);
 449 
 450         if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) {
 451                 priv->mac_dev->promisc = !priv->mac_dev->promisc;
 452                 err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac,
 453                                                  priv->mac_dev->promisc);
 454                 if (err < 0)
 455                         netif_err(priv, drv, net_dev,
 456                                   "mac_dev->set_promisc() = %d\n",
 457                                   err);
 458         }
 459 
 460         if (!!(net_dev->flags & IFF_ALLMULTI) != priv->mac_dev->allmulti) {
 461                 priv->mac_dev->allmulti = !priv->mac_dev->allmulti;
 462                 err = priv->mac_dev->set_allmulti(priv->mac_dev->fman_mac,
 463                                                   priv->mac_dev->allmulti);
 464                 if (err < 0)
 465                         netif_err(priv, drv, net_dev,
 466                                   "mac_dev->set_allmulti() = %d\n",
 467                                   err);
 468         }
 469 
 470         err = priv->mac_dev->set_multi(net_dev, priv->mac_dev);
 471         if (err < 0)
 472                 netif_err(priv, drv, net_dev, "mac_dev->set_multi() = %d\n",
 473                           err);
 474 }
 475 
 476 static struct dpaa_bp *dpaa_bpid2pool(int bpid)
 477 {
 478         if (WARN_ON(bpid < 0 || bpid >= BM_MAX_NUM_OF_POOLS))
 479                 return NULL;
 480 
 481         return dpaa_bp_array[bpid];
 482 }
 483 
 484 /* checks if this bpool is already allocated */
 485 static bool dpaa_bpid2pool_use(int bpid)
 486 {
 487         if (dpaa_bpid2pool(bpid)) {
 488                 refcount_inc(&dpaa_bp_array[bpid]->refs);
 489                 return true;
 490         }
 491 
 492         return false;
 493 }
 494 
 495 /* called only once per bpid by dpaa_bp_alloc_pool() */
 496 static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp)
 497 {
 498         dpaa_bp_array[bpid] = dpaa_bp;
 499         refcount_set(&dpaa_bp->refs, 1);
 500 }
 501 
 502 static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp)
 503 {
 504         int err;
 505 
 506         if (dpaa_bp->size == 0 || dpaa_bp->config_count == 0) {
 507                 pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n",
 508                        __func__);
 509                 return -EINVAL;
 510         }
 511 
 512         /* If the pool is already specified, we only create one per bpid */
 513         if (dpaa_bp->bpid != FSL_DPAA_BPID_INV &&
 514             dpaa_bpid2pool_use(dpaa_bp->bpid))
 515                 return 0;
 516 
 517         if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) {
 518                 dpaa_bp->pool = bman_new_pool();
 519                 if (!dpaa_bp->pool) {
 520                         pr_err("%s: bman_new_pool() failed\n",
 521                                __func__);
 522                         return -ENODEV;
 523                 }
 524 
 525                 dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool);
 526         }
 527 
 528         if (dpaa_bp->seed_cb) {
 529                 err = dpaa_bp->seed_cb(dpaa_bp);
 530                 if (err)
 531                         goto pool_seed_failed;
 532         }
 533 
 534         dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp);
 535 
 536         return 0;
 537 
 538 pool_seed_failed:
 539         pr_err("%s: pool seeding failed\n", __func__);
 540         bman_free_pool(dpaa_bp->pool);
 541 
 542         return err;
 543 }
 544 
 545 /* remove and free all the buffers from the given buffer pool */
 546 static void dpaa_bp_drain(struct dpaa_bp *bp)
 547 {
 548         u8 num = 8;
 549         int ret;
 550 
 551         do {
 552                 struct bm_buffer bmb[8];
 553                 int i;
 554 
 555                 ret = bman_acquire(bp->pool, bmb, num);
 556                 if (ret < 0) {
 557                         if (num == 8) {
 558                                 /* we have less than 8 buffers left;
 559                                  * drain them one by one
 560                                  */
 561                                 num = 1;
 562                                 ret = 1;
 563                                 continue;
 564                         } else {
 565                                 /* Pool is fully drained */
 566                                 break;
 567                         }
 568                 }
 569 
 570                 if (bp->free_buf_cb)
 571                         for (i = 0; i < num; i++)
 572                                 bp->free_buf_cb(bp, &bmb[i]);
 573         } while (ret > 0);
 574 }
 575 
 576 static void dpaa_bp_free(struct dpaa_bp *dpaa_bp)
 577 {
 578         struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid);
 579 
 580         /* the mapping between bpid and dpaa_bp is done very late in the
 581          * allocation procedure; if something failed before the mapping, the bp
 582          * was not configured, therefore we don't need the below instructions
 583          */
 584         if (!bp)
 585                 return;
 586 
 587         if (!refcount_dec_and_test(&bp->refs))
 588                 return;
 589 
 590         if (bp->free_buf_cb)
 591                 dpaa_bp_drain(bp);
 592 
 593         dpaa_bp_array[bp->bpid] = NULL;
 594         bman_free_pool(bp->pool);
 595 }
 596 
 597 static void dpaa_bps_free(struct dpaa_priv *priv)
 598 {
 599         int i;
 600 
 601         for (i = 0; i < DPAA_BPS_NUM; i++)
 602                 dpaa_bp_free(priv->dpaa_bps[i]);
 603 }
 604 
 605 /* Use multiple WQs for FQ assignment:
 606  *      - Tx Confirmation queues go to WQ1.
 607  *      - Rx Error and Tx Error queues go to WQ5 (giving them a better chance
 608  *        to be scheduled, in case there are many more FQs in WQ6).
 609  *      - Rx Default goes to WQ6.
 610  *      - Tx queues go to different WQs depending on their priority. Equal
 611  *        chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and
 612  *        WQ0 (highest priority).
 613  * This ensures that Tx-confirmed buffers are timely released. In particular,
 614  * it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they
 615  * are greatly outnumbered by other FQs in the system, while
 616  * dequeue scheduling is round-robin.
 617  */
 618 static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx)
 619 {
 620         switch (fq->fq_type) {
 621         case FQ_TYPE_TX_CONFIRM:
 622         case FQ_TYPE_TX_CONF_MQ:
 623                 fq->wq = 1;
 624                 break;
 625         case FQ_TYPE_RX_ERROR:
 626         case FQ_TYPE_TX_ERROR:
 627                 fq->wq = 5;
 628                 break;
 629         case FQ_TYPE_RX_DEFAULT:
 630         case FQ_TYPE_RX_PCD:
 631                 fq->wq = 6;
 632                 break;
 633         case FQ_TYPE_TX:
 634                 switch (idx / DPAA_TC_TXQ_NUM) {
 635                 case 0:
 636                         /* Low priority (best effort) */
 637                         fq->wq = 6;
 638                         break;
 639                 case 1:
 640                         /* Medium priority */
 641                         fq->wq = 2;
 642                         break;
 643                 case 2:
 644                         /* High priority */
 645                         fq->wq = 1;
 646                         break;
 647                 case 3:
 648                         /* Very high priority */
 649                         fq->wq = 0;
 650                         break;
 651                 default:
 652                         WARN(1, "Too many TX FQs: more than %d!\n",
 653                              DPAA_ETH_TXQ_NUM);
 654                 }
 655                 break;
 656         default:
 657                 WARN(1, "Invalid FQ type %d for FQID %d!\n",
 658                      fq->fq_type, fq->fqid);
 659         }
 660 }
 661 
 662 static struct dpaa_fq *dpaa_fq_alloc(struct device *dev,
 663                                      u32 start, u32 count,
 664                                      struct list_head *list,
 665                                      enum dpaa_fq_type fq_type)
 666 {
 667         struct dpaa_fq *dpaa_fq;
 668         int i;
 669 
 670         dpaa_fq = devm_kcalloc(dev, count, sizeof(*dpaa_fq),
 671                                GFP_KERNEL);
 672         if (!dpaa_fq)
 673                 return NULL;
 674 
 675         for (i = 0; i < count; i++) {
 676                 dpaa_fq[i].fq_type = fq_type;
 677                 dpaa_fq[i].fqid = start ? start + i : 0;
 678                 list_add_tail(&dpaa_fq[i].list, list);
 679         }
 680 
 681         for (i = 0; i < count; i++)
 682                 dpaa_assign_wq(dpaa_fq + i, i);
 683 
 684         return dpaa_fq;
 685 }
 686 
 687 static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list,
 688                               struct fm_port_fqs *port_fqs)
 689 {
 690         struct dpaa_fq *dpaa_fq;
 691         u32 fq_base, fq_base_aligned, i;
 692 
 693         dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR);
 694         if (!dpaa_fq)
 695                 goto fq_alloc_failed;
 696 
 697         port_fqs->rx_errq = &dpaa_fq[0];
 698 
 699         dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT);
 700         if (!dpaa_fq)
 701                 goto fq_alloc_failed;
 702 
 703         port_fqs->rx_defq = &dpaa_fq[0];
 704 
 705         /* the PCD FQIDs range needs to be aligned for correct operation */
 706         if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM))
 707                 goto fq_alloc_failed;
 708 
 709         fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM);
 710 
 711         for (i = fq_base; i < fq_base_aligned; i++)
 712                 qman_release_fqid(i);
 713 
 714         for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM;
 715              i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++)
 716                 qman_release_fqid(i);
 717 
 718         dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM,
 719                                 list, FQ_TYPE_RX_PCD);
 720         if (!dpaa_fq)
 721                 goto fq_alloc_failed;
 722 
 723         port_fqs->rx_pcdq = &dpaa_fq[0];
 724 
 725         if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX_CONF_MQ))
 726                 goto fq_alloc_failed;
 727 
 728         dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR);
 729         if (!dpaa_fq)
 730                 goto fq_alloc_failed;
 731 
 732         port_fqs->tx_errq = &dpaa_fq[0];
 733 
 734         dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM);
 735         if (!dpaa_fq)
 736                 goto fq_alloc_failed;
 737 
 738         port_fqs->tx_defq = &dpaa_fq[0];
 739 
 740         if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX))
 741                 goto fq_alloc_failed;
 742 
 743         return 0;
 744 
 745 fq_alloc_failed:
 746         dev_err(dev, "dpaa_fq_alloc() failed\n");
 747         return -ENOMEM;
 748 }
 749 
 750 static u32 rx_pool_channel;
 751 static DEFINE_SPINLOCK(rx_pool_channel_init);
 752 
 753 static int dpaa_get_channel(void)
 754 {
 755         spin_lock(&rx_pool_channel_init);
 756         if (!rx_pool_channel) {
 757                 u32 pool;
 758                 int ret;
 759 
 760                 ret = qman_alloc_pool(&pool);
 761 
 762                 if (!ret)
 763                         rx_pool_channel = pool;
 764         }
 765         spin_unlock(&rx_pool_channel_init);
 766         if (!rx_pool_channel)
 767                 return -ENOMEM;
 768         return rx_pool_channel;
 769 }
 770 
 771 static void dpaa_release_channel(void)
 772 {
 773         qman_release_pool(rx_pool_channel);
 774 }
 775 
 776 static void dpaa_eth_add_channel(u16 channel)
 777 {
 778         u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel);
 779         const cpumask_t *cpus = qman_affine_cpus();
 780         struct qman_portal *portal;
 781         int cpu;
 782 
 783         for_each_cpu_and(cpu, cpus, cpu_online_mask) {
 784                 portal = qman_get_affine_portal(cpu);
 785                 qman_p_static_dequeue_add(portal, pool);
 786         }
 787 }
 788 
 789 /* Congestion group state change notification callback.
 790  * Stops the device's egress queues while they are congested and
 791  * wakes them upon exiting congested state.
 792  * Also updates some CGR-related stats.
 793  */
 794 static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr,
 795                            int congested)
 796 {
 797         struct dpaa_priv *priv = (struct dpaa_priv *)container_of(cgr,
 798                 struct dpaa_priv, cgr_data.cgr);
 799 
 800         if (congested) {
 801                 priv->cgr_data.congestion_start_jiffies = jiffies;
 802                 netif_tx_stop_all_queues(priv->net_dev);
 803                 priv->cgr_data.cgr_congested_count++;
 804         } else {
 805                 priv->cgr_data.congested_jiffies +=
 806                         (jiffies - priv->cgr_data.congestion_start_jiffies);
 807                 netif_tx_wake_all_queues(priv->net_dev);
 808         }
 809 }
 810 
 811 static int dpaa_eth_cgr_init(struct dpaa_priv *priv)
 812 {
 813         struct qm_mcc_initcgr initcgr;
 814         u32 cs_th;
 815         int err;
 816 
 817         err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid);
 818         if (err < 0) {
 819                 if (netif_msg_drv(priv))
 820                         pr_err("%s: Error %d allocating CGR ID\n",
 821                                __func__, err);
 822                 goto out_error;
 823         }
 824         priv->cgr_data.cgr.cb = dpaa_eth_cgscn;
 825 
 826         /* Enable Congestion State Change Notifications and CS taildrop */
 827         memset(&initcgr, 0, sizeof(initcgr));
 828         initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES);
 829         initcgr.cgr.cscn_en = QM_CGR_EN;
 830 
 831         /* Set different thresholds based on the MAC speed.
 832          * This may turn suboptimal if the MAC is reconfigured at a speed
 833          * lower than its max, e.g. if a dTSEC later negotiates a 100Mbps link.
 834          * In such cases, we ought to reconfigure the threshold, too.
 835          */
 836         if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full)
 837                 cs_th = DPAA_CS_THRESHOLD_10G;
 838         else
 839                 cs_th = DPAA_CS_THRESHOLD_1G;
 840         qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
 841 
 842         initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
 843         initcgr.cgr.cstd_en = QM_CGR_EN;
 844 
 845         err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT,
 846                               &initcgr);
 847         if (err < 0) {
 848                 if (netif_msg_drv(priv))
 849                         pr_err("%s: Error %d creating CGR with ID %d\n",
 850                                __func__, err, priv->cgr_data.cgr.cgrid);
 851                 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
 852                 goto out_error;
 853         }
 854         if (netif_msg_drv(priv))
 855                 pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n",
 856                          priv->cgr_data.cgr.cgrid, priv->mac_dev->addr,
 857                          priv->cgr_data.cgr.chan);
 858 
 859 out_error:
 860         return err;
 861 }
 862 
 863 static inline void dpaa_setup_ingress(const struct dpaa_priv *priv,
 864                                       struct dpaa_fq *fq,
 865                                       const struct qman_fq *template)
 866 {
 867         fq->fq_base = *template;
 868         fq->net_dev = priv->net_dev;
 869 
 870         fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE;
 871         fq->channel = priv->channel;
 872 }
 873 
 874 static inline void dpaa_setup_egress(const struct dpaa_priv *priv,
 875                                      struct dpaa_fq *fq,
 876                                      struct fman_port *port,
 877                                      const struct qman_fq *template)
 878 {
 879         fq->fq_base = *template;
 880         fq->net_dev = priv->net_dev;
 881 
 882         if (port) {
 883                 fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL;
 884                 fq->channel = (u16)fman_port_get_qman_channel_id(port);
 885         } else {
 886                 fq->flags = QMAN_FQ_FLAG_NO_MODIFY;
 887         }
 888 }
 889 
 890 static void dpaa_fq_setup(struct dpaa_priv *priv,
 891                           const struct dpaa_fq_cbs *fq_cbs,
 892                           struct fman_port *tx_port)
 893 {
 894         int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu;
 895         const cpumask_t *affine_cpus = qman_affine_cpus();
 896         u16 channels[NR_CPUS];
 897         struct dpaa_fq *fq;
 898 
 899         for_each_cpu_and(cpu, affine_cpus, cpu_online_mask)
 900                 channels[num_portals++] = qman_affine_channel(cpu);
 901 
 902         if (num_portals == 0)
 903                 dev_err(priv->net_dev->dev.parent,
 904                         "No Qman software (affine) channels found");
 905 
 906         /* Initialize each FQ in the list */
 907         list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
 908                 switch (fq->fq_type) {
 909                 case FQ_TYPE_RX_DEFAULT:
 910                         dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
 911                         break;
 912                 case FQ_TYPE_RX_ERROR:
 913                         dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq);
 914                         break;
 915                 case FQ_TYPE_RX_PCD:
 916                         if (!num_portals)
 917                                 continue;
 918                         dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
 919                         fq->channel = channels[portal_cnt++ % num_portals];
 920                         break;
 921                 case FQ_TYPE_TX:
 922                         dpaa_setup_egress(priv, fq, tx_port,
 923                                           &fq_cbs->egress_ern);
 924                         /* If we have more Tx queues than the number of cores,
 925                          * just ignore the extra ones.
 926                          */
 927                         if (egress_cnt < DPAA_ETH_TXQ_NUM)
 928                                 priv->egress_fqs[egress_cnt++] = &fq->fq_base;
 929                         break;
 930                 case FQ_TYPE_TX_CONF_MQ:
 931                         priv->conf_fqs[conf_cnt++] = &fq->fq_base;
 932                         /* fall through */
 933                 case FQ_TYPE_TX_CONFIRM:
 934                         dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq);
 935                         break;
 936                 case FQ_TYPE_TX_ERROR:
 937                         dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq);
 938                         break;
 939                 default:
 940                         dev_warn(priv->net_dev->dev.parent,
 941                                  "Unknown FQ type detected!\n");
 942                         break;
 943                 }
 944         }
 945 
 946          /* Make sure all CPUs receive a corresponding Tx queue. */
 947         while (egress_cnt < DPAA_ETH_TXQ_NUM) {
 948                 list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
 949                         if (fq->fq_type != FQ_TYPE_TX)
 950                                 continue;
 951                         priv->egress_fqs[egress_cnt++] = &fq->fq_base;
 952                         if (egress_cnt == DPAA_ETH_TXQ_NUM)
 953                                 break;
 954                 }
 955         }
 956 }
 957 
 958 static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv,
 959                                    struct qman_fq *tx_fq)
 960 {
 961         int i;
 962 
 963         for (i = 0; i < DPAA_ETH_TXQ_NUM; i++)
 964                 if (priv->egress_fqs[i] == tx_fq)
 965                         return i;
 966 
 967         return -EINVAL;
 968 }
 969 
 970 static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable)
 971 {
 972         const struct dpaa_priv  *priv;
 973         struct qman_fq *confq = NULL;
 974         struct qm_mcc_initfq initfq;
 975         struct device *dev;
 976         struct qman_fq *fq;
 977         int queue_id;
 978         int err;
 979 
 980         priv = netdev_priv(dpaa_fq->net_dev);
 981         dev = dpaa_fq->net_dev->dev.parent;
 982 
 983         if (dpaa_fq->fqid == 0)
 984                 dpaa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
 985 
 986         dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY);
 987 
 988         err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base);
 989         if (err) {
 990                 dev_err(dev, "qman_create_fq() failed\n");
 991                 return err;
 992         }
 993         fq = &dpaa_fq->fq_base;
 994 
 995         if (dpaa_fq->init) {
 996                 memset(&initfq, 0, sizeof(initfq));
 997 
 998                 initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL);
 999                 /* Note: we may get to keep an empty FQ in cache */
1000                 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE);
1001 
1002                 /* Try to reduce the number of portal interrupts for
1003                  * Tx Confirmation FQs.
1004                  */
1005                 if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM)
1006                         initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK);
1007 
1008                 /* FQ placement */
1009                 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ);
1010 
1011                 qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq);
1012 
1013                 /* Put all egress queues in a congestion group of their own.
1014                  * Sensu stricto, the Tx confirmation queues are Rx FQs,
1015                  * rather than Tx - but they nonetheless account for the
1016                  * memory footprint on behalf of egress traffic. We therefore
1017                  * place them in the netdev's CGR, along with the Tx FQs.
1018                  */
1019                 if (dpaa_fq->fq_type == FQ_TYPE_TX ||
1020                     dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM ||
1021                     dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) {
1022                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1023                         initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1024                         initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid;
1025                         /* Set a fixed overhead accounting, in an attempt to
1026                          * reduce the impact of fixed-size skb shells and the
1027                          * driver's needed headroom on system memory. This is
1028                          * especially the case when the egress traffic is
1029                          * composed of small datagrams.
1030                          * Unfortunately, QMan's OAL value is capped to an
1031                          * insufficient value, but even that is better than
1032                          * no overhead accounting at all.
1033                          */
1034                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1035                         qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1036                         qm_fqd_set_oal(&initfq.fqd,
1037                                        min(sizeof(struct sk_buff) +
1038                                        priv->tx_headroom,
1039                                        (size_t)FSL_QMAN_MAX_OAL));
1040                 }
1041 
1042                 if (td_enable) {
1043                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH);
1044                         qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1);
1045                         initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE);
1046                 }
1047 
1048                 if (dpaa_fq->fq_type == FQ_TYPE_TX) {
1049                         queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base);
1050                         if (queue_id >= 0)
1051                                 confq = priv->conf_fqs[queue_id];
1052                         if (confq) {
1053                                 initfq.we_mask |=
1054                                         cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1055                         /* ContextA: OVOM=1(use contextA2 bits instead of ICAD)
1056                          *           A2V=1 (contextA A2 field is valid)
1057                          *           A0V=1 (contextA A0 field is valid)
1058                          *           B0V=1 (contextB field is valid)
1059                          * ContextA A2: EBD=1 (deallocate buffers inside FMan)
1060                          * ContextB B0(ASPID): 0 (absolute Virtual Storage ID)
1061                          */
1062                                 qm_fqd_context_a_set64(&initfq.fqd,
1063                                                        0x1e00000080000000ULL);
1064                         }
1065                 }
1066 
1067                 /* Put all the ingress queues in our "ingress CGR". */
1068                 if (priv->use_ingress_cgr &&
1069                     (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
1070                      dpaa_fq->fq_type == FQ_TYPE_RX_ERROR ||
1071                      dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) {
1072                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1073                         initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1074                         initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid;
1075                         /* Set a fixed overhead accounting, just like for the
1076                          * egress CGR.
1077                          */
1078                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1079                         qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1080                         qm_fqd_set_oal(&initfq.fqd,
1081                                        min(sizeof(struct sk_buff) +
1082                                        priv->tx_headroom,
1083                                        (size_t)FSL_QMAN_MAX_OAL));
1084                 }
1085 
1086                 /* Initialization common to all ingress queues */
1087                 if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) {
1088                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1089                         initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_HOLDACTIVE |
1090                                                 QM_FQCTRL_CTXASTASHING);
1091                         initfq.fqd.context_a.stashing.exclusive =
1092                                 QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX |
1093                                 QM_STASHING_EXCL_ANNOTATION;
1094                         qm_fqd_set_stashing(&initfq.fqd, 1, 2,
1095                                             DIV_ROUND_UP(sizeof(struct qman_fq),
1096                                                          64));
1097                 }
1098 
1099                 err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq);
1100                 if (err < 0) {
1101                         dev_err(dev, "qman_init_fq(%u) = %d\n",
1102                                 qman_fq_fqid(fq), err);
1103                         qman_destroy_fq(fq);
1104                         return err;
1105                 }
1106         }
1107 
1108         dpaa_fq->fqid = qman_fq_fqid(fq);
1109 
1110         return 0;
1111 }
1112 
1113 static int dpaa_fq_free_entry(struct device *dev, struct qman_fq *fq)
1114 {
1115         const struct dpaa_priv  *priv;
1116         struct dpaa_fq *dpaa_fq;
1117         int err, error;
1118 
1119         err = 0;
1120 
1121         dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
1122         priv = netdev_priv(dpaa_fq->net_dev);
1123 
1124         if (dpaa_fq->init) {
1125                 err = qman_retire_fq(fq, NULL);
1126                 if (err < 0 && netif_msg_drv(priv))
1127                         dev_err(dev, "qman_retire_fq(%u) = %d\n",
1128                                 qman_fq_fqid(fq), err);
1129 
1130                 error = qman_oos_fq(fq);
1131                 if (error < 0 && netif_msg_drv(priv)) {
1132                         dev_err(dev, "qman_oos_fq(%u) = %d\n",
1133                                 qman_fq_fqid(fq), error);
1134                         if (err >= 0)
1135                                 err = error;
1136                 }
1137         }
1138 
1139         qman_destroy_fq(fq);
1140         list_del(&dpaa_fq->list);
1141 
1142         return err;
1143 }
1144 
1145 static int dpaa_fq_free(struct device *dev, struct list_head *list)
1146 {
1147         struct dpaa_fq *dpaa_fq, *tmp;
1148         int err, error;
1149 
1150         err = 0;
1151         list_for_each_entry_safe(dpaa_fq, tmp, list, list) {
1152                 error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq);
1153                 if (error < 0 && err >= 0)
1154                         err = error;
1155         }
1156 
1157         return err;
1158 }
1159 
1160 static int dpaa_eth_init_tx_port(struct fman_port *port, struct dpaa_fq *errq,
1161                                  struct dpaa_fq *defq,
1162                                  struct dpaa_buffer_layout *buf_layout)
1163 {
1164         struct fman_buffer_prefix_content buf_prefix_content;
1165         struct fman_port_params params;
1166         int err;
1167 
1168         memset(&params, 0, sizeof(params));
1169         memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1170 
1171         buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1172         buf_prefix_content.pass_prs_result = true;
1173         buf_prefix_content.pass_hash_result = true;
1174         buf_prefix_content.pass_time_stamp = true;
1175         buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1176 
1177         params.specific_params.non_rx_params.err_fqid = errq->fqid;
1178         params.specific_params.non_rx_params.dflt_fqid = defq->fqid;
1179 
1180         err = fman_port_config(port, &params);
1181         if (err) {
1182                 pr_err("%s: fman_port_config failed\n", __func__);
1183                 return err;
1184         }
1185 
1186         err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1187         if (err) {
1188                 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1189                        __func__);
1190                 return err;
1191         }
1192 
1193         err = fman_port_init(port);
1194         if (err)
1195                 pr_err("%s: fm_port_init failed\n", __func__);
1196 
1197         return err;
1198 }
1199 
1200 static int dpaa_eth_init_rx_port(struct fman_port *port, struct dpaa_bp **bps,
1201                                  size_t count, struct dpaa_fq *errq,
1202                                  struct dpaa_fq *defq, struct dpaa_fq *pcdq,
1203                                  struct dpaa_buffer_layout *buf_layout)
1204 {
1205         struct fman_buffer_prefix_content buf_prefix_content;
1206         struct fman_port_rx_params *rx_p;
1207         struct fman_port_params params;
1208         int i, err;
1209 
1210         memset(&params, 0, sizeof(params));
1211         memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1212 
1213         buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1214         buf_prefix_content.pass_prs_result = true;
1215         buf_prefix_content.pass_hash_result = true;
1216         buf_prefix_content.pass_time_stamp = true;
1217         buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1218 
1219         rx_p = &params.specific_params.rx_params;
1220         rx_p->err_fqid = errq->fqid;
1221         rx_p->dflt_fqid = defq->fqid;
1222         if (pcdq) {
1223                 rx_p->pcd_base_fqid = pcdq->fqid;
1224                 rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM;
1225         }
1226 
1227         count = min(ARRAY_SIZE(rx_p->ext_buf_pools.ext_buf_pool), count);
1228         rx_p->ext_buf_pools.num_of_pools_used = (u8)count;
1229         for (i = 0; i < count; i++) {
1230                 rx_p->ext_buf_pools.ext_buf_pool[i].id =  bps[i]->bpid;
1231                 rx_p->ext_buf_pools.ext_buf_pool[i].size = (u16)bps[i]->size;
1232         }
1233 
1234         err = fman_port_config(port, &params);
1235         if (err) {
1236                 pr_err("%s: fman_port_config failed\n", __func__);
1237                 return err;
1238         }
1239 
1240         err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1241         if (err) {
1242                 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1243                        __func__);
1244                 return err;
1245         }
1246 
1247         err = fman_port_init(port);
1248         if (err)
1249                 pr_err("%s: fm_port_init failed\n", __func__);
1250 
1251         return err;
1252 }
1253 
1254 static int dpaa_eth_init_ports(struct mac_device *mac_dev,
1255                                struct dpaa_bp **bps, size_t count,
1256                                struct fm_port_fqs *port_fqs,
1257                                struct dpaa_buffer_layout *buf_layout,
1258                                struct device *dev)
1259 {
1260         struct fman_port *rxport = mac_dev->port[RX];
1261         struct fman_port *txport = mac_dev->port[TX];
1262         int err;
1263 
1264         err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq,
1265                                     port_fqs->tx_defq, &buf_layout[TX]);
1266         if (err)
1267                 return err;
1268 
1269         err = dpaa_eth_init_rx_port(rxport, bps, count, port_fqs->rx_errq,
1270                                     port_fqs->rx_defq, port_fqs->rx_pcdq,
1271                                     &buf_layout[RX]);
1272 
1273         return err;
1274 }
1275 
1276 static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp,
1277                              struct bm_buffer *bmb, int cnt)
1278 {
1279         int err;
1280 
1281         err = bman_release(dpaa_bp->pool, bmb, cnt);
1282         /* Should never occur, address anyway to avoid leaking the buffers */
1283         if (WARN_ON(err) && dpaa_bp->free_buf_cb)
1284                 while (cnt-- > 0)
1285                         dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]);
1286 
1287         return cnt;
1288 }
1289 
1290 static void dpaa_release_sgt_members(struct qm_sg_entry *sgt)
1291 {
1292         struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX];
1293         struct dpaa_bp *dpaa_bp;
1294         int i = 0, j;
1295 
1296         memset(bmb, 0, sizeof(bmb));
1297 
1298         do {
1299                 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1300                 if (!dpaa_bp)
1301                         return;
1302 
1303                 j = 0;
1304                 do {
1305                         WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1306 
1307                         bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i]));
1308 
1309                         j++; i++;
1310                 } while (j < ARRAY_SIZE(bmb) &&
1311                                 !qm_sg_entry_is_final(&sgt[i - 1]) &&
1312                                 sgt[i - 1].bpid == sgt[i].bpid);
1313 
1314                 dpaa_bman_release(dpaa_bp, bmb, j);
1315         } while (!qm_sg_entry_is_final(&sgt[i - 1]));
1316 }
1317 
1318 static void dpaa_fd_release(const struct net_device *net_dev,
1319                             const struct qm_fd *fd)
1320 {
1321         struct qm_sg_entry *sgt;
1322         struct dpaa_bp *dpaa_bp;
1323         struct bm_buffer bmb;
1324         dma_addr_t addr;
1325         void *vaddr;
1326 
1327         bmb.data = 0;
1328         bm_buffer_set64(&bmb, qm_fd_addr(fd));
1329 
1330         dpaa_bp = dpaa_bpid2pool(fd->bpid);
1331         if (!dpaa_bp)
1332                 return;
1333 
1334         if (qm_fd_get_format(fd) == qm_fd_sg) {
1335                 vaddr = phys_to_virt(qm_fd_addr(fd));
1336                 sgt = vaddr + qm_fd_get_offset(fd);
1337 
1338                 dma_unmap_single(dpaa_bp->dev, qm_fd_addr(fd), dpaa_bp->size,
1339                                  DMA_FROM_DEVICE);
1340 
1341                 dpaa_release_sgt_members(sgt);
1342 
1343                 addr = dma_map_single(dpaa_bp->dev, vaddr, dpaa_bp->size,
1344                                       DMA_FROM_DEVICE);
1345                 if (dma_mapping_error(dpaa_bp->dev, addr)) {
1346                         dev_err(dpaa_bp->dev, "DMA mapping failed");
1347                         return;
1348                 }
1349                 bm_buffer_set64(&bmb, addr);
1350         }
1351 
1352         dpaa_bman_release(dpaa_bp, &bmb, 1);
1353 }
1354 
1355 static void count_ern(struct dpaa_percpu_priv *percpu_priv,
1356                       const union qm_mr_entry *msg)
1357 {
1358         switch (msg->ern.rc & QM_MR_RC_MASK) {
1359         case QM_MR_RC_CGR_TAILDROP:
1360                 percpu_priv->ern_cnt.cg_tdrop++;
1361                 break;
1362         case QM_MR_RC_WRED:
1363                 percpu_priv->ern_cnt.wred++;
1364                 break;
1365         case QM_MR_RC_ERROR:
1366                 percpu_priv->ern_cnt.err_cond++;
1367                 break;
1368         case QM_MR_RC_ORPWINDOW_EARLY:
1369                 percpu_priv->ern_cnt.early_window++;
1370                 break;
1371         case QM_MR_RC_ORPWINDOW_LATE:
1372                 percpu_priv->ern_cnt.late_window++;
1373                 break;
1374         case QM_MR_RC_FQ_TAILDROP:
1375                 percpu_priv->ern_cnt.fq_tdrop++;
1376                 break;
1377         case QM_MR_RC_ORPWINDOW_RETIRED:
1378                 percpu_priv->ern_cnt.fq_retired++;
1379                 break;
1380         case QM_MR_RC_ORP_ZERO:
1381                 percpu_priv->ern_cnt.orp_zero++;
1382                 break;
1383         }
1384 }
1385 
1386 /* Turn on HW checksum computation for this outgoing frame.
1387  * If the current protocol is not something we support in this regard
1388  * (or if the stack has already computed the SW checksum), we do nothing.
1389  *
1390  * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value
1391  * otherwise.
1392  *
1393  * Note that this function may modify the fd->cmd field and the skb data buffer
1394  * (the Parse Results area).
1395  */
1396 static int dpaa_enable_tx_csum(struct dpaa_priv *priv,
1397                                struct sk_buff *skb,
1398                                struct qm_fd *fd,
1399                                char *parse_results)
1400 {
1401         struct fman_prs_result *parse_result;
1402         u16 ethertype = ntohs(skb->protocol);
1403         struct ipv6hdr *ipv6h = NULL;
1404         struct iphdr *iph;
1405         int retval = 0;
1406         u8 l4_proto;
1407 
1408         if (skb->ip_summed != CHECKSUM_PARTIAL)
1409                 return 0;
1410 
1411         /* Note: L3 csum seems to be already computed in sw, but we can't choose
1412          * L4 alone from the FM configuration anyway.
1413          */
1414 
1415         /* Fill in some fields of the Parse Results array, so the FMan
1416          * can find them as if they came from the FMan Parser.
1417          */
1418         parse_result = (struct fman_prs_result *)parse_results;
1419 
1420         /* If we're dealing with VLAN, get the real Ethernet type */
1421         if (ethertype == ETH_P_8021Q) {
1422                 /* We can't always assume the MAC header is set correctly
1423                  * by the stack, so reset to beginning of skb->data
1424                  */
1425                 skb_reset_mac_header(skb);
1426                 ethertype = ntohs(vlan_eth_hdr(skb)->h_vlan_encapsulated_proto);
1427         }
1428 
1429         /* Fill in the relevant L3 parse result fields
1430          * and read the L4 protocol type
1431          */
1432         switch (ethertype) {
1433         case ETH_P_IP:
1434                 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4);
1435                 iph = ip_hdr(skb);
1436                 WARN_ON(!iph);
1437                 l4_proto = iph->protocol;
1438                 break;
1439         case ETH_P_IPV6:
1440                 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6);
1441                 ipv6h = ipv6_hdr(skb);
1442                 WARN_ON(!ipv6h);
1443                 l4_proto = ipv6h->nexthdr;
1444                 break;
1445         default:
1446                 /* We shouldn't even be here */
1447                 if (net_ratelimit())
1448                         netif_alert(priv, tx_err, priv->net_dev,
1449                                     "Can't compute HW csum for L3 proto 0x%x\n",
1450                                     ntohs(skb->protocol));
1451                 retval = -EIO;
1452                 goto return_error;
1453         }
1454 
1455         /* Fill in the relevant L4 parse result fields */
1456         switch (l4_proto) {
1457         case IPPROTO_UDP:
1458                 parse_result->l4r = FM_L4_PARSE_RESULT_UDP;
1459                 break;
1460         case IPPROTO_TCP:
1461                 parse_result->l4r = FM_L4_PARSE_RESULT_TCP;
1462                 break;
1463         default:
1464                 if (net_ratelimit())
1465                         netif_alert(priv, tx_err, priv->net_dev,
1466                                     "Can't compute HW csum for L4 proto 0x%x\n",
1467                                     l4_proto);
1468                 retval = -EIO;
1469                 goto return_error;
1470         }
1471 
1472         /* At index 0 is IPOffset_1 as defined in the Parse Results */
1473         parse_result->ip_off[0] = (u8)skb_network_offset(skb);
1474         parse_result->l4_off = (u8)skb_transport_offset(skb);
1475 
1476         /* Enable L3 (and L4, if TCP or UDP) HW checksum. */
1477         fd->cmd |= cpu_to_be32(FM_FD_CMD_RPD | FM_FD_CMD_DTC);
1478 
1479         /* On P1023 and similar platforms fd->cmd interpretation could
1480          * be disabled by setting CONTEXT_A bit ICMD; currently this bit
1481          * is not set so we do not need to check; in the future, if/when
1482          * using context_a we need to check this bit
1483          */
1484 
1485 return_error:
1486         return retval;
1487 }
1488 
1489 static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp)
1490 {
1491         struct device *dev = dpaa_bp->dev;
1492         struct bm_buffer bmb[8];
1493         dma_addr_t addr;
1494         void *new_buf;
1495         u8 i;
1496 
1497         for (i = 0; i < 8; i++) {
1498                 new_buf = netdev_alloc_frag(dpaa_bp->raw_size);
1499                 if (unlikely(!new_buf)) {
1500                         dev_err(dev, "netdev_alloc_frag() failed, size %zu\n",
1501                                 dpaa_bp->raw_size);
1502                         goto release_previous_buffs;
1503                 }
1504                 new_buf = PTR_ALIGN(new_buf, SMP_CACHE_BYTES);
1505 
1506                 addr = dma_map_single(dev, new_buf,
1507                                       dpaa_bp->size, DMA_FROM_DEVICE);
1508                 if (unlikely(dma_mapping_error(dev, addr))) {
1509                         dev_err(dpaa_bp->dev, "DMA map failed");
1510                         goto release_previous_buffs;
1511                 }
1512 
1513                 bmb[i].data = 0;
1514                 bm_buffer_set64(&bmb[i], addr);
1515         }
1516 
1517 release_bufs:
1518         return dpaa_bman_release(dpaa_bp, bmb, i);
1519 
1520 release_previous_buffs:
1521         WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n");
1522 
1523         bm_buffer_set64(&bmb[i], 0);
1524         /* Avoid releasing a completely null buffer; bman_release() requires
1525          * at least one buffer.
1526          */
1527         if (likely(i))
1528                 goto release_bufs;
1529 
1530         return 0;
1531 }
1532 
1533 static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp)
1534 {
1535         int i;
1536 
1537         /* Give each CPU an allotment of "config_count" buffers */
1538         for_each_possible_cpu(i) {
1539                 int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i);
1540                 int j;
1541 
1542                 /* Although we access another CPU's counters here
1543                  * we do it at boot time so it is safe
1544                  */
1545                 for (j = 0; j < dpaa_bp->config_count; j += 8)
1546                         *count_ptr += dpaa_bp_add_8_bufs(dpaa_bp);
1547         }
1548         return 0;
1549 }
1550 
1551 /* Add buffers/(pages) for Rx processing whenever bpool count falls below
1552  * REFILL_THRESHOLD.
1553  */
1554 static int dpaa_eth_refill_bpool(struct dpaa_bp *dpaa_bp, int *countptr)
1555 {
1556         int count = *countptr;
1557         int new_bufs;
1558 
1559         if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) {
1560                 do {
1561                         new_bufs = dpaa_bp_add_8_bufs(dpaa_bp);
1562                         if (unlikely(!new_bufs)) {
1563                                 /* Avoid looping forever if we've temporarily
1564                                  * run out of memory. We'll try again at the
1565                                  * next NAPI cycle.
1566                                  */
1567                                 break;
1568                         }
1569                         count += new_bufs;
1570                 } while (count < FSL_DPAA_ETH_MAX_BUF_COUNT);
1571 
1572                 *countptr = count;
1573                 if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT))
1574                         return -ENOMEM;
1575         }
1576 
1577         return 0;
1578 }
1579 
1580 static int dpaa_eth_refill_bpools(struct dpaa_priv *priv)
1581 {
1582         struct dpaa_bp *dpaa_bp;
1583         int *countptr;
1584         int res, i;
1585 
1586         for (i = 0; i < DPAA_BPS_NUM; i++) {
1587                 dpaa_bp = priv->dpaa_bps[i];
1588                 if (!dpaa_bp)
1589                         return -EINVAL;
1590                 countptr = this_cpu_ptr(dpaa_bp->percpu_count);
1591                 res  = dpaa_eth_refill_bpool(dpaa_bp, countptr);
1592                 if (res)
1593                         return res;
1594         }
1595         return 0;
1596 }
1597 
1598 /* Cleanup function for outgoing frame descriptors that were built on Tx path,
1599  * either contiguous frames or scatter/gather ones.
1600  * Skb freeing is not handled here.
1601  *
1602  * This function may be called on error paths in the Tx function, so guard
1603  * against cases when not all fd relevant fields were filled in. To avoid
1604  * reading the invalid transmission timestamp for the error paths set ts to
1605  * false.
1606  *
1607  * Return the skb backpointer, since for S/G frames the buffer containing it
1608  * gets freed here.
1609  */
1610 static struct sk_buff *dpaa_cleanup_tx_fd(const struct dpaa_priv *priv,
1611                                           const struct qm_fd *fd, bool ts)
1612 {
1613         const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1614         struct device *dev = priv->net_dev->dev.parent;
1615         struct skb_shared_hwtstamps shhwtstamps;
1616         dma_addr_t addr = qm_fd_addr(fd);
1617         const struct qm_sg_entry *sgt;
1618         struct sk_buff **skbh, *skb;
1619         int nr_frags, i;
1620         u64 ns;
1621 
1622         skbh = (struct sk_buff **)phys_to_virt(addr);
1623         skb = *skbh;
1624 
1625         if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) {
1626                 nr_frags = skb_shinfo(skb)->nr_frags;
1627                 dma_unmap_single(dev, addr,
1628                                  qm_fd_get_offset(fd) + DPAA_SGT_SIZE,
1629                                  dma_dir);
1630 
1631                 /* The sgt buffer has been allocated with netdev_alloc_frag(),
1632                  * it's from lowmem.
1633                  */
1634                 sgt = phys_to_virt(addr + qm_fd_get_offset(fd));
1635 
1636                 /* sgt[0] is from lowmem, was dma_map_single()-ed */
1637                 dma_unmap_single(dev, qm_sg_addr(&sgt[0]),
1638                                  qm_sg_entry_get_len(&sgt[0]), dma_dir);
1639 
1640                 /* remaining pages were mapped with skb_frag_dma_map() */
1641                 for (i = 1; i <= nr_frags; i++) {
1642                         WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1643 
1644                         dma_unmap_page(dev, qm_sg_addr(&sgt[i]),
1645                                        qm_sg_entry_get_len(&sgt[i]), dma_dir);
1646                 }
1647         } else {
1648                 dma_unmap_single(dev, addr,
1649                                  skb_tail_pointer(skb) - (u8 *)skbh, dma_dir);
1650         }
1651 
1652         /* DMA unmapping is required before accessing the HW provided info */
1653         if (ts && priv->tx_tstamp &&
1654             skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
1655                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
1656 
1657                 if (!fman_port_get_tstamp(priv->mac_dev->port[TX], (void *)skbh,
1658                                           &ns)) {
1659                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
1660                         skb_tstamp_tx(skb, &shhwtstamps);
1661                 } else {
1662                         dev_warn(dev, "fman_port_get_tstamp failed!\n");
1663                 }
1664         }
1665 
1666         if (qm_fd_get_format(fd) == qm_fd_sg)
1667                 /* Free the page frag that we allocated on Tx */
1668                 skb_free_frag(phys_to_virt(addr));
1669 
1670         return skb;
1671 }
1672 
1673 static u8 rx_csum_offload(const struct dpaa_priv *priv, const struct qm_fd *fd)
1674 {
1675         /* The parser has run and performed L4 checksum validation.
1676          * We know there were no parser errors (and implicitly no
1677          * L4 csum error), otherwise we wouldn't be here.
1678          */
1679         if ((priv->net_dev->features & NETIF_F_RXCSUM) &&
1680             (be32_to_cpu(fd->status) & FM_FD_STAT_L4CV))
1681                 return CHECKSUM_UNNECESSARY;
1682 
1683         /* We're here because either the parser didn't run or the L4 checksum
1684          * was not verified. This may include the case of a UDP frame with
1685          * checksum zero or an L4 proto other than TCP/UDP
1686          */
1687         return CHECKSUM_NONE;
1688 }
1689 
1690 /* Build a linear skb around the received buffer.
1691  * We are guaranteed there is enough room at the end of the data buffer to
1692  * accommodate the shared info area of the skb.
1693  */
1694 static struct sk_buff *contig_fd_to_skb(const struct dpaa_priv *priv,
1695                                         const struct qm_fd *fd)
1696 {
1697         ssize_t fd_off = qm_fd_get_offset(fd);
1698         dma_addr_t addr = qm_fd_addr(fd);
1699         struct dpaa_bp *dpaa_bp;
1700         struct sk_buff *skb;
1701         void *vaddr;
1702 
1703         vaddr = phys_to_virt(addr);
1704         WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1705 
1706         dpaa_bp = dpaa_bpid2pool(fd->bpid);
1707         if (!dpaa_bp)
1708                 goto free_buffer;
1709 
1710         skb = build_skb(vaddr, dpaa_bp->size +
1711                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
1712         if (WARN_ONCE(!skb, "Build skb failure on Rx\n"))
1713                 goto free_buffer;
1714         WARN_ON(fd_off != priv->rx_headroom);
1715         skb_reserve(skb, fd_off);
1716         skb_put(skb, qm_fd_get_length(fd));
1717 
1718         skb->ip_summed = rx_csum_offload(priv, fd);
1719 
1720         return skb;
1721 
1722 free_buffer:
1723         skb_free_frag(vaddr);
1724         return NULL;
1725 }
1726 
1727 /* Build an skb with the data of the first S/G entry in the linear portion and
1728  * the rest of the frame as skb fragments.
1729  *
1730  * The page fragment holding the S/G Table is recycled here.
1731  */
1732 static struct sk_buff *sg_fd_to_skb(const struct dpaa_priv *priv,
1733                                     const struct qm_fd *fd)
1734 {
1735         ssize_t fd_off = qm_fd_get_offset(fd);
1736         dma_addr_t addr = qm_fd_addr(fd);
1737         const struct qm_sg_entry *sgt;
1738         struct page *page, *head_page;
1739         struct dpaa_bp *dpaa_bp;
1740         void *vaddr, *sg_vaddr;
1741         int frag_off, frag_len;
1742         struct sk_buff *skb;
1743         dma_addr_t sg_addr;
1744         int page_offset;
1745         unsigned int sz;
1746         int *count_ptr;
1747         int i;
1748 
1749         vaddr = phys_to_virt(addr);
1750         WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1751 
1752         /* Iterate through the SGT entries and add data buffers to the skb */
1753         sgt = vaddr + fd_off;
1754         skb = NULL;
1755         for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) {
1756                 /* Extension bit is not supported */
1757                 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1758 
1759                 sg_addr = qm_sg_addr(&sgt[i]);
1760                 sg_vaddr = phys_to_virt(sg_addr);
1761                 WARN_ON(!IS_ALIGNED((unsigned long)sg_vaddr,
1762                                     SMP_CACHE_BYTES));
1763 
1764                 /* We may use multiple Rx pools */
1765                 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1766                 if (!dpaa_bp)
1767                         goto free_buffers;
1768 
1769                 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1770                 dma_unmap_single(dpaa_bp->dev, sg_addr, dpaa_bp->size,
1771                                  DMA_FROM_DEVICE);
1772                 if (!skb) {
1773                         sz = dpaa_bp->size +
1774                                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1775                         skb = build_skb(sg_vaddr, sz);
1776                         if (WARN_ON(!skb))
1777                                 goto free_buffers;
1778 
1779                         skb->ip_summed = rx_csum_offload(priv, fd);
1780 
1781                         /* Make sure forwarded skbs will have enough space
1782                          * on Tx, if extra headers are added.
1783                          */
1784                         WARN_ON(fd_off != priv->rx_headroom);
1785                         skb_reserve(skb, fd_off);
1786                         skb_put(skb, qm_sg_entry_get_len(&sgt[i]));
1787                 } else {
1788                         /* Not the first S/G entry; all data from buffer will
1789                          * be added in an skb fragment; fragment index is offset
1790                          * by one since first S/G entry was incorporated in the
1791                          * linear part of the skb.
1792                          *
1793                          * Caution: 'page' may be a tail page.
1794                          */
1795                         page = virt_to_page(sg_vaddr);
1796                         head_page = virt_to_head_page(sg_vaddr);
1797 
1798                         /* Compute offset in (possibly tail) page */
1799                         page_offset = ((unsigned long)sg_vaddr &
1800                                         (PAGE_SIZE - 1)) +
1801                                 (page_address(page) - page_address(head_page));
1802                         /* page_offset only refers to the beginning of sgt[i];
1803                          * but the buffer itself may have an internal offset.
1804                          */
1805                         frag_off = qm_sg_entry_get_off(&sgt[i]) + page_offset;
1806                         frag_len = qm_sg_entry_get_len(&sgt[i]);
1807                         /* skb_add_rx_frag() does no checking on the page; if
1808                          * we pass it a tail page, we'll end up with
1809                          * bad page accounting and eventually with segafults.
1810                          */
1811                         skb_add_rx_frag(skb, i - 1, head_page, frag_off,
1812                                         frag_len, dpaa_bp->size);
1813                 }
1814                 /* Update the pool count for the current {cpu x bpool} */
1815                 (*count_ptr)--;
1816 
1817                 if (qm_sg_entry_is_final(&sgt[i]))
1818                         break;
1819         }
1820         WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n");
1821 
1822         /* free the SG table buffer */
1823         skb_free_frag(vaddr);
1824 
1825         return skb;
1826 
1827 free_buffers:
1828         /* compensate sw bpool counter changes */
1829         for (i--; i >= 0; i--) {
1830                 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1831                 if (dpaa_bp) {
1832                         count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1833                         (*count_ptr)++;
1834                 }
1835         }
1836         /* free all the SG entries */
1837         for (i = 0; i < DPAA_SGT_MAX_ENTRIES ; i++) {
1838                 sg_addr = qm_sg_addr(&sgt[i]);
1839                 sg_vaddr = phys_to_virt(sg_addr);
1840                 skb_free_frag(sg_vaddr);
1841                 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1842                 if (dpaa_bp) {
1843                         count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1844                         (*count_ptr)--;
1845                 }
1846 
1847                 if (qm_sg_entry_is_final(&sgt[i]))
1848                         break;
1849         }
1850         /* free the SGT fragment */
1851         skb_free_frag(vaddr);
1852 
1853         return NULL;
1854 }
1855 
1856 static int skb_to_contig_fd(struct dpaa_priv *priv,
1857                             struct sk_buff *skb, struct qm_fd *fd,
1858                             int *offset)
1859 {
1860         struct net_device *net_dev = priv->net_dev;
1861         struct device *dev = net_dev->dev.parent;
1862         enum dma_data_direction dma_dir;
1863         unsigned char *buffer_start;
1864         struct sk_buff **skbh;
1865         dma_addr_t addr;
1866         int err;
1867 
1868         /* We are guaranteed to have at least tx_headroom bytes
1869          * available, so just use that for offset.
1870          */
1871         fd->bpid = FSL_DPAA_BPID_INV;
1872         buffer_start = skb->data - priv->tx_headroom;
1873         dma_dir = DMA_TO_DEVICE;
1874 
1875         skbh = (struct sk_buff **)buffer_start;
1876         *skbh = skb;
1877 
1878         /* Enable L3/L4 hardware checksum computation.
1879          *
1880          * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1881          * need to write into the skb.
1882          */
1883         err = dpaa_enable_tx_csum(priv, skb, fd,
1884                                   ((char *)skbh) + DPAA_TX_PRIV_DATA_SIZE);
1885         if (unlikely(err < 0)) {
1886                 if (net_ratelimit())
1887                         netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1888                                   err);
1889                 return err;
1890         }
1891 
1892         /* Fill in the rest of the FD fields */
1893         qm_fd_set_contig(fd, priv->tx_headroom, skb->len);
1894         fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
1895 
1896         /* Map the entire buffer size that may be seen by FMan, but no more */
1897         addr = dma_map_single(dev, skbh,
1898                               skb_tail_pointer(skb) - buffer_start, dma_dir);
1899         if (unlikely(dma_mapping_error(dev, addr))) {
1900                 if (net_ratelimit())
1901                         netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n");
1902                 return -EINVAL;
1903         }
1904         qm_fd_addr_set64(fd, addr);
1905 
1906         return 0;
1907 }
1908 
1909 static int skb_to_sg_fd(struct dpaa_priv *priv,
1910                         struct sk_buff *skb, struct qm_fd *fd)
1911 {
1912         const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1913         const int nr_frags = skb_shinfo(skb)->nr_frags;
1914         struct net_device *net_dev = priv->net_dev;
1915         struct device *dev = net_dev->dev.parent;
1916         struct qm_sg_entry *sgt;
1917         struct sk_buff **skbh;
1918         int i, j, err, sz;
1919         void *buffer_start;
1920         skb_frag_t *frag;
1921         dma_addr_t addr;
1922         size_t frag_len;
1923         void *sgt_buf;
1924 
1925         /* get a page frag to store the SGTable */
1926         sz = SKB_DATA_ALIGN(priv->tx_headroom + DPAA_SGT_SIZE);
1927         sgt_buf = netdev_alloc_frag(sz);
1928         if (unlikely(!sgt_buf)) {
1929                 netdev_err(net_dev, "netdev_alloc_frag() failed for size %d\n",
1930                            sz);
1931                 return -ENOMEM;
1932         }
1933 
1934         /* Enable L3/L4 hardware checksum computation.
1935          *
1936          * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1937          * need to write into the skb.
1938          */
1939         err = dpaa_enable_tx_csum(priv, skb, fd,
1940                                   sgt_buf + DPAA_TX_PRIV_DATA_SIZE);
1941         if (unlikely(err < 0)) {
1942                 if (net_ratelimit())
1943                         netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1944                                   err);
1945                 goto csum_failed;
1946         }
1947 
1948         /* SGT[0] is used by the linear part */
1949         sgt = (struct qm_sg_entry *)(sgt_buf + priv->tx_headroom);
1950         frag_len = skb_headlen(skb);
1951         qm_sg_entry_set_len(&sgt[0], frag_len);
1952         sgt[0].bpid = FSL_DPAA_BPID_INV;
1953         sgt[0].offset = 0;
1954         addr = dma_map_single(dev, skb->data,
1955                               skb_headlen(skb), dma_dir);
1956         if (unlikely(dma_mapping_error(dev, addr))) {
1957                 dev_err(dev, "DMA mapping failed");
1958                 err = -EINVAL;
1959                 goto sg0_map_failed;
1960         }
1961         qm_sg_entry_set64(&sgt[0], addr);
1962 
1963         /* populate the rest of SGT entries */
1964         for (i = 0; i < nr_frags; i++) {
1965                 frag = &skb_shinfo(skb)->frags[i];
1966                 frag_len = skb_frag_size(frag);
1967                 WARN_ON(!skb_frag_page(frag));
1968                 addr = skb_frag_dma_map(dev, frag, 0,
1969                                         frag_len, dma_dir);
1970                 if (unlikely(dma_mapping_error(dev, addr))) {
1971                         dev_err(dev, "DMA mapping failed");
1972                         err = -EINVAL;
1973                         goto sg_map_failed;
1974                 }
1975 
1976                 qm_sg_entry_set_len(&sgt[i + 1], frag_len);
1977                 sgt[i + 1].bpid = FSL_DPAA_BPID_INV;
1978                 sgt[i + 1].offset = 0;
1979 
1980                 /* keep the offset in the address */
1981                 qm_sg_entry_set64(&sgt[i + 1], addr);
1982         }
1983 
1984         /* Set the final bit in the last used entry of the SGT */
1985         qm_sg_entry_set_f(&sgt[nr_frags], frag_len);
1986 
1987         qm_fd_set_sg(fd, priv->tx_headroom, skb->len);
1988 
1989         /* DMA map the SGT page */
1990         buffer_start = (void *)sgt - priv->tx_headroom;
1991         skbh = (struct sk_buff **)buffer_start;
1992         *skbh = skb;
1993 
1994         addr = dma_map_single(dev, buffer_start,
1995                               priv->tx_headroom + DPAA_SGT_SIZE, dma_dir);
1996         if (unlikely(dma_mapping_error(dev, addr))) {
1997                 dev_err(dev, "DMA mapping failed");
1998                 err = -EINVAL;
1999                 goto sgt_map_failed;
2000         }
2001 
2002         fd->bpid = FSL_DPAA_BPID_INV;
2003         fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
2004         qm_fd_addr_set64(fd, addr);
2005 
2006         return 0;
2007 
2008 sgt_map_failed:
2009 sg_map_failed:
2010         for (j = 0; j < i; j++)
2011                 dma_unmap_page(dev, qm_sg_addr(&sgt[j]),
2012                                qm_sg_entry_get_len(&sgt[j]), dma_dir);
2013 sg0_map_failed:
2014 csum_failed:
2015         skb_free_frag(sgt_buf);
2016 
2017         return err;
2018 }
2019 
2020 static inline int dpaa_xmit(struct dpaa_priv *priv,
2021                             struct rtnl_link_stats64 *percpu_stats,
2022                             int queue,
2023                             struct qm_fd *fd)
2024 {
2025         struct qman_fq *egress_fq;
2026         int err, i;
2027 
2028         egress_fq = priv->egress_fqs[queue];
2029         if (fd->bpid == FSL_DPAA_BPID_INV)
2030                 fd->cmd |= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue]));
2031 
2032         /* Trace this Tx fd */
2033         trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd);
2034 
2035         for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) {
2036                 err = qman_enqueue(egress_fq, fd);
2037                 if (err != -EBUSY)
2038                         break;
2039         }
2040 
2041         if (unlikely(err < 0)) {
2042                 percpu_stats->tx_fifo_errors++;
2043                 return err;
2044         }
2045 
2046         percpu_stats->tx_packets++;
2047         percpu_stats->tx_bytes += qm_fd_get_length(fd);
2048 
2049         return 0;
2050 }
2051 
2052 static netdev_tx_t
2053 dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
2054 {
2055         const int queue_mapping = skb_get_queue_mapping(skb);
2056         bool nonlinear = skb_is_nonlinear(skb);
2057         struct rtnl_link_stats64 *percpu_stats;
2058         struct dpaa_percpu_priv *percpu_priv;
2059         struct netdev_queue *txq;
2060         struct dpaa_priv *priv;
2061         struct qm_fd fd;
2062         int offset = 0;
2063         int err = 0;
2064 
2065         priv = netdev_priv(net_dev);
2066         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2067         percpu_stats = &percpu_priv->stats;
2068 
2069         qm_fd_clear_fd(&fd);
2070 
2071         if (!nonlinear) {
2072                 /* We're going to store the skb backpointer at the beginning
2073                  * of the data buffer, so we need a privately owned skb
2074                  *
2075                  * We've made sure skb is not shared in dev->priv_flags,
2076                  * we need to verify the skb head is not cloned
2077                  */
2078                 if (skb_cow_head(skb, priv->tx_headroom))
2079                         goto enomem;
2080 
2081                 WARN_ON(skb_is_nonlinear(skb));
2082         }
2083 
2084         /* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES;
2085          * make sure we don't feed FMan with more fragments than it supports.
2086          */
2087         if (unlikely(nonlinear &&
2088                      (skb_shinfo(skb)->nr_frags >= DPAA_SGT_MAX_ENTRIES))) {
2089                 /* If the egress skb contains more fragments than we support
2090                  * we have no choice but to linearize it ourselves.
2091                  */
2092                 if (__skb_linearize(skb))
2093                         goto enomem;
2094 
2095                 nonlinear = skb_is_nonlinear(skb);
2096         }
2097 
2098         if (nonlinear) {
2099                 /* Just create a S/G fd based on the skb */
2100                 err = skb_to_sg_fd(priv, skb, &fd);
2101                 percpu_priv->tx_frag_skbuffs++;
2102         } else {
2103                 /* Create a contig FD from this skb */
2104                 err = skb_to_contig_fd(priv, skb, &fd, &offset);
2105         }
2106         if (unlikely(err < 0))
2107                 goto skb_to_fd_failed;
2108 
2109         txq = netdev_get_tx_queue(net_dev, queue_mapping);
2110 
2111         /* LLTX requires to do our own update of trans_start */
2112         txq->trans_start = jiffies;
2113 
2114         if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
2115                 fd.cmd |= cpu_to_be32(FM_FD_CMD_UPD);
2116                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2117         }
2118 
2119         if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0))
2120                 return NETDEV_TX_OK;
2121 
2122         dpaa_cleanup_tx_fd(priv, &fd, false);
2123 skb_to_fd_failed:
2124 enomem:
2125         percpu_stats->tx_errors++;
2126         dev_kfree_skb(skb);
2127         return NETDEV_TX_OK;
2128 }
2129 
2130 static void dpaa_rx_error(struct net_device *net_dev,
2131                           const struct dpaa_priv *priv,
2132                           struct dpaa_percpu_priv *percpu_priv,
2133                           const struct qm_fd *fd,
2134                           u32 fqid)
2135 {
2136         if (net_ratelimit())
2137                 netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n",
2138                           be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS);
2139 
2140         percpu_priv->stats.rx_errors++;
2141 
2142         if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA)
2143                 percpu_priv->rx_errors.dme++;
2144         if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL)
2145                 percpu_priv->rx_errors.fpe++;
2146         if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE)
2147                 percpu_priv->rx_errors.fse++;
2148         if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR)
2149                 percpu_priv->rx_errors.phe++;
2150 
2151         dpaa_fd_release(net_dev, fd);
2152 }
2153 
2154 static void dpaa_tx_error(struct net_device *net_dev,
2155                           const struct dpaa_priv *priv,
2156                           struct dpaa_percpu_priv *percpu_priv,
2157                           const struct qm_fd *fd,
2158                           u32 fqid)
2159 {
2160         struct sk_buff *skb;
2161 
2162         if (net_ratelimit())
2163                 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2164                            be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS);
2165 
2166         percpu_priv->stats.tx_errors++;
2167 
2168         skb = dpaa_cleanup_tx_fd(priv, fd, false);
2169         dev_kfree_skb(skb);
2170 }
2171 
2172 static int dpaa_eth_poll(struct napi_struct *napi, int budget)
2173 {
2174         struct dpaa_napi_portal *np =
2175                         container_of(napi, struct dpaa_napi_portal, napi);
2176 
2177         int cleaned = qman_p_poll_dqrr(np->p, budget);
2178 
2179         if (cleaned < budget) {
2180                 napi_complete_done(napi, cleaned);
2181                 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2182         } else if (np->down) {
2183                 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2184         }
2185 
2186         return cleaned;
2187 }
2188 
2189 static void dpaa_tx_conf(struct net_device *net_dev,
2190                          const struct dpaa_priv *priv,
2191                          struct dpaa_percpu_priv *percpu_priv,
2192                          const struct qm_fd *fd,
2193                          u32 fqid)
2194 {
2195         struct sk_buff  *skb;
2196 
2197         if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) {
2198                 if (net_ratelimit())
2199                         netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2200                                    be32_to_cpu(fd->status) &
2201                                    FM_FD_STAT_TX_ERRORS);
2202 
2203                 percpu_priv->stats.tx_errors++;
2204         }
2205 
2206         percpu_priv->tx_confirm++;
2207 
2208         skb = dpaa_cleanup_tx_fd(priv, fd, true);
2209 
2210         consume_skb(skb);
2211 }
2212 
2213 static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv,
2214                                          struct qman_portal *portal)
2215 {
2216         if (unlikely(in_irq() || !in_serving_softirq())) {
2217                 /* Disable QMan IRQ and invoke NAPI */
2218                 qman_p_irqsource_remove(portal, QM_PIRQ_DQRI);
2219 
2220                 percpu_priv->np.p = portal;
2221                 napi_schedule(&percpu_priv->np.napi);
2222                 percpu_priv->in_interrupt++;
2223                 return 1;
2224         }
2225         return 0;
2226 }
2227 
2228 static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal,
2229                                               struct qman_fq *fq,
2230                                               const struct qm_dqrr_entry *dq)
2231 {
2232         struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
2233         struct dpaa_percpu_priv *percpu_priv;
2234         struct net_device *net_dev;
2235         struct dpaa_bp *dpaa_bp;
2236         struct dpaa_priv *priv;
2237 
2238         net_dev = dpaa_fq->net_dev;
2239         priv = netdev_priv(net_dev);
2240         dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2241         if (!dpaa_bp)
2242                 return qman_cb_dqrr_consume;
2243 
2244         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2245 
2246         if (dpaa_eth_napi_schedule(percpu_priv, portal))
2247                 return qman_cb_dqrr_stop;
2248 
2249         dpaa_eth_refill_bpools(priv);
2250         dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2251 
2252         return qman_cb_dqrr_consume;
2253 }
2254 
2255 static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal,
2256                                                 struct qman_fq *fq,
2257                                                 const struct qm_dqrr_entry *dq)
2258 {
2259         struct skb_shared_hwtstamps *shhwtstamps;
2260         struct rtnl_link_stats64 *percpu_stats;
2261         struct dpaa_percpu_priv *percpu_priv;
2262         const struct qm_fd *fd = &dq->fd;
2263         dma_addr_t addr = qm_fd_addr(fd);
2264         enum qm_fd_format fd_format;
2265         struct net_device *net_dev;
2266         u32 fd_status, hash_offset;
2267         struct dpaa_bp *dpaa_bp;
2268         struct dpaa_priv *priv;
2269         unsigned int skb_len;
2270         struct sk_buff *skb;
2271         int *count_ptr;
2272         void *vaddr;
2273         u64 ns;
2274 
2275         fd_status = be32_to_cpu(fd->status);
2276         fd_format = qm_fd_get_format(fd);
2277         net_dev = ((struct dpaa_fq *)fq)->net_dev;
2278         priv = netdev_priv(net_dev);
2279         dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2280         if (!dpaa_bp)
2281                 return qman_cb_dqrr_consume;
2282 
2283         /* Trace the Rx fd */
2284         trace_dpaa_rx_fd(net_dev, fq, &dq->fd);
2285 
2286         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2287         percpu_stats = &percpu_priv->stats;
2288 
2289         if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal)))
2290                 return qman_cb_dqrr_stop;
2291 
2292         /* Make sure we didn't run out of buffers */
2293         if (unlikely(dpaa_eth_refill_bpools(priv))) {
2294                 /* Unable to refill the buffer pool due to insufficient
2295                  * system memory. Just release the frame back into the pool,
2296                  * otherwise we'll soon end up with an empty buffer pool.
2297                  */
2298                 dpaa_fd_release(net_dev, &dq->fd);
2299                 return qman_cb_dqrr_consume;
2300         }
2301 
2302         if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) {
2303                 if (net_ratelimit())
2304                         netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2305                                    fd_status & FM_FD_STAT_RX_ERRORS);
2306 
2307                 percpu_stats->rx_errors++;
2308                 dpaa_fd_release(net_dev, fd);
2309                 return qman_cb_dqrr_consume;
2310         }
2311 
2312         dpaa_bp = dpaa_bpid2pool(fd->bpid);
2313         if (!dpaa_bp)
2314                 return qman_cb_dqrr_consume;
2315 
2316         dma_unmap_single(dpaa_bp->dev, addr, dpaa_bp->size, DMA_FROM_DEVICE);
2317 
2318         /* prefetch the first 64 bytes of the frame or the SGT start */
2319         vaddr = phys_to_virt(addr);
2320         prefetch(vaddr + qm_fd_get_offset(fd));
2321 
2322         /* The only FD types that we may receive are contig and S/G */
2323         WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg));
2324 
2325         /* Account for either the contig buffer or the SGT buffer (depending on
2326          * which case we were in) having been removed from the pool.
2327          */
2328         count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
2329         (*count_ptr)--;
2330 
2331         if (likely(fd_format == qm_fd_contig))
2332                 skb = contig_fd_to_skb(priv, fd);
2333         else
2334                 skb = sg_fd_to_skb(priv, fd);
2335         if (!skb)
2336                 return qman_cb_dqrr_consume;
2337 
2338         if (priv->rx_tstamp) {
2339                 shhwtstamps = skb_hwtstamps(skb);
2340                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2341 
2342                 if (!fman_port_get_tstamp(priv->mac_dev->port[RX], vaddr, &ns))
2343                         shhwtstamps->hwtstamp = ns_to_ktime(ns);
2344                 else
2345                         dev_warn(net_dev->dev.parent, "fman_port_get_tstamp failed!\n");
2346         }
2347 
2348         skb->protocol = eth_type_trans(skb, net_dev);
2349 
2350         if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use &&
2351             !fman_port_get_hash_result_offset(priv->mac_dev->port[RX],
2352                                               &hash_offset)) {
2353                 enum pkt_hash_types type;
2354 
2355                 /* if L4 exists, it was used in the hash generation */
2356                 type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ?
2357                         PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
2358                 skb_set_hash(skb, be32_to_cpu(*(u32 *)(vaddr + hash_offset)),
2359                              type);
2360         }
2361 
2362         skb_len = skb->len;
2363 
2364         if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) {
2365                 percpu_stats->rx_dropped++;
2366                 return qman_cb_dqrr_consume;
2367         }
2368 
2369         percpu_stats->rx_packets++;
2370         percpu_stats->rx_bytes += skb_len;
2371 
2372         return qman_cb_dqrr_consume;
2373 }
2374 
2375 static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal,
2376                                                 struct qman_fq *fq,
2377                                                 const struct qm_dqrr_entry *dq)
2378 {
2379         struct dpaa_percpu_priv *percpu_priv;
2380         struct net_device *net_dev;
2381         struct dpaa_priv *priv;
2382 
2383         net_dev = ((struct dpaa_fq *)fq)->net_dev;
2384         priv = netdev_priv(net_dev);
2385 
2386         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2387 
2388         if (dpaa_eth_napi_schedule(percpu_priv, portal))
2389                 return qman_cb_dqrr_stop;
2390 
2391         dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2392 
2393         return qman_cb_dqrr_consume;
2394 }
2395 
2396 static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal,
2397                                                struct qman_fq *fq,
2398                                                const struct qm_dqrr_entry *dq)
2399 {
2400         struct dpaa_percpu_priv *percpu_priv;
2401         struct net_device *net_dev;
2402         struct dpaa_priv *priv;
2403 
2404         net_dev = ((struct dpaa_fq *)fq)->net_dev;
2405         priv = netdev_priv(net_dev);
2406 
2407         /* Trace the fd */
2408         trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd);
2409 
2410         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2411 
2412         if (dpaa_eth_napi_schedule(percpu_priv, portal))
2413                 return qman_cb_dqrr_stop;
2414 
2415         dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2416 
2417         return qman_cb_dqrr_consume;
2418 }
2419 
2420 static void egress_ern(struct qman_portal *portal,
2421                        struct qman_fq *fq,
2422                        const union qm_mr_entry *msg)
2423 {
2424         const struct qm_fd *fd = &msg->ern.fd;
2425         struct dpaa_percpu_priv *percpu_priv;
2426         const struct dpaa_priv *priv;
2427         struct net_device *net_dev;
2428         struct sk_buff *skb;
2429 
2430         net_dev = ((struct dpaa_fq *)fq)->net_dev;
2431         priv = netdev_priv(net_dev);
2432         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2433 
2434         percpu_priv->stats.tx_dropped++;
2435         percpu_priv->stats.tx_fifo_errors++;
2436         count_ern(percpu_priv, msg);
2437 
2438         skb = dpaa_cleanup_tx_fd(priv, fd, false);
2439         dev_kfree_skb_any(skb);
2440 }
2441 
2442 static const struct dpaa_fq_cbs dpaa_fq_cbs = {
2443         .rx_defq = { .cb = { .dqrr = rx_default_dqrr } },
2444         .tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } },
2445         .rx_errq = { .cb = { .dqrr = rx_error_dqrr } },
2446         .tx_errq = { .cb = { .dqrr = conf_error_dqrr } },
2447         .egress_ern = { .cb = { .ern = egress_ern } }
2448 };
2449 
2450 static void dpaa_eth_napi_enable(struct dpaa_priv *priv)
2451 {
2452         struct dpaa_percpu_priv *percpu_priv;
2453         int i;
2454 
2455         for_each_online_cpu(i) {
2456                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2457 
2458                 percpu_priv->np.down = 0;
2459                 napi_enable(&percpu_priv->np.napi);
2460         }
2461 }
2462 
2463 static void dpaa_eth_napi_disable(struct dpaa_priv *priv)
2464 {
2465         struct dpaa_percpu_priv *percpu_priv;
2466         int i;
2467 
2468         for_each_online_cpu(i) {
2469                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2470 
2471                 percpu_priv->np.down = 1;
2472                 napi_disable(&percpu_priv->np.napi);
2473         }
2474 }
2475 
2476 static void dpaa_adjust_link(struct net_device *net_dev)
2477 {
2478         struct mac_device *mac_dev;
2479         struct dpaa_priv *priv;
2480 
2481         priv = netdev_priv(net_dev);
2482         mac_dev = priv->mac_dev;
2483         mac_dev->adjust_link(mac_dev);
2484 }
2485 
2486 /* The Aquantia PHYs are capable of performing rate adaptation */
2487 #define PHY_VEND_AQUANTIA       0x03a1b400
2488 
2489 static int dpaa_phy_init(struct net_device *net_dev)
2490 {
2491         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
2492         struct mac_device *mac_dev;
2493         struct phy_device *phy_dev;
2494         struct dpaa_priv *priv;
2495 
2496         priv = netdev_priv(net_dev);
2497         mac_dev = priv->mac_dev;
2498 
2499         phy_dev = of_phy_connect(net_dev, mac_dev->phy_node,
2500                                  &dpaa_adjust_link, 0,
2501                                  mac_dev->phy_if);
2502         if (!phy_dev) {
2503                 netif_err(priv, ifup, net_dev, "init_phy() failed\n");
2504                 return -ENODEV;
2505         }
2506 
2507         /* Unless the PHY is capable of rate adaptation */
2508         if (mac_dev->phy_if != PHY_INTERFACE_MODE_XGMII ||
2509             ((phy_dev->drv->phy_id & GENMASK(31, 10)) != PHY_VEND_AQUANTIA)) {
2510                 /* remove any features not supported by the controller */
2511                 ethtool_convert_legacy_u32_to_link_mode(mask,
2512                                                         mac_dev->if_support);
2513                 linkmode_and(phy_dev->supported, phy_dev->supported, mask);
2514         }
2515 
2516         phy_support_asym_pause(phy_dev);
2517 
2518         mac_dev->phy_dev = phy_dev;
2519         net_dev->phydev = phy_dev;
2520 
2521         return 0;
2522 }
2523 
2524 static int dpaa_open(struct net_device *net_dev)
2525 {
2526         struct mac_device *mac_dev;
2527         struct dpaa_priv *priv;
2528         int err, i;
2529 
2530         priv = netdev_priv(net_dev);
2531         mac_dev = priv->mac_dev;
2532         dpaa_eth_napi_enable(priv);
2533 
2534         err = dpaa_phy_init(net_dev);
2535         if (err)
2536                 goto phy_init_failed;
2537 
2538         for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
2539                 err = fman_port_enable(mac_dev->port[i]);
2540                 if (err)
2541                         goto mac_start_failed;
2542         }
2543 
2544         err = priv->mac_dev->start(mac_dev);
2545         if (err < 0) {
2546                 netif_err(priv, ifup, net_dev, "mac_dev->start() = %d\n", err);
2547                 goto mac_start_failed;
2548         }
2549 
2550         netif_tx_start_all_queues(net_dev);
2551 
2552         return 0;
2553 
2554 mac_start_failed:
2555         for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
2556                 fman_port_disable(mac_dev->port[i]);
2557 
2558 phy_init_failed:
2559         dpaa_eth_napi_disable(priv);
2560 
2561         return err;
2562 }
2563 
2564 static int dpaa_eth_stop(struct net_device *net_dev)
2565 {
2566         struct dpaa_priv *priv;
2567         int err;
2568 
2569         err = dpaa_stop(net_dev);
2570 
2571         priv = netdev_priv(net_dev);
2572         dpaa_eth_napi_disable(priv);
2573 
2574         return err;
2575 }
2576 
2577 static int dpaa_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2578 {
2579         struct dpaa_priv *priv = netdev_priv(dev);
2580         struct hwtstamp_config config;
2581 
2582         if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
2583                 return -EFAULT;
2584 
2585         switch (config.tx_type) {
2586         case HWTSTAMP_TX_OFF:
2587                 /* Couldn't disable rx/tx timestamping separately.
2588                  * Do nothing here.
2589                  */
2590                 priv->tx_tstamp = false;
2591                 break;
2592         case HWTSTAMP_TX_ON:
2593                 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true);
2594                 priv->tx_tstamp = true;
2595                 break;
2596         default:
2597                 return -ERANGE;
2598         }
2599 
2600         if (config.rx_filter == HWTSTAMP_FILTER_NONE) {
2601                 /* Couldn't disable rx/tx timestamping separately.
2602                  * Do nothing here.
2603                  */
2604                 priv->rx_tstamp = false;
2605         } else {
2606                 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true);
2607                 priv->rx_tstamp = true;
2608                 /* TS is set for all frame types, not only those requested */
2609                 config.rx_filter = HWTSTAMP_FILTER_ALL;
2610         }
2611 
2612         return copy_to_user(rq->ifr_data, &config, sizeof(config)) ?
2613                         -EFAULT : 0;
2614 }
2615 
2616 static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
2617 {
2618         int ret = -EINVAL;
2619 
2620         if (cmd == SIOCGMIIREG) {
2621                 if (net_dev->phydev)
2622                         return phy_mii_ioctl(net_dev->phydev, rq, cmd);
2623         }
2624 
2625         if (cmd == SIOCSHWTSTAMP)
2626                 return dpaa_ts_ioctl(net_dev, rq, cmd);
2627 
2628         return ret;
2629 }
2630 
2631 static const struct net_device_ops dpaa_ops = {
2632         .ndo_open = dpaa_open,
2633         .ndo_start_xmit = dpaa_start_xmit,
2634         .ndo_stop = dpaa_eth_stop,
2635         .ndo_tx_timeout = dpaa_tx_timeout,
2636         .ndo_get_stats64 = dpaa_get_stats64,
2637         .ndo_change_carrier = fixed_phy_change_carrier,
2638         .ndo_set_mac_address = dpaa_set_mac_address,
2639         .ndo_validate_addr = eth_validate_addr,
2640         .ndo_set_rx_mode = dpaa_set_rx_mode,
2641         .ndo_do_ioctl = dpaa_ioctl,
2642         .ndo_setup_tc = dpaa_setup_tc,
2643 };
2644 
2645 static int dpaa_napi_add(struct net_device *net_dev)
2646 {
2647         struct dpaa_priv *priv = netdev_priv(net_dev);
2648         struct dpaa_percpu_priv *percpu_priv;
2649         int cpu;
2650 
2651         for_each_possible_cpu(cpu) {
2652                 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
2653 
2654                 netif_napi_add(net_dev, &percpu_priv->np.napi,
2655                                dpaa_eth_poll, NAPI_POLL_WEIGHT);
2656         }
2657 
2658         return 0;
2659 }
2660 
2661 static void dpaa_napi_del(struct net_device *net_dev)
2662 {
2663         struct dpaa_priv *priv = netdev_priv(net_dev);
2664         struct dpaa_percpu_priv *percpu_priv;
2665         int cpu;
2666 
2667         for_each_possible_cpu(cpu) {
2668                 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
2669 
2670                 netif_napi_del(&percpu_priv->np.napi);
2671         }
2672 }
2673 
2674 static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp,
2675                                    struct bm_buffer *bmb)
2676 {
2677         dma_addr_t addr = bm_buf_addr(bmb);
2678 
2679         dma_unmap_single(bp->dev, addr, bp->size, DMA_FROM_DEVICE);
2680 
2681         skb_free_frag(phys_to_virt(addr));
2682 }
2683 
2684 /* Alloc the dpaa_bp struct and configure default values */
2685 static struct dpaa_bp *dpaa_bp_alloc(struct device *dev)
2686 {
2687         struct dpaa_bp *dpaa_bp;
2688 
2689         dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL);
2690         if (!dpaa_bp)
2691                 return ERR_PTR(-ENOMEM);
2692 
2693         dpaa_bp->bpid = FSL_DPAA_BPID_INV;
2694         dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count);
2695         if (!dpaa_bp->percpu_count)
2696                 return ERR_PTR(-ENOMEM);
2697 
2698         dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT;
2699 
2700         dpaa_bp->seed_cb = dpaa_bp_seed;
2701         dpaa_bp->free_buf_cb = dpaa_bp_free_pf;
2702 
2703         return dpaa_bp;
2704 }
2705 
2706 /* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR.
2707  * We won't be sending congestion notifications to FMan; for now, we just use
2708  * this CGR to generate enqueue rejections to FMan in order to drop the frames
2709  * before they reach our ingress queues and eat up memory.
2710  */
2711 static int dpaa_ingress_cgr_init(struct dpaa_priv *priv)
2712 {
2713         struct qm_mcc_initcgr initcgr;
2714         u32 cs_th;
2715         int err;
2716 
2717         err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid);
2718         if (err < 0) {
2719                 if (netif_msg_drv(priv))
2720                         pr_err("Error %d allocating CGR ID\n", err);
2721                 goto out_error;
2722         }
2723 
2724         /* Enable CS TD, but disable Congestion State Change Notifications. */
2725         memset(&initcgr, 0, sizeof(initcgr));
2726         initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES);
2727         initcgr.cgr.cscn_en = QM_CGR_EN;
2728         cs_th = DPAA_INGRESS_CS_THRESHOLD;
2729         qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
2730 
2731         initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
2732         initcgr.cgr.cstd_en = QM_CGR_EN;
2733 
2734         /* This CGR will be associated with the SWP affined to the current CPU.
2735          * However, we'll place all our ingress FQs in it.
2736          */
2737         err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT,
2738                               &initcgr);
2739         if (err < 0) {
2740                 if (netif_msg_drv(priv))
2741                         pr_err("Error %d creating ingress CGR with ID %d\n",
2742                                err, priv->ingress_cgr.cgrid);
2743                 qman_release_cgrid(priv->ingress_cgr.cgrid);
2744                 goto out_error;
2745         }
2746         if (netif_msg_drv(priv))
2747                 pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n",
2748                          priv->ingress_cgr.cgrid, priv->mac_dev->addr);
2749 
2750         priv->use_ingress_cgr = true;
2751 
2752 out_error:
2753         return err;
2754 }
2755 
2756 static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl)
2757 {
2758         u16 headroom;
2759 
2760         /* The frame headroom must accommodate:
2761          * - the driver private data area
2762          * - parse results, hash results, timestamp if selected
2763          * If either hash results or time stamp are selected, both will
2764          * be copied to/from the frame headroom, as TS is located between PR and
2765          * HR in the IC and IC copy size has a granularity of 16bytes
2766          * (see description of FMBM_RICP and FMBM_TICP registers in DPAARM)
2767          *
2768          * Also make sure the headroom is a multiple of data_align bytes
2769          */
2770         headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE +
2771                 DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE);
2772 
2773         return ALIGN(headroom, DPAA_FD_DATA_ALIGNMENT);
2774 }
2775 
2776 static int dpaa_eth_probe(struct platform_device *pdev)
2777 {
2778         struct dpaa_bp *dpaa_bps[DPAA_BPS_NUM] = {NULL};
2779         struct net_device *net_dev = NULL;
2780         struct dpaa_fq *dpaa_fq, *tmp;
2781         struct dpaa_priv *priv = NULL;
2782         struct fm_port_fqs port_fqs;
2783         struct mac_device *mac_dev;
2784         int err = 0, i, channel;
2785         struct device *dev;
2786 
2787         /* device used for DMA mapping */
2788         dev = pdev->dev.parent;
2789         err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(40));
2790         if (err) {
2791                 dev_err(dev, "dma_coerce_mask_and_coherent() failed\n");
2792                 return err;
2793         }
2794 
2795         /* Allocate this early, so we can store relevant information in
2796          * the private area
2797          */
2798         net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TXQ_NUM);
2799         if (!net_dev) {
2800                 dev_err(dev, "alloc_etherdev_mq() failed\n");
2801                 return -ENOMEM;
2802         }
2803 
2804         /* Do this here, so we can be verbose early */
2805         SET_NETDEV_DEV(net_dev, dev->parent);
2806         dev_set_drvdata(dev, net_dev);
2807 
2808         priv = netdev_priv(net_dev);
2809         priv->net_dev = net_dev;
2810 
2811         priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT);
2812 
2813         mac_dev = dpaa_mac_dev_get(pdev);
2814         if (IS_ERR(mac_dev)) {
2815                 dev_err(dev, "dpaa_mac_dev_get() failed\n");
2816                 err = PTR_ERR(mac_dev);
2817                 goto free_netdev;
2818         }
2819 
2820         /* If fsl_fm_max_frm is set to a higher value than the all-common 1500,
2821          * we choose conservatively and let the user explicitly set a higher
2822          * MTU via ifconfig. Otherwise, the user may end up with different MTUs
2823          * in the same LAN.
2824          * If on the other hand fsl_fm_max_frm has been chosen below 1500,
2825          * start with the maximum allowed.
2826          */
2827         net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN);
2828 
2829         netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n",
2830                    net_dev->mtu);
2831 
2832         priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */
2833         priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */
2834 
2835         /* bp init */
2836         for (i = 0; i < DPAA_BPS_NUM; i++) {
2837                 dpaa_bps[i] = dpaa_bp_alloc(dev);
2838                 if (IS_ERR(dpaa_bps[i])) {
2839                         err = PTR_ERR(dpaa_bps[i]);
2840                         goto free_dpaa_bps;
2841                 }
2842                 /* the raw size of the buffers used for reception */
2843                 dpaa_bps[i]->raw_size = bpool_buffer_raw_size(i, DPAA_BPS_NUM);
2844                 /* avoid runtime computations by keeping the usable size here */
2845                 dpaa_bps[i]->size = dpaa_bp_size(dpaa_bps[i]->raw_size);
2846                 dpaa_bps[i]->dev = dev;
2847 
2848                 err = dpaa_bp_alloc_pool(dpaa_bps[i]);
2849                 if (err < 0)
2850                         goto free_dpaa_bps;
2851                 priv->dpaa_bps[i] = dpaa_bps[i];
2852         }
2853 
2854         INIT_LIST_HEAD(&priv->dpaa_fq_list);
2855 
2856         memset(&port_fqs, 0, sizeof(port_fqs));
2857 
2858         err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs);
2859         if (err < 0) {
2860                 dev_err(dev, "dpaa_alloc_all_fqs() failed\n");
2861                 goto free_dpaa_bps;
2862         }
2863 
2864         priv->mac_dev = mac_dev;
2865 
2866         channel = dpaa_get_channel();
2867         if (channel < 0) {
2868                 dev_err(dev, "dpaa_get_channel() failed\n");
2869                 err = channel;
2870                 goto free_dpaa_bps;
2871         }
2872 
2873         priv->channel = (u16)channel;
2874 
2875         /* Walk the CPUs with affine portals
2876          * and add this pool channel to each's dequeue mask.
2877          */
2878         dpaa_eth_add_channel(priv->channel);
2879 
2880         dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]);
2881 
2882         /* Create a congestion group for this netdev, with
2883          * dynamically-allocated CGR ID.
2884          * Must be executed after probing the MAC, but before
2885          * assigning the egress FQs to the CGRs.
2886          */
2887         err = dpaa_eth_cgr_init(priv);
2888         if (err < 0) {
2889                 dev_err(dev, "Error initializing CGR\n");
2890                 goto free_dpaa_bps;
2891         }
2892 
2893         err = dpaa_ingress_cgr_init(priv);
2894         if (err < 0) {
2895                 dev_err(dev, "Error initializing ingress CGR\n");
2896                 goto delete_egress_cgr;
2897         }
2898 
2899         /* Add the FQs to the interface, and make them active */
2900         list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) {
2901                 err = dpaa_fq_init(dpaa_fq, false);
2902                 if (err < 0)
2903                         goto free_dpaa_fqs;
2904         }
2905 
2906         priv->tx_headroom = dpaa_get_headroom(&priv->buf_layout[TX]);
2907         priv->rx_headroom = dpaa_get_headroom(&priv->buf_layout[RX]);
2908 
2909         /* All real interfaces need their ports initialized */
2910         err = dpaa_eth_init_ports(mac_dev, dpaa_bps, DPAA_BPS_NUM, &port_fqs,
2911                                   &priv->buf_layout[0], dev);
2912         if (err)
2913                 goto free_dpaa_fqs;
2914 
2915         /* Rx traffic distribution based on keygen hashing defaults to on */
2916         priv->keygen_in_use = true;
2917 
2918         priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv);
2919         if (!priv->percpu_priv) {
2920                 dev_err(dev, "devm_alloc_percpu() failed\n");
2921                 err = -ENOMEM;
2922                 goto free_dpaa_fqs;
2923         }
2924 
2925         priv->num_tc = 1;
2926         netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
2927 
2928         /* Initialize NAPI */
2929         err = dpaa_napi_add(net_dev);
2930         if (err < 0)
2931                 goto delete_dpaa_napi;
2932 
2933         err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout);
2934         if (err < 0)
2935                 goto delete_dpaa_napi;
2936 
2937         dpaa_eth_sysfs_init(&net_dev->dev);
2938 
2939         netif_info(priv, probe, net_dev, "Probed interface %s\n",
2940                    net_dev->name);
2941 
2942         return 0;
2943 
2944 delete_dpaa_napi:
2945         dpaa_napi_del(net_dev);
2946 free_dpaa_fqs:
2947         dpaa_fq_free(dev, &priv->dpaa_fq_list);
2948         qman_delete_cgr_safe(&priv->ingress_cgr);
2949         qman_release_cgrid(priv->ingress_cgr.cgrid);
2950 delete_egress_cgr:
2951         qman_delete_cgr_safe(&priv->cgr_data.cgr);
2952         qman_release_cgrid(priv->cgr_data.cgr.cgrid);
2953 free_dpaa_bps:
2954         dpaa_bps_free(priv);
2955 free_netdev:
2956         dev_set_drvdata(dev, NULL);
2957         free_netdev(net_dev);
2958 
2959         return err;
2960 }
2961 
2962 static int dpaa_remove(struct platform_device *pdev)
2963 {
2964         struct net_device *net_dev;
2965         struct dpaa_priv *priv;
2966         struct device *dev;
2967         int err;
2968 
2969         dev = pdev->dev.parent;
2970         net_dev = dev_get_drvdata(dev);
2971 
2972         priv = netdev_priv(net_dev);
2973 
2974         dpaa_eth_sysfs_remove(dev);
2975 
2976         dev_set_drvdata(dev, NULL);
2977         unregister_netdev(net_dev);
2978 
2979         err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
2980 
2981         qman_delete_cgr_safe(&priv->ingress_cgr);
2982         qman_release_cgrid(priv->ingress_cgr.cgrid);
2983         qman_delete_cgr_safe(&priv->cgr_data.cgr);
2984         qman_release_cgrid(priv->cgr_data.cgr.cgrid);
2985 
2986         dpaa_napi_del(net_dev);
2987 
2988         dpaa_bps_free(priv);
2989 
2990         free_netdev(net_dev);
2991 
2992         return err;
2993 }
2994 
2995 static const struct platform_device_id dpaa_devtype[] = {
2996         {
2997                 .name = "dpaa-ethernet",
2998                 .driver_data = 0,
2999         }, {
3000         }
3001 };
3002 MODULE_DEVICE_TABLE(platform, dpaa_devtype);
3003 
3004 static struct platform_driver dpaa_driver = {
3005         .driver = {
3006                 .name = KBUILD_MODNAME,
3007         },
3008         .id_table = dpaa_devtype,
3009         .probe = dpaa_eth_probe,
3010         .remove = dpaa_remove
3011 };
3012 
3013 static int __init dpaa_load(void)
3014 {
3015         int err;
3016 
3017         pr_debug("FSL DPAA Ethernet driver\n");
3018 
3019         /* initialize dpaa_eth mirror values */
3020         dpaa_rx_extra_headroom = fman_get_rx_extra_headroom();
3021         dpaa_max_frm = fman_get_max_frm();
3022 
3023         err = platform_driver_register(&dpaa_driver);
3024         if (err < 0)
3025                 pr_err("Error, platform_driver_register() = %d\n", err);
3026 
3027         return err;
3028 }
3029 module_init(dpaa_load);
3030 
3031 static void __exit dpaa_unload(void)
3032 {
3033         platform_driver_unregister(&dpaa_driver);
3034 
3035         /* Only one channel is used and needs to be released after all
3036          * interfaces are removed
3037          */
3038         dpaa_release_channel();
3039 }
3040 module_exit(dpaa_unload);
3041 
3042 MODULE_LICENSE("Dual BSD/GPL");
3043 MODULE_DESCRIPTION("FSL DPAA Ethernet driver");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c

DEFINITIONS
