This source file includes following definitions.
- gfar_init_rxbdp
- gfar_init_tx_rx_base
- gfar_init_rqprm
- gfar_rx_offload_en
- gfar_mac_rx_config
- gfar_mac_tx_config
- gfar_configure_coalescing
- gfar_configure_coalescing_all
- gfar_get_stats
- gfar_set_hash_for_addr
- gfar_set_mac_for_addr
- gfar_set_mac_addr
- gfar_ints_disable
- gfar_ints_enable
- gfar_alloc_tx_queues
- gfar_alloc_rx_queues
- gfar_free_tx_queues
- gfar_free_rx_queues
- unmap_group_regs
- free_gfar_dev
- disable_napi
- enable_napi
- gfar_parse_group
- gfar_of_group_count
- gfar_get_interface
- gfar_of_init
- cluster_entry_per_class
- gfar_init_filer_table
- __gfar_detect_errata_83xx
- __gfar_detect_errata_85xx
- gfar_detect_errata
- gfar_init_addr_hash_table
- __gfar_is_rx_idle
- gfar_halt_nodisable
- gfar_halt
- free_skb_tx_queue
- free_skb_rx_queue
- free_skb_resources
- stop_gfar
- gfar_start
- gfar_new_page
- gfar_rx_alloc_err
- gfar_alloc_rx_buffs
- gfar_init_bds
- gfar_alloc_skb_resources
- startup_gfar
- gfar_get_flowctrl_cfg
- gfar_update_link_state
- adjust_link
- gfar_configure_serdes
- init_phy
- gfar_add_fcb
- gfar_tx_checksum
- gfar_tx_vlan
- skip_txbd
- next_txbd
- gfar_csum_errata_12
- gfar_csum_errata_76
- gfar_start_xmit
- gfar_set_mac_address
- gfar_change_mtu
- reset_gfar
- gfar_reset_task
- gfar_timeout
- gfar_hwtstamp_set
- gfar_hwtstamp_get
- gfar_ioctl
- gfar_clean_tx_ring
- count_errors
- gfar_receive
- gfar_transmit
- gfar_add_rx_frag
- gfar_reuse_rx_page
- gfar_get_next_rxbuff
- gfar_rx_checksum
- gfar_process_frame
- gfar_clean_rx_ring
- gfar_poll_rx_sq
- gfar_poll_tx_sq
- gfar_poll_rx
- gfar_poll_tx
- gfar_error
- gfar_interrupt
- gfar_netpoll
- free_grp_irqs
- register_grp_irqs
- gfar_free_irq
- gfar_request_irq
- gfar_enet_open
- gfar_close
- gfar_clear_exact_match
- gfar_set_multi
- gfar_mac_reset
- gfar_hw_init
- gfar_probe
- gfar_remove
- __gfar_filer_disable
- __gfar_filer_enable
- gfar_filer_config_wol
- gfar_filer_restore_table
- gfar_start_wol_filer
- gfar_suspend
- gfar_resume
- gfar_restore
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60 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
61 #define DEBUG
62
63 #include <linux/kernel.h>
64 #include <linux/string.h>
65 #include <linux/errno.h>
66 #include <linux/unistd.h>
67 #include <linux/slab.h>
68 #include <linux/interrupt.h>
69 #include <linux/delay.h>
70 #include <linux/netdevice.h>
71 #include <linux/etherdevice.h>
72 #include <linux/skbuff.h>
73 #include <linux/if_vlan.h>
74 #include <linux/spinlock.h>
75 #include <linux/mm.h>
76 #include <linux/of_address.h>
77 #include <linux/of_irq.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
80 #include <linux/ip.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
83 #include <linux/in.h>
84 #include <linux/net_tstamp.h>
85
86 #include <asm/io.h>
87 #ifdef CONFIG_PPC
88 #include <asm/reg.h>
89 #include <asm/mpc85xx.h>
90 #endif
91 #include <asm/irq.h>
92 #include <linux/uaccess.h>
93 #include <linux/module.h>
94 #include <linux/dma-mapping.h>
95 #include <linux/crc32.h>
96 #include <linux/mii.h>
97 #include <linux/phy.h>
98 #include <linux/phy_fixed.h>
99 #include <linux/of.h>
100 #include <linux/of_net.h>
101
102 #include "gianfar.h"
103
104 #define TX_TIMEOUT (5*HZ)
105
106 const char gfar_driver_version[] = "2.0";
107
108 MODULE_AUTHOR("Freescale Semiconductor, Inc");
109 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
110 MODULE_LICENSE("GPL");
111
112 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
113 dma_addr_t buf)
114 {
115 u32 lstatus;
116
117 bdp->bufPtr = cpu_to_be32(buf);
118
119 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
120 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
121 lstatus |= BD_LFLAG(RXBD_WRAP);
122
123 gfar_wmb();
124
125 bdp->lstatus = cpu_to_be32(lstatus);
126 }
127
128 static void gfar_init_tx_rx_base(struct gfar_private *priv)
129 {
130 struct gfar __iomem *regs = priv->gfargrp[0].regs;
131 u32 __iomem *baddr;
132 int i;
133
134 baddr = ®s->tbase0;
135 for (i = 0; i < priv->num_tx_queues; i++) {
136 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
137 baddr += 2;
138 }
139
140 baddr = ®s->rbase0;
141 for (i = 0; i < priv->num_rx_queues; i++) {
142 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
143 baddr += 2;
144 }
145 }
146
147 static void gfar_init_rqprm(struct gfar_private *priv)
148 {
149 struct gfar __iomem *regs = priv->gfargrp[0].regs;
150 u32 __iomem *baddr;
151 int i;
152
153 baddr = ®s->rqprm0;
154 for (i = 0; i < priv->num_rx_queues; i++) {
155 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
156 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
157 baddr++;
158 }
159 }
160
161 static void gfar_rx_offload_en(struct gfar_private *priv)
162 {
163
164 priv->uses_rxfcb = 0;
165
166 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
167 priv->uses_rxfcb = 1;
168
169 if (priv->hwts_rx_en || priv->rx_filer_enable)
170 priv->uses_rxfcb = 1;
171 }
172
173 static void gfar_mac_rx_config(struct gfar_private *priv)
174 {
175 struct gfar __iomem *regs = priv->gfargrp[0].regs;
176 u32 rctrl = 0;
177
178 if (priv->rx_filer_enable) {
179 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
180
181 if (priv->poll_mode == GFAR_SQ_POLLING)
182 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
183 else
184 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
185 }
186
187
188 if (priv->ndev->flags & IFF_PROMISC)
189 rctrl |= RCTRL_PROM;
190
191 if (priv->ndev->features & NETIF_F_RXCSUM)
192 rctrl |= RCTRL_CHECKSUMMING;
193
194 if (priv->extended_hash)
195 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
196
197 if (priv->padding) {
198 rctrl &= ~RCTRL_PAL_MASK;
199 rctrl |= RCTRL_PADDING(priv->padding);
200 }
201
202
203 if (priv->hwts_rx_en)
204 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
205
206 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
207 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
208
209
210 gfar_write(®s->rctrl, rctrl);
211
212 gfar_init_rqprm(priv);
213 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL);
214 rctrl |= RCTRL_LFC;
215
216
217 gfar_write(®s->rctrl, rctrl);
218 }
219
220 static void gfar_mac_tx_config(struct gfar_private *priv)
221 {
222 struct gfar __iomem *regs = priv->gfargrp[0].regs;
223 u32 tctrl = 0;
224
225 if (priv->ndev->features & NETIF_F_IP_CSUM)
226 tctrl |= TCTRL_INIT_CSUM;
227
228 if (priv->prio_sched_en)
229 tctrl |= TCTRL_TXSCHED_PRIO;
230 else {
231 tctrl |= TCTRL_TXSCHED_WRRS;
232 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
233 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
234 }
235
236 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
237 tctrl |= TCTRL_VLINS;
238
239 gfar_write(®s->tctrl, tctrl);
240 }
241
242 static void gfar_configure_coalescing(struct gfar_private *priv,
243 unsigned long tx_mask, unsigned long rx_mask)
244 {
245 struct gfar __iomem *regs = priv->gfargrp[0].regs;
246 u32 __iomem *baddr;
247
248 if (priv->mode == MQ_MG_MODE) {
249 int i = 0;
250
251 baddr = ®s->txic0;
252 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
253 gfar_write(baddr + i, 0);
254 if (likely(priv->tx_queue[i]->txcoalescing))
255 gfar_write(baddr + i, priv->tx_queue[i]->txic);
256 }
257
258 baddr = ®s->rxic0;
259 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
260 gfar_write(baddr + i, 0);
261 if (likely(priv->rx_queue[i]->rxcoalescing))
262 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
263 }
264 } else {
265
266
267
268 gfar_write(®s->txic, 0);
269 if (likely(priv->tx_queue[0]->txcoalescing))
270 gfar_write(®s->txic, priv->tx_queue[0]->txic);
271
272 gfar_write(®s->rxic, 0);
273 if (unlikely(priv->rx_queue[0]->rxcoalescing))
274 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
275 }
276 }
277
278 static void gfar_configure_coalescing_all(struct gfar_private *priv)
279 {
280 gfar_configure_coalescing(priv, 0xFF, 0xFF);
281 }
282
283 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
284 {
285 struct gfar_private *priv = netdev_priv(dev);
286 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
287 unsigned long tx_packets = 0, tx_bytes = 0;
288 int i;
289
290 for (i = 0; i < priv->num_rx_queues; i++) {
291 rx_packets += priv->rx_queue[i]->stats.rx_packets;
292 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
293 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
294 }
295
296 dev->stats.rx_packets = rx_packets;
297 dev->stats.rx_bytes = rx_bytes;
298 dev->stats.rx_dropped = rx_dropped;
299
300 for (i = 0; i < priv->num_tx_queues; i++) {
301 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
302 tx_packets += priv->tx_queue[i]->stats.tx_packets;
303 }
304
305 dev->stats.tx_bytes = tx_bytes;
306 dev->stats.tx_packets = tx_packets;
307
308 return &dev->stats;
309 }
310
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321
322
323
324
325 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
326 {
327 u32 tempval;
328 struct gfar_private *priv = netdev_priv(dev);
329 u32 result = ether_crc(ETH_ALEN, addr);
330 int width = priv->hash_width;
331 u8 whichbit = (result >> (32 - width)) & 0x1f;
332 u8 whichreg = result >> (32 - width + 5);
333 u32 value = (1 << (31-whichbit));
334
335 tempval = gfar_read(priv->hash_regs[whichreg]);
336 tempval |= value;
337 gfar_write(priv->hash_regs[whichreg], tempval);
338 }
339
340
341
342
343 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
344 const u8 *addr)
345 {
346 struct gfar_private *priv = netdev_priv(dev);
347 struct gfar __iomem *regs = priv->gfargrp[0].regs;
348 u32 tempval;
349 u32 __iomem *macptr = ®s->macstnaddr1;
350
351 macptr += num*2;
352
353
354
355
356
357 tempval = (addr[5] << 24) | (addr[4] << 16) |
358 (addr[3] << 8) | addr[2];
359
360 gfar_write(macptr, tempval);
361
362 tempval = (addr[1] << 24) | (addr[0] << 16);
363
364 gfar_write(macptr+1, tempval);
365 }
366
367 static int gfar_set_mac_addr(struct net_device *dev, void *p)
368 {
369 eth_mac_addr(dev, p);
370
371 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
372
373 return 0;
374 }
375
376 static void gfar_ints_disable(struct gfar_private *priv)
377 {
378 int i;
379 for (i = 0; i < priv->num_grps; i++) {
380 struct gfar __iomem *regs = priv->gfargrp[i].regs;
381
382 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
383
384
385 gfar_write(®s->imask, IMASK_INIT_CLEAR);
386 }
387 }
388
389 static void gfar_ints_enable(struct gfar_private *priv)
390 {
391 int i;
392 for (i = 0; i < priv->num_grps; i++) {
393 struct gfar __iomem *regs = priv->gfargrp[i].regs;
394
395 gfar_write(®s->imask, IMASK_DEFAULT);
396 }
397 }
398
399 static int gfar_alloc_tx_queues(struct gfar_private *priv)
400 {
401 int i;
402
403 for (i = 0; i < priv->num_tx_queues; i++) {
404 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
405 GFP_KERNEL);
406 if (!priv->tx_queue[i])
407 return -ENOMEM;
408
409 priv->tx_queue[i]->tx_skbuff = NULL;
410 priv->tx_queue[i]->qindex = i;
411 priv->tx_queue[i]->dev = priv->ndev;
412 spin_lock_init(&(priv->tx_queue[i]->txlock));
413 }
414 return 0;
415 }
416
417 static int gfar_alloc_rx_queues(struct gfar_private *priv)
418 {
419 int i;
420
421 for (i = 0; i < priv->num_rx_queues; i++) {
422 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
423 GFP_KERNEL);
424 if (!priv->rx_queue[i])
425 return -ENOMEM;
426
427 priv->rx_queue[i]->qindex = i;
428 priv->rx_queue[i]->ndev = priv->ndev;
429 }
430 return 0;
431 }
432
433 static void gfar_free_tx_queues(struct gfar_private *priv)
434 {
435 int i;
436
437 for (i = 0; i < priv->num_tx_queues; i++)
438 kfree(priv->tx_queue[i]);
439 }
440
441 static void gfar_free_rx_queues(struct gfar_private *priv)
442 {
443 int i;
444
445 for (i = 0; i < priv->num_rx_queues; i++)
446 kfree(priv->rx_queue[i]);
447 }
448
449 static void unmap_group_regs(struct gfar_private *priv)
450 {
451 int i;
452
453 for (i = 0; i < MAXGROUPS; i++)
454 if (priv->gfargrp[i].regs)
455 iounmap(priv->gfargrp[i].regs);
456 }
457
458 static void free_gfar_dev(struct gfar_private *priv)
459 {
460 int i, j;
461
462 for (i = 0; i < priv->num_grps; i++)
463 for (j = 0; j < GFAR_NUM_IRQS; j++) {
464 kfree(priv->gfargrp[i].irqinfo[j]);
465 priv->gfargrp[i].irqinfo[j] = NULL;
466 }
467
468 free_netdev(priv->ndev);
469 }
470
471 static void disable_napi(struct gfar_private *priv)
472 {
473 int i;
474
475 for (i = 0; i < priv->num_grps; i++) {
476 napi_disable(&priv->gfargrp[i].napi_rx);
477 napi_disable(&priv->gfargrp[i].napi_tx);
478 }
479 }
480
481 static void enable_napi(struct gfar_private *priv)
482 {
483 int i;
484
485 for (i = 0; i < priv->num_grps; i++) {
486 napi_enable(&priv->gfargrp[i].napi_rx);
487 napi_enable(&priv->gfargrp[i].napi_tx);
488 }
489 }
490
491 static int gfar_parse_group(struct device_node *np,
492 struct gfar_private *priv, const char *model)
493 {
494 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
495 int i;
496
497 for (i = 0; i < GFAR_NUM_IRQS; i++) {
498 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
499 GFP_KERNEL);
500 if (!grp->irqinfo[i])
501 return -ENOMEM;
502 }
503
504 grp->regs = of_iomap(np, 0);
505 if (!grp->regs)
506 return -ENOMEM;
507
508 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
509
510
511 if (model && strcasecmp(model, "FEC")) {
512 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
513 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
514 if (!gfar_irq(grp, TX)->irq ||
515 !gfar_irq(grp, RX)->irq ||
516 !gfar_irq(grp, ER)->irq)
517 return -EINVAL;
518 }
519
520 grp->priv = priv;
521 spin_lock_init(&grp->grplock);
522 if (priv->mode == MQ_MG_MODE) {
523 u32 rxq_mask, txq_mask;
524 int ret;
525
526 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
527 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
528
529 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
530 if (!ret) {
531 grp->rx_bit_map = rxq_mask ?
532 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
533 }
534
535 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
536 if (!ret) {
537 grp->tx_bit_map = txq_mask ?
538 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
539 }
540
541 if (priv->poll_mode == GFAR_SQ_POLLING) {
542
543 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
544 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
545 }
546 } else {
547 grp->rx_bit_map = 0xFF;
548 grp->tx_bit_map = 0xFF;
549 }
550
551
552
553
554 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
555 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
556
557
558
559
560 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
561 if (!grp->rx_queue)
562 grp->rx_queue = priv->rx_queue[i];
563 grp->num_rx_queues++;
564 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
565 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
566 priv->rx_queue[i]->grp = grp;
567 }
568
569 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
570 if (!grp->tx_queue)
571 grp->tx_queue = priv->tx_queue[i];
572 grp->num_tx_queues++;
573 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
574 priv->tqueue |= (TQUEUE_EN0 >> i);
575 priv->tx_queue[i]->grp = grp;
576 }
577
578 priv->num_grps++;
579
580 return 0;
581 }
582
583 static int gfar_of_group_count(struct device_node *np)
584 {
585 struct device_node *child;
586 int num = 0;
587
588 for_each_available_child_of_node(np, child)
589 if (of_node_name_eq(child, "queue-group"))
590 num++;
591
592 return num;
593 }
594
595
596
597
598 static phy_interface_t gfar_get_interface(struct net_device *dev)
599 {
600 struct gfar_private *priv = netdev_priv(dev);
601 struct gfar __iomem *regs = priv->gfargrp[0].regs;
602 u32 ecntrl;
603
604 ecntrl = gfar_read(®s->ecntrl);
605
606 if (ecntrl & ECNTRL_SGMII_MODE)
607 return PHY_INTERFACE_MODE_SGMII;
608
609 if (ecntrl & ECNTRL_TBI_MODE) {
610 if (ecntrl & ECNTRL_REDUCED_MODE)
611 return PHY_INTERFACE_MODE_RTBI;
612 else
613 return PHY_INTERFACE_MODE_TBI;
614 }
615
616 if (ecntrl & ECNTRL_REDUCED_MODE) {
617 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
618 return PHY_INTERFACE_MODE_RMII;
619 }
620 else {
621 phy_interface_t interface = priv->interface;
622
623
624
625
626 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
627 return PHY_INTERFACE_MODE_RGMII_ID;
628
629 return PHY_INTERFACE_MODE_RGMII;
630 }
631 }
632
633 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
634 return PHY_INTERFACE_MODE_GMII;
635
636 return PHY_INTERFACE_MODE_MII;
637 }
638
639 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
640 {
641 const char *model;
642 const void *mac_addr;
643 int err = 0, i;
644 struct net_device *dev = NULL;
645 struct gfar_private *priv = NULL;
646 struct device_node *np = ofdev->dev.of_node;
647 struct device_node *child = NULL;
648 u32 stash_len = 0;
649 u32 stash_idx = 0;
650 unsigned int num_tx_qs, num_rx_qs;
651 unsigned short mode, poll_mode;
652
653 if (!np)
654 return -ENODEV;
655
656 if (of_device_is_compatible(np, "fsl,etsec2")) {
657 mode = MQ_MG_MODE;
658 poll_mode = GFAR_SQ_POLLING;
659 } else {
660 mode = SQ_SG_MODE;
661 poll_mode = GFAR_SQ_POLLING;
662 }
663
664 if (mode == SQ_SG_MODE) {
665 num_tx_qs = 1;
666 num_rx_qs = 1;
667 } else {
668
669 unsigned int num_grps = gfar_of_group_count(np);
670
671 if (num_grps == 0 || num_grps > MAXGROUPS) {
672 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
673 num_grps);
674 pr_err("Cannot do alloc_etherdev, aborting\n");
675 return -EINVAL;
676 }
677
678 if (poll_mode == GFAR_SQ_POLLING) {
679 num_tx_qs = num_grps;
680 num_rx_qs = num_grps;
681 } else {
682 u32 tx_queues, rx_queues;
683 int ret;
684
685
686 ret = of_property_read_u32(np, "fsl,num_tx_queues",
687 &tx_queues);
688 num_tx_qs = ret ? 1 : tx_queues;
689
690 ret = of_property_read_u32(np, "fsl,num_rx_queues",
691 &rx_queues);
692 num_rx_qs = ret ? 1 : rx_queues;
693 }
694 }
695
696 if (num_tx_qs > MAX_TX_QS) {
697 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
698 num_tx_qs, MAX_TX_QS);
699 pr_err("Cannot do alloc_etherdev, aborting\n");
700 return -EINVAL;
701 }
702
703 if (num_rx_qs > MAX_RX_QS) {
704 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
705 num_rx_qs, MAX_RX_QS);
706 pr_err("Cannot do alloc_etherdev, aborting\n");
707 return -EINVAL;
708 }
709
710 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
711 dev = *pdev;
712 if (NULL == dev)
713 return -ENOMEM;
714
715 priv = netdev_priv(dev);
716 priv->ndev = dev;
717
718 priv->mode = mode;
719 priv->poll_mode = poll_mode;
720
721 priv->num_tx_queues = num_tx_qs;
722 netif_set_real_num_rx_queues(dev, num_rx_qs);
723 priv->num_rx_queues = num_rx_qs;
724
725 err = gfar_alloc_tx_queues(priv);
726 if (err)
727 goto tx_alloc_failed;
728
729 err = gfar_alloc_rx_queues(priv);
730 if (err)
731 goto rx_alloc_failed;
732
733 err = of_property_read_string(np, "model", &model);
734 if (err) {
735 pr_err("Device model property missing, aborting\n");
736 goto rx_alloc_failed;
737 }
738
739
740 INIT_LIST_HEAD(&priv->rx_list.list);
741 priv->rx_list.count = 0;
742 mutex_init(&priv->rx_queue_access);
743
744 for (i = 0; i < MAXGROUPS; i++)
745 priv->gfargrp[i].regs = NULL;
746
747
748 if (priv->mode == MQ_MG_MODE) {
749 for_each_available_child_of_node(np, child) {
750 if (!of_node_name_eq(child, "queue-group"))
751 continue;
752
753 err = gfar_parse_group(child, priv, model);
754 if (err)
755 goto err_grp_init;
756 }
757 } else {
758 err = gfar_parse_group(np, priv, model);
759 if (err)
760 goto err_grp_init;
761 }
762
763 if (of_property_read_bool(np, "bd-stash")) {
764 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
765 priv->bd_stash_en = 1;
766 }
767
768 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
769
770 if (err == 0)
771 priv->rx_stash_size = stash_len;
772
773 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
774
775 if (err == 0)
776 priv->rx_stash_index = stash_idx;
777
778 if (stash_len || stash_idx)
779 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
780
781 mac_addr = of_get_mac_address(np);
782
783 if (!IS_ERR(mac_addr))
784 ether_addr_copy(dev->dev_addr, mac_addr);
785
786 if (model && !strcasecmp(model, "TSEC"))
787 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
788 FSL_GIANFAR_DEV_HAS_COALESCE |
789 FSL_GIANFAR_DEV_HAS_RMON |
790 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
791
792 if (model && !strcasecmp(model, "eTSEC"))
793 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
794 FSL_GIANFAR_DEV_HAS_COALESCE |
795 FSL_GIANFAR_DEV_HAS_RMON |
796 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
797 FSL_GIANFAR_DEV_HAS_CSUM |
798 FSL_GIANFAR_DEV_HAS_VLAN |
799 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
800 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
801 FSL_GIANFAR_DEV_HAS_TIMER |
802 FSL_GIANFAR_DEV_HAS_RX_FILER;
803
804
805
806
807
808 err = of_get_phy_mode(np);
809 if (err >= 0)
810 priv->interface = err;
811 else
812 priv->interface = gfar_get_interface(dev);
813
814 if (of_find_property(np, "fsl,magic-packet", NULL))
815 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
816
817 if (of_get_property(np, "fsl,wake-on-filer", NULL))
818 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
819
820 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
821
822
823
824
825 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
826 err = of_phy_register_fixed_link(np);
827 if (err)
828 goto err_grp_init;
829
830 priv->phy_node = of_node_get(np);
831 }
832
833
834 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
835
836 return 0;
837
838 err_grp_init:
839 unmap_group_regs(priv);
840 rx_alloc_failed:
841 gfar_free_rx_queues(priv);
842 tx_alloc_failed:
843 gfar_free_tx_queues(priv);
844 free_gfar_dev(priv);
845 return err;
846 }
847
848 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
849 u32 class)
850 {
851 u32 rqfpr = FPR_FILER_MASK;
852 u32 rqfcr = 0x0;
853
854 rqfar--;
855 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
856 priv->ftp_rqfpr[rqfar] = rqfpr;
857 priv->ftp_rqfcr[rqfar] = rqfcr;
858 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
859
860 rqfar--;
861 rqfcr = RQFCR_CMP_NOMATCH;
862 priv->ftp_rqfpr[rqfar] = rqfpr;
863 priv->ftp_rqfcr[rqfar] = rqfcr;
864 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
865
866 rqfar--;
867 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
868 rqfpr = class;
869 priv->ftp_rqfcr[rqfar] = rqfcr;
870 priv->ftp_rqfpr[rqfar] = rqfpr;
871 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
872
873 rqfar--;
874 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
875 rqfpr = class;
876 priv->ftp_rqfcr[rqfar] = rqfcr;
877 priv->ftp_rqfpr[rqfar] = rqfpr;
878 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
879
880 return rqfar;
881 }
882
883 static void gfar_init_filer_table(struct gfar_private *priv)
884 {
885 int i = 0x0;
886 u32 rqfar = MAX_FILER_IDX;
887 u32 rqfcr = 0x0;
888 u32 rqfpr = FPR_FILER_MASK;
889
890
891 rqfcr = RQFCR_CMP_MATCH;
892 priv->ftp_rqfcr[rqfar] = rqfcr;
893 priv->ftp_rqfpr[rqfar] = rqfpr;
894 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
895
896 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
897 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
898 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
899 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
900 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
901 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
902
903
904 priv->cur_filer_idx = rqfar;
905
906
907 rqfcr = RQFCR_CMP_NOMATCH;
908 for (i = 0; i < rqfar; i++) {
909 priv->ftp_rqfcr[i] = rqfcr;
910 priv->ftp_rqfpr[i] = rqfpr;
911 gfar_write_filer(priv, i, rqfcr, rqfpr);
912 }
913 }
914
915 #ifdef CONFIG_PPC
916 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
917 {
918 unsigned int pvr = mfspr(SPRN_PVR);
919 unsigned int svr = mfspr(SPRN_SVR);
920 unsigned int mod = (svr >> 16) & 0xfff6;
921 unsigned int rev = svr & 0xffff;
922
923
924 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
925 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
926 priv->errata |= GFAR_ERRATA_74;
927
928
929 if ((pvr == 0x80850010 && mod == 0x80b0) ||
930 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
931 priv->errata |= GFAR_ERRATA_76;
932
933
934 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
935 priv->errata |= GFAR_ERRATA_12;
936 }
937
938 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
939 {
940 unsigned int svr = mfspr(SPRN_SVR);
941
942 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
943 priv->errata |= GFAR_ERRATA_12;
944
945 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
946 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
947 ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
948 priv->errata |= GFAR_ERRATA_76;
949 }
950 #endif
951
952 static void gfar_detect_errata(struct gfar_private *priv)
953 {
954 struct device *dev = &priv->ofdev->dev;
955
956
957 priv->errata |= GFAR_ERRATA_A002;
958
959 #ifdef CONFIG_PPC
960 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
961 __gfar_detect_errata_85xx(priv);
962 else
963 __gfar_detect_errata_83xx(priv);
964 #endif
965
966 if (priv->errata)
967 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
968 priv->errata);
969 }
970
971 static void gfar_init_addr_hash_table(struct gfar_private *priv)
972 {
973 struct gfar __iomem *regs = priv->gfargrp[0].regs;
974
975 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
976 priv->extended_hash = 1;
977 priv->hash_width = 9;
978
979 priv->hash_regs[0] = ®s->igaddr0;
980 priv->hash_regs[1] = ®s->igaddr1;
981 priv->hash_regs[2] = ®s->igaddr2;
982 priv->hash_regs[3] = ®s->igaddr3;
983 priv->hash_regs[4] = ®s->igaddr4;
984 priv->hash_regs[5] = ®s->igaddr5;
985 priv->hash_regs[6] = ®s->igaddr6;
986 priv->hash_regs[7] = ®s->igaddr7;
987 priv->hash_regs[8] = ®s->gaddr0;
988 priv->hash_regs[9] = ®s->gaddr1;
989 priv->hash_regs[10] = ®s->gaddr2;
990 priv->hash_regs[11] = ®s->gaddr3;
991 priv->hash_regs[12] = ®s->gaddr4;
992 priv->hash_regs[13] = ®s->gaddr5;
993 priv->hash_regs[14] = ®s->gaddr6;
994 priv->hash_regs[15] = ®s->gaddr7;
995
996 } else {
997 priv->extended_hash = 0;
998 priv->hash_width = 8;
999
1000 priv->hash_regs[0] = ®s->gaddr0;
1001 priv->hash_regs[1] = ®s->gaddr1;
1002 priv->hash_regs[2] = ®s->gaddr2;
1003 priv->hash_regs[3] = ®s->gaddr3;
1004 priv->hash_regs[4] = ®s->gaddr4;
1005 priv->hash_regs[5] = ®s->gaddr5;
1006 priv->hash_regs[6] = ®s->gaddr6;
1007 priv->hash_regs[7] = ®s->gaddr7;
1008 }
1009 }
1010
1011 static int __gfar_is_rx_idle(struct gfar_private *priv)
1012 {
1013 u32 res;
1014
1015
1016
1017
1018 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1019 return 0;
1020
1021
1022
1023
1024
1025 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1026 res &= 0x7f807f80;
1027 if ((res & 0xffff) == (res >> 16))
1028 return 1;
1029
1030 return 0;
1031 }
1032
1033
1034 static void gfar_halt_nodisable(struct gfar_private *priv)
1035 {
1036 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1037 u32 tempval;
1038 unsigned int timeout;
1039 int stopped;
1040
1041 gfar_ints_disable(priv);
1042
1043 if (gfar_is_dma_stopped(priv))
1044 return;
1045
1046
1047 tempval = gfar_read(®s->dmactrl);
1048 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1049 gfar_write(®s->dmactrl, tempval);
1050
1051 retry:
1052 timeout = 1000;
1053 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1054 cpu_relax();
1055 timeout--;
1056 }
1057
1058 if (!timeout)
1059 stopped = gfar_is_dma_stopped(priv);
1060
1061 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1062 !__gfar_is_rx_idle(priv))
1063 goto retry;
1064 }
1065
1066
1067 static void gfar_halt(struct gfar_private *priv)
1068 {
1069 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1070 u32 tempval;
1071
1072
1073 gfar_write(®s->rqueue, 0);
1074 gfar_write(®s->tqueue, 0);
1075
1076 mdelay(10);
1077
1078 gfar_halt_nodisable(priv);
1079
1080
1081 tempval = gfar_read(®s->maccfg1);
1082 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1083 gfar_write(®s->maccfg1, tempval);
1084 }
1085
1086 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1087 {
1088 struct txbd8 *txbdp;
1089 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1090 int i, j;
1091
1092 txbdp = tx_queue->tx_bd_base;
1093
1094 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1095 if (!tx_queue->tx_skbuff[i])
1096 continue;
1097
1098 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1099 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1100 txbdp->lstatus = 0;
1101 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1102 j++) {
1103 txbdp++;
1104 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1105 be16_to_cpu(txbdp->length),
1106 DMA_TO_DEVICE);
1107 }
1108 txbdp++;
1109 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1110 tx_queue->tx_skbuff[i] = NULL;
1111 }
1112 kfree(tx_queue->tx_skbuff);
1113 tx_queue->tx_skbuff = NULL;
1114 }
1115
1116 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1117 {
1118 int i;
1119
1120 struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1121
1122 dev_kfree_skb(rx_queue->skb);
1123
1124 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1125 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1126
1127 rxbdp->lstatus = 0;
1128 rxbdp->bufPtr = 0;
1129 rxbdp++;
1130
1131 if (!rxb->page)
1132 continue;
1133
1134 dma_unmap_page(rx_queue->dev, rxb->dma,
1135 PAGE_SIZE, DMA_FROM_DEVICE);
1136 __free_page(rxb->page);
1137
1138 rxb->page = NULL;
1139 }
1140
1141 kfree(rx_queue->rx_buff);
1142 rx_queue->rx_buff = NULL;
1143 }
1144
1145
1146
1147
1148 static void free_skb_resources(struct gfar_private *priv)
1149 {
1150 struct gfar_priv_tx_q *tx_queue = NULL;
1151 struct gfar_priv_rx_q *rx_queue = NULL;
1152 int i;
1153
1154
1155 for (i = 0; i < priv->num_tx_queues; i++) {
1156 struct netdev_queue *txq;
1157
1158 tx_queue = priv->tx_queue[i];
1159 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1160 if (tx_queue->tx_skbuff)
1161 free_skb_tx_queue(tx_queue);
1162 netdev_tx_reset_queue(txq);
1163 }
1164
1165 for (i = 0; i < priv->num_rx_queues; i++) {
1166 rx_queue = priv->rx_queue[i];
1167 if (rx_queue->rx_buff)
1168 free_skb_rx_queue(rx_queue);
1169 }
1170
1171 dma_free_coherent(priv->dev,
1172 sizeof(struct txbd8) * priv->total_tx_ring_size +
1173 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1174 priv->tx_queue[0]->tx_bd_base,
1175 priv->tx_queue[0]->tx_bd_dma_base);
1176 }
1177
1178 void stop_gfar(struct net_device *dev)
1179 {
1180 struct gfar_private *priv = netdev_priv(dev);
1181
1182 netif_tx_stop_all_queues(dev);
1183
1184 smp_mb__before_atomic();
1185 set_bit(GFAR_DOWN, &priv->state);
1186 smp_mb__after_atomic();
1187
1188 disable_napi(priv);
1189
1190
1191 gfar_halt(priv);
1192
1193 phy_stop(dev->phydev);
1194
1195 free_skb_resources(priv);
1196 }
1197
1198 static void gfar_start(struct gfar_private *priv)
1199 {
1200 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1201 u32 tempval;
1202 int i = 0;
1203
1204
1205 gfar_write(®s->rqueue, priv->rqueue);
1206 gfar_write(®s->tqueue, priv->tqueue);
1207
1208
1209 tempval = gfar_read(®s->dmactrl);
1210 tempval |= DMACTRL_INIT_SETTINGS;
1211 gfar_write(®s->dmactrl, tempval);
1212
1213
1214 tempval = gfar_read(®s->dmactrl);
1215 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1216 gfar_write(®s->dmactrl, tempval);
1217
1218 for (i = 0; i < priv->num_grps; i++) {
1219 regs = priv->gfargrp[i].regs;
1220
1221 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1222 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1223 }
1224
1225
1226 tempval = gfar_read(®s->maccfg1);
1227 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1228 gfar_write(®s->maccfg1, tempval);
1229
1230 gfar_ints_enable(priv);
1231
1232 netif_trans_update(priv->ndev);
1233 }
1234
1235 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
1236 {
1237 struct page *page;
1238 dma_addr_t addr;
1239
1240 page = dev_alloc_page();
1241 if (unlikely(!page))
1242 return false;
1243
1244 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
1245 if (unlikely(dma_mapping_error(rxq->dev, addr))) {
1246 __free_page(page);
1247
1248 return false;
1249 }
1250
1251 rxb->dma = addr;
1252 rxb->page = page;
1253 rxb->page_offset = 0;
1254
1255 return true;
1256 }
1257
1258 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
1259 {
1260 struct gfar_private *priv = netdev_priv(rx_queue->ndev);
1261 struct gfar_extra_stats *estats = &priv->extra_stats;
1262
1263 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
1264 atomic64_inc(&estats->rx_alloc_err);
1265 }
1266
1267 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
1268 int alloc_cnt)
1269 {
1270 struct rxbd8 *bdp;
1271 struct gfar_rx_buff *rxb;
1272 int i;
1273
1274 i = rx_queue->next_to_use;
1275 bdp = &rx_queue->rx_bd_base[i];
1276 rxb = &rx_queue->rx_buff[i];
1277
1278 while (alloc_cnt--) {
1279
1280 if (unlikely(!rxb->page)) {
1281 if (unlikely(!gfar_new_page(rx_queue, rxb))) {
1282 gfar_rx_alloc_err(rx_queue);
1283 break;
1284 }
1285 }
1286
1287
1288 gfar_init_rxbdp(rx_queue, bdp,
1289 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
1290
1291
1292 bdp++;
1293 rxb++;
1294
1295 if (unlikely(++i == rx_queue->rx_ring_size)) {
1296 i = 0;
1297 bdp = rx_queue->rx_bd_base;
1298 rxb = rx_queue->rx_buff;
1299 }
1300 }
1301
1302 rx_queue->next_to_use = i;
1303 rx_queue->next_to_alloc = i;
1304 }
1305
1306 static void gfar_init_bds(struct net_device *ndev)
1307 {
1308 struct gfar_private *priv = netdev_priv(ndev);
1309 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1310 struct gfar_priv_tx_q *tx_queue = NULL;
1311 struct gfar_priv_rx_q *rx_queue = NULL;
1312 struct txbd8 *txbdp;
1313 u32 __iomem *rfbptr;
1314 int i, j;
1315
1316 for (i = 0; i < priv->num_tx_queues; i++) {
1317 tx_queue = priv->tx_queue[i];
1318
1319 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
1320 tx_queue->dirty_tx = tx_queue->tx_bd_base;
1321 tx_queue->cur_tx = tx_queue->tx_bd_base;
1322 tx_queue->skb_curtx = 0;
1323 tx_queue->skb_dirtytx = 0;
1324
1325
1326 txbdp = tx_queue->tx_bd_base;
1327 for (j = 0; j < tx_queue->tx_ring_size; j++) {
1328 txbdp->lstatus = 0;
1329 txbdp->bufPtr = 0;
1330 txbdp++;
1331 }
1332
1333
1334 txbdp--;
1335 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
1336 TXBD_WRAP);
1337 }
1338
1339 rfbptr = ®s->rfbptr0;
1340 for (i = 0; i < priv->num_rx_queues; i++) {
1341 rx_queue = priv->rx_queue[i];
1342
1343 rx_queue->next_to_clean = 0;
1344 rx_queue->next_to_use = 0;
1345 rx_queue->next_to_alloc = 0;
1346
1347
1348
1349
1350 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
1351
1352 rx_queue->rfbptr = rfbptr;
1353 rfbptr += 2;
1354 }
1355 }
1356
1357 static int gfar_alloc_skb_resources(struct net_device *ndev)
1358 {
1359 void *vaddr;
1360 dma_addr_t addr;
1361 int i, j;
1362 struct gfar_private *priv = netdev_priv(ndev);
1363 struct device *dev = priv->dev;
1364 struct gfar_priv_tx_q *tx_queue = NULL;
1365 struct gfar_priv_rx_q *rx_queue = NULL;
1366
1367 priv->total_tx_ring_size = 0;
1368 for (i = 0; i < priv->num_tx_queues; i++)
1369 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
1370
1371 priv->total_rx_ring_size = 0;
1372 for (i = 0; i < priv->num_rx_queues; i++)
1373 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
1374
1375
1376 vaddr = dma_alloc_coherent(dev,
1377 (priv->total_tx_ring_size *
1378 sizeof(struct txbd8)) +
1379 (priv->total_rx_ring_size *
1380 sizeof(struct rxbd8)),
1381 &addr, GFP_KERNEL);
1382 if (!vaddr)
1383 return -ENOMEM;
1384
1385 for (i = 0; i < priv->num_tx_queues; i++) {
1386 tx_queue = priv->tx_queue[i];
1387 tx_queue->tx_bd_base = vaddr;
1388 tx_queue->tx_bd_dma_base = addr;
1389 tx_queue->dev = ndev;
1390
1391 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1392 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1393 }
1394
1395
1396 for (i = 0; i < priv->num_rx_queues; i++) {
1397 rx_queue = priv->rx_queue[i];
1398 rx_queue->rx_bd_base = vaddr;
1399 rx_queue->rx_bd_dma_base = addr;
1400 rx_queue->ndev = ndev;
1401 rx_queue->dev = dev;
1402 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1403 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1404 }
1405
1406
1407 for (i = 0; i < priv->num_tx_queues; i++) {
1408 tx_queue = priv->tx_queue[i];
1409 tx_queue->tx_skbuff =
1410 kmalloc_array(tx_queue->tx_ring_size,
1411 sizeof(*tx_queue->tx_skbuff),
1412 GFP_KERNEL);
1413 if (!tx_queue->tx_skbuff)
1414 goto cleanup;
1415
1416 for (j = 0; j < tx_queue->tx_ring_size; j++)
1417 tx_queue->tx_skbuff[j] = NULL;
1418 }
1419
1420 for (i = 0; i < priv->num_rx_queues; i++) {
1421 rx_queue = priv->rx_queue[i];
1422 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
1423 sizeof(*rx_queue->rx_buff),
1424 GFP_KERNEL);
1425 if (!rx_queue->rx_buff)
1426 goto cleanup;
1427 }
1428
1429 gfar_init_bds(ndev);
1430
1431 return 0;
1432
1433 cleanup:
1434 free_skb_resources(priv);
1435 return -ENOMEM;
1436 }
1437
1438
1439 int startup_gfar(struct net_device *ndev)
1440 {
1441 struct gfar_private *priv = netdev_priv(ndev);
1442 int err;
1443
1444 gfar_mac_reset(priv);
1445
1446 err = gfar_alloc_skb_resources(ndev);
1447 if (err)
1448 return err;
1449
1450 gfar_init_tx_rx_base(priv);
1451
1452 smp_mb__before_atomic();
1453 clear_bit(GFAR_DOWN, &priv->state);
1454 smp_mb__after_atomic();
1455
1456
1457 gfar_start(priv);
1458
1459
1460 priv->oldlink = 0;
1461 priv->oldspeed = 0;
1462 priv->oldduplex = -1;
1463
1464 phy_start(ndev->phydev);
1465
1466 enable_napi(priv);
1467
1468 netif_tx_wake_all_queues(ndev);
1469
1470 return 0;
1471 }
1472
1473 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
1474 {
1475 struct net_device *ndev = priv->ndev;
1476 struct phy_device *phydev = ndev->phydev;
1477 u32 val = 0;
1478
1479 if (!phydev->duplex)
1480 return val;
1481
1482 if (!priv->pause_aneg_en) {
1483 if (priv->tx_pause_en)
1484 val |= MACCFG1_TX_FLOW;
1485 if (priv->rx_pause_en)
1486 val |= MACCFG1_RX_FLOW;
1487 } else {
1488 u16 lcl_adv, rmt_adv;
1489 u8 flowctrl;
1490
1491 rmt_adv = 0;
1492 if (phydev->pause)
1493 rmt_adv = LPA_PAUSE_CAP;
1494 if (phydev->asym_pause)
1495 rmt_adv |= LPA_PAUSE_ASYM;
1496
1497 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising);
1498 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1499 if (flowctrl & FLOW_CTRL_TX)
1500 val |= MACCFG1_TX_FLOW;
1501 if (flowctrl & FLOW_CTRL_RX)
1502 val |= MACCFG1_RX_FLOW;
1503 }
1504
1505 return val;
1506 }
1507
1508 static noinline void gfar_update_link_state(struct gfar_private *priv)
1509 {
1510 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1511 struct net_device *ndev = priv->ndev;
1512 struct phy_device *phydev = ndev->phydev;
1513 struct gfar_priv_rx_q *rx_queue = NULL;
1514 int i;
1515
1516 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
1517 return;
1518
1519 if (phydev->link) {
1520 u32 tempval1 = gfar_read(®s->maccfg1);
1521 u32 tempval = gfar_read(®s->maccfg2);
1522 u32 ecntrl = gfar_read(®s->ecntrl);
1523 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
1524
1525 if (phydev->duplex != priv->oldduplex) {
1526 if (!(phydev->duplex))
1527 tempval &= ~(MACCFG2_FULL_DUPLEX);
1528 else
1529 tempval |= MACCFG2_FULL_DUPLEX;
1530
1531 priv->oldduplex = phydev->duplex;
1532 }
1533
1534 if (phydev->speed != priv->oldspeed) {
1535 switch (phydev->speed) {
1536 case 1000:
1537 tempval =
1538 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1539
1540 ecntrl &= ~(ECNTRL_R100);
1541 break;
1542 case 100:
1543 case 10:
1544 tempval =
1545 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1546
1547
1548
1549
1550 if (phydev->speed == SPEED_100)
1551 ecntrl |= ECNTRL_R100;
1552 else
1553 ecntrl &= ~(ECNTRL_R100);
1554 break;
1555 default:
1556 netif_warn(priv, link, priv->ndev,
1557 "Ack! Speed (%d) is not 10/100/1000!\n",
1558 phydev->speed);
1559 break;
1560 }
1561
1562 priv->oldspeed = phydev->speed;
1563 }
1564
1565 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1566 tempval1 |= gfar_get_flowctrl_cfg(priv);
1567
1568
1569 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
1570 for (i = 0; i < priv->num_rx_queues; i++) {
1571 u32 bdp_dma;
1572
1573 rx_queue = priv->rx_queue[i];
1574 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
1575 gfar_write(rx_queue->rfbptr, bdp_dma);
1576 }
1577
1578 priv->tx_actual_en = 1;
1579 }
1580
1581 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
1582 priv->tx_actual_en = 0;
1583
1584 gfar_write(®s->maccfg1, tempval1);
1585 gfar_write(®s->maccfg2, tempval);
1586 gfar_write(®s->ecntrl, ecntrl);
1587
1588 if (!priv->oldlink)
1589 priv->oldlink = 1;
1590
1591 } else if (priv->oldlink) {
1592 priv->oldlink = 0;
1593 priv->oldspeed = 0;
1594 priv->oldduplex = -1;
1595 }
1596
1597 if (netif_msg_link(priv))
1598 phy_print_status(phydev);
1599 }
1600
1601
1602
1603
1604
1605
1606
1607 static void adjust_link(struct net_device *dev)
1608 {
1609 struct gfar_private *priv = netdev_priv(dev);
1610 struct phy_device *phydev = dev->phydev;
1611
1612 if (unlikely(phydev->link != priv->oldlink ||
1613 (phydev->link && (phydev->duplex != priv->oldduplex ||
1614 phydev->speed != priv->oldspeed))))
1615 gfar_update_link_state(priv);
1616 }
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626 static void gfar_configure_serdes(struct net_device *dev)
1627 {
1628 struct gfar_private *priv = netdev_priv(dev);
1629 struct phy_device *tbiphy;
1630
1631 if (!priv->tbi_node) {
1632 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1633 "device tree specify a tbi-handle\n");
1634 return;
1635 }
1636
1637 tbiphy = of_phy_find_device(priv->tbi_node);
1638 if (!tbiphy) {
1639 dev_err(&dev->dev, "error: Could not get TBI device\n");
1640 return;
1641 }
1642
1643
1644
1645
1646
1647
1648 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1649 put_device(&tbiphy->mdio.dev);
1650 return;
1651 }
1652
1653
1654 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1655
1656 phy_write(tbiphy, MII_ADVERTISE,
1657 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1658 ADVERTISE_1000XPSE_ASYM);
1659
1660 phy_write(tbiphy, MII_BMCR,
1661 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1662 BMCR_SPEED1000);
1663
1664 put_device(&tbiphy->mdio.dev);
1665 }
1666
1667
1668
1669
1670 static int init_phy(struct net_device *dev)
1671 {
1672 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1673 struct gfar_private *priv = netdev_priv(dev);
1674 phy_interface_t interface = priv->interface;
1675 struct phy_device *phydev;
1676 struct ethtool_eee edata;
1677
1678 linkmode_set_bit_array(phy_10_100_features_array,
1679 ARRAY_SIZE(phy_10_100_features_array),
1680 mask);
1681 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);
1682 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);
1683 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1684 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mask);
1685
1686 priv->oldlink = 0;
1687 priv->oldspeed = 0;
1688 priv->oldduplex = -1;
1689
1690 phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1691 interface);
1692 if (!phydev) {
1693 dev_err(&dev->dev, "could not attach to PHY\n");
1694 return -ENODEV;
1695 }
1696
1697 if (interface == PHY_INTERFACE_MODE_SGMII)
1698 gfar_configure_serdes(dev);
1699
1700
1701 linkmode_and(phydev->supported, phydev->supported, mask);
1702 linkmode_copy(phydev->advertising, phydev->supported);
1703
1704
1705 phy_support_asym_pause(phydev);
1706
1707
1708 memset(&edata, 0, sizeof(struct ethtool_eee));
1709 phy_ethtool_set_eee(phydev, &edata);
1710
1711 return 0;
1712 }
1713
1714 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1715 {
1716 struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN);
1717
1718 memset(fcb, 0, GMAC_FCB_LEN);
1719
1720 return fcb;
1721 }
1722
1723 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1724 int fcb_length)
1725 {
1726
1727
1728
1729
1730 u8 flags = TXFCB_DEFAULT;
1731
1732
1733
1734
1735 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1736 flags |= TXFCB_UDP;
1737 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
1738 } else
1739 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
1740
1741
1742
1743
1744
1745
1746 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
1747 fcb->l4os = skb_network_header_len(skb);
1748
1749 fcb->flags = flags;
1750 }
1751
1752 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1753 {
1754 fcb->flags |= TXFCB_VLN;
1755 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
1756 }
1757
1758 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1759 struct txbd8 *base, int ring_size)
1760 {
1761 struct txbd8 *new_bd = bdp + stride;
1762
1763 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1764 }
1765
1766 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1767 int ring_size)
1768 {
1769 return skip_txbd(bdp, 1, base, ring_size);
1770 }
1771
1772
1773 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
1774 unsigned long fcb_addr)
1775 {
1776 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
1777 (fcb_addr % 0x20) > 0x18);
1778 }
1779
1780
1781
1782
1783 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
1784 unsigned int len)
1785 {
1786 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
1787 (len > 2500));
1788 }
1789
1790
1791
1792
1793 static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1794 {
1795 struct gfar_private *priv = netdev_priv(dev);
1796 struct gfar_priv_tx_q *tx_queue = NULL;
1797 struct netdev_queue *txq;
1798 struct gfar __iomem *regs = NULL;
1799 struct txfcb *fcb = NULL;
1800 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
1801 u32 lstatus;
1802 skb_frag_t *frag;
1803 int i, rq = 0;
1804 int do_tstamp, do_csum, do_vlan;
1805 u32 bufaddr;
1806 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
1807
1808 rq = skb->queue_mapping;
1809 tx_queue = priv->tx_queue[rq];
1810 txq = netdev_get_tx_queue(dev, rq);
1811 base = tx_queue->tx_bd_base;
1812 regs = tx_queue->grp->regs;
1813
1814 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
1815 do_vlan = skb_vlan_tag_present(skb);
1816 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1817 priv->hwts_tx_en;
1818
1819 if (do_csum || do_vlan)
1820 fcb_len = GMAC_FCB_LEN;
1821
1822
1823 if (unlikely(do_tstamp))
1824 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
1825
1826
1827 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
1828 struct sk_buff *skb_new;
1829
1830 skb_new = skb_realloc_headroom(skb, fcb_len);
1831 if (!skb_new) {
1832 dev->stats.tx_errors++;
1833 dev_kfree_skb_any(skb);
1834 return NETDEV_TX_OK;
1835 }
1836
1837 if (skb->sk)
1838 skb_set_owner_w(skb_new, skb->sk);
1839 dev_consume_skb_any(skb);
1840 skb = skb_new;
1841 }
1842
1843
1844 nr_frags = skb_shinfo(skb)->nr_frags;
1845
1846
1847 if (unlikely(do_tstamp))
1848 nr_txbds = nr_frags + 2;
1849 else
1850 nr_txbds = nr_frags + 1;
1851
1852
1853 if (nr_txbds > tx_queue->num_txbdfree) {
1854
1855 netif_tx_stop_queue(txq);
1856 dev->stats.tx_fifo_errors++;
1857 return NETDEV_TX_BUSY;
1858 }
1859
1860
1861 bytes_sent = skb->len;
1862 tx_queue->stats.tx_bytes += bytes_sent;
1863
1864 GFAR_CB(skb)->bytes_sent = bytes_sent;
1865 tx_queue->stats.tx_packets++;
1866
1867 txbdp = txbdp_start = tx_queue->cur_tx;
1868 lstatus = be32_to_cpu(txbdp->lstatus);
1869
1870
1871 if (unlikely(do_tstamp)) {
1872 skb_push(skb, GMAC_TXPAL_LEN);
1873 memset(skb->data, 0, GMAC_TXPAL_LEN);
1874 }
1875
1876
1877 if (fcb_len) {
1878 fcb = gfar_add_fcb(skb);
1879 lstatus |= BD_LFLAG(TXBD_TOE);
1880 }
1881
1882
1883 if (do_csum) {
1884 gfar_tx_checksum(skb, fcb, fcb_len);
1885
1886 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
1887 unlikely(gfar_csum_errata_76(priv, skb->len))) {
1888 __skb_pull(skb, GMAC_FCB_LEN);
1889 skb_checksum_help(skb);
1890 if (do_vlan || do_tstamp) {
1891
1892 fcb = gfar_add_fcb(skb);
1893 } else {
1894
1895 lstatus &= ~(BD_LFLAG(TXBD_TOE));
1896 fcb = NULL;
1897 }
1898 }
1899 }
1900
1901 if (do_vlan)
1902 gfar_tx_vlan(skb, fcb);
1903
1904 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
1905 DMA_TO_DEVICE);
1906 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1907 goto dma_map_err;
1908
1909 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
1910
1911
1912 if (unlikely(do_tstamp))
1913 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
1914 tx_queue->tx_ring_size);
1915
1916 if (likely(!nr_frags)) {
1917 if (likely(!do_tstamp))
1918 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1919 } else {
1920 u32 lstatus_start = lstatus;
1921
1922
1923 frag = &skb_shinfo(skb)->frags[0];
1924 for (i = 0; i < nr_frags; i++, frag++) {
1925 unsigned int size;
1926
1927
1928 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1929
1930 size = skb_frag_size(frag);
1931
1932 lstatus = be32_to_cpu(txbdp->lstatus) | size |
1933 BD_LFLAG(TXBD_READY);
1934
1935
1936 if (i == nr_frags - 1)
1937 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1938
1939 bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
1940 size, DMA_TO_DEVICE);
1941 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1942 goto dma_map_err;
1943
1944
1945 txbdp->bufPtr = cpu_to_be32(bufaddr);
1946 txbdp->lstatus = cpu_to_be32(lstatus);
1947 }
1948
1949 lstatus = lstatus_start;
1950 }
1951
1952
1953
1954
1955
1956
1957 if (unlikely(do_tstamp)) {
1958 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
1959
1960 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
1961 bufaddr += fcb_len;
1962
1963 lstatus_ts |= BD_LFLAG(TXBD_READY) |
1964 (skb_headlen(skb) - fcb_len);
1965 if (!nr_frags)
1966 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1967
1968 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
1969 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
1970 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
1971
1972
1973 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1974 fcb->ptp = 1;
1975 } else {
1976 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1977 }
1978
1979 netdev_tx_sent_queue(txq, bytes_sent);
1980
1981 gfar_wmb();
1982
1983 txbdp_start->lstatus = cpu_to_be32(lstatus);
1984
1985 gfar_wmb();
1986
1987 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
1988
1989
1990
1991
1992 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
1993 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
1994
1995 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1996
1997
1998
1999
2000
2001
2002 spin_lock_bh(&tx_queue->txlock);
2003
2004 tx_queue->num_txbdfree -= (nr_txbds);
2005 spin_unlock_bh(&tx_queue->txlock);
2006
2007
2008
2009
2010 if (!tx_queue->num_txbdfree) {
2011 netif_tx_stop_queue(txq);
2012
2013 dev->stats.tx_fifo_errors++;
2014 }
2015
2016
2017 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2018
2019 return NETDEV_TX_OK;
2020
2021 dma_map_err:
2022 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2023 if (do_tstamp)
2024 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2025 for (i = 0; i < nr_frags; i++) {
2026 lstatus = be32_to_cpu(txbdp->lstatus);
2027 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2028 break;
2029
2030 lstatus &= ~BD_LFLAG(TXBD_READY);
2031 txbdp->lstatus = cpu_to_be32(lstatus);
2032 bufaddr = be32_to_cpu(txbdp->bufPtr);
2033 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2034 DMA_TO_DEVICE);
2035 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2036 }
2037 gfar_wmb();
2038 dev_kfree_skb_any(skb);
2039 return NETDEV_TX_OK;
2040 }
2041
2042
2043 static int gfar_set_mac_address(struct net_device *dev)
2044 {
2045 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2046
2047 return 0;
2048 }
2049
2050 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2051 {
2052 struct gfar_private *priv = netdev_priv(dev);
2053
2054 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2055 cpu_relax();
2056
2057 if (dev->flags & IFF_UP)
2058 stop_gfar(dev);
2059
2060 dev->mtu = new_mtu;
2061
2062 if (dev->flags & IFF_UP)
2063 startup_gfar(dev);
2064
2065 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2066
2067 return 0;
2068 }
2069
2070 static void reset_gfar(struct net_device *ndev)
2071 {
2072 struct gfar_private *priv = netdev_priv(ndev);
2073
2074 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2075 cpu_relax();
2076
2077 stop_gfar(ndev);
2078 startup_gfar(ndev);
2079
2080 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2081 }
2082
2083
2084
2085
2086
2087
2088 static void gfar_reset_task(struct work_struct *work)
2089 {
2090 struct gfar_private *priv = container_of(work, struct gfar_private,
2091 reset_task);
2092 reset_gfar(priv->ndev);
2093 }
2094
2095 static void gfar_timeout(struct net_device *dev)
2096 {
2097 struct gfar_private *priv = netdev_priv(dev);
2098
2099 dev->stats.tx_errors++;
2100 schedule_work(&priv->reset_task);
2101 }
2102
2103 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
2104 {
2105 struct hwtstamp_config config;
2106 struct gfar_private *priv = netdev_priv(netdev);
2107
2108 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2109 return -EFAULT;
2110
2111
2112 if (config.flags)
2113 return -EINVAL;
2114
2115 switch (config.tx_type) {
2116 case HWTSTAMP_TX_OFF:
2117 priv->hwts_tx_en = 0;
2118 break;
2119 case HWTSTAMP_TX_ON:
2120 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2121 return -ERANGE;
2122 priv->hwts_tx_en = 1;
2123 break;
2124 default:
2125 return -ERANGE;
2126 }
2127
2128 switch (config.rx_filter) {
2129 case HWTSTAMP_FILTER_NONE:
2130 if (priv->hwts_rx_en) {
2131 priv->hwts_rx_en = 0;
2132 reset_gfar(netdev);
2133 }
2134 break;
2135 default:
2136 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2137 return -ERANGE;
2138 if (!priv->hwts_rx_en) {
2139 priv->hwts_rx_en = 1;
2140 reset_gfar(netdev);
2141 }
2142 config.rx_filter = HWTSTAMP_FILTER_ALL;
2143 break;
2144 }
2145
2146 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2147 -EFAULT : 0;
2148 }
2149
2150 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
2151 {
2152 struct hwtstamp_config config;
2153 struct gfar_private *priv = netdev_priv(netdev);
2154
2155 config.flags = 0;
2156 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2157 config.rx_filter = (priv->hwts_rx_en ?
2158 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
2159
2160 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2161 -EFAULT : 0;
2162 }
2163
2164 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2165 {
2166 struct phy_device *phydev = dev->phydev;
2167
2168 if (!netif_running(dev))
2169 return -EINVAL;
2170
2171 if (cmd == SIOCSHWTSTAMP)
2172 return gfar_hwtstamp_set(dev, rq);
2173 if (cmd == SIOCGHWTSTAMP)
2174 return gfar_hwtstamp_get(dev, rq);
2175
2176 if (!phydev)
2177 return -ENODEV;
2178
2179 return phy_mii_ioctl(phydev, rq, cmd);
2180 }
2181
2182
2183 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2184 {
2185 struct net_device *dev = tx_queue->dev;
2186 struct netdev_queue *txq;
2187 struct gfar_private *priv = netdev_priv(dev);
2188 struct txbd8 *bdp, *next = NULL;
2189 struct txbd8 *lbdp = NULL;
2190 struct txbd8 *base = tx_queue->tx_bd_base;
2191 struct sk_buff *skb;
2192 int skb_dirtytx;
2193 int tx_ring_size = tx_queue->tx_ring_size;
2194 int frags = 0, nr_txbds = 0;
2195 int i;
2196 int howmany = 0;
2197 int tqi = tx_queue->qindex;
2198 unsigned int bytes_sent = 0;
2199 u32 lstatus;
2200 size_t buflen;
2201
2202 txq = netdev_get_tx_queue(dev, tqi);
2203 bdp = tx_queue->dirty_tx;
2204 skb_dirtytx = tx_queue->skb_dirtytx;
2205
2206 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2207 bool do_tstamp;
2208
2209 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2210 priv->hwts_tx_en;
2211
2212 frags = skb_shinfo(skb)->nr_frags;
2213
2214
2215
2216
2217 if (unlikely(do_tstamp))
2218 nr_txbds = frags + 2;
2219 else
2220 nr_txbds = frags + 1;
2221
2222 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2223
2224 lstatus = be32_to_cpu(lbdp->lstatus);
2225
2226
2227 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2228 (lstatus & BD_LENGTH_MASK))
2229 break;
2230
2231 if (unlikely(do_tstamp)) {
2232 next = next_txbd(bdp, base, tx_ring_size);
2233 buflen = be16_to_cpu(next->length) +
2234 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2235 } else
2236 buflen = be16_to_cpu(bdp->length);
2237
2238 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2239 buflen, DMA_TO_DEVICE);
2240
2241 if (unlikely(do_tstamp)) {
2242 struct skb_shared_hwtstamps shhwtstamps;
2243 u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2244 ~0x7UL);
2245
2246 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2247 shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2248 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2249 skb_tstamp_tx(skb, &shhwtstamps);
2250 gfar_clear_txbd_status(bdp);
2251 bdp = next;
2252 }
2253
2254 gfar_clear_txbd_status(bdp);
2255 bdp = next_txbd(bdp, base, tx_ring_size);
2256
2257 for (i = 0; i < frags; i++) {
2258 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2259 be16_to_cpu(bdp->length),
2260 DMA_TO_DEVICE);
2261 gfar_clear_txbd_status(bdp);
2262 bdp = next_txbd(bdp, base, tx_ring_size);
2263 }
2264
2265 bytes_sent += GFAR_CB(skb)->bytes_sent;
2266
2267 dev_kfree_skb_any(skb);
2268
2269 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2270
2271 skb_dirtytx = (skb_dirtytx + 1) &
2272 TX_RING_MOD_MASK(tx_ring_size);
2273
2274 howmany++;
2275 spin_lock(&tx_queue->txlock);
2276 tx_queue->num_txbdfree += nr_txbds;
2277 spin_unlock(&tx_queue->txlock);
2278 }
2279
2280
2281 if (tx_queue->num_txbdfree &&
2282 netif_tx_queue_stopped(txq) &&
2283 !(test_bit(GFAR_DOWN, &priv->state)))
2284 netif_wake_subqueue(priv->ndev, tqi);
2285
2286
2287 tx_queue->skb_dirtytx = skb_dirtytx;
2288 tx_queue->dirty_tx = bdp;
2289
2290 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2291 }
2292
2293 static void count_errors(u32 lstatus, struct net_device *ndev)
2294 {
2295 struct gfar_private *priv = netdev_priv(ndev);
2296 struct net_device_stats *stats = &ndev->stats;
2297 struct gfar_extra_stats *estats = &priv->extra_stats;
2298
2299
2300 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2301 stats->rx_length_errors++;
2302
2303 atomic64_inc(&estats->rx_trunc);
2304
2305 return;
2306 }
2307
2308 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2309 stats->rx_length_errors++;
2310
2311 if (lstatus & BD_LFLAG(RXBD_LARGE))
2312 atomic64_inc(&estats->rx_large);
2313 else
2314 atomic64_inc(&estats->rx_short);
2315 }
2316 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2317 stats->rx_frame_errors++;
2318 atomic64_inc(&estats->rx_nonoctet);
2319 }
2320 if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2321 atomic64_inc(&estats->rx_crcerr);
2322 stats->rx_crc_errors++;
2323 }
2324 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2325 atomic64_inc(&estats->rx_overrun);
2326 stats->rx_over_errors++;
2327 }
2328 }
2329
2330 static irqreturn_t gfar_receive(int irq, void *grp_id)
2331 {
2332 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2333 unsigned long flags;
2334 u32 imask, ievent;
2335
2336 ievent = gfar_read(&grp->regs->ievent);
2337
2338 if (unlikely(ievent & IEVENT_FGPI)) {
2339 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2340 return IRQ_HANDLED;
2341 }
2342
2343 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2344 spin_lock_irqsave(&grp->grplock, flags);
2345 imask = gfar_read(&grp->regs->imask);
2346 imask &= IMASK_RX_DISABLED;
2347 gfar_write(&grp->regs->imask, imask);
2348 spin_unlock_irqrestore(&grp->grplock, flags);
2349 __napi_schedule(&grp->napi_rx);
2350 } else {
2351
2352
2353
2354 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2355 }
2356
2357 return IRQ_HANDLED;
2358 }
2359
2360
2361 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2362 {
2363 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2364 unsigned long flags;
2365 u32 imask;
2366
2367 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2368 spin_lock_irqsave(&grp->grplock, flags);
2369 imask = gfar_read(&grp->regs->imask);
2370 imask &= IMASK_TX_DISABLED;
2371 gfar_write(&grp->regs->imask, imask);
2372 spin_unlock_irqrestore(&grp->grplock, flags);
2373 __napi_schedule(&grp->napi_tx);
2374 } else {
2375
2376
2377
2378 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2379 }
2380
2381 return IRQ_HANDLED;
2382 }
2383
2384 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2385 struct sk_buff *skb, bool first)
2386 {
2387 int size = lstatus & BD_LENGTH_MASK;
2388 struct page *page = rxb->page;
2389
2390 if (likely(first)) {
2391 skb_put(skb, size);
2392 } else {
2393
2394 if (lstatus & BD_LFLAG(RXBD_LAST))
2395 size -= skb->len;
2396
2397 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2398 rxb->page_offset + RXBUF_ALIGNMENT,
2399 size, GFAR_RXB_TRUESIZE);
2400 }
2401
2402
2403 if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2404 return false;
2405
2406
2407 rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2408
2409 page_ref_inc(page);
2410
2411 return true;
2412 }
2413
2414 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2415 struct gfar_rx_buff *old_rxb)
2416 {
2417 struct gfar_rx_buff *new_rxb;
2418 u16 nta = rxq->next_to_alloc;
2419
2420 new_rxb = &rxq->rx_buff[nta];
2421
2422
2423 nta++;
2424 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2425
2426
2427 *new_rxb = *old_rxb;
2428
2429
2430 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2431 old_rxb->page_offset,
2432 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2433 }
2434
2435 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2436 u32 lstatus, struct sk_buff *skb)
2437 {
2438 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2439 struct page *page = rxb->page;
2440 bool first = false;
2441
2442 if (likely(!skb)) {
2443 void *buff_addr = page_address(page) + rxb->page_offset;
2444
2445 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2446 if (unlikely(!skb)) {
2447 gfar_rx_alloc_err(rx_queue);
2448 return NULL;
2449 }
2450 skb_reserve(skb, RXBUF_ALIGNMENT);
2451 first = true;
2452 }
2453
2454 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2455 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2456
2457 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2458
2459 gfar_reuse_rx_page(rx_queue, rxb);
2460 } else {
2461
2462 dma_unmap_page(rx_queue->dev, rxb->dma,
2463 PAGE_SIZE, DMA_FROM_DEVICE);
2464 }
2465
2466
2467 rxb->page = NULL;
2468
2469 return skb;
2470 }
2471
2472 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2473 {
2474
2475
2476
2477
2478 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2479 (RXFCB_CIP | RXFCB_CTU))
2480 skb->ip_summed = CHECKSUM_UNNECESSARY;
2481 else
2482 skb_checksum_none_assert(skb);
2483 }
2484
2485
2486 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
2487 {
2488 struct gfar_private *priv = netdev_priv(ndev);
2489 struct rxfcb *fcb = NULL;
2490
2491
2492 fcb = (struct rxfcb *)skb->data;
2493
2494
2495
2496
2497 if (priv->uses_rxfcb)
2498 skb_pull(skb, GMAC_FCB_LEN);
2499
2500
2501 if (priv->hwts_rx_en) {
2502 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2503 u64 *ns = (u64 *) skb->data;
2504
2505 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2506 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2507 }
2508
2509 if (priv->padding)
2510 skb_pull(skb, priv->padding);
2511
2512
2513 pskb_trim(skb, skb->len - ETH_FCS_LEN);
2514
2515 if (ndev->features & NETIF_F_RXCSUM)
2516 gfar_rx_checksum(skb, fcb);
2517
2518
2519
2520
2521
2522 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2523 be16_to_cpu(fcb->flags) & RXFCB_VLN)
2524 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2525 be16_to_cpu(fcb->vlctl));
2526 }
2527
2528
2529
2530
2531
2532 static int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue,
2533 int rx_work_limit)
2534 {
2535 struct net_device *ndev = rx_queue->ndev;
2536 struct gfar_private *priv = netdev_priv(ndev);
2537 struct rxbd8 *bdp;
2538 int i, howmany = 0;
2539 struct sk_buff *skb = rx_queue->skb;
2540 int cleaned_cnt = gfar_rxbd_unused(rx_queue);
2541 unsigned int total_bytes = 0, total_pkts = 0;
2542
2543
2544 i = rx_queue->next_to_clean;
2545
2546 while (rx_work_limit--) {
2547 u32 lstatus;
2548
2549 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
2550 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2551 cleaned_cnt = 0;
2552 }
2553
2554 bdp = &rx_queue->rx_bd_base[i];
2555 lstatus = be32_to_cpu(bdp->lstatus);
2556 if (lstatus & BD_LFLAG(RXBD_EMPTY))
2557 break;
2558
2559
2560 rmb();
2561
2562
2563 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
2564 if (unlikely(!skb))
2565 break;
2566
2567 cleaned_cnt++;
2568 howmany++;
2569
2570 if (unlikely(++i == rx_queue->rx_ring_size))
2571 i = 0;
2572
2573 rx_queue->next_to_clean = i;
2574
2575
2576 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
2577 continue;
2578
2579 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
2580 count_errors(lstatus, ndev);
2581
2582
2583 dev_kfree_skb(skb);
2584 skb = NULL;
2585 rx_queue->stats.rx_dropped++;
2586 continue;
2587 }
2588
2589 gfar_process_frame(ndev, skb);
2590
2591
2592 total_pkts++;
2593 total_bytes += skb->len;
2594
2595 skb_record_rx_queue(skb, rx_queue->qindex);
2596
2597 skb->protocol = eth_type_trans(skb, ndev);
2598
2599
2600 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
2601
2602 skb = NULL;
2603 }
2604
2605
2606 rx_queue->skb = skb;
2607
2608 rx_queue->stats.rx_packets += total_pkts;
2609 rx_queue->stats.rx_bytes += total_bytes;
2610
2611 if (cleaned_cnt)
2612 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2613
2614
2615 if (unlikely(priv->tx_actual_en)) {
2616 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
2617
2618 gfar_write(rx_queue->rfbptr, bdp_dma);
2619 }
2620
2621 return howmany;
2622 }
2623
2624 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2625 {
2626 struct gfar_priv_grp *gfargrp =
2627 container_of(napi, struct gfar_priv_grp, napi_rx);
2628 struct gfar __iomem *regs = gfargrp->regs;
2629 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2630 int work_done = 0;
2631
2632
2633
2634
2635 gfar_write(®s->ievent, IEVENT_RX_MASK);
2636
2637 work_done = gfar_clean_rx_ring(rx_queue, budget);
2638
2639 if (work_done < budget) {
2640 u32 imask;
2641 napi_complete_done(napi, work_done);
2642
2643 gfar_write(®s->rstat, gfargrp->rstat);
2644
2645 spin_lock_irq(&gfargrp->grplock);
2646 imask = gfar_read(®s->imask);
2647 imask |= IMASK_RX_DEFAULT;
2648 gfar_write(®s->imask, imask);
2649 spin_unlock_irq(&gfargrp->grplock);
2650 }
2651
2652 return work_done;
2653 }
2654
2655 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
2656 {
2657 struct gfar_priv_grp *gfargrp =
2658 container_of(napi, struct gfar_priv_grp, napi_tx);
2659 struct gfar __iomem *regs = gfargrp->regs;
2660 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
2661 u32 imask;
2662
2663
2664
2665
2666 gfar_write(®s->ievent, IEVENT_TX_MASK);
2667
2668
2669 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2670 gfar_clean_tx_ring(tx_queue);
2671
2672 napi_complete(napi);
2673
2674 spin_lock_irq(&gfargrp->grplock);
2675 imask = gfar_read(®s->imask);
2676 imask |= IMASK_TX_DEFAULT;
2677 gfar_write(®s->imask, imask);
2678 spin_unlock_irq(&gfargrp->grplock);
2679
2680 return 0;
2681 }
2682
2683 static int gfar_poll_rx(struct napi_struct *napi, int budget)
2684 {
2685 struct gfar_priv_grp *gfargrp =
2686 container_of(napi, struct gfar_priv_grp, napi_rx);
2687 struct gfar_private *priv = gfargrp->priv;
2688 struct gfar __iomem *regs = gfargrp->regs;
2689 struct gfar_priv_rx_q *rx_queue = NULL;
2690 int work_done = 0, work_done_per_q = 0;
2691 int i, budget_per_q = 0;
2692 unsigned long rstat_rxf;
2693 int num_act_queues;
2694
2695
2696
2697
2698 gfar_write(®s->ievent, IEVENT_RX_MASK);
2699
2700 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
2701
2702 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2703 if (num_act_queues)
2704 budget_per_q = budget/num_act_queues;
2705
2706 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2707
2708 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2709 continue;
2710
2711 rx_queue = priv->rx_queue[i];
2712 work_done_per_q =
2713 gfar_clean_rx_ring(rx_queue, budget_per_q);
2714 work_done += work_done_per_q;
2715
2716
2717 if (work_done_per_q < budget_per_q) {
2718
2719 gfar_write(®s->rstat,
2720 RSTAT_CLEAR_RXF0 >> i);
2721 num_act_queues--;
2722
2723 if (!num_act_queues)
2724 break;
2725 }
2726 }
2727
2728 if (!num_act_queues) {
2729 u32 imask;
2730 napi_complete_done(napi, work_done);
2731
2732
2733 gfar_write(®s->rstat, gfargrp->rstat);
2734
2735 spin_lock_irq(&gfargrp->grplock);
2736 imask = gfar_read(®s->imask);
2737 imask |= IMASK_RX_DEFAULT;
2738 gfar_write(®s->imask, imask);
2739 spin_unlock_irq(&gfargrp->grplock);
2740 }
2741
2742 return work_done;
2743 }
2744
2745 static int gfar_poll_tx(struct napi_struct *napi, int budget)
2746 {
2747 struct gfar_priv_grp *gfargrp =
2748 container_of(napi, struct gfar_priv_grp, napi_tx);
2749 struct gfar_private *priv = gfargrp->priv;
2750 struct gfar __iomem *regs = gfargrp->regs;
2751 struct gfar_priv_tx_q *tx_queue = NULL;
2752 int has_tx_work = 0;
2753 int i;
2754
2755
2756
2757
2758 gfar_write(®s->ievent, IEVENT_TX_MASK);
2759
2760 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2761 tx_queue = priv->tx_queue[i];
2762
2763 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2764 gfar_clean_tx_ring(tx_queue);
2765 has_tx_work = 1;
2766 }
2767 }
2768
2769 if (!has_tx_work) {
2770 u32 imask;
2771 napi_complete(napi);
2772
2773 spin_lock_irq(&gfargrp->grplock);
2774 imask = gfar_read(®s->imask);
2775 imask |= IMASK_TX_DEFAULT;
2776 gfar_write(®s->imask, imask);
2777 spin_unlock_irq(&gfargrp->grplock);
2778 }
2779
2780 return 0;
2781 }
2782
2783
2784 static irqreturn_t gfar_error(int irq, void *grp_id)
2785 {
2786 struct gfar_priv_grp *gfargrp = grp_id;
2787 struct gfar __iomem *regs = gfargrp->regs;
2788 struct gfar_private *priv= gfargrp->priv;
2789 struct net_device *dev = priv->ndev;
2790
2791
2792 u32 events = gfar_read(®s->ievent);
2793
2794
2795 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
2796
2797
2798 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2799 (events & IEVENT_MAG))
2800 events &= ~IEVENT_MAG;
2801
2802
2803 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2804 netdev_dbg(dev,
2805 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
2806 events, gfar_read(®s->imask));
2807
2808
2809 if (events & IEVENT_TXE) {
2810 dev->stats.tx_errors++;
2811
2812 if (events & IEVENT_LC)
2813 dev->stats.tx_window_errors++;
2814 if (events & IEVENT_CRL)
2815 dev->stats.tx_aborted_errors++;
2816 if (events & IEVENT_XFUN) {
2817 netif_dbg(priv, tx_err, dev,
2818 "TX FIFO underrun, packet dropped\n");
2819 dev->stats.tx_dropped++;
2820 atomic64_inc(&priv->extra_stats.tx_underrun);
2821
2822 schedule_work(&priv->reset_task);
2823 }
2824 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
2825 }
2826 if (events & IEVENT_BSY) {
2827 dev->stats.rx_over_errors++;
2828 atomic64_inc(&priv->extra_stats.rx_bsy);
2829
2830 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
2831 gfar_read(®s->rstat));
2832 }
2833 if (events & IEVENT_BABR) {
2834 dev->stats.rx_errors++;
2835 atomic64_inc(&priv->extra_stats.rx_babr);
2836
2837 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
2838 }
2839 if (events & IEVENT_EBERR) {
2840 atomic64_inc(&priv->extra_stats.eberr);
2841 netif_dbg(priv, rx_err, dev, "bus error\n");
2842 }
2843 if (events & IEVENT_RXC)
2844 netif_dbg(priv, rx_status, dev, "control frame\n");
2845
2846 if (events & IEVENT_BABT) {
2847 atomic64_inc(&priv->extra_stats.tx_babt);
2848 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
2849 }
2850 return IRQ_HANDLED;
2851 }
2852
2853
2854 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2855 {
2856 struct gfar_priv_grp *gfargrp = grp_id;
2857
2858
2859 u32 events = gfar_read(&gfargrp->regs->ievent);
2860
2861
2862 if (events & IEVENT_RX_MASK)
2863 gfar_receive(irq, grp_id);
2864
2865
2866 if (events & IEVENT_TX_MASK)
2867 gfar_transmit(irq, grp_id);
2868
2869
2870 if (events & IEVENT_ERR_MASK)
2871 gfar_error(irq, grp_id);
2872
2873 return IRQ_HANDLED;
2874 }
2875
2876 #ifdef CONFIG_NET_POLL_CONTROLLER
2877
2878
2879
2880
2881 static void gfar_netpoll(struct net_device *dev)
2882 {
2883 struct gfar_private *priv = netdev_priv(dev);
2884 int i;
2885
2886
2887 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2888 for (i = 0; i < priv->num_grps; i++) {
2889 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2890
2891 disable_irq(gfar_irq(grp, TX)->irq);
2892 disable_irq(gfar_irq(grp, RX)->irq);
2893 disable_irq(gfar_irq(grp, ER)->irq);
2894 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2895 enable_irq(gfar_irq(grp, ER)->irq);
2896 enable_irq(gfar_irq(grp, RX)->irq);
2897 enable_irq(gfar_irq(grp, TX)->irq);
2898 }
2899 } else {
2900 for (i = 0; i < priv->num_grps; i++) {
2901 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2902
2903 disable_irq(gfar_irq(grp, TX)->irq);
2904 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2905 enable_irq(gfar_irq(grp, TX)->irq);
2906 }
2907 }
2908 }
2909 #endif
2910
2911 static void free_grp_irqs(struct gfar_priv_grp *grp)
2912 {
2913 free_irq(gfar_irq(grp, TX)->irq, grp);
2914 free_irq(gfar_irq(grp, RX)->irq, grp);
2915 free_irq(gfar_irq(grp, ER)->irq, grp);
2916 }
2917
2918 static int register_grp_irqs(struct gfar_priv_grp *grp)
2919 {
2920 struct gfar_private *priv = grp->priv;
2921 struct net_device *dev = priv->ndev;
2922 int err;
2923
2924
2925
2926
2927 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2928
2929
2930
2931 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2932 gfar_irq(grp, ER)->name, grp);
2933 if (err < 0) {
2934 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2935 gfar_irq(grp, ER)->irq);
2936
2937 goto err_irq_fail;
2938 }
2939 enable_irq_wake(gfar_irq(grp, ER)->irq);
2940
2941 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2942 gfar_irq(grp, TX)->name, grp);
2943 if (err < 0) {
2944 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2945 gfar_irq(grp, TX)->irq);
2946 goto tx_irq_fail;
2947 }
2948 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2949 gfar_irq(grp, RX)->name, grp);
2950 if (err < 0) {
2951 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2952 gfar_irq(grp, RX)->irq);
2953 goto rx_irq_fail;
2954 }
2955 enable_irq_wake(gfar_irq(grp, RX)->irq);
2956
2957 } else {
2958 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2959 gfar_irq(grp, TX)->name, grp);
2960 if (err < 0) {
2961 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2962 gfar_irq(grp, TX)->irq);
2963 goto err_irq_fail;
2964 }
2965 enable_irq_wake(gfar_irq(grp, TX)->irq);
2966 }
2967
2968 return 0;
2969
2970 rx_irq_fail:
2971 free_irq(gfar_irq(grp, TX)->irq, grp);
2972 tx_irq_fail:
2973 free_irq(gfar_irq(grp, ER)->irq, grp);
2974 err_irq_fail:
2975 return err;
2976
2977 }
2978
2979 static void gfar_free_irq(struct gfar_private *priv)
2980 {
2981 int i;
2982
2983
2984 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2985 for (i = 0; i < priv->num_grps; i++)
2986 free_grp_irqs(&priv->gfargrp[i]);
2987 } else {
2988 for (i = 0; i < priv->num_grps; i++)
2989 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2990 &priv->gfargrp[i]);
2991 }
2992 }
2993
2994 static int gfar_request_irq(struct gfar_private *priv)
2995 {
2996 int err, i, j;
2997
2998 for (i = 0; i < priv->num_grps; i++) {
2999 err = register_grp_irqs(&priv->gfargrp[i]);
3000 if (err) {
3001 for (j = 0; j < i; j++)
3002 free_grp_irqs(&priv->gfargrp[j]);
3003 return err;
3004 }
3005 }
3006
3007 return 0;
3008 }
3009
3010
3011
3012
3013 static int gfar_enet_open(struct net_device *dev)
3014 {
3015 struct gfar_private *priv = netdev_priv(dev);
3016 int err;
3017
3018 err = init_phy(dev);
3019 if (err)
3020 return err;
3021
3022 err = gfar_request_irq(priv);
3023 if (err)
3024 return err;
3025
3026 err = startup_gfar(dev);
3027 if (err)
3028 return err;
3029
3030 return err;
3031 }
3032
3033
3034 static int gfar_close(struct net_device *dev)
3035 {
3036 struct gfar_private *priv = netdev_priv(dev);
3037
3038 cancel_work_sync(&priv->reset_task);
3039 stop_gfar(dev);
3040
3041
3042 phy_disconnect(dev->phydev);
3043
3044 gfar_free_irq(priv);
3045
3046 return 0;
3047 }
3048
3049
3050
3051
3052 static void gfar_clear_exact_match(struct net_device *dev)
3053 {
3054 int idx;
3055 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3056
3057 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3058 gfar_set_mac_for_addr(dev, idx, zero_arr);
3059 }
3060
3061
3062
3063
3064
3065
3066 static void gfar_set_multi(struct net_device *dev)
3067 {
3068 struct netdev_hw_addr *ha;
3069 struct gfar_private *priv = netdev_priv(dev);
3070 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3071 u32 tempval;
3072
3073 if (dev->flags & IFF_PROMISC) {
3074
3075 tempval = gfar_read(®s->rctrl);
3076 tempval |= RCTRL_PROM;
3077 gfar_write(®s->rctrl, tempval);
3078 } else {
3079
3080 tempval = gfar_read(®s->rctrl);
3081 tempval &= ~(RCTRL_PROM);
3082 gfar_write(®s->rctrl, tempval);
3083 }
3084
3085 if (dev->flags & IFF_ALLMULTI) {
3086
3087 gfar_write(®s->igaddr0, 0xffffffff);
3088 gfar_write(®s->igaddr1, 0xffffffff);
3089 gfar_write(®s->igaddr2, 0xffffffff);
3090 gfar_write(®s->igaddr3, 0xffffffff);
3091 gfar_write(®s->igaddr4, 0xffffffff);
3092 gfar_write(®s->igaddr5, 0xffffffff);
3093 gfar_write(®s->igaddr6, 0xffffffff);
3094 gfar_write(®s->igaddr7, 0xffffffff);
3095 gfar_write(®s->gaddr0, 0xffffffff);
3096 gfar_write(®s->gaddr1, 0xffffffff);
3097 gfar_write(®s->gaddr2, 0xffffffff);
3098 gfar_write(®s->gaddr3, 0xffffffff);
3099 gfar_write(®s->gaddr4, 0xffffffff);
3100 gfar_write(®s->gaddr5, 0xffffffff);
3101 gfar_write(®s->gaddr6, 0xffffffff);
3102 gfar_write(®s->gaddr7, 0xffffffff);
3103 } else {
3104 int em_num;
3105 int idx;
3106
3107
3108 gfar_write(®s->igaddr0, 0x0);
3109 gfar_write(®s->igaddr1, 0x0);
3110 gfar_write(®s->igaddr2, 0x0);
3111 gfar_write(®s->igaddr3, 0x0);
3112 gfar_write(®s->igaddr4, 0x0);
3113 gfar_write(®s->igaddr5, 0x0);
3114 gfar_write(®s->igaddr6, 0x0);
3115 gfar_write(®s->igaddr7, 0x0);
3116 gfar_write(®s->gaddr0, 0x0);
3117 gfar_write(®s->gaddr1, 0x0);
3118 gfar_write(®s->gaddr2, 0x0);
3119 gfar_write(®s->gaddr3, 0x0);
3120 gfar_write(®s->gaddr4, 0x0);
3121 gfar_write(®s->gaddr5, 0x0);
3122 gfar_write(®s->gaddr6, 0x0);
3123 gfar_write(®s->gaddr7, 0x0);
3124
3125
3126
3127
3128
3129 if (priv->extended_hash) {
3130 em_num = GFAR_EM_NUM + 1;
3131 gfar_clear_exact_match(dev);
3132 idx = 1;
3133 } else {
3134 idx = 0;
3135 em_num = 0;
3136 }
3137
3138 if (netdev_mc_empty(dev))
3139 return;
3140
3141
3142 netdev_for_each_mc_addr(ha, dev) {
3143 if (idx < em_num) {
3144 gfar_set_mac_for_addr(dev, idx, ha->addr);
3145 idx++;
3146 } else
3147 gfar_set_hash_for_addr(dev, ha->addr);
3148 }
3149 }
3150 }
3151
3152 void gfar_mac_reset(struct gfar_private *priv)
3153 {
3154 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3155 u32 tempval;
3156
3157
3158 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
3159
3160
3161 udelay(3);
3162
3163
3164
3165
3166 gfar_write(®s->maccfg1, 0);
3167
3168 udelay(3);
3169
3170 gfar_rx_offload_en(priv);
3171
3172
3173 gfar_write(®s->maxfrm, GFAR_JUMBO_FRAME_SIZE);
3174 gfar_write(®s->mrblr, GFAR_RXB_SIZE);
3175
3176
3177 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
3178
3179
3180 tempval = MACCFG2_INIT_SETTINGS;
3181
3182
3183
3184
3185
3186 if (gfar_has_errata(priv, GFAR_ERRATA_74))
3187 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
3188
3189 gfar_write(®s->maccfg2, tempval);
3190
3191
3192 gfar_write(®s->igaddr0, 0);
3193 gfar_write(®s->igaddr1, 0);
3194 gfar_write(®s->igaddr2, 0);
3195 gfar_write(®s->igaddr3, 0);
3196 gfar_write(®s->igaddr4, 0);
3197 gfar_write(®s->igaddr5, 0);
3198 gfar_write(®s->igaddr6, 0);
3199 gfar_write(®s->igaddr7, 0);
3200
3201 gfar_write(®s->gaddr0, 0);
3202 gfar_write(®s->gaddr1, 0);
3203 gfar_write(®s->gaddr2, 0);
3204 gfar_write(®s->gaddr3, 0);
3205 gfar_write(®s->gaddr4, 0);
3206 gfar_write(®s->gaddr5, 0);
3207 gfar_write(®s->gaddr6, 0);
3208 gfar_write(®s->gaddr7, 0);
3209
3210 if (priv->extended_hash)
3211 gfar_clear_exact_match(priv->ndev);
3212
3213 gfar_mac_rx_config(priv);
3214
3215 gfar_mac_tx_config(priv);
3216
3217 gfar_set_mac_address(priv->ndev);
3218
3219 gfar_set_multi(priv->ndev);
3220
3221
3222 gfar_ints_disable(priv);
3223
3224
3225 gfar_configure_coalescing_all(priv);
3226 }
3227
3228 static void gfar_hw_init(struct gfar_private *priv)
3229 {
3230 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3231 u32 attrs;
3232
3233
3234
3235
3236 gfar_halt(priv);
3237
3238 gfar_mac_reset(priv);
3239
3240
3241 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
3242 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
3243
3244
3245 gfar_write(®s->rmon.cam1, 0xffffffff);
3246 gfar_write(®s->rmon.cam2, 0xffffffff);
3247 }
3248
3249
3250 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
3251
3252
3253 attrs = ATTRELI_EL(priv->rx_stash_size) |
3254 ATTRELI_EI(priv->rx_stash_index);
3255
3256 gfar_write(®s->attreli, attrs);
3257
3258
3259
3260
3261 attrs = ATTR_INIT_SETTINGS;
3262
3263 if (priv->bd_stash_en)
3264 attrs |= ATTR_BDSTASH;
3265
3266 if (priv->rx_stash_size != 0)
3267 attrs |= ATTR_BUFSTASH;
3268
3269 gfar_write(®s->attr, attrs);
3270
3271
3272 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
3273 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
3274 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
3275
3276
3277 if (priv->num_grps > 1)
3278 gfar_write_isrg(priv);
3279 }
3280
3281 static const struct net_device_ops gfar_netdev_ops = {
3282 .ndo_open = gfar_enet_open,
3283 .ndo_start_xmit = gfar_start_xmit,
3284 .ndo_stop = gfar_close,
3285 .ndo_change_mtu = gfar_change_mtu,
3286 .ndo_set_features = gfar_set_features,
3287 .ndo_set_rx_mode = gfar_set_multi,
3288 .ndo_tx_timeout = gfar_timeout,
3289 .ndo_do_ioctl = gfar_ioctl,
3290 .ndo_get_stats = gfar_get_stats,
3291 .ndo_change_carrier = fixed_phy_change_carrier,
3292 .ndo_set_mac_address = gfar_set_mac_addr,
3293 .ndo_validate_addr = eth_validate_addr,
3294 #ifdef CONFIG_NET_POLL_CONTROLLER
3295 .ndo_poll_controller = gfar_netpoll,
3296 #endif
3297 };
3298
3299
3300
3301
3302 static int gfar_probe(struct platform_device *ofdev)
3303 {
3304 struct device_node *np = ofdev->dev.of_node;
3305 struct net_device *dev = NULL;
3306 struct gfar_private *priv = NULL;
3307 int err = 0, i;
3308
3309 err = gfar_of_init(ofdev, &dev);
3310
3311 if (err)
3312 return err;
3313
3314 priv = netdev_priv(dev);
3315 priv->ndev = dev;
3316 priv->ofdev = ofdev;
3317 priv->dev = &ofdev->dev;
3318 SET_NETDEV_DEV(dev, &ofdev->dev);
3319
3320 INIT_WORK(&priv->reset_task, gfar_reset_task);
3321
3322 platform_set_drvdata(ofdev, priv);
3323
3324 gfar_detect_errata(priv);
3325
3326
3327 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
3328
3329
3330 dev->watchdog_timeo = TX_TIMEOUT;
3331
3332 dev->mtu = 1500;
3333 dev->min_mtu = 50;
3334 dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN;
3335 dev->netdev_ops = &gfar_netdev_ops;
3336 dev->ethtool_ops = &gfar_ethtool_ops;
3337
3338
3339 for (i = 0; i < priv->num_grps; i++) {
3340 if (priv->poll_mode == GFAR_SQ_POLLING) {
3341 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3342 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
3343 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3344 gfar_poll_tx_sq, 2);
3345 } else {
3346 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3347 gfar_poll_rx, GFAR_DEV_WEIGHT);
3348 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3349 gfar_poll_tx, 2);
3350 }
3351 }
3352
3353 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
3354 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3355 NETIF_F_RXCSUM;
3356 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
3357 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
3358 }
3359
3360 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
3361 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
3362 NETIF_F_HW_VLAN_CTAG_RX;
3363 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3364 }
3365
3366 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3367
3368 gfar_init_addr_hash_table(priv);
3369
3370
3371
3372
3373 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3374 priv->padding = 8 + DEFAULT_PADDING;
3375
3376 if (dev->features & NETIF_F_IP_CSUM ||
3377 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3378 dev->needed_headroom = GMAC_FCB_LEN;
3379
3380
3381 for (i = 0; i < priv->num_tx_queues; i++) {
3382 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
3383 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
3384 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
3385 priv->tx_queue[i]->txic = DEFAULT_TXIC;
3386 }
3387
3388 for (i = 0; i < priv->num_rx_queues; i++) {
3389 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
3390 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
3391 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
3392 }
3393
3394
3395 priv->rx_filer_enable =
3396 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
3397
3398 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
3399
3400 if (priv->num_tx_queues == 1)
3401 priv->prio_sched_en = 1;
3402
3403 set_bit(GFAR_DOWN, &priv->state);
3404
3405 gfar_hw_init(priv);
3406
3407
3408 netif_carrier_off(dev);
3409
3410 err = register_netdev(dev);
3411
3412 if (err) {
3413 pr_err("%s: Cannot register net device, aborting\n", dev->name);
3414 goto register_fail;
3415 }
3416
3417 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
3418 priv->wol_supported |= GFAR_WOL_MAGIC;
3419
3420 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
3421 priv->rx_filer_enable)
3422 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
3423
3424 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
3425
3426
3427 for (i = 0; i < priv->num_grps; i++) {
3428 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3429 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3430 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
3431 dev->name, "_g", '0' + i, "_tx");
3432 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
3433 dev->name, "_g", '0' + i, "_rx");
3434 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
3435 dev->name, "_g", '0' + i, "_er");
3436 } else
3437 strcpy(gfar_irq(grp, TX)->name, dev->name);
3438 }
3439
3440
3441 gfar_init_filer_table(priv);
3442
3443
3444 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
3445
3446
3447
3448
3449 netdev_info(dev, "Running with NAPI enabled\n");
3450 for (i = 0; i < priv->num_rx_queues; i++)
3451 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
3452 i, priv->rx_queue[i]->rx_ring_size);
3453 for (i = 0; i < priv->num_tx_queues; i++)
3454 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
3455 i, priv->tx_queue[i]->tx_ring_size);
3456
3457 return 0;
3458
3459 register_fail:
3460 if (of_phy_is_fixed_link(np))
3461 of_phy_deregister_fixed_link(np);
3462 unmap_group_regs(priv);
3463 gfar_free_rx_queues(priv);
3464 gfar_free_tx_queues(priv);
3465 of_node_put(priv->phy_node);
3466 of_node_put(priv->tbi_node);
3467 free_gfar_dev(priv);
3468 return err;
3469 }
3470
3471 static int gfar_remove(struct platform_device *ofdev)
3472 {
3473 struct gfar_private *priv = platform_get_drvdata(ofdev);
3474 struct device_node *np = ofdev->dev.of_node;
3475
3476 of_node_put(priv->phy_node);
3477 of_node_put(priv->tbi_node);
3478
3479 unregister_netdev(priv->ndev);
3480
3481 if (of_phy_is_fixed_link(np))
3482 of_phy_deregister_fixed_link(np);
3483
3484 unmap_group_regs(priv);
3485 gfar_free_rx_queues(priv);
3486 gfar_free_tx_queues(priv);
3487 free_gfar_dev(priv);
3488
3489 return 0;
3490 }
3491
3492 #ifdef CONFIG_PM
3493
3494 static void __gfar_filer_disable(struct gfar_private *priv)
3495 {
3496 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3497 u32 temp;
3498
3499 temp = gfar_read(®s->rctrl);
3500 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
3501 gfar_write(®s->rctrl, temp);
3502 }
3503
3504 static void __gfar_filer_enable(struct gfar_private *priv)
3505 {
3506 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3507 u32 temp;
3508
3509 temp = gfar_read(®s->rctrl);
3510 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
3511 gfar_write(®s->rctrl, temp);
3512 }
3513
3514
3515 static void gfar_filer_config_wol(struct gfar_private *priv)
3516 {
3517 unsigned int i;
3518 u32 rqfcr;
3519
3520 __gfar_filer_disable(priv);
3521
3522
3523 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
3524 for (i = 0; i <= MAX_FILER_IDX; i++)
3525 gfar_write_filer(priv, i, rqfcr, 0);
3526
3527 i = 0;
3528 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
3529
3530 struct net_device *ndev = priv->ndev;
3531
3532 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
3533 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
3534 (ndev->dev_addr[1] << 8) |
3535 ndev->dev_addr[2];
3536
3537 rqfcr = (qindex << 10) | RQFCR_AND |
3538 RQFCR_CMP_EXACT | RQFCR_PID_DAH;
3539
3540 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3541
3542 dest_mac_addr = (ndev->dev_addr[3] << 16) |
3543 (ndev->dev_addr[4] << 8) |
3544 ndev->dev_addr[5];
3545 rqfcr = (qindex << 10) | RQFCR_GPI |
3546 RQFCR_CMP_EXACT | RQFCR_PID_DAL;
3547 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3548 }
3549
3550 __gfar_filer_enable(priv);
3551 }
3552
3553 static void gfar_filer_restore_table(struct gfar_private *priv)
3554 {
3555 u32 rqfcr, rqfpr;
3556 unsigned int i;
3557
3558 __gfar_filer_disable(priv);
3559
3560 for (i = 0; i <= MAX_FILER_IDX; i++) {
3561 rqfcr = priv->ftp_rqfcr[i];
3562 rqfpr = priv->ftp_rqfpr[i];
3563 gfar_write_filer(priv, i, rqfcr, rqfpr);
3564 }
3565
3566 __gfar_filer_enable(priv);
3567 }
3568
3569
3570 static void gfar_start_wol_filer(struct gfar_private *priv)
3571 {
3572 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3573 u32 tempval;
3574 int i = 0;
3575
3576
3577 gfar_write(®s->rqueue, priv->rqueue);
3578
3579
3580 tempval = gfar_read(®s->dmactrl);
3581 tempval |= DMACTRL_INIT_SETTINGS;
3582 gfar_write(®s->dmactrl, tempval);
3583
3584
3585 tempval = gfar_read(®s->dmactrl);
3586 tempval &= ~DMACTRL_GRS;
3587 gfar_write(®s->dmactrl, tempval);
3588
3589 for (i = 0; i < priv->num_grps; i++) {
3590 regs = priv->gfargrp[i].regs;
3591
3592 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
3593
3594 gfar_write(®s->imask, IMASK_FGPI);
3595 }
3596
3597
3598 tempval = gfar_read(®s->maccfg1);
3599 tempval |= MACCFG1_RX_EN;
3600 gfar_write(®s->maccfg1, tempval);
3601 }
3602
3603 static int gfar_suspend(struct device *dev)
3604 {
3605 struct gfar_private *priv = dev_get_drvdata(dev);
3606 struct net_device *ndev = priv->ndev;
3607 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3608 u32 tempval;
3609 u16 wol = priv->wol_opts;
3610
3611 if (!netif_running(ndev))
3612 return 0;
3613
3614 disable_napi(priv);
3615 netif_tx_lock(ndev);
3616 netif_device_detach(ndev);
3617 netif_tx_unlock(ndev);
3618
3619 gfar_halt(priv);
3620
3621 if (wol & GFAR_WOL_MAGIC) {
3622
3623 gfar_write(®s->imask, IMASK_MAG);
3624
3625
3626 tempval = gfar_read(®s->maccfg2);
3627 tempval |= MACCFG2_MPEN;
3628 gfar_write(®s->maccfg2, tempval);
3629
3630
3631 tempval = gfar_read(®s->maccfg1);
3632 tempval |= MACCFG1_RX_EN;
3633 gfar_write(®s->maccfg1, tempval);
3634
3635 } else if (wol & GFAR_WOL_FILER_UCAST) {
3636 gfar_filer_config_wol(priv);
3637 gfar_start_wol_filer(priv);
3638
3639 } else {
3640 phy_stop(ndev->phydev);
3641 }
3642
3643 return 0;
3644 }
3645
3646 static int gfar_resume(struct device *dev)
3647 {
3648 struct gfar_private *priv = dev_get_drvdata(dev);
3649 struct net_device *ndev = priv->ndev;
3650 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3651 u32 tempval;
3652 u16 wol = priv->wol_opts;
3653
3654 if (!netif_running(ndev))
3655 return 0;
3656
3657 if (wol & GFAR_WOL_MAGIC) {
3658
3659 tempval = gfar_read(®s->maccfg2);
3660 tempval &= ~MACCFG2_MPEN;
3661 gfar_write(®s->maccfg2, tempval);
3662
3663 } else if (wol & GFAR_WOL_FILER_UCAST) {
3664
3665 gfar_halt(priv);
3666 gfar_filer_restore_table(priv);
3667
3668 } else {
3669 phy_start(ndev->phydev);
3670 }
3671
3672 gfar_start(priv);
3673
3674 netif_device_attach(ndev);
3675 enable_napi(priv);
3676
3677 return 0;
3678 }
3679
3680 static int gfar_restore(struct device *dev)
3681 {
3682 struct gfar_private *priv = dev_get_drvdata(dev);
3683 struct net_device *ndev = priv->ndev;
3684
3685 if (!netif_running(ndev)) {
3686 netif_device_attach(ndev);
3687
3688 return 0;
3689 }
3690
3691 gfar_init_bds(ndev);
3692
3693 gfar_mac_reset(priv);
3694
3695 gfar_init_tx_rx_base(priv);
3696
3697 gfar_start(priv);
3698
3699 priv->oldlink = 0;
3700 priv->oldspeed = 0;
3701 priv->oldduplex = -1;
3702
3703 if (ndev->phydev)
3704 phy_start(ndev->phydev);
3705
3706 netif_device_attach(ndev);
3707 enable_napi(priv);
3708
3709 return 0;
3710 }
3711
3712 static const struct dev_pm_ops gfar_pm_ops = {
3713 .suspend = gfar_suspend,
3714 .resume = gfar_resume,
3715 .freeze = gfar_suspend,
3716 .thaw = gfar_resume,
3717 .restore = gfar_restore,
3718 };
3719
3720 #define GFAR_PM_OPS (&gfar_pm_ops)
3721
3722 #else
3723
3724 #define GFAR_PM_OPS NULL
3725
3726 #endif
3727
3728 static const struct of_device_id gfar_match[] =
3729 {
3730 {
3731 .type = "network",
3732 .compatible = "gianfar",
3733 },
3734 {
3735 .compatible = "fsl,etsec2",
3736 },
3737 {},
3738 };
3739 MODULE_DEVICE_TABLE(of, gfar_match);
3740
3741
3742 static struct platform_driver gfar_driver = {
3743 .driver = {
3744 .name = "fsl-gianfar",
3745 .pm = GFAR_PM_OPS,
3746 .of_match_table = gfar_match,
3747 },
3748 .probe = gfar_probe,
3749 .remove = gfar_remove,
3750 };
3751
3752 module_platform_driver(gfar_driver);