root/drivers/net/ethernet/freescale/gianfar.h

INCLUDED FROM

DEFINITIONS

1. gfar_has_errata
2. gfar_read
3. gfar_write
4. gfar_write_filer
5. gfar_read_filer
6. gfar_write_isrg
7. gfar_is_dma_stopped
8. gfar_is_rx_dma_stopped
9. gfar_wmb
10. gfar_clear_txbd_status
11. gfar_rxbd_unused
12. gfar_rxbd_dma_lastfree

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * drivers/net/ethernet/freescale/gianfar.h
   4  *
   5  * Gianfar Ethernet Driver
   6  * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12  *
  13  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  14  *
  15  *  Still left to do:
  16  *      -Add support for module parameters
  17  *      -Add patch for ethtool phys id
  18  */
  19 #ifndef __GIANFAR_H
  20 #define __GIANFAR_H
  21 
  22 #include <linux/kernel.h>
  23 #include <linux/sched.h>
  24 #include <linux/string.h>
  25 #include <linux/errno.h>
  26 #include <linux/slab.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/skbuff.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/mm.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/module.h>
  41 #include <linux/crc32.h>
  42 #include <linux/workqueue.h>
  43 #include <linux/ethtool.h>
  44 
  45 struct ethtool_flow_spec_container {
  46         struct ethtool_rx_flow_spec fs;
  47         struct list_head list;
  48 };
  49 
  50 struct ethtool_rx_list {
  51         struct list_head list;
  52         unsigned int count;
  53 };
  54 
  55 /* The maximum number of packets to be handled in one call of gfar_poll */
  56 #define GFAR_DEV_WEIGHT 64
  57 
  58 /* Length for FCB */
  59 #define GMAC_FCB_LEN 8
  60 
  61 /* Length for TxPAL */
  62 #define GMAC_TXPAL_LEN 16
  63 
  64 /* Default padding amount */
  65 #define DEFAULT_PADDING 2
  66 
  67 /* Number of bytes to align the rx bufs to */
  68 #define RXBUF_ALIGNMENT 64
  69 
  70 #define DRV_NAME "gfar-enet"
  71 extern const char gfar_driver_version[];
  72 
  73 /* MAXIMUM NUMBER OF QUEUES SUPPORTED */
  74 #define MAX_TX_QS       0x8
  75 #define MAX_RX_QS       0x8
  76 
  77 /* MAXIMUM NUMBER OF GROUPS SUPPORTED */
  78 #define MAXGROUPS 0x2
  79 
  80 /* These need to be powers of 2 for this driver */
  81 #define DEFAULT_TX_RING_SIZE    256
  82 #define DEFAULT_RX_RING_SIZE    256
  83 
  84 #define GFAR_RX_BUFF_ALLOC      16
  85 
  86 #define GFAR_RX_MAX_RING_SIZE   256
  87 #define GFAR_TX_MAX_RING_SIZE   256
  88 
  89 #define FBTHR_SHIFT        24
  90 #define DEFAULT_RX_LFC_THR  16
  91 #define DEFAULT_LFC_PTVVAL  4
  92 
  93 /* prevent fragmenation by HW in DSA environments */
  94 #define GFAR_RXB_SIZE roundup(1536 + 8, 64)
  95 #define GFAR_SKBFRAG_SIZE (RXBUF_ALIGNMENT + GFAR_RXB_SIZE \
  96                           + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
  97 #define GFAR_RXB_TRUESIZE 2048
  98 
  99 #define TX_RING_MOD_MASK(size) (size-1)
 100 #define RX_RING_MOD_MASK(size) (size-1)
 101 #define GFAR_JUMBO_FRAME_SIZE 9600
 102 
 103 #define DEFAULT_FIFO_TX_THR 0x100
 104 #define DEFAULT_FIFO_TX_STARVE 0x40
 105 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
 106 
 107 /* The number of Exact Match registers */
 108 #define GFAR_EM_NUM     15
 109 
 110 /* Latency of interface clock in nanoseconds */
 111 /* Interface clock latency , in this case, means the
 112  * time described by a value of 1 in the interrupt
 113  * coalescing registers' time fields.  Since those fields
 114  * refer to the time it takes for 64 clocks to pass, the
 115  * latencies are as such:
 116  * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
 117  * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
 118  * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
 119  */
 120 #define GFAR_GBIT_TIME  512
 121 #define GFAR_100_TIME   2560
 122 #define GFAR_10_TIME    25600
 123 
 124 #define DEFAULT_TX_COALESCE 1
 125 #define DEFAULT_TXCOUNT 16
 126 #define DEFAULT_TXTIME  21
 127 
 128 #define DEFAULT_RXTIME  21
 129 
 130 #define DEFAULT_RX_COALESCE 0
 131 #define DEFAULT_RXCOUNT 0
 132 
 133 /* TBI register addresses */
 134 #define MII_TBICON              0x11
 135 
 136 /* TBICON register bit fields */
 137 #define TBICON_CLK_SELECT       0x0020
 138 
 139 /* MAC register bits */
 140 #define MACCFG1_SOFT_RESET      0x80000000
 141 #define MACCFG1_RESET_RX_MC     0x00080000
 142 #define MACCFG1_RESET_TX_MC     0x00040000
 143 #define MACCFG1_RESET_RX_FUN    0x00020000
 144 #define MACCFG1_RESET_TX_FUN    0x00010000
 145 #define MACCFG1_LOOPBACK        0x00000100
 146 #define MACCFG1_RX_FLOW         0x00000020
 147 #define MACCFG1_TX_FLOW         0x00000010
 148 #define MACCFG1_SYNCD_RX_EN     0x00000008
 149 #define MACCFG1_RX_EN           0x00000004
 150 #define MACCFG1_SYNCD_TX_EN     0x00000002
 151 #define MACCFG1_TX_EN           0x00000001
 152 
 153 #define MACCFG2_INIT_SETTINGS   0x00007205
 154 #define MACCFG2_FULL_DUPLEX     0x00000001
 155 #define MACCFG2_IF              0x00000300
 156 #define MACCFG2_MII             0x00000100
 157 #define MACCFG2_GMII            0x00000200
 158 #define MACCFG2_HUGEFRAME       0x00000020
 159 #define MACCFG2_LENGTHCHECK     0x00000010
 160 #define MACCFG2_MPEN            0x00000008
 161 
 162 #define ECNTRL_FIFM             0x00008000
 163 #define ECNTRL_INIT_SETTINGS    0x00001000
 164 #define ECNTRL_TBI_MODE         0x00000020
 165 #define ECNTRL_REDUCED_MODE     0x00000010
 166 #define ECNTRL_R100             0x00000008
 167 #define ECNTRL_REDUCED_MII_MODE 0x00000004
 168 #define ECNTRL_SGMII_MODE       0x00000002
 169 
 170 #define MINFLR_INIT_SETTINGS    0x00000040
 171 
 172 /* Tqueue control */
 173 #define TQUEUE_EN0              0x00008000
 174 #define TQUEUE_EN1              0x00004000
 175 #define TQUEUE_EN2              0x00002000
 176 #define TQUEUE_EN3              0x00001000
 177 #define TQUEUE_EN4              0x00000800
 178 #define TQUEUE_EN5              0x00000400
 179 #define TQUEUE_EN6              0x00000200
 180 #define TQUEUE_EN7              0x00000100
 181 #define TQUEUE_EN_ALL           0x0000FF00
 182 
 183 #define TR03WT_WT0_MASK         0xFF000000
 184 #define TR03WT_WT1_MASK         0x00FF0000
 185 #define TR03WT_WT2_MASK         0x0000FF00
 186 #define TR03WT_WT3_MASK         0x000000FF
 187 
 188 #define TR47WT_WT4_MASK         0xFF000000
 189 #define TR47WT_WT5_MASK         0x00FF0000
 190 #define TR47WT_WT6_MASK         0x0000FF00
 191 #define TR47WT_WT7_MASK         0x000000FF
 192 
 193 /* Rqueue control */
 194 #define RQUEUE_EX0              0x00800000
 195 #define RQUEUE_EX1              0x00400000
 196 #define RQUEUE_EX2              0x00200000
 197 #define RQUEUE_EX3              0x00100000
 198 #define RQUEUE_EX4              0x00080000
 199 #define RQUEUE_EX5              0x00040000
 200 #define RQUEUE_EX6              0x00020000
 201 #define RQUEUE_EX7              0x00010000
 202 #define RQUEUE_EX_ALL           0x00FF0000
 203 
 204 #define RQUEUE_EN0              0x00000080
 205 #define RQUEUE_EN1              0x00000040
 206 #define RQUEUE_EN2              0x00000020
 207 #define RQUEUE_EN3              0x00000010
 208 #define RQUEUE_EN4              0x00000008
 209 #define RQUEUE_EN5              0x00000004
 210 #define RQUEUE_EN6              0x00000002
 211 #define RQUEUE_EN7              0x00000001
 212 #define RQUEUE_EN_ALL           0x000000FF
 213 
 214 /* Init to do tx snooping for buffers and descriptors */
 215 #define DMACTRL_INIT_SETTINGS   0x000000c3
 216 #define DMACTRL_GRS             0x00000010
 217 #define DMACTRL_GTS             0x00000008
 218 
 219 #define TSTAT_CLEAR_THALT_ALL   0xFF000000
 220 #define TSTAT_CLEAR_THALT       0x80000000
 221 #define TSTAT_CLEAR_THALT0      0x80000000
 222 #define TSTAT_CLEAR_THALT1      0x40000000
 223 #define TSTAT_CLEAR_THALT2      0x20000000
 224 #define TSTAT_CLEAR_THALT3      0x10000000
 225 #define TSTAT_CLEAR_THALT4      0x08000000
 226 #define TSTAT_CLEAR_THALT5      0x04000000
 227 #define TSTAT_CLEAR_THALT6      0x02000000
 228 #define TSTAT_CLEAR_THALT7      0x01000000
 229 
 230 /* Interrupt coalescing macros */
 231 #define IC_ICEN                 0x80000000
 232 #define IC_ICFT_MASK            0x1fe00000
 233 #define IC_ICFT_SHIFT           21
 234 #define mk_ic_icft(x)           \
 235         (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
 236 #define IC_ICTT_MASK            0x0000ffff
 237 #define mk_ic_ictt(x)           (x&IC_ICTT_MASK)
 238 
 239 #define mk_ic_value(count, time) (IC_ICEN | \
 240                                 mk_ic_icft(count) | \
 241                                 mk_ic_ictt(time))
 242 #define get_icft_value(ic)      (((unsigned long)ic & IC_ICFT_MASK) >> \
 243                                  IC_ICFT_SHIFT)
 244 #define get_ictt_value(ic)      ((unsigned long)ic & IC_ICTT_MASK)
 245 
 246 #define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
 247 #define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
 248 
 249 #define RCTRL_TS_ENABLE         0x01000000
 250 #define RCTRL_PAL_MASK          0x001f0000
 251 #define RCTRL_LFC               0x00004000
 252 #define RCTRL_VLEX              0x00002000
 253 #define RCTRL_FILREN            0x00001000
 254 #define RCTRL_GHTX              0x00000400
 255 #define RCTRL_IPCSEN            0x00000200
 256 #define RCTRL_TUCSEN            0x00000100
 257 #define RCTRL_PRSDEP_MASK       0x000000c0
 258 #define RCTRL_PRSDEP_INIT       0x000000c0
 259 #define RCTRL_PRSFM             0x00000020
 260 #define RCTRL_PROM              0x00000008
 261 #define RCTRL_EMEN              0x00000002
 262 #define RCTRL_REQ_PARSER        (RCTRL_VLEX | RCTRL_IPCSEN | \
 263                                  RCTRL_TUCSEN | RCTRL_FILREN)
 264 #define RCTRL_CHECKSUMMING      (RCTRL_IPCSEN | RCTRL_TUCSEN | \
 265                                 RCTRL_PRSDEP_INIT)
 266 #define RCTRL_EXTHASH           (RCTRL_GHTX)
 267 #define RCTRL_VLAN              (RCTRL_PRSDEP_INIT)
 268 #define RCTRL_PADDING(x)        ((x << 16) & RCTRL_PAL_MASK)
 269 
 270 
 271 #define RSTAT_CLEAR_RHALT       0x00800000
 272 #define RSTAT_CLEAR_RXF0        0x00000080
 273 #define RSTAT_RXF_MASK          0x000000ff
 274 
 275 #define TCTRL_IPCSEN            0x00004000
 276 #define TCTRL_TUCSEN            0x00002000
 277 #define TCTRL_VLINS             0x00001000
 278 #define TCTRL_THDF              0x00000800
 279 #define TCTRL_RFCPAUSE          0x00000010
 280 #define TCTRL_TFCPAUSE          0x00000008
 281 #define TCTRL_TXSCHED_MASK      0x00000006
 282 #define TCTRL_TXSCHED_INIT      0x00000000
 283 /* priority scheduling */
 284 #define TCTRL_TXSCHED_PRIO      0x00000002
 285 /* weighted round-robin scheduling (WRRS) */
 286 #define TCTRL_TXSCHED_WRRS      0x00000004
 287 /* default WRRS weight and policy setting,
 288  * tailored to the tr03wt and tr47wt registers:
 289  * equal weight for all Tx Qs, measured in 64byte units
 290  */
 291 #define DEFAULT_WRRS_WEIGHT     0x18181818
 292 
 293 #define TCTRL_INIT_CSUM         (TCTRL_TUCSEN | TCTRL_IPCSEN)
 294 
 295 #define IEVENT_INIT_CLEAR       0xffffffff
 296 #define IEVENT_BABR             0x80000000
 297 #define IEVENT_RXC              0x40000000
 298 #define IEVENT_BSY              0x20000000
 299 #define IEVENT_EBERR            0x10000000
 300 #define IEVENT_MSRO             0x04000000
 301 #define IEVENT_GTSC             0x02000000
 302 #define IEVENT_BABT             0x01000000
 303 #define IEVENT_TXC              0x00800000
 304 #define IEVENT_TXE              0x00400000
 305 #define IEVENT_TXB              0x00200000
 306 #define IEVENT_TXF              0x00100000
 307 #define IEVENT_LC               0x00040000
 308 #define IEVENT_CRL              0x00020000
 309 #define IEVENT_XFUN             0x00010000
 310 #define IEVENT_RXB0             0x00008000
 311 #define IEVENT_MAG              0x00000800
 312 #define IEVENT_GRSC             0x00000100
 313 #define IEVENT_RXF0             0x00000080
 314 #define IEVENT_FGPI             0x00000010
 315 #define IEVENT_FIR              0x00000008
 316 #define IEVENT_FIQ              0x00000004
 317 #define IEVENT_DPE              0x00000002
 318 #define IEVENT_PERR             0x00000001
 319 #define IEVENT_RX_MASK          (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
 320 #define IEVENT_TX_MASK          (IEVENT_TXB | IEVENT_TXF)
 321 #define IEVENT_RTX_MASK         (IEVENT_RX_MASK | IEVENT_TX_MASK)
 322 #define IEVENT_ERR_MASK         \
 323 (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
 324  IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
 325  | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
 326  | IEVENT_MAG | IEVENT_BABR)
 327 
 328 #define IMASK_INIT_CLEAR        0x00000000
 329 #define IMASK_BABR              0x80000000
 330 #define IMASK_RXC               0x40000000
 331 #define IMASK_BSY               0x20000000
 332 #define IMASK_EBERR             0x10000000
 333 #define IMASK_MSRO              0x04000000
 334 #define IMASK_GTSC              0x02000000
 335 #define IMASK_BABT              0x01000000
 336 #define IMASK_TXC               0x00800000
 337 #define IMASK_TXEEN             0x00400000
 338 #define IMASK_TXBEN             0x00200000
 339 #define IMASK_TXFEN             0x00100000
 340 #define IMASK_LC                0x00040000
 341 #define IMASK_CRL               0x00020000
 342 #define IMASK_XFUN              0x00010000
 343 #define IMASK_RXB0              0x00008000
 344 #define IMASK_MAG               0x00000800
 345 #define IMASK_GRSC              0x00000100
 346 #define IMASK_RXFEN0            0x00000080
 347 #define IMASK_FGPI              0x00000010
 348 #define IMASK_FIR               0x00000008
 349 #define IMASK_FIQ               0x00000004
 350 #define IMASK_DPE               0x00000002
 351 #define IMASK_PERR              0x00000001
 352 #define IMASK_DEFAULT  (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
 353                 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
 354                 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
 355                 | IMASK_PERR)
 356 #define IMASK_RX_DEFAULT (IMASK_RXFEN0 | IMASK_BSY)
 357 #define IMASK_TX_DEFAULT (IMASK_TXFEN | IMASK_TXBEN)
 358 
 359 #define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT)
 360 #define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT)
 361 
 362 /* Attribute fields */
 363 
 364 /* This enables rx snooping for buffers and descriptors */
 365 #define ATTR_BDSTASH            0x00000800
 366 
 367 #define ATTR_BUFSTASH           0x00004000
 368 
 369 #define ATTR_SNOOPING           0x000000c0
 370 #define ATTR_INIT_SETTINGS      ATTR_SNOOPING
 371 
 372 #define ATTRELI_INIT_SETTINGS   0x0
 373 #define ATTRELI_EL_MASK         0x3fff0000
 374 #define ATTRELI_EL(x) (x << 16)
 375 #define ATTRELI_EI_MASK         0x00003fff
 376 #define ATTRELI_EI(x) (x)
 377 
 378 #define BD_LFLAG(flags) ((flags) << 16)
 379 #define BD_LENGTH_MASK          0x0000ffff
 380 
 381 #define FPR_FILER_MASK  0xFFFFFFFF
 382 #define MAX_FILER_IDX   0xFF
 383 
 384 /* This default RIR value directly corresponds
 385  * to the 3-bit hash value generated */
 386 #define DEFAULT_8RXQ_RIR0       0x05397700
 387 /* Map even hash values to Q0, and odd ones to Q1 */
 388 #define DEFAULT_2RXQ_RIR0       0x04104100
 389 
 390 /* RQFCR register bits */
 391 #define RQFCR_GPI               0x80000000
 392 #define RQFCR_HASHTBL_Q         0x00000000
 393 #define RQFCR_HASHTBL_0         0x00020000
 394 #define RQFCR_HASHTBL_1         0x00040000
 395 #define RQFCR_HASHTBL_2         0x00060000
 396 #define RQFCR_HASHTBL_3         0x00080000
 397 #define RQFCR_HASH              0x00010000
 398 #define RQFCR_QUEUE             0x0000FC00
 399 #define RQFCR_CLE               0x00000200
 400 #define RQFCR_RJE               0x00000100
 401 #define RQFCR_AND               0x00000080
 402 #define RQFCR_CMP_EXACT         0x00000000
 403 #define RQFCR_CMP_MATCH         0x00000020
 404 #define RQFCR_CMP_NOEXACT       0x00000040
 405 #define RQFCR_CMP_NOMATCH       0x00000060
 406 
 407 /* RQFCR PID values */
 408 #define RQFCR_PID_MASK          0x00000000
 409 #define RQFCR_PID_PARSE         0x00000001
 410 #define RQFCR_PID_ARB           0x00000002
 411 #define RQFCR_PID_DAH           0x00000003
 412 #define RQFCR_PID_DAL           0x00000004
 413 #define RQFCR_PID_SAH           0x00000005
 414 #define RQFCR_PID_SAL           0x00000006
 415 #define RQFCR_PID_ETY           0x00000007
 416 #define RQFCR_PID_VID           0x00000008
 417 #define RQFCR_PID_PRI           0x00000009
 418 #define RQFCR_PID_TOS           0x0000000A
 419 #define RQFCR_PID_L4P           0x0000000B
 420 #define RQFCR_PID_DIA           0x0000000C
 421 #define RQFCR_PID_SIA           0x0000000D
 422 #define RQFCR_PID_DPT           0x0000000E
 423 #define RQFCR_PID_SPT           0x0000000F
 424 
 425 /* RQFPR when PID is 0x0001 */
 426 #define RQFPR_HDR_GE_512        0x00200000
 427 #define RQFPR_LERR              0x00100000
 428 #define RQFPR_RAR               0x00080000
 429 #define RQFPR_RARQ              0x00040000
 430 #define RQFPR_AR                0x00020000
 431 #define RQFPR_ARQ               0x00010000
 432 #define RQFPR_EBC               0x00008000
 433 #define RQFPR_VLN               0x00004000
 434 #define RQFPR_CFI               0x00002000
 435 #define RQFPR_JUM               0x00001000
 436 #define RQFPR_IPF               0x00000800
 437 #define RQFPR_FIF               0x00000400
 438 #define RQFPR_IPV4              0x00000200
 439 #define RQFPR_IPV6              0x00000100
 440 #define RQFPR_ICC               0x00000080
 441 #define RQFPR_ICV               0x00000040
 442 #define RQFPR_TCP               0x00000020
 443 #define RQFPR_UDP               0x00000010
 444 #define RQFPR_TUC               0x00000008
 445 #define RQFPR_TUV               0x00000004
 446 #define RQFPR_PER               0x00000002
 447 #define RQFPR_EER               0x00000001
 448 
 449 /* TxBD status field bits */
 450 #define TXBD_READY              0x8000
 451 #define TXBD_PADCRC             0x4000
 452 #define TXBD_WRAP               0x2000
 453 #define TXBD_INTERRUPT          0x1000
 454 #define TXBD_LAST               0x0800
 455 #define TXBD_CRC                0x0400
 456 #define TXBD_DEF                0x0200
 457 #define TXBD_HUGEFRAME          0x0080
 458 #define TXBD_LATECOLLISION      0x0080
 459 #define TXBD_RETRYLIMIT         0x0040
 460 #define TXBD_RETRYCOUNTMASK     0x003c
 461 #define TXBD_UNDERRUN           0x0002
 462 #define TXBD_TOE                0x0002
 463 
 464 /* Tx FCB param bits */
 465 #define TXFCB_VLN               0x80
 466 #define TXFCB_IP                0x40
 467 #define TXFCB_IP6               0x20
 468 #define TXFCB_TUP               0x10
 469 #define TXFCB_UDP               0x08
 470 #define TXFCB_CIP               0x04
 471 #define TXFCB_CTU               0x02
 472 #define TXFCB_NPH               0x01
 473 #define TXFCB_DEFAULT           (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
 474 
 475 /* RxBD status field bits */
 476 #define RXBD_EMPTY              0x8000
 477 #define RXBD_RO1                0x4000
 478 #define RXBD_WRAP               0x2000
 479 #define RXBD_INTERRUPT          0x1000
 480 #define RXBD_LAST               0x0800
 481 #define RXBD_FIRST              0x0400
 482 #define RXBD_MISS               0x0100
 483 #define RXBD_BROADCAST          0x0080
 484 #define RXBD_MULTICAST          0x0040
 485 #define RXBD_LARGE              0x0020
 486 #define RXBD_NONOCTET           0x0010
 487 #define RXBD_SHORT              0x0008
 488 #define RXBD_CRCERR             0x0004
 489 #define RXBD_OVERRUN            0x0002
 490 #define RXBD_TRUNCATED          0x0001
 491 #define RXBD_STATS              0x01ff
 492 #define RXBD_ERR                (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET        \
 493                                 | RXBD_CRCERR | RXBD_OVERRUN                    \
 494                                 | RXBD_TRUNCATED)
 495 
 496 /* Rx FCB status field bits */
 497 #define RXFCB_VLN               0x8000
 498 #define RXFCB_IP                0x4000
 499 #define RXFCB_IP6               0x2000
 500 #define RXFCB_TUP               0x1000
 501 #define RXFCB_CIP               0x0800
 502 #define RXFCB_CTU               0x0400
 503 #define RXFCB_EIP               0x0200
 504 #define RXFCB_ETU               0x0100
 505 #define RXFCB_CSUM_MASK         0x0f00
 506 #define RXFCB_PERR_MASK         0x000c
 507 #define RXFCB_PERR_BADL3        0x0008
 508 
 509 #define GFAR_INT_NAME_MAX       (IFNAMSIZ + 6)  /* '_g#_xx' */
 510 
 511 #define GFAR_WOL_MAGIC          0x00000001
 512 #define GFAR_WOL_FILER_UCAST    0x00000002
 513 
 514 struct txbd8
 515 {
 516         union {
 517                 struct {
 518                         __be16  status; /* Status Fields */
 519                         __be16  length; /* Buffer length */
 520                 };
 521                 __be32 lstatus;
 522         };
 523         __be32  bufPtr; /* Buffer Pointer */
 524 };
 525 
 526 struct txfcb {
 527         u8      flags;
 528         u8      ptp;    /* Flag to enable tx timestamping */
 529         u8      l4os;   /* Level 4 Header Offset */
 530         u8      l3os;   /* Level 3 Header Offset */
 531         __be16  phcs;   /* Pseudo-header Checksum */
 532         __be16  vlctl;  /* VLAN control word */
 533 };
 534 
 535 struct rxbd8
 536 {
 537         union {
 538                 struct {
 539                         __be16  status; /* Status Fields */
 540                         __be16  length; /* Buffer Length */
 541                 };
 542                 __be32 lstatus;
 543         };
 544         __be32  bufPtr; /* Buffer Pointer */
 545 };
 546 
 547 struct rxfcb {
 548         __be16  flags;
 549         u8      rq;     /* Receive Queue index */
 550         u8      pro;    /* Layer 4 Protocol */
 551         u16     reserved;
 552         __be16  vlctl;  /* VLAN control word */
 553 };
 554 
 555 struct gianfar_skb_cb {
 556         unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */
 557 };
 558 
 559 #define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
 560 
 561 struct rmon_mib
 562 {
 563         u32     tr64;   /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
 564         u32     tr127;  /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
 565         u32     tr255;  /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
 566         u32     tr511;  /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
 567         u32     tr1k;   /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
 568         u32     trmax;  /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
 569         u32     trmgv;  /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
 570         u32     rbyt;   /* 0x.69c - Receive Byte Counter */
 571         u32     rpkt;   /* 0x.6a0 - Receive Packet Counter */
 572         u32     rfcs;   /* 0x.6a4 - Receive FCS Error Counter */
 573         u32     rmca;   /* 0x.6a8 - Receive Multicast Packet Counter */
 574         u32     rbca;   /* 0x.6ac - Receive Broadcast Packet Counter */
 575         u32     rxcf;   /* 0x.6b0 - Receive Control Frame Packet Counter */
 576         u32     rxpf;   /* 0x.6b4 - Receive Pause Frame Packet Counter */
 577         u32     rxuo;   /* 0x.6b8 - Receive Unknown OP Code Counter */
 578         u32     raln;   /* 0x.6bc - Receive Alignment Error Counter */
 579         u32     rflr;   /* 0x.6c0 - Receive Frame Length Error Counter */
 580         u32     rcde;   /* 0x.6c4 - Receive Code Error Counter */
 581         u32     rcse;   /* 0x.6c8 - Receive Carrier Sense Error Counter */
 582         u32     rund;   /* 0x.6cc - Receive Undersize Packet Counter */
 583         u32     rovr;   /* 0x.6d0 - Receive Oversize Packet Counter */
 584         u32     rfrg;   /* 0x.6d4 - Receive Fragments Counter */
 585         u32     rjbr;   /* 0x.6d8 - Receive Jabber Counter */
 586         u32     rdrp;   /* 0x.6dc - Receive Drop Counter */
 587         u32     tbyt;   /* 0x.6e0 - Transmit Byte Counter Counter */
 588         u32     tpkt;   /* 0x.6e4 - Transmit Packet Counter */
 589         u32     tmca;   /* 0x.6e8 - Transmit Multicast Packet Counter */
 590         u32     tbca;   /* 0x.6ec - Transmit Broadcast Packet Counter */
 591         u32     txpf;   /* 0x.6f0 - Transmit Pause Control Frame Counter */
 592         u32     tdfr;   /* 0x.6f4 - Transmit Deferral Packet Counter */
 593         u32     tedf;   /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
 594         u32     tscl;   /* 0x.6fc - Transmit Single Collision Packet Counter */
 595         u32     tmcl;   /* 0x.700 - Transmit Multiple Collision Packet Counter */
 596         u32     tlcl;   /* 0x.704 - Transmit Late Collision Packet Counter */
 597         u32     txcl;   /* 0x.708 - Transmit Excessive Collision Packet Counter */
 598         u32     tncl;   /* 0x.70c - Transmit Total Collision Counter */
 599         u8      res1[4];
 600         u32     tdrp;   /* 0x.714 - Transmit Drop Frame Counter */
 601         u32     tjbr;   /* 0x.718 - Transmit Jabber Frame Counter */
 602         u32     tfcs;   /* 0x.71c - Transmit FCS Error Counter */
 603         u32     txcf;   /* 0x.720 - Transmit Control Frame Counter */
 604         u32     tovr;   /* 0x.724 - Transmit Oversize Frame Counter */
 605         u32     tund;   /* 0x.728 - Transmit Undersize Frame Counter */
 606         u32     tfrg;   /* 0x.72c - Transmit Fragments Frame Counter */
 607         u32     car1;   /* 0x.730 - Carry Register One */
 608         u32     car2;   /* 0x.734 - Carry Register Two */
 609         u32     cam1;   /* 0x.738 - Carry Mask Register One */
 610         u32     cam2;   /* 0x.73c - Carry Mask Register Two */
 611 };
 612 
 613 struct gfar_extra_stats {
 614         atomic64_t rx_alloc_err;
 615         atomic64_t rx_large;
 616         atomic64_t rx_short;
 617         atomic64_t rx_nonoctet;
 618         atomic64_t rx_crcerr;
 619         atomic64_t rx_overrun;
 620         atomic64_t rx_bsy;
 621         atomic64_t rx_babr;
 622         atomic64_t rx_trunc;
 623         atomic64_t eberr;
 624         atomic64_t tx_babt;
 625         atomic64_t tx_underrun;
 626         atomic64_t tx_timeout;
 627 };
 628 
 629 #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
 630 #define GFAR_EXTRA_STATS_LEN \
 631         (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t))
 632 
 633 /* Number of stats exported via ethtool */
 634 #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
 635 
 636 struct gfar {
 637         u32     tsec_id;        /* 0x.000 - Controller ID register */
 638         u32     tsec_id2;       /* 0x.004 - Controller ID2 register */
 639         u8      res1[8];
 640         u32     ievent;         /* 0x.010 - Interrupt Event Register */
 641         u32     imask;          /* 0x.014 - Interrupt Mask Register */
 642         u32     edis;           /* 0x.018 - Error Disabled Register */
 643         u32     emapg;          /* 0x.01c - Group Error mapping register */
 644         u32     ecntrl;         /* 0x.020 - Ethernet Control Register */
 645         u32     minflr;         /* 0x.024 - Minimum Frame Length Register */
 646         u32     ptv;            /* 0x.028 - Pause Time Value Register */
 647         u32     dmactrl;        /* 0x.02c - DMA Control Register */
 648         u32     tbipa;          /* 0x.030 - TBI PHY Address Register */
 649         u8      res2[28];
 650         u32     fifo_rx_pause;  /* 0x.050 - FIFO receive pause start threshold
 651                                         register */
 652         u32     fifo_rx_pause_shutoff;  /* x.054 - FIFO receive starve shutoff
 653                                                 register */
 654         u32     fifo_rx_alarm;  /* 0x.058 - FIFO receive alarm start threshold
 655                                                 register */
 656         u32     fifo_rx_alarm_shutoff;  /*0x.05c - FIFO receive alarm  starve
 657                                                 shutoff register */
 658         u8      res3[44];
 659         u32     fifo_tx_thr;    /* 0x.08c - FIFO transmit threshold register */
 660         u8      res4[8];
 661         u32     fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
 662         u32     fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
 663         u8      res5[96];
 664         u32     tctrl;          /* 0x.100 - Transmit Control Register */
 665         u32     tstat;          /* 0x.104 - Transmit Status Register */
 666         u32     dfvlan;         /* 0x.108 - Default VLAN Control word */
 667         u32     tbdlen;         /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
 668         u32     txic;           /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
 669         u32     tqueue;         /* 0x.114 - Transmit queue control register */
 670         u8      res7[40];
 671         u32     tr03wt;         /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
 672         u32     tr47wt;         /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
 673         u8      res8[52];
 674         u32     tbdbph;         /* 0x.17c - Tx data buffer pointer high */
 675         u8      res9a[4];
 676         u32     tbptr0;         /* 0x.184 - TxBD Pointer for ring 0 */
 677         u8      res9b[4];
 678         u32     tbptr1;         /* 0x.18c - TxBD Pointer for ring 1 */
 679         u8      res9c[4];
 680         u32     tbptr2;         /* 0x.194 - TxBD Pointer for ring 2 */
 681         u8      res9d[4];
 682         u32     tbptr3;         /* 0x.19c - TxBD Pointer for ring 3 */
 683         u8      res9e[4];
 684         u32     tbptr4;         /* 0x.1a4 - TxBD Pointer for ring 4 */
 685         u8      res9f[4];
 686         u32     tbptr5;         /* 0x.1ac - TxBD Pointer for ring 5 */
 687         u8      res9g[4];
 688         u32     tbptr6;         /* 0x.1b4 - TxBD Pointer for ring 6 */
 689         u8      res9h[4];
 690         u32     tbptr7;         /* 0x.1bc - TxBD Pointer for ring 7 */
 691         u8      res9[64];
 692         u32     tbaseh;         /* 0x.200 - TxBD base address high */
 693         u32     tbase0;         /* 0x.204 - TxBD Base Address of ring 0 */
 694         u8      res10a[4];
 695         u32     tbase1;         /* 0x.20c - TxBD Base Address of ring 1 */
 696         u8      res10b[4];
 697         u32     tbase2;         /* 0x.214 - TxBD Base Address of ring 2 */
 698         u8      res10c[4];
 699         u32     tbase3;         /* 0x.21c - TxBD Base Address of ring 3 */
 700         u8      res10d[4];
 701         u32     tbase4;         /* 0x.224 - TxBD Base Address of ring 4 */
 702         u8      res10e[4];
 703         u32     tbase5;         /* 0x.22c - TxBD Base Address of ring 5 */
 704         u8      res10f[4];
 705         u32     tbase6;         /* 0x.234 - TxBD Base Address of ring 6 */
 706         u8      res10g[4];
 707         u32     tbase7;         /* 0x.23c - TxBD Base Address of ring 7 */
 708         u8      res10[192];
 709         u32     rctrl;          /* 0x.300 - Receive Control Register */
 710         u32     rstat;          /* 0x.304 - Receive Status Register */
 711         u8      res12[8];
 712         u32     rxic;           /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
 713         u32     rqueue;         /* 0x.314 - Receive queue control register */
 714         u32     rir0;           /* 0x.318 - Ring mapping register 0 */
 715         u32     rir1;           /* 0x.31c - Ring mapping register 1 */
 716         u32     rir2;           /* 0x.320 - Ring mapping register 2 */
 717         u32     rir3;           /* 0x.324 - Ring mapping register 3 */
 718         u8      res13[8];
 719         u32     rbifx;          /* 0x.330 - Receive bit field extract control register */
 720         u32     rqfar;          /* 0x.334 - Receive queue filing table address register */
 721         u32     rqfcr;          /* 0x.338 - Receive queue filing table control register */
 722         u32     rqfpr;          /* 0x.33c - Receive queue filing table property register */
 723         u32     mrblr;          /* 0x.340 - Maximum Receive Buffer Length Register */
 724         u8      res14[56];
 725         u32     rbdbph;         /* 0x.37c - Rx data buffer pointer high */
 726         u8      res15a[4];
 727         u32     rbptr0;         /* 0x.384 - RxBD pointer for ring 0 */
 728         u8      res15b[4];
 729         u32     rbptr1;         /* 0x.38c - RxBD pointer for ring 1 */
 730         u8      res15c[4];
 731         u32     rbptr2;         /* 0x.394 - RxBD pointer for ring 2 */
 732         u8      res15d[4];
 733         u32     rbptr3;         /* 0x.39c - RxBD pointer for ring 3 */
 734         u8      res15e[4];
 735         u32     rbptr4;         /* 0x.3a4 - RxBD pointer for ring 4 */
 736         u8      res15f[4];
 737         u32     rbptr5;         /* 0x.3ac - RxBD pointer for ring 5 */
 738         u8      res15g[4];
 739         u32     rbptr6;         /* 0x.3b4 - RxBD pointer for ring 6 */
 740         u8      res15h[4];
 741         u32     rbptr7;         /* 0x.3bc - RxBD pointer for ring 7 */
 742         u8      res16[64];
 743         u32     rbaseh;         /* 0x.400 - RxBD base address high */
 744         u32     rbase0;         /* 0x.404 - RxBD base address of ring 0 */
 745         u8      res17a[4];
 746         u32     rbase1;         /* 0x.40c - RxBD base address of ring 1 */
 747         u8      res17b[4];
 748         u32     rbase2;         /* 0x.414 - RxBD base address of ring 2 */
 749         u8      res17c[4];
 750         u32     rbase3;         /* 0x.41c - RxBD base address of ring 3 */
 751         u8      res17d[4];
 752         u32     rbase4;         /* 0x.424 - RxBD base address of ring 4 */
 753         u8      res17e[4];
 754         u32     rbase5;         /* 0x.42c - RxBD base address of ring 5 */
 755         u8      res17f[4];
 756         u32     rbase6;         /* 0x.434 - RxBD base address of ring 6 */
 757         u8      res17g[4];
 758         u32     rbase7;         /* 0x.43c - RxBD base address of ring 7 */
 759         u8      res17[192];
 760         u32     maccfg1;        /* 0x.500 - MAC Configuration 1 Register */
 761         u32     maccfg2;        /* 0x.504 - MAC Configuration 2 Register */
 762         u32     ipgifg;         /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
 763         u32     hafdup;         /* 0x.50c - Half Duplex Register */
 764         u32     maxfrm;         /* 0x.510 - Maximum Frame Length Register */
 765         u8      res18[12];
 766         u8      gfar_mii_regs[24];      /* See gianfar_phy.h */
 767         u32     ifctrl;         /* 0x.538 - Interface control register */
 768         u32     ifstat;         /* 0x.53c - Interface Status Register */
 769         u32     macstnaddr1;    /* 0x.540 - Station Address Part 1 Register */
 770         u32     macstnaddr2;    /* 0x.544 - Station Address Part 2 Register */
 771         u32     mac01addr1;     /* 0x.548 - MAC exact match address 1, part 1 */
 772         u32     mac01addr2;     /* 0x.54c - MAC exact match address 1, part 2 */
 773         u32     mac02addr1;     /* 0x.550 - MAC exact match address 2, part 1 */
 774         u32     mac02addr2;     /* 0x.554 - MAC exact match address 2, part 2 */
 775         u32     mac03addr1;     /* 0x.558 - MAC exact match address 3, part 1 */
 776         u32     mac03addr2;     /* 0x.55c - MAC exact match address 3, part 2 */
 777         u32     mac04addr1;     /* 0x.560 - MAC exact match address 4, part 1 */
 778         u32     mac04addr2;     /* 0x.564 - MAC exact match address 4, part 2 */
 779         u32     mac05addr1;     /* 0x.568 - MAC exact match address 5, part 1 */
 780         u32     mac05addr2;     /* 0x.56c - MAC exact match address 5, part 2 */
 781         u32     mac06addr1;     /* 0x.570 - MAC exact match address 6, part 1 */
 782         u32     mac06addr2;     /* 0x.574 - MAC exact match address 6, part 2 */
 783         u32     mac07addr1;     /* 0x.578 - MAC exact match address 7, part 1 */
 784         u32     mac07addr2;     /* 0x.57c - MAC exact match address 7, part 2 */
 785         u32     mac08addr1;     /* 0x.580 - MAC exact match address 8, part 1 */
 786         u32     mac08addr2;     /* 0x.584 - MAC exact match address 8, part 2 */
 787         u32     mac09addr1;     /* 0x.588 - MAC exact match address 9, part 1 */
 788         u32     mac09addr2;     /* 0x.58c - MAC exact match address 9, part 2 */
 789         u32     mac10addr1;     /* 0x.590 - MAC exact match address 10, part 1*/
 790         u32     mac10addr2;     /* 0x.594 - MAC exact match address 10, part 2*/
 791         u32     mac11addr1;     /* 0x.598 - MAC exact match address 11, part 1*/
 792         u32     mac11addr2;     /* 0x.59c - MAC exact match address 11, part 2*/
 793         u32     mac12addr1;     /* 0x.5a0 - MAC exact match address 12, part 1*/
 794         u32     mac12addr2;     /* 0x.5a4 - MAC exact match address 12, part 2*/
 795         u32     mac13addr1;     /* 0x.5a8 - MAC exact match address 13, part 1*/
 796         u32     mac13addr2;     /* 0x.5ac - MAC exact match address 13, part 2*/
 797         u32     mac14addr1;     /* 0x.5b0 - MAC exact match address 14, part 1*/
 798         u32     mac14addr2;     /* 0x.5b4 - MAC exact match address 14, part 2*/
 799         u32     mac15addr1;     /* 0x.5b8 - MAC exact match address 15, part 1*/
 800         u32     mac15addr2;     /* 0x.5bc - MAC exact match address 15, part 2*/
 801         u8      res20[192];
 802         struct rmon_mib rmon;   /* 0x.680-0x.73c */
 803         u32     rrej;           /* 0x.740 - Receive filer rejected packet counter */
 804         u8      res21[188];
 805         u32     igaddr0;        /* 0x.800 - Indivdual/Group address register 0*/
 806         u32     igaddr1;        /* 0x.804 - Indivdual/Group address register 1*/
 807         u32     igaddr2;        /* 0x.808 - Indivdual/Group address register 2*/
 808         u32     igaddr3;        /* 0x.80c - Indivdual/Group address register 3*/
 809         u32     igaddr4;        /* 0x.810 - Indivdual/Group address register 4*/
 810         u32     igaddr5;        /* 0x.814 - Indivdual/Group address register 5*/
 811         u32     igaddr6;        /* 0x.818 - Indivdual/Group address register 6*/
 812         u32     igaddr7;        /* 0x.81c - Indivdual/Group address register 7*/
 813         u8      res22[96];
 814         u32     gaddr0;         /* 0x.880 - Group address register 0 */
 815         u32     gaddr1;         /* 0x.884 - Group address register 1 */
 816         u32     gaddr2;         /* 0x.888 - Group address register 2 */
 817         u32     gaddr3;         /* 0x.88c - Group address register 3 */
 818         u32     gaddr4;         /* 0x.890 - Group address register 4 */
 819         u32     gaddr5;         /* 0x.894 - Group address register 5 */
 820         u32     gaddr6;         /* 0x.898 - Group address register 6 */
 821         u32     gaddr7;         /* 0x.89c - Group address register 7 */
 822         u8      res23a[352];
 823         u32     fifocfg;        /* 0x.a00 - FIFO interface config register */
 824         u8      res23b[252];
 825         u8      res23c[248];
 826         u32     attr;           /* 0x.bf8 - Attributes Register */
 827         u32     attreli;        /* 0x.bfc - Attributes Extract Length and Extract Index Register */
 828         u32     rqprm0; /* 0x.c00 - Receive queue parameters register 0 */
 829         u32     rqprm1; /* 0x.c04 - Receive queue parameters register 1 */
 830         u32     rqprm2; /* 0x.c08 - Receive queue parameters register 2 */
 831         u32     rqprm3; /* 0x.c0c - Receive queue parameters register 3 */
 832         u32     rqprm4; /* 0x.c10 - Receive queue parameters register 4 */
 833         u32     rqprm5; /* 0x.c14 - Receive queue parameters register 5 */
 834         u32     rqprm6; /* 0x.c18 - Receive queue parameters register 6 */
 835         u32     rqprm7; /* 0x.c1c - Receive queue parameters register 7 */
 836         u8      res24[36];
 837         u32     rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */
 838         u8      res24a[4];
 839         u32     rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */
 840         u8      res24b[4];
 841         u32     rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */
 842         u8      res24c[4];
 843         u32     rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */
 844         u8      res24d[4];
 845         u32     rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */
 846         u8      res24e[4];
 847         u32     rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */
 848         u8      res24f[4];
 849         u32     rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */
 850         u8      res24g[4];
 851         u32     rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */
 852         u8      res24h[4];
 853         u8      res24x[556];
 854         u32     isrg0;          /* 0x.eb0 - Interrupt steering group 0 register */
 855         u32     isrg1;          /* 0x.eb4 - Interrupt steering group 1 register */
 856         u32     isrg2;          /* 0x.eb8 - Interrupt steering group 2 register */
 857         u32     isrg3;          /* 0x.ebc - Interrupt steering group 3 register */
 858         u8      res25[16];
 859         u32     rxic0;          /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
 860         u32     rxic1;          /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
 861         u32     rxic2;          /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
 862         u32     rxic3;          /* 0x.edc - Ring 3 Rx interrupt coalescing */
 863         u32     rxic4;          /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
 864         u32     rxic5;          /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
 865         u32     rxic6;          /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
 866         u32     rxic7;          /* 0x.eec - Ring 7 Rx interrupt coalescing */
 867         u8      res26[32];
 868         u32     txic0;          /* 0x.f10 - Ring 0 Tx interrupt coalescing */
 869         u32     txic1;          /* 0x.f14 - Ring 1 Tx interrupt coalescing */
 870         u32     txic2;          /* 0x.f18 - Ring 2 Tx interrupt coalescing */
 871         u32     txic3;          /* 0x.f1c - Ring 3 Tx interrupt coalescing */
 872         u32     txic4;          /* 0x.f20 - Ring 4 Tx interrupt coalescing */
 873         u32     txic5;          /* 0x.f24 - Ring 5 Tx interrupt coalescing */
 874         u32     txic6;          /* 0x.f28 - Ring 6 Tx interrupt coalescing */
 875         u32     txic7;          /* 0x.f2c - Ring 7 Tx interrupt coalescing */
 876         u8      res27[208];
 877 };
 878 
 879 /* Flags related to gianfar device features */
 880 #define FSL_GIANFAR_DEV_HAS_GIGABIT             0x00000001
 881 #define FSL_GIANFAR_DEV_HAS_COALESCE            0x00000002
 882 #define FSL_GIANFAR_DEV_HAS_RMON                0x00000004
 883 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR          0x00000008
 884 #define FSL_GIANFAR_DEV_HAS_CSUM                0x00000010
 885 #define FSL_GIANFAR_DEV_HAS_VLAN                0x00000020
 886 #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH       0x00000040
 887 #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET        0x00000100
 888 #define FSL_GIANFAR_DEV_HAS_BD_STASHING         0x00000200
 889 #define FSL_GIANFAR_DEV_HAS_BUF_STASHING        0x00000400
 890 #define FSL_GIANFAR_DEV_HAS_TIMER               0x00000800
 891 #define FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER       0x00001000
 892 #define FSL_GIANFAR_DEV_HAS_RX_FILER            0x00002000
 893 
 894 #if (MAXGROUPS == 2)
 895 #define DEFAULT_MAPPING         0xAA
 896 #else
 897 #define DEFAULT_MAPPING         0xFF
 898 #endif
 899 
 900 #define ISRG_RR0        0x80000000
 901 #define ISRG_TR0        0x00800000
 902 
 903 /* The same driver can operate in two modes */
 904 /* SQ_SG_MODE: Single Queue Single Group Mode
 905  *              (Backward compatible mode)
 906  * MQ_MG_MODE: Multi Queue Multi Group mode
 907  */
 908 enum {
 909         SQ_SG_MODE = 0,
 910         MQ_MG_MODE
 911 };
 912 
 913 /* GFAR_SQ_POLLING: Single Queue NAPI polling mode
 914  *      The driver supports a single pair of RX/Tx queues
 915  *      per interrupt group (Rx/Tx int line). MQ_MG mode
 916  *      devices have 2 interrupt groups, so the device will
 917  *      have a total of 2 Tx and 2 Rx queues in this case.
 918  * GFAR_MQ_POLLING: Multi Queue NAPI polling mode
 919  *      The driver supports all the 8 Rx and Tx HW queues
 920  *      each queue mapped by the Device Tree to one of
 921  *      the 2 interrupt groups. This mode implies significant
 922  *      processing overhead (CPU and controller level).
 923  */
 924 enum gfar_poll_mode {
 925         GFAR_SQ_POLLING = 0,
 926         GFAR_MQ_POLLING
 927 };
 928 
 929 /*
 930  * Per TX queue stats
 931  */
 932 struct tx_q_stats {
 933         unsigned long tx_packets;
 934         unsigned long tx_bytes;
 935 };
 936 
 937 /**
 938  *      struct gfar_priv_tx_q - per tx queue structure
 939  *      @txlock: per queue tx spin lock
 940  *      @tx_skbuff:skb pointers
 941  *      @skb_curtx: to be used skb pointer
 942  *      @skb_dirtytx:the last used skb pointer
 943  *      @stats: bytes/packets stats
 944  *      @qindex: index of this queue
 945  *      @dev: back pointer to the dev structure
 946  *      @grp: back pointer to the group to which this queue belongs
 947  *      @tx_bd_base: First tx buffer descriptor
 948  *      @cur_tx: Next free ring entry
 949  *      @dirty_tx: First buffer in line to be transmitted
 950  *      @tx_ring_size: Tx ring size
 951  *      @num_txbdfree: number of free TxBds
 952  *      @txcoalescing: enable/disable tx coalescing
 953  *      @txic: transmit interrupt coalescing value
 954  *      @txcount: coalescing value if based on tx frame count
 955  *      @txtime: coalescing value if based on time
 956  */
 957 struct gfar_priv_tx_q {
 958         /* cacheline 1 */
 959         spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
 960         struct  txbd8 *tx_bd_base;
 961         struct  txbd8 *cur_tx;
 962         unsigned int num_txbdfree;
 963         unsigned short skb_curtx;
 964         unsigned short tx_ring_size;
 965         struct tx_q_stats stats;
 966         struct gfar_priv_grp *grp;
 967         /* cacheline 2 */
 968         struct net_device *dev;
 969         struct sk_buff **tx_skbuff;
 970         struct  txbd8 *dirty_tx;
 971         unsigned short skb_dirtytx;
 972         unsigned short qindex;
 973         /* Configuration info for the coalescing features */
 974         unsigned int txcoalescing;
 975         unsigned long txic;
 976         dma_addr_t tx_bd_dma_base;
 977 };
 978 
 979 /*
 980  * Per RX queue stats
 981  */
 982 struct rx_q_stats {
 983         unsigned long rx_packets;
 984         unsigned long rx_bytes;
 985         unsigned long rx_dropped;
 986 };
 987 
 988 struct gfar_rx_buff {
 989         dma_addr_t dma;
 990         struct page *page;
 991         unsigned int page_offset;
 992 };
 993 
 994 /**
 995  *      struct gfar_priv_rx_q - per rx queue structure
 996  *      @rx_buff: Array of buffer info metadata structs
 997  *      @rx_bd_base: First rx buffer descriptor
 998  *      @next_to_use: index of the next buffer to be alloc'd
 999  *      @next_to_clean: index of the next buffer to be cleaned
1000  *      @qindex: index of this queue
1001  *      @ndev: back pointer to net_device
1002  *      @rx_ring_size: Rx ring size
1003  *      @rxcoalescing: enable/disable rx-coalescing
1004  *      @rxic: receive interrupt coalescing vlaue
1005  */
1006 
1007 struct gfar_priv_rx_q {
1008         struct  gfar_rx_buff *rx_buff __aligned(SMP_CACHE_BYTES);
1009         struct  rxbd8 *rx_bd_base;
1010         struct  net_device *ndev;
1011         struct  device *dev;
1012         u16 rx_ring_size;
1013         u16 qindex;
1014         struct  gfar_priv_grp *grp;
1015         u16 next_to_clean;
1016         u16 next_to_use;
1017         u16 next_to_alloc;
1018         struct  sk_buff *skb;
1019         struct rx_q_stats stats;
1020         u32 __iomem *rfbptr;
1021         unsigned char rxcoalescing;
1022         unsigned long rxic;
1023         dma_addr_t rx_bd_dma_base;
1024 };
1025 
1026 enum gfar_irqinfo_id {
1027         GFAR_TX = 0,
1028         GFAR_RX = 1,
1029         GFAR_ER = 2,
1030         GFAR_NUM_IRQS = 3
1031 };
1032 
1033 struct gfar_irqinfo {
1034         unsigned int irq;
1035         char name[GFAR_INT_NAME_MAX];
1036 };
1037 
1038 /**
1039  *      struct gfar_priv_grp - per group structure
1040  *      @napi: the napi poll function
1041  *      @priv: back pointer to the priv structure
1042  *      @regs: the ioremapped register space for this group
1043  *      @irqinfo: TX/RX/ER irq data for this group
1044  */
1045 
1046 struct gfar_priv_grp {
1047         spinlock_t grplock __aligned(SMP_CACHE_BYTES);
1048         struct  napi_struct napi_rx;
1049         struct  napi_struct napi_tx;
1050         struct gfar __iomem *regs;
1051         struct gfar_priv_tx_q *tx_queue;
1052         struct gfar_priv_rx_q *rx_queue;
1053         unsigned int tstat;
1054         unsigned int rstat;
1055 
1056         struct gfar_private *priv;
1057         unsigned long num_tx_queues;
1058         unsigned long tx_bit_map;
1059         unsigned long num_rx_queues;
1060         unsigned long rx_bit_map;
1061 
1062         struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
1063 };
1064 
1065 #define gfar_irq(grp, ID) \
1066         ((grp)->irqinfo[GFAR_##ID])
1067 
1068 enum gfar_errata {
1069         GFAR_ERRATA_74          = 0x01,
1070         GFAR_ERRATA_76          = 0x02,
1071         GFAR_ERRATA_A002        = 0x04,
1072         GFAR_ERRATA_12          = 0x08, /* a.k.a errata eTSEC49 */
1073 };
1074 
1075 enum gfar_dev_state {
1076         GFAR_DOWN = 1,
1077         GFAR_RESETTING
1078 };
1079 
1080 /* Struct stolen almost completely (and shamelessly) from the FCC enet source
1081  * (Ok, that's not so true anymore, but there is a family resemblance)
1082  * The GFAR buffer descriptors track the ring buffers.  The rx_bd_base
1083  * and tx_bd_base always point to the currently available buffer.
1084  * The dirty_tx tracks the current buffer that is being sent by the
1085  * controller.  The cur_tx and dirty_tx are equal under both completely
1086  * empty and completely full conditions.  The empty/ready indicator in
1087  * the buffer descriptor determines the actual condition.
1088  */
1089 struct gfar_private {
1090         struct device *dev;
1091         struct net_device *ndev;
1092         enum gfar_errata errata;
1093 
1094         u16 uses_rxfcb;
1095         u16 padding;
1096         u32 device_flags;
1097 
1098         /* HW time stamping enabled flag */
1099         int hwts_rx_en;
1100         int hwts_tx_en;
1101 
1102         struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1103         struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
1104         struct gfar_priv_grp gfargrp[MAXGROUPS];
1105 
1106         unsigned long state;
1107 
1108         unsigned short mode;
1109         unsigned short poll_mode;
1110         unsigned int num_tx_queues;
1111         unsigned int num_rx_queues;
1112         unsigned int num_grps;
1113         int tx_actual_en;
1114 
1115         /* Network Statistics */
1116         struct gfar_extra_stats extra_stats;
1117 
1118         /* PHY stuff */
1119         phy_interface_t interface;
1120         struct device_node *phy_node;
1121         struct device_node *tbi_node;
1122         struct mii_bus *mii_bus;
1123         int oldspeed;
1124         int oldduplex;
1125         int oldlink;
1126 
1127         uint32_t msg_enable;
1128 
1129         struct work_struct reset_task;
1130 
1131         struct platform_device *ofdev;
1132         unsigned char
1133                 extended_hash:1,
1134                 bd_stash_en:1,
1135                 rx_filer_enable:1,
1136                 /* Enable priorty based Tx scheduling in Hw */
1137                 prio_sched_en:1,
1138                 /* Flow control flags */
1139                 pause_aneg_en:1,
1140                 tx_pause_en:1,
1141                 rx_pause_en:1;
1142 
1143         /* The total tx and rx ring size for the enabled queues */
1144         unsigned int total_tx_ring_size;
1145         unsigned int total_rx_ring_size;
1146 
1147         u32 rqueue;
1148         u32 tqueue;
1149 
1150         /* RX per device parameters */
1151         unsigned int rx_stash_size;
1152         unsigned int rx_stash_index;
1153 
1154         u32 cur_filer_idx;
1155 
1156         /* RX queue filer rule set*/
1157         struct ethtool_rx_list rx_list;
1158         struct mutex rx_queue_access;
1159 
1160         /* Hash registers and their width */
1161         u32 __iomem *hash_regs[16];
1162         int hash_width;
1163 
1164         /* wake-on-lan settings */
1165         u16 wol_opts;
1166         u16 wol_supported;
1167 
1168         /*Filer table*/
1169         unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1170         unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
1171 };
1172 
1173 
1174 static inline int gfar_has_errata(struct gfar_private *priv,
1175                                   enum gfar_errata err)
1176 {
1177         return priv->errata & err;
1178 }
1179 
1180 static inline u32 gfar_read(unsigned __iomem *addr)
1181 {
1182         u32 val;
1183         val = ioread32be(addr);
1184         return val;
1185 }
1186 
1187 static inline void gfar_write(unsigned __iomem *addr, u32 val)
1188 {
1189         iowrite32be(val, addr);
1190 }
1191 
1192 static inline void gfar_write_filer(struct gfar_private *priv,
1193                 unsigned int far, unsigned int fcr, unsigned int fpr)
1194 {
1195         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1196 
1197         gfar_write(&regs->rqfar, far);
1198         gfar_write(&regs->rqfcr, fcr);
1199         gfar_write(&regs->rqfpr, fpr);
1200 }
1201 
1202 static inline void gfar_read_filer(struct gfar_private *priv,
1203                 unsigned int far, unsigned int *fcr, unsigned int *fpr)
1204 {
1205         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1206 
1207         gfar_write(&regs->rqfar, far);
1208         *fcr = gfar_read(&regs->rqfcr);
1209         *fpr = gfar_read(&regs->rqfpr);
1210 }
1211 
1212 static inline void gfar_write_isrg(struct gfar_private *priv)
1213 {
1214         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1215         u32 __iomem *baddr = &regs->isrg0;
1216         u32 isrg = 0;
1217         int grp_idx, i;
1218 
1219         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1220                 struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx];
1221 
1222                 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
1223                         isrg |= (ISRG_RR0 >> i);
1224                 }
1225 
1226                 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
1227                         isrg |= (ISRG_TR0 >> i);
1228                 }
1229 
1230                 gfar_write(baddr, isrg);
1231 
1232                 baddr++;
1233                 isrg = 0;
1234         }
1235 }
1236 
1237 static inline int gfar_is_dma_stopped(struct gfar_private *priv)
1238 {
1239         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1240 
1241         return ((gfar_read(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) ==
1242                (IEVENT_GRSC | IEVENT_GTSC));
1243 }
1244 
1245 static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv)
1246 {
1247         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1248 
1249         return gfar_read(&regs->ievent) & IEVENT_GRSC;
1250 }
1251 
1252 static inline void gfar_wmb(void)
1253 {
1254 #if defined(CONFIG_PPC)
1255         /* The powerpc-specific eieio() is used, as wmb() has too strong
1256          * semantics (it requires synchronization between cacheable and
1257          * uncacheable mappings, which eieio() doesn't provide and which we
1258          * don't need), thus requiring a more expensive sync instruction.  At
1259          * some point, the set of architecture-independent barrier functions
1260          * should be expanded to include weaker barriers.
1261          */
1262         eieio();
1263 #else
1264         wmb(); /* order write acesses for BD (or FCB) fields */
1265 #endif
1266 }
1267 
1268 static inline void gfar_clear_txbd_status(struct txbd8 *bdp)
1269 {
1270         u32 lstatus = be32_to_cpu(bdp->lstatus);
1271 
1272         lstatus &= BD_LFLAG(TXBD_WRAP);
1273         bdp->lstatus = cpu_to_be32(lstatus);
1274 }
1275 
1276 static inline int gfar_rxbd_unused(struct gfar_priv_rx_q *rxq)
1277 {
1278         if (rxq->next_to_clean > rxq->next_to_use)
1279                 return rxq->next_to_clean - rxq->next_to_use - 1;
1280 
1281         return rxq->rx_ring_size + rxq->next_to_clean - rxq->next_to_use - 1;
1282 }
1283 
1284 static inline u32 gfar_rxbd_dma_lastfree(struct gfar_priv_rx_q *rxq)
1285 {
1286         struct rxbd8 *bdp;
1287         u32 bdp_dma;
1288         int i;
1289 
1290         i = rxq->next_to_use ? rxq->next_to_use - 1 : rxq->rx_ring_size - 1;
1291         bdp = &rxq->rx_bd_base[i];
1292         bdp_dma = lower_32_bits(rxq->rx_bd_dma_base);
1293         bdp_dma += (uintptr_t)bdp - (uintptr_t)rxq->rx_bd_base;
1294 
1295         return bdp_dma;
1296 }
1297 
1298 int startup_gfar(struct net_device *dev);
1299 void stop_gfar(struct net_device *dev);
1300 void gfar_mac_reset(struct gfar_private *priv);
1301 int gfar_set_features(struct net_device *dev, netdev_features_t features);
1302 
1303 extern const struct ethtool_ops gfar_ethtool_ops;
1304 
1305 #define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX))
1306 
1307 #define RQFCR_PID_PRI_MASK 0xFFFFFFF8
1308 #define RQFCR_PID_L4P_MASK 0xFFFFFF00
1309 #define RQFCR_PID_VID_MASK 0xFFFFF000
1310 #define RQFCR_PID_PORT_MASK 0xFFFF0000
1311 #define RQFCR_PID_MAC_MASK 0xFF000000
1312 
1313 /* Represents a receive filer table entry */
1314 struct gfar_filer_entry {
1315         u32 ctrl;
1316         u32 prop;
1317 };
1318 
1319 
1320 /* The 20 additional entries are a shadow for one extra element */
1321 struct filer_table {
1322         u32 index;
1323         struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
1324 };
1325 
1326 #endif /* __GIANFAR_H */