root/drivers/net/ethernet/freescale/enetc/enetc_hw.h

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INCLUDED FROM


DEFINITIONS

This source file includes following definitions.
  1. enetc_vsi_set_msize
  2. enetc_rd_reg64
  3. enetc_clear_tx_bd
  4. enetc_txbd_l3_csoff
  5. enetc_get_primary_mac_addr
  6. enetc_enable_rxvlan
  7. enetc_enable_txvlan
  8. enetc_set_bdr_prio

   1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
   2 /* Copyright 2017-2019 NXP */
   3 
   4 #include <linux/bitops.h>
   5 
   6 /* ENETC device IDs */
   7 #define ENETC_DEV_ID_PF         0xe100
   8 #define ENETC_DEV_ID_VF         0xef00
   9 #define ENETC_DEV_ID_PTP        0xee02
  10 
  11 /* ENETC register block BAR */
  12 #define ENETC_BAR_REGS  0
  13 
  14 /** SI regs, offset: 0h */
  15 #define ENETC_SIMR      0
  16 #define ENETC_SIMR_EN   BIT(31)
  17 #define ENETC_SIMR_RSSE BIT(0)
  18 #define ENETC_SICTR0    0x18
  19 #define ENETC_SICTR1    0x1c
  20 #define ENETC_SIPCAPR0  0x20
  21 #define ENETC_SIPCAPR0_RSS      BIT(8)
  22 #define ENETC_SIPCAPR1  0x24
  23 #define ENETC_SITGTGR   0x30
  24 #define ENETC_SIRBGCR   0x38
  25 /* cache attribute registers for transactions initiated by ENETC */
  26 #define ENETC_SICAR0    0x40
  27 #define ENETC_SICAR1    0x44
  28 #define ENETC_SICAR2    0x48
  29 /* rd snoop, no alloc
  30  * wr snoop, no alloc, partial cache line update for BDs and full cache line
  31  * update for data
  32  */
  33 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000
  34 #define ENETC_SICAR_WR_COHERENT 0x00006727
  35 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */
  36 
  37 #define ENETC_SIPMAR0   0x80
  38 #define ENETC_SIPMAR1   0x84
  39 
  40 /* VF-PF Message passing */
  41 #define ENETC_DEFAULT_MSG_SIZE  1024    /* and max size */
  42 /* msg size encoding: default and max msg value of 1024B encoded as 0 */
  43 static inline u32 enetc_vsi_set_msize(u32 size)
  44 {
  45         return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0;
  46 }
  47 
  48 #define ENETC_PSIMSGRR  0x204
  49 #define ENETC_PSIMSGRR_MR_MASK  GENMASK(2, 1)
  50 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */
  51 #define ENETC_PSIVMSGRCVAR0(n)  (0x210 + (n) * 0x8) /* n = VSI index */
  52 #define ENETC_PSIVMSGRCVAR1(n)  (0x214 + (n) * 0x8)
  53 
  54 #define ENETC_VSIMSGSR  0x204   /* RO */
  55 #define ENETC_VSIMSGSR_MB       BIT(0)
  56 #define ENETC_VSIMSGSR_MS       BIT(1)
  57 #define ENETC_VSIMSGSNDAR0      0x210
  58 #define ENETC_VSIMSGSNDAR1      0x214
  59 
  60 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16)
  61 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16)
  62 
  63 /* SI statistics */
  64 #define ENETC_SIROCT    0x300
  65 #define ENETC_SIRFRM    0x308
  66 #define ENETC_SIRUCA    0x310
  67 #define ENETC_SIRMCA    0x318
  68 #define ENETC_SITOCT    0x320
  69 #define ENETC_SITFRM    0x328
  70 #define ENETC_SITUCA    0x330
  71 #define ENETC_SITMCA    0x338
  72 #define ENETC_RBDCR(n)  (0x8180 + (n) * 0x200)
  73 
  74 /* Control BDR regs */
  75 #define ENETC_SICBDRMR          0x800
  76 #define ENETC_SICBDRSR          0x804   /* RO */
  77 #define ENETC_SICBDRBAR0        0x810
  78 #define ENETC_SICBDRBAR1        0x814
  79 #define ENETC_SICBDRPIR         0x818
  80 #define ENETC_SICBDRCIR         0x81c
  81 #define ENETC_SICBDRLENR        0x820
  82 
  83 #define ENETC_SICAPR0   0x900
  84 #define ENETC_SICAPR1   0x904
  85 
  86 #define ENETC_PSIIER    0xa00
  87 #define ENETC_PSIIER_MR_MASK    GENMASK(2, 1)
  88 #define ENETC_PSIIDR    0xa08
  89 #define ENETC_SITXIDR   0xa18
  90 #define ENETC_SIRXIDR   0xa28
  91 #define ENETC_SIMSIVR   0xa30
  92 
  93 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
  94 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
  95 
  96 #define ENETC_SIUEFDCR  0xe28
  97 
  98 #define ENETC_SIRFSCAPR 0x1200
  99 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f)
 100 #define ENETC_SIRSSCAPR 0x1600
 101 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
 102 
 103 /** SI BDR sub-blocks, n = 0..7 */
 104 enum enetc_bdr_type {TX, RX};
 105 #define ENETC_BDR_OFF(i)        ((i) * 0x200)
 106 #define ENETC_BDR(t, i, r)      (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r))
 107 /* RX BDR reg offsets */
 108 #define ENETC_RBMR      0
 109 #define ENETC_RBMR_BDS  BIT(2)
 110 #define ENETC_RBMR_VTE  BIT(5)
 111 #define ENETC_RBMR_EN   BIT(31)
 112 #define ENETC_RBSR      0x4
 113 #define ENETC_RBBSR     0x8
 114 #define ENETC_RBCIR     0xc
 115 #define ENETC_RBBAR0    0x10
 116 #define ENETC_RBBAR1    0x14
 117 #define ENETC_RBPIR     0x18
 118 #define ENETC_RBLENR    0x20
 119 #define ENETC_RBIER     0xa0
 120 #define ENETC_RBIER_RXTIE       BIT(0)
 121 #define ENETC_RBIDR     0xa4
 122 #define ENETC_RBICIR0   0xa8
 123 #define ENETC_RBICIR0_ICEN      BIT(31)
 124 
 125 /* TX BDR reg offsets */
 126 #define ENETC_TBMR      0
 127 #define ENETC_TBSR_BUSY BIT(0)
 128 #define ENETC_TBMR_VIH  BIT(9)
 129 #define ENETC_TBMR_PRIO_MASK            GENMASK(2, 0)
 130 #define ENETC_TBMR_SET_PRIO(val)        ((val) & ENETC_TBMR_PRIO_MASK)
 131 #define ENETC_TBMR_EN   BIT(31)
 132 #define ENETC_TBSR      0x4
 133 #define ENETC_TBBAR0    0x10
 134 #define ENETC_TBBAR1    0x14
 135 #define ENETC_TBPIR     0x18
 136 #define ENETC_TBCIR     0x1c
 137 #define ENETC_TBCIR_IDX_MASK    0xffff
 138 #define ENETC_TBLENR    0x20
 139 #define ENETC_TBIER     0xa0
 140 #define ENETC_TBIER_TXTIE       BIT(0)
 141 #define ENETC_TBIDR     0xa4
 142 #define ENETC_TBICIR0   0xa8
 143 #define ENETC_TBICIR0_ICEN      BIT(31)
 144 
 145 #define ENETC_RTBLENR_LEN(n)    ((n) & ~0x7)
 146 
 147 /* Port regs, offset: 1_0000h */
 148 #define ENETC_PORT_BASE         0x10000
 149 #define ENETC_PMR               0x0000
 150 #define ENETC_PMR_EN    GENMASK(18, 16)
 151 #define ENETC_PSR               0x0004 /* RO */
 152 #define ENETC_PSIPMR            0x0018
 153 #define ENETC_PSIPMR_SET_UP(n)  BIT(n) /* n = SI index */
 154 #define ENETC_PSIPMR_SET_MP(n)  BIT((n) + 16)
 155 #define ENETC_PSIPVMR           0x001c
 156 #define ENETC_VLAN_PROMISC_MAP_ALL      0x7
 157 #define ENETC_PSIPVMR_SET_VP(simap)     ((simap) & 0x7)
 158 #define ENETC_PSIPVMR_SET_VUTA(simap)   (((simap) & 0x7) << 16)
 159 #define ENETC_PSIPMAR0(n)       (0x0100 + (n) * 0x8) /* n = SI index */
 160 #define ENETC_PSIPMAR1(n)       (0x0104 + (n) * 0x8)
 161 #define ENETC_PVCLCTR           0x0208
 162 #define ENETC_VLAN_TYPE_C       BIT(0)
 163 #define ENETC_VLAN_TYPE_S       BIT(1)
 164 #define ENETC_PVCLCTR_OVTPIDL(bmp)      ((bmp) & 0xff) /* VLAN_TYPE */
 165 #define ENETC_PSIVLANR(n)       (0x0240 + (n) * 4) /* n = SI index */
 166 #define ENETC_PSIVLAN_EN        BIT(31)
 167 #define ENETC_PSIVLAN_SET_QOS(val)      ((u32)(val) << 12)
 168 #define ENETC_PTXMBAR           0x0608
 169 #define ENETC_PCAPR0            0x0900
 170 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24)
 171 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff)
 172 #define ENETC_PCAPR1            0x0904
 173 #define ENETC_PSICFGR0(n)       (0x0940 + (n) * 0xc)  /* n = SI index */
 174 #define ENETC_PSICFGR0_SET_TXBDR(val)   ((val) & 0xff)
 175 #define ENETC_PSICFGR0_SET_RXBDR(val)   (((val) & 0xff) << 16)
 176 #define ENETC_PSICFGR0_VTE      BIT(12)
 177 #define ENETC_PSICFGR0_SIVIE    BIT(14)
 178 #define ENETC_PSICFGR0_ASE      BIT(15)
 179 #define ENETC_PSICFGR0_SIVC(bmp)        (((bmp) & 0xff) << 24) /* VLAN_TYPE */
 180 
 181 #define ENETC_PTCCBSR0(n)       (0x1110 + (n) * 8) /* n = 0 to 7*/
 182 #define ENETC_PTCCBSR1(n)       (0x1114 + (n) * 8) /* n = 0 to 7*/
 183 #define ENETC_RSSHASH_KEY_SIZE  40
 184 #define ENETC_PRSSK(n)          (0x1410 + (n) * 4) /* n = [0..9] */
 185 #define ENETC_PSIVLANFMR        0x1700
 186 #define ENETC_PSIVLANFMR_VS     BIT(0)
 187 #define ENETC_PRFSMR            0x1800
 188 #define ENETC_PRFSMR_RFSE       BIT(31)
 189 #define ENETC_PRFSCAPR          0x1804
 190 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16)
 191 #define ENETC_PSIRFSCFGR(n)     (0x1814 + (n) * 4) /* n = SI index */
 192 #define ENETC_PFPMR             0x1900
 193 #define ENETC_PFPMR_PMACE       BIT(1)
 194 #define ENETC_PFPMR_MWLM        BIT(0)
 195 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
 196 #define ENETC_PSIUMHFR1(n)      (0x1d04 + (n) * 0x10)
 197 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10)
 198 #define ENETC_PSIMMHFR1(n)      (0x1d0c + (n) * 0x10)
 199 #define ENETC_PSIVHFR0(n)       (0x1e00 + (n) * 8) /* n = SI index */
 200 #define ENETC_PSIVHFR1(n)       (0x1e04 + (n) * 8) /* n = SI index */
 201 #define ENETC_MMCSR             0x1f00
 202 #define ENETC_MMCSR_ME          BIT(16)
 203 #define ENETC_PTCMSDUR(n)       (0x2020 + (n) * 4) /* n = TC index [0..7] */
 204 
 205 #define ENETC_PM0_CMD_CFG       0x8008
 206 #define ENETC_PM1_CMD_CFG       0x9008
 207 #define ENETC_PM0_TX_EN         BIT(0)
 208 #define ENETC_PM0_RX_EN         BIT(1)
 209 #define ENETC_PM0_PROMISC       BIT(4)
 210 #define ENETC_PM0_CMD_XGLP      BIT(10)
 211 #define ENETC_PM0_CMD_TXP       BIT(11)
 212 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15)
 213 #define ENETC_PM0_CMD_SFD       BIT(21)
 214 #define ENETC_PM0_MAXFRM        0x8014
 215 #define ENETC_SET_TX_MTU(val)   ((val) << 16)
 216 #define ENETC_SET_MAXFRM(val)   ((val) & 0xffff)
 217 #define ENETC_PM0_IF_MODE       0x8300
 218 #define ENETC_PMO_IFM_RG        BIT(2)
 219 #define ENETC_PM0_IFM_RLP       (BIT(5) | BIT(11))
 220 #define ENETC_PM0_IFM_RGAUTO    (BIT(15) | ENETC_PMO_IFM_RG | BIT(1))
 221 #define ENETC_PM0_IFM_XGMII     BIT(12)
 222 
 223 /* MAC counters */
 224 #define ENETC_PM0_REOCT         0x8100
 225 #define ENETC_PM0_RALN          0x8110
 226 #define ENETC_PM0_RXPF          0x8118
 227 #define ENETC_PM0_RFRM          0x8120
 228 #define ENETC_PM0_RFCS          0x8128
 229 #define ENETC_PM0_RVLAN         0x8130
 230 #define ENETC_PM0_RERR          0x8138
 231 #define ENETC_PM0_RUCA          0x8140
 232 #define ENETC_PM0_RMCA          0x8148
 233 #define ENETC_PM0_RBCA          0x8150
 234 #define ENETC_PM0_RDRP          0x8158
 235 #define ENETC_PM0_RPKT          0x8160
 236 #define ENETC_PM0_RUND          0x8168
 237 #define ENETC_PM0_R64           0x8170
 238 #define ENETC_PM0_R127          0x8178
 239 #define ENETC_PM0_R255          0x8180
 240 #define ENETC_PM0_R511          0x8188
 241 #define ENETC_PM0_R1023         0x8190
 242 #define ENETC_PM0_R1518         0x8198
 243 #define ENETC_PM0_R1519X        0x81A0
 244 #define ENETC_PM0_ROVR          0x81A8
 245 #define ENETC_PM0_RJBR          0x81B0
 246 #define ENETC_PM0_RFRG          0x81B8
 247 #define ENETC_PM0_RCNP          0x81C0
 248 #define ENETC_PM0_RDRNTP        0x81C8
 249 #define ENETC_PM0_TEOCT         0x8200
 250 #define ENETC_PM0_TOCT          0x8208
 251 #define ENETC_PM0_TCRSE         0x8210
 252 #define ENETC_PM0_TXPF          0x8218
 253 #define ENETC_PM0_TFRM          0x8220
 254 #define ENETC_PM0_TFCS          0x8228
 255 #define ENETC_PM0_TVLAN         0x8230
 256 #define ENETC_PM0_TERR          0x8238
 257 #define ENETC_PM0_TUCA          0x8240
 258 #define ENETC_PM0_TMCA          0x8248
 259 #define ENETC_PM0_TBCA          0x8250
 260 #define ENETC_PM0_TPKT          0x8260
 261 #define ENETC_PM0_TUND          0x8268
 262 #define ENETC_PM0_T127          0x8278
 263 #define ENETC_PM0_T1023         0x8290
 264 #define ENETC_PM0_T1518         0x8298
 265 #define ENETC_PM0_TCNP          0x82C0
 266 #define ENETC_PM0_TDFR          0x82D0
 267 #define ENETC_PM0_TMCOL         0x82D8
 268 #define ENETC_PM0_TSCOL         0x82E0
 269 #define ENETC_PM0_TLCOL         0x82E8
 270 #define ENETC_PM0_TECOL         0x82F0
 271 
 272 /* Port counters */
 273 #define ENETC_PICDR(n)          (0x0700 + (n) * 8) /* n = [0..3] */
 274 #define ENETC_PBFDSIR           0x0810
 275 #define ENETC_PFDMSAPR          0x0814
 276 #define ENETC_UFDMF             0x1680
 277 #define ENETC_MFDMF             0x1684
 278 #define ENETC_PUFDVFR           0x1780
 279 #define ENETC_PMFDVFR           0x1784
 280 #define ENETC_PBFDVFR           0x1788
 281 
 282 /** Global regs, offset: 2_0000h */
 283 #define ENETC_GLOBAL_BASE       0x20000
 284 #define ENETC_G_EIPBRR0         0x0bf8
 285 #define ENETC_G_EIPBRR1         0x0bfc
 286 #define ENETC_G_EPFBLPR(n)      (0xd00 + 4 * (n))
 287 #define ENETC_G_EPFBLPR1_XGMII  0x80000000
 288 
 289 /* PCI device info */
 290 struct enetc_hw {
 291         /* SI registers, used by all PCI functions */
 292         void __iomem *reg;
 293         /* Port registers, PF only */
 294         void __iomem *port;
 295         /* IP global registers, PF only */
 296         void __iomem *global;
 297 };
 298 
 299 /* general register accessors */
 300 #define enetc_rd_reg(reg)       ioread32((reg))
 301 #define enetc_wr_reg(reg, val)  iowrite32((val), (reg))
 302 #ifdef ioread64
 303 #define enetc_rd_reg64(reg)     ioread64((reg))
 304 #else
 305 /* using this to read out stats on 32b systems */
 306 static inline u64 enetc_rd_reg64(void __iomem *reg)
 307 {
 308         u32 low, high, tmp;
 309 
 310         do {
 311                 high = ioread32(reg + 4);
 312                 low = ioread32(reg);
 313                 tmp = ioread32(reg + 4);
 314         } while (high != tmp);
 315 
 316         return le64_to_cpu((__le64)high << 32 | low);
 317 }
 318 #endif
 319 
 320 #define enetc_rd(hw, off)               enetc_rd_reg((hw)->reg + (off))
 321 #define enetc_wr(hw, off, val)          enetc_wr_reg((hw)->reg + (off), val)
 322 #define enetc_rd64(hw, off)             enetc_rd_reg64((hw)->reg + (off))
 323 /* port register accessors - PF only */
 324 #define enetc_port_rd(hw, off)          enetc_rd_reg((hw)->port + (off))
 325 #define enetc_port_wr(hw, off, val)     enetc_wr_reg((hw)->port + (off), val)
 326 /* global register accessors - PF only */
 327 #define enetc_global_rd(hw, off)        enetc_rd_reg((hw)->global + (off))
 328 #define enetc_global_wr(hw, off, val)   enetc_wr_reg((hw)->global + (off), val)
 329 /* BDR register accessors, see ENETC_BDR() */
 330 #define enetc_bdr_rd(hw, t, n, off) \
 331                                 enetc_rd(hw, ENETC_BDR(t, n, off))
 332 #define enetc_bdr_wr(hw, t, n, off, val) \
 333                                 enetc_wr(hw, ENETC_BDR(t, n, off), val)
 334 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off)
 335 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off)
 336 #define enetc_txbdr_wr(hw, n, off, val) \
 337                                 enetc_bdr_wr(hw, TX, n, off, val)
 338 #define enetc_rxbdr_wr(hw, n, off, val) \
 339                                 enetc_bdr_wr(hw, RX, n, off, val)
 340 
 341 /* Buffer Descriptors (BD) */
 342 union enetc_tx_bd {
 343         struct {
 344                 __le64 addr;
 345                 __le16 buf_len;
 346                 __le16 frm_len;
 347                 union {
 348                         struct {
 349                                 __le16 l3_csoff;
 350                                 u8 l4_csoff;
 351                                 u8 flags;
 352                         }; /* default layout */
 353                         __le32 lstatus;
 354                 };
 355         };
 356         struct {
 357                 __le32 tstamp;
 358                 __le16 tpid;
 359                 __le16 vid;
 360                 u8 reserved[6];
 361                 u8 e_flags;
 362                 u8 flags;
 363         } ext; /* Tx BD extension */
 364         struct {
 365                 __le32 tstamp;
 366                 u8 reserved[10];
 367                 u8 status;
 368                 u8 flags;
 369         } wb; /* writeback descriptor */
 370 };
 371 
 372 #define ENETC_TXBD_FLAGS_L4CS   BIT(0)
 373 #define ENETC_TXBD_FLAGS_W      BIT(2)
 374 #define ENETC_TXBD_FLAGS_CSUM   BIT(3)
 375 #define ENETC_TXBD_FLAGS_EX     BIT(6)
 376 #define ENETC_TXBD_FLAGS_F      BIT(7)
 377 
 378 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd)
 379 {
 380         memset(txbd, 0, sizeof(*txbd));
 381 }
 382 
 383 /* L3 csum flags */
 384 #define ENETC_TXBD_L3_IPCS      BIT(7)
 385 #define ENETC_TXBD_L3_IPV6      BIT(15)
 386 
 387 #define ENETC_TXBD_L3_START_MASK        GENMASK(6, 0)
 388 #define ENETC_TXBD_L3_SET_HSIZE(val)    ((((val) >> 2) & 0x7f) << 8)
 389 
 390 /* Extension flags */
 391 #define ENETC_TXBD_E_FLAGS_VLAN_INS     BIT(0)
 392 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2)
 393 
 394 static inline __le16 enetc_txbd_l3_csoff(int start, int hdr_sz, u16 l3_flags)
 395 {
 396         return cpu_to_le16(l3_flags | ENETC_TXBD_L3_SET_HSIZE(hdr_sz) |
 397                            (start & ENETC_TXBD_L3_START_MASK));
 398 }
 399 
 400 /* L4 csum flags */
 401 #define ENETC_TXBD_L4_UDP       BIT(5)
 402 #define ENETC_TXBD_L4_TCP       BIT(6)
 403 
 404 union enetc_rx_bd {
 405         struct {
 406                 __le64 addr;
 407                 u8 reserved[8];
 408 #ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING
 409                 u8 reserved1[16];
 410 #endif
 411         } w;
 412         struct {
 413                 __le16 inet_csum;
 414                 __le16 parse_summary;
 415                 __le32 rss_hash;
 416                 __le16 buf_len;
 417                 __le16 vlan_opt;
 418                 union {
 419                         struct {
 420                                 __le16 flags;
 421                                 __le16 error;
 422                         };
 423                         __le32 lstatus;
 424                 };
 425 #ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING
 426                 __le32 tstamp;
 427                 u8 reserved[12];
 428 #endif
 429         } r;
 430 };
 431 
 432 #define ENETC_RXBD_LSTATUS_R    BIT(30)
 433 #define ENETC_RXBD_LSTATUS_F    BIT(31)
 434 #define ENETC_RXBD_ERR_MASK     0xff
 435 #define ENETC_RXBD_LSTATUS(flags)       ((flags) << 16)
 436 #define ENETC_RXBD_FLAG_VLAN    BIT(9)
 437 #define ENETC_RXBD_FLAG_TSTMP   BIT(10)
 438 
 439 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */
 440 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */
 441 #define ENETC_MAX_NUM_VFS       2
 442 
 443 struct enetc_cbd {
 444         union {
 445                 struct {
 446                         __le32 addr[2];
 447                         __le32 opt[4];
 448                 };
 449                 __le32 data[6];
 450         };
 451         __le16 index;
 452         __le16 length;
 453         u8 cmd;
 454         u8 cls;
 455         u8 _res;
 456         u8 status_flags;
 457 };
 458 
 459 #define ENETC_CBD_FLAGS_SF      BIT(7) /* short format */
 460 #define ENETC_CBD_STATUS_MASK   0xf
 461 
 462 struct enetc_cmd_rfse {
 463         u8 smac_h[6];
 464         u8 smac_m[6];
 465         u8 dmac_h[6];
 466         u8 dmac_m[6];
 467         u32 sip_h[4];
 468         u32 sip_m[4];
 469         u32 dip_h[4];
 470         u32 dip_m[4];
 471         u16 ethtype_h;
 472         u16 ethtype_m;
 473         u16 ethtype4_h;
 474         u16 ethtype4_m;
 475         u16 sport_h;
 476         u16 sport_m;
 477         u16 dport_h;
 478         u16 dport_m;
 479         u16 vlan_h;
 480         u16 vlan_m;
 481         u8 proto_h;
 482         u8 proto_m;
 483         u16 flags;
 484         u16 result;
 485         u16 mode;
 486 };
 487 
 488 #define ENETC_RFSE_EN   BIT(15)
 489 #define ENETC_RFSE_MODE_BD      2
 490 
 491 static inline void enetc_get_primary_mac_addr(struct enetc_hw *hw, u8 *addr)
 492 {
 493         *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0);
 494         *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1);
 495 }
 496 
 497 #define ENETC_SI_INT_IDX        0
 498 /* base index for Rx/Tx interrupts */
 499 #define ENETC_BDR_INT_BASE_IDX  1
 500 
 501 /* Messaging */
 502 
 503 /* Command completion status */
 504 enum enetc_msg_cmd_status {
 505         ENETC_MSG_CMD_STATUS_OK,
 506         ENETC_MSG_CMD_STATUS_FAIL
 507 };
 508 
 509 /* VSI-PSI command message types */
 510 enum enetc_msg_cmd_type {
 511         ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */
 512         ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */
 513         ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */
 514 };
 515 
 516 /* VSI-PSI command action types */
 517 enum enetc_msg_cmd_action_type {
 518         ENETC_MSG_CMD_MNG_ADD = 1,
 519         ENETC_MSG_CMD_MNG_REMOVE
 520 };
 521 
 522 /* PSI-VSI command header format */
 523 struct enetc_msg_cmd_header {
 524         u16 type;       /* command class type */
 525         u16 id;         /* denotes the specific required action */
 526 };
 527 
 528 /* Common H/W utility functions */
 529 
 530 static inline void enetc_enable_rxvlan(struct enetc_hw *hw, int si_idx,
 531                                        bool en)
 532 {
 533         u32 val = enetc_rxbdr_rd(hw, si_idx, ENETC_RBMR);
 534 
 535         val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0);
 536         enetc_rxbdr_wr(hw, si_idx, ENETC_RBMR, val);
 537 }
 538 
 539 static inline void enetc_enable_txvlan(struct enetc_hw *hw, int si_idx,
 540                                        bool en)
 541 {
 542         u32 val = enetc_txbdr_rd(hw, si_idx, ENETC_TBMR);
 543 
 544         val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0);
 545         enetc_txbdr_wr(hw, si_idx, ENETC_TBMR, val);
 546 }
 547 
 548 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx,
 549                                       int prio)
 550 {
 551         u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR);
 552 
 553         val &= ~ENETC_TBMR_PRIO_MASK;
 554         val |= ENETC_TBMR_SET_PRIO(prio);
 555         enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val);
 556 }

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