drivers/net/ethernet/freescale/fman/fman

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This source file includes following definitions.
init_bmi_rx
init_bmi_tx
init_qmi
stop_port_hwp
start_port_hwp
init_hwp
init
set_bpools
is_init_done
verify_size_of_fifo
set_ext_buffer_pools
init_low_level_driver
fill_soc_specific_params
get_dflt_fifo_deq_pipeline_depth
get_dflt_num_of_tasks
get_dflt_extra_num_of_tasks
get_dflt_num_of_open_dmas
get_dflt_extra_num_of_open_dmas
get_dflt_num_of_fifo_bufs
set_dflt_cfg
set_rx_dflt_cfg
set_tx_dflt_cfg
fman_port_config
fman_port_use_kg_hash
fman_port_init
fman_port_cfg_buf_prefix_content
fman_port_disable
fman_port_enable
fman_port_bind
fman_port_get_qman_channel_id
fman_port_get_hash_result_offset
fman_port_get_tstamp
fman_port_probe
fman_port_load
fman_port_unload
   1 /*
   2  * Copyright 2008 - 2015 Freescale Semiconductor Inc.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are met:
   6  *     * Redistributions of source code must retain the above copyright
   7  *       notice, this list of conditions and the following disclaimer.
   8  *     * Redistributions in binary form must reproduce the above copyright
   9  *       notice, this list of conditions and the following disclaimer in the
  10  *       documentation and/or other materials provided with the distribution.
  11  *     * Neither the name of Freescale Semiconductor nor the
  12  *       names of its contributors may be used to endorse or promote products
  13  *       derived from this software without specific prior written permission.
  14  *
  15  *
  16  * ALTERNATIVELY, this software may be distributed under the terms of the
  17  * GNU General Public License ("GPL") as published by the Free Software
  18  * Foundation, either version 2 of that License or (at your option) any
  19  * later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  22  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32 
  33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  34 
  35 #include <linux/io.h>
  36 #include <linux/slab.h>
  37 #include <linux/module.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/of_platform.h>
  40 #include <linux/of_address.h>
  41 #include <linux/delay.h>
  42 #include <linux/libfdt_env.h>
  43 
  44 #include "fman.h"
  45 #include "fman_port.h"
  46 #include "fman_sp.h"
  47 #include "fman_keygen.h"
  48 
  49 /* Queue ID */
  50 #define DFLT_FQ_ID              0x00FFFFFF
  51 
  52 /* General defines */
  53 #define PORT_BMI_FIFO_UNITS             0x100
  54 
  55 #define MAX_PORT_FIFO_SIZE(bmi_max_fifo_size)   \
  56         min((u32)bmi_max_fifo_size, (u32)1024 * FMAN_BMI_FIFO_UNITS)
  57 
  58 #define PORT_CG_MAP_NUM                 8
  59 #define PORT_PRS_RESULT_WORDS_NUM       8
  60 #define PORT_IC_OFFSET_UNITS            0x10
  61 
  62 #define MIN_EXT_BUF_SIZE                64
  63 
  64 #define BMI_PORT_REGS_OFFSET                            0
  65 #define QMI_PORT_REGS_OFFSET                            0x400
  66 #define HWP_PORT_REGS_OFFSET                            0x800
  67 
  68 /* Default values */
  69 #define DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN              \
  70         DFLT_FM_SP_BUFFER_PREFIX_CONTEXT_DATA_ALIGN
  71 
  72 #define DFLT_PORT_CUT_BYTES_FROM_END            4
  73 
  74 #define DFLT_PORT_ERRORS_TO_DISCARD             FM_PORT_FRM_ERR_CLS_DISCARD
  75 #define DFLT_PORT_MAX_FRAME_LENGTH              9600
  76 
  77 #define DFLT_PORT_RX_FIFO_PRI_ELEVATION_LEV(bmi_max_fifo_size)  \
  78         MAX_PORT_FIFO_SIZE(bmi_max_fifo_size)
  79 
  80 #define DFLT_PORT_RX_FIFO_THRESHOLD(major, bmi_max_fifo_size)   \
  81         (major == 6 ?                                           \
  82         MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) :         \
  83         (MAX_PORT_FIFO_SIZE(bmi_max_fifo_size) * 3 / 4))        \
  84 
  85 #define DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS                0
  86 
  87 /* QMI defines */
  88 #define QMI_DEQ_CFG_SUBPORTAL_MASK              0x1f
  89 
  90 #define QMI_PORT_CFG_EN                         0x80000000
  91 #define QMI_PORT_STATUS_DEQ_FD_BSY              0x20000000
  92 
  93 #define QMI_DEQ_CFG_PRI                         0x80000000
  94 #define QMI_DEQ_CFG_TYPE1                       0x10000000
  95 #define QMI_DEQ_CFG_TYPE2                       0x20000000
  96 #define QMI_DEQ_CFG_TYPE3                       0x30000000
  97 #define QMI_DEQ_CFG_PREFETCH_PARTIAL            0x01000000
  98 #define QMI_DEQ_CFG_PREFETCH_FULL               0x03000000
  99 #define QMI_DEQ_CFG_SP_MASK                     0xf
 100 #define QMI_DEQ_CFG_SP_SHIFT                    20
 101 
 102 #define QMI_BYTE_COUNT_LEVEL_CONTROL(_type)     \
 103         (_type == FMAN_PORT_TYPE_TX ? 0x1400 : 0x400)
 104 
 105 /* BMI defins */
 106 #define BMI_EBD_EN                              0x80000000
 107 
 108 #define BMI_PORT_CFG_EN                         0x80000000
 109 
 110 #define BMI_PORT_STATUS_BSY                     0x80000000
 111 
 112 #define BMI_DMA_ATTR_SWP_SHIFT                  FMAN_SP_DMA_ATTR_SWP_SHIFT
 113 #define BMI_DMA_ATTR_WRITE_OPTIMIZE             FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE
 114 
 115 #define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16
 116 #define BMI_RX_FIFO_THRESHOLD_ETHE              0x80000000
 117 
 118 #define BMI_FRAME_END_CS_IGNORE_SHIFT           24
 119 #define BMI_FRAME_END_CS_IGNORE_MASK            0x0000001f
 120 
 121 #define BMI_RX_FRAME_END_CUT_SHIFT              16
 122 #define BMI_RX_FRAME_END_CUT_MASK               0x0000001f
 123 
 124 #define BMI_IC_TO_EXT_SHIFT                     FMAN_SP_IC_TO_EXT_SHIFT
 125 #define BMI_IC_TO_EXT_MASK                      0x0000001f
 126 #define BMI_IC_FROM_INT_SHIFT                   FMAN_SP_IC_FROM_INT_SHIFT
 127 #define BMI_IC_FROM_INT_MASK                    0x0000000f
 128 #define BMI_IC_SIZE_MASK                        0x0000001f
 129 
 130 #define BMI_INT_BUF_MARG_SHIFT                  28
 131 #define BMI_INT_BUF_MARG_MASK                   0x0000000f
 132 #define BMI_EXT_BUF_MARG_START_SHIFT            FMAN_SP_EXT_BUF_MARG_START_SHIFT
 133 #define BMI_EXT_BUF_MARG_START_MASK             0x000001ff
 134 #define BMI_EXT_BUF_MARG_END_MASK               0x000001ff
 135 
 136 #define BMI_CMD_MR_LEAC                         0x00200000
 137 #define BMI_CMD_MR_SLEAC                        0x00100000
 138 #define BMI_CMD_MR_MA                           0x00080000
 139 #define BMI_CMD_MR_DEAS                         0x00040000
 140 #define BMI_CMD_RX_MR_DEF                       (BMI_CMD_MR_LEAC | \
 141                                                 BMI_CMD_MR_SLEAC | \
 142                                                 BMI_CMD_MR_MA | \
 143                                                 BMI_CMD_MR_DEAS)
 144 #define BMI_CMD_TX_MR_DEF                       0
 145 
 146 #define BMI_CMD_ATTR_ORDER                      0x80000000
 147 #define BMI_CMD_ATTR_SYNC                       0x02000000
 148 #define BMI_CMD_ATTR_COLOR_SHIFT                26
 149 
 150 #define BMI_FIFO_PIPELINE_DEPTH_SHIFT           12
 151 #define BMI_FIFO_PIPELINE_DEPTH_MASK            0x0000000f
 152 #define BMI_NEXT_ENG_FD_BITS_SHIFT              24
 153 
 154 #define BMI_EXT_BUF_POOL_VALID                  FMAN_SP_EXT_BUF_POOL_VALID
 155 #define BMI_EXT_BUF_POOL_EN_COUNTER             FMAN_SP_EXT_BUF_POOL_EN_COUNTER
 156 #define BMI_EXT_BUF_POOL_BACKUP         FMAN_SP_EXT_BUF_POOL_BACKUP
 157 #define BMI_EXT_BUF_POOL_ID_SHIFT               16
 158 #define BMI_EXT_BUF_POOL_ID_MASK                0x003F0000
 159 #define BMI_POOL_DEP_NUM_OF_POOLS_SHIFT 16
 160 
 161 #define BMI_TX_FIFO_MIN_FILL_SHIFT              16
 162 
 163 #define BMI_PRIORITY_ELEVATION_LEVEL ((0x3FF + 1) * PORT_BMI_FIFO_UNITS)
 164 #define BMI_FIFO_THRESHOLD            ((0x3FF + 1) * PORT_BMI_FIFO_UNITS)
 165 
 166 #define BMI_DEQUEUE_PIPELINE_DEPTH(_type, _speed)               \
 167         ((_type == FMAN_PORT_TYPE_TX && _speed == 10000) ? 4 : 1)
 168 
 169 #define RX_ERRS_TO_ENQ                            \
 170         (FM_PORT_FRM_ERR_DMA                    | \
 171         FM_PORT_FRM_ERR_PHYSICAL                | \
 172         FM_PORT_FRM_ERR_SIZE                    | \
 173         FM_PORT_FRM_ERR_EXTRACTION              | \
 174         FM_PORT_FRM_ERR_NO_SCHEME               | \
 175         FM_PORT_FRM_ERR_PRS_TIMEOUT             | \
 176         FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT        | \
 177         FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED    | \
 178         FM_PORT_FRM_ERR_PRS_HDR_ERR             | \
 179         FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW        | \
 180         FM_PORT_FRM_ERR_IPRE)
 181 
 182 /* NIA defines */
 183 #define NIA_ORDER_RESTOR                                0x00800000
 184 #define NIA_ENG_BMI                                     0x00500000
 185 #define NIA_ENG_QMI_ENQ                                 0x00540000
 186 #define NIA_ENG_QMI_DEQ                                 0x00580000
 187 #define NIA_ENG_HWP                                     0x00440000
 188 #define NIA_ENG_HWK                                     0x00480000
 189 #define NIA_BMI_AC_ENQ_FRAME                            0x00000002
 190 #define NIA_BMI_AC_TX_RELEASE                           0x000002C0
 191 #define NIA_BMI_AC_RELEASE                              0x000000C0
 192 #define NIA_BMI_AC_TX                                   0x00000274
 193 #define NIA_BMI_AC_FETCH_ALL_FRAME                      0x0000020c
 194 
 195 /* Port IDs */
 196 #define TX_10G_PORT_BASE                0x30
 197 #define RX_10G_PORT_BASE                0x10
 198 
 199 /* BMI Rx port register map */
 200 struct fman_port_rx_bmi_regs {
 201         u32 fmbm_rcfg;          /* Rx Configuration */
 202         u32 fmbm_rst;           /* Rx Status */
 203         u32 fmbm_rda;           /* Rx DMA attributes */
 204         u32 fmbm_rfp;           /* Rx FIFO Parameters */
 205         u32 fmbm_rfed;          /* Rx Frame End Data */
 206         u32 fmbm_ricp;          /* Rx Internal Context Parameters */
 207         u32 fmbm_rim;           /* Rx Internal Buffer Margins */
 208         u32 fmbm_rebm;          /* Rx External Buffer Margins */
 209         u32 fmbm_rfne;          /* Rx Frame Next Engine */
 210         u32 fmbm_rfca;          /* Rx Frame Command Attributes. */
 211         u32 fmbm_rfpne;         /* Rx Frame Parser Next Engine */
 212         u32 fmbm_rpso;          /* Rx Parse Start Offset */
 213         u32 fmbm_rpp;           /* Rx Policer Profile  */
 214         u32 fmbm_rccb;          /* Rx Coarse Classification Base */
 215         u32 fmbm_reth;          /* Rx Excessive Threshold */
 216         u32 reserved003c[1];    /* (0x03C 0x03F) */
 217         u32 fmbm_rprai[PORT_PRS_RESULT_WORDS_NUM];
 218         /* Rx Parse Results Array Init */
 219         u32 fmbm_rfqid;         /* Rx Frame Queue ID */
 220         u32 fmbm_refqid;        /* Rx Error Frame Queue ID */
 221         u32 fmbm_rfsdm;         /* Rx Frame Status Discard Mask */
 222         u32 fmbm_rfsem;         /* Rx Frame Status Error Mask */
 223         u32 fmbm_rfene;         /* Rx Frame Enqueue Next Engine */
 224         u32 reserved0074[0x2];  /* (0x074-0x07C)  */
 225         u32 fmbm_rcmne;         /* Rx Frame Continuous Mode Next Engine */
 226         u32 reserved0080[0x20]; /* (0x080 0x0FF)  */
 227         u32 fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM];
 228         /* Buffer Manager pool Information- */
 229         u32 fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM];     /* Allocate Counter- */
 230         u32 reserved0130[8];    /* 0x130/0x140 - 0x15F reserved - */
 231         u32 fmbm_rcgm[PORT_CG_MAP_NUM]; /* Congestion Group Map */
 232         u32 fmbm_mpd;           /* BM Pool Depletion  */
 233         u32 reserved0184[0x1F]; /* (0x184 0x1FF) */
 234         u32 fmbm_rstc;          /* Rx Statistics Counters */
 235         u32 fmbm_rfrc;          /* Rx Frame Counter */
 236         u32 fmbm_rfbc;          /* Rx Bad Frames Counter */
 237         u32 fmbm_rlfc;          /* Rx Large Frames Counter */
 238         u32 fmbm_rffc;          /* Rx Filter Frames Counter */
 239         u32 fmbm_rfdc;          /* Rx Frame Discard Counter */
 240         u32 fmbm_rfldec;                /* Rx Frames List DMA Error Counter */
 241         u32 fmbm_rodc;          /* Rx Out of Buffers Discard nntr */
 242         u32 fmbm_rbdc;          /* Rx Buffers Deallocate Counter */
 243         u32 fmbm_rpec;          /* RX Prepare to enqueue Counte */
 244         u32 reserved0224[0x16]; /* (0x224 0x27F) */
 245         u32 fmbm_rpc;           /* Rx Performance Counters */
 246         u32 fmbm_rpcp;          /* Rx Performance Count Parameters */
 247         u32 fmbm_rccn;          /* Rx Cycle Counter */
 248         u32 fmbm_rtuc;          /* Rx Tasks Utilization Counter */
 249         u32 fmbm_rrquc;         /* Rx Receive Queue Utilization cntr */
 250         u32 fmbm_rduc;          /* Rx DMA Utilization Counter */
 251         u32 fmbm_rfuc;          /* Rx FIFO Utilization Counter */
 252         u32 fmbm_rpac;          /* Rx Pause Activation Counter */
 253         u32 reserved02a0[0x18]; /* (0x2A0 0x2FF) */
 254         u32 fmbm_rdcfg[0x3];    /* Rx Debug Configuration */
 255         u32 fmbm_rgpr;          /* Rx General Purpose Register */
 256         u32 reserved0310[0x3a];
 257 };
 258 
 259 /* BMI Tx port register map */
 260 struct fman_port_tx_bmi_regs {
 261         u32 fmbm_tcfg;          /* Tx Configuration */
 262         u32 fmbm_tst;           /* Tx Status */
 263         u32 fmbm_tda;           /* Tx DMA attributes */
 264         u32 fmbm_tfp;           /* Tx FIFO Parameters */
 265         u32 fmbm_tfed;          /* Tx Frame End Data */
 266         u32 fmbm_ticp;          /* Tx Internal Context Parameters */
 267         u32 fmbm_tfdne;         /* Tx Frame Dequeue Next Engine. */
 268         u32 fmbm_tfca;          /* Tx Frame Command attribute. */
 269         u32 fmbm_tcfqid;        /* Tx Confirmation Frame Queue ID. */
 270         u32 fmbm_tefqid;        /* Tx Frame Error Queue ID */
 271         u32 fmbm_tfene;         /* Tx Frame Enqueue Next Engine */
 272         u32 fmbm_trlmts;        /* Tx Rate Limiter Scale */
 273         u32 fmbm_trlmt;         /* Tx Rate Limiter */
 274         u32 reserved0034[0x0e]; /* (0x034-0x6c) */
 275         u32 fmbm_tccb;          /* Tx Coarse Classification base */
 276         u32 fmbm_tfne;          /* Tx Frame Next Engine */
 277         u32 fmbm_tpfcm[0x02];
 278         /* Tx Priority based Flow Control (PFC) Mapping */
 279         u32 fmbm_tcmne;         /* Tx Frame Continuous Mode Next Engine */
 280         u32 reserved0080[0x60]; /* (0x080-0x200) */
 281         u32 fmbm_tstc;          /* Tx Statistics Counters */
 282         u32 fmbm_tfrc;          /* Tx Frame Counter */
 283         u32 fmbm_tfdc;          /* Tx Frames Discard Counter */
 284         u32 fmbm_tfledc;        /* Tx Frame len error discard cntr */
 285         u32 fmbm_tfufdc;        /* Tx Frame unsprt frmt discard cntr */
 286         u32 fmbm_tbdc;          /* Tx Buffers Deallocate Counter */
 287         u32 reserved0218[0x1A]; /* (0x218-0x280) */
 288         u32 fmbm_tpc;           /* Tx Performance Counters */
 289         u32 fmbm_tpcp;          /* Tx Performance Count Parameters */
 290         u32 fmbm_tccn;          /* Tx Cycle Counter */
 291         u32 fmbm_ttuc;          /* Tx Tasks Utilization Counter */
 292         u32 fmbm_ttcquc;        /* Tx Transmit conf Q util Counter */
 293         u32 fmbm_tduc;          /* Tx DMA Utilization Counter */
 294         u32 fmbm_tfuc;          /* Tx FIFO Utilization Counter */
 295         u32 reserved029c[16];   /* (0x29C-0x2FF) */
 296         u32 fmbm_tdcfg[0x3];    /* Tx Debug Configuration */
 297         u32 fmbm_tgpr;          /* Tx General Purpose Register */
 298         u32 reserved0310[0x3a]; /* (0x310-0x3FF) */
 299 };
 300 
 301 /* BMI port register map */
 302 union fman_port_bmi_regs {
 303         struct fman_port_rx_bmi_regs rx;
 304         struct fman_port_tx_bmi_regs tx;
 305 };
 306 
 307 /* QMI port register map */
 308 struct fman_port_qmi_regs {
 309         u32 fmqm_pnc;           /* PortID n Configuration Register */
 310         u32 fmqm_pns;           /* PortID n Status Register */
 311         u32 fmqm_pnts;          /* PortID n Task Status Register */
 312         u32 reserved00c[4];     /* 0xn00C - 0xn01B */
 313         u32 fmqm_pnen;          /* PortID n Enqueue NIA Register */
 314         u32 fmqm_pnetfc;                /* PortID n Enq Total Frame Counter */
 315         u32 reserved024[2];     /* 0xn024 - 0x02B */
 316         u32 fmqm_pndn;          /* PortID n Dequeue NIA Register */
 317         u32 fmqm_pndc;          /* PortID n Dequeue Config Register */
 318         u32 fmqm_pndtfc;                /* PortID n Dequeue tot Frame cntr */
 319         u32 fmqm_pndfdc;                /* PortID n Dequeue FQID Dflt Cntr */
 320         u32 fmqm_pndcc;         /* PortID n Dequeue Confirm Counter */
 321 };
 322 
 323 #define HWP_HXS_COUNT 16
 324 #define HWP_HXS_PHE_REPORT 0x00000800
 325 #define HWP_HXS_PCAC_PSTAT 0x00000100
 326 #define HWP_HXS_PCAC_PSTOP 0x00000001
 327 #define HWP_HXS_TCP_OFFSET 0xA
 328 #define HWP_HXS_UDP_OFFSET 0xB
 329 #define HWP_HXS_SH_PAD_REM 0x80000000
 330 
 331 struct fman_port_hwp_regs {
 332         struct {
 333                 u32 ssa; /* Soft Sequence Attachment */
 334                 u32 lcv; /* Line-up Enable Confirmation Mask */
 335         } pmda[HWP_HXS_COUNT]; /* Parse Memory Direct Access Registers */
 336         u32 reserved080[(0x3f8 - 0x080) / 4]; /* (0x080-0x3f7) */
 337         u32 fmpr_pcac; /* Configuration Access Control */
 338 };
 339 
 340 /* QMI dequeue prefetch modes */
 341 enum fman_port_deq_prefetch {
 342         FMAN_PORT_DEQ_NO_PREFETCH, /* No prefetch mode */
 343         FMAN_PORT_DEQ_PART_PREFETCH, /* Partial prefetch mode */
 344         FMAN_PORT_DEQ_FULL_PREFETCH /* Full prefetch mode */
 345 };
 346 
 347 /* A structure for defining FM port resources */
 348 struct fman_port_rsrc {
 349         u32 num; /* Committed required resource */
 350         u32 extra; /* Extra (not committed) required resource */
 351 };
 352 
 353 enum fman_port_dma_swap {
 354         FMAN_PORT_DMA_NO_SWAP,  /* No swap, transfer data as is */
 355         FMAN_PORT_DMA_SWAP_LE,
 356         /* The transferred data should be swapped in PPC Little Endian mode */
 357         FMAN_PORT_DMA_SWAP_BE
 358         /* The transferred data should be swapped in Big Endian mode */
 359 };
 360 
 361 /* Default port color */
 362 enum fman_port_color {
 363         FMAN_PORT_COLOR_GREEN,  /* Default port color is green */
 364         FMAN_PORT_COLOR_YELLOW, /* Default port color is yellow */
 365         FMAN_PORT_COLOR_RED,            /* Default port color is red */
 366         FMAN_PORT_COLOR_OVERRIDE        /* Ignore color */
 367 };
 368 
 369 /* QMI dequeue from the SP channel - types */
 370 enum fman_port_deq_type {
 371         FMAN_PORT_DEQ_BY_PRI,
 372         /* Priority precedence and Intra-Class scheduling */
 373         FMAN_PORT_DEQ_ACTIVE_FQ,
 374         /* Active FQ precedence and Intra-Class scheduling */
 375         FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS
 376         /* Active FQ precedence and override Intra-Class scheduling */
 377 };
 378 
 379 /* External buffer pools configuration */
 380 struct fman_port_bpools {
 381         u8 count;                       /* Num of pools to set up */
 382         bool counters_enable;           /* Enable allocate counters */
 383         u8 grp_bp_depleted_num;
 384         /* Number of depleted pools - if reached the BMI indicates
 385          * the MAC to send a pause frame
 386          */
 387         struct {
 388                 u8 bpid;                /* BM pool ID */
 389                 u16 size;
 390                 /* Pool's size - must be in ascending order */
 391                 bool is_backup;
 392                 /* If this is a backup pool */
 393                 bool grp_bp_depleted;
 394                 /* Consider this buffer in multiple pools depletion criteria */
 395                 bool single_bp_depleted;
 396                 /* Consider this buffer in single pool depletion criteria */
 397         } bpool[FMAN_PORT_MAX_EXT_POOLS_NUM];
 398 };
 399 
 400 struct fman_port_cfg {
 401         u32 dflt_fqid;
 402         u32 err_fqid;
 403         u32 pcd_base_fqid;
 404         u32 pcd_fqs_count;
 405         u8 deq_sp;
 406         bool deq_high_priority;
 407         enum fman_port_deq_type deq_type;
 408         enum fman_port_deq_prefetch deq_prefetch_option;
 409         u16 deq_byte_cnt;
 410         u8 cheksum_last_bytes_ignore;
 411         u8 rx_cut_end_bytes;
 412         struct fman_buf_pool_depletion buf_pool_depletion;
 413         struct fman_ext_pools ext_buf_pools;
 414         u32 tx_fifo_min_level;
 415         u32 tx_fifo_low_comf_level;
 416         u32 rx_pri_elevation;
 417         u32 rx_fifo_thr;
 418         struct fman_sp_buf_margins buf_margins;
 419         u32 int_buf_start_margin;
 420         struct fman_sp_int_context_data_copy int_context;
 421         u32 discard_mask;
 422         u32 err_mask;
 423         struct fman_buffer_prefix_content buffer_prefix_content;
 424         bool dont_release_buf;
 425 
 426         u8 rx_fd_bits;
 427         u32 tx_fifo_deq_pipeline_depth;
 428         bool errata_A006320;
 429         bool excessive_threshold_register;
 430         bool fmbm_tfne_has_features;
 431 
 432         enum fman_port_dma_swap dma_swap_data;
 433         enum fman_port_color color;
 434 };
 435 
 436 struct fman_port_rx_pools_params {
 437         u8 num_of_pools;
 438         u16 second_largest_buf_size;
 439         u16 largest_buf_size;
 440 };
 441 
 442 struct fman_port_dts_params {
 443         void __iomem *base_addr;        /* FMan port virtual memory */
 444         enum fman_port_type type;       /* Port type */
 445         u16 speed;                      /* Port speed */
 446         u8 id;                          /* HW Port Id */
 447         u32 qman_channel_id;            /* QMan channel id (non RX only) */
 448         struct fman *fman;              /* FMan Handle */
 449 };
 450 
 451 struct fman_port {
 452         void *fm;
 453         struct device *dev;
 454         struct fman_rev_info rev_info;
 455         u8 port_id;
 456         enum fman_port_type port_type;
 457         u16 port_speed;
 458 
 459         union fman_port_bmi_regs __iomem *bmi_regs;
 460         struct fman_port_qmi_regs __iomem *qmi_regs;
 461         struct fman_port_hwp_regs __iomem *hwp_regs;
 462 
 463         struct fman_sp_buffer_offsets buffer_offsets;
 464 
 465         u8 internal_buf_offset;
 466         struct fman_ext_pools ext_buf_pools;
 467 
 468         u16 max_frame_length;
 469         struct fman_port_rsrc open_dmas;
 470         struct fman_port_rsrc tasks;
 471         struct fman_port_rsrc fifo_bufs;
 472         struct fman_port_rx_pools_params rx_pools_params;
 473 
 474         struct fman_port_cfg *cfg;
 475         struct fman_port_dts_params dts_params;
 476 
 477         u8 ext_pools_num;
 478         u32 max_port_fifo_size;
 479         u32 max_num_of_ext_pools;
 480         u32 max_num_of_sub_portals;
 481         u32 bm_max_num_of_pools;
 482 };
 483 
 484 static int init_bmi_rx(struct fman_port *port)
 485 {
 486         struct fman_port_rx_bmi_regs __iomem *regs = &port->bmi_regs->rx;
 487         struct fman_port_cfg *cfg = port->cfg;
 488         u32 tmp;
 489 
 490         /* DMA attributes */
 491         tmp = (u32)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT;
 492         /* Enable write optimization */
 493         tmp |= BMI_DMA_ATTR_WRITE_OPTIMIZE;
 494         iowrite32be(tmp, &regs->fmbm_rda);
 495 
 496         /* Rx FIFO parameters */
 497         tmp = (cfg->rx_pri_elevation / PORT_BMI_FIFO_UNITS - 1) <<
 498                 BMI_RX_FIFO_PRI_ELEVATION_SHIFT;
 499         tmp |= cfg->rx_fifo_thr / PORT_BMI_FIFO_UNITS - 1;
 500         iowrite32be(tmp, &regs->fmbm_rfp);
 501 
 502         if (cfg->excessive_threshold_register)
 503                 /* always allow access to the extra resources */
 504                 iowrite32be(BMI_RX_FIFO_THRESHOLD_ETHE, &regs->fmbm_reth);
 505 
 506         /* Frame end data */
 507         tmp = (cfg->cheksum_last_bytes_ignore & BMI_FRAME_END_CS_IGNORE_MASK) <<
 508                 BMI_FRAME_END_CS_IGNORE_SHIFT;
 509         tmp |= (cfg->rx_cut_end_bytes & BMI_RX_FRAME_END_CUT_MASK) <<
 510                 BMI_RX_FRAME_END_CUT_SHIFT;
 511         if (cfg->errata_A006320)
 512                 tmp &= 0xffe0ffff;
 513         iowrite32be(tmp, &regs->fmbm_rfed);
 514 
 515         /* Internal context parameters */
 516         tmp = ((cfg->int_context.ext_buf_offset / PORT_IC_OFFSET_UNITS) &
 517                 BMI_IC_TO_EXT_MASK) << BMI_IC_TO_EXT_SHIFT;
 518         tmp |= ((cfg->int_context.int_context_offset / PORT_IC_OFFSET_UNITS) &
 519                 BMI_IC_FROM_INT_MASK) << BMI_IC_FROM_INT_SHIFT;
 520         tmp |= (cfg->int_context.size / PORT_IC_OFFSET_UNITS) &
 521                 BMI_IC_SIZE_MASK;
 522         iowrite32be(tmp, &regs->fmbm_ricp);
 523 
 524         /* Internal buffer offset */
 525         tmp = ((cfg->int_buf_start_margin / PORT_IC_OFFSET_UNITS) &
 526                 BMI_INT_BUF_MARG_MASK) << BMI_INT_BUF_MARG_SHIFT;
 527         iowrite32be(tmp, &regs->fmbm_rim);
 528 
 529         /* External buffer margins */
 530         tmp = (cfg->buf_margins.start_margins & BMI_EXT_BUF_MARG_START_MASK) <<
 531                 BMI_EXT_BUF_MARG_START_SHIFT;
 532         tmp |= cfg->buf_margins.end_margins & BMI_EXT_BUF_MARG_END_MASK;
 533         iowrite32be(tmp, &regs->fmbm_rebm);
 534 
 535         /* Frame attributes */
 536         tmp = BMI_CMD_RX_MR_DEF;
 537         tmp |= BMI_CMD_ATTR_ORDER;
 538         tmp |= (u32)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT;
 539         /* Synchronization request */
 540         tmp |= BMI_CMD_ATTR_SYNC;
 541 
 542         iowrite32be(tmp, &regs->fmbm_rfca);
 543 
 544         /* NIA */
 545         tmp = (u32)cfg->rx_fd_bits << BMI_NEXT_ENG_FD_BITS_SHIFT;
 546 
 547         tmp |= NIA_ENG_HWP;
 548         iowrite32be(tmp, &regs->fmbm_rfne);
 549 
 550         /* Parser Next Engine NIA */
 551         iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME, &regs->fmbm_rfpne);
 552 
 553         /* Enqueue NIA */
 554         iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, &regs->fmbm_rfene);
 555 
 556         /* Default/error queues */
 557         iowrite32be((cfg->dflt_fqid & DFLT_FQ_ID), &regs->fmbm_rfqid);
 558         iowrite32be((cfg->err_fqid & DFLT_FQ_ID), &regs->fmbm_refqid);
 559 
 560         /* Discard/error masks */
 561         iowrite32be(cfg->discard_mask, &regs->fmbm_rfsdm);
 562         iowrite32be(cfg->err_mask, &regs->fmbm_rfsem);
 563 
 564         return 0;
 565 }
 566 
 567 static int init_bmi_tx(struct fman_port *port)
 568 {
 569         struct fman_port_tx_bmi_regs __iomem *regs = &port->bmi_regs->tx;
 570         struct fman_port_cfg *cfg = port->cfg;
 571         u32 tmp;
 572 
 573         /* Tx Configuration register */
 574         tmp = 0;
 575         iowrite32be(tmp, &regs->fmbm_tcfg);
 576 
 577         /* DMA attributes */
 578         tmp = (u32)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT;
 579         iowrite32be(tmp, &regs->fmbm_tda);
 580 
 581         /* Tx FIFO parameters */
 582         tmp = (cfg->tx_fifo_min_level / PORT_BMI_FIFO_UNITS) <<
 583                 BMI_TX_FIFO_MIN_FILL_SHIFT;
 584         tmp |= ((cfg->tx_fifo_deq_pipeline_depth - 1) &
 585                 BMI_FIFO_PIPELINE_DEPTH_MASK) << BMI_FIFO_PIPELINE_DEPTH_SHIFT;
 586         tmp |= (cfg->tx_fifo_low_comf_level / PORT_BMI_FIFO_UNITS) - 1;
 587         iowrite32be(tmp, &regs->fmbm_tfp);
 588 
 589         /* Frame end data */
 590         tmp = (cfg->cheksum_last_bytes_ignore & BMI_FRAME_END_CS_IGNORE_MASK) <<
 591                 BMI_FRAME_END_CS_IGNORE_SHIFT;
 592         iowrite32be(tmp, &regs->fmbm_tfed);
 593 
 594         /* Internal context parameters */
 595         tmp = ((cfg->int_context.ext_buf_offset / PORT_IC_OFFSET_UNITS) &
 596                 BMI_IC_TO_EXT_MASK) << BMI_IC_TO_EXT_SHIFT;
 597         tmp |= ((cfg->int_context.int_context_offset / PORT_IC_OFFSET_UNITS) &
 598                 BMI_IC_FROM_INT_MASK) << BMI_IC_FROM_INT_SHIFT;
 599         tmp |= (cfg->int_context.size / PORT_IC_OFFSET_UNITS) &
 600                 BMI_IC_SIZE_MASK;
 601         iowrite32be(tmp, &regs->fmbm_ticp);
 602 
 603         /* Frame attributes */
 604         tmp = BMI_CMD_TX_MR_DEF;
 605         tmp |= BMI_CMD_ATTR_ORDER;
 606         tmp |= (u32)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT;
 607         iowrite32be(tmp, &regs->fmbm_tfca);
 608 
 609         /* Dequeue NIA + enqueue NIA */
 610         iowrite32be(NIA_ENG_QMI_DEQ, &regs->fmbm_tfdne);
 611         iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, &regs->fmbm_tfene);
 612         if (cfg->fmbm_tfne_has_features)
 613                 iowrite32be(!cfg->dflt_fqid ?
 614                             BMI_EBD_EN | NIA_BMI_AC_FETCH_ALL_FRAME :
 615                             NIA_BMI_AC_FETCH_ALL_FRAME, &regs->fmbm_tfne);
 616         if (!cfg->dflt_fqid && cfg->dont_release_buf) {
 617                 iowrite32be(DFLT_FQ_ID, &regs->fmbm_tcfqid);
 618                 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE,
 619                             &regs->fmbm_tfene);
 620                 if (cfg->fmbm_tfne_has_features)
 621                         iowrite32be(ioread32be(&regs->fmbm_tfne) & ~BMI_EBD_EN,
 622                                     &regs->fmbm_tfne);
 623         }
 624 
 625         /* Confirmation/error queues */
 626         if (cfg->dflt_fqid || !cfg->dont_release_buf)
 627                 iowrite32be(cfg->dflt_fqid & DFLT_FQ_ID, &regs->fmbm_tcfqid);
 628         iowrite32be((cfg->err_fqid & DFLT_FQ_ID), &regs->fmbm_tefqid);
 629 
 630         return 0;
 631 }
 632 
 633 static int init_qmi(struct fman_port *port)
 634 {
 635         struct fman_port_qmi_regs __iomem *regs = port->qmi_regs;
 636         struct fman_port_cfg *cfg = port->cfg;
 637         u32 tmp;
 638 
 639         /* Rx port configuration */
 640         if (port->port_type == FMAN_PORT_TYPE_RX) {
 641                 /* Enqueue NIA */
 642                 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_RELEASE, &regs->fmqm_pnen);
 643                 return 0;
 644         }
 645 
 646         /* Continue with Tx port configuration */
 647         if (port->port_type == FMAN_PORT_TYPE_TX) {
 648                 /* Enqueue NIA */
 649                 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE,
 650                             &regs->fmqm_pnen);
 651                 /* Dequeue NIA */
 652                 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX, &regs->fmqm_pndn);
 653         }
 654 
 655         /* Dequeue Configuration register */
 656         tmp = 0;
 657         if (cfg->deq_high_priority)
 658                 tmp |= QMI_DEQ_CFG_PRI;
 659 
 660         switch (cfg->deq_type) {
 661         case FMAN_PORT_DEQ_BY_PRI:
 662                 tmp |= QMI_DEQ_CFG_TYPE1;
 663                 break;
 664         case FMAN_PORT_DEQ_ACTIVE_FQ:
 665                 tmp |= QMI_DEQ_CFG_TYPE2;
 666                 break;
 667         case FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS:
 668                 tmp |= QMI_DEQ_CFG_TYPE3;
 669                 break;
 670         default:
 671                 return -EINVAL;
 672         }
 673 
 674         switch (cfg->deq_prefetch_option) {
 675         case FMAN_PORT_DEQ_NO_PREFETCH:
 676                 break;
 677         case FMAN_PORT_DEQ_PART_PREFETCH:
 678                 tmp |= QMI_DEQ_CFG_PREFETCH_PARTIAL;
 679                 break;
 680         case FMAN_PORT_DEQ_FULL_PREFETCH:
 681                 tmp |= QMI_DEQ_CFG_PREFETCH_FULL;
 682                 break;
 683         default:
 684                 return -EINVAL;
 685         }
 686 
 687         tmp |= (cfg->deq_sp & QMI_DEQ_CFG_SP_MASK) << QMI_DEQ_CFG_SP_SHIFT;
 688         tmp |= cfg->deq_byte_cnt;
 689         iowrite32be(tmp, &regs->fmqm_pndc);
 690 
 691         return 0;
 692 }
 693 
 694 static void stop_port_hwp(struct fman_port *port)
 695 {
 696         struct fman_port_hwp_regs __iomem *regs = port->hwp_regs;
 697         int cnt = 100;
 698 
 699         iowrite32be(HWP_HXS_PCAC_PSTOP, &regs->fmpr_pcac);
 700 
 701         while (cnt-- > 0 &&
 702                (ioread32be(&regs->fmpr_pcac) & HWP_HXS_PCAC_PSTAT))
 703                 udelay(10);
 704         if (!cnt)
 705                 pr_err("Timeout stopping HW Parser\n");
 706 }
 707 
 708 static void start_port_hwp(struct fman_port *port)
 709 {
 710         struct fman_port_hwp_regs __iomem *regs = port->hwp_regs;
 711         int cnt = 100;
 712 
 713         iowrite32be(0, &regs->fmpr_pcac);
 714 
 715         while (cnt-- > 0 &&
 716                !(ioread32be(&regs->fmpr_pcac) & HWP_HXS_PCAC_PSTAT))
 717                 udelay(10);
 718         if (!cnt)
 719                 pr_err("Timeout starting HW Parser\n");
 720 }
 721 
 722 static void init_hwp(struct fman_port *port)
 723 {
 724         struct fman_port_hwp_regs __iomem *regs = port->hwp_regs;
 725         int i;
 726 
 727         stop_port_hwp(port);
 728 
 729         for (i = 0; i < HWP_HXS_COUNT; i++) {
 730                 /* enable HXS error reporting into FD[STATUS] PHE */
 731                 iowrite32be(0x00000000, &regs->pmda[i].ssa);
 732                 iowrite32be(0xffffffff, &regs->pmda[i].lcv);
 733         }
 734 
 735         /* Short packet padding removal from checksum calculation */
 736         iowrite32be(HWP_HXS_SH_PAD_REM, &regs->pmda[HWP_HXS_TCP_OFFSET].ssa);
 737         iowrite32be(HWP_HXS_SH_PAD_REM, &regs->pmda[HWP_HXS_UDP_OFFSET].ssa);
 738 
 739         start_port_hwp(port);
 740 }
 741 
 742 static int init(struct fman_port *port)
 743 {
 744         int err;
 745 
 746         /* Init BMI registers */
 747         switch (port->port_type) {
 748         case FMAN_PORT_TYPE_RX:
 749                 err = init_bmi_rx(port);
 750                 if (!err)
 751                         init_hwp(port);
 752                 break;
 753         case FMAN_PORT_TYPE_TX:
 754                 err = init_bmi_tx(port);
 755                 break;
 756         default:
 757                 return -EINVAL;
 758         }
 759 
 760         if (err)
 761                 return err;
 762 
 763         /* Init QMI registers */
 764         err = init_qmi(port);
 765         if (err)
 766                 return err;
 767 
 768         return 0;
 769 }
 770 
 771 static int set_bpools(const struct fman_port *port,
 772                       const struct fman_port_bpools *bp)
 773 {
 774         u32 __iomem *bp_reg, *bp_depl_reg;
 775         u32 tmp;
 776         u8 i, max_bp_num;
 777         bool grp_depl_used = false, rx_port;
 778 
 779         switch (port->port_type) {
 780         case FMAN_PORT_TYPE_RX:
 781                 max_bp_num = port->ext_pools_num;
 782                 rx_port = true;
 783                 bp_reg = port->bmi_regs->rx.fmbm_ebmpi;
 784                 bp_depl_reg = &port->bmi_regs->rx.fmbm_mpd;
 785                 break;
 786         default:
 787                 return -EINVAL;
 788         }
 789 
 790         if (rx_port) {
 791                 /* Check buffers are provided in ascending order */
 792                 for (i = 0; (i < (bp->count - 1) &&
 793                              (i < FMAN_PORT_MAX_EXT_POOLS_NUM - 1)); i++) {
 794                         if (bp->bpool[i].size > bp->bpool[i + 1].size)
 795                                 return -EINVAL;
 796                 }
 797         }
 798 
 799         /* Set up external buffers pools */
 800         for (i = 0; i < bp->count; i++) {
 801                 tmp = BMI_EXT_BUF_POOL_VALID;
 802                 tmp |= ((u32)bp->bpool[i].bpid <<
 803                         BMI_EXT_BUF_POOL_ID_SHIFT) & BMI_EXT_BUF_POOL_ID_MASK;
 804 
 805                 if (rx_port) {
 806                         if (bp->counters_enable)
 807                                 tmp |= BMI_EXT_BUF_POOL_EN_COUNTER;
 808 
 809                         if (bp->bpool[i].is_backup)
 810                                 tmp |= BMI_EXT_BUF_POOL_BACKUP;
 811 
 812                         tmp |= (u32)bp->bpool[i].size;
 813                 }
 814 
 815                 iowrite32be(tmp, &bp_reg[i]);
 816         }
 817 
 818         /* Clear unused pools */
 819         for (i = bp->count; i < max_bp_num; i++)
 820                 iowrite32be(0, &bp_reg[i]);
 821 
 822         /* Pools depletion */
 823         tmp = 0;
 824         for (i = 0; i < FMAN_PORT_MAX_EXT_POOLS_NUM; i++) {
 825                 if (bp->bpool[i].grp_bp_depleted) {
 826                         grp_depl_used = true;
 827                         tmp |= 0x80000000 >> i;
 828                 }
 829 
 830                 if (bp->bpool[i].single_bp_depleted)
 831                         tmp |= 0x80 >> i;
 832         }
 833 
 834         if (grp_depl_used)
 835                 tmp |= ((u32)bp->grp_bp_depleted_num - 1) <<
 836                     BMI_POOL_DEP_NUM_OF_POOLS_SHIFT;
 837 
 838         iowrite32be(tmp, bp_depl_reg);
 839         return 0;
 840 }
 841 
 842 static bool is_init_done(struct fman_port_cfg *cfg)
 843 {
 844         /* Checks if FMan port driver parameters were initialized */
 845         if (!cfg)
 846                 return true;
 847 
 848         return false;
 849 }
 850 
 851 static int verify_size_of_fifo(struct fman_port *port)
 852 {
 853         u32 min_fifo_size_required = 0, opt_fifo_size_for_b2b = 0;
 854 
 855         /* TX Ports */
 856         if (port->port_type == FMAN_PORT_TYPE_TX) {
 857                 min_fifo_size_required = (u32)
 858                     (roundup(port->max_frame_length,
 859                              FMAN_BMI_FIFO_UNITS) + (3 * FMAN_BMI_FIFO_UNITS));
 860 
 861                 min_fifo_size_required +=
 862                     port->cfg->tx_fifo_deq_pipeline_depth *
 863                     FMAN_BMI_FIFO_UNITS;
 864 
 865                 opt_fifo_size_for_b2b = min_fifo_size_required;
 866 
 867                 /* Add some margin for back-to-back capability to improve
 868                  * performance, allows the hardware to pipeline new frame dma
 869                  * while the previous frame not yet transmitted.
 870                  */
 871                 if (port->port_speed == 10000)
 872                         opt_fifo_size_for_b2b += 3 * FMAN_BMI_FIFO_UNITS;
 873                 else
 874                         opt_fifo_size_for_b2b += 2 * FMAN_BMI_FIFO_UNITS;
 875         }
 876 
 877         /* RX Ports */
 878         else if (port->port_type == FMAN_PORT_TYPE_RX) {
 879                 if (port->rev_info.major >= 6)
 880                         min_fifo_size_required = (u32)
 881                         (roundup(port->max_frame_length,
 882                                  FMAN_BMI_FIFO_UNITS) +
 883                                  (5 * FMAN_BMI_FIFO_UNITS));
 884                         /* 4 according to spec + 1 for FOF>0 */
 885                 else
 886                         min_fifo_size_required = (u32)
 887                         (roundup(min(port->max_frame_length,
 888                                      port->rx_pools_params.largest_buf_size),
 889                                      FMAN_BMI_FIFO_UNITS) +
 890                                      (7 * FMAN_BMI_FIFO_UNITS));
 891 
 892                 opt_fifo_size_for_b2b = min_fifo_size_required;
 893 
 894                 /* Add some margin for back-to-back capability to improve
 895                  * performance,allows the hardware to pipeline new frame dma
 896                  * while the previous frame not yet transmitted.
 897                  */
 898                 if (port->port_speed == 10000)
 899                         opt_fifo_size_for_b2b += 8 * FMAN_BMI_FIFO_UNITS;
 900                 else
 901                         opt_fifo_size_for_b2b += 3 * FMAN_BMI_FIFO_UNITS;
 902         }
 903 
 904         WARN_ON(min_fifo_size_required <= 0);
 905         WARN_ON(opt_fifo_size_for_b2b < min_fifo_size_required);
 906 
 907         /* Verify the size  */
 908         if (port->fifo_bufs.num < min_fifo_size_required)
 909                 dev_dbg(port->dev, "%s: FIFO size should be enlarged to %d bytes\n",
 910                         __func__, min_fifo_size_required);
 911         else if (port->fifo_bufs.num < opt_fifo_size_for_b2b)
 912                 dev_dbg(port->dev, "%s: For b2b processing,FIFO may be enlarged to %d bytes\n",
 913                         __func__, opt_fifo_size_for_b2b);
 914 
 915         return 0;
 916 }
 917 
 918 static int set_ext_buffer_pools(struct fman_port *port)
 919 {
 920         struct fman_ext_pools *ext_buf_pools = &port->cfg->ext_buf_pools;
 921         struct fman_buf_pool_depletion *buf_pool_depletion =
 922         &port->cfg->buf_pool_depletion;
 923         u8 ordered_array[FMAN_PORT_MAX_EXT_POOLS_NUM];
 924         u16 sizes_array[BM_MAX_NUM_OF_POOLS];
 925         int i = 0, j = 0, err;
 926         struct fman_port_bpools bpools;
 927 
 928         memset(&ordered_array, 0, sizeof(u8) * FMAN_PORT_MAX_EXT_POOLS_NUM);
 929         memset(&sizes_array, 0, sizeof(u16) * BM_MAX_NUM_OF_POOLS);
 930         memcpy(&port->ext_buf_pools, ext_buf_pools,
 931                sizeof(struct fman_ext_pools));
 932 
 933         fman_sp_set_buf_pools_in_asc_order_of_buf_sizes(ext_buf_pools,
 934                                                         ordered_array,
 935                                                         sizes_array);
 936 
 937         memset(&bpools, 0, sizeof(struct fman_port_bpools));
 938         bpools.count = ext_buf_pools->num_of_pools_used;
 939         bpools.counters_enable = true;
 940         for (i = 0; i < ext_buf_pools->num_of_pools_used; i++) {
 941                 bpools.bpool[i].bpid = ordered_array[i];
 942                 bpools.bpool[i].size = sizes_array[ordered_array[i]];
 943         }
 944 
 945         /* save pools parameters for later use */
 946         port->rx_pools_params.num_of_pools = ext_buf_pools->num_of_pools_used;
 947         port->rx_pools_params.largest_buf_size =
 948             sizes_array[ordered_array[ext_buf_pools->num_of_pools_used - 1]];
 949         port->rx_pools_params.second_largest_buf_size =
 950             sizes_array[ordered_array[ext_buf_pools->num_of_pools_used - 2]];
 951 
 952         /* FMBM_RMPD reg. - pool depletion */
 953         if (buf_pool_depletion->pools_grp_mode_enable) {
 954                 bpools.grp_bp_depleted_num = buf_pool_depletion->num_of_pools;
 955                 for (i = 0; i < port->bm_max_num_of_pools; i++) {
 956                         if (buf_pool_depletion->pools_to_consider[i]) {
 957                                 for (j = 0; j < ext_buf_pools->
 958                                      num_of_pools_used; j++) {
 959                                         if (i == ordered_array[j]) {
 960                                                 bpools.bpool[j].
 961                                                     grp_bp_depleted = true;
 962                                                 break;
 963                                         }
 964                                 }
 965                         }
 966                 }
 967         }
 968 
 969         if (buf_pool_depletion->single_pool_mode_enable) {
 970                 for (i = 0; i < port->bm_max_num_of_pools; i++) {
 971                         if (buf_pool_depletion->
 972                             pools_to_consider_for_single_mode[i]) {
 973                                 for (j = 0; j < ext_buf_pools->
 974                                      num_of_pools_used; j++) {
 975                                         if (i == ordered_array[j]) {
 976                                                 bpools.bpool[j].
 977                                                     single_bp_depleted = true;
 978                                                 break;
 979                                         }
 980                                 }
 981                         }
 982                 }
 983         }
 984 
 985         err = set_bpools(port, &bpools);
 986         if (err != 0) {
 987                 dev_err(port->dev, "%s: set_bpools() failed\n", __func__);
 988                 return -EINVAL;
 989         }
 990 
 991         return 0;
 992 }
 993 
 994 static int init_low_level_driver(struct fman_port *port)
 995 {
 996         struct fman_port_cfg *cfg = port->cfg;
 997         u32 tmp_val;
 998 
 999         switch (port->port_type) {
1000         case FMAN_PORT_TYPE_RX:
1001                 cfg->err_mask = (RX_ERRS_TO_ENQ & ~cfg->discard_mask);
1002                 break;
1003         default:
1004                 break;
1005         }
1006 
1007         tmp_val = (u32)((port->internal_buf_offset % OFFSET_UNITS) ?
1008                 (port->internal_buf_offset / OFFSET_UNITS + 1) :
1009                 (port->internal_buf_offset / OFFSET_UNITS));
1010         port->internal_buf_offset = (u8)(tmp_val * OFFSET_UNITS);
1011         port->cfg->int_buf_start_margin = port->internal_buf_offset;
1012 
1013         if (init(port) != 0) {
1014                 dev_err(port->dev, "%s: fman port initialization failed\n",
1015                         __func__);
1016                 return -ENODEV;
1017         }
1018 
1019         /* The code bellow is a trick so the FM will not release the buffer
1020          * to BM nor will try to enqueue the frame to QM
1021          */
1022         if (port->port_type == FMAN_PORT_TYPE_TX) {
1023                 if (!cfg->dflt_fqid && cfg->dont_release_buf) {
1024                         /* override fmbm_tcfqid 0 with a false non-0 value.
1025                          * This will force FM to act according to tfene.
1026                          * Otherwise, if fmbm_tcfqid is 0 the FM will release
1027                          * buffers to BM regardless of fmbm_tfene
1028                          */
1029                         iowrite32be(0xFFFFFF, &port->bmi_regs->tx.fmbm_tcfqid);
1030                         iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE,
1031                                     &port->bmi_regs->tx.fmbm_tfene);
1032                 }
1033         }
1034 
1035         return 0;
1036 }
1037 
1038 static int fill_soc_specific_params(struct fman_port *port)
1039 {
1040         u32 bmi_max_fifo_size;
1041 
1042         bmi_max_fifo_size = fman_get_bmi_max_fifo_size(port->fm);
1043         port->max_port_fifo_size = MAX_PORT_FIFO_SIZE(bmi_max_fifo_size);
1044         port->bm_max_num_of_pools = 64;
1045 
1046         /* P4080 - Major 2
1047          * P2041/P3041/P5020/P5040 - Major 3
1048          * Tx/Bx - Major 6
1049          */
1050         switch (port->rev_info.major) {
1051         case 2:
1052         case 3:
1053                 port->max_num_of_ext_pools              = 4;
1054                 port->max_num_of_sub_portals            = 12;
1055                 break;
1056 
1057         case 6:
1058                 port->max_num_of_ext_pools              = 8;
1059                 port->max_num_of_sub_portals            = 16;
1060                 break;
1061 
1062         default:
1063                 dev_err(port->dev, "%s: Unsupported FMan version\n", __func__);
1064                 return -EINVAL;
1065         }
1066 
1067         return 0;
1068 }
1069 
1070 static int get_dflt_fifo_deq_pipeline_depth(u8 major, enum fman_port_type type,
1071                                             u16 speed)
1072 {
1073         switch (type) {
1074         case FMAN_PORT_TYPE_RX:
1075         case FMAN_PORT_TYPE_TX:
1076                 switch (speed) {
1077                 case 10000:
1078                         return 4;
1079                 case 1000:
1080                         if (major >= 6)
1081                                 return 2;
1082                         else
1083                                 return 1;
1084                 default:
1085                         return 0;
1086                 }
1087         default:
1088                 return 0;
1089         }
1090 }
1091 
1092 static int get_dflt_num_of_tasks(u8 major, enum fman_port_type type,
1093                                  u16 speed)
1094 {
1095         switch (type) {
1096         case FMAN_PORT_TYPE_RX:
1097         case FMAN_PORT_TYPE_TX:
1098                 switch (speed) {
1099                 case 10000:
1100                         return 16;
1101                 case 1000:
1102                         if (major >= 6)
1103                                 return 4;
1104                         else
1105                                 return 3;
1106                 default:
1107                         return 0;
1108                 }
1109         default:
1110                 return 0;
1111         }
1112 }
1113 
1114 static int get_dflt_extra_num_of_tasks(u8 major, enum fman_port_type type,
1115                                        u16 speed)
1116 {
1117         switch (type) {
1118         case FMAN_PORT_TYPE_RX:
1119                 /* FMan V3 */
1120                 if (major >= 6)
1121                         return 0;
1122 
1123                 /* FMan V2 */
1124                 if (speed == 10000)
1125                         return 8;
1126                 else
1127                         return 2;
1128         case FMAN_PORT_TYPE_TX:
1129         default:
1130                 return 0;
1131         }
1132 }
1133 
1134 static int get_dflt_num_of_open_dmas(u8 major, enum fman_port_type type,
1135                                      u16 speed)
1136 {
1137         int val;
1138 
1139         if (major >= 6) {
1140                 switch (type) {
1141                 case FMAN_PORT_TYPE_TX:
1142                         if (speed == 10000)
1143                                 val = 12;
1144                         else
1145                                 val = 3;
1146                         break;
1147                 case FMAN_PORT_TYPE_RX:
1148                         if (speed == 10000)
1149                                 val = 8;
1150                         else
1151                                 val = 2;
1152                         break;
1153                 default:
1154                         return 0;
1155                 }
1156         } else {
1157                 switch (type) {
1158                 case FMAN_PORT_TYPE_TX:
1159                 case FMAN_PORT_TYPE_RX:
1160                         if (speed == 10000)
1161                                 val = 8;
1162                         else
1163                                 val = 1;
1164                         break;
1165                 default:
1166                         val = 0;
1167                 }
1168         }
1169 
1170         return val;
1171 }
1172 
1173 static int get_dflt_extra_num_of_open_dmas(u8 major, enum fman_port_type type,
1174                                            u16 speed)
1175 {
1176         /* FMan V3 */
1177         if (major >= 6)
1178                 return 0;
1179 
1180         /* FMan V2 */
1181         switch (type) {
1182         case FMAN_PORT_TYPE_RX:
1183         case FMAN_PORT_TYPE_TX:
1184                 if (speed == 10000)
1185                         return 8;
1186                 else
1187                         return 1;
1188         default:
1189                 return 0;
1190         }
1191 }
1192 
1193 static int get_dflt_num_of_fifo_bufs(u8 major, enum fman_port_type type,
1194                                      u16 speed)
1195 {
1196         int val;
1197 
1198         if (major >= 6) {
1199                 switch (type) {
1200                 case FMAN_PORT_TYPE_TX:
1201                         if (speed == 10000)
1202                                 val = 64;
1203                         else
1204                                 val = 50;
1205                         break;
1206                 case FMAN_PORT_TYPE_RX:
1207                         if (speed == 10000)
1208                                 val = 96;
1209                         else
1210                                 val = 50;
1211                         break;
1212                 default:
1213                         val = 0;
1214                 }
1215         } else {
1216                 switch (type) {
1217                 case FMAN_PORT_TYPE_TX:
1218                         if (speed == 10000)
1219                                 val = 48;
1220                         else
1221                                 val = 44;
1222                         break;
1223                 case FMAN_PORT_TYPE_RX:
1224                         if (speed == 10000)
1225                                 val = 48;
1226                         else
1227                                 val = 45;
1228                         break;
1229                 default:
1230                         val = 0;
1231                 }
1232         }
1233 
1234         return val;
1235 }
1236 
1237 static void set_dflt_cfg(struct fman_port *port,
1238                          struct fman_port_params *port_params)
1239 {
1240         struct fman_port_cfg *cfg = port->cfg;
1241 
1242         cfg->dma_swap_data = FMAN_PORT_DMA_NO_SWAP;
1243         cfg->color = FMAN_PORT_COLOR_GREEN;
1244         cfg->rx_cut_end_bytes = DFLT_PORT_CUT_BYTES_FROM_END;
1245         cfg->rx_pri_elevation = BMI_PRIORITY_ELEVATION_LEVEL;
1246         cfg->rx_fifo_thr = BMI_FIFO_THRESHOLD;
1247         cfg->tx_fifo_low_comf_level = (5 * 1024);
1248         cfg->deq_type = FMAN_PORT_DEQ_BY_PRI;
1249         cfg->deq_prefetch_option = FMAN_PORT_DEQ_FULL_PREFETCH;
1250         cfg->tx_fifo_deq_pipeline_depth =
1251                 BMI_DEQUEUE_PIPELINE_DEPTH(port->port_type, port->port_speed);
1252         cfg->deq_byte_cnt = QMI_BYTE_COUNT_LEVEL_CONTROL(port->port_type);
1253 
1254         cfg->rx_pri_elevation =
1255                 DFLT_PORT_RX_FIFO_PRI_ELEVATION_LEV(port->max_port_fifo_size);
1256         port->cfg->rx_fifo_thr =
1257                 DFLT_PORT_RX_FIFO_THRESHOLD(port->rev_info.major,
1258                                             port->max_port_fifo_size);
1259 
1260         if ((port->rev_info.major == 6) &&
1261             ((port->rev_info.minor == 0) || (port->rev_info.minor == 3)))
1262                 cfg->errata_A006320 = true;
1263 
1264         /* Excessive Threshold register - exists for pre-FMv3 chips only */
1265         if (port->rev_info.major < 6)
1266                 cfg->excessive_threshold_register = true;
1267         else
1268                 cfg->fmbm_tfne_has_features = true;
1269 
1270         cfg->buffer_prefix_content.data_align =
1271                 DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN;
1272 }
1273 
1274 static void set_rx_dflt_cfg(struct fman_port *port,
1275                             struct fman_port_params *port_params)
1276 {
1277         port->cfg->discard_mask = DFLT_PORT_ERRORS_TO_DISCARD;
1278 
1279         memcpy(&port->cfg->ext_buf_pools,
1280                &port_params->specific_params.rx_params.ext_buf_pools,
1281                sizeof(struct fman_ext_pools));
1282         port->cfg->err_fqid =
1283                 port_params->specific_params.rx_params.err_fqid;
1284         port->cfg->dflt_fqid =
1285                 port_params->specific_params.rx_params.dflt_fqid;
1286         port->cfg->pcd_base_fqid =
1287                 port_params->specific_params.rx_params.pcd_base_fqid;
1288         port->cfg->pcd_fqs_count =
1289                 port_params->specific_params.rx_params.pcd_fqs_count;
1290 }
1291 
1292 static void set_tx_dflt_cfg(struct fman_port *port,
1293                             struct fman_port_params *port_params,
1294                             struct fman_port_dts_params *dts_params)
1295 {
1296         port->cfg->tx_fifo_deq_pipeline_depth =
1297                 get_dflt_fifo_deq_pipeline_depth(port->rev_info.major,
1298                                                  port->port_type,
1299                                                  port->port_speed);
1300         port->cfg->err_fqid =
1301                 port_params->specific_params.non_rx_params.err_fqid;
1302         port->cfg->deq_sp =
1303                 (u8)(dts_params->qman_channel_id & QMI_DEQ_CFG_SUBPORTAL_MASK);
1304         port->cfg->dflt_fqid =
1305                 port_params->specific_params.non_rx_params.dflt_fqid;
1306         port->cfg->deq_high_priority = true;
1307 }
1308 
1309 /**
1310  * fman_port_config
1311  * @port:       Pointer to the port structure
1312  * @params:     Pointer to data structure of parameters
1313  *
1314  * Creates a descriptor for the FM PORT module.
1315  * The routine returns a pointer to the FM PORT object.
1316  * This descriptor must be passed as first parameter to all other FM PORT
1317  * function calls.
1318  * No actual initialization or configuration of FM hardware is done by this
1319  * routine.
1320  *
1321  * Return: 0 on success; Error code otherwise.
1322  */
1323 int fman_port_config(struct fman_port *port, struct fman_port_params *params)
1324 {
1325         void __iomem *base_addr = port->dts_params.base_addr;
1326         int err;
1327 
1328         /* Allocate the FM driver's parameters structure */
1329         port->cfg = kzalloc(sizeof(*port->cfg), GFP_KERNEL);
1330         if (!port->cfg)
1331                 return -EINVAL;
1332 
1333         /* Initialize FM port parameters which will be kept by the driver */
1334         port->port_type = port->dts_params.type;
1335         port->port_speed = port->dts_params.speed;
1336         port->port_id = port->dts_params.id;
1337         port->fm = port->dts_params.fman;
1338         port->ext_pools_num = (u8)8;
1339 
1340         /* get FM revision */
1341         fman_get_revision(port->fm, &port->rev_info);
1342 
1343         err = fill_soc_specific_params(port);
1344         if (err)
1345                 goto err_port_cfg;
1346 
1347         switch (port->port_type) {
1348         case FMAN_PORT_TYPE_RX:
1349                 set_rx_dflt_cfg(port, params);
1350                 /* fall through */
1351         case FMAN_PORT_TYPE_TX:
1352                 set_tx_dflt_cfg(port, params, &port->dts_params);
1353                 /* fall through */
1354         default:
1355                 set_dflt_cfg(port, params);
1356         }
1357 
1358         /* Continue with other parameters */
1359         /* set memory map pointers */
1360         port->bmi_regs = base_addr + BMI_PORT_REGS_OFFSET;
1361         port->qmi_regs = base_addr + QMI_PORT_REGS_OFFSET;
1362         port->hwp_regs = base_addr + HWP_PORT_REGS_OFFSET;
1363 
1364         port->max_frame_length = DFLT_PORT_MAX_FRAME_LENGTH;
1365         /* resource distribution. */
1366 
1367         port->fifo_bufs.num =
1368         get_dflt_num_of_fifo_bufs(port->rev_info.major, port->port_type,
1369                                   port->port_speed) * FMAN_BMI_FIFO_UNITS;
1370         port->fifo_bufs.extra =
1371         DFLT_PORT_EXTRA_NUM_OF_FIFO_BUFS * FMAN_BMI_FIFO_UNITS;
1372 
1373         port->open_dmas.num =
1374         get_dflt_num_of_open_dmas(port->rev_info.major,
1375                                   port->port_type, port->port_speed);
1376         port->open_dmas.extra =
1377         get_dflt_extra_num_of_open_dmas(port->rev_info.major,
1378                                         port->port_type, port->port_speed);
1379         port->tasks.num =
1380         get_dflt_num_of_tasks(port->rev_info.major,
1381                               port->port_type, port->port_speed);
1382         port->tasks.extra =
1383         get_dflt_extra_num_of_tasks(port->rev_info.major,
1384                                     port->port_type, port->port_speed);
1385 
1386         /* FM_HEAVY_TRAFFIC_SEQUENCER_HANG_ERRATA_FMAN_A006981 errata
1387          * workaround
1388          */
1389         if ((port->rev_info.major == 6) && (port->rev_info.minor == 0) &&
1390             (((port->port_type == FMAN_PORT_TYPE_TX) &&
1391             (port->port_speed == 1000)))) {
1392                 port->open_dmas.num = 16;
1393                 port->open_dmas.extra = 0;
1394         }
1395 
1396         if (port->rev_info.major >= 6 &&
1397             port->port_type == FMAN_PORT_TYPE_TX &&
1398             port->port_speed == 1000) {
1399                 /* FM_WRONG_RESET_VALUES_ERRATA_FMAN_A005127 Errata
1400                  * workaround
1401                  */
1402                 u32 reg;
1403 
1404                 reg = 0x00001013;
1405                 iowrite32be(reg, &port->bmi_regs->tx.fmbm_tfp);
1406         }
1407 
1408         return 0;
1409 
1410 err_port_cfg:
1411         kfree(port->cfg);
1412         return -EINVAL;
1413 }
1414 EXPORT_SYMBOL(fman_port_config);
1415 
1416 /**
1417  * fman_port_use_kg_hash
1418  * port:        A pointer to a FM Port module.
1419  * Sets the HW KeyGen or the BMI as HW Parser next engine, enabling
1420  * or bypassing the KeyGen hashing of Rx traffic
1421  */
1422 void fman_port_use_kg_hash(struct fman_port *port, bool enable)
1423 {
1424         if (enable)
1425                 /* After the Parser frames go to KeyGen */
1426                 iowrite32be(NIA_ENG_HWK, &port->bmi_regs->rx.fmbm_rfpne);
1427         else
1428                 /* After the Parser frames go to BMI */
1429                 iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME,
1430                             &port->bmi_regs->rx.fmbm_rfpne);
1431 }
1432 EXPORT_SYMBOL(fman_port_use_kg_hash);
1433 
1434 /**
1435  * fman_port_init
1436  * port:        A pointer to a FM Port module.
1437  * Initializes the FM PORT module by defining the software structure and
1438  * configuring the hardware registers.
1439  *
1440  * Return: 0 on success; Error code otherwise.
1441  */
1442 int fman_port_init(struct fman_port *port)
1443 {
1444         struct fman_port_init_params params;
1445         struct fman_keygen *keygen;
1446         struct fman_port_cfg *cfg;
1447         int err;
1448 
1449         if (is_init_done(port->cfg))
1450                 return -EINVAL;
1451 
1452         err = fman_sp_build_buffer_struct(&port->cfg->int_context,
1453                                           &port->cfg->buffer_prefix_content,
1454                                           &port->cfg->buf_margins,
1455                                           &port->buffer_offsets,
1456                                           &port->internal_buf_offset);
1457         if (err)
1458                 return err;
1459 
1460         cfg = port->cfg;
1461 
1462         if (port->port_type == FMAN_PORT_TYPE_RX) {
1463                 /* Call the external Buffer routine which also checks fifo
1464                  * size and updates it if necessary
1465                  */
1466                 /* define external buffer pools and pool depletion */
1467                 err = set_ext_buffer_pools(port);
1468                 if (err)
1469                         return err;
1470                 /* check if the largest external buffer pool is large enough */
1471                 if (cfg->buf_margins.start_margins + MIN_EXT_BUF_SIZE +
1472                     cfg->buf_margins.end_margins >
1473                     port->rx_pools_params.largest_buf_size) {
1474                         dev_err(port->dev, "%s: buf_margins.start_margins (%d) + minimum buf size (64) + buf_margins.end_margins (%d) is larger than maximum external buffer size (%d)\n",
1475                                 __func__, cfg->buf_margins.start_margins,
1476                                 cfg->buf_margins.end_margins,
1477                                 port->rx_pools_params.largest_buf_size);
1478                         return -EINVAL;
1479                 }
1480         }
1481 
1482         /* Call FM module routine for communicating parameters */
1483         memset(&params, 0, sizeof(params));
1484         params.port_id = port->port_id;
1485         params.port_type = port->port_type;
1486         params.port_speed = port->port_speed;
1487         params.num_of_tasks = (u8)port->tasks.num;
1488         params.num_of_extra_tasks = (u8)port->tasks.extra;
1489         params.num_of_open_dmas = (u8)port->open_dmas.num;
1490         params.num_of_extra_open_dmas = (u8)port->open_dmas.extra;
1491 
1492         if (port->fifo_bufs.num) {
1493                 err = verify_size_of_fifo(port);
1494                 if (err)
1495                         return err;
1496         }
1497         params.size_of_fifo = port->fifo_bufs.num;
1498         params.extra_size_of_fifo = port->fifo_bufs.extra;
1499         params.deq_pipeline_depth = port->cfg->tx_fifo_deq_pipeline_depth;
1500         params.max_frame_length = port->max_frame_length;
1501 
1502         err = fman_set_port_params(port->fm, &params);
1503         if (err)
1504                 return err;
1505 
1506         err = init_low_level_driver(port);
1507         if (err)
1508                 return err;
1509 
1510         if (port->cfg->pcd_fqs_count) {
1511                 keygen = port->dts_params.fman->keygen;
1512                 err = keygen_port_hashing_init(keygen, port->port_id,
1513                                                port->cfg->pcd_base_fqid,
1514                                                port->cfg->pcd_fqs_count);
1515                 if (err)
1516                         return err;
1517 
1518                 fman_port_use_kg_hash(port, true);
1519         }
1520 
1521         kfree(port->cfg);
1522         port->cfg = NULL;
1523 
1524         return 0;
1525 }
1526 EXPORT_SYMBOL(fman_port_init);
1527 
1528 /**
1529  * fman_port_cfg_buf_prefix_content
1530  * @port                        A pointer to a FM Port module.
1531  * @buffer_prefix_content       A structure of parameters describing
1532  *                              the structure of the buffer.
1533  *                              Out parameter:
1534  *                              Start margin - offset of data from
1535  *                              start of external buffer.
1536  * Defines the structure, size and content of the application buffer.
1537  * The prefix, in Tx ports, if 'pass_prs_result', the application should set
1538  * a value to their offsets in the prefix of the FM will save the first
1539  * 'priv_data_size', than, depending on 'pass_prs_result' and
1540  * 'pass_time_stamp', copy parse result and timeStamp, and the packet itself
1541  * (in this order), to the application buffer, and to offset.
1542  * Calling this routine changes the buffer margins definitions in the internal
1543  * driver data base from its default configuration:
1544  * Data size:  [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PRIV_DATA_SIZE]
1545  * Pass Parser result: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PASS_PRS_RESULT].
1546  * Pass timestamp: [DEFAULT_PORT_BUFFER_PREFIX_CONTENT_PASS_TIME_STAMP].
1547  * May be used for all ports
1548  *
1549  * Allowed only following fman_port_config() and before fman_port_init().
1550  *
1551  * Return: 0 on success; Error code otherwise.
1552  */
1553 int fman_port_cfg_buf_prefix_content(struct fman_port *port,
1554                                      struct fman_buffer_prefix_content *
1555                                      buffer_prefix_content)
1556 {
1557         if (is_init_done(port->cfg))
1558                 return -EINVAL;
1559 
1560         memcpy(&port->cfg->buffer_prefix_content,
1561                buffer_prefix_content,
1562                sizeof(struct fman_buffer_prefix_content));
1563         /* if data_align was not initialized by user,
1564          * we return to driver's default
1565          */
1566         if (!port->cfg->buffer_prefix_content.data_align)
1567                 port->cfg->buffer_prefix_content.data_align =
1568                 DFLT_PORT_BUFFER_PREFIX_CONTEXT_DATA_ALIGN;
1569 
1570         return 0;
1571 }
1572 EXPORT_SYMBOL(fman_port_cfg_buf_prefix_content);
1573 
1574 /**
1575  * fman_port_disable
1576  * port:        A pointer to a FM Port module.
1577  *
1578  * Gracefully disable an FM port. The port will not start new   tasks after all
1579  * tasks associated with the port are terminated.
1580  *
1581  * This is a blocking routine, it returns after port is gracefully stopped,
1582  * i.e. the port will not except new frames, but it will finish all frames
1583  * or tasks which were already began.
1584  * Allowed only following fman_port_init().
1585  *
1586  * Return: 0 on success; Error code otherwise.
1587  */
1588 int fman_port_disable(struct fman_port *port)
1589 {
1590         u32 __iomem *bmi_cfg_reg, *bmi_status_reg;
1591         u32 tmp;
1592         bool rx_port, failure = false;
1593         int count;
1594 
1595         if (!is_init_done(port->cfg))
1596                 return -EINVAL;
1597 
1598         switch (port->port_type) {
1599         case FMAN_PORT_TYPE_RX:
1600                 bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg;
1601                 bmi_status_reg = &port->bmi_regs->rx.fmbm_rst;
1602                 rx_port = true;
1603                 break;
1604         case FMAN_PORT_TYPE_TX:
1605                 bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg;
1606                 bmi_status_reg = &port->bmi_regs->tx.fmbm_tst;
1607                 rx_port = false;
1608                 break;
1609         default:
1610                 return -EINVAL;
1611         }
1612 
1613         /* Disable QMI */
1614         if (!rx_port) {
1615                 tmp = ioread32be(&port->qmi_regs->fmqm_pnc) & ~QMI_PORT_CFG_EN;
1616                 iowrite32be(tmp, &port->qmi_regs->fmqm_pnc);
1617 
1618                 /* Wait for QMI to finish FD handling */
1619                 count = 100;
1620                 do {
1621                         udelay(10);
1622                         tmp = ioread32be(&port->qmi_regs->fmqm_pns);
1623                 } while ((tmp & QMI_PORT_STATUS_DEQ_FD_BSY) && --count);
1624 
1625                 if (count == 0) {
1626                         /* Timeout */
1627                         failure = true;
1628                 }
1629         }
1630 
1631         /* Disable BMI */
1632         tmp = ioread32be(bmi_cfg_reg) & ~BMI_PORT_CFG_EN;
1633         iowrite32be(tmp, bmi_cfg_reg);
1634 
1635         /* Wait for graceful stop end */
1636         count = 500;
1637         do {
1638                 udelay(10);
1639                 tmp = ioread32be(bmi_status_reg);
1640         } while ((tmp & BMI_PORT_STATUS_BSY) && --count);
1641 
1642         if (count == 0) {
1643                 /* Timeout */
1644                 failure = true;
1645         }
1646 
1647         if (failure)
1648                 dev_dbg(port->dev, "%s: FMan Port[%d]: BMI or QMI is Busy. Port forced down\n",
1649                         __func__,  port->port_id);
1650 
1651         return 0;
1652 }
1653 EXPORT_SYMBOL(fman_port_disable);
1654 
1655 /**
1656  * fman_port_enable
1657  * port:        A pointer to a FM Port module.
1658  *
1659  * A runtime routine provided to allow disable/enable of port.
1660  *
1661  * Allowed only following fman_port_init().
1662  *
1663  * Return: 0 on success; Error code otherwise.
1664  */
1665 int fman_port_enable(struct fman_port *port)
1666 {
1667         u32 __iomem *bmi_cfg_reg;
1668         u32 tmp;
1669         bool rx_port;
1670 
1671         if (!is_init_done(port->cfg))
1672                 return -EINVAL;
1673 
1674         switch (port->port_type) {
1675         case FMAN_PORT_TYPE_RX:
1676                 bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg;
1677                 rx_port = true;
1678                 break;
1679         case FMAN_PORT_TYPE_TX:
1680                 bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg;
1681                 rx_port = false;
1682                 break;
1683         default:
1684                 return -EINVAL;
1685         }
1686 
1687         /* Enable QMI */
1688         if (!rx_port) {
1689                 tmp = ioread32be(&port->qmi_regs->fmqm_pnc) | QMI_PORT_CFG_EN;
1690                 iowrite32be(tmp, &port->qmi_regs->fmqm_pnc);
1691         }
1692 
1693         /* Enable BMI */
1694         tmp = ioread32be(bmi_cfg_reg) | BMI_PORT_CFG_EN;
1695         iowrite32be(tmp, bmi_cfg_reg);
1696 
1697         return 0;
1698 }
1699 EXPORT_SYMBOL(fman_port_enable);
1700 
1701 /**
1702  * fman_port_bind
1703  * dev:         FMan Port OF device pointer
1704  *
1705  * Bind to a specific FMan Port.
1706  *
1707  * Allowed only after the port was created.
1708  *
1709  * Return: A pointer to the FMan port device.
1710  */
1711 struct fman_port *fman_port_bind(struct device *dev)
1712 {
1713         return (struct fman_port *)(dev_get_drvdata(get_device(dev)));
1714 }
1715 EXPORT_SYMBOL(fman_port_bind);
1716 
1717 /**
1718  * fman_port_get_qman_channel_id
1719  * port:        Pointer to the FMan port devuce
1720  *
1721  * Get the QMan channel ID for the specific port
1722  *
1723  * Return: QMan channel ID
1724  */
1725 u32 fman_port_get_qman_channel_id(struct fman_port *port)
1726 {
1727         return port->dts_params.qman_channel_id;
1728 }
1729 EXPORT_SYMBOL(fman_port_get_qman_channel_id);
1730 
1731 int fman_port_get_hash_result_offset(struct fman_port *port, u32 *offset)
1732 {
1733         if (port->buffer_offsets.hash_result_offset == ILLEGAL_BASE)
1734                 return -EINVAL;
1735 
1736         *offset = port->buffer_offsets.hash_result_offset;
1737 
1738         return 0;
1739 }
1740 EXPORT_SYMBOL(fman_port_get_hash_result_offset);
1741 
1742 int fman_port_get_tstamp(struct fman_port *port, const void *data, u64 *tstamp)
1743 {
1744         if (port->buffer_offsets.time_stamp_offset == ILLEGAL_BASE)
1745                 return -EINVAL;
1746 
1747         *tstamp = be64_to_cpu(*(__be64 *)(data +
1748                         port->buffer_offsets.time_stamp_offset));
1749 
1750         return 0;
1751 }
1752 EXPORT_SYMBOL(fman_port_get_tstamp);
1753 
1754 static int fman_port_probe(struct platform_device *of_dev)
1755 {
1756         struct fman_port *port;
1757         struct fman *fman;
1758         struct device_node *fm_node, *port_node;
1759         struct resource res;
1760         struct resource *dev_res;
1761         u32 val;
1762         int err = 0, lenp;
1763         enum fman_port_type port_type;
1764         u16 port_speed;
1765         u8 port_id;
1766 
1767         port = kzalloc(sizeof(*port), GFP_KERNEL);
1768         if (!port)
1769                 return -ENOMEM;
1770 
1771         port->dev = &of_dev->dev;
1772 
1773         port_node = of_node_get(of_dev->dev.of_node);
1774 
1775         /* Get the FM node */
1776         fm_node = of_get_parent(port_node);
1777         if (!fm_node) {
1778                 dev_err(port->dev, "%s: of_get_parent() failed\n", __func__);
1779                 err = -ENODEV;
1780                 goto return_err;
1781         }
1782 
1783         fman = dev_get_drvdata(&of_find_device_by_node(fm_node)->dev);
1784         of_node_put(fm_node);
1785         if (!fman) {
1786                 err = -EINVAL;
1787                 goto return_err;
1788         }
1789 
1790         err = of_property_read_u32(port_node, "cell-index", &val);
1791         if (err) {
1792                 dev_err(port->dev, "%s: reading cell-index for %pOF failed\n",
1793                         __func__, port_node);
1794                 err = -EINVAL;
1795                 goto return_err;
1796         }
1797         port_id = (u8)val;
1798         port->dts_params.id = port_id;
1799 
1800         if (of_device_is_compatible(port_node, "fsl,fman-v3-port-tx")) {
1801                 port_type = FMAN_PORT_TYPE_TX;
1802                 port_speed = 1000;
1803                 if (of_find_property(port_node, "fsl,fman-10g-port", &lenp))
1804                         port_speed = 10000;
1805 
1806         } else if (of_device_is_compatible(port_node, "fsl,fman-v2-port-tx")) {
1807                 if (port_id >= TX_10G_PORT_BASE)
1808                         port_speed = 10000;
1809                 else
1810                         port_speed = 1000;
1811                 port_type = FMAN_PORT_TYPE_TX;
1812 
1813         } else if (of_device_is_compatible(port_node, "fsl,fman-v3-port-rx")) {
1814                 port_type = FMAN_PORT_TYPE_RX;
1815                 port_speed = 1000;
1816                 if (of_find_property(port_node, "fsl,fman-10g-port", &lenp))
1817                         port_speed = 10000;
1818 
1819         } else if (of_device_is_compatible(port_node, "fsl,fman-v2-port-rx")) {
1820                 if (port_id >= RX_10G_PORT_BASE)
1821                         port_speed = 10000;
1822                 else
1823                         port_speed = 1000;
1824                 port_type = FMAN_PORT_TYPE_RX;
1825 
1826         }  else {
1827                 dev_err(port->dev, "%s: Illegal port type\n", __func__);
1828                 err = -EINVAL;
1829                 goto return_err;
1830         }
1831 
1832         port->dts_params.type = port_type;
1833         port->dts_params.speed = port_speed;
1834 
1835         if (port_type == FMAN_PORT_TYPE_TX) {
1836                 u32 qman_channel_id;
1837 
1838                 qman_channel_id = fman_get_qman_channel_id(fman, port_id);
1839                 if (qman_channel_id == 0) {
1840                         dev_err(port->dev, "%s: incorrect qman-channel-id\n",
1841                                 __func__);
1842                         err = -EINVAL;
1843                         goto return_err;
1844                 }
1845                 port->dts_params.qman_channel_id = qman_channel_id;
1846         }
1847 
1848         err = of_address_to_resource(port_node, 0, &res);
1849         if (err < 0) {
1850                 dev_err(port->dev, "%s: of_address_to_resource() failed\n",
1851                         __func__);
1852                 err = -ENOMEM;
1853                 goto return_err;
1854         }
1855 
1856         port->dts_params.fman = fman;
1857 
1858         of_node_put(port_node);
1859 
1860         dev_res = __devm_request_region(port->dev, &res, res.start,
1861                                         resource_size(&res), "fman-port");
1862         if (!dev_res) {
1863                 dev_err(port->dev, "%s: __devm_request_region() failed\n",
1864                         __func__);
1865                 err = -EINVAL;
1866                 goto free_port;
1867         }
1868 
1869         port->dts_params.base_addr = devm_ioremap(port->dev, res.start,
1870                                                   resource_size(&res));
1871         if (!port->dts_params.base_addr)
1872                 dev_err(port->dev, "%s: devm_ioremap() failed\n", __func__);
1873 
1874         dev_set_drvdata(&of_dev->dev, port);
1875 
1876         return 0;
1877 
1878 return_err:
1879         of_node_put(port_node);
1880 free_port:
1881         kfree(port);
1882         return err;
1883 }
1884 
1885 static const struct of_device_id fman_port_match[] = {
1886         {.compatible = "fsl,fman-v3-port-rx"},
1887         {.compatible = "fsl,fman-v2-port-rx"},
1888         {.compatible = "fsl,fman-v3-port-tx"},
1889         {.compatible = "fsl,fman-v2-port-tx"},
1890         {}
1891 };
1892 
1893 MODULE_DEVICE_TABLE(of, fman_port_match);
1894 
1895 static struct platform_driver fman_port_driver = {
1896         .driver = {
1897                 .name = "fsl-fman-port",
1898                 .of_match_table = fman_port_match,
1899         },
1900         .probe = fman_port_probe,
1901 };
1902 
1903 static int __init fman_port_load(void)
1904 {
1905         int err;
1906 
1907         pr_debug("FSL DPAA FMan driver\n");
1908 
1909         err = platform_driver_register(&fman_port_driver);
1910         if (err < 0)
1911                 pr_err("Error, platform_driver_register() = %d\n", err);
1912 
1913         return err;
1914 }
1915 module_init(fman_port_load);
1916 
1917 static void __exit fman_port_unload(void)
1918 {
1919         platform_driver_unregister(&fman_port_driver);
1920 }
1921 module_exit(fman_port_unload);
1922 
1923 MODULE_LICENSE("Dual BSD/GPL");
1924 MODULE_DESCRIPTION("Freescale DPAA Frame Manager Port driver");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/freescale/fman/fman_port.c

DEFINITIONS
