drivers/net/ethernet/freescale/fman/fman.c

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This source file includes following definitions.
fman_exceptions
fman_bus_error
call_mac_isr
hw_port_id_to_sw_port_id
set_port_order_restoration
set_port_liodn
enable_rams_ecc
disable_rams_ecc
fman_defconfig
dma_init
fpm_init
bmi_init
qmi_init
hwp_init
enable
set_exception
resume
fill_soc_specific_params
is_init_done
free_init_resources
bmi_err_event
qmi_err_event
dma_err_event
fpm_err_event
muram_err_intr
qmi_event
enable_time_stamp
clear_iram
get_exception_flag
get_module_event
set_size_of_fifo
set_num_of_tasks
set_num_of_open_dmas
fman_config
fman_reset
fman_init
fman_set_exception
fman_register_intr
fman_unregister_intr
fman_set_port_params
fman_reset_mac
fman_set_mac_max_frame
fman_get_clock_freq
fman_get_bmi_max_fifo_size
fman_get_revision
fman_get_qman_channel_id
fman_get_mem_region
fman_get_max_frm
fman_get_rx_extra_headroom
fman_bind
fman_has_errata_a050385
fman_err_irq
fman_irq
read_dts_node
fman_probe
fman_load
fman_unload
   1 /*
   2  * Copyright 2008-2015 Freescale Semiconductor Inc.
   3  * Copyright 2020 NXP
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of Freescale Semiconductor nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  *
  17  * ALTERNATIVELY, this software may be distributed under the terms of the
  18  * GNU General Public License ("GPL") as published by the Free Software
  19  * Foundation, either version 2 of that License or (at your option) any
  20  * later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  23  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  26  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  31  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33 
  34 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  35 
  36 #include <linux/fsl/guts.h>
  37 #include <linux/slab.h>
  38 #include <linux/delay.h>
  39 #include <linux/module.h>
  40 #include <linux/of_platform.h>
  41 #include <linux/clk.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_irq.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/libfdt_env.h>
  46 
  47 #include "fman.h"
  48 #include "fman_muram.h"
  49 #include "fman_keygen.h"
  50 
  51 /* General defines */
  52 #define FMAN_LIODN_TBL                  64      /* size of LIODN table */
  53 #define MAX_NUM_OF_MACS                 10
  54 #define FM_NUM_OF_FMAN_CTRL_EVENT_REGS  4
  55 #define BASE_RX_PORTID                  0x08
  56 #define BASE_TX_PORTID                  0x28
  57 
  58 /* Modules registers offsets */
  59 #define BMI_OFFSET              0x00080000
  60 #define QMI_OFFSET              0x00080400
  61 #define KG_OFFSET               0x000C1000
  62 #define DMA_OFFSET              0x000C2000
  63 #define FPM_OFFSET              0x000C3000
  64 #define IMEM_OFFSET             0x000C4000
  65 #define HWP_OFFSET              0x000C7000
  66 #define CGP_OFFSET              0x000DB000
  67 
  68 /* Exceptions bit map */
  69 #define EX_DMA_BUS_ERROR                0x80000000
  70 #define EX_DMA_READ_ECC                 0x40000000
  71 #define EX_DMA_SYSTEM_WRITE_ECC 0x20000000
  72 #define EX_DMA_FM_WRITE_ECC             0x10000000
  73 #define EX_FPM_STALL_ON_TASKS           0x08000000
  74 #define EX_FPM_SINGLE_ECC               0x04000000
  75 #define EX_FPM_DOUBLE_ECC               0x02000000
  76 #define EX_QMI_SINGLE_ECC               0x01000000
  77 #define EX_QMI_DEQ_FROM_UNKNOWN_PORTID  0x00800000
  78 #define EX_QMI_DOUBLE_ECC               0x00400000
  79 #define EX_BMI_LIST_RAM_ECC             0x00200000
  80 #define EX_BMI_STORAGE_PROFILE_ECC      0x00100000
  81 #define EX_BMI_STATISTICS_RAM_ECC       0x00080000
  82 #define EX_IRAM_ECC                     0x00040000
  83 #define EX_MURAM_ECC                    0x00020000
  84 #define EX_BMI_DISPATCH_RAM_ECC 0x00010000
  85 #define EX_DMA_SINGLE_PORT_ECC          0x00008000
  86 
  87 /* DMA defines */
  88 /* masks */
  89 #define DMA_MODE_BER                    0x00200000
  90 #define DMA_MODE_ECC                    0x00000020
  91 #define DMA_MODE_SECURE_PROT            0x00000800
  92 #define DMA_MODE_AXI_DBG_MASK           0x0F000000
  93 
  94 #define DMA_TRANSFER_PORTID_MASK        0xFF000000
  95 #define DMA_TRANSFER_TNUM_MASK          0x00FF0000
  96 #define DMA_TRANSFER_LIODN_MASK 0x00000FFF
  97 
  98 #define DMA_STATUS_BUS_ERR              0x08000000
  99 #define DMA_STATUS_READ_ECC             0x04000000
 100 #define DMA_STATUS_SYSTEM_WRITE_ECC     0x02000000
 101 #define DMA_STATUS_FM_WRITE_ECC 0x01000000
 102 #define DMA_STATUS_FM_SPDAT_ECC 0x00080000
 103 
 104 #define DMA_MODE_CACHE_OR_SHIFT         30
 105 #define DMA_MODE_AXI_DBG_SHIFT                  24
 106 #define DMA_MODE_CEN_SHIFT                      13
 107 #define DMA_MODE_CEN_MASK                       0x00000007
 108 #define DMA_MODE_DBG_SHIFT                      7
 109 #define DMA_MODE_AID_MODE_SHIFT         4
 110 
 111 #define DMA_THRESH_COMMQ_SHIFT                  24
 112 #define DMA_THRESH_READ_INT_BUF_SHIFT           16
 113 #define DMA_THRESH_READ_INT_BUF_MASK            0x0000003f
 114 #define DMA_THRESH_WRITE_INT_BUF_MASK           0x0000003f
 115 
 116 #define DMA_TRANSFER_PORTID_SHIFT               24
 117 #define DMA_TRANSFER_TNUM_SHIFT         16
 118 
 119 #define DMA_CAM_SIZEOF_ENTRY                    0x40
 120 #define DMA_CAM_UNITS                           8
 121 
 122 #define DMA_LIODN_SHIFT         16
 123 #define DMA_LIODN_BASE_MASK     0x00000FFF
 124 
 125 /* FPM defines */
 126 #define FPM_EV_MASK_DOUBLE_ECC          0x80000000
 127 #define FPM_EV_MASK_STALL               0x40000000
 128 #define FPM_EV_MASK_SINGLE_ECC          0x20000000
 129 #define FPM_EV_MASK_RELEASE_FM          0x00010000
 130 #define FPM_EV_MASK_DOUBLE_ECC_EN       0x00008000
 131 #define FPM_EV_MASK_STALL_EN            0x00004000
 132 #define FPM_EV_MASK_SINGLE_ECC_EN       0x00002000
 133 #define FPM_EV_MASK_EXTERNAL_HALT       0x00000008
 134 #define FPM_EV_MASK_ECC_ERR_HALT        0x00000004
 135 
 136 #define FPM_RAM_MURAM_ECC               0x00008000
 137 #define FPM_RAM_IRAM_ECC                0x00004000
 138 #define FPM_IRAM_ECC_ERR_EX_EN          0x00020000
 139 #define FPM_MURAM_ECC_ERR_EX_EN 0x00040000
 140 #define FPM_RAM_IRAM_ECC_EN             0x40000000
 141 #define FPM_RAM_RAMS_ECC_EN             0x80000000
 142 #define FPM_RAM_RAMS_ECC_EN_SRC_SEL     0x08000000
 143 
 144 #define FPM_REV1_MAJOR_MASK             0x0000FF00
 145 #define FPM_REV1_MINOR_MASK             0x000000FF
 146 
 147 #define FPM_DISP_LIMIT_SHIFT            24
 148 
 149 #define FPM_PRT_FM_CTL1                 0x00000001
 150 #define FPM_PRT_FM_CTL2                 0x00000002
 151 #define FPM_PORT_FM_CTL_PORTID_SHIFT    24
 152 #define FPM_PRC_ORA_FM_CTL_SEL_SHIFT    16
 153 
 154 #define FPM_THR1_PRS_SHIFT              24
 155 #define FPM_THR1_KG_SHIFT               16
 156 #define FPM_THR1_PLCR_SHIFT             8
 157 #define FPM_THR1_BMI_SHIFT              0
 158 
 159 #define FPM_THR2_QMI_ENQ_SHIFT          24
 160 #define FPM_THR2_QMI_DEQ_SHIFT          0
 161 #define FPM_THR2_FM_CTL1_SHIFT          16
 162 #define FPM_THR2_FM_CTL2_SHIFT          8
 163 
 164 #define FPM_EV_MASK_CAT_ERR_SHIFT       1
 165 #define FPM_EV_MASK_DMA_ERR_SHIFT       0
 166 
 167 #define FPM_REV1_MAJOR_SHIFT            8
 168 
 169 #define FPM_RSTC_FM_RESET               0x80000000
 170 #define FPM_RSTC_MAC0_RESET             0x40000000
 171 #define FPM_RSTC_MAC1_RESET             0x20000000
 172 #define FPM_RSTC_MAC2_RESET             0x10000000
 173 #define FPM_RSTC_MAC3_RESET             0x08000000
 174 #define FPM_RSTC_MAC8_RESET             0x04000000
 175 #define FPM_RSTC_MAC4_RESET             0x02000000
 176 #define FPM_RSTC_MAC5_RESET             0x01000000
 177 #define FPM_RSTC_MAC6_RESET             0x00800000
 178 #define FPM_RSTC_MAC7_RESET             0x00400000
 179 #define FPM_RSTC_MAC9_RESET             0x00200000
 180 
 181 #define FPM_TS_INT_SHIFT                16
 182 #define FPM_TS_CTL_EN                   0x80000000
 183 
 184 /* BMI defines */
 185 #define BMI_INIT_START                          0x80000000
 186 #define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC     0x80000000
 187 #define BMI_ERR_INTR_EN_LIST_RAM_ECC            0x40000000
 188 #define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC      0x20000000
 189 #define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC        0x10000000
 190 #define BMI_NUM_OF_TASKS_MASK                   0x3F000000
 191 #define BMI_NUM_OF_EXTRA_TASKS_MASK             0x000F0000
 192 #define BMI_NUM_OF_DMAS_MASK                    0x00000F00
 193 #define BMI_NUM_OF_EXTRA_DMAS_MASK              0x0000000F
 194 #define BMI_FIFO_SIZE_MASK                      0x000003FF
 195 #define BMI_EXTRA_FIFO_SIZE_MASK                0x03FF0000
 196 #define BMI_CFG2_DMAS_MASK                      0x0000003F
 197 #define BMI_CFG2_TASKS_MASK                     0x0000003F
 198 
 199 #define BMI_CFG2_TASKS_SHIFT            16
 200 #define BMI_CFG2_DMAS_SHIFT             0
 201 #define BMI_CFG1_FIFO_SIZE_SHIFT        16
 202 #define BMI_NUM_OF_TASKS_SHIFT          24
 203 #define BMI_EXTRA_NUM_OF_TASKS_SHIFT    16
 204 #define BMI_NUM_OF_DMAS_SHIFT           8
 205 #define BMI_EXTRA_NUM_OF_DMAS_SHIFT     0
 206 
 207 #define BMI_FIFO_ALIGN                  0x100
 208 
 209 #define BMI_EXTRA_FIFO_SIZE_SHIFT       16
 210 
 211 /* QMI defines */
 212 #define QMI_CFG_ENQ_EN                  0x80000000
 213 #define QMI_CFG_DEQ_EN                  0x40000000
 214 #define QMI_CFG_EN_COUNTERS             0x10000000
 215 #define QMI_CFG_DEQ_MASK                0x0000003F
 216 #define QMI_CFG_ENQ_MASK                0x00003F00
 217 #define QMI_CFG_ENQ_SHIFT               8
 218 
 219 #define QMI_ERR_INTR_EN_DOUBLE_ECC      0x80000000
 220 #define QMI_ERR_INTR_EN_DEQ_FROM_DEF    0x40000000
 221 #define QMI_INTR_EN_SINGLE_ECC          0x80000000
 222 
 223 #define QMI_GS_HALT_NOT_BUSY            0x00000002
 224 
 225 /* HWP defines */
 226 #define HWP_RPIMAC_PEN                  0x00000001
 227 
 228 /* IRAM defines */
 229 #define IRAM_IADD_AIE                   0x80000000
 230 #define IRAM_READY                      0x80000000
 231 
 232 /* Default values */
 233 #define DEFAULT_CATASTROPHIC_ERR                0
 234 #define DEFAULT_DMA_ERR                         0
 235 #define DEFAULT_AID_MODE                        FMAN_DMA_AID_OUT_TNUM
 236 #define DEFAULT_DMA_COMM_Q_LOW                  0x2A
 237 #define DEFAULT_DMA_COMM_Q_HIGH         0x3F
 238 #define DEFAULT_CACHE_OVERRIDE                  0
 239 #define DEFAULT_DMA_CAM_NUM_OF_ENTRIES          64
 240 #define DEFAULT_DMA_DBG_CNT_MODE                0
 241 #define DEFAULT_DMA_SOS_EMERGENCY               0
 242 #define DEFAULT_DMA_WATCHDOG                    0
 243 #define DEFAULT_DISP_LIMIT                      0
 244 #define DEFAULT_PRS_DISP_TH                     16
 245 #define DEFAULT_PLCR_DISP_TH                    16
 246 #define DEFAULT_KG_DISP_TH                      16
 247 #define DEFAULT_BMI_DISP_TH                     16
 248 #define DEFAULT_QMI_ENQ_DISP_TH         16
 249 #define DEFAULT_QMI_DEQ_DISP_TH         16
 250 #define DEFAULT_FM_CTL1_DISP_TH         16
 251 #define DEFAULT_FM_CTL2_DISP_TH         16
 252 
 253 #define DFLT_AXI_DBG_NUM_OF_BEATS               1
 254 
 255 #define DFLT_DMA_READ_INT_BUF_LOW(dma_thresh_max_buf)   \
 256         ((dma_thresh_max_buf + 1) / 2)
 257 #define DFLT_DMA_READ_INT_BUF_HIGH(dma_thresh_max_buf)  \
 258         ((dma_thresh_max_buf + 1) * 3 / 4)
 259 #define DFLT_DMA_WRITE_INT_BUF_LOW(dma_thresh_max_buf)  \
 260         ((dma_thresh_max_buf + 1) / 2)
 261 #define DFLT_DMA_WRITE_INT_BUF_HIGH(dma_thresh_max_buf)\
 262         ((dma_thresh_max_buf + 1) * 3 / 4)
 263 
 264 #define DMA_COMM_Q_LOW_FMAN_V3          0x2A
 265 #define DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq)            \
 266         ((dma_thresh_max_commq + 1) / 2)
 267 #define DFLT_DMA_COMM_Q_LOW(major, dma_thresh_max_commq)        \
 268         ((major == 6) ? DMA_COMM_Q_LOW_FMAN_V3 :                \
 269         DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq))
 270 
 271 #define DMA_COMM_Q_HIGH_FMAN_V3 0x3f
 272 #define DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq)           \
 273         ((dma_thresh_max_commq + 1) * 3 / 4)
 274 #define DFLT_DMA_COMM_Q_HIGH(major, dma_thresh_max_commq)       \
 275         ((major == 6) ? DMA_COMM_Q_HIGH_FMAN_V3 :               \
 276         DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq))
 277 
 278 #define TOTAL_NUM_OF_TASKS_FMAN_V3L     59
 279 #define TOTAL_NUM_OF_TASKS_FMAN_V3H     124
 280 #define DFLT_TOTAL_NUM_OF_TASKS(major, minor, bmi_max_num_of_tasks)     \
 281         ((major == 6) ? ((minor == 1 || minor == 4) ?                   \
 282         TOTAL_NUM_OF_TASKS_FMAN_V3L : TOTAL_NUM_OF_TASKS_FMAN_V3H) :    \
 283         bmi_max_num_of_tasks)
 284 
 285 #define DMA_CAM_NUM_OF_ENTRIES_FMAN_V3          64
 286 #define DMA_CAM_NUM_OF_ENTRIES_FMAN_V2          32
 287 #define DFLT_DMA_CAM_NUM_OF_ENTRIES(major)                      \
 288         (major == 6 ? DMA_CAM_NUM_OF_ENTRIES_FMAN_V3 :          \
 289         DMA_CAM_NUM_OF_ENTRIES_FMAN_V2)
 290 
 291 #define FM_TIMESTAMP_1_USEC_BIT             8
 292 
 293 /* Defines used for enabling/disabling FMan interrupts */
 294 #define ERR_INTR_EN_DMA         0x00010000
 295 #define ERR_INTR_EN_FPM         0x80000000
 296 #define ERR_INTR_EN_BMI         0x00800000
 297 #define ERR_INTR_EN_QMI         0x00400000
 298 #define ERR_INTR_EN_MURAM       0x00040000
 299 #define ERR_INTR_EN_MAC0        0x00004000
 300 #define ERR_INTR_EN_MAC1        0x00002000
 301 #define ERR_INTR_EN_MAC2        0x00001000
 302 #define ERR_INTR_EN_MAC3        0x00000800
 303 #define ERR_INTR_EN_MAC4        0x00000400
 304 #define ERR_INTR_EN_MAC5        0x00000200
 305 #define ERR_INTR_EN_MAC6        0x00000100
 306 #define ERR_INTR_EN_MAC7        0x00000080
 307 #define ERR_INTR_EN_MAC8        0x00008000
 308 #define ERR_INTR_EN_MAC9        0x00000040
 309 
 310 #define INTR_EN_QMI             0x40000000
 311 #define INTR_EN_MAC0            0x00080000
 312 #define INTR_EN_MAC1            0x00040000
 313 #define INTR_EN_MAC2            0x00020000
 314 #define INTR_EN_MAC3            0x00010000
 315 #define INTR_EN_MAC4            0x00000040
 316 #define INTR_EN_MAC5            0x00000020
 317 #define INTR_EN_MAC6            0x00000008
 318 #define INTR_EN_MAC7            0x00000002
 319 #define INTR_EN_MAC8            0x00200000
 320 #define INTR_EN_MAC9            0x00100000
 321 #define INTR_EN_REV0            0x00008000
 322 #define INTR_EN_REV1            0x00004000
 323 #define INTR_EN_REV2            0x00002000
 324 #define INTR_EN_REV3            0x00001000
 325 #define INTR_EN_TMR             0x01000000
 326 
 327 enum fman_dma_aid_mode {
 328         FMAN_DMA_AID_OUT_PORT_ID = 0,             /* 4 LSB of PORT_ID */
 329         FMAN_DMA_AID_OUT_TNUM                     /* 4 LSB of TNUM */
 330 };
 331 
 332 struct fman_iram_regs {
 333         u32 iadd;       /* FM IRAM instruction address register */
 334         u32 idata;      /* FM IRAM instruction data register */
 335         u32 itcfg;      /* FM IRAM timing config register */
 336         u32 iready;     /* FM IRAM ready register */
 337 };
 338 
 339 struct fman_fpm_regs {
 340         u32 fmfp_tnc;           /* FPM TNUM Control 0x00 */
 341         u32 fmfp_prc;           /* FPM Port_ID FmCtl Association 0x04 */
 342         u32 fmfp_brkc;          /* FPM Breakpoint Control 0x08 */
 343         u32 fmfp_mxd;           /* FPM Flush Control 0x0c */
 344         u32 fmfp_dist1;         /* FPM Dispatch Thresholds1 0x10 */
 345         u32 fmfp_dist2;         /* FPM Dispatch Thresholds2 0x14 */
 346         u32 fm_epi;             /* FM Error Pending Interrupts 0x18 */
 347         u32 fm_rie;             /* FM Error Interrupt Enable 0x1c */
 348         u32 fmfp_fcev[4];       /* FPM FMan-Controller Event 1-4 0x20-0x2f */
 349         u32 res0030[4];         /* res 0x30 - 0x3f */
 350         u32 fmfp_cee[4];        /* PM FMan-Controller Event 1-4 0x40-0x4f */
 351         u32 res0050[4];         /* res 0x50-0x5f */
 352         u32 fmfp_tsc1;          /* FPM TimeStamp Control1 0x60 */
 353         u32 fmfp_tsc2;          /* FPM TimeStamp Control2 0x64 */
 354         u32 fmfp_tsp;           /* FPM Time Stamp 0x68 */
 355         u32 fmfp_tsf;           /* FPM Time Stamp Fraction 0x6c */
 356         u32 fm_rcr;             /* FM Rams Control 0x70 */
 357         u32 fmfp_extc;          /* FPM External Requests Control 0x74 */
 358         u32 fmfp_ext1;          /* FPM External Requests Config1 0x78 */
 359         u32 fmfp_ext2;          /* FPM External Requests Config2 0x7c */
 360         u32 fmfp_drd[16];       /* FPM Data_Ram Data 0-15 0x80 - 0xbf */
 361         u32 fmfp_dra;           /* FPM Data Ram Access 0xc0 */
 362         u32 fm_ip_rev_1;        /* FM IP Block Revision 1 0xc4 */
 363         u32 fm_ip_rev_2;        /* FM IP Block Revision 2 0xc8 */
 364         u32 fm_rstc;            /* FM Reset Command 0xcc */
 365         u32 fm_cld;             /* FM Classifier Debug 0xd0 */
 366         u32 fm_npi;             /* FM Normal Pending Interrupts 0xd4 */
 367         u32 fmfp_exte;          /* FPM External Requests Enable 0xd8 */
 368         u32 fmfp_ee;            /* FPM Event&Mask 0xdc */
 369         u32 fmfp_cev[4];        /* FPM CPU Event 1-4 0xe0-0xef */
 370         u32 res00f0[4];         /* res 0xf0-0xff */
 371         u32 fmfp_ps[50];        /* FPM Port Status 0x100-0x1c7 */
 372         u32 res01c8[14];        /* res 0x1c8-0x1ff */
 373         u32 fmfp_clfabc;        /* FPM CLFABC 0x200 */
 374         u32 fmfp_clfcc;         /* FPM CLFCC 0x204 */
 375         u32 fmfp_clfaval;       /* FPM CLFAVAL 0x208 */
 376         u32 fmfp_clfbval;       /* FPM CLFBVAL 0x20c */
 377         u32 fmfp_clfcval;       /* FPM CLFCVAL 0x210 */
 378         u32 fmfp_clfamsk;       /* FPM CLFAMSK 0x214 */
 379         u32 fmfp_clfbmsk;       /* FPM CLFBMSK 0x218 */
 380         u32 fmfp_clfcmsk;       /* FPM CLFCMSK 0x21c */
 381         u32 fmfp_clfamc;        /* FPM CLFAMC 0x220 */
 382         u32 fmfp_clfbmc;        /* FPM CLFBMC 0x224 */
 383         u32 fmfp_clfcmc;        /* FPM CLFCMC 0x228 */
 384         u32 fmfp_decceh;        /* FPM DECCEH 0x22c */
 385         u32 res0230[116];       /* res 0x230 - 0x3ff */
 386         u32 fmfp_ts[128];       /* 0x400: FPM Task Status 0x400 - 0x5ff */
 387         u32 res0600[0x400 - 384];
 388 };
 389 
 390 struct fman_bmi_regs {
 391         u32 fmbm_init;          /* BMI Initialization 0x00 */
 392         u32 fmbm_cfg1;          /* BMI Configuration 1 0x04 */
 393         u32 fmbm_cfg2;          /* BMI Configuration 2 0x08 */
 394         u32 res000c[5];         /* 0x0c - 0x1f */
 395         u32 fmbm_ievr;          /* Interrupt Event Register 0x20 */
 396         u32 fmbm_ier;           /* Interrupt Enable Register 0x24 */
 397         u32 fmbm_ifr;           /* Interrupt Force Register 0x28 */
 398         u32 res002c[5];         /* 0x2c - 0x3f */
 399         u32 fmbm_arb[8];        /* BMI Arbitration 0x40 - 0x5f */
 400         u32 res0060[12];        /* 0x60 - 0x8f */
 401         u32 fmbm_dtc[3];        /* Debug Trap Counter 0x90 - 0x9b */
 402         u32 res009c;            /* 0x9c */
 403         u32 fmbm_dcv[3][4];     /* Debug Compare val 0xa0-0xcf */
 404         u32 fmbm_dcm[3][4];     /* Debug Compare Mask 0xd0-0xff */
 405         u32 fmbm_gde;           /* BMI Global Debug Enable 0x100 */
 406         u32 fmbm_pp[63];        /* BMI Port Parameters 0x104 - 0x1ff */
 407         u32 res0200;            /* 0x200 */
 408         u32 fmbm_pfs[63];       /* BMI Port FIFO Size 0x204 - 0x2ff */
 409         u32 res0300;            /* 0x300 */
 410         u32 fmbm_spliodn[63];   /* Port Partition ID 0x304 - 0x3ff */
 411 };
 412 
 413 struct fman_qmi_regs {
 414         u32 fmqm_gc;            /* General Configuration Register 0x00 */
 415         u32 res0004;            /* 0x04 */
 416         u32 fmqm_eie;           /* Error Interrupt Event Register 0x08 */
 417         u32 fmqm_eien;          /* Error Interrupt Enable Register 0x0c */
 418         u32 fmqm_eif;           /* Error Interrupt Force Register 0x10 */
 419         u32 fmqm_ie;            /* Interrupt Event Register 0x14 */
 420         u32 fmqm_ien;           /* Interrupt Enable Register 0x18 */
 421         u32 fmqm_if;            /* Interrupt Force Register 0x1c */
 422         u32 fmqm_gs;            /* Global Status Register 0x20 */
 423         u32 fmqm_ts;            /* Task Status Register 0x24 */
 424         u32 fmqm_etfc;          /* Enqueue Total Frame Counter 0x28 */
 425         u32 fmqm_dtfc;          /* Dequeue Total Frame Counter 0x2c */
 426         u32 fmqm_dc0;           /* Dequeue Counter 0 0x30 */
 427         u32 fmqm_dc1;           /* Dequeue Counter 1 0x34 */
 428         u32 fmqm_dc2;           /* Dequeue Counter 2 0x38 */
 429         u32 fmqm_dc3;           /* Dequeue Counter 3 0x3c */
 430         u32 fmqm_dfdc;          /* Dequeue FQID from Default Counter 0x40 */
 431         u32 fmqm_dfcc;          /* Dequeue FQID from Context Counter 0x44 */
 432         u32 fmqm_dffc;          /* Dequeue FQID from FD Counter 0x48 */
 433         u32 fmqm_dcc;           /* Dequeue Confirm Counter 0x4c */
 434         u32 res0050[7];         /* 0x50 - 0x6b */
 435         u32 fmqm_tapc;          /* Tnum Aging Period Control 0x6c */
 436         u32 fmqm_dmcvc;         /* Dequeue MAC Command Valid Counter 0x70 */
 437         u32 fmqm_difdcc;        /* Dequeue Invalid FD Command Counter 0x74 */
 438         u32 fmqm_da1v;          /* Dequeue A1 Valid Counter 0x78 */
 439         u32 res007c;            /* 0x7c */
 440         u32 fmqm_dtc;           /* 0x80 Debug Trap Counter 0x80 */
 441         u32 fmqm_efddd;         /* 0x84 Enqueue Frame desc Dynamic dbg 0x84 */
 442         u32 res0088[2];         /* 0x88 - 0x8f */
 443         struct {
 444                 u32 fmqm_dtcfg1;        /* 0x90 dbg trap cfg 1 Register 0x00 */
 445                 u32 fmqm_dtval1;        /* Debug Trap Value 1 Register 0x04 */
 446                 u32 fmqm_dtm1;          /* Debug Trap Mask 1 Register 0x08 */
 447                 u32 fmqm_dtc1;          /* Debug Trap Counter 1 Register 0x0c */
 448                 u32 fmqm_dtcfg2;        /* dbg Trap cfg 2 Register 0x10 */
 449                 u32 fmqm_dtval2;        /* Debug Trap Value 2 Register 0x14 */
 450                 u32 fmqm_dtm2;          /* Debug Trap Mask 2 Register 0x18 */
 451                 u32 res001c;            /* 0x1c */
 452         } dbg_traps[3];                 /* 0x90 - 0xef */
 453         u8 res00f0[0x400 - 0xf0];       /* 0xf0 - 0x3ff */
 454 };
 455 
 456 struct fman_dma_regs {
 457         u32 fmdmsr;     /* FM DMA status register 0x00 */
 458         u32 fmdmmr;     /* FM DMA mode register 0x04 */
 459         u32 fmdmtr;     /* FM DMA bus threshold register 0x08 */
 460         u32 fmdmhy;     /* FM DMA bus hysteresis register 0x0c */
 461         u32 fmdmsetr;   /* FM DMA SOS emergency Threshold Register 0x10 */
 462         u32 fmdmtah;    /* FM DMA transfer bus address high reg 0x14 */
 463         u32 fmdmtal;    /* FM DMA transfer bus address low reg 0x18 */
 464         u32 fmdmtcid;   /* FM DMA transfer bus communication ID reg 0x1c */
 465         u32 fmdmra;     /* FM DMA bus internal ram address register 0x20 */
 466         u32 fmdmrd;     /* FM DMA bus internal ram data register 0x24 */
 467         u32 fmdmwcr;    /* FM DMA CAM watchdog counter value 0x28 */
 468         u32 fmdmebcr;   /* FM DMA CAM base in MURAM register 0x2c */
 469         u32 fmdmccqdr;  /* FM DMA CAM and CMD Queue Debug reg 0x30 */
 470         u32 fmdmccqvr1; /* FM DMA CAM and CMD Queue Value reg #1 0x34 */
 471         u32 fmdmccqvr2; /* FM DMA CAM and CMD Queue Value reg #2 0x38 */
 472         u32 fmdmcqvr3;  /* FM DMA CMD Queue Value register #3 0x3c */
 473         u32 fmdmcqvr4;  /* FM DMA CMD Queue Value register #4 0x40 */
 474         u32 fmdmcqvr5;  /* FM DMA CMD Queue Value register #5 0x44 */
 475         u32 fmdmsefrc;  /* FM DMA Semaphore Entry Full Reject Cntr 0x48 */
 476         u32 fmdmsqfrc;  /* FM DMA Semaphore Queue Full Reject Cntr 0x4c */
 477         u32 fmdmssrc;   /* FM DMA Semaphore SYNC Reject Counter 0x50 */
 478         u32 fmdmdcr;    /* FM DMA Debug Counter 0x54 */
 479         u32 fmdmemsr;   /* FM DMA Emergency Smoother Register 0x58 */
 480         u32 res005c;    /* 0x5c */
 481         u32 fmdmplr[FMAN_LIODN_TBL / 2];        /* DMA LIODN regs 0x60-0xdf */
 482         u32 res00e0[0x400 - 56];
 483 };
 484 
 485 struct fman_hwp_regs {
 486         u32 res0000[0x844 / 4];         /* 0x000..0x843 */
 487         u32 fmprrpimac; /* FM Parser Internal memory access control */
 488         u32 res[(0x1000 - 0x848) / 4];  /* 0x848..0xFFF */
 489 };
 490 
 491 /* Structure that holds current FMan state.
 492  * Used for saving run time information.
 493  */
 494 struct fman_state_struct {
 495         u8 fm_id;
 496         u16 fm_clk_freq;
 497         struct fman_rev_info rev_info;
 498         bool enabled_time_stamp;
 499         u8 count1_micro_bit;
 500         u8 total_num_of_tasks;
 501         u8 accumulated_num_of_tasks;
 502         u32 accumulated_fifo_size;
 503         u8 accumulated_num_of_open_dmas;
 504         u8 accumulated_num_of_deq_tnums;
 505         u32 exceptions;
 506         u32 extra_fifo_pool_size;
 507         u8 extra_tasks_pool_size;
 508         u8 extra_open_dmas_pool_size;
 509         u16 port_mfl[MAX_NUM_OF_MACS];
 510         u16 mac_mfl[MAX_NUM_OF_MACS];
 511 
 512         /* SOC specific */
 513         u32 fm_iram_size;
 514         /* DMA */
 515         u32 dma_thresh_max_commq;
 516         u32 dma_thresh_max_buf;
 517         u32 max_num_of_open_dmas;
 518         /* QMI */
 519         u32 qmi_max_num_of_tnums;
 520         u32 qmi_def_tnums_thresh;
 521         /* BMI */
 522         u32 bmi_max_num_of_tasks;
 523         u32 bmi_max_fifo_size;
 524         /* General */
 525         u32 fm_port_num_of_cg;
 526         u32 num_of_rx_ports;
 527         u32 total_fifo_size;
 528 
 529         u32 qman_channel_base;
 530         u32 num_of_qman_channels;
 531 
 532         struct resource *res;
 533 };
 534 
 535 /* Structure that holds FMan initial configuration */
 536 struct fman_cfg {
 537         u8 disp_limit_tsh;
 538         u8 prs_disp_tsh;
 539         u8 plcr_disp_tsh;
 540         u8 kg_disp_tsh;
 541         u8 bmi_disp_tsh;
 542         u8 qmi_enq_disp_tsh;
 543         u8 qmi_deq_disp_tsh;
 544         u8 fm_ctl1_disp_tsh;
 545         u8 fm_ctl2_disp_tsh;
 546         int dma_cache_override;
 547         enum fman_dma_aid_mode dma_aid_mode;
 548         u32 dma_axi_dbg_num_of_beats;
 549         u32 dma_cam_num_of_entries;
 550         u32 dma_watchdog;
 551         u8 dma_comm_qtsh_asrt_emer;
 552         u32 dma_write_buf_tsh_asrt_emer;
 553         u32 dma_read_buf_tsh_asrt_emer;
 554         u8 dma_comm_qtsh_clr_emer;
 555         u32 dma_write_buf_tsh_clr_emer;
 556         u32 dma_read_buf_tsh_clr_emer;
 557         u32 dma_sos_emergency;
 558         int dma_dbg_cnt_mode;
 559         int catastrophic_err;
 560         int dma_err;
 561         u32 exceptions;
 562         u16 clk_freq;
 563         u32 cam_base_addr;
 564         u32 fifo_base_addr;
 565         u32 total_fifo_size;
 566         u32 total_num_of_tasks;
 567         u32 qmi_def_tnums_thresh;
 568 };
 569 
 570 #ifdef CONFIG_DPAA_ERRATUM_A050385
 571 static bool fman_has_err_a050385;
 572 #endif
 573 
 574 static irqreturn_t fman_exceptions(struct fman *fman,
 575                                    enum fman_exceptions exception)
 576 {
 577         dev_dbg(fman->dev, "%s: FMan[%d] exception %d\n",
 578                 __func__, fman->state->fm_id, exception);
 579 
 580         return IRQ_HANDLED;
 581 }
 582 
 583 static irqreturn_t fman_bus_error(struct fman *fman, u8 __maybe_unused port_id,
 584                                   u64 __maybe_unused addr,
 585                                   u8 __maybe_unused tnum,
 586                                   u16 __maybe_unused liodn)
 587 {
 588         dev_dbg(fman->dev, "%s: FMan[%d] bus error: port_id[%d]\n",
 589                 __func__, fman->state->fm_id, port_id);
 590 
 591         return IRQ_HANDLED;
 592 }
 593 
 594 static inline irqreturn_t call_mac_isr(struct fman *fman, u8 id)
 595 {
 596         if (fman->intr_mng[id].isr_cb) {
 597                 fman->intr_mng[id].isr_cb(fman->intr_mng[id].src_handle);
 598 
 599                 return IRQ_HANDLED;
 600         }
 601 
 602         return IRQ_NONE;
 603 }
 604 
 605 static inline u8 hw_port_id_to_sw_port_id(u8 major, u8 hw_port_id)
 606 {
 607         u8 sw_port_id = 0;
 608 
 609         if (hw_port_id >= BASE_TX_PORTID)
 610                 sw_port_id = hw_port_id - BASE_TX_PORTID;
 611         else if (hw_port_id >= BASE_RX_PORTID)
 612                 sw_port_id = hw_port_id - BASE_RX_PORTID;
 613         else
 614                 sw_port_id = 0;
 615 
 616         return sw_port_id;
 617 }
 618 
 619 static void set_port_order_restoration(struct fman_fpm_regs __iomem *fpm_rg,
 620                                        u8 port_id)
 621 {
 622         u32 tmp = 0;
 623 
 624         tmp = port_id << FPM_PORT_FM_CTL_PORTID_SHIFT;
 625 
 626         tmp |= FPM_PRT_FM_CTL2 | FPM_PRT_FM_CTL1;
 627 
 628         /* order restoration */
 629         if (port_id % 2)
 630                 tmp |= FPM_PRT_FM_CTL1 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT;
 631         else
 632                 tmp |= FPM_PRT_FM_CTL2 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT;
 633 
 634         iowrite32be(tmp, &fpm_rg->fmfp_prc);
 635 }
 636 
 637 static void set_port_liodn(struct fman *fman, u8 port_id,
 638                            u32 liodn_base, u32 liodn_ofst)
 639 {
 640         u32 tmp;
 641 
 642         /* set LIODN base for this port */
 643         tmp = ioread32be(&fman->dma_regs->fmdmplr[port_id / 2]);
 644         if (port_id % 2) {
 645                 tmp &= ~DMA_LIODN_BASE_MASK;
 646                 tmp |= liodn_base;
 647         } else {
 648                 tmp &= ~(DMA_LIODN_BASE_MASK << DMA_LIODN_SHIFT);
 649                 tmp |= liodn_base << DMA_LIODN_SHIFT;
 650         }
 651         iowrite32be(tmp, &fman->dma_regs->fmdmplr[port_id / 2]);
 652         iowrite32be(liodn_ofst, &fman->bmi_regs->fmbm_spliodn[port_id - 1]);
 653 }
 654 
 655 static void enable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
 656 {
 657         u32 tmp;
 658 
 659         tmp = ioread32be(&fpm_rg->fm_rcr);
 660         if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
 661                 iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
 662         else
 663                 iowrite32be(tmp | FPM_RAM_RAMS_ECC_EN |
 664                             FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
 665 }
 666 
 667 static void disable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
 668 {
 669         u32 tmp;
 670 
 671         tmp = ioread32be(&fpm_rg->fm_rcr);
 672         if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
 673                 iowrite32be(tmp & ~FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
 674         else
 675                 iowrite32be(tmp & ~(FPM_RAM_RAMS_ECC_EN | FPM_RAM_IRAM_ECC_EN),
 676                             &fpm_rg->fm_rcr);
 677 }
 678 
 679 static void fman_defconfig(struct fman_cfg *cfg)
 680 {
 681         memset(cfg, 0, sizeof(struct fman_cfg));
 682 
 683         cfg->catastrophic_err = DEFAULT_CATASTROPHIC_ERR;
 684         cfg->dma_err = DEFAULT_DMA_ERR;
 685         cfg->dma_aid_mode = DEFAULT_AID_MODE;
 686         cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW;
 687         cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH;
 688         cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE;
 689         cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES;
 690         cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE;
 691         cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY;
 692         cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG;
 693         cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT;
 694         cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH;
 695         cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH;
 696         cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH;
 697         cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH;
 698         cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH;
 699         cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH;
 700         cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH;
 701         cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH;
 702 }
 703 
 704 static int dma_init(struct fman *fman)
 705 {
 706         struct fman_dma_regs __iomem *dma_rg = fman->dma_regs;
 707         struct fman_cfg *cfg = fman->cfg;
 708         u32 tmp_reg;
 709 
 710         /* Init DMA Registers */
 711 
 712         /* clear status reg events */
 713         tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC |
 714                    DMA_STATUS_SYSTEM_WRITE_ECC | DMA_STATUS_FM_WRITE_ECC);
 715         iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, &dma_rg->fmdmsr);
 716 
 717         /* configure mode register */
 718         tmp_reg = 0;
 719         tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT;
 720         if (cfg->exceptions & EX_DMA_BUS_ERROR)
 721                 tmp_reg |= DMA_MODE_BER;
 722         if ((cfg->exceptions & EX_DMA_SYSTEM_WRITE_ECC) |
 723             (cfg->exceptions & EX_DMA_READ_ECC) |
 724             (cfg->exceptions & EX_DMA_FM_WRITE_ECC))
 725                 tmp_reg |= DMA_MODE_ECC;
 726         if (cfg->dma_axi_dbg_num_of_beats)
 727                 tmp_reg |= (DMA_MODE_AXI_DBG_MASK &
 728                         ((cfg->dma_axi_dbg_num_of_beats - 1)
 729                         << DMA_MODE_AXI_DBG_SHIFT));
 730 
 731         tmp_reg |= (((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) &
 732                 DMA_MODE_CEN_MASK) << DMA_MODE_CEN_SHIFT;
 733         tmp_reg |= DMA_MODE_SECURE_PROT;
 734         tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT;
 735         tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT;
 736 
 737         iowrite32be(tmp_reg, &dma_rg->fmdmmr);
 738 
 739         /* configure thresholds register */
 740         tmp_reg = ((u32)cfg->dma_comm_qtsh_asrt_emer <<
 741                 DMA_THRESH_COMMQ_SHIFT);
 742         tmp_reg |= (cfg->dma_read_buf_tsh_asrt_emer &
 743                 DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT;
 744         tmp_reg |= cfg->dma_write_buf_tsh_asrt_emer &
 745                 DMA_THRESH_WRITE_INT_BUF_MASK;
 746 
 747         iowrite32be(tmp_reg, &dma_rg->fmdmtr);
 748 
 749         /* configure hysteresis register */
 750         tmp_reg = ((u32)cfg->dma_comm_qtsh_clr_emer <<
 751                 DMA_THRESH_COMMQ_SHIFT);
 752         tmp_reg |= (cfg->dma_read_buf_tsh_clr_emer &
 753                 DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT;
 754         tmp_reg |= cfg->dma_write_buf_tsh_clr_emer &
 755                 DMA_THRESH_WRITE_INT_BUF_MASK;
 756 
 757         iowrite32be(tmp_reg, &dma_rg->fmdmhy);
 758 
 759         /* configure emergency threshold */
 760         iowrite32be(cfg->dma_sos_emergency, &dma_rg->fmdmsetr);
 761 
 762         /* configure Watchdog */
 763         iowrite32be((cfg->dma_watchdog * cfg->clk_freq), &dma_rg->fmdmwcr);
 764 
 765         iowrite32be(cfg->cam_base_addr, &dma_rg->fmdmebcr);
 766 
 767         /* Allocate MURAM for CAM */
 768         fman->cam_size =
 769                 (u32)(fman->cfg->dma_cam_num_of_entries * DMA_CAM_SIZEOF_ENTRY);
 770         fman->cam_offset = fman_muram_alloc(fman->muram, fman->cam_size);
 771         if (IS_ERR_VALUE(fman->cam_offset)) {
 772                 dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n",
 773                         __func__);
 774                 return -ENOMEM;
 775         }
 776 
 777         if (fman->state->rev_info.major == 2) {
 778                 u32 __iomem *cam_base_addr;
 779 
 780                 fman_muram_free_mem(fman->muram, fman->cam_offset,
 781                                     fman->cam_size);
 782 
 783                 fman->cam_size = fman->cfg->dma_cam_num_of_entries * 72 + 128;
 784                 fman->cam_offset = fman_muram_alloc(fman->muram,
 785                                                     fman->cam_size);
 786                 if (IS_ERR_VALUE(fman->cam_offset)) {
 787                         dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n",
 788                                 __func__);
 789                         return -ENOMEM;
 790                 }
 791 
 792                 if (fman->cfg->dma_cam_num_of_entries % 8 ||
 793                     fman->cfg->dma_cam_num_of_entries > 32) {
 794                         dev_err(fman->dev, "%s: wrong dma_cam_num_of_entries\n",
 795                                 __func__);
 796                         return -EINVAL;
 797                 }
 798 
 799                 cam_base_addr = (u32 __iomem *)
 800                         fman_muram_offset_to_vbase(fman->muram,
 801                                                    fman->cam_offset);
 802                 iowrite32be(~((1 <<
 803                             (32 - fman->cfg->dma_cam_num_of_entries)) - 1),
 804                             cam_base_addr);
 805         }
 806 
 807         fman->cfg->cam_base_addr = fman->cam_offset;
 808 
 809         return 0;
 810 }
 811 
 812 static void fpm_init(struct fman_fpm_regs __iomem *fpm_rg, struct fman_cfg *cfg)
 813 {
 814         u32 tmp_reg;
 815         int i;
 816 
 817         /* Init FPM Registers */
 818 
 819         tmp_reg = (u32)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT);
 820         iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd);
 821 
 822         tmp_reg = (((u32)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) |
 823                    ((u32)cfg->kg_disp_tsh << FPM_THR1_KG_SHIFT) |
 824                    ((u32)cfg->plcr_disp_tsh << FPM_THR1_PLCR_SHIFT) |
 825                    ((u32)cfg->bmi_disp_tsh << FPM_THR1_BMI_SHIFT));
 826         iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1);
 827 
 828         tmp_reg =
 829                 (((u32)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) |
 830                  ((u32)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT) |
 831                  ((u32)cfg->fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) |
 832                  ((u32)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT));
 833         iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2);
 834 
 835         /* define exceptions and error behavior */
 836         tmp_reg = 0;
 837         /* Clear events */
 838         tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC |
 839                     FPM_EV_MASK_SINGLE_ECC);
 840         /* enable interrupts */
 841         if (cfg->exceptions & EX_FPM_STALL_ON_TASKS)
 842                 tmp_reg |= FPM_EV_MASK_STALL_EN;
 843         if (cfg->exceptions & EX_FPM_SINGLE_ECC)
 844                 tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN;
 845         if (cfg->exceptions & EX_FPM_DOUBLE_ECC)
 846                 tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN;
 847         tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT);
 848         tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT);
 849         /* FMan is not halted upon external halt activation */
 850         tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT;
 851         /* Man is not halted upon  Unrecoverable ECC error behavior */
 852         tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT;
 853         iowrite32be(tmp_reg, &fpm_rg->fmfp_ee);
 854 
 855         /* clear all fmCtls event registers */
 856         for (i = 0; i < FM_NUM_OF_FMAN_CTRL_EVENT_REGS; i++)
 857                 iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]);
 858 
 859         /* RAM ECC -  enable and clear events */
 860         /* first we need to clear all parser memory,
 861          * as it is uninitialized and may cause ECC errors
 862          */
 863         /* event bits */
 864         tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC);
 865 
 866         iowrite32be(tmp_reg, &fpm_rg->fm_rcr);
 867 
 868         tmp_reg = 0;
 869         if (cfg->exceptions & EX_IRAM_ECC) {
 870                 tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN;
 871                 enable_rams_ecc(fpm_rg);
 872         }
 873         if (cfg->exceptions & EX_MURAM_ECC) {
 874                 tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN;
 875                 enable_rams_ecc(fpm_rg);
 876         }
 877         iowrite32be(tmp_reg, &fpm_rg->fm_rie);
 878 }
 879 
 880 static void bmi_init(struct fman_bmi_regs __iomem *bmi_rg,
 881                      struct fman_cfg *cfg)
 882 {
 883         u32 tmp_reg;
 884 
 885         /* Init BMI Registers */
 886 
 887         /* define common resources */
 888         tmp_reg = cfg->fifo_base_addr;
 889         tmp_reg = tmp_reg / BMI_FIFO_ALIGN;
 890 
 891         tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) <<
 892                     BMI_CFG1_FIFO_SIZE_SHIFT);
 893         iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1);
 894 
 895         tmp_reg = ((cfg->total_num_of_tasks - 1) & BMI_CFG2_TASKS_MASK) <<
 896                    BMI_CFG2_TASKS_SHIFT;
 897         /* num of DMA's will be dynamically updated when each port is set */
 898         iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2);
 899 
 900         /* define unmaskable exceptions, enable and clear events */
 901         tmp_reg = 0;
 902         iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC |
 903                     BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC |
 904                     BMI_ERR_INTR_EN_STATISTICS_RAM_ECC |
 905                     BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, &bmi_rg->fmbm_ievr);
 906 
 907         if (cfg->exceptions & EX_BMI_LIST_RAM_ECC)
 908                 tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
 909         if (cfg->exceptions & EX_BMI_STORAGE_PROFILE_ECC)
 910                 tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
 911         if (cfg->exceptions & EX_BMI_STATISTICS_RAM_ECC)
 912                 tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
 913         if (cfg->exceptions & EX_BMI_DISPATCH_RAM_ECC)
 914                 tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
 915         iowrite32be(tmp_reg, &bmi_rg->fmbm_ier);
 916 }
 917 
 918 static void qmi_init(struct fman_qmi_regs __iomem *qmi_rg,
 919                      struct fman_cfg *cfg)
 920 {
 921         u32 tmp_reg;
 922 
 923         /* Init QMI Registers */
 924 
 925         /* Clear error interrupt events */
 926 
 927         iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC | QMI_ERR_INTR_EN_DEQ_FROM_DEF,
 928                     &qmi_rg->fmqm_eie);
 929         tmp_reg = 0;
 930         if (cfg->exceptions & EX_QMI_DEQ_FROM_UNKNOWN_PORTID)
 931                 tmp_reg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
 932         if (cfg->exceptions & EX_QMI_DOUBLE_ECC)
 933                 tmp_reg |= QMI_ERR_INTR_EN_DOUBLE_ECC;
 934         /* enable events */
 935         iowrite32be(tmp_reg, &qmi_rg->fmqm_eien);
 936 
 937         tmp_reg = 0;
 938         /* Clear interrupt events */
 939         iowrite32be(QMI_INTR_EN_SINGLE_ECC, &qmi_rg->fmqm_ie);
 940         if (cfg->exceptions & EX_QMI_SINGLE_ECC)
 941                 tmp_reg |= QMI_INTR_EN_SINGLE_ECC;
 942         /* enable events */
 943         iowrite32be(tmp_reg, &qmi_rg->fmqm_ien);
 944 }
 945 
 946 static void hwp_init(struct fman_hwp_regs __iomem *hwp_rg)
 947 {
 948         /* enable HW Parser */
 949         iowrite32be(HWP_RPIMAC_PEN, &hwp_rg->fmprrpimac);
 950 }
 951 
 952 static int enable(struct fman *fman, struct fman_cfg *cfg)
 953 {
 954         u32 cfg_reg = 0;
 955 
 956         /* Enable all modules */
 957 
 958         /* clear&enable global counters - calculate reg and save for later,
 959          * because it's the same reg for QMI enable
 960          */
 961         cfg_reg = QMI_CFG_EN_COUNTERS;
 962 
 963         /* Set enqueue and dequeue thresholds */
 964         cfg_reg |= (cfg->qmi_def_tnums_thresh << 8) | cfg->qmi_def_tnums_thresh;
 965 
 966         iowrite32be(BMI_INIT_START, &fman->bmi_regs->fmbm_init);
 967         iowrite32be(cfg_reg | QMI_CFG_ENQ_EN | QMI_CFG_DEQ_EN,
 968                     &fman->qmi_regs->fmqm_gc);
 969 
 970         return 0;
 971 }
 972 
 973 static int set_exception(struct fman *fman,
 974                          enum fman_exceptions exception, bool enable)
 975 {
 976         u32 tmp;
 977 
 978         switch (exception) {
 979         case FMAN_EX_DMA_BUS_ERROR:
 980                 tmp = ioread32be(&fman->dma_regs->fmdmmr);
 981                 if (enable)
 982                         tmp |= DMA_MODE_BER;
 983                 else
 984                         tmp &= ~DMA_MODE_BER;
 985                 /* disable bus error */
 986                 iowrite32be(tmp, &fman->dma_regs->fmdmmr);
 987                 break;
 988         case FMAN_EX_DMA_READ_ECC:
 989         case FMAN_EX_DMA_SYSTEM_WRITE_ECC:
 990         case FMAN_EX_DMA_FM_WRITE_ECC:
 991                 tmp = ioread32be(&fman->dma_regs->fmdmmr);
 992                 if (enable)
 993                         tmp |= DMA_MODE_ECC;
 994                 else
 995                         tmp &= ~DMA_MODE_ECC;
 996                 iowrite32be(tmp, &fman->dma_regs->fmdmmr);
 997                 break;
 998         case FMAN_EX_FPM_STALL_ON_TASKS:
 999                 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1000                 if (enable)
1001                         tmp |= FPM_EV_MASK_STALL_EN;
1002                 else
1003                         tmp &= ~FPM_EV_MASK_STALL_EN;
1004                 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1005                 break;
1006         case FMAN_EX_FPM_SINGLE_ECC:
1007                 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1008                 if (enable)
1009                         tmp |= FPM_EV_MASK_SINGLE_ECC_EN;
1010                 else
1011                         tmp &= ~FPM_EV_MASK_SINGLE_ECC_EN;
1012                 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1013                 break;
1014         case FMAN_EX_FPM_DOUBLE_ECC:
1015                 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1016                 if (enable)
1017                         tmp |= FPM_EV_MASK_DOUBLE_ECC_EN;
1018                 else
1019                         tmp &= ~FPM_EV_MASK_DOUBLE_ECC_EN;
1020                 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1021                 break;
1022         case FMAN_EX_QMI_SINGLE_ECC:
1023                 tmp = ioread32be(&fman->qmi_regs->fmqm_ien);
1024                 if (enable)
1025                         tmp |= QMI_INTR_EN_SINGLE_ECC;
1026                 else
1027                         tmp &= ~QMI_INTR_EN_SINGLE_ECC;
1028                 iowrite32be(tmp, &fman->qmi_regs->fmqm_ien);
1029                 break;
1030         case FMAN_EX_QMI_DOUBLE_ECC:
1031                 tmp = ioread32be(&fman->qmi_regs->fmqm_eien);
1032                 if (enable)
1033                         tmp |= QMI_ERR_INTR_EN_DOUBLE_ECC;
1034                 else
1035                         tmp &= ~QMI_ERR_INTR_EN_DOUBLE_ECC;
1036                 iowrite32be(tmp, &fman->qmi_regs->fmqm_eien);
1037                 break;
1038         case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:
1039                 tmp = ioread32be(&fman->qmi_regs->fmqm_eien);
1040                 if (enable)
1041                         tmp |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
1042                 else
1043                         tmp &= ~QMI_ERR_INTR_EN_DEQ_FROM_DEF;
1044                 iowrite32be(tmp, &fman->qmi_regs->fmqm_eien);
1045                 break;
1046         case FMAN_EX_BMI_LIST_RAM_ECC:
1047                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1048                 if (enable)
1049                         tmp |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
1050                 else
1051                         tmp &= ~BMI_ERR_INTR_EN_LIST_RAM_ECC;
1052                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1053                 break;
1054         case FMAN_EX_BMI_STORAGE_PROFILE_ECC:
1055                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1056                 if (enable)
1057                         tmp |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
1058                 else
1059                         tmp &= ~BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
1060                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1061                 break;
1062         case FMAN_EX_BMI_STATISTICS_RAM_ECC:
1063                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1064                 if (enable)
1065                         tmp |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
1066                 else
1067                         tmp &= ~BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
1068                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1069                 break;
1070         case FMAN_EX_BMI_DISPATCH_RAM_ECC:
1071                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1072                 if (enable)
1073                         tmp |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
1074                 else
1075                         tmp &= ~BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
1076                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1077                 break;
1078         case FMAN_EX_IRAM_ECC:
1079                 tmp = ioread32be(&fman->fpm_regs->fm_rie);
1080                 if (enable) {
1081                         /* enable ECC if not enabled */
1082                         enable_rams_ecc(fman->fpm_regs);
1083                         /* enable ECC interrupts */
1084                         tmp |= FPM_IRAM_ECC_ERR_EX_EN;
1085                 } else {
1086                         /* ECC mechanism may be disabled,
1087                          * depending on driver status
1088                          */
1089                         disable_rams_ecc(fman->fpm_regs);
1090                         tmp &= ~FPM_IRAM_ECC_ERR_EX_EN;
1091                 }
1092                 iowrite32be(tmp, &fman->fpm_regs->fm_rie);
1093                 break;
1094         case FMAN_EX_MURAM_ECC:
1095                 tmp = ioread32be(&fman->fpm_regs->fm_rie);
1096                 if (enable) {
1097                         /* enable ECC if not enabled */
1098                         enable_rams_ecc(fman->fpm_regs);
1099                         /* enable ECC interrupts */
1100                         tmp |= FPM_MURAM_ECC_ERR_EX_EN;
1101                 } else {
1102                         /* ECC mechanism may be disabled,
1103                          * depending on driver status
1104                          */
1105                         disable_rams_ecc(fman->fpm_regs);
1106                         tmp &= ~FPM_MURAM_ECC_ERR_EX_EN;
1107                 }
1108                 iowrite32be(tmp, &fman->fpm_regs->fm_rie);
1109                 break;
1110         default:
1111                 return -EINVAL;
1112         }
1113         return 0;
1114 }
1115 
1116 static void resume(struct fman_fpm_regs __iomem *fpm_rg)
1117 {
1118         u32 tmp;
1119 
1120         tmp = ioread32be(&fpm_rg->fmfp_ee);
1121         /* clear tmp_reg event bits in order not to clear standing events */
1122         tmp &= ~(FPM_EV_MASK_DOUBLE_ECC |
1123                  FPM_EV_MASK_STALL | FPM_EV_MASK_SINGLE_ECC);
1124         tmp |= FPM_EV_MASK_RELEASE_FM;
1125 
1126         iowrite32be(tmp, &fpm_rg->fmfp_ee);
1127 }
1128 
1129 static int fill_soc_specific_params(struct fman_state_struct *state)
1130 {
1131         u8 minor = state->rev_info.minor;
1132         /* P4080 - Major 2
1133          * P2041/P3041/P5020/P5040 - Major 3
1134          * Tx/Bx - Major 6
1135          */
1136         switch (state->rev_info.major) {
1137         case 3:
1138                 state->bmi_max_fifo_size        = 160 * 1024;
1139                 state->fm_iram_size             = 64 * 1024;
1140                 state->dma_thresh_max_commq     = 31;
1141                 state->dma_thresh_max_buf       = 127;
1142                 state->qmi_max_num_of_tnums     = 64;
1143                 state->qmi_def_tnums_thresh     = 48;
1144                 state->bmi_max_num_of_tasks     = 128;
1145                 state->max_num_of_open_dmas     = 32;
1146                 state->fm_port_num_of_cg        = 256;
1147                 state->num_of_rx_ports  = 6;
1148                 state->total_fifo_size  = 136 * 1024;
1149                 break;
1150 
1151         case 2:
1152                 state->bmi_max_fifo_size        = 160 * 1024;
1153                 state->fm_iram_size             = 64 * 1024;
1154                 state->dma_thresh_max_commq     = 31;
1155                 state->dma_thresh_max_buf       = 127;
1156                 state->qmi_max_num_of_tnums     = 64;
1157                 state->qmi_def_tnums_thresh     = 48;
1158                 state->bmi_max_num_of_tasks     = 128;
1159                 state->max_num_of_open_dmas     = 32;
1160                 state->fm_port_num_of_cg        = 256;
1161                 state->num_of_rx_ports  = 5;
1162                 state->total_fifo_size  = 100 * 1024;
1163                 break;
1164 
1165         case 6:
1166                 state->dma_thresh_max_commq     = 83;
1167                 state->dma_thresh_max_buf       = 127;
1168                 state->qmi_max_num_of_tnums     = 64;
1169                 state->qmi_def_tnums_thresh     = 32;
1170                 state->fm_port_num_of_cg        = 256;
1171 
1172                 /* FManV3L */
1173                 if (minor == 1 || minor == 4) {
1174                         state->bmi_max_fifo_size        = 192 * 1024;
1175                         state->bmi_max_num_of_tasks     = 64;
1176                         state->max_num_of_open_dmas     = 32;
1177                         state->num_of_rx_ports          = 5;
1178                         if (minor == 1)
1179                                 state->fm_iram_size     = 32 * 1024;
1180                         else
1181                                 state->fm_iram_size     = 64 * 1024;
1182                         state->total_fifo_size          = 156 * 1024;
1183                 }
1184                 /* FManV3H */
1185                 else if (minor == 0 || minor == 2 || minor == 3) {
1186                         state->bmi_max_fifo_size        = 384 * 1024;
1187                         state->fm_iram_size             = 64 * 1024;
1188                         state->bmi_max_num_of_tasks     = 128;
1189                         state->max_num_of_open_dmas     = 84;
1190                         state->num_of_rx_ports          = 8;
1191                         state->total_fifo_size          = 295 * 1024;
1192                 } else {
1193                         pr_err("Unsupported FManv3 version\n");
1194                         return -EINVAL;
1195                 }
1196 
1197                 break;
1198         default:
1199                 pr_err("Unsupported FMan version\n");
1200                 return -EINVAL;
1201         }
1202 
1203         return 0;
1204 }
1205 
1206 static bool is_init_done(struct fman_cfg *cfg)
1207 {
1208         /* Checks if FMan driver parameters were initialized */
1209         if (!cfg)
1210                 return true;
1211 
1212         return false;
1213 }
1214 
1215 static void free_init_resources(struct fman *fman)
1216 {
1217         if (fman->cam_offset)
1218                 fman_muram_free_mem(fman->muram, fman->cam_offset,
1219                                     fman->cam_size);
1220         if (fman->fifo_offset)
1221                 fman_muram_free_mem(fman->muram, fman->fifo_offset,
1222                                     fman->fifo_size);
1223 }
1224 
1225 static irqreturn_t bmi_err_event(struct fman *fman)
1226 {
1227         u32 event, mask, force;
1228         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1229         irqreturn_t ret = IRQ_NONE;
1230 
1231         event = ioread32be(&bmi_rg->fmbm_ievr);
1232         mask = ioread32be(&bmi_rg->fmbm_ier);
1233         event &= mask;
1234         /* clear the forced events */
1235         force = ioread32be(&bmi_rg->fmbm_ifr);
1236         if (force & event)
1237                 iowrite32be(force & ~event, &bmi_rg->fmbm_ifr);
1238         /* clear the acknowledged events */
1239         iowrite32be(event, &bmi_rg->fmbm_ievr);
1240 
1241         if (event & BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC)
1242                 ret = fman->exception_cb(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC);
1243         if (event & BMI_ERR_INTR_EN_LIST_RAM_ECC)
1244                 ret = fman->exception_cb(fman, FMAN_EX_BMI_LIST_RAM_ECC);
1245         if (event & BMI_ERR_INTR_EN_STATISTICS_RAM_ECC)
1246                 ret = fman->exception_cb(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC);
1247         if (event & BMI_ERR_INTR_EN_DISPATCH_RAM_ECC)
1248                 ret = fman->exception_cb(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC);
1249 
1250         return ret;
1251 }
1252 
1253 static irqreturn_t qmi_err_event(struct fman *fman)
1254 {
1255         u32 event, mask, force;
1256         struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs;
1257         irqreturn_t ret = IRQ_NONE;
1258 
1259         event = ioread32be(&qmi_rg->fmqm_eie);
1260         mask = ioread32be(&qmi_rg->fmqm_eien);
1261         event &= mask;
1262 
1263         /* clear the forced events */
1264         force = ioread32be(&qmi_rg->fmqm_eif);
1265         if (force & event)
1266                 iowrite32be(force & ~event, &qmi_rg->fmqm_eif);
1267         /* clear the acknowledged events */
1268         iowrite32be(event, &qmi_rg->fmqm_eie);
1269 
1270         if (event & QMI_ERR_INTR_EN_DOUBLE_ECC)
1271                 ret = fman->exception_cb(fman, FMAN_EX_QMI_DOUBLE_ECC);
1272         if (event & QMI_ERR_INTR_EN_DEQ_FROM_DEF)
1273                 ret = fman->exception_cb(fman,
1274                                          FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID);
1275 
1276         return ret;
1277 }
1278 
1279 static irqreturn_t dma_err_event(struct fman *fman)
1280 {
1281         u32 status, mask, com_id;
1282         u8 tnum, port_id, relative_port_id;
1283         u16 liodn;
1284         struct fman_dma_regs __iomem *dma_rg = fman->dma_regs;
1285         irqreturn_t ret = IRQ_NONE;
1286 
1287         status = ioread32be(&dma_rg->fmdmsr);
1288         mask = ioread32be(&dma_rg->fmdmmr);
1289 
1290         /* clear DMA_STATUS_BUS_ERR if mask has no DMA_MODE_BER */
1291         if ((mask & DMA_MODE_BER) != DMA_MODE_BER)
1292                 status &= ~DMA_STATUS_BUS_ERR;
1293 
1294         /* clear relevant bits if mask has no DMA_MODE_ECC */
1295         if ((mask & DMA_MODE_ECC) != DMA_MODE_ECC)
1296                 status &= ~(DMA_STATUS_FM_SPDAT_ECC |
1297                             DMA_STATUS_READ_ECC |
1298                             DMA_STATUS_SYSTEM_WRITE_ECC |
1299                             DMA_STATUS_FM_WRITE_ECC);
1300 
1301         /* clear set events */
1302         iowrite32be(status, &dma_rg->fmdmsr);
1303 
1304         if (status & DMA_STATUS_BUS_ERR) {
1305                 u64 addr;
1306 
1307                 addr = (u64)ioread32be(&dma_rg->fmdmtal);
1308                 addr |= ((u64)(ioread32be(&dma_rg->fmdmtah)) << 32);
1309 
1310                 com_id = ioread32be(&dma_rg->fmdmtcid);
1311                 port_id = (u8)(((com_id & DMA_TRANSFER_PORTID_MASK) >>
1312                                DMA_TRANSFER_PORTID_SHIFT));
1313                 relative_port_id =
1314                 hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id);
1315                 tnum = (u8)((com_id & DMA_TRANSFER_TNUM_MASK) >>
1316                             DMA_TRANSFER_TNUM_SHIFT);
1317                 liodn = (u16)(com_id & DMA_TRANSFER_LIODN_MASK);
1318                 ret = fman->bus_error_cb(fman, relative_port_id, addr, tnum,
1319                                          liodn);
1320         }
1321         if (status & DMA_STATUS_FM_SPDAT_ECC)
1322                 ret = fman->exception_cb(fman, FMAN_EX_DMA_SINGLE_PORT_ECC);
1323         if (status & DMA_STATUS_READ_ECC)
1324                 ret = fman->exception_cb(fman, FMAN_EX_DMA_READ_ECC);
1325         if (status & DMA_STATUS_SYSTEM_WRITE_ECC)
1326                 ret = fman->exception_cb(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC);
1327         if (status & DMA_STATUS_FM_WRITE_ECC)
1328                 ret = fman->exception_cb(fman, FMAN_EX_DMA_FM_WRITE_ECC);
1329 
1330         return ret;
1331 }
1332 
1333 static irqreturn_t fpm_err_event(struct fman *fman)
1334 {
1335         u32 event;
1336         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1337         irqreturn_t ret = IRQ_NONE;
1338 
1339         event = ioread32be(&fpm_rg->fmfp_ee);
1340         /* clear the all occurred events */
1341         iowrite32be(event, &fpm_rg->fmfp_ee);
1342 
1343         if ((event & FPM_EV_MASK_DOUBLE_ECC) &&
1344             (event & FPM_EV_MASK_DOUBLE_ECC_EN))
1345                 ret = fman->exception_cb(fman, FMAN_EX_FPM_DOUBLE_ECC);
1346         if ((event & FPM_EV_MASK_STALL) && (event & FPM_EV_MASK_STALL_EN))
1347                 ret = fman->exception_cb(fman, FMAN_EX_FPM_STALL_ON_TASKS);
1348         if ((event & FPM_EV_MASK_SINGLE_ECC) &&
1349             (event & FPM_EV_MASK_SINGLE_ECC_EN))
1350                 ret = fman->exception_cb(fman, FMAN_EX_FPM_SINGLE_ECC);
1351 
1352         return ret;
1353 }
1354 
1355 static irqreturn_t muram_err_intr(struct fman *fman)
1356 {
1357         u32 event, mask;
1358         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1359         irqreturn_t ret = IRQ_NONE;
1360 
1361         event = ioread32be(&fpm_rg->fm_rcr);
1362         mask = ioread32be(&fpm_rg->fm_rie);
1363 
1364         /* clear MURAM event bit (do not clear IRAM event) */
1365         iowrite32be(event & ~FPM_RAM_IRAM_ECC, &fpm_rg->fm_rcr);
1366 
1367         if ((mask & FPM_MURAM_ECC_ERR_EX_EN) && (event & FPM_RAM_MURAM_ECC))
1368                 ret = fman->exception_cb(fman, FMAN_EX_MURAM_ECC);
1369 
1370         return ret;
1371 }
1372 
1373 static irqreturn_t qmi_event(struct fman *fman)
1374 {
1375         u32 event, mask, force;
1376         struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs;
1377         irqreturn_t ret = IRQ_NONE;
1378 
1379         event = ioread32be(&qmi_rg->fmqm_ie);
1380         mask = ioread32be(&qmi_rg->fmqm_ien);
1381         event &= mask;
1382         /* clear the forced events */
1383         force = ioread32be(&qmi_rg->fmqm_if);
1384         if (force & event)
1385                 iowrite32be(force & ~event, &qmi_rg->fmqm_if);
1386         /* clear the acknowledged events */
1387         iowrite32be(event, &qmi_rg->fmqm_ie);
1388 
1389         if (event & QMI_INTR_EN_SINGLE_ECC)
1390                 ret = fman->exception_cb(fman, FMAN_EX_QMI_SINGLE_ECC);
1391 
1392         return ret;
1393 }
1394 
1395 static void enable_time_stamp(struct fman *fman)
1396 {
1397         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1398         u16 fm_clk_freq = fman->state->fm_clk_freq;
1399         u32 tmp, intgr, ts_freq;
1400         u64 frac;
1401 
1402         ts_freq = (u32)(1 << fman->state->count1_micro_bit);
1403         /* configure timestamp so that bit 8 will count 1 microsecond
1404          * Find effective count rate at TIMESTAMP least significant bits:
1405          * Effective_Count_Rate = 1MHz x 2^8 = 256MHz
1406          * Find frequency ratio between effective count rate and the clock:
1407          * Effective_Count_Rate / CLK e.g. for 600 MHz clock:
1408          * 256/600 = 0.4266666...
1409          */
1410 
1411         intgr = ts_freq / fm_clk_freq;
1412         /* we multiply by 2^16 to keep the fraction of the division
1413          * we do not div back, since we write this value as a fraction
1414          * see spec
1415          */
1416 
1417         frac = ((ts_freq << 16) - (intgr << 16) * fm_clk_freq) / fm_clk_freq;
1418         /* we check remainder of the division in order to round up if not int */
1419         if (((ts_freq << 16) - (intgr << 16) * fm_clk_freq) % fm_clk_freq)
1420                 frac++;
1421 
1422         tmp = (intgr << FPM_TS_INT_SHIFT) | (u16)frac;
1423         iowrite32be(tmp, &fpm_rg->fmfp_tsc2);
1424 
1425         /* enable timestamp with original clock */
1426         iowrite32be(FPM_TS_CTL_EN, &fpm_rg->fmfp_tsc1);
1427         fman->state->enabled_time_stamp = true;
1428 }
1429 
1430 static int clear_iram(struct fman *fman)
1431 {
1432         struct fman_iram_regs __iomem *iram;
1433         int i, count;
1434 
1435         iram = fman->base_addr + IMEM_OFFSET;
1436 
1437         /* Enable the auto-increment */
1438         iowrite32be(IRAM_IADD_AIE, &iram->iadd);
1439         count = 100;
1440         do {
1441                 udelay(1);
1442         } while ((ioread32be(&iram->iadd) != IRAM_IADD_AIE) && --count);
1443         if (count == 0)
1444                 return -EBUSY;
1445 
1446         for (i = 0; i < (fman->state->fm_iram_size / 4); i++)
1447                 iowrite32be(0xffffffff, &iram->idata);
1448 
1449         iowrite32be(fman->state->fm_iram_size - 4, &iram->iadd);
1450         count = 100;
1451         do {
1452                 udelay(1);
1453         } while ((ioread32be(&iram->idata) != 0xffffffff) && --count);
1454         if (count == 0)
1455                 return -EBUSY;
1456 
1457         return 0;
1458 }
1459 
1460 static u32 get_exception_flag(enum fman_exceptions exception)
1461 {
1462         u32 bit_mask;
1463 
1464         switch (exception) {
1465         case FMAN_EX_DMA_BUS_ERROR:
1466                 bit_mask = EX_DMA_BUS_ERROR;
1467                 break;
1468         case FMAN_EX_DMA_SINGLE_PORT_ECC:
1469                 bit_mask = EX_DMA_SINGLE_PORT_ECC;
1470                 break;
1471         case FMAN_EX_DMA_READ_ECC:
1472                 bit_mask = EX_DMA_READ_ECC;
1473                 break;
1474         case FMAN_EX_DMA_SYSTEM_WRITE_ECC:
1475                 bit_mask = EX_DMA_SYSTEM_WRITE_ECC;
1476                 break;
1477         case FMAN_EX_DMA_FM_WRITE_ECC:
1478                 bit_mask = EX_DMA_FM_WRITE_ECC;
1479                 break;
1480         case FMAN_EX_FPM_STALL_ON_TASKS:
1481                 bit_mask = EX_FPM_STALL_ON_TASKS;
1482                 break;
1483         case FMAN_EX_FPM_SINGLE_ECC:
1484                 bit_mask = EX_FPM_SINGLE_ECC;
1485                 break;
1486         case FMAN_EX_FPM_DOUBLE_ECC:
1487                 bit_mask = EX_FPM_DOUBLE_ECC;
1488                 break;
1489         case FMAN_EX_QMI_SINGLE_ECC:
1490                 bit_mask = EX_QMI_SINGLE_ECC;
1491                 break;
1492         case FMAN_EX_QMI_DOUBLE_ECC:
1493                 bit_mask = EX_QMI_DOUBLE_ECC;
1494                 break;
1495         case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:
1496                 bit_mask = EX_QMI_DEQ_FROM_UNKNOWN_PORTID;
1497                 break;
1498         case FMAN_EX_BMI_LIST_RAM_ECC:
1499                 bit_mask = EX_BMI_LIST_RAM_ECC;
1500                 break;
1501         case FMAN_EX_BMI_STORAGE_PROFILE_ECC:
1502                 bit_mask = EX_BMI_STORAGE_PROFILE_ECC;
1503                 break;
1504         case FMAN_EX_BMI_STATISTICS_RAM_ECC:
1505                 bit_mask = EX_BMI_STATISTICS_RAM_ECC;
1506                 break;
1507         case FMAN_EX_BMI_DISPATCH_RAM_ECC:
1508                 bit_mask = EX_BMI_DISPATCH_RAM_ECC;
1509                 break;
1510         case FMAN_EX_MURAM_ECC:
1511                 bit_mask = EX_MURAM_ECC;
1512                 break;
1513         default:
1514                 bit_mask = 0;
1515                 break;
1516         }
1517 
1518         return bit_mask;
1519 }
1520 
1521 static int get_module_event(enum fman_event_modules module, u8 mod_id,
1522                             enum fman_intr_type intr_type)
1523 {
1524         int event;
1525 
1526         switch (module) {
1527         case FMAN_MOD_MAC:
1528                 if (intr_type == FMAN_INTR_TYPE_ERR)
1529                         event = FMAN_EV_ERR_MAC0 + mod_id;
1530                 else
1531                         event = FMAN_EV_MAC0 + mod_id;
1532                 break;
1533         case FMAN_MOD_FMAN_CTRL:
1534                 if (intr_type == FMAN_INTR_TYPE_ERR)
1535                         event = FMAN_EV_CNT;
1536                 else
1537                         event = (FMAN_EV_FMAN_CTRL_0 + mod_id);
1538                 break;
1539         case FMAN_MOD_DUMMY_LAST:
1540                 event = FMAN_EV_CNT;
1541                 break;
1542         default:
1543                 event = FMAN_EV_CNT;
1544                 break;
1545         }
1546 
1547         return event;
1548 }
1549 
1550 static int set_size_of_fifo(struct fman *fman, u8 port_id, u32 *size_of_fifo,
1551                             u32 *extra_size_of_fifo)
1552 {
1553         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1554         u32 fifo = *size_of_fifo;
1555         u32 extra_fifo = *extra_size_of_fifo;
1556         u32 tmp;
1557 
1558         /* if this is the first time a port requires extra_fifo_pool_size,
1559          * the total extra_fifo_pool_size must be initialized to 1 buffer per
1560          * port
1561          */
1562         if (extra_fifo && !fman->state->extra_fifo_pool_size)
1563                 fman->state->extra_fifo_pool_size =
1564                         fman->state->num_of_rx_ports * FMAN_BMI_FIFO_UNITS;
1565 
1566         fman->state->extra_fifo_pool_size =
1567                 max(fman->state->extra_fifo_pool_size, extra_fifo);
1568 
1569         /* check that there are enough uncommitted fifo size */
1570         if ((fman->state->accumulated_fifo_size + fifo) >
1571             (fman->state->total_fifo_size -
1572             fman->state->extra_fifo_pool_size)) {
1573                 dev_err(fman->dev, "%s: Requested fifo size and extra size exceed total FIFO size.\n",
1574                         __func__);
1575                 return -EAGAIN;
1576         }
1577 
1578         /* Read, modify and write to HW */
1579         tmp = (fifo / FMAN_BMI_FIFO_UNITS - 1) |
1580                ((extra_fifo / FMAN_BMI_FIFO_UNITS) <<
1581                BMI_EXTRA_FIFO_SIZE_SHIFT);
1582         iowrite32be(tmp, &bmi_rg->fmbm_pfs[port_id - 1]);
1583 
1584         /* update accumulated */
1585         fman->state->accumulated_fifo_size += fifo;
1586 
1587         return 0;
1588 }
1589 
1590 static int set_num_of_tasks(struct fman *fman, u8 port_id, u8 *num_of_tasks,
1591                             u8 *num_of_extra_tasks)
1592 {
1593         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1594         u8 tasks = *num_of_tasks;
1595         u8 extra_tasks = *num_of_extra_tasks;
1596         u32 tmp;
1597 
1598         if (extra_tasks)
1599                 fman->state->extra_tasks_pool_size =
1600                 max(fman->state->extra_tasks_pool_size, extra_tasks);
1601 
1602         /* check that there are enough uncommitted tasks */
1603         if ((fman->state->accumulated_num_of_tasks + tasks) >
1604             (fman->state->total_num_of_tasks -
1605              fman->state->extra_tasks_pool_size)) {
1606                 dev_err(fman->dev, "%s: Requested num_of_tasks and extra tasks pool for fm%d exceed total num_of_tasks.\n",
1607                         __func__, fman->state->fm_id);
1608                 return -EAGAIN;
1609         }
1610         /* update accumulated */
1611         fman->state->accumulated_num_of_tasks += tasks;
1612 
1613         /* Write to HW */
1614         tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
1615             ~(BMI_NUM_OF_TASKS_MASK | BMI_NUM_OF_EXTRA_TASKS_MASK);
1616         tmp |= ((u32)((tasks - 1) << BMI_NUM_OF_TASKS_SHIFT) |
1617                 (u32)(extra_tasks << BMI_EXTRA_NUM_OF_TASKS_SHIFT));
1618         iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
1619 
1620         return 0;
1621 }
1622 
1623 static int set_num_of_open_dmas(struct fman *fman, u8 port_id,
1624                                 u8 *num_of_open_dmas,
1625                                 u8 *num_of_extra_open_dmas)
1626 {
1627         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1628         u8 open_dmas = *num_of_open_dmas;
1629         u8 extra_open_dmas = *num_of_extra_open_dmas;
1630         u8 total_num_dmas = 0, current_val = 0, current_extra_val = 0;
1631         u32 tmp;
1632 
1633         if (!open_dmas) {
1634                 /* Configuration according to values in the HW.
1635                  * read the current number of open Dma's
1636                  */
1637                 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
1638                 current_extra_val = (u8)((tmp & BMI_NUM_OF_EXTRA_DMAS_MASK) >>
1639                                          BMI_EXTRA_NUM_OF_DMAS_SHIFT);
1640 
1641                 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
1642                 current_val = (u8)(((tmp & BMI_NUM_OF_DMAS_MASK) >>
1643                                    BMI_NUM_OF_DMAS_SHIFT) + 1);
1644 
1645                 /* This is the first configuration and user did not
1646                  * specify value (!open_dmas), reset values will be used
1647                  * and we just save these values for resource management
1648                  */
1649                 fman->state->extra_open_dmas_pool_size =
1650                         (u8)max(fman->state->extra_open_dmas_pool_size,
1651                                 current_extra_val);
1652                 fman->state->accumulated_num_of_open_dmas += current_val;
1653                 *num_of_open_dmas = current_val;
1654                 *num_of_extra_open_dmas = current_extra_val;
1655                 return 0;
1656         }
1657 
1658         if (extra_open_dmas > current_extra_val)
1659                 fman->state->extra_open_dmas_pool_size =
1660                     (u8)max(fman->state->extra_open_dmas_pool_size,
1661                             extra_open_dmas);
1662 
1663         if ((fman->state->rev_info.major < 6) &&
1664             (fman->state->accumulated_num_of_open_dmas - current_val +
1665              open_dmas > fman->state->max_num_of_open_dmas)) {
1666                 dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds total num_of_open_dmas.\n",
1667                         __func__, fman->state->fm_id);
1668                 return -EAGAIN;
1669         } else if ((fman->state->rev_info.major >= 6) &&
1670                    !((fman->state->rev_info.major == 6) &&
1671                    (fman->state->rev_info.minor == 0)) &&
1672                    (fman->state->accumulated_num_of_open_dmas -
1673                    current_val + open_dmas >
1674                    fman->state->dma_thresh_max_commq + 1)) {
1675                 dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds DMA Command queue (%d)\n",
1676                         __func__, fman->state->fm_id,
1677                        fman->state->dma_thresh_max_commq + 1);
1678                 return -EAGAIN;
1679         }
1680 
1681         WARN_ON(fman->state->accumulated_num_of_open_dmas < current_val);
1682         /* update acummulated */
1683         fman->state->accumulated_num_of_open_dmas -= current_val;
1684         fman->state->accumulated_num_of_open_dmas += open_dmas;
1685 
1686         if (fman->state->rev_info.major < 6)
1687                 total_num_dmas =
1688                     (u8)(fman->state->accumulated_num_of_open_dmas +
1689                     fman->state->extra_open_dmas_pool_size);
1690 
1691         /* calculate reg */
1692         tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
1693             ~(BMI_NUM_OF_DMAS_MASK | BMI_NUM_OF_EXTRA_DMAS_MASK);
1694         tmp |= (u32)(((open_dmas - 1) << BMI_NUM_OF_DMAS_SHIFT) |
1695                            (extra_open_dmas << BMI_EXTRA_NUM_OF_DMAS_SHIFT));
1696         iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
1697 
1698         /* update total num of DMA's with committed number of open DMAS,
1699          * and max uncommitted pool.
1700          */
1701         if (total_num_dmas) {
1702                 tmp = ioread32be(&bmi_rg->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK;
1703                 tmp |= (u32)(total_num_dmas - 1) << BMI_CFG2_DMAS_SHIFT;
1704                 iowrite32be(tmp, &bmi_rg->fmbm_cfg2);
1705         }
1706 
1707         return 0;
1708 }
1709 
1710 static int fman_config(struct fman *fman)
1711 {
1712         void __iomem *base_addr;
1713         int err;
1714 
1715         base_addr = fman->dts_params.base_addr;
1716 
1717         fman->state = kzalloc(sizeof(*fman->state), GFP_KERNEL);
1718         if (!fman->state)
1719                 goto err_fm_state;
1720 
1721         /* Allocate the FM driver's parameters structure */
1722         fman->cfg = kzalloc(sizeof(*fman->cfg), GFP_KERNEL);
1723         if (!fman->cfg)
1724                 goto err_fm_drv;
1725 
1726         /* Initialize MURAM block */
1727         fman->muram =
1728                 fman_muram_init(fman->dts_params.muram_res.start,
1729                                 resource_size(&fman->dts_params.muram_res));
1730         if (!fman->muram)
1731                 goto err_fm_soc_specific;
1732 
1733         /* Initialize FM parameters which will be kept by the driver */
1734         fman->state->fm_id = fman->dts_params.id;
1735         fman->state->fm_clk_freq = fman->dts_params.clk_freq;
1736         fman->state->qman_channel_base = fman->dts_params.qman_channel_base;
1737         fman->state->num_of_qman_channels =
1738                 fman->dts_params.num_of_qman_channels;
1739         fman->state->res = fman->dts_params.res;
1740         fman->exception_cb = fman_exceptions;
1741         fman->bus_error_cb = fman_bus_error;
1742         fman->fpm_regs = base_addr + FPM_OFFSET;
1743         fman->bmi_regs = base_addr + BMI_OFFSET;
1744         fman->qmi_regs = base_addr + QMI_OFFSET;
1745         fman->dma_regs = base_addr + DMA_OFFSET;
1746         fman->hwp_regs = base_addr + HWP_OFFSET;
1747         fman->kg_regs = base_addr + KG_OFFSET;
1748         fman->base_addr = base_addr;
1749 
1750         spin_lock_init(&fman->spinlock);
1751         fman_defconfig(fman->cfg);
1752 
1753         fman->state->extra_fifo_pool_size = 0;
1754         fman->state->exceptions = (EX_DMA_BUS_ERROR                 |
1755                                         EX_DMA_READ_ECC              |
1756                                         EX_DMA_SYSTEM_WRITE_ECC      |
1757                                         EX_DMA_FM_WRITE_ECC          |
1758                                         EX_FPM_STALL_ON_TASKS        |
1759                                         EX_FPM_SINGLE_ECC            |
1760                                         EX_FPM_DOUBLE_ECC            |
1761                                         EX_QMI_DEQ_FROM_UNKNOWN_PORTID |
1762                                         EX_BMI_LIST_RAM_ECC          |
1763                                         EX_BMI_STORAGE_PROFILE_ECC   |
1764                                         EX_BMI_STATISTICS_RAM_ECC    |
1765                                         EX_MURAM_ECC                 |
1766                                         EX_BMI_DISPATCH_RAM_ECC      |
1767                                         EX_QMI_DOUBLE_ECC            |
1768                                         EX_QMI_SINGLE_ECC);
1769 
1770         /* Read FMan revision for future use*/
1771         fman_get_revision(fman, &fman->state->rev_info);
1772 
1773         err = fill_soc_specific_params(fman->state);
1774         if (err)
1775                 goto err_fm_soc_specific;
1776 
1777         /* FM_AID_MODE_NO_TNUM_SW005 Errata workaround */
1778         if (fman->state->rev_info.major >= 6)
1779                 fman->cfg->dma_aid_mode = FMAN_DMA_AID_OUT_PORT_ID;
1780 
1781         fman->cfg->qmi_def_tnums_thresh = fman->state->qmi_def_tnums_thresh;
1782 
1783         fman->state->total_num_of_tasks =
1784         (u8)DFLT_TOTAL_NUM_OF_TASKS(fman->state->rev_info.major,
1785                                     fman->state->rev_info.minor,
1786                                     fman->state->bmi_max_num_of_tasks);
1787 
1788         if (fman->state->rev_info.major < 6) {
1789                 fman->cfg->dma_comm_qtsh_clr_emer =
1790                 (u8)DFLT_DMA_COMM_Q_LOW(fman->state->rev_info.major,
1791                                         fman->state->dma_thresh_max_commq);
1792 
1793                 fman->cfg->dma_comm_qtsh_asrt_emer =
1794                 (u8)DFLT_DMA_COMM_Q_HIGH(fman->state->rev_info.major,
1795                                          fman->state->dma_thresh_max_commq);
1796 
1797                 fman->cfg->dma_cam_num_of_entries =
1798                 DFLT_DMA_CAM_NUM_OF_ENTRIES(fman->state->rev_info.major);
1799 
1800                 fman->cfg->dma_read_buf_tsh_clr_emer =
1801                 DFLT_DMA_READ_INT_BUF_LOW(fman->state->dma_thresh_max_buf);
1802 
1803                 fman->cfg->dma_read_buf_tsh_asrt_emer =
1804                 DFLT_DMA_READ_INT_BUF_HIGH(fman->state->dma_thresh_max_buf);
1805 
1806                 fman->cfg->dma_write_buf_tsh_clr_emer =
1807                 DFLT_DMA_WRITE_INT_BUF_LOW(fman->state->dma_thresh_max_buf);
1808 
1809                 fman->cfg->dma_write_buf_tsh_asrt_emer =
1810                 DFLT_DMA_WRITE_INT_BUF_HIGH(fman->state->dma_thresh_max_buf);
1811 
1812                 fman->cfg->dma_axi_dbg_num_of_beats =
1813                 DFLT_AXI_DBG_NUM_OF_BEATS;
1814         }
1815 
1816         return 0;
1817 
1818 err_fm_soc_specific:
1819         kfree(fman->cfg);
1820 err_fm_drv:
1821         kfree(fman->state);
1822 err_fm_state:
1823         kfree(fman);
1824         return -EINVAL;
1825 }
1826 
1827 static int fman_reset(struct fman *fman)
1828 {
1829         u32 count;
1830         int err = 0;
1831 
1832         if (fman->state->rev_info.major < 6) {
1833                 iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc);
1834                 /* Wait for reset completion */
1835                 count = 100;
1836                 do {
1837                         udelay(1);
1838                 } while (((ioread32be(&fman->fpm_regs->fm_rstc)) &
1839                          FPM_RSTC_FM_RESET) && --count);
1840                 if (count == 0)
1841                         err = -EBUSY;
1842 
1843                 goto _return;
1844         } else {
1845 #ifdef CONFIG_PPC
1846                 struct device_node *guts_node;
1847                 struct ccsr_guts __iomem *guts_regs;
1848                 u32 devdisr2, reg;
1849 
1850                 /* Errata A007273 */
1851                 guts_node =
1852                         of_find_compatible_node(NULL, NULL,
1853                                                 "fsl,qoriq-device-config-2.0");
1854                 if (!guts_node) {
1855                         dev_err(fman->dev, "%s: Couldn't find guts node\n",
1856                                 __func__);
1857                         goto guts_node;
1858                 }
1859 
1860                 guts_regs = of_iomap(guts_node, 0);
1861                 if (!guts_regs) {
1862                         dev_err(fman->dev, "%s: Couldn't map %pOF regs\n",
1863                                 __func__, guts_node);
1864                         goto guts_regs;
1865                 }
1866 #define FMAN1_ALL_MACS_MASK     0xFCC00000
1867 #define FMAN2_ALL_MACS_MASK     0x000FCC00
1868                 /* Read current state */
1869                 devdisr2 = ioread32be(&guts_regs->devdisr2);
1870                 if (fman->dts_params.id == 0)
1871                         reg = devdisr2 & ~FMAN1_ALL_MACS_MASK;
1872                 else
1873                         reg = devdisr2 & ~FMAN2_ALL_MACS_MASK;
1874 
1875                 /* Enable all MACs */
1876                 iowrite32be(reg, &guts_regs->devdisr2);
1877 #endif
1878 
1879                 /* Perform FMan reset */
1880                 iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc);
1881 
1882                 /* Wait for reset completion */
1883                 count = 100;
1884                 do {
1885                         udelay(1);
1886                 } while (((ioread32be(&fman->fpm_regs->fm_rstc)) &
1887                          FPM_RSTC_FM_RESET) && --count);
1888                 if (count == 0) {
1889 #ifdef CONFIG_PPC
1890                         iounmap(guts_regs);
1891                         of_node_put(guts_node);
1892 #endif
1893                         err = -EBUSY;
1894                         goto _return;
1895                 }
1896 #ifdef CONFIG_PPC
1897 
1898                 /* Restore devdisr2 value */
1899                 iowrite32be(devdisr2, &guts_regs->devdisr2);
1900 
1901                 iounmap(guts_regs);
1902                 of_node_put(guts_node);
1903 #endif
1904 
1905                 goto _return;
1906 
1907 #ifdef CONFIG_PPC
1908 guts_regs:
1909                 of_node_put(guts_node);
1910 guts_node:
1911                 dev_dbg(fman->dev, "%s: Didn't perform FManV3 reset due to Errata A007273!\n",
1912                         __func__);
1913 #endif
1914         }
1915 _return:
1916         return err;
1917 }
1918 
1919 static int fman_init(struct fman *fman)
1920 {
1921         struct fman_cfg *cfg = NULL;
1922         int err = 0, i, count;
1923 
1924         if (is_init_done(fman->cfg))
1925                 return -EINVAL;
1926 
1927         fman->state->count1_micro_bit = FM_TIMESTAMP_1_USEC_BIT;
1928 
1929         cfg = fman->cfg;
1930 
1931         /* clear revision-dependent non existing exception */
1932         if (fman->state->rev_info.major < 6)
1933                 fman->state->exceptions &= ~FMAN_EX_BMI_DISPATCH_RAM_ECC;
1934 
1935         if (fman->state->rev_info.major >= 6)
1936                 fman->state->exceptions &= ~FMAN_EX_QMI_SINGLE_ECC;
1937 
1938         /* clear CPG */
1939         memset_io((void __iomem *)(fman->base_addr + CGP_OFFSET), 0,
1940                   fman->state->fm_port_num_of_cg);
1941 
1942         /* Save LIODN info before FMan reset
1943          * Skipping non-existent port 0 (i = 1)
1944          */
1945         for (i = 1; i < FMAN_LIODN_TBL; i++) {
1946                 u32 liodn_base;
1947 
1948                 fman->liodn_offset[i] =
1949                         ioread32be(&fman->bmi_regs->fmbm_spliodn[i - 1]);
1950                 liodn_base = ioread32be(&fman->dma_regs->fmdmplr[i / 2]);
1951                 if (i % 2) {
1952                         /* FMDM_PLR LSB holds LIODN base for odd ports */
1953                         liodn_base &= DMA_LIODN_BASE_MASK;
1954                 } else {
1955                         /* FMDM_PLR MSB holds LIODN base for even ports */
1956                         liodn_base >>= DMA_LIODN_SHIFT;
1957                         liodn_base &= DMA_LIODN_BASE_MASK;
1958                 }
1959                 fman->liodn_base[i] = liodn_base;
1960         }
1961 
1962         err = fman_reset(fman);
1963         if (err)
1964                 return err;
1965 
1966         if (ioread32be(&fman->qmi_regs->fmqm_gs) & QMI_GS_HALT_NOT_BUSY) {
1967                 resume(fman->fpm_regs);
1968                 /* Wait until QMI is not in halt not busy state */
1969                 count = 100;
1970                 do {
1971                         udelay(1);
1972                 } while (((ioread32be(&fman->qmi_regs->fmqm_gs)) &
1973                          QMI_GS_HALT_NOT_BUSY) && --count);
1974                 if (count == 0)
1975                         dev_warn(fman->dev, "%s: QMI is in halt not busy state\n",
1976                                  __func__);
1977         }
1978 
1979         if (clear_iram(fman) != 0)
1980                 return -EINVAL;
1981 
1982         cfg->exceptions = fman->state->exceptions;
1983 
1984         /* Init DMA Registers */
1985 
1986         err = dma_init(fman);
1987         if (err != 0) {
1988                 free_init_resources(fman);
1989                 return err;
1990         }
1991 
1992         /* Init FPM Registers */
1993         fpm_init(fman->fpm_regs, fman->cfg);
1994 
1995         /* define common resources */
1996         /* allocate MURAM for FIFO according to total size */
1997         fman->fifo_offset = fman_muram_alloc(fman->muram,
1998                                              fman->state->total_fifo_size);
1999         if (IS_ERR_VALUE(fman->fifo_offset)) {
2000                 free_init_resources(fman);
2001                 dev_err(fman->dev, "%s: MURAM alloc for BMI FIFO failed\n",
2002                         __func__);
2003                 return -ENOMEM;
2004         }
2005 
2006         cfg->fifo_base_addr = fman->fifo_offset;
2007         cfg->total_fifo_size = fman->state->total_fifo_size;
2008         cfg->total_num_of_tasks = fman->state->total_num_of_tasks;
2009         cfg->clk_freq = fman->state->fm_clk_freq;
2010 
2011         /* Init BMI Registers */
2012         bmi_init(fman->bmi_regs, fman->cfg);
2013 
2014         /* Init QMI Registers */
2015         qmi_init(fman->qmi_regs, fman->cfg);
2016 
2017         /* Init HW Parser */
2018         hwp_init(fman->hwp_regs);
2019 
2020         /* Init KeyGen */
2021         fman->keygen = keygen_init(fman->kg_regs);
2022         if (!fman->keygen)
2023                 return -EINVAL;
2024 
2025         err = enable(fman, cfg);
2026         if (err != 0)
2027                 return err;
2028 
2029         enable_time_stamp(fman);
2030 
2031         kfree(fman->cfg);
2032         fman->cfg = NULL;
2033 
2034         return 0;
2035 }
2036 
2037 static int fman_set_exception(struct fman *fman,
2038                               enum fman_exceptions exception, bool enable)
2039 {
2040         u32 bit_mask = 0;
2041 
2042         if (!is_init_done(fman->cfg))
2043                 return -EINVAL;
2044 
2045         bit_mask = get_exception_flag(exception);
2046         if (bit_mask) {
2047                 if (enable)
2048                         fman->state->exceptions |= bit_mask;
2049                 else
2050                         fman->state->exceptions &= ~bit_mask;
2051         } else {
2052                 dev_err(fman->dev, "%s: Undefined exception (%d)\n",
2053                         __func__, exception);
2054                 return -EINVAL;
2055         }
2056 
2057         return set_exception(fman, exception, enable);
2058 }
2059 
2060 /**
2061  * fman_register_intr
2062  * @fman:       A Pointer to FMan device
2063  * @mod:        Calling module
2064  * @mod_id:     Module id (if more than 1 exists, '0' if not)
2065  * @intr_type:  Interrupt type (error/normal) selection.
2066  * @f_isr:      The interrupt service routine.
2067  * @h_src_arg:  Argument to be passed to f_isr.
2068  *
2069  * Used to register an event handler to be processed by FMan
2070  *
2071  * Return: 0 on success; Error code otherwise.
2072  */
2073 void fman_register_intr(struct fman *fman, enum fman_event_modules module,
2074                         u8 mod_id, enum fman_intr_type intr_type,
2075                         void (*isr_cb)(void *src_arg), void *src_arg)
2076 {
2077         int event = 0;
2078 
2079         event = get_module_event(module, mod_id, intr_type);
2080         WARN_ON(event >= FMAN_EV_CNT);
2081 
2082         /* register in local FM structure */
2083         fman->intr_mng[event].isr_cb = isr_cb;
2084         fman->intr_mng[event].src_handle = src_arg;
2085 }
2086 EXPORT_SYMBOL(fman_register_intr);
2087 
2088 /**
2089  * fman_unregister_intr
2090  * @fman:       A Pointer to FMan device
2091  * @mod:        Calling module
2092  * @mod_id:     Module id (if more than 1 exists, '0' if not)
2093  * @intr_type:  Interrupt type (error/normal) selection.
2094  *
2095  * Used to unregister an event handler to be processed by FMan
2096  *
2097  * Return: 0 on success; Error code otherwise.
2098  */
2099 void fman_unregister_intr(struct fman *fman, enum fman_event_modules module,
2100                           u8 mod_id, enum fman_intr_type intr_type)
2101 {
2102         int event = 0;
2103 
2104         event = get_module_event(module, mod_id, intr_type);
2105         WARN_ON(event >= FMAN_EV_CNT);
2106 
2107         fman->intr_mng[event].isr_cb = NULL;
2108         fman->intr_mng[event].src_handle = NULL;
2109 }
2110 EXPORT_SYMBOL(fman_unregister_intr);
2111 
2112 /**
2113  * fman_set_port_params
2114  * @fman:               A Pointer to FMan device
2115  * @port_params:        Port parameters
2116  *
2117  * Used by FMan Port to pass parameters to the FMan
2118  *
2119  * Return: 0 on success; Error code otherwise.
2120  */
2121 int fman_set_port_params(struct fman *fman,
2122                          struct fman_port_init_params *port_params)
2123 {
2124         int err;
2125         unsigned long flags;
2126         u8 port_id = port_params->port_id, mac_id;
2127 
2128         spin_lock_irqsave(&fman->spinlock, flags);
2129 
2130         err = set_num_of_tasks(fman, port_params->port_id,
2131                                &port_params->num_of_tasks,
2132                                &port_params->num_of_extra_tasks);
2133         if (err)
2134                 goto return_err;
2135 
2136         /* TX Ports */
2137         if (port_params->port_type != FMAN_PORT_TYPE_RX) {
2138                 u32 enq_th, deq_th, reg;
2139 
2140                 /* update qmi ENQ/DEQ threshold */
2141                 fman->state->accumulated_num_of_deq_tnums +=
2142                         port_params->deq_pipeline_depth;
2143                 enq_th = (ioread32be(&fman->qmi_regs->fmqm_gc) &
2144                           QMI_CFG_ENQ_MASK) >> QMI_CFG_ENQ_SHIFT;
2145                 /* if enq_th is too big, we reduce it to the max value
2146                  * that is still 0
2147                  */
2148                 if (enq_th >= (fman->state->qmi_max_num_of_tnums -
2149                     fman->state->accumulated_num_of_deq_tnums)) {
2150                         enq_th =
2151                         fman->state->qmi_max_num_of_tnums -
2152                         fman->state->accumulated_num_of_deq_tnums - 1;
2153 
2154                         reg = ioread32be(&fman->qmi_regs->fmqm_gc);
2155                         reg &= ~QMI_CFG_ENQ_MASK;
2156                         reg |= (enq_th << QMI_CFG_ENQ_SHIFT);
2157                         iowrite32be(reg, &fman->qmi_regs->fmqm_gc);
2158                 }
2159 
2160                 deq_th = ioread32be(&fman->qmi_regs->fmqm_gc) &
2161                                     QMI_CFG_DEQ_MASK;
2162                 /* if deq_th is too small, we enlarge it to the min
2163                  * value that is still 0.
2164                  * depTh may not be larger than 63
2165                  * (fman->state->qmi_max_num_of_tnums-1).
2166                  */
2167                 if ((deq_th <= fman->state->accumulated_num_of_deq_tnums) &&
2168                     (deq_th < fman->state->qmi_max_num_of_tnums - 1)) {
2169                         deq_th = fman->state->accumulated_num_of_deq_tnums + 1;
2170                         reg = ioread32be(&fman->qmi_regs->fmqm_gc);
2171                         reg &= ~QMI_CFG_DEQ_MASK;
2172                         reg |= deq_th;
2173                         iowrite32be(reg, &fman->qmi_regs->fmqm_gc);
2174                 }
2175         }
2176 
2177         err = set_size_of_fifo(fman, port_params->port_id,
2178                                &port_params->size_of_fifo,
2179                                &port_params->extra_size_of_fifo);
2180         if (err)
2181                 goto return_err;
2182 
2183         err = set_num_of_open_dmas(fman, port_params->port_id,
2184                                    &port_params->num_of_open_dmas,
2185                                    &port_params->num_of_extra_open_dmas);
2186         if (err)
2187                 goto return_err;
2188 
2189         set_port_liodn(fman, port_id, fman->liodn_base[port_id],
2190                        fman->liodn_offset[port_id]);
2191 
2192         if (fman->state->rev_info.major < 6)
2193                 set_port_order_restoration(fman->fpm_regs, port_id);
2194 
2195         mac_id = hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id);
2196 
2197         if (port_params->max_frame_length >= fman->state->mac_mfl[mac_id]) {
2198                 fman->state->port_mfl[mac_id] = port_params->max_frame_length;
2199         } else {
2200                 dev_warn(fman->dev, "%s: Port (%d) max_frame_length is smaller than MAC (%d) current MTU\n",
2201                          __func__, port_id, mac_id);
2202                 err = -EINVAL;
2203                 goto return_err;
2204         }
2205 
2206         spin_unlock_irqrestore(&fman->spinlock, flags);
2207 
2208         return 0;
2209 
2210 return_err:
2211         spin_unlock_irqrestore(&fman->spinlock, flags);
2212         return err;
2213 }
2214 EXPORT_SYMBOL(fman_set_port_params);
2215 
2216 /**
2217  * fman_reset_mac
2218  * @fman:       A Pointer to FMan device
2219  * @mac_id:     MAC id to be reset
2220  *
2221  * Reset a specific MAC
2222  *
2223  * Return: 0 on success; Error code otherwise.
2224  */
2225 int fman_reset_mac(struct fman *fman, u8 mac_id)
2226 {
2227         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
2228         u32 msk, timeout = 100;
2229 
2230         if (fman->state->rev_info.major >= 6) {
2231                 dev_err(fman->dev, "%s: FMan MAC reset no available for FMan V3!\n",
2232                         __func__);
2233                 return -EINVAL;
2234         }
2235 
2236         /* Get the relevant bit mask */
2237         switch (mac_id) {
2238         case 0:
2239                 msk = FPM_RSTC_MAC0_RESET;
2240                 break;
2241         case 1:
2242                 msk = FPM_RSTC_MAC1_RESET;
2243                 break;
2244         case 2:
2245                 msk = FPM_RSTC_MAC2_RESET;
2246                 break;
2247         case 3:
2248                 msk = FPM_RSTC_MAC3_RESET;
2249                 break;
2250         case 4:
2251                 msk = FPM_RSTC_MAC4_RESET;
2252                 break;
2253         case 5:
2254                 msk = FPM_RSTC_MAC5_RESET;
2255                 break;
2256         case 6:
2257                 msk = FPM_RSTC_MAC6_RESET;
2258                 break;
2259         case 7:
2260                 msk = FPM_RSTC_MAC7_RESET;
2261                 break;
2262         case 8:
2263                 msk = FPM_RSTC_MAC8_RESET;
2264                 break;
2265         case 9:
2266                 msk = FPM_RSTC_MAC9_RESET;
2267                 break;
2268         default:
2269                 dev_warn(fman->dev, "%s: Illegal MAC Id [%d]\n",
2270                          __func__, mac_id);
2271                 return -EINVAL;
2272         }
2273 
2274         /* reset */
2275         iowrite32be(msk, &fpm_rg->fm_rstc);
2276         while ((ioread32be(&fpm_rg->fm_rstc) & msk) && --timeout)
2277                 udelay(10);
2278 
2279         if (!timeout)
2280                 return -EIO;
2281 
2282         return 0;
2283 }
2284 EXPORT_SYMBOL(fman_reset_mac);
2285 
2286 /**
2287  * fman_set_mac_max_frame
2288  * @fman:       A Pointer to FMan device
2289  * @mac_id:     MAC id
2290  * @mfl:        Maximum frame length
2291  *
2292  * Set maximum frame length of specific MAC in FMan driver
2293  *
2294  * Return: 0 on success; Error code otherwise.
2295  */
2296 int fman_set_mac_max_frame(struct fman *fman, u8 mac_id, u16 mfl)
2297 {
2298         /* if port is already initialized, check that MaxFrameLength is smaller
2299          * or equal to the port's max
2300          */
2301         if ((!fman->state->port_mfl[mac_id]) ||
2302             (mfl <= fman->state->port_mfl[mac_id])) {
2303                 fman->state->mac_mfl[mac_id] = mfl;
2304         } else {
2305                 dev_warn(fman->dev, "%s: MAC max_frame_length is larger than Port max_frame_length\n",
2306                          __func__);
2307                 return -EINVAL;
2308         }
2309         return 0;
2310 }
2311 EXPORT_SYMBOL(fman_set_mac_max_frame);
2312 
2313 /**
2314  * fman_get_clock_freq
2315  * @fman:       A Pointer to FMan device
2316  *
2317  * Get FMan clock frequency
2318  *
2319  * Return: FMan clock frequency
2320  */
2321 u16 fman_get_clock_freq(struct fman *fman)
2322 {
2323         return fman->state->fm_clk_freq;
2324 }
2325 
2326 /**
2327  * fman_get_bmi_max_fifo_size
2328  * @fman:       A Pointer to FMan device
2329  *
2330  * Get FMan maximum FIFO size
2331  *
2332  * Return: FMan Maximum FIFO size
2333  */
2334 u32 fman_get_bmi_max_fifo_size(struct fman *fman)
2335 {
2336         return fman->state->bmi_max_fifo_size;
2337 }
2338 EXPORT_SYMBOL(fman_get_bmi_max_fifo_size);
2339 
2340 /**
2341  * fman_get_revision
2342  * @fman                - Pointer to the FMan module
2343  * @rev_info            - A structure of revision information parameters.
2344  *
2345  * Returns the FM revision
2346  *
2347  * Allowed only following fman_init().
2348  *
2349  * Return: 0 on success; Error code otherwise.
2350  */
2351 void fman_get_revision(struct fman *fman, struct fman_rev_info *rev_info)
2352 {
2353         u32 tmp;
2354 
2355         tmp = ioread32be(&fman->fpm_regs->fm_ip_rev_1);
2356         rev_info->major = (u8)((tmp & FPM_REV1_MAJOR_MASK) >>
2357                                 FPM_REV1_MAJOR_SHIFT);
2358         rev_info->minor = tmp & FPM_REV1_MINOR_MASK;
2359 }
2360 EXPORT_SYMBOL(fman_get_revision);
2361 
2362 /**
2363  * fman_get_qman_channel_id
2364  * @fman:       A Pointer to FMan device
2365  * @port_id:    Port id
2366  *
2367  * Get QMan channel ID associated to the Port id
2368  *
2369  * Return: QMan channel ID
2370  */
2371 u32 fman_get_qman_channel_id(struct fman *fman, u32 port_id)
2372 {
2373         int i;
2374 
2375         if (fman->state->rev_info.major >= 6) {
2376                 static const u32 port_ids[] = {
2377                         0x30, 0x31, 0x28, 0x29, 0x2a, 0x2b,
2378                         0x2c, 0x2d, 0x2, 0x3, 0x4, 0x5, 0x7, 0x7
2379                 };
2380 
2381                 for (i = 0; i < fman->state->num_of_qman_channels; i++) {
2382                         if (port_ids[i] == port_id)
2383                                 break;
2384                 }
2385         } else {
2386                 static const u32 port_ids[] = {
2387                         0x30, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x1,
2388                         0x2, 0x3, 0x4, 0x5, 0x7, 0x7
2389                 };
2390 
2391                 for (i = 0; i < fman->state->num_of_qman_channels; i++) {
2392                         if (port_ids[i] == port_id)
2393                                 break;
2394                 }
2395         }
2396 
2397         if (i == fman->state->num_of_qman_channels)
2398                 return 0;
2399 
2400         return fman->state->qman_channel_base + i;
2401 }
2402 EXPORT_SYMBOL(fman_get_qman_channel_id);
2403 
2404 /**
2405  * fman_get_mem_region
2406  * @fman:       A Pointer to FMan device
2407  *
2408  * Get FMan memory region
2409  *
2410  * Return: A structure with FMan memory region information
2411  */
2412 struct resource *fman_get_mem_region(struct fman *fman)
2413 {
2414         return fman->state->res;
2415 }
2416 EXPORT_SYMBOL(fman_get_mem_region);
2417 
2418 /* Bootargs defines */
2419 /* Extra headroom for RX buffers - Default, min and max */
2420 #define FSL_FM_RX_EXTRA_HEADROOM        64
2421 #define FSL_FM_RX_EXTRA_HEADROOM_MIN    16
2422 #define FSL_FM_RX_EXTRA_HEADROOM_MAX    384
2423 
2424 /* Maximum frame length */
2425 #define FSL_FM_MAX_FRAME_SIZE                   1522
2426 #define FSL_FM_MAX_POSSIBLE_FRAME_SIZE          9600
2427 #define FSL_FM_MIN_POSSIBLE_FRAME_SIZE          64
2428 
2429 /* Extra headroom for Rx buffers.
2430  * FMan is instructed to allocate, on the Rx path, this amount of
2431  * space at the beginning of a data buffer, beside the DPA private
2432  * data area and the IC fields.
2433  * Does not impact Tx buffer layout.
2434  * Configurable from bootargs. 64 by default, it's needed on
2435  * particular forwarding scenarios that add extra headers to the
2436  * forwarded frame.
2437  */
2438 static int fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM;
2439 module_param(fsl_fm_rx_extra_headroom, int, 0);
2440 MODULE_PARM_DESC(fsl_fm_rx_extra_headroom, "Extra headroom for Rx buffers");
2441 
2442 /* Max frame size, across all interfaces.
2443  * Configurable from bootargs, to avoid allocating oversized (socket)
2444  * buffers when not using jumbo frames.
2445  * Must be large enough to accommodate the network MTU, but small enough
2446  * to avoid wasting skb memory.
2447  */
2448 static int fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE;
2449 module_param(fsl_fm_max_frm, int, 0);
2450 MODULE_PARM_DESC(fsl_fm_max_frm, "Maximum frame size, across all interfaces");
2451 
2452 /**
2453  * fman_get_max_frm
2454  *
2455  * Return: Max frame length configured in the FM driver
2456  */
2457 u16 fman_get_max_frm(void)
2458 {
2459         static bool fm_check_mfl;
2460 
2461         if (!fm_check_mfl) {
2462                 if (fsl_fm_max_frm > FSL_FM_MAX_POSSIBLE_FRAME_SIZE ||
2463                     fsl_fm_max_frm < FSL_FM_MIN_POSSIBLE_FRAME_SIZE) {
2464                         pr_warn("Invalid fsl_fm_max_frm value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n",
2465                                 fsl_fm_max_frm,
2466                                 FSL_FM_MIN_POSSIBLE_FRAME_SIZE,
2467                                 FSL_FM_MAX_POSSIBLE_FRAME_SIZE,
2468                                 FSL_FM_MAX_FRAME_SIZE);
2469                         fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE;
2470                 }
2471                 fm_check_mfl = true;
2472         }
2473 
2474         return fsl_fm_max_frm;
2475 }
2476 EXPORT_SYMBOL(fman_get_max_frm);
2477 
2478 /**
2479  * fman_get_rx_extra_headroom
2480  *
2481  * Return: Extra headroom size configured in the FM driver
2482  */
2483 int fman_get_rx_extra_headroom(void)
2484 {
2485         static bool fm_check_rx_extra_headroom;
2486 
2487         if (!fm_check_rx_extra_headroom) {
2488                 if (fsl_fm_rx_extra_headroom > FSL_FM_RX_EXTRA_HEADROOM_MAX ||
2489                     fsl_fm_rx_extra_headroom < FSL_FM_RX_EXTRA_HEADROOM_MIN) {
2490                         pr_warn("Invalid fsl_fm_rx_extra_headroom value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n",
2491                                 fsl_fm_rx_extra_headroom,
2492                                 FSL_FM_RX_EXTRA_HEADROOM_MIN,
2493                                 FSL_FM_RX_EXTRA_HEADROOM_MAX,
2494                                 FSL_FM_RX_EXTRA_HEADROOM);
2495                         fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM;
2496                 }
2497 
2498                 fm_check_rx_extra_headroom = true;
2499                 fsl_fm_rx_extra_headroom = ALIGN(fsl_fm_rx_extra_headroom, 16);
2500         }
2501 
2502         return fsl_fm_rx_extra_headroom;
2503 }
2504 EXPORT_SYMBOL(fman_get_rx_extra_headroom);
2505 
2506 /**
2507  * fman_bind
2508  * @dev:        FMan OF device pointer
2509  *
2510  * Bind to a specific FMan device.
2511  *
2512  * Allowed only after the port was created.
2513  *
2514  * Return: A pointer to the FMan device
2515  */
2516 struct fman *fman_bind(struct device *fm_dev)
2517 {
2518         return (struct fman *)(dev_get_drvdata(get_device(fm_dev)));
2519 }
2520 EXPORT_SYMBOL(fman_bind);
2521 
2522 #ifdef CONFIG_DPAA_ERRATUM_A050385
2523 bool fman_has_errata_a050385(void)
2524 {
2525         return fman_has_err_a050385;
2526 }
2527 EXPORT_SYMBOL(fman_has_errata_a050385);
2528 #endif
2529 
2530 static irqreturn_t fman_err_irq(int irq, void *handle)
2531 {
2532         struct fman *fman = (struct fman *)handle;
2533         u32 pending;
2534         struct fman_fpm_regs __iomem *fpm_rg;
2535         irqreturn_t single_ret, ret = IRQ_NONE;
2536 
2537         if (!is_init_done(fman->cfg))
2538                 return IRQ_NONE;
2539 
2540         fpm_rg = fman->fpm_regs;
2541 
2542         /* error interrupts */
2543         pending = ioread32be(&fpm_rg->fm_epi);
2544         if (!pending)
2545                 return IRQ_NONE;
2546 
2547         if (pending & ERR_INTR_EN_BMI) {
2548                 single_ret = bmi_err_event(fman);
2549                 if (single_ret == IRQ_HANDLED)
2550                         ret = IRQ_HANDLED;
2551         }
2552         if (pending & ERR_INTR_EN_QMI) {
2553                 single_ret = qmi_err_event(fman);
2554                 if (single_ret == IRQ_HANDLED)
2555                         ret = IRQ_HANDLED;
2556         }
2557         if (pending & ERR_INTR_EN_FPM) {
2558                 single_ret = fpm_err_event(fman);
2559                 if (single_ret == IRQ_HANDLED)
2560                         ret = IRQ_HANDLED;
2561         }
2562         if (pending & ERR_INTR_EN_DMA) {
2563                 single_ret = dma_err_event(fman);
2564                 if (single_ret == IRQ_HANDLED)
2565                         ret = IRQ_HANDLED;
2566         }
2567         if (pending & ERR_INTR_EN_MURAM) {
2568                 single_ret = muram_err_intr(fman);
2569                 if (single_ret == IRQ_HANDLED)
2570                         ret = IRQ_HANDLED;
2571         }
2572 
2573         /* MAC error interrupts */
2574         if (pending & ERR_INTR_EN_MAC0) {
2575                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 0);
2576                 if (single_ret == IRQ_HANDLED)
2577                         ret = IRQ_HANDLED;
2578         }
2579         if (pending & ERR_INTR_EN_MAC1) {
2580                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 1);
2581                 if (single_ret == IRQ_HANDLED)
2582                         ret = IRQ_HANDLED;
2583         }
2584         if (pending & ERR_INTR_EN_MAC2) {
2585                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 2);
2586                 if (single_ret == IRQ_HANDLED)
2587                         ret = IRQ_HANDLED;
2588         }
2589         if (pending & ERR_INTR_EN_MAC3) {
2590                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 3);
2591                 if (single_ret == IRQ_HANDLED)
2592                         ret = IRQ_HANDLED;
2593         }
2594         if (pending & ERR_INTR_EN_MAC4) {
2595                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 4);
2596                 if (single_ret == IRQ_HANDLED)
2597                         ret = IRQ_HANDLED;
2598         }
2599         if (pending & ERR_INTR_EN_MAC5) {
2600                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 5);
2601                 if (single_ret == IRQ_HANDLED)
2602                         ret = IRQ_HANDLED;
2603         }
2604         if (pending & ERR_INTR_EN_MAC6) {
2605                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 6);
2606                 if (single_ret == IRQ_HANDLED)
2607                         ret = IRQ_HANDLED;
2608         }
2609         if (pending & ERR_INTR_EN_MAC7) {
2610                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 7);
2611                 if (single_ret == IRQ_HANDLED)
2612                         ret = IRQ_HANDLED;
2613         }
2614         if (pending & ERR_INTR_EN_MAC8) {
2615                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 8);
2616                 if (single_ret == IRQ_HANDLED)
2617                         ret = IRQ_HANDLED;
2618         }
2619         if (pending & ERR_INTR_EN_MAC9) {
2620                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 9);
2621                 if (single_ret == IRQ_HANDLED)
2622                         ret = IRQ_HANDLED;
2623         }
2624 
2625         return ret;
2626 }
2627 
2628 static irqreturn_t fman_irq(int irq, void *handle)
2629 {
2630         struct fman *fman = (struct fman *)handle;
2631         u32 pending;
2632         struct fman_fpm_regs __iomem *fpm_rg;
2633         irqreturn_t single_ret, ret = IRQ_NONE;
2634 
2635         if (!is_init_done(fman->cfg))
2636                 return IRQ_NONE;
2637 
2638         fpm_rg = fman->fpm_regs;
2639 
2640         /* normal interrupts */
2641         pending = ioread32be(&fpm_rg->fm_npi);
2642         if (!pending)
2643                 return IRQ_NONE;
2644 
2645         if (pending & INTR_EN_QMI) {
2646                 single_ret = qmi_event(fman);
2647                 if (single_ret == IRQ_HANDLED)
2648                         ret = IRQ_HANDLED;
2649         }
2650 
2651         /* MAC interrupts */
2652         if (pending & INTR_EN_MAC0) {
2653                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 0);
2654                 if (single_ret == IRQ_HANDLED)
2655                         ret = IRQ_HANDLED;
2656         }
2657         if (pending & INTR_EN_MAC1) {
2658                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 1);
2659                 if (single_ret == IRQ_HANDLED)
2660                         ret = IRQ_HANDLED;
2661         }
2662         if (pending & INTR_EN_MAC2) {
2663                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 2);
2664                 if (single_ret == IRQ_HANDLED)
2665                         ret = IRQ_HANDLED;
2666         }
2667         if (pending & INTR_EN_MAC3) {
2668                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 3);
2669                 if (single_ret == IRQ_HANDLED)
2670                         ret = IRQ_HANDLED;
2671         }
2672         if (pending & INTR_EN_MAC4) {
2673                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 4);
2674                 if (single_ret == IRQ_HANDLED)
2675                         ret = IRQ_HANDLED;
2676         }
2677         if (pending & INTR_EN_MAC5) {
2678                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 5);
2679                 if (single_ret == IRQ_HANDLED)
2680                         ret = IRQ_HANDLED;
2681         }
2682         if (pending & INTR_EN_MAC6) {
2683                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 6);
2684                 if (single_ret == IRQ_HANDLED)
2685                         ret = IRQ_HANDLED;
2686         }
2687         if (pending & INTR_EN_MAC7) {
2688                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 7);
2689                 if (single_ret == IRQ_HANDLED)
2690                         ret = IRQ_HANDLED;
2691         }
2692         if (pending & INTR_EN_MAC8) {
2693                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 8);
2694                 if (single_ret == IRQ_HANDLED)
2695                         ret = IRQ_HANDLED;
2696         }
2697         if (pending & INTR_EN_MAC9) {
2698                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 9);
2699                 if (single_ret == IRQ_HANDLED)
2700                         ret = IRQ_HANDLED;
2701         }
2702 
2703         return ret;
2704 }
2705 
2706 static const struct of_device_id fman_muram_match[] = {
2707         {
2708                 .compatible = "fsl,fman-muram"},
2709         {}
2710 };
2711 MODULE_DEVICE_TABLE(of, fman_muram_match);
2712 
2713 static struct fman *read_dts_node(struct platform_device *of_dev)
2714 {
2715         struct fman *fman;
2716         struct device_node *fm_node, *muram_node;
2717         struct resource *res;
2718         u32 val, range[2];
2719         int err, irq;
2720         struct clk *clk;
2721         u32 clk_rate;
2722         phys_addr_t phys_base_addr;
2723         resource_size_t mem_size;
2724 
2725         fman = kzalloc(sizeof(*fman), GFP_KERNEL);
2726         if (!fman)
2727                 return NULL;
2728 
2729         fm_node = of_node_get(of_dev->dev.of_node);
2730 
2731         err = of_property_read_u32(fm_node, "cell-index", &val);
2732         if (err) {
2733                 dev_err(&of_dev->dev, "%s: failed to read cell-index for %pOF\n",
2734                         __func__, fm_node);
2735                 goto fman_node_put;
2736         }
2737         fman->dts_params.id = (u8)val;
2738 
2739         /* Get the FM interrupt */
2740         res = platform_get_resource(of_dev, IORESOURCE_IRQ, 0);
2741         if (!res) {
2742                 dev_err(&of_dev->dev, "%s: Can't get FMan IRQ resource\n",
2743                         __func__);
2744                 goto fman_node_put;
2745         }
2746         irq = res->start;
2747 
2748         /* Get the FM error interrupt */
2749         res = platform_get_resource(of_dev, IORESOURCE_IRQ, 1);
2750         if (!res) {
2751                 dev_err(&of_dev->dev, "%s: Can't get FMan Error IRQ resource\n",
2752                         __func__);
2753                 goto fman_node_put;
2754         }
2755         fman->dts_params.err_irq = res->start;
2756 
2757         /* Get the FM address */
2758         res = platform_get_resource(of_dev, IORESOURCE_MEM, 0);
2759         if (!res) {
2760                 dev_err(&of_dev->dev, "%s: Can't get FMan memory resource\n",
2761                         __func__);
2762                 goto fman_node_put;
2763         }
2764 
2765         phys_base_addr = res->start;
2766         mem_size = resource_size(res);
2767 
2768         clk = of_clk_get(fm_node, 0);
2769         if (IS_ERR(clk)) {
2770                 dev_err(&of_dev->dev, "%s: Failed to get FM%d clock structure\n",
2771                         __func__, fman->dts_params.id);
2772                 goto fman_node_put;
2773         }
2774 
2775         clk_rate = clk_get_rate(clk);
2776         if (!clk_rate) {
2777                 dev_err(&of_dev->dev, "%s: Failed to determine FM%d clock rate\n",
2778                         __func__, fman->dts_params.id);
2779                 goto fman_node_put;
2780         }
2781         /* Rounding to MHz */
2782         fman->dts_params.clk_freq = DIV_ROUND_UP(clk_rate, 1000000);
2783 
2784         err = of_property_read_u32_array(fm_node, "fsl,qman-channel-range",
2785                                          &range[0], 2);
2786         if (err) {
2787                 dev_err(&of_dev->dev, "%s: failed to read fsl,qman-channel-range for %pOF\n",
2788                         __func__, fm_node);
2789                 goto fman_node_put;
2790         }
2791         fman->dts_params.qman_channel_base = range[0];
2792         fman->dts_params.num_of_qman_channels = range[1];
2793 
2794         /* Get the MURAM base address and size */
2795         muram_node = of_find_matching_node(fm_node, fman_muram_match);
2796         if (!muram_node) {
2797                 dev_err(&of_dev->dev, "%s: could not find MURAM node\n",
2798                         __func__);
2799                 goto fman_free;
2800         }
2801 
2802         err = of_address_to_resource(muram_node, 0,
2803                                      &fman->dts_params.muram_res);
2804         if (err) {
2805                 of_node_put(muram_node);
2806                 dev_err(&of_dev->dev, "%s: of_address_to_resource() = %d\n",
2807                         __func__, err);
2808                 goto fman_free;
2809         }
2810 
2811         of_node_put(muram_node);
2812 
2813         err = devm_request_irq(&of_dev->dev, irq, fman_irq, IRQF_SHARED,
2814                                "fman", fman);
2815         if (err < 0) {
2816                 dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n",
2817                         __func__, irq, err);
2818                 goto fman_free;
2819         }
2820 
2821         if (fman->dts_params.err_irq != 0) {
2822                 err = devm_request_irq(&of_dev->dev, fman->dts_params.err_irq,
2823                                        fman_err_irq, IRQF_SHARED,
2824                                        "fman-err", fman);
2825                 if (err < 0) {
2826                         dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n",
2827                                 __func__, fman->dts_params.err_irq, err);
2828                         goto fman_free;
2829                 }
2830         }
2831 
2832         fman->dts_params.res =
2833                 devm_request_mem_region(&of_dev->dev, phys_base_addr,
2834                                         mem_size, "fman");
2835         if (!fman->dts_params.res) {
2836                 dev_err(&of_dev->dev, "%s: request_mem_region() failed\n",
2837                         __func__);
2838                 goto fman_free;
2839         }
2840 
2841         fman->dts_params.base_addr =
2842                 devm_ioremap(&of_dev->dev, phys_base_addr, mem_size);
2843         if (!fman->dts_params.base_addr) {
2844                 dev_err(&of_dev->dev, "%s: devm_ioremap() failed\n", __func__);
2845                 goto fman_free;
2846         }
2847 
2848         fman->dev = &of_dev->dev;
2849 
2850         err = of_platform_populate(fm_node, NULL, NULL, &of_dev->dev);
2851         if (err) {
2852                 dev_err(&of_dev->dev, "%s: of_platform_populate() failed\n",
2853                         __func__);
2854                 goto fman_free;
2855         }
2856 
2857 #ifdef CONFIG_DPAA_ERRATUM_A050385
2858         fman_has_err_a050385 =
2859                 of_property_read_bool(fm_node, "fsl,erratum-a050385");
2860 #endif
2861 
2862         return fman;
2863 
2864 fman_node_put:
2865         of_node_put(fm_node);
2866 fman_free:
2867         kfree(fman);
2868         return NULL;
2869 }
2870 
2871 static int fman_probe(struct platform_device *of_dev)
2872 {
2873         struct fman *fman;
2874         struct device *dev;
2875         int err;
2876 
2877         dev = &of_dev->dev;
2878 
2879         fman = read_dts_node(of_dev);
2880         if (!fman)
2881                 return -EIO;
2882 
2883         err = fman_config(fman);
2884         if (err) {
2885                 dev_err(dev, "%s: FMan config failed\n", __func__);
2886                 return -EINVAL;
2887         }
2888 
2889         if (fman_init(fman) != 0) {
2890                 dev_err(dev, "%s: FMan init failed\n", __func__);
2891                 return -EINVAL;
2892         }
2893 
2894         if (fman->dts_params.err_irq == 0) {
2895                 fman_set_exception(fman, FMAN_EX_DMA_BUS_ERROR, false);
2896                 fman_set_exception(fman, FMAN_EX_DMA_READ_ECC, false);
2897                 fman_set_exception(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC, false);
2898                 fman_set_exception(fman, FMAN_EX_DMA_FM_WRITE_ECC, false);
2899                 fman_set_exception(fman, FMAN_EX_DMA_SINGLE_PORT_ECC, false);
2900                 fman_set_exception(fman, FMAN_EX_FPM_STALL_ON_TASKS, false);
2901                 fman_set_exception(fman, FMAN_EX_FPM_SINGLE_ECC, false);
2902                 fman_set_exception(fman, FMAN_EX_FPM_DOUBLE_ECC, false);
2903                 fman_set_exception(fman, FMAN_EX_QMI_SINGLE_ECC, false);
2904                 fman_set_exception(fman, FMAN_EX_QMI_DOUBLE_ECC, false);
2905                 fman_set_exception(fman,
2906                                    FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID, false);
2907                 fman_set_exception(fman, FMAN_EX_BMI_LIST_RAM_ECC, false);
2908                 fman_set_exception(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC,
2909                                    false);
2910                 fman_set_exception(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC, false);
2911                 fman_set_exception(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC, false);
2912         }
2913 
2914         dev_set_drvdata(dev, fman);
2915 
2916         dev_dbg(dev, "FMan%d probed\n", fman->dts_params.id);
2917 
2918         return 0;
2919 }
2920 
2921 static const struct of_device_id fman_match[] = {
2922         {
2923                 .compatible = "fsl,fman"},
2924         {}
2925 };
2926 
2927 MODULE_DEVICE_TABLE(of, fman_match);
2928 
2929 static struct platform_driver fman_driver = {
2930         .driver = {
2931                 .name = "fsl-fman",
2932                 .of_match_table = fman_match,
2933         },
2934         .probe = fman_probe,
2935 };
2936 
2937 static int __init fman_load(void)
2938 {
2939         int err;
2940 
2941         pr_debug("FSL DPAA FMan driver\n");
2942 
2943         err = platform_driver_register(&fman_driver);
2944         if (err < 0)
2945                 pr_err("Error, platform_driver_register() = %d\n", err);
2946 
2947         return err;
2948 }
2949 module_init(fman_load);
2950 
2951 static void __exit fman_unload(void)
2952 {
2953         platform_driver_unregister(&fman_driver);
2954 }
2955 module_exit(fman_unload);
2956 
2957 MODULE_LICENSE("Dual BSD/GPL");
2958 MODULE_DESCRIPTION("Freescale DPAA Frame Manager driver");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/freescale/fman/fman.c

DEFINITIONS
