root/drivers/net/ethernet/smsc/smsc911x.h

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INCLUDED FROM


   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /***************************************************************************
   3  *
   4  * Copyright (C) 2004-2008 SMSC
   5  * Copyright (C) 2005-2008 ARM
   6  *
   7  ***************************************************************************/
   8 #ifndef __SMSC911X_H__
   9 #define __SMSC911X_H__
  10 
  11 /*Chip ID*/
  12 #define LAN9115 0x01150000
  13 #define LAN9116 0x01160000
  14 #define LAN9117 0x01170000
  15 #define LAN9118 0x01180000
  16 #define LAN9215 0x115A0000
  17 #define LAN9216 0x116A0000
  18 #define LAN9217 0x117A0000
  19 #define LAN9218 0x118A0000
  20 #define LAN9210 0x92100000
  21 #define LAN9211 0x92110000
  22 #define LAN9220 0x92200000
  23 #define LAN9221 0x92210000
  24 #define LAN9250 0x92500000
  25 #define LAN89218        0x218A0000
  26 
  27 #define TX_FIFO_LOW_THRESHOLD   ((u32)1600)
  28 #define SMSC911X_EEPROM_SIZE    ((u32)128)
  29 #define USE_DEBUG               0
  30 
  31 /* This is the maximum number of packets to be received every
  32  * NAPI poll */
  33 #define SMSC_NAPI_WEIGHT        16
  34 
  35 /* implements a PHY loopback test at initialisation time, to ensure a packet
  36  * can be successfully looped back */
  37 #define USE_PHY_WORK_AROUND
  38 
  39 #if USE_DEBUG >= 1
  40 #define SMSC_WARN(pdata, nlevel, fmt, args...)                  \
  41         netif_warn(pdata, nlevel, (pdata)->dev,                 \
  42                    "%s: " fmt "\n", __func__, ##args)
  43 #else
  44 #define SMSC_WARN(pdata, nlevel, fmt, args...)                  \
  45         no_printk(fmt "\n", ##args)
  46 #endif
  47 
  48 #if USE_DEBUG >= 2
  49 #define SMSC_TRACE(pdata, nlevel, fmt, args...)                 \
  50         netif_info(pdata, nlevel, pdata->dev, fmt "\n", ##args)
  51 #else
  52 #define SMSC_TRACE(pdata, nlevel, fmt, args...)                 \
  53         no_printk(fmt "\n", ##args)
  54 #endif
  55 
  56 #ifdef CONFIG_DEBUG_SPINLOCK
  57 #define SMSC_ASSERT_MAC_LOCK(pdata) \
  58                 lockdep_assert_held(&pdata->mac_lock)
  59 #else
  60 #define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0)
  61 #endif                          /* CONFIG_DEBUG_SPINLOCK */
  62 
  63 /* SMSC911x registers and bitfields */
  64 #define RX_DATA_FIFO                    0x00
  65 
  66 #define TX_DATA_FIFO                    0x20
  67 #define TX_CMD_A_ON_COMP_               0x80000000
  68 #define TX_CMD_A_BUF_END_ALGN_          0x03000000
  69 #define TX_CMD_A_4_BYTE_ALGN_           0x00000000
  70 #define TX_CMD_A_16_BYTE_ALGN_          0x01000000
  71 #define TX_CMD_A_32_BYTE_ALGN_          0x02000000
  72 #define TX_CMD_A_DATA_OFFSET_           0x001F0000
  73 #define TX_CMD_A_FIRST_SEG_             0x00002000
  74 #define TX_CMD_A_LAST_SEG_              0x00001000
  75 #define TX_CMD_A_BUF_SIZE_              0x000007FF
  76 #define TX_CMD_B_PKT_TAG_               0xFFFF0000
  77 #define TX_CMD_B_ADD_CRC_DISABLE_       0x00002000
  78 #define TX_CMD_B_DISABLE_PADDING_       0x00001000
  79 #define TX_CMD_B_PKT_BYTE_LENGTH_       0x000007FF
  80 
  81 #define RX_STATUS_FIFO                  0x40
  82 #define RX_STS_ES_                      0x00008000
  83 #define RX_STS_LENGTH_ERR_              0x00001000
  84 #define RX_STS_MCAST_                   0x00000400
  85 #define RX_STS_FRAME_TYPE_              0x00000020
  86 #define RX_STS_CRC_ERR_                 0x00000002
  87 
  88 #define RX_STATUS_FIFO_PEEK             0x44
  89 
  90 #define TX_STATUS_FIFO                  0x48
  91 #define TX_STS_ES_                      0x00008000
  92 #define TX_STS_LOST_CARRIER_            0x00000800
  93 #define TX_STS_NO_CARRIER_              0x00000400
  94 #define TX_STS_LATE_COL_                0x00000200
  95 #define TX_STS_EXCESS_COL_              0x00000100
  96 
  97 #define TX_STATUS_FIFO_PEEK             0x4C
  98 
  99 #define ID_REV                          0x50
 100 #define ID_REV_CHIP_ID_                 0xFFFF0000
 101 #define ID_REV_REV_ID_                  0x0000FFFF
 102 
 103 #define INT_CFG                         0x54
 104 #define INT_CFG_INT_DEAS_               0xFF000000
 105 #define INT_CFG_INT_DEAS_CLR_           0x00004000
 106 #define INT_CFG_INT_DEAS_STS_           0x00002000
 107 #define INT_CFG_IRQ_INT_                0x00001000
 108 #define INT_CFG_IRQ_EN_                 0x00000100
 109 #define INT_CFG_IRQ_POL_                0x00000010
 110 #define INT_CFG_IRQ_TYPE_               0x00000001
 111 
 112 #define INT_STS                         0x58
 113 #define INT_STS_SW_INT_                 0x80000000
 114 #define INT_STS_TXSTOP_INT_             0x02000000
 115 #define INT_STS_RXSTOP_INT_             0x01000000
 116 #define INT_STS_RXDFH_INT_              0x00800000
 117 #define INT_STS_RXDF_INT_               0x00400000
 118 #define INT_STS_TX_IOC_                 0x00200000
 119 #define INT_STS_RXD_INT_                0x00100000
 120 #define INT_STS_GPT_INT_                0x00080000
 121 #define INT_STS_PHY_INT_                0x00040000
 122 #define INT_STS_PME_INT_                0x00020000
 123 #define INT_STS_TXSO_                   0x00010000
 124 #define INT_STS_RWT_                    0x00008000
 125 #define INT_STS_RXE_                    0x00004000
 126 #define INT_STS_TXE_                    0x00002000
 127 #define INT_STS_TDFU_                   0x00000800
 128 #define INT_STS_TDFO_                   0x00000400
 129 #define INT_STS_TDFA_                   0x00000200
 130 #define INT_STS_TSFF_                   0x00000100
 131 #define INT_STS_TSFL_                   0x00000080
 132 #define INT_STS_RXDF_                   0x00000040
 133 #define INT_STS_RDFL_                   0x00000020
 134 #define INT_STS_RSFF_                   0x00000010
 135 #define INT_STS_RSFL_                   0x00000008
 136 #define INT_STS_GPIO2_INT_              0x00000004
 137 #define INT_STS_GPIO1_INT_              0x00000002
 138 #define INT_STS_GPIO0_INT_              0x00000001
 139 
 140 #define INT_EN                          0x5C
 141 #define INT_EN_SW_INT_EN_               0x80000000
 142 #define INT_EN_TXSTOP_INT_EN_           0x02000000
 143 #define INT_EN_RXSTOP_INT_EN_           0x01000000
 144 #define INT_EN_RXDFH_INT_EN_            0x00800000
 145 #define INT_EN_TIOC_INT_EN_             0x00200000
 146 #define INT_EN_RXD_INT_EN_              0x00100000
 147 #define INT_EN_GPT_INT_EN_              0x00080000
 148 #define INT_EN_PHY_INT_EN_              0x00040000
 149 #define INT_EN_PME_INT_EN_              0x00020000
 150 #define INT_EN_TXSO_EN_                 0x00010000
 151 #define INT_EN_RWT_EN_                  0x00008000
 152 #define INT_EN_RXE_EN_                  0x00004000
 153 #define INT_EN_TXE_EN_                  0x00002000
 154 #define INT_EN_TDFU_EN_                 0x00000800
 155 #define INT_EN_TDFO_EN_                 0x00000400
 156 #define INT_EN_TDFA_EN_                 0x00000200
 157 #define INT_EN_TSFF_EN_                 0x00000100
 158 #define INT_EN_TSFL_EN_                 0x00000080
 159 #define INT_EN_RXDF_EN_                 0x00000040
 160 #define INT_EN_RDFL_EN_                 0x00000020
 161 #define INT_EN_RSFF_EN_                 0x00000010
 162 #define INT_EN_RSFL_EN_                 0x00000008
 163 #define INT_EN_GPIO2_INT_               0x00000004
 164 #define INT_EN_GPIO1_INT_               0x00000002
 165 #define INT_EN_GPIO0_INT_               0x00000001
 166 
 167 #define BYTE_TEST                       0x64
 168 
 169 #define FIFO_INT                        0x68
 170 #define FIFO_INT_TX_AVAIL_LEVEL_        0xFF000000
 171 #define FIFO_INT_TX_STS_LEVEL_          0x00FF0000
 172 #define FIFO_INT_RX_AVAIL_LEVEL_        0x0000FF00
 173 #define FIFO_INT_RX_STS_LEVEL_          0x000000FF
 174 
 175 #define RX_CFG                          0x6C
 176 #define RX_CFG_RX_END_ALGN_             0xC0000000
 177 #define RX_CFG_RX_END_ALGN4_            0x00000000
 178 #define RX_CFG_RX_END_ALGN16_           0x40000000
 179 #define RX_CFG_RX_END_ALGN32_           0x80000000
 180 #define RX_CFG_RX_DMA_CNT_              0x0FFF0000
 181 #define RX_CFG_RX_DUMP_                 0x00008000
 182 #define RX_CFG_RXDOFF_                  0x00001F00
 183 
 184 #define TX_CFG                          0x70
 185 #define TX_CFG_TXS_DUMP_                0x00008000
 186 #define TX_CFG_TXD_DUMP_                0x00004000
 187 #define TX_CFG_TXSAO_                   0x00000004
 188 #define TX_CFG_TX_ON_                   0x00000002
 189 #define TX_CFG_STOP_TX_                 0x00000001
 190 
 191 #define HW_CFG                          0x74
 192 #define HW_CFG_TTM_                     0x00200000
 193 #define HW_CFG_SF_                      0x00100000
 194 #define HW_CFG_TX_FIF_SZ_               0x000F0000
 195 #define HW_CFG_TR_                      0x00003000
 196 #define HW_CFG_SRST_                    0x00000001
 197 
 198 /* only available on 115/117 */
 199 #define HW_CFG_PHY_CLK_SEL_             0x00000060
 200 #define HW_CFG_PHY_CLK_SEL_INT_PHY_     0x00000000
 201 #define HW_CFG_PHY_CLK_SEL_EXT_PHY_     0x00000020
 202 #define HW_CFG_PHY_CLK_SEL_CLK_DIS_     0x00000040
 203 #define HW_CFG_SMI_SEL_                 0x00000010
 204 #define HW_CFG_EXT_PHY_DET_             0x00000008
 205 #define HW_CFG_EXT_PHY_EN_              0x00000004
 206 #define HW_CFG_SRST_TO_                 0x00000002
 207 
 208 /* only available  on 116/118 */
 209 #define HW_CFG_32_16_BIT_MODE_          0x00000004
 210 
 211 #define RX_DP_CTRL                      0x78
 212 #define RX_DP_CTRL_RX_FFWD_             0x80000000
 213 
 214 #define RX_FIFO_INF                     0x7C
 215 #define RX_FIFO_INF_RXSUSED_            0x00FF0000
 216 #define RX_FIFO_INF_RXDUSED_            0x0000FFFF
 217 
 218 #define TX_FIFO_INF                     0x80
 219 #define TX_FIFO_INF_TSUSED_             0x00FF0000
 220 #define TX_FIFO_INF_TDFREE_             0x0000FFFF
 221 
 222 #define PMT_CTRL                        0x84
 223 #define PMT_CTRL_PM_MODE_               0x00003000
 224 #define PMT_CTRL_PM_MODE_D0_            0x00000000
 225 #define PMT_CTRL_PM_MODE_D1_            0x00001000
 226 #define PMT_CTRL_PM_MODE_D2_            0x00002000
 227 #define PMT_CTRL_PM_MODE_D3_            0x00003000
 228 #define PMT_CTRL_PHY_RST_               0x00000400
 229 #define PMT_CTRL_WOL_EN_                0x00000200
 230 #define PMT_CTRL_ED_EN_                 0x00000100
 231 #define PMT_CTRL_PME_TYPE_              0x00000040
 232 #define PMT_CTRL_WUPS_                  0x00000030
 233 #define PMT_CTRL_WUPS_NOWAKE_           0x00000000
 234 #define PMT_CTRL_WUPS_ED_               0x00000010
 235 #define PMT_CTRL_WUPS_WOL_              0x00000020
 236 #define PMT_CTRL_WUPS_MULTI_            0x00000030
 237 #define PMT_CTRL_PME_IND_               0x00000008
 238 #define PMT_CTRL_PME_POL_               0x00000004
 239 #define PMT_CTRL_PME_EN_                0x00000002
 240 #define PMT_CTRL_READY_                 0x00000001
 241 
 242 #define GPIO_CFG                        0x88
 243 #define GPIO_CFG_LED3_EN_               0x40000000
 244 #define GPIO_CFG_LED2_EN_               0x20000000
 245 #define GPIO_CFG_LED1_EN_               0x10000000
 246 #define GPIO_CFG_GPIO2_INT_POL_         0x04000000
 247 #define GPIO_CFG_GPIO1_INT_POL_         0x02000000
 248 #define GPIO_CFG_GPIO0_INT_POL_         0x01000000
 249 #define GPIO_CFG_EEPR_EN_               0x00700000
 250 #define GPIO_CFG_GPIOBUF2_              0x00040000
 251 #define GPIO_CFG_GPIOBUF1_              0x00020000
 252 #define GPIO_CFG_GPIOBUF0_              0x00010000
 253 #define GPIO_CFG_GPIODIR2_              0x00000400
 254 #define GPIO_CFG_GPIODIR1_              0x00000200
 255 #define GPIO_CFG_GPIODIR0_              0x00000100
 256 #define GPIO_CFG_GPIOD4_                0x00000020
 257 #define GPIO_CFG_GPIOD3_                0x00000010
 258 #define GPIO_CFG_GPIOD2_                0x00000004
 259 #define GPIO_CFG_GPIOD1_                0x00000002
 260 #define GPIO_CFG_GPIOD0_                0x00000001
 261 
 262 #define GPT_CFG                         0x8C
 263 #define GPT_CFG_TIMER_EN_               0x20000000
 264 #define GPT_CFG_GPT_LOAD_               0x0000FFFF
 265 
 266 #define GPT_CNT                         0x90
 267 #define GPT_CNT_GPT_CNT_                0x0000FFFF
 268 
 269 #define WORD_SWAP                       0x98
 270 
 271 #define FREE_RUN                        0x9C
 272 
 273 #define RX_DROP                         0xA0
 274 
 275 #define MAC_CSR_CMD                     0xA4
 276 #define MAC_CSR_CMD_CSR_BUSY_           0x80000000
 277 #define MAC_CSR_CMD_R_NOT_W_            0x40000000
 278 #define MAC_CSR_CMD_CSR_ADDR_           0x000000FF
 279 
 280 #define MAC_CSR_DATA                    0xA8
 281 
 282 #define AFC_CFG                         0xAC
 283 #define AFC_CFG_AFC_HI_                 0x00FF0000
 284 #define AFC_CFG_AFC_LO_                 0x0000FF00
 285 #define AFC_CFG_BACK_DUR_               0x000000F0
 286 #define AFC_CFG_FCMULT_                 0x00000008
 287 #define AFC_CFG_FCBRD_                  0x00000004
 288 #define AFC_CFG_FCADD_                  0x00000002
 289 #define AFC_CFG_FCANY_                  0x00000001
 290 
 291 #define E2P_CMD                         0xB0
 292 #define E2P_CMD_EPC_BUSY_               0x80000000
 293 #define E2P_CMD_EPC_CMD_                0x70000000
 294 #define E2P_CMD_EPC_CMD_READ_           0x00000000
 295 #define E2P_CMD_EPC_CMD_EWDS_           0x10000000
 296 #define E2P_CMD_EPC_CMD_EWEN_           0x20000000
 297 #define E2P_CMD_EPC_CMD_WRITE_          0x30000000
 298 #define E2P_CMD_EPC_CMD_WRAL_           0x40000000
 299 #define E2P_CMD_EPC_CMD_ERASE_          0x50000000
 300 #define E2P_CMD_EPC_CMD_ERAL_           0x60000000
 301 #define E2P_CMD_EPC_CMD_RELOAD_         0x70000000
 302 #define E2P_CMD_EPC_TIMEOUT_            0x00000200
 303 #define E2P_CMD_MAC_ADDR_LOADED_        0x00000100
 304 #define E2P_CMD_EPC_ADDR_               0x000000FF
 305 
 306 #define E2P_DATA                        0xB4
 307 #define E2P_DATA_EEPROM_DATA_           0x000000FF
 308 #define LAN_REGISTER_EXTENT             0x00000100
 309 
 310 #define RESET_CTL                       0x1F8
 311 #define RESET_CTL_DIGITAL_RST_          0x00000001
 312 
 313 /*
 314  * MAC Control and Status Register (Indirect Address)
 315  * Offset (through the MAC_CSR CMD and DATA port)
 316  */
 317 #define MAC_CR                          0x01
 318 #define MAC_CR_RXALL_                   0x80000000
 319 #define MAC_CR_HBDIS_                   0x10000000
 320 #define MAC_CR_RCVOWN_                  0x00800000
 321 #define MAC_CR_LOOPBK_                  0x00200000
 322 #define MAC_CR_FDPX_                    0x00100000
 323 #define MAC_CR_MCPAS_                   0x00080000
 324 #define MAC_CR_PRMS_                    0x00040000
 325 #define MAC_CR_INVFILT_                 0x00020000
 326 #define MAC_CR_PASSBAD_                 0x00010000
 327 #define MAC_CR_HFILT_                   0x00008000
 328 #define MAC_CR_HPFILT_                  0x00002000
 329 #define MAC_CR_LCOLL_                   0x00001000
 330 #define MAC_CR_BCAST_                   0x00000800
 331 #define MAC_CR_DISRTY_                  0x00000400
 332 #define MAC_CR_PADSTR_                  0x00000100
 333 #define MAC_CR_BOLMT_MASK_              0x000000C0
 334 #define MAC_CR_DFCHK_                   0x00000020
 335 #define MAC_CR_TXEN_                    0x00000008
 336 #define MAC_CR_RXEN_                    0x00000004
 337 
 338 #define ADDRH                           0x02
 339 
 340 #define ADDRL                           0x03
 341 
 342 #define HASHH                           0x04
 343 
 344 #define HASHL                           0x05
 345 
 346 #define MII_ACC                         0x06
 347 #define MII_ACC_PHY_ADDR_               0x0000F800
 348 #define MII_ACC_MIIRINDA_               0x000007C0
 349 #define MII_ACC_MII_WRITE_              0x00000002
 350 #define MII_ACC_MII_BUSY_               0x00000001
 351 
 352 #define MII_DATA                        0x07
 353 
 354 #define FLOW                            0x08
 355 #define FLOW_FCPT_                      0xFFFF0000
 356 #define FLOW_FCPASS_                    0x00000004
 357 #define FLOW_FCEN_                      0x00000002
 358 #define FLOW_FCBSY_                     0x00000001
 359 
 360 #define VLAN1                           0x09
 361 
 362 #define VLAN2                           0x0A
 363 
 364 #define WUFF                            0x0B
 365 
 366 #define WUCSR                           0x0C
 367 #define WUCSR_GUE_                      0x00000200
 368 #define WUCSR_WUFR_                     0x00000040
 369 #define WUCSR_MPR_                      0x00000020
 370 #define WUCSR_WAKE_EN_                  0x00000004
 371 #define WUCSR_MPEN_                     0x00000002
 372 
 373 /*
 374  * Phy definitions (vendor-specific)
 375  */
 376 #define LAN9118_PHY_ID                  0x00C0001C
 377 
 378 #define MII_INTSTS                      0x1D
 379 
 380 #define MII_INTMSK                      0x1E
 381 #define PHY_INTMSK_AN_RCV_              (1 << 1)
 382 #define PHY_INTMSK_PDFAULT_             (1 << 2)
 383 #define PHY_INTMSK_AN_ACK_              (1 << 3)
 384 #define PHY_INTMSK_LNKDOWN_             (1 << 4)
 385 #define PHY_INTMSK_RFAULT_              (1 << 5)
 386 #define PHY_INTMSK_AN_COMP_             (1 << 6)
 387 #define PHY_INTMSK_ENERGYON_            (1 << 7)
 388 #define PHY_INTMSK_DEFAULT_             (PHY_INTMSK_ENERGYON_ | \
 389                                          PHY_INTMSK_AN_COMP_ | \
 390                                          PHY_INTMSK_RFAULT_ | \
 391                                          PHY_INTMSK_LNKDOWN_)
 392 
 393 #define ADVERTISE_PAUSE_ALL             (ADVERTISE_PAUSE_CAP | \
 394                                          ADVERTISE_PAUSE_ASYM)
 395 
 396 #define LPA_PAUSE_ALL                   (LPA_PAUSE_CAP | \
 397                                          LPA_PAUSE_ASYM)
 398 
 399 /*
 400  * Provide hooks to let the arch add to the initialisation procedure
 401  * and to override the source of the MAC address.
 402  */
 403 #define SMSC_INITIALIZE()               do {} while (0)
 404 #define smsc_get_mac(dev)               smsc911x_read_mac_address((dev))
 405 
 406 #ifdef CONFIG_SMSC911X_ARCH_HOOKS
 407 #include <asm/smsc911x.h>
 408 #endif
 409 
 410 #include <linux/smscphy.h>
 411 
 412 #endif                          /* __SMSC911X_H__ */

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