This source file includes following definitions.
- PRIV
- kick_rx
- build_rx_desc
- ns83820_add_rx_skb
- rx_refill
- rx_refill_atomic
- queue_refill
- clear_rx_desc
- phy_intr
- ns83820_setup_rx
- ns83820_cleanup_rx
- ns83820_rx_kick
- rx_irq
- rx_action
- kick_tx
- do_tx_done
- ns83820_cleanup_tx
- ns83820_hard_start_xmit
- ns83820_update_stats
- ns83820_get_stats
- ns83820_get_link_ksettings
- ns83820_set_link_ksettings
- ns83820_get_drvinfo
- ns83820_get_link
- ns83820_disable_interrupts
- ns83820_mib_isr
- ns83820_irq
- ns83820_do_isr
- ns83820_do_reset
- ns83820_stop
- ns83820_tx_timeout
- ns83820_tx_watch
- ns83820_open
- ns83820_getmac
- ns83820_set_multicast
- ns83820_run_bist
- ns83820_mii_write_bit
- ns83820_mii_read_bit
- ns83820_mii_read_reg
- ns83820_mii_write_reg
- ns83820_probe_phy
- ns83820_init_one
- ns83820_remove_one
- ns83820_init
- ns83820_exit
1
2 #define VERSION "0.23"
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82 #define dprintk(x...) do { } while (0)
83
84 #include <linux/module.h>
85 #include <linux/moduleparam.h>
86 #include <linux/types.h>
87 #include <linux/pci.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/netdevice.h>
90 #include <linux/etherdevice.h>
91 #include <linux/delay.h>
92 #include <linux/workqueue.h>
93 #include <linux/init.h>
94 #include <linux/interrupt.h>
95 #include <linux/ip.h>
96 #include <linux/in.h>
97 #include <linux/compiler.h>
98 #include <linux/prefetch.h>
99 #include <linux/ethtool.h>
100 #include <linux/sched.h>
101 #include <linux/timer.h>
102 #include <linux/if_vlan.h>
103 #include <linux/rtnetlink.h>
104 #include <linux/jiffies.h>
105 #include <linux/slab.h>
106
107 #include <asm/io.h>
108 #include <linux/uaccess.h>
109
110 #define DRV_NAME "ns83820"
111
112
113 static int ihr = 2;
114 static int reset_phy = 0;
115 static int lnksts = 0;
116
117
118 #undef Dprintk
119 #define Dprintk dprintk
120
121
122 #define RX_BUF_SIZE 1500
123 #if IS_ENABLED(CONFIG_VLAN_8021Q)
124 #define NS83820_VLAN_ACCEL_SUPPORT
125 #endif
126
127
128 #define NR_RX_DESC 64
129 #define NR_TX_DESC 128
130
131
132 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14)
133
134 #define MIN_TX_DESC_FREE 8
135
136
137 #define CFGCS 0x04
138
139 #define CR_TXE 0x00000001
140 #define CR_TXD 0x00000002
141
142
143
144 #define CR_RXE 0x00000004
145 #define CR_RXD 0x00000008
146 #define CR_TXR 0x00000010
147 #define CR_RXR 0x00000020
148 #define CR_SWI 0x00000080
149 #define CR_RST 0x00000100
150
151 #define PTSCR_EEBIST_FAIL 0x00000001
152 #define PTSCR_EEBIST_EN 0x00000002
153 #define PTSCR_EELOAD_EN 0x00000004
154 #define PTSCR_RBIST_FAIL 0x000001b8
155 #define PTSCR_RBIST_DONE 0x00000200
156 #define PTSCR_RBIST_EN 0x00000400
157 #define PTSCR_RBIST_RST 0x00002000
158
159 #define MEAR_EEDI 0x00000001
160 #define MEAR_EEDO 0x00000002
161 #define MEAR_EECLK 0x00000004
162 #define MEAR_EESEL 0x00000008
163 #define MEAR_MDIO 0x00000010
164 #define MEAR_MDDIR 0x00000020
165 #define MEAR_MDC 0x00000040
166
167 #define ISR_TXDESC3 0x40000000
168 #define ISR_TXDESC2 0x20000000
169 #define ISR_TXDESC1 0x10000000
170 #define ISR_TXDESC0 0x08000000
171 #define ISR_RXDESC3 0x04000000
172 #define ISR_RXDESC2 0x02000000
173 #define ISR_RXDESC1 0x01000000
174 #define ISR_RXDESC0 0x00800000
175 #define ISR_TXRCMP 0x00400000
176 #define ISR_RXRCMP 0x00200000
177 #define ISR_DPERR 0x00100000
178 #define ISR_SSERR 0x00080000
179 #define ISR_RMABT 0x00040000
180 #define ISR_RTABT 0x00020000
181 #define ISR_RXSOVR 0x00010000
182 #define ISR_HIBINT 0x00008000
183 #define ISR_PHY 0x00004000
184 #define ISR_PME 0x00002000
185 #define ISR_SWI 0x00001000
186 #define ISR_MIB 0x00000800
187 #define ISR_TXURN 0x00000400
188 #define ISR_TXIDLE 0x00000200
189 #define ISR_TXERR 0x00000100
190 #define ISR_TXDESC 0x00000080
191 #define ISR_TXOK 0x00000040
192 #define ISR_RXORN 0x00000020
193 #define ISR_RXIDLE 0x00000010
194 #define ISR_RXEARLY 0x00000008
195 #define ISR_RXERR 0x00000004
196 #define ISR_RXDESC 0x00000002
197 #define ISR_RXOK 0x00000001
198
199 #define TXCFG_CSI 0x80000000
200 #define TXCFG_HBI 0x40000000
201 #define TXCFG_MLB 0x20000000
202 #define TXCFG_ATP 0x10000000
203 #define TXCFG_ECRETRY 0x00800000
204 #define TXCFG_BRST_DIS 0x00080000
205 #define TXCFG_MXDMA1024 0x00000000
206 #define TXCFG_MXDMA512 0x00700000
207 #define TXCFG_MXDMA256 0x00600000
208 #define TXCFG_MXDMA128 0x00500000
209 #define TXCFG_MXDMA64 0x00400000
210 #define TXCFG_MXDMA32 0x00300000
211 #define TXCFG_MXDMA16 0x00200000
212 #define TXCFG_MXDMA8 0x00100000
213
214 #define CFG_LNKSTS 0x80000000
215 #define CFG_SPDSTS 0x60000000
216 #define CFG_SPDSTS1 0x40000000
217 #define CFG_SPDSTS0 0x20000000
218 #define CFG_DUPSTS 0x10000000
219 #define CFG_TBI_EN 0x01000000
220 #define CFG_MODE_1000 0x00400000
221
222
223 #define CFG_AUTO_1000 0x00200000
224 #define CFG_PINT_CTL 0x001c0000
225 #define CFG_PINT_DUPSTS 0x00100000
226 #define CFG_PINT_LNKSTS 0x00080000
227 #define CFG_PINT_SPDSTS 0x00040000
228 #define CFG_TMRTEST 0x00020000
229 #define CFG_MRM_DIS 0x00010000
230 #define CFG_MWI_DIS 0x00008000
231 #define CFG_T64ADDR 0x00004000
232 #define CFG_PCI64_DET 0x00002000
233 #define CFG_DATA64_EN 0x00001000
234 #define CFG_M64ADDR 0x00000800
235 #define CFG_PHY_RST 0x00000400
236 #define CFG_PHY_DIS 0x00000200
237 #define CFG_EXTSTS_EN 0x00000100
238 #define CFG_REQALG 0x00000080
239 #define CFG_SB 0x00000040
240 #define CFG_POW 0x00000020
241 #define CFG_EXD 0x00000010
242 #define CFG_PESEL 0x00000008
243 #define CFG_BROM_DIS 0x00000004
244 #define CFG_EXT_125 0x00000002
245 #define CFG_BEM 0x00000001
246
247 #define EXTSTS_UDPPKT 0x00200000
248 #define EXTSTS_TCPPKT 0x00080000
249 #define EXTSTS_IPPKT 0x00020000
250 #define EXTSTS_VPKT 0x00010000
251 #define EXTSTS_VTG_MASK 0x0000ffff
252
253 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
254
255 #define MIBC_MIBS 0x00000008
256 #define MIBC_ACLR 0x00000004
257 #define MIBC_FRZ 0x00000002
258 #define MIBC_WRN 0x00000001
259
260 #define PCR_PSEN (1 << 31)
261 #define PCR_PS_MCAST (1 << 30)
262 #define PCR_PS_DA (1 << 29)
263 #define PCR_STHI_8 (3 << 23)
264 #define PCR_STLO_4 (1 << 23)
265 #define PCR_FFHI_8K (3 << 21)
266 #define PCR_FFLO_4K (1 << 21)
267 #define PCR_PAUSE_CNT 0xFFFE
268
269 #define RXCFG_AEP 0x80000000
270 #define RXCFG_ARP 0x40000000
271 #define RXCFG_STRIPCRC 0x20000000
272 #define RXCFG_RX_FD 0x10000000
273 #define RXCFG_ALP 0x08000000
274 #define RXCFG_AIRL 0x04000000
275 #define RXCFG_MXDMA512 0x00700000
276 #define RXCFG_DRTH 0x0000003e
277 #define RXCFG_DRTH0 0x00000002
278
279 #define RFCR_RFEN 0x80000000
280 #define RFCR_AAB 0x40000000
281 #define RFCR_AAM 0x20000000
282 #define RFCR_AAU 0x10000000
283 #define RFCR_APM 0x08000000
284 #define RFCR_APAT 0x07800000
285 #define RFCR_APAT3 0x04000000
286 #define RFCR_APAT2 0x02000000
287 #define RFCR_APAT1 0x01000000
288 #define RFCR_APAT0 0x00800000
289 #define RFCR_AARP 0x00400000
290 #define RFCR_MHEN 0x00200000
291 #define RFCR_UHEN 0x00100000
292 #define RFCR_ULM 0x00080000
293
294 #define VRCR_RUDPE 0x00000080
295 #define VRCR_RTCPE 0x00000040
296 #define VRCR_RIPE 0x00000020
297 #define VRCR_IPEN 0x00000010
298 #define VRCR_DUTF 0x00000008
299 #define VRCR_DVTF 0x00000004
300 #define VRCR_VTREN 0x00000002
301 #define VRCR_VTDEN 0x00000001
302
303 #define VTCR_PPCHK 0x00000008
304 #define VTCR_GCHK 0x00000004
305 #define VTCR_VPPTI 0x00000002
306 #define VTCR_VGTI 0x00000001
307
308 #define CR 0x00
309 #define CFG 0x04
310 #define MEAR 0x08
311 #define PTSCR 0x0c
312 #define ISR 0x10
313 #define IMR 0x14
314 #define IER 0x18
315 #define IHR 0x1c
316 #define TXDP 0x20
317 #define TXDP_HI 0x24
318 #define TXCFG 0x28
319 #define GPIOR 0x2c
320 #define RXDP 0x30
321 #define RXDP_HI 0x34
322 #define RXCFG 0x38
323 #define PQCR 0x3c
324 #define WCSR 0x40
325 #define PCR 0x44
326 #define RFCR 0x48
327 #define RFDR 0x4c
328
329 #define SRR 0x58
330
331 #define VRCR 0xbc
332 #define VTCR 0xc0
333 #define VDR 0xc4
334 #define CCSR 0xcc
335
336 #define TBICR 0xe0
337 #define TBISR 0xe4
338 #define TANAR 0xe8
339 #define TANLPAR 0xec
340 #define TANER 0xf0
341 #define TESR 0xf4
342
343 #define TBICR_MR_AN_ENABLE 0x00001000
344 #define TBICR_MR_RESTART_AN 0x00000200
345
346 #define TBISR_MR_LINK_STATUS 0x00000020
347 #define TBISR_MR_AN_COMPLETE 0x00000004
348
349 #define TANAR_PS2 0x00000100
350 #define TANAR_PS1 0x00000080
351 #define TANAR_HALF_DUP 0x00000040
352 #define TANAR_FULL_DUP 0x00000020
353
354 #define GPIOR_GP5_OE 0x00000200
355 #define GPIOR_GP4_OE 0x00000100
356 #define GPIOR_GP3_OE 0x00000080
357 #define GPIOR_GP2_OE 0x00000040
358 #define GPIOR_GP1_OE 0x00000020
359 #define GPIOR_GP3_OUT 0x00000004
360 #define GPIOR_GP1_OUT 0x00000001
361
362 #define LINK_AUTONEGOTIATE 0x01
363 #define LINK_DOWN 0x02
364 #define LINK_UP 0x04
365
366 #define HW_ADDR_LEN sizeof(dma_addr_t)
367 #define desc_addr_set(desc, addr) \
368 do { \
369 ((desc)[0] = cpu_to_le32(addr)); \
370 if (HW_ADDR_LEN == 8) \
371 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
372 } while(0)
373 #define desc_addr_get(desc) \
374 (le32_to_cpu((desc)[0]) | \
375 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
376
377 #define DESC_LINK 0
378 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
379 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
380 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
381
382 #define CMDSTS_OWN 0x80000000
383 #define CMDSTS_MORE 0x40000000
384 #define CMDSTS_INTR 0x20000000
385 #define CMDSTS_ERR 0x10000000
386 #define CMDSTS_OK 0x08000000
387 #define CMDSTS_RUNT 0x00200000
388 #define CMDSTS_LEN_MASK 0x0000ffff
389
390 #define CMDSTS_DEST_MASK 0x01800000
391 #define CMDSTS_DEST_SELF 0x00800000
392 #define CMDSTS_DEST_MULTI 0x01000000
393
394 #define DESC_SIZE 8
395
396 struct rx_info {
397 spinlock_t lock;
398 int up;
399 unsigned long idle;
400
401 struct sk_buff *skbs[NR_RX_DESC];
402
403 __le32 *next_rx_desc;
404 u16 next_rx, next_empty;
405
406 __le32 *descs;
407 dma_addr_t phy_descs;
408 };
409
410
411 struct ns83820 {
412 u8 __iomem *base;
413
414 struct pci_dev *pci_dev;
415 struct net_device *ndev;
416
417 struct rx_info rx_info;
418 struct tasklet_struct rx_tasklet;
419
420 unsigned ihr;
421 struct work_struct tq_refill;
422
423
424 spinlock_t misc_lock;
425
426 u32 CFG_cache;
427
428 u32 MEAR_cache;
429 u32 IMR_cache;
430
431 unsigned linkstate;
432
433 spinlock_t tx_lock;
434
435 u16 tx_done_idx;
436 u16 tx_idx;
437 volatile u16 tx_free_idx;
438 u16 tx_intr_idx;
439
440 atomic_t nr_tx_skbs;
441 struct sk_buff *tx_skbs[NR_TX_DESC];
442
443 char pad[16] __attribute__((aligned(16)));
444 __le32 *tx_descs;
445 dma_addr_t tx_phy_descs;
446
447 struct timer_list tx_watchdog;
448 };
449
450 static inline struct ns83820 *PRIV(struct net_device *dev)
451 {
452 return netdev_priv(dev);
453 }
454
455 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
456
457 static inline void kick_rx(struct net_device *ndev)
458 {
459 struct ns83820 *dev = PRIV(ndev);
460 dprintk("kick_rx: maybe kicking\n");
461 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
462 dprintk("actually kicking\n");
463 writel(dev->rx_info.phy_descs +
464 (4 * DESC_SIZE * dev->rx_info.next_rx),
465 dev->base + RXDP);
466 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
467 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
468 ndev->name);
469 __kick_rx(dev);
470 }
471 }
472
473
474 #define start_tx_okay(dev) \
475 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
476
477
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489
490 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
491 {
492 desc_addr_set(desc + DESC_LINK, link);
493 desc_addr_set(desc + DESC_BUFPTR, buf);
494 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
495 mb();
496 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
497 }
498
499 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
500 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
501 {
502 unsigned next_empty;
503 u32 cmdsts;
504 __le32 *sg;
505 dma_addr_t buf;
506
507 next_empty = dev->rx_info.next_empty;
508
509
510 if (unlikely(nr_rx_empty(dev) <= 2)) {
511 kfree_skb(skb);
512 return 1;
513 }
514
515 #if 0
516 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
517 dev->rx_info.next_empty,
518 dev->rx_info.nr_used,
519 dev->rx_info.next_rx
520 );
521 #endif
522
523 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
524 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
525 dev->rx_info.skbs[next_empty] = skb;
526
527 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
528 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
529 buf = pci_map_single(dev->pci_dev, skb->data,
530 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
531 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
532
533 if (likely(next_empty != dev->rx_info.next_rx))
534 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
535
536 return 0;
537 }
538
539 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
540 {
541 struct ns83820 *dev = PRIV(ndev);
542 unsigned i;
543 unsigned long flags = 0;
544
545 if (unlikely(nr_rx_empty(dev) <= 2))
546 return 0;
547
548 dprintk("rx_refill(%p)\n", ndev);
549 if (gfp == GFP_ATOMIC)
550 spin_lock_irqsave(&dev->rx_info.lock, flags);
551 for (i=0; i<NR_RX_DESC; i++) {
552 struct sk_buff *skb;
553 long res;
554
555
556 skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp);
557 if (unlikely(!skb))
558 break;
559
560 skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16));
561 if (gfp != GFP_ATOMIC)
562 spin_lock_irqsave(&dev->rx_info.lock, flags);
563 res = ns83820_add_rx_skb(dev, skb);
564 if (gfp != GFP_ATOMIC)
565 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
566 if (res) {
567 i = 1;
568 break;
569 }
570 }
571 if (gfp == GFP_ATOMIC)
572 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
573
574 return i ? 0 : -ENOMEM;
575 }
576
577 static void rx_refill_atomic(struct net_device *ndev)
578 {
579 rx_refill(ndev, GFP_ATOMIC);
580 }
581
582
583 static inline void queue_refill(struct work_struct *work)
584 {
585 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
586 struct net_device *ndev = dev->ndev;
587
588 rx_refill(ndev, GFP_KERNEL);
589 if (dev->rx_info.up)
590 kick_rx(ndev);
591 }
592
593 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
594 {
595 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
596 }
597
598 static void phy_intr(struct net_device *ndev)
599 {
600 struct ns83820 *dev = PRIV(ndev);
601 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
602 u32 cfg, new_cfg;
603 u32 tbisr, tanar, tanlpar;
604 int speed, fullduplex, newlinkstate;
605
606 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
607
608 if (dev->CFG_cache & CFG_TBI_EN) {
609
610 tbisr = readl(dev->base + TBISR);
611 tanar = readl(dev->base + TANAR);
612 tanlpar = readl(dev->base + TANLPAR);
613 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
614 tbisr, tanar, tanlpar);
615
616 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP) &&
617 (tanar & TANAR_FULL_DUP)) ) {
618
619
620 writel(readl(dev->base + TXCFG)
621 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
622 dev->base + TXCFG);
623 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
624 dev->base + RXCFG);
625
626 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
627 dev->base + GPIOR);
628
629 } else if (((tanlpar & TANAR_HALF_DUP) &&
630 (tanar & TANAR_HALF_DUP)) ||
631 ((tanlpar & TANAR_FULL_DUP) &&
632 (tanar & TANAR_HALF_DUP)) ||
633 ((tanlpar & TANAR_HALF_DUP) &&
634 (tanar & TANAR_FULL_DUP))) {
635
636
637 writel((readl(dev->base + TXCFG)
638 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
639 dev->base + TXCFG);
640 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
641 dev->base + RXCFG);
642
643 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
644 dev->base + GPIOR);
645 }
646
647 speed = 4;
648
649 } else {
650
651 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
652
653 if (cfg & CFG_SPDSTS1)
654 new_cfg |= CFG_MODE_1000;
655 else
656 new_cfg &= ~CFG_MODE_1000;
657
658 speed = ((cfg / CFG_SPDSTS0) & 3);
659 fullduplex = (cfg & CFG_DUPSTS);
660
661 if (fullduplex) {
662 new_cfg |= CFG_SB;
663 writel(readl(dev->base + TXCFG)
664 | TXCFG_CSI | TXCFG_HBI,
665 dev->base + TXCFG);
666 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
667 dev->base + RXCFG);
668 } else {
669 writel(readl(dev->base + TXCFG)
670 & ~(TXCFG_CSI | TXCFG_HBI),
671 dev->base + TXCFG);
672 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
673 dev->base + RXCFG);
674 }
675
676 if ((cfg & CFG_LNKSTS) &&
677 ((new_cfg ^ dev->CFG_cache) != 0)) {
678 writel(new_cfg, dev->base + CFG);
679 dev->CFG_cache = new_cfg;
680 }
681
682 dev->CFG_cache &= ~CFG_SPDSTS;
683 dev->CFG_cache |= cfg & CFG_SPDSTS;
684 }
685
686 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
687
688 if (newlinkstate & LINK_UP &&
689 dev->linkstate != newlinkstate) {
690 netif_start_queue(ndev);
691 netif_wake_queue(ndev);
692 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
693 ndev->name,
694 speeds[speed],
695 fullduplex ? "full" : "half");
696 } else if (newlinkstate & LINK_DOWN &&
697 dev->linkstate != newlinkstate) {
698 netif_stop_queue(ndev);
699 printk(KERN_INFO "%s: link now down.\n", ndev->name);
700 }
701
702 dev->linkstate = newlinkstate;
703 }
704
705 static int ns83820_setup_rx(struct net_device *ndev)
706 {
707 struct ns83820 *dev = PRIV(ndev);
708 unsigned i;
709 int ret;
710
711 dprintk("ns83820_setup_rx(%p)\n", ndev);
712
713 dev->rx_info.idle = 1;
714 dev->rx_info.next_rx = 0;
715 dev->rx_info.next_rx_desc = dev->rx_info.descs;
716 dev->rx_info.next_empty = 0;
717
718 for (i=0; i<NR_RX_DESC; i++)
719 clear_rx_desc(dev, i);
720
721 writel(0, dev->base + RXDP_HI);
722 writel(dev->rx_info.phy_descs, dev->base + RXDP);
723
724 ret = rx_refill(ndev, GFP_KERNEL);
725 if (!ret) {
726 dprintk("starting receiver\n");
727
728 spin_lock_irq(&dev->rx_info.lock);
729
730 writel(0x0001, dev->base + CCSR);
731 writel(0, dev->base + RFCR);
732 writel(0x7fc00000, dev->base + RFCR);
733 writel(0xffc00000, dev->base + RFCR);
734
735 dev->rx_info.up = 1;
736
737 phy_intr(ndev);
738
739
740 spin_lock(&dev->misc_lock);
741 dev->IMR_cache |= ISR_PHY;
742 dev->IMR_cache |= ISR_RXRCMP;
743
744
745 dev->IMR_cache |= ISR_RXORN;
746 dev->IMR_cache |= ISR_RXSOVR;
747 dev->IMR_cache |= ISR_RXDESC;
748 dev->IMR_cache |= ISR_RXIDLE;
749 dev->IMR_cache |= ISR_TXDESC;
750 dev->IMR_cache |= ISR_TXIDLE;
751
752 writel(dev->IMR_cache, dev->base + IMR);
753 writel(1, dev->base + IER);
754 spin_unlock(&dev->misc_lock);
755
756 kick_rx(ndev);
757
758 spin_unlock_irq(&dev->rx_info.lock);
759 }
760 return ret;
761 }
762
763 static void ns83820_cleanup_rx(struct ns83820 *dev)
764 {
765 unsigned i;
766 unsigned long flags;
767
768 dprintk("ns83820_cleanup_rx(%p)\n", dev);
769
770
771 spin_lock_irqsave(&dev->misc_lock, flags);
772 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
773 writel(dev->IMR_cache, dev->base + IMR);
774 spin_unlock_irqrestore(&dev->misc_lock, flags);
775
776
777 dev->rx_info.up = 0;
778 synchronize_irq(dev->pci_dev->irq);
779
780
781 readl(dev->base + IMR);
782
783
784 writel(0, dev->base + RXDP_HI);
785 writel(0, dev->base + RXDP);
786
787 for (i=0; i<NR_RX_DESC; i++) {
788 struct sk_buff *skb = dev->rx_info.skbs[i];
789 dev->rx_info.skbs[i] = NULL;
790 clear_rx_desc(dev, i);
791 kfree_skb(skb);
792 }
793 }
794
795 static void ns83820_rx_kick(struct net_device *ndev)
796 {
797 struct ns83820 *dev = PRIV(ndev);
798 {
799 if (dev->rx_info.up) {
800 rx_refill_atomic(ndev);
801 kick_rx(ndev);
802 }
803 }
804
805 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
806 schedule_work(&dev->tq_refill);
807 else
808 kick_rx(ndev);
809 if (dev->rx_info.idle)
810 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
811 }
812
813
814
815
816 static void rx_irq(struct net_device *ndev)
817 {
818 struct ns83820 *dev = PRIV(ndev);
819 struct rx_info *info = &dev->rx_info;
820 unsigned next_rx;
821 int rx_rc, len;
822 u32 cmdsts;
823 __le32 *desc;
824 unsigned long flags;
825 int nr = 0;
826
827 dprintk("rx_irq(%p)\n", ndev);
828 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
829 readl(dev->base + RXDP),
830 (long)(dev->rx_info.phy_descs),
831 (int)dev->rx_info.next_rx,
832 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
833 (int)dev->rx_info.next_empty,
834 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
835 );
836
837 spin_lock_irqsave(&info->lock, flags);
838 if (!info->up)
839 goto out;
840
841 dprintk("walking descs\n");
842 next_rx = info->next_rx;
843 desc = info->next_rx_desc;
844 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
845 (cmdsts != CMDSTS_OWN)) {
846 struct sk_buff *skb;
847 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
848 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
849
850 dprintk("cmdsts: %08x\n", cmdsts);
851 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
852 dprintk("extsts: %08x\n", extsts);
853
854 skb = info->skbs[next_rx];
855 info->skbs[next_rx] = NULL;
856 info->next_rx = (next_rx + 1) % NR_RX_DESC;
857
858 mb();
859 clear_rx_desc(dev, next_rx);
860
861 pci_unmap_single(dev->pci_dev, bufptr,
862 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
863 len = cmdsts & CMDSTS_LEN_MASK;
864 #ifdef NS83820_VLAN_ACCEL_SUPPORT
865
866
867
868
869
870
871
872
873
874
875
876 if (likely((CMDSTS_OK & cmdsts) ||
877 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
878 #else
879 if (likely(CMDSTS_OK & cmdsts)) {
880 #endif
881 skb_put(skb, len);
882 if (unlikely(!skb))
883 goto netdev_mangle_me_harder_failed;
884 if (cmdsts & CMDSTS_DEST_MULTI)
885 ndev->stats.multicast++;
886 ndev->stats.rx_packets++;
887 ndev->stats.rx_bytes += len;
888 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
889 skb->ip_summed = CHECKSUM_UNNECESSARY;
890 } else {
891 skb_checksum_none_assert(skb);
892 }
893 skb->protocol = eth_type_trans(skb, ndev);
894 #ifdef NS83820_VLAN_ACCEL_SUPPORT
895 if(extsts & EXTSTS_VPKT) {
896 unsigned short tag;
897
898 tag = ntohs(extsts & EXTSTS_VTG_MASK);
899 __vlan_hwaccel_put_tag(skb, htons(ETH_P_IPV6), tag);
900 }
901 #endif
902 rx_rc = netif_rx(skb);
903 if (NET_RX_DROP == rx_rc) {
904 netdev_mangle_me_harder_failed:
905 ndev->stats.rx_dropped++;
906 }
907 } else {
908 dev_kfree_skb_irq(skb);
909 }
910
911 nr++;
912 next_rx = info->next_rx;
913 desc = info->descs + (DESC_SIZE * next_rx);
914 }
915 info->next_rx = next_rx;
916 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
917
918 out:
919 if (0 && !nr) {
920 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
921 }
922
923 spin_unlock_irqrestore(&info->lock, flags);
924 }
925
926 static void rx_action(unsigned long _dev)
927 {
928 struct net_device *ndev = (void *)_dev;
929 struct ns83820 *dev = PRIV(ndev);
930 rx_irq(ndev);
931 writel(ihr, dev->base + IHR);
932
933 spin_lock_irq(&dev->misc_lock);
934 dev->IMR_cache |= ISR_RXDESC;
935 writel(dev->IMR_cache, dev->base + IMR);
936 spin_unlock_irq(&dev->misc_lock);
937
938 rx_irq(ndev);
939 ns83820_rx_kick(ndev);
940 }
941
942
943
944 static inline void kick_tx(struct ns83820 *dev)
945 {
946 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
947 dev, dev->tx_idx, dev->tx_free_idx);
948 writel(CR_TXE, dev->base + CR);
949 }
950
951
952
953
954 static void do_tx_done(struct net_device *ndev)
955 {
956 struct ns83820 *dev = PRIV(ndev);
957 u32 cmdsts, tx_done_idx;
958 __le32 *desc;
959
960 dprintk("do_tx_done(%p)\n", ndev);
961 tx_done_idx = dev->tx_done_idx;
962 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
963
964 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
965 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
966 while ((tx_done_idx != dev->tx_free_idx) &&
967 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
968 struct sk_buff *skb;
969 unsigned len;
970 dma_addr_t addr;
971
972 if (cmdsts & CMDSTS_ERR)
973 ndev->stats.tx_errors++;
974 if (cmdsts & CMDSTS_OK)
975 ndev->stats.tx_packets++;
976 if (cmdsts & CMDSTS_OK)
977 ndev->stats.tx_bytes += cmdsts & 0xffff;
978
979 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
980 tx_done_idx, dev->tx_free_idx, cmdsts);
981 skb = dev->tx_skbs[tx_done_idx];
982 dev->tx_skbs[tx_done_idx] = NULL;
983 dprintk("done(%p)\n", skb);
984
985 len = cmdsts & CMDSTS_LEN_MASK;
986 addr = desc_addr_get(desc + DESC_BUFPTR);
987 if (skb) {
988 pci_unmap_single(dev->pci_dev,
989 addr,
990 len,
991 PCI_DMA_TODEVICE);
992 dev_consume_skb_irq(skb);
993 atomic_dec(&dev->nr_tx_skbs);
994 } else
995 pci_unmap_page(dev->pci_dev,
996 addr,
997 len,
998 PCI_DMA_TODEVICE);
999
1000 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1001 dev->tx_done_idx = tx_done_idx;
1002 desc[DESC_CMDSTS] = cpu_to_le32(0);
1003 mb();
1004 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1005 }
1006
1007
1008
1009
1010 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1011 dprintk("start_queue(%p)\n", ndev);
1012 netif_start_queue(ndev);
1013 netif_wake_queue(ndev);
1014 }
1015 }
1016
1017 static void ns83820_cleanup_tx(struct ns83820 *dev)
1018 {
1019 unsigned i;
1020
1021 for (i=0; i<NR_TX_DESC; i++) {
1022 struct sk_buff *skb = dev->tx_skbs[i];
1023 dev->tx_skbs[i] = NULL;
1024 if (skb) {
1025 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1026 pci_unmap_single(dev->pci_dev,
1027 desc_addr_get(desc + DESC_BUFPTR),
1028 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1029 PCI_DMA_TODEVICE);
1030 dev_kfree_skb_irq(skb);
1031 atomic_dec(&dev->nr_tx_skbs);
1032 }
1033 }
1034
1035 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1036 }
1037
1038
1039
1040
1041
1042
1043
1044 static netdev_tx_t ns83820_hard_start_xmit(struct sk_buff *skb,
1045 struct net_device *ndev)
1046 {
1047 struct ns83820 *dev = PRIV(ndev);
1048 u32 free_idx, cmdsts, extsts;
1049 int nr_free, nr_frags;
1050 unsigned tx_done_idx, last_idx;
1051 dma_addr_t buf;
1052 unsigned len;
1053 skb_frag_t *frag;
1054 int stopped = 0;
1055 int do_intr = 0;
1056 volatile __le32 *first_desc;
1057
1058 dprintk("ns83820_hard_start_xmit\n");
1059
1060 nr_frags = skb_shinfo(skb)->nr_frags;
1061 again:
1062 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1063 netif_stop_queue(ndev);
1064 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1065 return NETDEV_TX_BUSY;
1066 netif_start_queue(ndev);
1067 }
1068
1069 last_idx = free_idx = dev->tx_free_idx;
1070 tx_done_idx = dev->tx_done_idx;
1071 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1072 nr_free -= 1;
1073 if (nr_free <= nr_frags) {
1074 dprintk("stop_queue - not enough(%p)\n", ndev);
1075 netif_stop_queue(ndev);
1076
1077
1078 if (dev->tx_done_idx != tx_done_idx) {
1079 dprintk("restart queue(%p)\n", ndev);
1080 netif_start_queue(ndev);
1081 goto again;
1082 }
1083 return NETDEV_TX_BUSY;
1084 }
1085
1086 if (free_idx == dev->tx_intr_idx) {
1087 do_intr = 1;
1088 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1089 }
1090
1091 nr_free -= nr_frags;
1092 if (nr_free < MIN_TX_DESC_FREE) {
1093 dprintk("stop_queue - last entry(%p)\n", ndev);
1094 netif_stop_queue(ndev);
1095 stopped = 1;
1096 }
1097
1098 frag = skb_shinfo(skb)->frags;
1099 if (!nr_frags)
1100 frag = NULL;
1101 extsts = 0;
1102 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1103 extsts |= EXTSTS_IPPKT;
1104 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1105 extsts |= EXTSTS_TCPPKT;
1106 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1107 extsts |= EXTSTS_UDPPKT;
1108 }
1109
1110 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1111 if (skb_vlan_tag_present(skb)) {
1112
1113
1114
1115
1116 short tag = skb_vlan_tag_get(skb);
1117 extsts |= (EXTSTS_VPKT | htons(tag));
1118 }
1119 #endif
1120
1121 len = skb->len;
1122 if (nr_frags)
1123 len -= skb->data_len;
1124 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1125
1126 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1127
1128 for (;;) {
1129 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1130
1131 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1132 (unsigned long long)buf);
1133 last_idx = free_idx;
1134 free_idx = (free_idx + 1) % NR_TX_DESC;
1135 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1136 desc_addr_set(desc + DESC_BUFPTR, buf);
1137 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1138
1139 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1140 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1141 cmdsts |= len;
1142 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1143
1144 if (!nr_frags)
1145 break;
1146
1147 buf = skb_frag_dma_map(&dev->pci_dev->dev, frag, 0,
1148 skb_frag_size(frag), DMA_TO_DEVICE);
1149 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1150 (long long)buf, (long) page_to_pfn(frag->page),
1151 frag->page_offset);
1152 len = skb_frag_size(frag);
1153 frag++;
1154 nr_frags--;
1155 }
1156 dprintk("done pkt\n");
1157
1158 spin_lock_irq(&dev->tx_lock);
1159 dev->tx_skbs[last_idx] = skb;
1160 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1161 dev->tx_free_idx = free_idx;
1162 atomic_inc(&dev->nr_tx_skbs);
1163 spin_unlock_irq(&dev->tx_lock);
1164
1165 kick_tx(dev);
1166
1167
1168 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1169 netif_start_queue(ndev);
1170
1171 return NETDEV_TX_OK;
1172 }
1173
1174 static void ns83820_update_stats(struct ns83820 *dev)
1175 {
1176 struct net_device *ndev = dev->ndev;
1177 u8 __iomem *base = dev->base;
1178
1179
1180 ndev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1181 ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1182 ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1183 ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1184 readl(base + 0x70);
1185 ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1186 ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1187 readl(base + 0x7c);
1188 readl(base + 0x80);
1189 readl(base + 0x84);
1190 ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1191 }
1192
1193 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1194 {
1195 struct ns83820 *dev = PRIV(ndev);
1196
1197
1198 spin_lock_irq(&dev->misc_lock);
1199 ns83820_update_stats(dev);
1200 spin_unlock_irq(&dev->misc_lock);
1201
1202 return &ndev->stats;
1203 }
1204
1205
1206 static int ns83820_get_link_ksettings(struct net_device *ndev,
1207 struct ethtool_link_ksettings *cmd)
1208 {
1209 struct ns83820 *dev = PRIV(ndev);
1210 u32 cfg, tanar, tbicr;
1211 int fullduplex = 0;
1212 u32 supported;
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1229 tanar = readl(dev->base + TANAR);
1230 tbicr = readl(dev->base + TBICR);
1231
1232 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1233
1234 supported = SUPPORTED_Autoneg;
1235
1236 if (dev->CFG_cache & CFG_TBI_EN) {
1237
1238 supported |= SUPPORTED_1000baseT_Half |
1239 SUPPORTED_1000baseT_Full |
1240 SUPPORTED_FIBRE;
1241 cmd->base.port = PORT_FIBRE;
1242 } else {
1243
1244 supported |= SUPPORTED_10baseT_Half |
1245 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
1246 SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half |
1247 SUPPORTED_1000baseT_Full |
1248 SUPPORTED_MII;
1249 cmd->base.port = PORT_MII;
1250 }
1251
1252 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1253 supported);
1254
1255 cmd->base.duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1256 switch (cfg / CFG_SPDSTS0 & 3) {
1257 case 2:
1258 cmd->base.speed = SPEED_1000;
1259 break;
1260 case 1:
1261 cmd->base.speed = SPEED_100;
1262 break;
1263 default:
1264 cmd->base.speed = SPEED_10;
1265 break;
1266 }
1267 cmd->base.autoneg = (tbicr & TBICR_MR_AN_ENABLE)
1268 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1269 return 0;
1270 }
1271
1272
1273 static int ns83820_set_link_ksettings(struct net_device *ndev,
1274 const struct ethtool_link_ksettings *cmd)
1275 {
1276 struct ns83820 *dev = PRIV(ndev);
1277 u32 cfg, tanar;
1278 int have_optical = 0;
1279 int fullduplex = 0;
1280
1281
1282 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1283 tanar = readl(dev->base + TANAR);
1284
1285 if (dev->CFG_cache & CFG_TBI_EN) {
1286
1287 have_optical = 1;
1288 fullduplex = (tanar & TANAR_FULL_DUP);
1289
1290 } else {
1291
1292 fullduplex = cfg & CFG_DUPSTS;
1293 }
1294
1295 spin_lock_irq(&dev->misc_lock);
1296 spin_lock(&dev->tx_lock);
1297
1298
1299 if (cmd->base.duplex != fullduplex) {
1300 if (have_optical) {
1301
1302 if (cmd->base.duplex == DUPLEX_FULL) {
1303
1304 writel(readl(dev->base + TXCFG)
1305 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
1306 dev->base + TXCFG);
1307 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1308 dev->base + RXCFG);
1309
1310 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1311 dev->base + GPIOR);
1312 } else {
1313
1314 }
1315
1316 } else {
1317
1318
1319 }
1320 printk(KERN_INFO "%s: Duplex set via ethtool\n",
1321 ndev->name);
1322 }
1323
1324
1325 if (1) {
1326 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1327
1328 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1329 dev->base + TBICR);
1330 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1331 dev->linkstate = LINK_AUTONEGOTIATE;
1332
1333 printk(KERN_INFO "%s: autoneg enabled via ethtool\n",
1334 ndev->name);
1335 } else {
1336
1337 writel(0x00000000, dev->base + TBICR);
1338 }
1339
1340 printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
1341 cmd->base.autoneg ? "ENABLED" : "DISABLED");
1342 }
1343
1344 phy_intr(ndev);
1345 spin_unlock(&dev->tx_lock);
1346 spin_unlock_irq(&dev->misc_lock);
1347
1348 return 0;
1349 }
1350
1351
1352 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1353 {
1354 struct ns83820 *dev = PRIV(ndev);
1355 strlcpy(info->driver, "ns83820", sizeof(info->driver));
1356 strlcpy(info->version, VERSION, sizeof(info->version));
1357 strlcpy(info->bus_info, pci_name(dev->pci_dev), sizeof(info->bus_info));
1358 }
1359
1360 static u32 ns83820_get_link(struct net_device *ndev)
1361 {
1362 struct ns83820 *dev = PRIV(ndev);
1363 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1364 return cfg & CFG_LNKSTS ? 1 : 0;
1365 }
1366
1367 static const struct ethtool_ops ops = {
1368 .get_drvinfo = ns83820_get_drvinfo,
1369 .get_link = ns83820_get_link,
1370 .get_link_ksettings = ns83820_get_link_ksettings,
1371 .set_link_ksettings = ns83820_set_link_ksettings,
1372 };
1373
1374 static inline void ns83820_disable_interrupts(struct ns83820 *dev)
1375 {
1376 writel(0, dev->base + IMR);
1377 writel(0, dev->base + IER);
1378 readl(dev->base + IER);
1379 }
1380
1381
1382 static void ns83820_mib_isr(struct ns83820 *dev)
1383 {
1384 unsigned long flags;
1385 spin_lock_irqsave(&dev->misc_lock, flags);
1386 ns83820_update_stats(dev);
1387 spin_unlock_irqrestore(&dev->misc_lock, flags);
1388 }
1389
1390 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1391 static irqreturn_t ns83820_irq(int foo, void *data)
1392 {
1393 struct net_device *ndev = data;
1394 struct ns83820 *dev = PRIV(ndev);
1395 u32 isr;
1396 dprintk("ns83820_irq(%p)\n", ndev);
1397
1398 dev->ihr = 0;
1399
1400 isr = readl(dev->base + ISR);
1401 dprintk("irq: %08x\n", isr);
1402 ns83820_do_isr(ndev, isr);
1403 return IRQ_HANDLED;
1404 }
1405
1406 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1407 {
1408 struct ns83820 *dev = PRIV(ndev);
1409 unsigned long flags;
1410
1411 #ifdef DEBUG
1412 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1413 Dprintk("odd isr? 0x%08x\n", isr);
1414 #endif
1415
1416 if (ISR_RXIDLE & isr) {
1417 dev->rx_info.idle = 1;
1418 Dprintk("oh dear, we are idle\n");
1419 ns83820_rx_kick(ndev);
1420 }
1421
1422 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1423 prefetch(dev->rx_info.next_rx_desc);
1424
1425 spin_lock_irqsave(&dev->misc_lock, flags);
1426 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1427 writel(dev->IMR_cache, dev->base + IMR);
1428 spin_unlock_irqrestore(&dev->misc_lock, flags);
1429
1430 tasklet_schedule(&dev->rx_tasklet);
1431
1432
1433 }
1434
1435 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1436 ns83820_rx_kick(ndev);
1437
1438 if (unlikely(ISR_RXSOVR & isr)) {
1439
1440 ndev->stats.rx_fifo_errors++;
1441 }
1442
1443 if (unlikely(ISR_RXORN & isr)) {
1444
1445 ndev->stats.rx_fifo_errors++;
1446 }
1447
1448 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1449 writel(CR_RXE, dev->base + CR);
1450
1451 if (ISR_TXIDLE & isr) {
1452 u32 txdp;
1453 txdp = readl(dev->base + TXDP);
1454 dprintk("txdp: %08x\n", txdp);
1455 txdp -= dev->tx_phy_descs;
1456 dev->tx_idx = txdp / (DESC_SIZE * 4);
1457 if (dev->tx_idx >= NR_TX_DESC) {
1458 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1459 dev->tx_idx = 0;
1460 }
1461
1462
1463
1464
1465
1466 if (dev->tx_idx != dev->tx_free_idx)
1467 kick_tx(dev);
1468 }
1469
1470
1471
1472
1473 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1474 spin_lock_irqsave(&dev->tx_lock, flags);
1475 do_tx_done(ndev);
1476 spin_unlock_irqrestore(&dev->tx_lock, flags);
1477
1478
1479
1480 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1481 (dev->IMR_cache & ISR_TXOK)) {
1482 spin_lock_irqsave(&dev->misc_lock, flags);
1483 dev->IMR_cache &= ~ISR_TXOK;
1484 writel(dev->IMR_cache, dev->base + IMR);
1485 spin_unlock_irqrestore(&dev->misc_lock, flags);
1486 }
1487 }
1488
1489
1490
1491
1492
1493
1494
1495 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1496 spin_lock_irqsave(&dev->misc_lock, flags);
1497 dev->IMR_cache |= ISR_TXOK;
1498 writel(dev->IMR_cache, dev->base + IMR);
1499 spin_unlock_irqrestore(&dev->misc_lock, flags);
1500 }
1501
1502
1503 if (unlikely(ISR_MIB & isr))
1504 ns83820_mib_isr(dev);
1505
1506
1507 if (unlikely(ISR_PHY & isr))
1508 phy_intr(ndev);
1509
1510 #if 0
1511 if (dev->ihr)
1512 writel(dev->ihr, dev->base + IHR);
1513 #endif
1514 }
1515
1516 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1517 {
1518 Dprintk("resetting chip...\n");
1519 writel(which, dev->base + CR);
1520 do {
1521 schedule();
1522 } while (readl(dev->base + CR) & which);
1523 Dprintk("okay!\n");
1524 }
1525
1526 static int ns83820_stop(struct net_device *ndev)
1527 {
1528 struct ns83820 *dev = PRIV(ndev);
1529
1530
1531 del_timer_sync(&dev->tx_watchdog);
1532
1533 ns83820_disable_interrupts(dev);
1534
1535 dev->rx_info.up = 0;
1536 synchronize_irq(dev->pci_dev->irq);
1537
1538 ns83820_do_reset(dev, CR_RST);
1539
1540 synchronize_irq(dev->pci_dev->irq);
1541
1542 spin_lock_irq(&dev->misc_lock);
1543 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1544 spin_unlock_irq(&dev->misc_lock);
1545
1546 ns83820_cleanup_rx(dev);
1547 ns83820_cleanup_tx(dev);
1548
1549 return 0;
1550 }
1551
1552 static void ns83820_tx_timeout(struct net_device *ndev)
1553 {
1554 struct ns83820 *dev = PRIV(ndev);
1555 u32 tx_done_idx;
1556 __le32 *desc;
1557 unsigned long flags;
1558
1559 spin_lock_irqsave(&dev->tx_lock, flags);
1560
1561 tx_done_idx = dev->tx_done_idx;
1562 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1563
1564 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1565 ndev->name,
1566 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1567
1568 #if defined(DEBUG)
1569 {
1570 u32 isr;
1571 isr = readl(dev->base + ISR);
1572 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1573 ns83820_do_isr(ndev, isr);
1574 }
1575 #endif
1576
1577 do_tx_done(ndev);
1578
1579 tx_done_idx = dev->tx_done_idx;
1580 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1581
1582 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1583 ndev->name,
1584 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1585
1586 spin_unlock_irqrestore(&dev->tx_lock, flags);
1587 }
1588
1589 static void ns83820_tx_watch(struct timer_list *t)
1590 {
1591 struct ns83820 *dev = from_timer(dev, t, tx_watchdog);
1592 struct net_device *ndev = dev->ndev;
1593
1594 #if defined(DEBUG)
1595 printk("ns83820_tx_watch: %u %u %d\n",
1596 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1597 );
1598 #endif
1599
1600 if (time_after(jiffies, dev_trans_start(ndev) + 1*HZ) &&
1601 dev->tx_done_idx != dev->tx_free_idx) {
1602 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1603 ndev->name,
1604 dev->tx_done_idx, dev->tx_free_idx,
1605 atomic_read(&dev->nr_tx_skbs));
1606 ns83820_tx_timeout(ndev);
1607 }
1608
1609 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1610 }
1611
1612 static int ns83820_open(struct net_device *ndev)
1613 {
1614 struct ns83820 *dev = PRIV(ndev);
1615 unsigned i;
1616 u32 desc;
1617 int ret;
1618
1619 dprintk("ns83820_open\n");
1620
1621 writel(0, dev->base + PQCR);
1622
1623 ret = ns83820_setup_rx(ndev);
1624 if (ret)
1625 goto failed;
1626
1627 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1628 for (i=0; i<NR_TX_DESC; i++) {
1629 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1630 = cpu_to_le32(
1631 dev->tx_phy_descs
1632 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1633 }
1634
1635 dev->tx_idx = 0;
1636 dev->tx_done_idx = 0;
1637 desc = dev->tx_phy_descs;
1638 writel(0, dev->base + TXDP_HI);
1639 writel(desc, dev->base + TXDP);
1640
1641 timer_setup(&dev->tx_watchdog, ns83820_tx_watch, 0);
1642 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1643
1644 netif_start_queue(ndev);
1645
1646 return 0;
1647
1648 failed:
1649 ns83820_stop(ndev);
1650 return ret;
1651 }
1652
1653 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1654 {
1655 unsigned i;
1656 for (i=0; i<3; i++) {
1657 u32 data;
1658
1659
1660
1661
1662 writel(i*2, dev->base + RFCR);
1663 data = readl(dev->base + RFDR);
1664
1665 *mac++ = data;
1666 *mac++ = data >> 8;
1667 }
1668 }
1669
1670 static void ns83820_set_multicast(struct net_device *ndev)
1671 {
1672 struct ns83820 *dev = PRIV(ndev);
1673 u8 __iomem *rfcr = dev->base + RFCR;
1674 u32 and_mask = 0xffffffff;
1675 u32 or_mask = 0;
1676 u32 val;
1677
1678 if (ndev->flags & IFF_PROMISC)
1679 or_mask |= RFCR_AAU | RFCR_AAM;
1680 else
1681 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1682
1683 if (ndev->flags & IFF_ALLMULTI || netdev_mc_count(ndev))
1684 or_mask |= RFCR_AAM;
1685 else
1686 and_mask &= ~RFCR_AAM;
1687
1688 spin_lock_irq(&dev->misc_lock);
1689 val = (readl(rfcr) & and_mask) | or_mask;
1690
1691 writel(val & ~RFCR_RFEN, rfcr);
1692 writel(val, rfcr);
1693 spin_unlock_irq(&dev->misc_lock);
1694 }
1695
1696 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1697 {
1698 struct ns83820 *dev = PRIV(ndev);
1699 int timed_out = 0;
1700 unsigned long start;
1701 u32 status;
1702 int loops = 0;
1703
1704 dprintk("%s: start %s\n", ndev->name, name);
1705
1706 start = jiffies;
1707
1708 writel(enable, dev->base + PTSCR);
1709 for (;;) {
1710 loops++;
1711 status = readl(dev->base + PTSCR);
1712 if (!(status & enable))
1713 break;
1714 if (status & done)
1715 break;
1716 if (status & fail)
1717 break;
1718 if (time_after_eq(jiffies, start + HZ)) {
1719 timed_out = 1;
1720 break;
1721 }
1722 schedule_timeout_uninterruptible(1);
1723 }
1724
1725 if (status & fail)
1726 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1727 ndev->name, name, status, fail);
1728 else if (timed_out)
1729 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1730 ndev->name, name, status);
1731
1732 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1733 }
1734
1735 #ifdef PHY_CODE_IS_FINISHED
1736 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1737 {
1738
1739 dev->MEAR_cache &= ~MEAR_MDC;
1740 writel(dev->MEAR_cache, dev->base + MEAR);
1741 readl(dev->base + MEAR);
1742
1743
1744 dev->MEAR_cache |= MEAR_MDDIR;
1745 if (bit)
1746 dev->MEAR_cache |= MEAR_MDIO;
1747 else
1748 dev->MEAR_cache &= ~MEAR_MDIO;
1749
1750
1751 writel(dev->MEAR_cache, dev->base + MEAR);
1752 readl(dev->base + MEAR);
1753
1754
1755 udelay(1);
1756
1757
1758 dev->MEAR_cache |= MEAR_MDC;
1759 writel(dev->MEAR_cache, dev->base + MEAR);
1760 readl(dev->base + MEAR);
1761
1762
1763 udelay(1);
1764 }
1765
1766 static int ns83820_mii_read_bit(struct ns83820 *dev)
1767 {
1768 int bit;
1769
1770
1771 dev->MEAR_cache &= ~MEAR_MDC;
1772 dev->MEAR_cache &= ~MEAR_MDDIR;
1773 writel(dev->MEAR_cache, dev->base + MEAR);
1774 readl(dev->base + MEAR);
1775
1776
1777 udelay(1);
1778
1779
1780 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1781 dev->MEAR_cache |= MEAR_MDC;
1782 writel(dev->MEAR_cache, dev->base + MEAR);
1783
1784
1785 udelay(1);
1786
1787 return bit;
1788 }
1789
1790 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1791 {
1792 unsigned data = 0;
1793 int i;
1794
1795
1796 for (i=0; i<64; i++)
1797 ns83820_mii_read_bit(dev);
1798
1799 ns83820_mii_write_bit(dev, 0);
1800 ns83820_mii_write_bit(dev, 1);
1801 ns83820_mii_write_bit(dev, 1);
1802 ns83820_mii_write_bit(dev, 0);
1803
1804
1805 for (i=0; i<5; i++)
1806 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1807
1808
1809 for (i=0; i<5; i++)
1810 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1811
1812 ns83820_mii_read_bit(dev);
1813 ns83820_mii_read_bit(dev);
1814
1815
1816 for (i=0; i<16; i++) {
1817 data <<= 1;
1818 data |= ns83820_mii_read_bit(dev);
1819 }
1820
1821 return data;
1822 }
1823
1824 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1825 {
1826 int i;
1827
1828
1829 for (i=0; i<64; i++)
1830 ns83820_mii_read_bit(dev);
1831
1832 ns83820_mii_write_bit(dev, 0);
1833 ns83820_mii_write_bit(dev, 1);
1834 ns83820_mii_write_bit(dev, 0);
1835 ns83820_mii_write_bit(dev, 1);
1836
1837
1838 for (i=0; i<5; i++)
1839 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1840
1841
1842 for (i=0; i<5; i++)
1843 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1844
1845 ns83820_mii_read_bit(dev);
1846 ns83820_mii_read_bit(dev);
1847
1848
1849 for (i=0; i<16; i++)
1850 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1851
1852 return data;
1853 }
1854
1855 static void ns83820_probe_phy(struct net_device *ndev)
1856 {
1857 struct ns83820 *dev = PRIV(ndev);
1858 int j;
1859 unsigned a, b;
1860
1861 for (j = 0; j < 0x16; j += 4) {
1862 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1863 ndev->name, j,
1864 ns83820_mii_read_reg(dev, 1, 0 + j),
1865 ns83820_mii_read_reg(dev, 1, 1 + j),
1866 ns83820_mii_read_reg(dev, 1, 2 + j),
1867 ns83820_mii_read_reg(dev, 1, 3 + j)
1868 );
1869 }
1870
1871
1872 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1873 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1874 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1875
1876 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1877 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1878 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1879 dprintk("version: 0x%04x 0x%04x\n", a, b);
1880 }
1881 #endif
1882
1883 static const struct net_device_ops netdev_ops = {
1884 .ndo_open = ns83820_open,
1885 .ndo_stop = ns83820_stop,
1886 .ndo_start_xmit = ns83820_hard_start_xmit,
1887 .ndo_get_stats = ns83820_get_stats,
1888 .ndo_set_rx_mode = ns83820_set_multicast,
1889 .ndo_validate_addr = eth_validate_addr,
1890 .ndo_set_mac_address = eth_mac_addr,
1891 .ndo_tx_timeout = ns83820_tx_timeout,
1892 };
1893
1894 static int ns83820_init_one(struct pci_dev *pci_dev,
1895 const struct pci_device_id *id)
1896 {
1897 struct net_device *ndev;
1898 struct ns83820 *dev;
1899 long addr;
1900 int err;
1901 int using_dac = 0;
1902
1903
1904 if (sizeof(dma_addr_t) == 8 &&
1905 !pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) {
1906 using_dac = 1;
1907 } else if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) {
1908 using_dac = 0;
1909 } else {
1910 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1911 return -ENODEV;
1912 }
1913
1914 ndev = alloc_etherdev(sizeof(struct ns83820));
1915 err = -ENOMEM;
1916 if (!ndev)
1917 goto out;
1918
1919 dev = PRIV(ndev);
1920 dev->ndev = ndev;
1921
1922 spin_lock_init(&dev->rx_info.lock);
1923 spin_lock_init(&dev->tx_lock);
1924 spin_lock_init(&dev->misc_lock);
1925 dev->pci_dev = pci_dev;
1926
1927 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1928
1929 INIT_WORK(&dev->tq_refill, queue_refill);
1930 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1931
1932 err = pci_enable_device(pci_dev);
1933 if (err) {
1934 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1935 goto out_free;
1936 }
1937
1938 pci_set_master(pci_dev);
1939 addr = pci_resource_start(pci_dev, 1);
1940 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1941 dev->tx_descs = pci_alloc_consistent(pci_dev,
1942 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1943 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1944 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1945 err = -ENOMEM;
1946 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1947 goto out_disable;
1948
1949 dprintk("%p: %08lx %p: %08lx\n",
1950 dev->tx_descs, (long)dev->tx_phy_descs,
1951 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1952
1953 ns83820_disable_interrupts(dev);
1954
1955 dev->IMR_cache = 0;
1956
1957 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
1958 DRV_NAME, ndev);
1959 if (err) {
1960 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
1961 pci_dev->irq, err);
1962 goto out_disable;
1963 }
1964
1965
1966
1967
1968
1969
1970
1971
1972 rtnl_lock();
1973 err = dev_alloc_name(ndev, ndev->name);
1974 if (err < 0) {
1975 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1976 goto out_free_irq;
1977 }
1978
1979 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1980 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1981 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1982
1983 ndev->netdev_ops = &netdev_ops;
1984 ndev->ethtool_ops = &ops;
1985 ndev->watchdog_timeo = 5 * HZ;
1986 pci_set_drvdata(pci_dev, ndev);
1987
1988 ns83820_do_reset(dev, CR_RST);
1989
1990
1991 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1992 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1993 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1994 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1995 PTSCR_EEBIST_FAIL);
1996 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1997
1998
1999 dev->CFG_cache = readl(dev->base + CFG);
2000
2001 if ((dev->CFG_cache & CFG_PCI64_DET)) {
2002 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
2003 ndev->name);
2004
2005 if (!(dev->CFG_cache & CFG_DATA64_EN))
2006 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
2007 ndev->name);
2008 } else
2009 dev->CFG_cache &= ~(CFG_DATA64_EN);
2010
2011 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
2012 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
2013 CFG_M64ADDR);
2014 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2015 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
2016 dev->CFG_cache |= CFG_REQALG;
2017 dev->CFG_cache |= CFG_POW;
2018 dev->CFG_cache |= CFG_TMRTEST;
2019
2020
2021
2022
2023 if (sizeof(dma_addr_t) == 8)
2024 dev->CFG_cache |= CFG_M64ADDR;
2025 if (using_dac)
2026 dev->CFG_cache |= CFG_T64ADDR;
2027
2028
2029 dev->CFG_cache &= ~CFG_BEM;
2030
2031
2032 if (dev->CFG_cache & CFG_TBI_EN) {
2033 printk(KERN_INFO "%s: enabling optical transceiver\n",
2034 ndev->name);
2035 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2036
2037
2038 writel(readl(dev->base + TANAR)
2039 | TANAR_HALF_DUP | TANAR_FULL_DUP,
2040 dev->base + TANAR);
2041
2042
2043 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
2044 dev->base + TBICR);
2045 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2046 dev->linkstate = LINK_AUTONEGOTIATE;
2047
2048 dev->CFG_cache |= CFG_MODE_1000;
2049 }
2050
2051 writel(dev->CFG_cache, dev->base + CFG);
2052 dprintk("CFG: %08x\n", dev->CFG_cache);
2053
2054 if (reset_phy) {
2055 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2056 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2057 msleep(10);
2058 writel(dev->CFG_cache, dev->base + CFG);
2059 }
2060
2061 #if 0
2062
2063
2064 if (readl(dev->base + SRR))
2065 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2066 #endif
2067
2068
2069
2070
2071
2072
2073
2074
2075 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2076 | ((1600 / 32) * 0x100),
2077 dev->base + TXCFG);
2078
2079
2080 writel(0x000, dev->base + IHR);
2081 writel(0x100, dev->base + IHR);
2082 writel(0x000, dev->base + IHR);
2083
2084
2085
2086
2087
2088
2089
2090 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2091 | RXCFG_STRIPCRC
2092
2093 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2094
2095
2096 writel(0, dev->base + PQCR);
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2112 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2113 #else
2114 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2115 #endif
2116 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2117
2118
2119
2120
2121
2122 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2123 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2124 #else
2125 #define VTCR_INIT_VALUE VTCR_PPCHK
2126 #endif
2127 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2128
2129
2130
2131 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2132 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2133 dev->base + PCR);
2134
2135
2136 writel(0, dev->base + WCSR);
2137
2138 ns83820_getmac(dev, ndev->dev_addr);
2139
2140
2141 ndev->features |= NETIF_F_SG;
2142 ndev->features |= NETIF_F_IP_CSUM;
2143
2144 ndev->min_mtu = 0;
2145
2146 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2147
2148 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
2149 #endif
2150
2151 if (using_dac) {
2152 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2153 ndev->name);
2154 ndev->features |= NETIF_F_HIGHDMA;
2155 }
2156
2157 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n",
2158 ndev->name,
2159 (unsigned)readl(dev->base + SRR) >> 8,
2160 (unsigned)readl(dev->base + SRR) & 0xff,
2161 ndev->dev_addr, addr, pci_dev->irq,
2162 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2163 );
2164
2165 #ifdef PHY_CODE_IS_FINISHED
2166 ns83820_probe_phy(ndev);
2167 #endif
2168
2169 err = register_netdevice(ndev);
2170 if (err) {
2171 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2172 goto out_cleanup;
2173 }
2174 rtnl_unlock();
2175
2176 return 0;
2177
2178 out_cleanup:
2179 ns83820_disable_interrupts(dev);
2180 out_free_irq:
2181 rtnl_unlock();
2182 free_irq(pci_dev->irq, ndev);
2183 out_disable:
2184 if (dev->base)
2185 iounmap(dev->base);
2186 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2187 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2188 pci_disable_device(pci_dev);
2189 out_free:
2190 free_netdev(ndev);
2191 out:
2192 return err;
2193 }
2194
2195 static void ns83820_remove_one(struct pci_dev *pci_dev)
2196 {
2197 struct net_device *ndev = pci_get_drvdata(pci_dev);
2198 struct ns83820 *dev = PRIV(ndev);
2199
2200 if (!ndev)
2201 return;
2202
2203 ns83820_disable_interrupts(dev);
2204
2205 unregister_netdev(ndev);
2206 free_irq(dev->pci_dev->irq, ndev);
2207 iounmap(dev->base);
2208 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2209 dev->tx_descs, dev->tx_phy_descs);
2210 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2211 dev->rx_info.descs, dev->rx_info.phy_descs);
2212 pci_disable_device(dev->pci_dev);
2213 free_netdev(ndev);
2214 }
2215
2216 static const struct pci_device_id ns83820_pci_tbl[] = {
2217 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2218 { 0, },
2219 };
2220
2221 static struct pci_driver driver = {
2222 .name = "ns83820",
2223 .id_table = ns83820_pci_tbl,
2224 .probe = ns83820_init_one,
2225 .remove = ns83820_remove_one,
2226 #if 0
2227 .suspend = ,
2228 .resume = ,
2229 #endif
2230 };
2231
2232
2233 static int __init ns83820_init(void)
2234 {
2235 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2236 return pci_register_driver(&driver);
2237 }
2238
2239 static void __exit ns83820_exit(void)
2240 {
2241 pci_unregister_driver(&driver);
2242 }
2243
2244 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2245 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2246 MODULE_LICENSE("GPL");
2247
2248 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2249
2250 module_param(lnksts, int, 0);
2251 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2252
2253 module_param(ihr, int, 0);
2254 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2255
2256 module_param(reset_phy, int, 0);
2257 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2258
2259 module_init(ns83820_init);
2260 module_exit(ns83820_exit);