This source file includes following definitions.
- bnxt_tx_avail
- bnxt_db_write_relaxed
- bnxt_db_write
- bnxt_cfa_hwrm_message
- bnxt_kong_hwrm_message
- bnxt_hwrm_kong_chnl
- bnxt_get_hwrm_resp_addr
- bnxt_get_hwrm_seq_id
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11 #ifndef BNXT_H
12 #define BNXT_H
13
14 #define DRV_MODULE_NAME "bnxt_en"
15 #define DRV_MODULE_VERSION "1.10.0"
16
17 #define DRV_VER_MAJ 1
18 #define DRV_VER_MIN 10
19 #define DRV_VER_UPD 0
20
21 #include <linux/interrupt.h>
22 #include <linux/rhashtable.h>
23 #include <linux/crash_dump.h>
24 #include <net/devlink.h>
25 #include <net/dst_metadata.h>
26 #include <net/xdp.h>
27 #include <linux/dim.h>
28
29 struct page_pool;
30
31 struct tx_bd {
32 __le32 tx_bd_len_flags_type;
33 #define TX_BD_TYPE (0x3f << 0)
34 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
35 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
36 #define TX_BD_FLAGS_PACKET_END (1 << 6)
37 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
38 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
39 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
40 #define TX_BD_FLAGS_LHINT (3 << 13)
41 #define TX_BD_FLAGS_LHINT_SHIFT 13
42 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
43 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
44 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
45 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
46 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
47 #define TX_BD_LEN (0xffff << 16)
48 #define TX_BD_LEN_SHIFT 16
49
50 u32 tx_bd_opaque;
51 __le64 tx_bd_haddr;
52 } __packed;
53
54 struct tx_bd_ext {
55 __le32 tx_bd_hsize_lflags;
56 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
57 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
58 #define TX_BD_FLAGS_NO_CRC (1 << 2)
59 #define TX_BD_FLAGS_STAMP (1 << 3)
60 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
61 #define TX_BD_FLAGS_LSO (1 << 5)
62 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
63 #define TX_BD_FLAGS_T_IPID (1 << 7)
64 #define TX_BD_HSIZE (0xff << 16)
65 #define TX_BD_HSIZE_SHIFT 16
66
67 __le32 tx_bd_mss;
68 __le32 tx_bd_cfa_action;
69 #define TX_BD_CFA_ACTION (0xffff << 16)
70 #define TX_BD_CFA_ACTION_SHIFT 16
71
72 __le32 tx_bd_cfa_meta;
73 #define TX_BD_CFA_META_MASK 0xfffffff
74 #define TX_BD_CFA_META_VID_MASK 0xfff
75 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
76 #define TX_BD_CFA_META_PRI_SHIFT 12
77 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
78 #define TX_BD_CFA_META_TPID_SHIFT 16
79 #define TX_BD_CFA_META_KEY (0xf << 28)
80 #define TX_BD_CFA_META_KEY_SHIFT 28
81 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
82 };
83
84 struct rx_bd {
85 __le32 rx_bd_len_flags_type;
86 #define RX_BD_TYPE (0x3f << 0)
87 #define RX_BD_TYPE_RX_PACKET_BD 0x4
88 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
89 #define RX_BD_TYPE_RX_AGG_BD 0x6
90 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
91 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
92 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
93 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
94 #define RX_BD_FLAGS_SOP (1 << 6)
95 #define RX_BD_FLAGS_EOP (1 << 7)
96 #define RX_BD_FLAGS_BUFFERS (3 << 8)
97 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
98 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
99 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
100 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
101 #define RX_BD_LEN (0xffff << 16)
102 #define RX_BD_LEN_SHIFT 16
103
104 u32 rx_bd_opaque;
105 __le64 rx_bd_haddr;
106 };
107
108 struct tx_cmp {
109 __le32 tx_cmp_flags_type;
110 #define CMP_TYPE (0x3f << 0)
111 #define CMP_TYPE_TX_L2_CMP 0
112 #define CMP_TYPE_RX_L2_CMP 17
113 #define CMP_TYPE_RX_AGG_CMP 18
114 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
115 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
116 #define CMP_TYPE_RX_TPA_AGG_CMP 22
117 #define CMP_TYPE_STATUS_CMP 32
118 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
119 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
120 #define CMP_TYPE_ERROR_STATUS 48
121 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
122 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
123 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
124 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
125 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
126
127 #define TX_CMP_FLAGS_ERROR (1 << 6)
128 #define TX_CMP_FLAGS_PUSH (1 << 7)
129
130 u32 tx_cmp_opaque;
131 __le32 tx_cmp_errors_v;
132 #define TX_CMP_V (1 << 0)
133 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
134 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
135 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
136 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
137 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
138 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
139 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
140 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
141 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
142
143 __le32 tx_cmp_unsed_3;
144 };
145
146 struct rx_cmp {
147 __le32 rx_cmp_len_flags_type;
148 #define RX_CMP_CMP_TYPE (0x3f << 0)
149 #define RX_CMP_FLAGS_ERROR (1 << 6)
150 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
151 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
152 #define RX_CMP_FLAGS_UNUSED (1 << 11)
153 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
154 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
155 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
156 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
157 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
158 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
159 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
160 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
161 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
162 #define RX_CMP_LEN (0xffff << 16)
163 #define RX_CMP_LEN_SHIFT 16
164
165 u32 rx_cmp_opaque;
166 __le32 rx_cmp_misc_v1;
167 #define RX_CMP_V1 (1 << 0)
168 #define RX_CMP_AGG_BUFS (0x1f << 1)
169 #define RX_CMP_AGG_BUFS_SHIFT 1
170 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
171 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
172 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
173 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
174
175 __le32 rx_cmp_rss_hash;
176 };
177
178 #define RX_CMP_HASH_VALID(rxcmp) \
179 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
180
181 #define RSS_PROFILE_ID_MASK 0x1f
182
183 #define RX_CMP_HASH_TYPE(rxcmp) \
184 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
185 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
186
187 struct rx_cmp_ext {
188 __le32 rx_cmp_flags2;
189 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
190 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
191 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
192 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
193 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
194 __le32 rx_cmp_meta_data;
195 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
196 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
197 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
198 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
199 __le32 rx_cmp_cfa_code_errors_v2;
200 #define RX_CMP_V (1 << 0)
201 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
202 #define RX_CMPL_ERRORS_SFT 1
203 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
204 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
205 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
206 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
207 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
208 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
209 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
210 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
211 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
212 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
213 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
214 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
215 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
216 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
217 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
218 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
219 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
220 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
221 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
222 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
223 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
224 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
225 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
226 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
227 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
228 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
229 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
230 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
231
232 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
233 #define RX_CMPL_CFA_CODE_SFT 16
234
235 __le32 rx_cmp_unused3;
236 };
237
238 #define RX_CMP_L2_ERRORS \
239 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
240
241 #define RX_CMP_L4_CS_BITS \
242 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
243
244 #define RX_CMP_L4_CS_ERR_BITS \
245 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
246
247 #define RX_CMP_L4_CS_OK(rxcmp1) \
248 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
249 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
250
251 #define RX_CMP_ENCAP(rxcmp1) \
252 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
253 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
254
255 #define RX_CMP_CFA_CODE(rxcmpl1) \
256 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
257 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
258
259 struct rx_agg_cmp {
260 __le32 rx_agg_cmp_len_flags_type;
261 #define RX_AGG_CMP_TYPE (0x3f << 0)
262 #define RX_AGG_CMP_LEN (0xffff << 16)
263 #define RX_AGG_CMP_LEN_SHIFT 16
264 u32 rx_agg_cmp_opaque;
265 __le32 rx_agg_cmp_v;
266 #define RX_AGG_CMP_V (1 << 0)
267 #define RX_AGG_CMP_AGG_ID (0xffff << 16)
268 #define RX_AGG_CMP_AGG_ID_SHIFT 16
269 __le32 rx_agg_cmp_unused;
270 };
271
272 #define TPA_AGG_AGG_ID(rx_agg) \
273 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
274 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
275
276 struct rx_tpa_start_cmp {
277 __le32 rx_tpa_start_cmp_len_flags_type;
278 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
279 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
280 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
281 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
282 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
283 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
284 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
285 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
286 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
287 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
288 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
289 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
290 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
291 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
292 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
293 #define RX_TPA_START_CMP_LEN (0xffff << 16)
294 #define RX_TPA_START_CMP_LEN_SHIFT 16
295
296 u32 rx_tpa_start_cmp_opaque;
297 __le32 rx_tpa_start_cmp_misc_v1;
298 #define RX_TPA_START_CMP_V1 (0x1 << 0)
299 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
300 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
301 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
302 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
303 #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
304 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
305
306 __le32 rx_tpa_start_cmp_rss_hash;
307 };
308
309 #define TPA_START_HASH_VALID(rx_tpa_start) \
310 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
311 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
312
313 #define TPA_START_HASH_TYPE(rx_tpa_start) \
314 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
315 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
316 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
317
318 #define TPA_START_AGG_ID(rx_tpa_start) \
319 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
320 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
321
322 #define TPA_START_AGG_ID_P5(rx_tpa_start) \
323 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
324 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
325
326 #define TPA_START_ERROR(rx_tpa_start) \
327 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
328 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
329
330 struct rx_tpa_start_cmp_ext {
331 __le32 rx_tpa_start_cmp_flags2;
332 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
333 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
334 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
335 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
336 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
337 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
338 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
339 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
340 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
341 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
342
343 __le32 rx_tpa_start_cmp_metadata;
344 __le32 rx_tpa_start_cmp_cfa_code_v2;
345 #define RX_TPA_START_CMP_V2 (0x1 << 0)
346 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
347 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
348 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
349 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
350 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
351 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
352 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
353 __le32 rx_tpa_start_cmp_hdr_info;
354 };
355
356 #define TPA_START_CFA_CODE(rx_tpa_start) \
357 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
358 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
359
360 #define TPA_START_IS_IPV6(rx_tpa_start) \
361 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
362 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
363
364 #define TPA_START_ERROR_CODE(rx_tpa_start) \
365 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
366 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
367 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
368
369 struct rx_tpa_end_cmp {
370 __le32 rx_tpa_end_cmp_len_flags_type;
371 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
372 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
373 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
374 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
375 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
376 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
377 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
378 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
379 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
380 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
381 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
382 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
383 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
384 #define RX_TPA_END_CMP_LEN (0xffff << 16)
385 #define RX_TPA_END_CMP_LEN_SHIFT 16
386
387 u32 rx_tpa_end_cmp_opaque;
388 __le32 rx_tpa_end_cmp_misc_v1;
389 #define RX_TPA_END_CMP_V1 (0x1 << 0)
390 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
391 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
392 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
393 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
394 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
395 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
396 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
397 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
398 #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
399 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
400
401 __le32 rx_tpa_end_cmp_tsdelta;
402 #define RX_TPA_END_GRO_TS (0x1 << 31)
403 };
404
405 #define TPA_END_AGG_ID(rx_tpa_end) \
406 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
407 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
408
409 #define TPA_END_AGG_ID_P5(rx_tpa_end) \
410 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
411 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
412
413 #define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
414 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
415 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
416
417 #define TPA_END_AGG_BUFS(rx_tpa_end) \
418 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
419 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
420
421 #define TPA_END_TPA_SEGS(rx_tpa_end) \
422 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
423 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
424
425 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
426 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
427 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
428
429 #define TPA_END_GRO(rx_tpa_end) \
430 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
431 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
432
433 #define TPA_END_GRO_TS(rx_tpa_end) \
434 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
435 cpu_to_le32(RX_TPA_END_GRO_TS)))
436
437 struct rx_tpa_end_cmp_ext {
438 __le32 rx_tpa_end_cmp_dup_acks;
439 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
440 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
441 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
442 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
443 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
444
445 __le32 rx_tpa_end_cmp_seg_len;
446 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
447
448 __le32 rx_tpa_end_cmp_errors_v2;
449 #define RX_TPA_END_CMP_V2 (0x1 << 0)
450 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
451 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
452 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
453 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
454 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
455 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
456 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
457 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
458
459 u32 rx_tpa_end_cmp_start_opaque;
460 };
461
462 #define TPA_END_ERRORS(rx_tpa_end_ext) \
463 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
464 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
465
466 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
467 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
468 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
469 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
470
471 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
472 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
473 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
474
475 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
476 (((data1) & \
477 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
478 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
479
480 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
481 !!((data1) & \
482 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
483
484 #define EVENT_DATA1_RECOVERY_ENABLED(data1) \
485 !!((data1) & \
486 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
487
488 struct nqe_cn {
489 __le16 type;
490 #define NQ_CN_TYPE_MASK 0x3fUL
491 #define NQ_CN_TYPE_SFT 0
492 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
493 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
494 __le16 reserved16;
495 __le32 cq_handle_low;
496 __le32 v;
497 #define NQ_CN_V 0x1UL
498 __le32 cq_handle_high;
499 };
500
501 #define DB_IDX_MASK 0xffffff
502 #define DB_IDX_VALID (0x1 << 26)
503 #define DB_IRQ_DIS (0x1 << 27)
504 #define DB_KEY_TX (0x0 << 28)
505 #define DB_KEY_RX (0x1 << 28)
506 #define DB_KEY_CP (0x2 << 28)
507 #define DB_KEY_ST (0x3 << 28)
508 #define DB_KEY_TX_PUSH (0x4 << 28)
509 #define DB_LONG_TX_PUSH (0x2 << 24)
510
511 #define BNXT_MIN_ROCE_CP_RINGS 2
512 #define BNXT_MIN_ROCE_STAT_CTXS 1
513
514
515 #define DBR_INDEX_MASK 0x0000000000ffffffULL
516 #define DBR_XID_MASK 0x000fffff00000000ULL
517 #define DBR_XID_SFT 32
518 #define DBR_PATH_L2 (0x1ULL << 56)
519 #define DBR_TYPE_SQ (0x0ULL << 60)
520 #define DBR_TYPE_RQ (0x1ULL << 60)
521 #define DBR_TYPE_SRQ (0x2ULL << 60)
522 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
523 #define DBR_TYPE_CQ (0x4ULL << 60)
524 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
525 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
526 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
527 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
528 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
529 #define DBR_TYPE_NQ (0xaULL << 60)
530 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
531 #define DBR_TYPE_NULL (0xfULL << 60)
532
533 #define INVALID_HW_RING_ID ((u16)-1)
534
535
536
537
538 #if (PAGE_SHIFT < 12)
539 #define BNXT_PAGE_SHIFT 12
540 #elif (PAGE_SHIFT <= 13)
541 #define BNXT_PAGE_SHIFT PAGE_SHIFT
542 #elif (PAGE_SHIFT < 16)
543 #define BNXT_PAGE_SHIFT 13
544 #else
545 #define BNXT_PAGE_SHIFT 16
546 #endif
547
548 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
549
550
551 #if (PAGE_SHIFT > 15)
552 #define BNXT_RX_PAGE_SHIFT 15
553 #else
554 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
555 #endif
556
557 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
558
559 #define BNXT_MAX_MTU 9500
560 #define BNXT_MAX_PAGE_MODE_MTU \
561 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
562 XDP_PACKET_HEADROOM)
563
564 #define BNXT_MIN_PKT_SIZE 52
565
566 #define BNXT_DEFAULT_RX_RING_SIZE 511
567 #define BNXT_DEFAULT_TX_RING_SIZE 511
568
569 #define MAX_TPA 64
570 #define MAX_TPA_P5 256
571 #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
572 #define MAX_TPA_SEGS_P5 0x3f
573
574 #if (BNXT_PAGE_SHIFT == 16)
575 #define MAX_RX_PAGES 1
576 #define MAX_RX_AGG_PAGES 4
577 #define MAX_TX_PAGES 1
578 #define MAX_CP_PAGES 8
579 #else
580 #define MAX_RX_PAGES 8
581 #define MAX_RX_AGG_PAGES 32
582 #define MAX_TX_PAGES 8
583 #define MAX_CP_PAGES 64
584 #endif
585
586 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
587 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
588 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
589
590 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
591 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
592
593 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
594
595 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
596 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
597
598 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
599
600 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
601 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
602 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
603
604 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
605 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
606
607 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
608 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
609
610 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
611 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
612
613 #define TX_CMP_VALID(txcmp, raw_cons) \
614 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
615 !((raw_cons) & bp->cp_bit))
616
617 #define RX_CMP_VALID(rxcmp1, raw_cons) \
618 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
619 !((raw_cons) & bp->cp_bit))
620
621 #define RX_AGG_CMP_VALID(agg, raw_cons) \
622 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
623 !((raw_cons) & bp->cp_bit))
624
625 #define NQ_CMP_VALID(nqcmp, raw_cons) \
626 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
627
628 #define TX_CMP_TYPE(txcmp) \
629 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
630
631 #define RX_CMP_TYPE(rxcmp) \
632 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
633
634 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
635
636 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
637
638 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
639
640 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
641 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
642 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
643 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
644
645 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
646 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
647 #define DFLT_HWRM_CMD_TIMEOUT 500
648 #define SHORT_HWRM_CMD_TIMEOUT 20
649 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
650 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
651 #define HWRM_COREDUMP_TIMEOUT ((HWRM_CMD_TIMEOUT) * 12)
652 #define HWRM_RESP_ERR_CODE_MASK 0xffff
653 #define HWRM_RESP_LEN_OFFSET 4
654 #define HWRM_RESP_LEN_MASK 0xffff0000
655 #define HWRM_RESP_LEN_SFT 16
656 #define HWRM_RESP_VALID_MASK 0xff000000
657 #define BNXT_HWRM_REQ_MAX_SIZE 128
658 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
659 BNXT_HWRM_REQ_MAX_SIZE)
660 #define HWRM_SHORT_MIN_TIMEOUT 3
661 #define HWRM_SHORT_MAX_TIMEOUT 10
662 #define HWRM_SHORT_TIMEOUT_COUNTER 5
663
664 #define HWRM_MIN_TIMEOUT 25
665 #define HWRM_MAX_TIMEOUT 40
666
667 #define HWRM_TOTAL_TIMEOUT(n) (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ? \
668 ((n) * HWRM_SHORT_MIN_TIMEOUT) : \
669 (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT + \
670 ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
671
672 #define HWRM_VALID_BIT_DELAY_USEC 150
673
674 #define BNXT_HWRM_CHNL_CHIMP 0
675 #define BNXT_HWRM_CHNL_KONG 1
676
677 #define BNXT_RX_EVENT 1
678 #define BNXT_AGG_EVENT 2
679 #define BNXT_TX_EVENT 4
680 #define BNXT_REDIRECT_EVENT 8
681
682 struct bnxt_sw_tx_bd {
683 union {
684 struct sk_buff *skb;
685 struct xdp_frame *xdpf;
686 };
687 DEFINE_DMA_UNMAP_ADDR(mapping);
688 DEFINE_DMA_UNMAP_LEN(len);
689 u8 is_gso;
690 u8 is_push;
691 u8 action;
692 union {
693 unsigned short nr_frags;
694 u16 rx_prod;
695 };
696 };
697
698 struct bnxt_sw_rx_bd {
699 void *data;
700 u8 *data_ptr;
701 dma_addr_t mapping;
702 };
703
704 struct bnxt_sw_rx_agg_bd {
705 struct page *page;
706 unsigned int offset;
707 dma_addr_t mapping;
708 };
709
710 struct bnxt_ring_mem_info {
711 int nr_pages;
712 int page_size;
713 u16 flags;
714 #define BNXT_RMEM_VALID_PTE_FLAG 1
715 #define BNXT_RMEM_RING_PTE_FLAG 2
716 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
717
718 u16 depth;
719
720 void **pg_arr;
721 dma_addr_t *dma_arr;
722
723 __le64 *pg_tbl;
724 dma_addr_t pg_tbl_map;
725
726 int vmem_size;
727 void **vmem;
728 };
729
730 struct bnxt_ring_struct {
731 struct bnxt_ring_mem_info ring_mem;
732
733 u16 fw_ring_id;
734 union {
735 u16 grp_idx;
736 u16 map_idx;
737 };
738 u32 handle;
739 u8 queue_id;
740 };
741
742 struct tx_push_bd {
743 __le32 doorbell;
744 __le32 tx_bd_len_flags_type;
745 u32 tx_bd_opaque;
746 struct tx_bd_ext txbd2;
747 };
748
749 struct tx_push_buffer {
750 struct tx_push_bd push_bd;
751 u32 data[25];
752 };
753
754 struct bnxt_db_info {
755 void __iomem *doorbell;
756 union {
757 u64 db_key64;
758 u32 db_key32;
759 };
760 };
761
762 struct bnxt_tx_ring_info {
763 struct bnxt_napi *bnapi;
764 u16 tx_prod;
765 u16 tx_cons;
766 u16 txq_index;
767 struct bnxt_db_info tx_db;
768
769 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
770 struct bnxt_sw_tx_bd *tx_buf_ring;
771
772 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
773
774 struct tx_push_buffer *tx_push;
775 dma_addr_t tx_push_mapping;
776 __le64 data_mapping;
777
778 #define BNXT_DEV_STATE_CLOSING 0x1
779 u32 dev_state;
780
781 struct bnxt_ring_struct tx_ring_struct;
782 };
783
784 #define BNXT_LEGACY_COAL_CMPL_PARAMS \
785 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
786 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
787 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
788 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
789 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
790 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
791 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
792 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
793 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
794
795 #define BNXT_COAL_CMPL_ENABLES \
796 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
797 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
798 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
799 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
800
801 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
802 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
803
804 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
805 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
806
807 struct bnxt_coal_cap {
808 u32 cmpl_params;
809 u32 nq_params;
810 u16 num_cmpl_dma_aggr_max;
811 u16 num_cmpl_dma_aggr_during_int_max;
812 u16 cmpl_aggr_dma_tmr_max;
813 u16 cmpl_aggr_dma_tmr_during_int_max;
814 u16 int_lat_tmr_min_max;
815 u16 int_lat_tmr_max_max;
816 u16 num_cmpl_aggr_int_max;
817 u16 timer_units;
818 };
819
820 struct bnxt_coal {
821 u16 coal_ticks;
822 u16 coal_ticks_irq;
823 u16 coal_bufs;
824 u16 coal_bufs_irq;
825
826 u16 idle_thresh;
827 u8 bufs_per_record;
828 u8 budget;
829 };
830
831 struct bnxt_tpa_info {
832 void *data;
833 u8 *data_ptr;
834 dma_addr_t mapping;
835 u16 len;
836 unsigned short gso_type;
837 u32 flags2;
838 u32 metadata;
839 enum pkt_hash_types hash_type;
840 u32 rss_hash;
841 u32 hdr_info;
842
843 #define BNXT_TPA_L4_SIZE(hdr_info) \
844 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
845
846 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
847 (((hdr_info) >> 18) & 0x1ff)
848
849 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
850 (((hdr_info) >> 9) & 0x1ff)
851
852 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
853 ((hdr_info) & 0x1ff)
854
855 u16 cfa_code;
856 u8 agg_count;
857 struct rx_agg_cmp *agg_arr;
858 };
859
860 #define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
861
862 struct bnxt_tpa_idx_map {
863 u16 agg_id_tbl[1024];
864 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
865 };
866
867 struct bnxt_rx_ring_info {
868 struct bnxt_napi *bnapi;
869 u16 rx_prod;
870 u16 rx_agg_prod;
871 u16 rx_sw_agg_prod;
872 u16 rx_next_cons;
873 struct bnxt_db_info rx_db;
874 struct bnxt_db_info rx_agg_db;
875
876 struct bpf_prog *xdp_prog;
877
878 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
879 struct bnxt_sw_rx_bd *rx_buf_ring;
880
881 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
882 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
883
884 unsigned long *rx_agg_bmap;
885 u16 rx_agg_bmap_size;
886
887 struct page *rx_page;
888 unsigned int rx_page_offset;
889
890 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
891 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
892
893 struct bnxt_tpa_info *rx_tpa;
894 struct bnxt_tpa_idx_map *rx_tpa_idx_map;
895
896 struct bnxt_ring_struct rx_ring_struct;
897 struct bnxt_ring_struct rx_agg_ring_struct;
898 struct xdp_rxq_info xdp_rxq;
899 struct page_pool *page_pool;
900 };
901
902 struct bnxt_cp_ring_info {
903 struct bnxt_napi *bnapi;
904 u32 cp_raw_cons;
905 struct bnxt_db_info cp_db;
906
907 u8 had_work_done:1;
908 u8 has_more_work:1;
909
910 u32 last_cp_raw_cons;
911
912 struct bnxt_coal rx_ring_coal;
913 u64 rx_packets;
914 u64 rx_bytes;
915 u64 event_ctr;
916
917 struct dim dim;
918
919 union {
920 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
921 struct nqe_cn *nq_desc_ring[MAX_CP_PAGES];
922 };
923
924 dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
925
926 struct ctx_hw_stats *hw_stats;
927 dma_addr_t hw_stats_map;
928 u32 hw_stats_ctx_id;
929 u64 rx_l4_csum_errors;
930 u64 rx_buf_errors;
931 u64 missed_irqs;
932
933 struct bnxt_ring_struct cp_ring_struct;
934
935 struct bnxt_cp_ring_info *cp_ring_arr[2];
936 #define BNXT_RX_HDL 0
937 #define BNXT_TX_HDL 1
938 };
939
940 struct bnxt_napi {
941 struct napi_struct napi;
942 struct bnxt *bp;
943
944 int index;
945 struct bnxt_cp_ring_info cp_ring;
946 struct bnxt_rx_ring_info *rx_ring;
947 struct bnxt_tx_ring_info *tx_ring;
948
949 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
950 int);
951 int tx_pkts;
952 u8 events;
953
954 u32 flags;
955 #define BNXT_NAPI_FLAG_XDP 0x1
956
957 bool in_reset;
958 };
959
960 struct bnxt_irq {
961 irq_handler_t handler;
962 unsigned int vector;
963 u8 requested:1;
964 u8 have_cpumask:1;
965 char name[IFNAMSIZ + 2];
966 cpumask_var_t cpu_mask;
967 };
968
969 #define HWRM_RING_ALLOC_TX 0x1
970 #define HWRM_RING_ALLOC_RX 0x2
971 #define HWRM_RING_ALLOC_AGG 0x4
972 #define HWRM_RING_ALLOC_CMPL 0x8
973 #define HWRM_RING_ALLOC_NQ 0x10
974
975 #define INVALID_STATS_CTX_ID -1
976
977 struct bnxt_ring_grp_info {
978 u16 fw_stats_ctx;
979 u16 fw_grp_id;
980 u16 rx_fw_ring_id;
981 u16 agg_fw_ring_id;
982 u16 cp_fw_ring_id;
983 };
984
985 struct bnxt_vnic_info {
986 u16 fw_vnic_id;
987 #define BNXT_MAX_CTX_PER_VNIC 8
988 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
989 u16 fw_l2_ctx_id;
990 #define BNXT_MAX_UC_ADDRS 4
991 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
992
993 u16 uc_filter_count;
994 u8 *uc_list;
995
996 u16 *fw_grp_ids;
997 dma_addr_t rss_table_dma_addr;
998 __le16 *rss_table;
999 dma_addr_t rss_hash_key_dma_addr;
1000 u64 *rss_hash_key;
1001 u32 rx_mask;
1002
1003 u8 *mc_list;
1004 int mc_list_size;
1005 int mc_list_count;
1006 dma_addr_t mc_list_mapping;
1007 #define BNXT_MAX_MC_ADDRS 16
1008
1009 u32 flags;
1010 #define BNXT_VNIC_RSS_FLAG 1
1011 #define BNXT_VNIC_RFS_FLAG 2
1012 #define BNXT_VNIC_MCAST_FLAG 4
1013 #define BNXT_VNIC_UCAST_FLAG 8
1014 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1015 };
1016
1017 struct bnxt_hw_resc {
1018 u16 min_rsscos_ctxs;
1019 u16 max_rsscos_ctxs;
1020 u16 min_cp_rings;
1021 u16 max_cp_rings;
1022 u16 resv_cp_rings;
1023 u16 min_tx_rings;
1024 u16 max_tx_rings;
1025 u16 resv_tx_rings;
1026 u16 max_tx_sch_inputs;
1027 u16 min_rx_rings;
1028 u16 max_rx_rings;
1029 u16 resv_rx_rings;
1030 u16 min_hw_ring_grps;
1031 u16 max_hw_ring_grps;
1032 u16 resv_hw_ring_grps;
1033 u16 min_l2_ctxs;
1034 u16 max_l2_ctxs;
1035 u16 min_vnics;
1036 u16 max_vnics;
1037 u16 resv_vnics;
1038 u16 min_stat_ctxs;
1039 u16 max_stat_ctxs;
1040 u16 resv_stat_ctxs;
1041 u16 max_nqs;
1042 u16 max_irqs;
1043 u16 resv_irqs;
1044 };
1045
1046 #if defined(CONFIG_BNXT_SRIOV)
1047 struct bnxt_vf_info {
1048 u16 fw_fid;
1049 u8 mac_addr[ETH_ALEN];
1050 u8 vf_mac_addr[ETH_ALEN];
1051
1052
1053 u16 vlan;
1054 u16 func_qcfg_flags;
1055 u32 flags;
1056 #define BNXT_VF_QOS 0x1
1057 #define BNXT_VF_SPOOFCHK 0x2
1058 #define BNXT_VF_LINK_FORCED 0x4
1059 #define BNXT_VF_LINK_UP 0x8
1060 #define BNXT_VF_TRUST 0x10
1061 u32 min_tx_rate;
1062 u32 max_tx_rate;
1063 void *hwrm_cmd_req_addr;
1064 dma_addr_t hwrm_cmd_req_dma_addr;
1065 };
1066 #endif
1067
1068 struct bnxt_pf_info {
1069 #define BNXT_FIRST_PF_FID 1
1070 #define BNXT_FIRST_VF_FID 128
1071 u16 fw_fid;
1072 u16 port_id;
1073 u8 mac_addr[ETH_ALEN];
1074 u32 first_vf_id;
1075 u16 active_vfs;
1076 u16 registered_vfs;
1077 u16 max_vfs;
1078 u32 max_encap_records;
1079 u32 max_decap_records;
1080 u32 max_tx_em_flows;
1081 u32 max_tx_wm_flows;
1082 u32 max_rx_em_flows;
1083 u32 max_rx_wm_flows;
1084 unsigned long *vf_event_bmap;
1085 u16 hwrm_cmd_req_pages;
1086 u8 vf_resv_strategy;
1087 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1088 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1089 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1090 void *hwrm_cmd_req_addr[4];
1091 dma_addr_t hwrm_cmd_req_dma_addr[4];
1092 struct bnxt_vf_info *vf;
1093 };
1094
1095 struct bnxt_ntuple_filter {
1096 struct hlist_node hash;
1097 u8 dst_mac_addr[ETH_ALEN];
1098 u8 src_mac_addr[ETH_ALEN];
1099 struct flow_keys fkeys;
1100 __le64 filter_id;
1101 u16 sw_id;
1102 u8 l2_fltr_idx;
1103 u16 rxq;
1104 u32 flow_id;
1105 unsigned long state;
1106 #define BNXT_FLTR_VALID 0
1107 #define BNXT_FLTR_UPDATE 1
1108 };
1109
1110 struct bnxt_link_info {
1111 u8 phy_type;
1112 u8 media_type;
1113 u8 transceiver;
1114 u8 phy_addr;
1115 u8 phy_link_status;
1116 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1117 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1118 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1119 u8 wire_speed;
1120 u8 loop_back;
1121 u8 link_up;
1122 u8 duplex;
1123 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1124 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1125 u8 pause;
1126 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1127 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1128 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1129 PORT_PHY_QCFG_RESP_PAUSE_TX)
1130 u8 lp_pause;
1131 u8 auto_pause_setting;
1132 u8 force_pause_setting;
1133 u8 duplex_setting;
1134 u8 auto_mode;
1135 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1136 (mode) <= BNXT_LINK_AUTO_MSK)
1137 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1138 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1139 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1140 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1141 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1142 #define PHY_VER_LEN 3
1143 u8 phy_ver[PHY_VER_LEN];
1144 u16 link_speed;
1145 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1146 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1147 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1148 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1149 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1150 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1151 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1152 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1153 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1154 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1155 u16 support_speeds;
1156 u16 auto_link_speeds;
1157 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1158 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1159 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1160 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1161 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1162 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1163 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1164 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1165 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1166 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1167 u16 support_auto_speeds;
1168 u16 lp_auto_link_speeds;
1169 u16 force_link_speed;
1170 u32 preemphasis;
1171 u8 module_status;
1172 u16 fec_cfg;
1173 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1174 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1175 #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
1176
1177
1178 u8 autoneg;
1179 #define BNXT_AUTONEG_SPEED 1
1180 #define BNXT_AUTONEG_FLOW_CTRL 2
1181 u8 req_duplex;
1182 u8 req_flow_ctrl;
1183 u16 req_link_speed;
1184 u16 advertising;
1185 bool force_link_chng;
1186
1187 bool phy_retry;
1188 unsigned long phy_retry_expires;
1189
1190
1191
1192
1193 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1194 };
1195
1196 #define BNXT_MAX_QUEUE 8
1197
1198 struct bnxt_queue_info {
1199 u8 queue_id;
1200 u8 queue_profile;
1201 };
1202
1203 #define BNXT_MAX_LED 4
1204
1205 struct bnxt_led_info {
1206 u8 led_id;
1207 u8 led_type;
1208 u8 led_group_id;
1209 u8 unused;
1210 __le16 led_state_caps;
1211 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1212 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1213
1214 __le16 led_color_caps;
1215 };
1216
1217 #define BNXT_MAX_TEST 8
1218
1219 struct bnxt_test_info {
1220 u8 offline_mask;
1221 u8 flags;
1222 #define BNXT_TEST_FL_EXT_LPBK 0x1
1223 u16 timeout;
1224 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1225 };
1226
1227 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1228 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1229 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1230 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1231 #define BNXT_CAG_REG_BASE 0x300000
1232
1233 #define BNXT_GRCPF_REG_KONG_COMM 0xA00
1234 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1235
1236 #define BNXT_GRC_BASE_MASK 0xfffff000
1237 #define BNXT_GRC_OFFSET_MASK 0x00000ffc
1238
1239 struct bnxt_tc_flow_stats {
1240 u64 packets;
1241 u64 bytes;
1242 };
1243
1244 struct bnxt_tc_info {
1245 bool enabled;
1246
1247
1248 struct rhashtable flow_table;
1249 struct rhashtable_params flow_ht_params;
1250
1251
1252 struct rhashtable l2_table;
1253 struct rhashtable_params l2_ht_params;
1254
1255 struct rhashtable decap_l2_table;
1256 struct rhashtable_params decap_l2_ht_params;
1257
1258 struct rhashtable decap_table;
1259 struct rhashtable_params decap_ht_params;
1260
1261 struct rhashtable encap_table;
1262 struct rhashtable_params encap_ht_params;
1263
1264
1265
1266
1267 struct mutex lock;
1268
1269
1270 struct rhashtable_iter iter;
1271 #define BNXT_FLOW_STATS_BATCH_MAX 10
1272 struct bnxt_tc_stats_batch {
1273 void *flow_node;
1274 struct bnxt_tc_flow_stats hw_stats;
1275 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1276
1277
1278 u64 bytes_mask;
1279 u64 packets_mask;
1280 };
1281
1282 struct bnxt_vf_rep_stats {
1283 u64 packets;
1284 u64 bytes;
1285 u64 dropped;
1286 };
1287
1288 struct bnxt_vf_rep {
1289 struct bnxt *bp;
1290 struct net_device *dev;
1291 struct metadata_dst *dst;
1292 u16 vf_idx;
1293 u16 tx_cfa_action;
1294 u16 rx_cfa_code;
1295
1296 struct bnxt_vf_rep_stats rx_stats;
1297 struct bnxt_vf_rep_stats tx_stats;
1298 };
1299
1300 #define PTU_PTE_VALID 0x1UL
1301 #define PTU_PTE_LAST 0x2UL
1302 #define PTU_PTE_NEXT_TO_LAST 0x4UL
1303
1304 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1305 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1306
1307 struct bnxt_ctx_pg_info {
1308 u32 entries;
1309 u32 nr_pages;
1310 void *ctx_pg_arr[MAX_CTX_PAGES];
1311 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1312 struct bnxt_ring_mem_info ring_mem;
1313 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1314 };
1315
1316 struct bnxt_ctx_mem_info {
1317 u32 qp_max_entries;
1318 u16 qp_min_qp1_entries;
1319 u16 qp_max_l2_entries;
1320 u16 qp_entry_size;
1321 u16 srq_max_l2_entries;
1322 u32 srq_max_entries;
1323 u16 srq_entry_size;
1324 u16 cq_max_l2_entries;
1325 u32 cq_max_entries;
1326 u16 cq_entry_size;
1327 u16 vnic_max_vnic_entries;
1328 u16 vnic_max_ring_table_entries;
1329 u16 vnic_entry_size;
1330 u32 stat_max_entries;
1331 u16 stat_entry_size;
1332 u16 tqm_entry_size;
1333 u32 tqm_min_entries_per_ring;
1334 u32 tqm_max_entries_per_ring;
1335 u32 mrav_max_entries;
1336 u16 mrav_entry_size;
1337 u16 tim_entry_size;
1338 u32 tim_max_entries;
1339 u16 mrav_num_entries_units;
1340 u8 tqm_entries_multiple;
1341
1342 u32 flags;
1343 #define BNXT_CTX_FLAG_INITED 0x01
1344
1345 struct bnxt_ctx_pg_info qp_mem;
1346 struct bnxt_ctx_pg_info srq_mem;
1347 struct bnxt_ctx_pg_info cq_mem;
1348 struct bnxt_ctx_pg_info vnic_mem;
1349 struct bnxt_ctx_pg_info stat_mem;
1350 struct bnxt_ctx_pg_info mrav_mem;
1351 struct bnxt_ctx_pg_info tim_mem;
1352 struct bnxt_ctx_pg_info *tqm_mem[9];
1353 };
1354
1355 struct bnxt_fw_health {
1356 u32 flags;
1357 u32 polling_dsecs;
1358 u32 master_func_wait_dsecs;
1359 u32 normal_func_wait_dsecs;
1360 u32 post_reset_wait_dsecs;
1361 u32 post_reset_max_wait_dsecs;
1362 u32 regs[4];
1363 u32 mapped_regs[4];
1364 #define BNXT_FW_HEALTH_REG 0
1365 #define BNXT_FW_HEARTBEAT_REG 1
1366 #define BNXT_FW_RESET_CNT_REG 2
1367 #define BNXT_FW_RESET_INPROG_REG 3
1368 u32 fw_reset_inprog_reg_mask;
1369 u32 last_fw_heartbeat;
1370 u32 last_fw_reset_cnt;
1371 u8 enabled:1;
1372 u8 master:1;
1373 u8 tmr_multiplier;
1374 u8 tmr_counter;
1375 u8 fw_reset_seq_cnt;
1376 u32 fw_reset_seq_regs[16];
1377 u32 fw_reset_seq_vals[16];
1378 u32 fw_reset_seq_delay_msec[16];
1379 struct devlink_health_reporter *fw_reporter;
1380 struct devlink_health_reporter *fw_reset_reporter;
1381 struct devlink_health_reporter *fw_fatal_reporter;
1382 };
1383
1384 struct bnxt_fw_reporter_ctx {
1385 unsigned long sp_event;
1386 };
1387
1388 #define BNXT_FW_HEALTH_REG_TYPE_MASK 3
1389 #define BNXT_FW_HEALTH_REG_TYPE_CFG 0
1390 #define BNXT_FW_HEALTH_REG_TYPE_GRC 1
1391 #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
1392 #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
1393
1394 #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1395 #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1396
1397 #define BNXT_FW_HEALTH_WIN_BASE 0x3000
1398 #define BNXT_FW_HEALTH_WIN_MAP_OFF 8
1399
1400 #define BNXT_FW_STATUS_HEALTHY 0x8000
1401 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
1402
1403 struct bnxt {
1404 void __iomem *bar0;
1405 void __iomem *bar1;
1406 void __iomem *bar2;
1407
1408 u32 reg_base;
1409 u16 chip_num;
1410 #define CHIP_NUM_57301 0x16c8
1411 #define CHIP_NUM_57302 0x16c9
1412 #define CHIP_NUM_57304 0x16ca
1413 #define CHIP_NUM_58700 0x16cd
1414 #define CHIP_NUM_57402 0x16d0
1415 #define CHIP_NUM_57404 0x16d1
1416 #define CHIP_NUM_57406 0x16d2
1417 #define CHIP_NUM_57407 0x16d5
1418
1419 #define CHIP_NUM_57311 0x16ce
1420 #define CHIP_NUM_57312 0x16cf
1421 #define CHIP_NUM_57314 0x16df
1422 #define CHIP_NUM_57317 0x16e0
1423 #define CHIP_NUM_57412 0x16d6
1424 #define CHIP_NUM_57414 0x16d7
1425 #define CHIP_NUM_57416 0x16d8
1426 #define CHIP_NUM_57417 0x16d9
1427 #define CHIP_NUM_57412L 0x16da
1428 #define CHIP_NUM_57414L 0x16db
1429
1430 #define CHIP_NUM_5745X 0xd730
1431
1432 #define CHIP_NUM_57508 0x1750
1433 #define CHIP_NUM_57504 0x1751
1434 #define CHIP_NUM_57502 0x1752
1435
1436 #define CHIP_NUM_58802 0xd802
1437 #define CHIP_NUM_58804 0xd804
1438 #define CHIP_NUM_58808 0xd808
1439
1440 #define BNXT_CHIP_NUM_5730X(chip_num) \
1441 ((chip_num) >= CHIP_NUM_57301 && \
1442 (chip_num) <= CHIP_NUM_57304)
1443
1444 #define BNXT_CHIP_NUM_5740X(chip_num) \
1445 (((chip_num) >= CHIP_NUM_57402 && \
1446 (chip_num) <= CHIP_NUM_57406) || \
1447 (chip_num) == CHIP_NUM_57407)
1448
1449 #define BNXT_CHIP_NUM_5731X(chip_num) \
1450 ((chip_num) == CHIP_NUM_57311 || \
1451 (chip_num) == CHIP_NUM_57312 || \
1452 (chip_num) == CHIP_NUM_57314 || \
1453 (chip_num) == CHIP_NUM_57317)
1454
1455 #define BNXT_CHIP_NUM_5741X(chip_num) \
1456 ((chip_num) >= CHIP_NUM_57412 && \
1457 (chip_num) <= CHIP_NUM_57414L)
1458
1459 #define BNXT_CHIP_NUM_58700(chip_num) \
1460 ((chip_num) == CHIP_NUM_58700)
1461
1462 #define BNXT_CHIP_NUM_5745X(chip_num) \
1463 ((chip_num) == CHIP_NUM_5745X)
1464
1465 #define BNXT_CHIP_NUM_57X0X(chip_num) \
1466 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1467
1468 #define BNXT_CHIP_NUM_57X1X(chip_num) \
1469 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1470
1471 #define BNXT_CHIP_NUM_588XX(chip_num) \
1472 ((chip_num) == CHIP_NUM_58802 || \
1473 (chip_num) == CHIP_NUM_58804 || \
1474 (chip_num) == CHIP_NUM_58808)
1475
1476 struct net_device *dev;
1477 struct pci_dev *pdev;
1478
1479 atomic_t intr_sem;
1480
1481 u32 flags;
1482 #define BNXT_FLAG_CHIP_P5 0x1
1483 #define BNXT_FLAG_VF 0x2
1484 #define BNXT_FLAG_LRO 0x4
1485 #ifdef CONFIG_INET
1486 #define BNXT_FLAG_GRO 0x8
1487 #else
1488
1489 #define BNXT_FLAG_GRO 0x0
1490 #endif
1491 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1492 #define BNXT_FLAG_JUMBO 0x10
1493 #define BNXT_FLAG_STRIP_VLAN 0x20
1494 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1495 BNXT_FLAG_LRO)
1496 #define BNXT_FLAG_USING_MSIX 0x40
1497 #define BNXT_FLAG_MSIX_CAP 0x80
1498 #define BNXT_FLAG_RFS 0x100
1499 #define BNXT_FLAG_SHARED_RINGS 0x200
1500 #define BNXT_FLAG_PORT_STATS 0x400
1501 #define BNXT_FLAG_UDP_RSS_CAP 0x800
1502 #define BNXT_FLAG_EEE_CAP 0x1000
1503 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
1504 #define BNXT_FLAG_WOL_CAP 0x4000
1505 #define BNXT_FLAG_ROCEV1_CAP 0x8000
1506 #define BNXT_FLAG_ROCEV2_CAP 0x10000
1507 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
1508 BNXT_FLAG_ROCEV2_CAP)
1509 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1510 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1511 #define BNXT_FLAG_MULTI_HOST 0x100000
1512 #define BNXT_FLAG_DSN_VALID 0x200000
1513 #define BNXT_FLAG_DOUBLE_DB 0x400000
1514 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1515 #define BNXT_FLAG_DIM 0x2000000
1516 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
1517 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
1518 #define BNXT_FLAG_PCIE_STATS 0x40000000
1519
1520 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
1521 BNXT_FLAG_RFS | \
1522 BNXT_FLAG_STRIP_VLAN)
1523
1524 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
1525 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
1526 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
1527 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1528 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1529 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1530 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1531 #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
1532 (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \
1533 (bp)->max_tpa_v2) && !is_kdump_kernel())
1534
1535
1536 #define BNXT_CHIP_P5(bp) \
1537 ((bp)->chip_num == CHIP_NUM_57508 || \
1538 (bp)->chip_num == CHIP_NUM_57504 || \
1539 (bp)->chip_num == CHIP_NUM_57502)
1540
1541
1542 #define BNXT_CHIP_P4(bp) \
1543 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1544 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1545 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1546 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1547 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1548
1549 #define BNXT_CHIP_P4_PLUS(bp) \
1550 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1551
1552 struct bnxt_en_dev *edev;
1553 struct bnxt_en_dev * (*ulp_probe)(struct net_device *);
1554
1555 struct bnxt_napi **bnapi;
1556
1557 struct bnxt_rx_ring_info *rx_ring;
1558 struct bnxt_tx_ring_info *tx_ring;
1559 u16 *tx_ring_map;
1560
1561 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
1562 struct sk_buff *);
1563
1564 struct sk_buff * (*rx_skb_func)(struct bnxt *,
1565 struct bnxt_rx_ring_info *,
1566 u16, void *, u8 *, dma_addr_t,
1567 unsigned int);
1568
1569 u16 max_tpa_v2;
1570 u16 max_tpa;
1571 u32 rx_buf_size;
1572 u32 rx_buf_use_size;
1573 u16 rx_offset;
1574 u16 rx_dma_offset;
1575 enum dma_data_direction rx_dir;
1576 u32 rx_ring_size;
1577 u32 rx_agg_ring_size;
1578 u32 rx_copy_thresh;
1579 u32 rx_ring_mask;
1580 u32 rx_agg_ring_mask;
1581 int rx_nr_pages;
1582 int rx_agg_nr_pages;
1583 int rx_nr_rings;
1584 int rsscos_nr_ctxs;
1585
1586 u32 tx_ring_size;
1587 u32 tx_ring_mask;
1588 int tx_nr_pages;
1589 int tx_nr_rings;
1590 int tx_nr_rings_per_tc;
1591 int tx_nr_rings_xdp;
1592
1593 int tx_wake_thresh;
1594 int tx_push_thresh;
1595 int tx_push_size;
1596
1597 u32 cp_ring_size;
1598 u32 cp_ring_mask;
1599 u32 cp_bit;
1600 int cp_nr_pages;
1601 int cp_nr_rings;
1602
1603
1604 struct bnxt_ring_grp_info *grp_info;
1605 struct bnxt_vnic_info *vnic_info;
1606 int nr_vnics;
1607 u32 rss_hash_cfg;
1608
1609 u16 max_mtu;
1610 u8 max_tc;
1611 u8 max_lltc;
1612 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1613 u8 tc_to_qidx[BNXT_MAX_QUEUE];
1614 u8 q_ids[BNXT_MAX_QUEUE];
1615 u8 max_q;
1616
1617 unsigned int current_interval;
1618 #define BNXT_TIMER_INTERVAL HZ
1619
1620 struct timer_list timer;
1621
1622 unsigned long state;
1623 #define BNXT_STATE_OPEN 0
1624 #define BNXT_STATE_IN_SP_TASK 1
1625 #define BNXT_STATE_READ_STATS 2
1626 #define BNXT_STATE_FW_RESET_DET 3
1627 #define BNXT_STATE_IN_FW_RESET 4
1628 #define BNXT_STATE_ABORT_ERR 5
1629 #define BNXT_STATE_FW_FATAL_COND 6
1630
1631 struct bnxt_irq *irq_tbl;
1632 int total_irqs;
1633 u8 mac_addr[ETH_ALEN];
1634
1635 #ifdef CONFIG_BNXT_DCB
1636 struct ieee_pfc *ieee_pfc;
1637 struct ieee_ets *ieee_ets;
1638 u8 dcbx_cap;
1639 u8 default_pri;
1640 u8 max_dscp_value;
1641 #endif
1642
1643 u32 msg_enable;
1644
1645 u32 fw_cap;
1646 #define BNXT_FW_CAP_SHORT_CMD 0x00000001
1647 #define BNXT_FW_CAP_LLDP_AGENT 0x00000002
1648 #define BNXT_FW_CAP_DCBX_AGENT 0x00000004
1649 #define BNXT_FW_CAP_NEW_RM 0x00000008
1650 #define BNXT_FW_CAP_IF_CHANGE 0x00000010
1651 #define BNXT_FW_CAP_KONG_MB_CHNL 0x00000080
1652 #define BNXT_FW_CAP_OVS_64BIT_HANDLE 0x00000400
1653 #define BNXT_FW_CAP_TRUSTED_VF 0x00000800
1654 #define BNXT_FW_CAP_ERROR_RECOVERY 0x00002000
1655 #define BNXT_FW_CAP_PKG_VER 0x00004000
1656 #define BNXT_FW_CAP_CFA_ADV_FLOW 0x00008000
1657 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX 0x00010000
1658 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED 0x00020000
1659 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED 0x00040000
1660 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD 0x00100000
1661 #define BNXT_FW_CAP_HOT_RESET 0x00200000
1662
1663 #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1664 u32 hwrm_spec_code;
1665 u16 hwrm_cmd_seq;
1666 u16 hwrm_cmd_kong_seq;
1667 u16 hwrm_intr_seq_id;
1668 void *hwrm_short_cmd_req_addr;
1669 dma_addr_t hwrm_short_cmd_req_dma_addr;
1670 void *hwrm_cmd_resp_addr;
1671 dma_addr_t hwrm_cmd_resp_dma_addr;
1672 void *hwrm_cmd_kong_resp_addr;
1673 dma_addr_t hwrm_cmd_kong_resp_dma_addr;
1674
1675 struct rtnl_link_stats64 net_stats_prev;
1676 struct rx_port_stats *hw_rx_port_stats;
1677 struct tx_port_stats *hw_tx_port_stats;
1678 struct rx_port_stats_ext *hw_rx_port_stats_ext;
1679 struct tx_port_stats_ext *hw_tx_port_stats_ext;
1680 struct pcie_ctx_hw_stats *hw_pcie_stats;
1681 dma_addr_t hw_rx_port_stats_map;
1682 dma_addr_t hw_tx_port_stats_map;
1683 dma_addr_t hw_rx_port_stats_ext_map;
1684 dma_addr_t hw_tx_port_stats_ext_map;
1685 dma_addr_t hw_pcie_stats_map;
1686 int hw_port_stats_size;
1687 u16 fw_rx_stats_ext_size;
1688 u16 fw_tx_stats_ext_size;
1689 u16 hw_ring_stats_size;
1690 u8 pri2cos_idx[8];
1691 u8 pri2cos_valid;
1692
1693 u16 hwrm_max_req_len;
1694 u16 hwrm_max_ext_req_len;
1695 int hwrm_cmd_timeout;
1696 struct mutex hwrm_cmd_lock;
1697 struct hwrm_ver_get_output ver_resp;
1698 #define FW_VER_STR_LEN 32
1699 #define BC_HWRM_STR_LEN 21
1700 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1701 char fw_ver_str[FW_VER_STR_LEN];
1702 __be16 vxlan_port;
1703 u8 vxlan_port_cnt;
1704 __le16 vxlan_fw_dst_port_id;
1705 __be16 nge_port;
1706 u8 nge_port_cnt;
1707 __le16 nge_fw_dst_port_id;
1708 u8 port_partition_type;
1709 u8 port_count;
1710 u16 br_mode;
1711
1712 struct bnxt_coal_cap coal_cap;
1713 struct bnxt_coal rx_coal;
1714 struct bnxt_coal tx_coal;
1715
1716 u32 stats_coal_ticks;
1717 #define BNXT_DEF_STATS_COAL_TICKS 1000000
1718 #define BNXT_MIN_STATS_COAL_TICKS 250000
1719 #define BNXT_MAX_STATS_COAL_TICKS 1000000
1720
1721 struct work_struct sp_task;
1722 unsigned long sp_event;
1723 #define BNXT_RX_MASK_SP_EVENT 0
1724 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
1725 #define BNXT_LINK_CHNG_SP_EVENT 2
1726 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1727 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
1728 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
1729 #define BNXT_RESET_TASK_SP_EVENT 6
1730 #define BNXT_RST_RING_SP_EVENT 7
1731 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
1732 #define BNXT_PERIODIC_STATS_SP_EVENT 9
1733 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
1734 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1735 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12
1736 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
1737 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
1738 #define BNXT_FLOW_STATS_SP_EVENT 15
1739 #define BNXT_UPDATE_PHY_SP_EVENT 16
1740 #define BNXT_RING_COAL_NOW_SP_EVENT 17
1741 #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
1742 #define BNXT_FW_EXCEPTION_SP_EVENT 19
1743
1744 struct delayed_work fw_reset_task;
1745 int fw_reset_state;
1746 #define BNXT_FW_RESET_STATE_POLL_VF 1
1747 #define BNXT_FW_RESET_STATE_RESET_FW 2
1748 #define BNXT_FW_RESET_STATE_ENABLE_DEV 3
1749 #define BNXT_FW_RESET_STATE_POLL_FW 4
1750 #define BNXT_FW_RESET_STATE_OPENING 5
1751 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
1752
1753 u16 fw_reset_min_dsecs;
1754 #define BNXT_DFLT_FW_RST_MIN_DSECS 20
1755 u16 fw_reset_max_dsecs;
1756 #define BNXT_DFLT_FW_RST_MAX_DSECS 60
1757 unsigned long fw_reset_timestamp;
1758
1759 struct bnxt_fw_health *fw_health;
1760
1761 struct bnxt_hw_resc hw_resc;
1762 struct bnxt_pf_info pf;
1763 struct bnxt_ctx_mem_info *ctx;
1764 #ifdef CONFIG_BNXT_SRIOV
1765 int nr_vfs;
1766 struct bnxt_vf_info vf;
1767 wait_queue_head_t sriov_cfg_wait;
1768 bool sriov_cfg;
1769 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1770
1771
1772
1773
1774
1775 struct mutex sriov_lock;
1776 #endif
1777
1778 #if BITS_PER_LONG == 32
1779
1780 spinlock_t db_lock;
1781 #endif
1782
1783 #define BNXT_NTP_FLTR_MAX_FLTR 4096
1784 #define BNXT_NTP_FLTR_HASH_SIZE 512
1785 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1786 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1787 spinlock_t ntp_fltr_lock;
1788
1789 unsigned long *ntp_fltr_bmap;
1790 int ntp_fltr_count;
1791
1792
1793
1794
1795 struct mutex link_lock;
1796 struct bnxt_link_info link_info;
1797 struct ethtool_eee eee;
1798 u32 lpi_tmr_lo;
1799 u32 lpi_tmr_hi;
1800
1801 u8 num_tests;
1802 struct bnxt_test_info *test_info;
1803
1804 u8 wol_filter_id;
1805 u8 wol;
1806
1807 u8 num_leds;
1808 struct bnxt_led_info leds[BNXT_MAX_LED];
1809
1810 struct bpf_prog *xdp_prog;
1811
1812
1813 struct devlink *dl;
1814 struct devlink_port dl_port;
1815 enum devlink_eswitch_mode eswitch_mode;
1816 struct bnxt_vf_rep **vf_reps;
1817 u16 *cfa_code_map;
1818 u8 switch_id[8];
1819 struct bnxt_tc_info *tc_info;
1820 struct dentry *debugfs_pdev;
1821 struct device *hwmon_dev;
1822 };
1823
1824 #define BNXT_RX_STATS_OFFSET(counter) \
1825 (offsetof(struct rx_port_stats, counter) / 8)
1826
1827 #define BNXT_TX_STATS_OFFSET(counter) \
1828 ((offsetof(struct tx_port_stats, counter) + \
1829 sizeof(struct rx_port_stats) + 512) / 8)
1830
1831 #define BNXT_RX_STATS_EXT_OFFSET(counter) \
1832 (offsetof(struct rx_port_stats_ext, counter) / 8)
1833
1834 #define BNXT_TX_STATS_EXT_OFFSET(counter) \
1835 (offsetof(struct tx_port_stats_ext, counter) / 8)
1836
1837 #define BNXT_PCIE_STATS_OFFSET(counter) \
1838 (offsetof(struct pcie_ctx_hw_stats, counter) / 8)
1839
1840 #define I2C_DEV_ADDR_A0 0xa0
1841 #define I2C_DEV_ADDR_A2 0xa2
1842 #define SFF_DIAG_SUPPORT_OFFSET 0x5c
1843 #define SFF_MODULE_ID_SFP 0x3
1844 #define SFF_MODULE_ID_QSFP 0xc
1845 #define SFF_MODULE_ID_QSFP_PLUS 0xd
1846 #define SFF_MODULE_ID_QSFP28 0x11
1847 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
1848
1849 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
1850 {
1851
1852 barrier();
1853
1854 return bp->tx_ring_size -
1855 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1856 }
1857
1858 #if BITS_PER_LONG == 32
1859 #define writeq(val64, db) \
1860 do { \
1861 spin_lock(&bp->db_lock); \
1862 writel((val64) & 0xffffffff, db); \
1863 writel((val64) >> 32, (db) + 4); \
1864 spin_unlock(&bp->db_lock); \
1865 } while (0)
1866
1867 #define writeq_relaxed writeq
1868 #endif
1869
1870
1871 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
1872 struct bnxt_db_info *db, u32 idx)
1873 {
1874 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1875 writeq_relaxed(db->db_key64 | idx, db->doorbell);
1876 } else {
1877 u32 db_val = db->db_key32 | idx;
1878
1879 writel_relaxed(db_val, db->doorbell);
1880 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1881 writel_relaxed(db_val, db->doorbell);
1882 }
1883 }
1884
1885
1886 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
1887 u32 idx)
1888 {
1889 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1890 writeq(db->db_key64 | idx, db->doorbell);
1891 } else {
1892 u32 db_val = db->db_key32 | idx;
1893
1894 writel(db_val, db->doorbell);
1895 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1896 writel(db_val, db->doorbell);
1897 }
1898 }
1899
1900 static inline bool bnxt_cfa_hwrm_message(u16 req_type)
1901 {
1902 switch (req_type) {
1903 case HWRM_CFA_ENCAP_RECORD_ALLOC:
1904 case HWRM_CFA_ENCAP_RECORD_FREE:
1905 case HWRM_CFA_DECAP_FILTER_ALLOC:
1906 case HWRM_CFA_DECAP_FILTER_FREE:
1907 case HWRM_CFA_EM_FLOW_ALLOC:
1908 case HWRM_CFA_EM_FLOW_FREE:
1909 case HWRM_CFA_EM_FLOW_CFG:
1910 case HWRM_CFA_FLOW_ALLOC:
1911 case HWRM_CFA_FLOW_FREE:
1912 case HWRM_CFA_FLOW_INFO:
1913 case HWRM_CFA_FLOW_FLUSH:
1914 case HWRM_CFA_FLOW_STATS:
1915 case HWRM_CFA_METER_PROFILE_ALLOC:
1916 case HWRM_CFA_METER_PROFILE_FREE:
1917 case HWRM_CFA_METER_PROFILE_CFG:
1918 case HWRM_CFA_METER_INSTANCE_ALLOC:
1919 case HWRM_CFA_METER_INSTANCE_FREE:
1920 return true;
1921 default:
1922 return false;
1923 }
1924 }
1925
1926 static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req)
1927 {
1928 return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
1929 bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));
1930 }
1931
1932 static inline bool bnxt_hwrm_kong_chnl(struct bnxt *bp, struct input *req)
1933 {
1934 return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
1935 req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));
1936 }
1937
1938 static inline void *bnxt_get_hwrm_resp_addr(struct bnxt *bp, void *req)
1939 {
1940 if (bnxt_hwrm_kong_chnl(bp, (struct input *)req))
1941 return bp->hwrm_cmd_kong_resp_addr;
1942 else
1943 return bp->hwrm_cmd_resp_addr;
1944 }
1945
1946 static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst)
1947 {
1948 u16 seq_id;
1949
1950 if (dst == BNXT_HWRM_CHNL_CHIMP)
1951 seq_id = bp->hwrm_cmd_seq++;
1952 else
1953 seq_id = bp->hwrm_cmd_kong_seq++;
1954 return seq_id;
1955 }
1956
1957 extern const u16 bnxt_lhint_arr[];
1958
1959 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1960 u16 prod, gfp_t gfp);
1961 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
1962 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
1963 void bnxt_set_tpa_flags(struct bnxt *bp);
1964 void bnxt_set_ring_params(struct bnxt *);
1965 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
1966 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1967 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1968 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
1969 int hwrm_send_message(struct bnxt *, void *, u32, int);
1970 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1971 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
1972 int bmap_size);
1973 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
1974 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
1975 int bnxt_nq_rings_in_use(struct bnxt *bp);
1976 int bnxt_hwrm_set_coal(struct bnxt *);
1977 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
1978 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
1979 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
1980 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
1981 int bnxt_get_avail_msix(struct bnxt *bp, int num);
1982 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
1983 void bnxt_tx_disable(struct bnxt *bp);
1984 void bnxt_tx_enable(struct bnxt *bp);
1985 int bnxt_hwrm_set_pause(struct bnxt *);
1986 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1987 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
1988 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
1989 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
1990 int bnxt_hwrm_fw_set_time(struct bnxt *);
1991 int bnxt_open_nic(struct bnxt *, bool, bool);
1992 int bnxt_half_open_nic(struct bnxt *bp);
1993 void bnxt_half_close_nic(struct bnxt *bp);
1994 int bnxt_close_nic(struct bnxt *, bool, bool);
1995 void bnxt_fw_exception(struct bnxt *bp);
1996 void bnxt_fw_reset(struct bnxt *bp);
1997 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
1998 int tx_xdp);
1999 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2000 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2001 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2002 int bnxt_get_port_parent_id(struct net_device *dev,
2003 struct netdev_phys_item_id *ppid);
2004 void bnxt_dim_work(struct work_struct *work);
2005 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2006
2007 #endif