root/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h

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INCLUDED FROM


   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2014-2018 Broadcom Limited
   5  * Copyright (c) 2018-2019 Broadcom Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation.
  10  *
  11  * DO NOT MODIFY!!! This file is automatically generated.
  12  */
  13 
  14 #ifndef _BNXT_HSI_H_
  15 #define _BNXT_HSI_H_
  16 
  17 /* hwrm_cmd_hdr (size:128b/16B) */
  18 struct hwrm_cmd_hdr {
  19         __le16  req_type;
  20         __le16  cmpl_ring;
  21         __le16  seq_id;
  22         __le16  target_id;
  23         __le64  resp_addr;
  24 };
  25 
  26 /* hwrm_resp_hdr (size:64b/8B) */
  27 struct hwrm_resp_hdr {
  28         __le16  error_code;
  29         __le16  req_type;
  30         __le16  seq_id;
  31         __le16  resp_len;
  32 };
  33 
  34 #define CMD_DISCR_TLV_ENCAP 0x8000UL
  35 #define CMD_DISCR_LAST     CMD_DISCR_TLV_ENCAP
  36 
  37 
  38 #define TLV_TYPE_HWRM_REQUEST                    0x1UL
  39 #define TLV_TYPE_HWRM_RESPONSE                   0x2UL
  40 #define TLV_TYPE_ROCE_SP_COMMAND                 0x3UL
  41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1              0x4UL
  42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1             0x5UL
  43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
  44 #define TLV_TYPE_ENGINE_CKV_IV                   0x8003UL
  45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG             0x8004UL
  46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT           0x8005UL
  47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS      0x8006UL
  48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY  0x8007UL
  49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE      0x8008UL
  50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY    0x8009UL
  51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS        0x800aUL
  52 #define TLV_TYPE_LAST                           TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
  53 
  54 
  55 /* tlv (size:64b/8B) */
  56 struct tlv {
  57         __le16  cmd_discr;
  58         u8      reserved_8b;
  59         u8      flags;
  60         #define TLV_FLAGS_MORE         0x1UL
  61         #define TLV_FLAGS_MORE_LAST      0x0UL
  62         #define TLV_FLAGS_MORE_NOT_LAST  0x1UL
  63         #define TLV_FLAGS_REQUIRED     0x2UL
  64         #define TLV_FLAGS_REQUIRED_NO    (0x0UL << 1)
  65         #define TLV_FLAGS_REQUIRED_YES   (0x1UL << 1)
  66         #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
  67         __le16  tlv_type;
  68         __le16  length;
  69 };
  70 
  71 /* input (size:128b/16B) */
  72 struct input {
  73         __le16  req_type;
  74         __le16  cmpl_ring;
  75         __le16  seq_id;
  76         __le16  target_id;
  77         __le64  resp_addr;
  78 };
  79 
  80 /* output (size:64b/8B) */
  81 struct output {
  82         __le16  error_code;
  83         __le16  req_type;
  84         __le16  seq_id;
  85         __le16  resp_len;
  86 };
  87 
  88 /* hwrm_short_input (size:128b/16B) */
  89 struct hwrm_short_input {
  90         __le16  req_type;
  91         __le16  signature;
  92         #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
  93         #define SHORT_REQ_SIGNATURE_LAST     SHORT_REQ_SIGNATURE_SHORT_CMD
  94         __le16  target_id;
  95         #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL
  96         #define SHORT_REQ_TARGET_ID_TOOLS   0xfffdUL
  97         #define SHORT_REQ_TARGET_ID_LAST   SHORT_REQ_TARGET_ID_TOOLS
  98         __le16  size;
  99         __le64  req_addr;
 100 };
 101 
 102 /* cmd_nums (size:64b/8B) */
 103 struct cmd_nums {
 104         __le16  req_type;
 105         #define HWRM_VER_GET                              0x0UL
 106         #define HWRM_ERROR_RECOVERY_QCFG                  0xcUL
 107         #define HWRM_FUNC_DRV_IF_CHANGE                   0xdUL
 108         #define HWRM_FUNC_BUF_UNRGTR                      0xeUL
 109         #define HWRM_FUNC_VF_CFG                          0xfUL
 110         #define HWRM_RESERVED1                            0x10UL
 111         #define HWRM_FUNC_RESET                           0x11UL
 112         #define HWRM_FUNC_GETFID                          0x12UL
 113         #define HWRM_FUNC_VF_ALLOC                        0x13UL
 114         #define HWRM_FUNC_VF_FREE                         0x14UL
 115         #define HWRM_FUNC_QCAPS                           0x15UL
 116         #define HWRM_FUNC_QCFG                            0x16UL
 117         #define HWRM_FUNC_CFG                             0x17UL
 118         #define HWRM_FUNC_QSTATS                          0x18UL
 119         #define HWRM_FUNC_CLR_STATS                       0x19UL
 120         #define HWRM_FUNC_DRV_UNRGTR                      0x1aUL
 121         #define HWRM_FUNC_VF_RESC_FREE                    0x1bUL
 122         #define HWRM_FUNC_VF_VNIC_IDS_QUERY               0x1cUL
 123         #define HWRM_FUNC_DRV_RGTR                        0x1dUL
 124         #define HWRM_FUNC_DRV_QVER                        0x1eUL
 125         #define HWRM_FUNC_BUF_RGTR                        0x1fUL
 126         #define HWRM_PORT_PHY_CFG                         0x20UL
 127         #define HWRM_PORT_MAC_CFG                         0x21UL
 128         #define HWRM_PORT_TS_QUERY                        0x22UL
 129         #define HWRM_PORT_QSTATS                          0x23UL
 130         #define HWRM_PORT_LPBK_QSTATS                     0x24UL
 131         #define HWRM_PORT_CLR_STATS                       0x25UL
 132         #define HWRM_PORT_LPBK_CLR_STATS                  0x26UL
 133         #define HWRM_PORT_PHY_QCFG                        0x27UL
 134         #define HWRM_PORT_MAC_QCFG                        0x28UL
 135         #define HWRM_PORT_MAC_PTP_QCFG                    0x29UL
 136         #define HWRM_PORT_PHY_QCAPS                       0x2aUL
 137         #define HWRM_PORT_PHY_I2C_WRITE                   0x2bUL
 138         #define HWRM_PORT_PHY_I2C_READ                    0x2cUL
 139         #define HWRM_PORT_LED_CFG                         0x2dUL
 140         #define HWRM_PORT_LED_QCFG                        0x2eUL
 141         #define HWRM_PORT_LED_QCAPS                       0x2fUL
 142         #define HWRM_QUEUE_QPORTCFG                       0x30UL
 143         #define HWRM_QUEUE_QCFG                           0x31UL
 144         #define HWRM_QUEUE_CFG                            0x32UL
 145         #define HWRM_FUNC_VLAN_CFG                        0x33UL
 146         #define HWRM_FUNC_VLAN_QCFG                       0x34UL
 147         #define HWRM_QUEUE_PFCENABLE_QCFG                 0x35UL
 148         #define HWRM_QUEUE_PFCENABLE_CFG                  0x36UL
 149         #define HWRM_QUEUE_PRI2COS_QCFG                   0x37UL
 150         #define HWRM_QUEUE_PRI2COS_CFG                    0x38UL
 151         #define HWRM_QUEUE_COS2BW_QCFG                    0x39UL
 152         #define HWRM_QUEUE_COS2BW_CFG                     0x3aUL
 153         #define HWRM_QUEUE_DSCP_QCAPS                     0x3bUL
 154         #define HWRM_QUEUE_DSCP2PRI_QCFG                  0x3cUL
 155         #define HWRM_QUEUE_DSCP2PRI_CFG                   0x3dUL
 156         #define HWRM_VNIC_ALLOC                           0x40UL
 157         #define HWRM_VNIC_FREE                            0x41UL
 158         #define HWRM_VNIC_CFG                             0x42UL
 159         #define HWRM_VNIC_QCFG                            0x43UL
 160         #define HWRM_VNIC_TPA_CFG                         0x44UL
 161         #define HWRM_VNIC_TPA_QCFG                        0x45UL
 162         #define HWRM_VNIC_RSS_CFG                         0x46UL
 163         #define HWRM_VNIC_RSS_QCFG                        0x47UL
 164         #define HWRM_VNIC_PLCMODES_CFG                    0x48UL
 165         #define HWRM_VNIC_PLCMODES_QCFG                   0x49UL
 166         #define HWRM_VNIC_QCAPS                           0x4aUL
 167         #define HWRM_RING_ALLOC                           0x50UL
 168         #define HWRM_RING_FREE                            0x51UL
 169         #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS        0x52UL
 170         #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS     0x53UL
 171         #define HWRM_RING_AGGINT_QCAPS                    0x54UL
 172         #define HWRM_RING_RESET                           0x5eUL
 173         #define HWRM_RING_GRP_ALLOC                       0x60UL
 174         #define HWRM_RING_GRP_FREE                        0x61UL
 175         #define HWRM_RESERVED5                            0x64UL
 176         #define HWRM_RESERVED6                            0x65UL
 177         #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC            0x70UL
 178         #define HWRM_VNIC_RSS_COS_LB_CTX_FREE             0x71UL
 179         #define HWRM_CFA_L2_FILTER_ALLOC                  0x90UL
 180         #define HWRM_CFA_L2_FILTER_FREE                   0x91UL
 181         #define HWRM_CFA_L2_FILTER_CFG                    0x92UL
 182         #define HWRM_CFA_L2_SET_RX_MASK                   0x93UL
 183         #define HWRM_CFA_VLAN_ANTISPOOF_CFG               0x94UL
 184         #define HWRM_CFA_TUNNEL_FILTER_ALLOC              0x95UL
 185         #define HWRM_CFA_TUNNEL_FILTER_FREE               0x96UL
 186         #define HWRM_CFA_ENCAP_RECORD_ALLOC               0x97UL
 187         #define HWRM_CFA_ENCAP_RECORD_FREE                0x98UL
 188         #define HWRM_CFA_NTUPLE_FILTER_ALLOC              0x99UL
 189         #define HWRM_CFA_NTUPLE_FILTER_FREE               0x9aUL
 190         #define HWRM_CFA_NTUPLE_FILTER_CFG                0x9bUL
 191         #define HWRM_CFA_EM_FLOW_ALLOC                    0x9cUL
 192         #define HWRM_CFA_EM_FLOW_FREE                     0x9dUL
 193         #define HWRM_CFA_EM_FLOW_CFG                      0x9eUL
 194         #define HWRM_TUNNEL_DST_PORT_QUERY                0xa0UL
 195         #define HWRM_TUNNEL_DST_PORT_ALLOC                0xa1UL
 196         #define HWRM_TUNNEL_DST_PORT_FREE                 0xa2UL
 197         #define HWRM_STAT_CTX_ENG_QUERY                   0xafUL
 198         #define HWRM_STAT_CTX_ALLOC                       0xb0UL
 199         #define HWRM_STAT_CTX_FREE                        0xb1UL
 200         #define HWRM_STAT_CTX_QUERY                       0xb2UL
 201         #define HWRM_STAT_CTX_CLR_STATS                   0xb3UL
 202         #define HWRM_PORT_QSTATS_EXT                      0xb4UL
 203         #define HWRM_PORT_PHY_MDIO_WRITE                  0xb5UL
 204         #define HWRM_PORT_PHY_MDIO_READ                   0xb6UL
 205         #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE            0xb7UL
 206         #define HWRM_PORT_PHY_MDIO_BUS_RELEASE            0xb8UL
 207         #define HWRM_FW_RESET                             0xc0UL
 208         #define HWRM_FW_QSTATUS                           0xc1UL
 209         #define HWRM_FW_HEALTH_CHECK                      0xc2UL
 210         #define HWRM_FW_SYNC                              0xc3UL
 211         #define HWRM_FW_STATE_BUFFER_QCAPS                0xc4UL
 212         #define HWRM_FW_STATE_QUIESCE                     0xc5UL
 213         #define HWRM_FW_STATE_BACKUP                      0xc6UL
 214         #define HWRM_FW_STATE_RESTORE                     0xc7UL
 215         #define HWRM_FW_SET_TIME                          0xc8UL
 216         #define HWRM_FW_GET_TIME                          0xc9UL
 217         #define HWRM_FW_SET_STRUCTURED_DATA               0xcaUL
 218         #define HWRM_FW_GET_STRUCTURED_DATA               0xcbUL
 219         #define HWRM_FW_IPC_MAILBOX                       0xccUL
 220         #define HWRM_EXEC_FWD_RESP                        0xd0UL
 221         #define HWRM_REJECT_FWD_RESP                      0xd1UL
 222         #define HWRM_FWD_RESP                             0xd2UL
 223         #define HWRM_FWD_ASYNC_EVENT_CMPL                 0xd3UL
 224         #define HWRM_OEM_CMD                              0xd4UL
 225         #define HWRM_PORT_PRBS_TEST                       0xd5UL
 226         #define HWRM_PORT_SFP_SIDEBAND_CFG                0xd6UL
 227         #define HWRM_PORT_SFP_SIDEBAND_QCFG               0xd7UL
 228         #define HWRM_TEMP_MONITOR_QUERY                   0xe0UL
 229         #define HWRM_REG_POWER_QUERY                      0xe1UL
 230         #define HWRM_WOL_FILTER_ALLOC                     0xf0UL
 231         #define HWRM_WOL_FILTER_FREE                      0xf1UL
 232         #define HWRM_WOL_FILTER_QCFG                      0xf2UL
 233         #define HWRM_WOL_REASON_QCFG                      0xf3UL
 234         #define HWRM_CFA_METER_QCAPS                      0xf4UL
 235         #define HWRM_CFA_METER_PROFILE_ALLOC              0xf5UL
 236         #define HWRM_CFA_METER_PROFILE_FREE               0xf6UL
 237         #define HWRM_CFA_METER_PROFILE_CFG                0xf7UL
 238         #define HWRM_CFA_METER_INSTANCE_ALLOC             0xf8UL
 239         #define HWRM_CFA_METER_INSTANCE_FREE              0xf9UL
 240         #define HWRM_CFA_METER_INSTANCE_CFG               0xfaUL
 241         #define HWRM_CFA_VFR_ALLOC                        0xfdUL
 242         #define HWRM_CFA_VFR_FREE                         0xfeUL
 243         #define HWRM_CFA_VF_PAIR_ALLOC                    0x100UL
 244         #define HWRM_CFA_VF_PAIR_FREE                     0x101UL
 245         #define HWRM_CFA_VF_PAIR_INFO                     0x102UL
 246         #define HWRM_CFA_FLOW_ALLOC                       0x103UL
 247         #define HWRM_CFA_FLOW_FREE                        0x104UL
 248         #define HWRM_CFA_FLOW_FLUSH                       0x105UL
 249         #define HWRM_CFA_FLOW_STATS                       0x106UL
 250         #define HWRM_CFA_FLOW_INFO                        0x107UL
 251         #define HWRM_CFA_DECAP_FILTER_ALLOC               0x108UL
 252         #define HWRM_CFA_DECAP_FILTER_FREE                0x109UL
 253         #define HWRM_CFA_VLAN_ANTISPOOF_QCFG              0x10aUL
 254         #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC       0x10bUL
 255         #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE        0x10cUL
 256         #define HWRM_CFA_PAIR_ALLOC                       0x10dUL
 257         #define HWRM_CFA_PAIR_FREE                        0x10eUL
 258         #define HWRM_CFA_PAIR_INFO                        0x10fUL
 259         #define HWRM_FW_IPC_MSG                           0x110UL
 260         #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO        0x111UL
 261         #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE       0x112UL
 262         #define HWRM_CFA_FLOW_AGING_TIMER_RESET           0x113UL
 263         #define HWRM_CFA_FLOW_AGING_CFG                   0x114UL
 264         #define HWRM_CFA_FLOW_AGING_QCFG                  0x115UL
 265         #define HWRM_CFA_FLOW_AGING_QCAPS                 0x116UL
 266         #define HWRM_CFA_CTX_MEM_RGTR                     0x117UL
 267         #define HWRM_CFA_CTX_MEM_UNRGTR                   0x118UL
 268         #define HWRM_CFA_CTX_MEM_QCTX                     0x119UL
 269         #define HWRM_CFA_CTX_MEM_QCAPS                    0x11aUL
 270         #define HWRM_CFA_COUNTER_QCAPS                    0x11bUL
 271         #define HWRM_CFA_COUNTER_CFG                      0x11cUL
 272         #define HWRM_CFA_COUNTER_QCFG                     0x11dUL
 273         #define HWRM_CFA_COUNTER_QSTATS                   0x11eUL
 274         #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG            0x11fUL
 275         #define HWRM_CFA_EEM_QCAPS                        0x120UL
 276         #define HWRM_CFA_EEM_CFG                          0x121UL
 277         #define HWRM_CFA_EEM_QCFG                         0x122UL
 278         #define HWRM_CFA_EEM_OP                           0x123UL
 279         #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS              0x124UL
 280         #define HWRM_CFA_TFLIB                            0x125UL
 281         #define HWRM_ENGINE_CKV_STATUS                    0x12eUL
 282         #define HWRM_ENGINE_CKV_CKEK_ADD                  0x12fUL
 283         #define HWRM_ENGINE_CKV_CKEK_DELETE               0x130UL
 284         #define HWRM_ENGINE_CKV_KEY_ADD                   0x131UL
 285         #define HWRM_ENGINE_CKV_KEY_DELETE                0x132UL
 286         #define HWRM_ENGINE_CKV_FLUSH                     0x133UL
 287         #define HWRM_ENGINE_CKV_RNG_GET                   0x134UL
 288         #define HWRM_ENGINE_CKV_KEY_GEN                   0x135UL
 289         #define HWRM_ENGINE_CKV_KEY_LABEL_CFG             0x136UL
 290         #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG            0x137UL
 291         #define HWRM_ENGINE_QG_CONFIG_QUERY               0x13cUL
 292         #define HWRM_ENGINE_QG_QUERY                      0x13dUL
 293         #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
 294         #define HWRM_ENGINE_QG_METER_PROFILE_QUERY        0x13fUL
 295         #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC        0x140UL
 296         #define HWRM_ENGINE_QG_METER_PROFILE_FREE         0x141UL
 297         #define HWRM_ENGINE_QG_METER_QUERY                0x142UL
 298         #define HWRM_ENGINE_QG_METER_BIND                 0x143UL
 299         #define HWRM_ENGINE_QG_METER_UNBIND               0x144UL
 300         #define HWRM_ENGINE_QG_FUNC_BIND                  0x145UL
 301         #define HWRM_ENGINE_SG_CONFIG_QUERY               0x146UL
 302         #define HWRM_ENGINE_SG_QUERY                      0x147UL
 303         #define HWRM_ENGINE_SG_METER_QUERY                0x148UL
 304         #define HWRM_ENGINE_SG_METER_CONFIG               0x149UL
 305         #define HWRM_ENGINE_SG_QG_BIND                    0x14aUL
 306         #define HWRM_ENGINE_QG_SG_UNBIND                  0x14bUL
 307         #define HWRM_ENGINE_CONFIG_QUERY                  0x154UL
 308         #define HWRM_ENGINE_STATS_CONFIG                  0x155UL
 309         #define HWRM_ENGINE_STATS_CLEAR                   0x156UL
 310         #define HWRM_ENGINE_STATS_QUERY                   0x157UL
 311         #define HWRM_ENGINE_RQ_ALLOC                      0x15eUL
 312         #define HWRM_ENGINE_RQ_FREE                       0x15fUL
 313         #define HWRM_ENGINE_CQ_ALLOC                      0x160UL
 314         #define HWRM_ENGINE_CQ_FREE                       0x161UL
 315         #define HWRM_ENGINE_NQ_ALLOC                      0x162UL
 316         #define HWRM_ENGINE_NQ_FREE                       0x163UL
 317         #define HWRM_ENGINE_ON_DIE_RQE_CREDITS            0x164UL
 318         #define HWRM_ENGINE_FUNC_QCFG                     0x165UL
 319         #define HWRM_FUNC_RESOURCE_QCAPS                  0x190UL
 320         #define HWRM_FUNC_VF_RESOURCE_CFG                 0x191UL
 321         #define HWRM_FUNC_BACKING_STORE_QCAPS             0x192UL
 322         #define HWRM_FUNC_BACKING_STORE_CFG               0x193UL
 323         #define HWRM_FUNC_BACKING_STORE_QCFG              0x194UL
 324         #define HWRM_FUNC_VF_BW_CFG                       0x195UL
 325         #define HWRM_FUNC_VF_BW_QCFG                      0x196UL
 326         #define HWRM_FUNC_HOST_PF_IDS_QUERY               0x197UL
 327         #define HWRM_SELFTEST_QLIST                       0x200UL
 328         #define HWRM_SELFTEST_EXEC                        0x201UL
 329         #define HWRM_SELFTEST_IRQ                         0x202UL
 330         #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA        0x203UL
 331         #define HWRM_PCIE_QSTATS                          0x204UL
 332         #define HWRM_MFG_FRU_WRITE_CONTROL                0x205UL
 333         #define HWRM_MFG_TIMERS_QUERY                     0x206UL
 334         #define HWRM_MFG_OTP_CFG                          0x207UL
 335         #define HWRM_MFG_OTP_QCFG                         0x208UL
 336         #define HWRM_MFG_HDMA_TEST                        0x209UL
 337         #define HWRM_DBG_READ_DIRECT                      0xff10UL
 338         #define HWRM_DBG_READ_INDIRECT                    0xff11UL
 339         #define HWRM_DBG_WRITE_DIRECT                     0xff12UL
 340         #define HWRM_DBG_WRITE_INDIRECT                   0xff13UL
 341         #define HWRM_DBG_DUMP                             0xff14UL
 342         #define HWRM_DBG_ERASE_NVM                        0xff15UL
 343         #define HWRM_DBG_CFG                              0xff16UL
 344         #define HWRM_DBG_COREDUMP_LIST                    0xff17UL
 345         #define HWRM_DBG_COREDUMP_INITIATE                0xff18UL
 346         #define HWRM_DBG_COREDUMP_RETRIEVE                0xff19UL
 347         #define HWRM_DBG_FW_CLI                           0xff1aUL
 348         #define HWRM_DBG_I2C_CMD                          0xff1bUL
 349         #define HWRM_DBG_RING_INFO_GET                    0xff1cUL
 350         #define HWRM_DBG_CRASHDUMP_HEADER                 0xff1dUL
 351         #define HWRM_DBG_CRASHDUMP_ERASE                  0xff1eUL
 352         #define HWRM_NVM_FACTORY_DEFAULTS                 0xffeeUL
 353         #define HWRM_NVM_VALIDATE_OPTION                  0xffefUL
 354         #define HWRM_NVM_FLUSH                            0xfff0UL
 355         #define HWRM_NVM_GET_VARIABLE                     0xfff1UL
 356         #define HWRM_NVM_SET_VARIABLE                     0xfff2UL
 357         #define HWRM_NVM_INSTALL_UPDATE                   0xfff3UL
 358         #define HWRM_NVM_MODIFY                           0xfff4UL
 359         #define HWRM_NVM_VERIFY_UPDATE                    0xfff5UL
 360         #define HWRM_NVM_GET_DEV_INFO                     0xfff6UL
 361         #define HWRM_NVM_ERASE_DIR_ENTRY                  0xfff7UL
 362         #define HWRM_NVM_MOD_DIR_ENTRY                    0xfff8UL
 363         #define HWRM_NVM_FIND_DIR_ENTRY                   0xfff9UL
 364         #define HWRM_NVM_GET_DIR_ENTRIES                  0xfffaUL
 365         #define HWRM_NVM_GET_DIR_INFO                     0xfffbUL
 366         #define HWRM_NVM_RAW_DUMP                         0xfffcUL
 367         #define HWRM_NVM_READ                             0xfffdUL
 368         #define HWRM_NVM_WRITE                            0xfffeUL
 369         #define HWRM_NVM_RAW_WRITE_BLK                    0xffffUL
 370         #define HWRM_LAST                                HWRM_NVM_RAW_WRITE_BLK
 371         __le16  unused_0[3];
 372 };
 373 
 374 /* ret_codes (size:64b/8B) */
 375 struct ret_codes {
 376         __le16  error_code;
 377         #define HWRM_ERR_CODE_SUCCESS                      0x0UL
 378         #define HWRM_ERR_CODE_FAIL                         0x1UL
 379         #define HWRM_ERR_CODE_INVALID_PARAMS               0x2UL
 380         #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED       0x3UL
 381         #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR         0x4UL
 382         #define HWRM_ERR_CODE_INVALID_FLAGS                0x5UL
 383         #define HWRM_ERR_CODE_INVALID_ENABLES              0x6UL
 384         #define HWRM_ERR_CODE_UNSUPPORTED_TLV              0x7UL
 385         #define HWRM_ERR_CODE_NO_BUFFER                    0x8UL
 386         #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR       0x9UL
 387         #define HWRM_ERR_CODE_HOT_RESET_PROGRESS           0xaUL
 388         #define HWRM_ERR_CODE_HOT_RESET_FAIL               0xbUL
 389         #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL
 390         #define HWRM_ERR_CODE_KEY_HASH_COLLISION           0xdUL
 391         #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS           0xeUL
 392         #define HWRM_ERR_CODE_HWRM_ERROR                   0xfUL
 393         #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE    0x8000UL
 394         #define HWRM_ERR_CODE_UNKNOWN_ERR                  0xfffeUL
 395         #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED            0xffffUL
 396         #define HWRM_ERR_CODE_LAST                        HWRM_ERR_CODE_CMD_NOT_SUPPORTED
 397         __le16  unused_0[3];
 398 };
 399 
 400 /* hwrm_err_output (size:128b/16B) */
 401 struct hwrm_err_output {
 402         __le16  error_code;
 403         __le16  req_type;
 404         __le16  seq_id;
 405         __le16  resp_len;
 406         __le32  opaque_0;
 407         __le16  opaque_1;
 408         u8      cmd_err;
 409         u8      valid;
 410 };
 411 #define HWRM_NA_SIGNATURE ((__le32)(-1))
 412 #define HWRM_MAX_REQ_LEN 128
 413 #define HWRM_MAX_RESP_LEN 704
 414 #define HW_HASH_INDEX_SIZE 0x80
 415 #define HW_HASH_KEY_SIZE 40
 416 #define HWRM_RESP_VALID_KEY 1
 417 #define HWRM_TARGET_ID_BONO 0xFFF8
 418 #define HWRM_TARGET_ID_KONG 0xFFF9
 419 #define HWRM_TARGET_ID_APE 0xFFFA
 420 #define HWRM_TARGET_ID_TOOLS 0xFFFD
 421 #define HWRM_VERSION_MAJOR 1
 422 #define HWRM_VERSION_MINOR 10
 423 #define HWRM_VERSION_UPDATE 0
 424 #define HWRM_VERSION_RSVD 100
 425 #define HWRM_VERSION_STR "1.10.0.100"
 426 
 427 /* hwrm_ver_get_input (size:192b/24B) */
 428 struct hwrm_ver_get_input {
 429         __le16  req_type;
 430         __le16  cmpl_ring;
 431         __le16  seq_id;
 432         __le16  target_id;
 433         __le64  resp_addr;
 434         u8      hwrm_intf_maj;
 435         u8      hwrm_intf_min;
 436         u8      hwrm_intf_upd;
 437         u8      unused_0[5];
 438 };
 439 
 440 /* hwrm_ver_get_output (size:1408b/176B) */
 441 struct hwrm_ver_get_output {
 442         __le16  error_code;
 443         __le16  req_type;
 444         __le16  seq_id;
 445         __le16  resp_len;
 446         u8      hwrm_intf_maj_8b;
 447         u8      hwrm_intf_min_8b;
 448         u8      hwrm_intf_upd_8b;
 449         u8      hwrm_intf_rsvd_8b;
 450         u8      hwrm_fw_maj_8b;
 451         u8      hwrm_fw_min_8b;
 452         u8      hwrm_fw_bld_8b;
 453         u8      hwrm_fw_rsvd_8b;
 454         u8      mgmt_fw_maj_8b;
 455         u8      mgmt_fw_min_8b;
 456         u8      mgmt_fw_bld_8b;
 457         u8      mgmt_fw_rsvd_8b;
 458         u8      netctrl_fw_maj_8b;
 459         u8      netctrl_fw_min_8b;
 460         u8      netctrl_fw_bld_8b;
 461         u8      netctrl_fw_rsvd_8b;
 462         __le32  dev_caps_cfg;
 463         #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED                  0x1UL
 464         #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED                  0x2UL
 465         #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED                      0x4UL
 466         #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED                       0x8UL
 467         #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED                   0x10UL
 468         #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED              0x20UL
 469         #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED     0x40UL
 470         #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED         0x80UL
 471         #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED                     0x100UL
 472         #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED                     0x200UL
 473         #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED              0x400UL
 474         #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED                        0x800UL
 475         #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED              0x1000UL
 476         #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED                      0x2000UL
 477         u8      roce_fw_maj_8b;
 478         u8      roce_fw_min_8b;
 479         u8      roce_fw_bld_8b;
 480         u8      roce_fw_rsvd_8b;
 481         char    hwrm_fw_name[16];
 482         char    mgmt_fw_name[16];
 483         char    netctrl_fw_name[16];
 484         char    active_pkg_name[16];
 485         char    roce_fw_name[16];
 486         __le16  chip_num;
 487         u8      chip_rev;
 488         u8      chip_metal;
 489         u8      chip_bond_id;
 490         u8      chip_platform_type;
 491         #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC      0x0UL
 492         #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA      0x1UL
 493         #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
 494         #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST     VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
 495         __le16  max_req_win_len;
 496         __le16  max_resp_len;
 497         __le16  def_req_timeout;
 498         u8      flags;
 499         #define VER_GET_RESP_FLAGS_DEV_NOT_RDY       0x1UL
 500         #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL     0x2UL
 501         u8      unused_0[2];
 502         u8      always_1;
 503         __le16  hwrm_intf_major;
 504         __le16  hwrm_intf_minor;
 505         __le16  hwrm_intf_build;
 506         __le16  hwrm_intf_patch;
 507         __le16  hwrm_fw_major;
 508         __le16  hwrm_fw_minor;
 509         __le16  hwrm_fw_build;
 510         __le16  hwrm_fw_patch;
 511         __le16  mgmt_fw_major;
 512         __le16  mgmt_fw_minor;
 513         __le16  mgmt_fw_build;
 514         __le16  mgmt_fw_patch;
 515         __le16  netctrl_fw_major;
 516         __le16  netctrl_fw_minor;
 517         __le16  netctrl_fw_build;
 518         __le16  netctrl_fw_patch;
 519         __le16  roce_fw_major;
 520         __le16  roce_fw_minor;
 521         __le16  roce_fw_build;
 522         __le16  roce_fw_patch;
 523         __le16  max_ext_req_len;
 524         u8      unused_1[5];
 525         u8      valid;
 526 };
 527 
 528 /* eject_cmpl (size:128b/16B) */
 529 struct eject_cmpl {
 530         __le16  type;
 531         #define EJECT_CMPL_TYPE_MASK       0x3fUL
 532         #define EJECT_CMPL_TYPE_SFT        0
 533         #define EJECT_CMPL_TYPE_STAT_EJECT   0x1aUL
 534         #define EJECT_CMPL_TYPE_LAST        EJECT_CMPL_TYPE_STAT_EJECT
 535         #define EJECT_CMPL_FLAGS_MASK      0xffc0UL
 536         #define EJECT_CMPL_FLAGS_SFT       6
 537         #define EJECT_CMPL_FLAGS_ERROR      0x40UL
 538         __le16  len;
 539         __le32  opaque;
 540         __le16  v;
 541         #define EJECT_CMPL_V                              0x1UL
 542         #define EJECT_CMPL_ERRORS_MASK                    0xfffeUL
 543         #define EJECT_CMPL_ERRORS_SFT                     1
 544         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK        0xeUL
 545         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT         1
 546         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER     (0x0UL << 1)
 547         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT   (0x1UL << 1)
 548         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT    (0x3UL << 1)
 549         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH         (0x5UL << 1)
 550         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST         EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
 551         __le16  reserved16;
 552         __le32  unused_2;
 553 };
 554 
 555 /* hwrm_cmpl (size:128b/16B) */
 556 struct hwrm_cmpl {
 557         __le16  type;
 558         #define CMPL_TYPE_MASK     0x3fUL
 559         #define CMPL_TYPE_SFT      0
 560         #define CMPL_TYPE_HWRM_DONE  0x20UL
 561         #define CMPL_TYPE_LAST      CMPL_TYPE_HWRM_DONE
 562         __le16  sequence_id;
 563         __le32  unused_1;
 564         __le32  v;
 565         #define CMPL_V     0x1UL
 566         __le32  unused_3;
 567 };
 568 
 569 /* hwrm_fwd_req_cmpl (size:128b/16B) */
 570 struct hwrm_fwd_req_cmpl {
 571         __le16  req_len_type;
 572         #define FWD_REQ_CMPL_TYPE_MASK        0x3fUL
 573         #define FWD_REQ_CMPL_TYPE_SFT         0
 574         #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ  0x22UL
 575         #define FWD_REQ_CMPL_TYPE_LAST         FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
 576         #define FWD_REQ_CMPL_REQ_LEN_MASK     0xffc0UL
 577         #define FWD_REQ_CMPL_REQ_LEN_SFT      6
 578         __le16  source_id;
 579         __le32  unused0;
 580         __le32  req_buf_addr_v[2];
 581         #define FWD_REQ_CMPL_V                0x1UL
 582         #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
 583         #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
 584 };
 585 
 586 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
 587 struct hwrm_fwd_resp_cmpl {
 588         __le16  type;
 589         #define FWD_RESP_CMPL_TYPE_MASK         0x3fUL
 590         #define FWD_RESP_CMPL_TYPE_SFT          0
 591         #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP  0x24UL
 592         #define FWD_RESP_CMPL_TYPE_LAST          FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
 593         __le16  source_id;
 594         __le16  resp_len;
 595         __le16  unused_1;
 596         __le32  resp_buf_addr_v[2];
 597         #define FWD_RESP_CMPL_V                 0x1UL
 598         #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
 599         #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
 600 };
 601 
 602 /* hwrm_async_event_cmpl (size:128b/16B) */
 603 struct hwrm_async_event_cmpl {
 604         __le16  type;
 605         #define ASYNC_EVENT_CMPL_TYPE_MASK            0x3fUL
 606         #define ASYNC_EVENT_CMPL_TYPE_SFT             0
 607         #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 608         #define ASYNC_EVENT_CMPL_TYPE_LAST             ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
 609         __le16  event_id;
 610         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE         0x0UL
 611         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE            0x1UL
 612         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE          0x2UL
 613         #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE          0x3UL
 614         #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED      0x4UL
 615         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
 616         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE      0x6UL
 617         #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE        0x7UL
 618         #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY               0x8UL
 619         #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY             0x9UL
 620         #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD           0x10UL
 621         #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD             0x11UL
 622         #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT        0x12UL
 623         #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD             0x20UL
 624         #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD               0x21UL
 625         #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR                     0x30UL
 626         #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE         0x31UL
 627         #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE   0x32UL
 628         #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE              0x33UL
 629         #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE            0x34UL
 630         #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE        0x35UL
 631         #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED               0x36UL
 632         #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION         0x37UL
 633         #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ        0x38UL
 634         #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE       0x39UL
 635         #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE     0x3aUL
 636         #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE            0x3bUL
 637         #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE             0x3cUL
 638         #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE  0x3dUL
 639         #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE   0x3eUL
 640         #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG               0xfeUL
 641         #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR                 0xffUL
 642         #define ASYNC_EVENT_CMPL_EVENT_ID_LAST                      ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
 643         __le32  event_data2;
 644         u8      opaque_v;
 645         #define ASYNC_EVENT_CMPL_V          0x1UL
 646         #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
 647         #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
 648         u8      timestamp_lo;
 649         __le16  timestamp_hi;
 650         __le32  event_data1;
 651 };
 652 
 653 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
 654 struct hwrm_async_event_cmpl_link_status_change {
 655         __le16  type;
 656         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK            0x3fUL
 657         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT             0
 658         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 659         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
 660         __le16  event_id;
 661         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
 662         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST              ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
 663         __le32  event_data2;
 664         u8      opaque_v;
 665         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V          0x1UL
 666         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
 667         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
 668         u8      timestamp_lo;
 669         __le16  timestamp_hi;
 670         __le32  event_data1;
 671         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE     0x1UL
 672         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN  0x0UL
 673         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP    0x1UL
 674         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
 675         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK       0xeUL
 676         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT        1
 677         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK    0xffff0UL
 678         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT     4
 679         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK      0xff00000UL
 680         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT       20
 681 };
 682 
 683 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
 684 struct hwrm_async_event_cmpl_port_conn_not_allowed {
 685         __le16  type;
 686         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK            0x3fUL
 687         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT             0
 688         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 689         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST             ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
 690         __le16  event_id;
 691         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
 692         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
 693         __le32  event_data2;
 694         u8      opaque_v;
 695         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V          0x1UL
 696         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
 697         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
 698         u8      timestamp_lo;
 699         __le16  timestamp_hi;
 700         __le32  event_data1;
 701         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK                 0xffffUL
 702         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT                  0
 703         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK      0xff0000UL
 704         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT       16
 705         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE        (0x0UL << 16)
 706         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX   (0x1UL << 16)
 707         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG  (0x2UL << 16)
 708         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN     (0x3UL << 16)
 709         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST       ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
 710 };
 711 
 712 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
 713 struct hwrm_async_event_cmpl_link_speed_cfg_change {
 714         __le16  type;
 715         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK            0x3fUL
 716         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT             0
 717         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 718         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
 719         __le16  event_id;
 720         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
 721         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
 722         __le32  event_data2;
 723         u8      opaque_v;
 724         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V          0x1UL
 725         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
 726         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
 727         u8      timestamp_lo;
 728         __le16  timestamp_hi;
 729         __le32  event_data1;
 730         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK                     0xffffUL
 731         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT                      0
 732         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE     0x10000UL
 733         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG           0x20000UL
 734 };
 735 
 736 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
 737 struct hwrm_async_event_cmpl_reset_notify {
 738         __le16  type;
 739         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK            0x3fUL
 740         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT             0
 741         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 742         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST             ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
 743         __le16  event_id;
 744         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
 745         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST        ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
 746         __le32  event_data2;
 747         u8      opaque_v;
 748         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V          0x1UL
 749         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
 750         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
 751         u8      timestamp_lo;
 752         __le16  timestamp_hi;
 753         __le32  event_data1;
 754         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK                  0xffUL
 755         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT                   0
 756         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE    0x1UL
 757         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN           0x2UL
 758         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST                   ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
 759         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK                    0xff00UL
 760         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT                     8
 761         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST  (0x1UL << 8)
 762         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL        (0x2UL << 8)
 763         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL    (0x3UL << 8)
 764         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST                     ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
 765         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK           0xffff0000UL
 766         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT            16
 767 };
 768 
 769 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
 770 struct hwrm_async_event_cmpl_error_recovery {
 771         __le16  type;
 772         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK            0x3fUL
 773         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT             0
 774         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 775         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
 776         __le16  event_id;
 777         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL
 778         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST          ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
 779         __le32  event_data2;
 780         u8      opaque_v;
 781         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V          0x1UL
 782         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL
 783         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
 784         u8      timestamp_lo;
 785         __le16  timestamp_hi;
 786         __le32  event_data1;
 787         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK                 0xffUL
 788         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT                  0
 789         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC           0x1UL
 790         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED      0x2UL
 791 };
 792 
 793 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
 794 struct hwrm_async_event_cmpl_vf_cfg_change {
 795         __le16  type;
 796         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK            0x3fUL
 797         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT             0
 798         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 799         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
 800         __le16  event_id;
 801         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
 802         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST         ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
 803         __le32  event_data2;
 804         u8      opaque_v;
 805         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V          0x1UL
 806         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
 807         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
 808         u8      timestamp_lo;
 809         __le16  timestamp_hi;
 810         __le32  event_data1;
 811         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE                0x1UL
 812         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE                0x2UL
 813         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE      0x4UL
 814         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE          0x8UL
 815         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE     0x10UL
 816 };
 817 
 818 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
 819 struct hwrm_async_event_cmpl_default_vnic_change {
 820         __le16  type;
 821         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK            0x3fUL
 822         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT             0
 823         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 824         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
 825         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK         0xffc0UL
 826         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT          6
 827         __le16  event_id;
 828         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
 829         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST                   ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
 830         __le32  event_data2;
 831         u8      opaque_v;
 832         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V          0x1UL
 833         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
 834         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
 835         u8      timestamp_lo;
 836         __le16  timestamp_hi;
 837         __le32  event_data1;
 838         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK          0x3UL
 839         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT           0
 840         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC  0x1UL
 841         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE   0x2UL
 842         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST           ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
 843         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK                   0x3fcUL
 844         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT                    2
 845         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK                   0x3fffc00UL
 846         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT                    10
 847 };
 848 
 849 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
 850 struct hwrm_async_event_cmpl_hw_flow_aged {
 851         __le16  type;
 852         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK            0x3fUL
 853         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT             0
 854         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 855         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST             ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
 856         __le16  event_id;
 857         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
 858         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST        ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
 859         __le32  event_data2;
 860         u8      opaque_v;
 861         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V          0x1UL
 862         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
 863         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
 864         u8      timestamp_lo;
 865         __le16  timestamp_hi;
 866         __le32  event_data1;
 867         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK       0x7fffffffUL
 868         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT        0
 869         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION     0x80000000UL
 870         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX    (0x0UL << 31)
 871         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX    (0x1UL << 31)
 872         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
 873 };
 874 
 875 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
 876 struct hwrm_async_event_cmpl_eem_cache_flush_req {
 877         __le16  type;
 878         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK            0x3fUL
 879         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT             0
 880         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 881         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST             ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
 882         __le16  event_id;
 883         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
 884         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST               ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
 885         __le32  event_data2;
 886         u8      opaque_v;
 887         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V          0x1UL
 888         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL
 889         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
 890         u8      timestamp_lo;
 891         __le16  timestamp_hi;
 892         __le32  event_data1;
 893 };
 894 
 895 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
 896 struct hwrm_async_event_cmpl_eem_cache_flush_done {
 897         __le16  type;
 898         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK            0x3fUL
 899         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT             0
 900         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 901         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST             ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
 902         __le16  event_id;
 903         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
 904         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST                ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
 905         __le32  event_data2;
 906         u8      opaque_v;
 907         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V          0x1UL
 908         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL
 909         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
 910         u8      timestamp_lo;
 911         __le16  timestamp_hi;
 912         __le32  event_data1;
 913         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL
 914         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
 915 };
 916 
 917 /* hwrm_func_reset_input (size:192b/24B) */
 918 struct hwrm_func_reset_input {
 919         __le16  req_type;
 920         __le16  cmpl_ring;
 921         __le16  seq_id;
 922         __le16  target_id;
 923         __le64  resp_addr;
 924         __le32  enables;
 925         #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID     0x1UL
 926         __le16  vf_id;
 927         u8      func_reset_level;
 928         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL      0x0UL
 929         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME       0x1UL
 930         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
 931         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF       0x3UL
 932         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST         FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
 933         u8      unused_0;
 934 };
 935 
 936 /* hwrm_func_reset_output (size:128b/16B) */
 937 struct hwrm_func_reset_output {
 938         __le16  error_code;
 939         __le16  req_type;
 940         __le16  seq_id;
 941         __le16  resp_len;
 942         u8      unused_0[7];
 943         u8      valid;
 944 };
 945 
 946 /* hwrm_func_getfid_input (size:192b/24B) */
 947 struct hwrm_func_getfid_input {
 948         __le16  req_type;
 949         __le16  cmpl_ring;
 950         __le16  seq_id;
 951         __le16  target_id;
 952         __le64  resp_addr;
 953         __le32  enables;
 954         #define FUNC_GETFID_REQ_ENABLES_PCI_ID     0x1UL
 955         __le16  pci_id;
 956         u8      unused_0[2];
 957 };
 958 
 959 /* hwrm_func_getfid_output (size:128b/16B) */
 960 struct hwrm_func_getfid_output {
 961         __le16  error_code;
 962         __le16  req_type;
 963         __le16  seq_id;
 964         __le16  resp_len;
 965         __le16  fid;
 966         u8      unused_0[5];
 967         u8      valid;
 968 };
 969 
 970 /* hwrm_func_vf_alloc_input (size:192b/24B) */
 971 struct hwrm_func_vf_alloc_input {
 972         __le16  req_type;
 973         __le16  cmpl_ring;
 974         __le16  seq_id;
 975         __le16  target_id;
 976         __le64  resp_addr;
 977         __le32  enables;
 978         #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID     0x1UL
 979         __le16  first_vf_id;
 980         __le16  num_vfs;
 981 };
 982 
 983 /* hwrm_func_vf_alloc_output (size:128b/16B) */
 984 struct hwrm_func_vf_alloc_output {
 985         __le16  error_code;
 986         __le16  req_type;
 987         __le16  seq_id;
 988         __le16  resp_len;
 989         __le16  first_vf_id;
 990         u8      unused_0[5];
 991         u8      valid;
 992 };
 993 
 994 /* hwrm_func_vf_free_input (size:192b/24B) */
 995 struct hwrm_func_vf_free_input {
 996         __le16  req_type;
 997         __le16  cmpl_ring;
 998         __le16  seq_id;
 999         __le16  target_id;
1000         __le64  resp_addr;
1001         __le32  enables;
1002         #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID     0x1UL
1003         __le16  first_vf_id;
1004         __le16  num_vfs;
1005 };
1006 
1007 /* hwrm_func_vf_free_output (size:128b/16B) */
1008 struct hwrm_func_vf_free_output {
1009         __le16  error_code;
1010         __le16  req_type;
1011         __le16  seq_id;
1012         __le16  resp_len;
1013         u8      unused_0[7];
1014         u8      valid;
1015 };
1016 
1017 /* hwrm_func_vf_cfg_input (size:448b/56B) */
1018 struct hwrm_func_vf_cfg_input {
1019         __le16  req_type;
1020         __le16  cmpl_ring;
1021         __le16  seq_id;
1022         __le16  target_id;
1023         __le64  resp_addr;
1024         __le32  enables;
1025         #define FUNC_VF_CFG_REQ_ENABLES_MTU                  0x1UL
1026         #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN           0x2UL
1027         #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR       0x4UL
1028         #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR        0x8UL
1029         #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS      0x10UL
1030         #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS       0x20UL
1031         #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS         0x40UL
1032         #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS         0x80UL
1033         #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS          0x100UL
1034         #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS            0x200UL
1035         #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS        0x400UL
1036         #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS     0x800UL
1037         __le16  mtu;
1038         __le16  guest_vlan;
1039         __le16  async_event_cr;
1040         u8      dflt_mac_addr[6];
1041         __le32  flags;
1042         #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST             0x1UL
1043         #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST             0x2UL
1044         #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST           0x4UL
1045         #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST     0x8UL
1046         #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST       0x10UL
1047         #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST       0x20UL
1048         #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST           0x40UL
1049         #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST         0x80UL
1050         __le16  num_rsscos_ctxs;
1051         __le16  num_cmpl_rings;
1052         __le16  num_tx_rings;
1053         __le16  num_rx_rings;
1054         __le16  num_l2_ctxs;
1055         __le16  num_vnics;
1056         __le16  num_stat_ctxs;
1057         __le16  num_hw_ring_grps;
1058         u8      unused_0[4];
1059 };
1060 
1061 /* hwrm_func_vf_cfg_output (size:128b/16B) */
1062 struct hwrm_func_vf_cfg_output {
1063         __le16  error_code;
1064         __le16  req_type;
1065         __le16  seq_id;
1066         __le16  resp_len;
1067         u8      unused_0[7];
1068         u8      valid;
1069 };
1070 
1071 /* hwrm_func_qcaps_input (size:192b/24B) */
1072 struct hwrm_func_qcaps_input {
1073         __le16  req_type;
1074         __le16  cmpl_ring;
1075         __le16  seq_id;
1076         __le16  target_id;
1077         __le64  resp_addr;
1078         __le16  fid;
1079         u8      unused_0[6];
1080 };
1081 
1082 /* hwrm_func_qcaps_output (size:640b/80B) */
1083 struct hwrm_func_qcaps_output {
1084         __le16  error_code;
1085         __le16  req_type;
1086         __le16  seq_id;
1087         __le16  resp_len;
1088         __le16  fid;
1089         __le16  port_id;
1090         __le32  flags;
1091         #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED                   0x1UL
1092         #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING               0x2UL
1093         #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED                         0x4UL
1094         #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED                     0x8UL
1095         #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED                     0x10UL
1096         #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED                0x20UL
1097         #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED                     0x40UL
1098         #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED                  0x80UL
1099         #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED                   0x100UL
1100         #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED               0x200UL
1101         #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED                   0x400UL
1102         #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED            0x800UL
1103         #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED            0x1000UL
1104         #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED             0x2000UL
1105         #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED               0x4000UL
1106         #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED              0x8000UL
1107         #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED                  0x10000UL
1108         #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED                  0x20000UL
1109         #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED                    0x40000UL
1110         #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED           0x80000UL
1111         #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE                         0x100000UL
1112         #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC                 0x200000UL
1113         #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE                     0x400000UL
1114         #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE                0x800000UL
1115         #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED                   0x1000000UL
1116         #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD                    0x2000000UL
1117         #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED     0x4000000UL
1118         u8      mac_address[6];
1119         __le16  max_rsscos_ctx;
1120         __le16  max_cmpl_rings;
1121         __le16  max_tx_rings;
1122         __le16  max_rx_rings;
1123         __le16  max_l2_ctxs;
1124         __le16  max_vnics;
1125         __le16  first_vf_id;
1126         __le16  max_vfs;
1127         __le16  max_stat_ctx;
1128         __le32  max_encap_records;
1129         __le32  max_decap_records;
1130         __le32  max_tx_em_flows;
1131         __le32  max_tx_wm_flows;
1132         __le32  max_rx_em_flows;
1133         __le32  max_rx_wm_flows;
1134         __le32  max_mcast_filters;
1135         __le32  max_flow_id;
1136         __le32  max_hw_ring_grps;
1137         __le16  max_sp_tx_rings;
1138         u8      unused_0;
1139         u8      valid;
1140 };
1141 
1142 /* hwrm_func_qcfg_input (size:192b/24B) */
1143 struct hwrm_func_qcfg_input {
1144         __le16  req_type;
1145         __le16  cmpl_ring;
1146         __le16  seq_id;
1147         __le16  target_id;
1148         __le64  resp_addr;
1149         __le16  fid;
1150         u8      unused_0[6];
1151 };
1152 
1153 /* hwrm_func_qcfg_output (size:704b/88B) */
1154 struct hwrm_func_qcfg_output {
1155         __le16  error_code;
1156         __le16  req_type;
1157         __le16  seq_id;
1158         __le16  resp_len;
1159         __le16  fid;
1160         __le16  port_id;
1161         __le16  vlan;
1162         __le16  flags;
1163         #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED     0x1UL
1164         #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED          0x2UL
1165         #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED        0x4UL
1166         #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED     0x8UL
1167         #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED        0x10UL
1168         #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST                   0x20UL
1169         #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF                   0x40UL
1170         #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED          0x80UL
1171         #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS      0x100UL
1172         u8      mac_address[6];
1173         __le16  pci_id;
1174         __le16  alloc_rsscos_ctx;
1175         __le16  alloc_cmpl_rings;
1176         __le16  alloc_tx_rings;
1177         __le16  alloc_rx_rings;
1178         __le16  alloc_l2_ctx;
1179         __le16  alloc_vnics;
1180         __le16  mtu;
1181         __le16  mru;
1182         __le16  stat_ctx_id;
1183         u8      port_partition_type;
1184         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF     0x0UL
1185         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS    0x1UL
1186         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
1187         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
1188         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
1189         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
1190         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST   FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
1191         u8      port_pf_cnt;
1192         #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
1193         #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST   FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
1194         __le16  dflt_vnic_id;
1195         __le16  max_mtu_configured;
1196         __le32  min_bw;
1197         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK             0xfffffffUL
1198         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT              0
1199         #define FUNC_QCFG_RESP_MIN_BW_SCALE                     0x10000000UL
1200         #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS                  (0x0UL << 28)
1201         #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
1202         #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST                 FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
1203         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1204         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT         29
1205         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
1206         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
1207         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
1208         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
1209         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1210         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
1211         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
1212         __le32  max_bw;
1213         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK             0xfffffffUL
1214         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT              0
1215         #define FUNC_QCFG_RESP_MAX_BW_SCALE                     0x10000000UL
1216         #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS                  (0x0UL << 28)
1217         #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
1218         #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST                 FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
1219         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1220         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT         29
1221         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
1222         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
1223         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
1224         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
1225         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1226         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
1227         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
1228         u8      evb_mode;
1229         #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
1230         #define FUNC_QCFG_RESP_EVB_MODE_VEB    0x1UL
1231         #define FUNC_QCFG_RESP_EVB_MODE_VEPA   0x2UL
1232         #define FUNC_QCFG_RESP_EVB_MODE_LAST  FUNC_QCFG_RESP_EVB_MODE_VEPA
1233         u8      options;
1234         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK         0x3UL
1235         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT          0
1236         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64        0x0UL
1237         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128       0x1UL
1238         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST          FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
1239         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK       0xcUL
1240         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT        2
1241         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (0x0UL << 2)
1242         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP    (0x1UL << 2)
1243         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO         (0x2UL << 2)
1244         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST        FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
1245         #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK                   0xf0UL
1246         #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT                    4
1247         __le16  alloc_vfs;
1248         __le32  alloc_mcast_filters;
1249         __le32  alloc_hw_ring_grps;
1250         __le16  alloc_sp_tx_rings;
1251         __le16  alloc_stat_ctx;
1252         __le16  alloc_msix;
1253         __le16  registered_vfs;
1254         __le16  l2_doorbell_bar_size_kb;
1255         u8      unused_1;
1256         u8      always_1;
1257         __le32  reset_addr_poll;
1258         u8      unused_2[3];
1259         u8      valid;
1260 };
1261 
1262 /* hwrm_func_cfg_input (size:704b/88B) */
1263 struct hwrm_func_cfg_input {
1264         __le16  req_type;
1265         __le16  cmpl_ring;
1266         __le16  seq_id;
1267         __le16  target_id;
1268         __le64  resp_addr;
1269         __le16  fid;
1270         __le16  num_msix;
1271         __le32  flags;
1272         #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE     0x1UL
1273         #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE      0x2UL
1274         #define FUNC_CFG_REQ_FLAGS_RSVD_MASK                      0x1fcUL
1275         #define FUNC_CFG_REQ_FLAGS_RSVD_SFT                       2
1276         #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE        0x200UL
1277         #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE       0x400UL
1278         #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST               0x800UL
1279         #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC         0x1000UL
1280         #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST                 0x2000UL
1281         #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST                 0x4000UL
1282         #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST               0x8000UL
1283         #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST         0x10000UL
1284         #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST           0x20000UL
1285         #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST           0x40000UL
1286         #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST               0x80000UL
1287         #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST             0x100000UL
1288         #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE              0x200000UL
1289         #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC          0x400000UL
1290         #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST                 0x800000UL
1291         #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE             0x1000000UL
1292         #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS        0x2000000UL
1293         __le32  enables;
1294         #define FUNC_CFG_REQ_ENABLES_MTU                     0x1UL
1295         #define FUNC_CFG_REQ_ENABLES_MRU                     0x2UL
1296         #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS         0x4UL
1297         #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS          0x8UL
1298         #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS            0x10UL
1299         #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS            0x20UL
1300         #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS             0x40UL
1301         #define FUNC_CFG_REQ_ENABLES_NUM_VNICS               0x80UL
1302         #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS           0x100UL
1303         #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR           0x200UL
1304         #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN               0x400UL
1305         #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR            0x800UL
1306         #define FUNC_CFG_REQ_ENABLES_MIN_BW                  0x1000UL
1307         #define FUNC_CFG_REQ_ENABLES_MAX_BW                  0x2000UL
1308         #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR          0x4000UL
1309         #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE     0x8000UL
1310         #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS       0x10000UL
1311         #define FUNC_CFG_REQ_ENABLES_EVB_MODE                0x20000UL
1312         #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS       0x40000UL
1313         #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS        0x80000UL
1314         #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE          0x100000UL
1315         #define FUNC_CFG_REQ_ENABLES_NUM_MSIX                0x200000UL
1316         #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE        0x400000UL
1317         __le16  mtu;
1318         __le16  mru;
1319         __le16  num_rsscos_ctxs;
1320         __le16  num_cmpl_rings;
1321         __le16  num_tx_rings;
1322         __le16  num_rx_rings;
1323         __le16  num_l2_ctxs;
1324         __le16  num_vnics;
1325         __le16  num_stat_ctxs;
1326         __le16  num_hw_ring_grps;
1327         u8      dflt_mac_addr[6];
1328         __le16  dflt_vlan;
1329         __be32  dflt_ip_addr[4];
1330         __le32  min_bw;
1331         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK             0xfffffffUL
1332         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT              0
1333         #define FUNC_CFG_REQ_MIN_BW_SCALE                     0x10000000UL
1334         #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS                  (0x0UL << 28)
1335         #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
1336         #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST                 FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
1337         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1338         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT         29
1339         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
1340         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
1341         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
1342         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
1343         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1344         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
1345         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
1346         __le32  max_bw;
1347         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK             0xfffffffUL
1348         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT              0
1349         #define FUNC_CFG_REQ_MAX_BW_SCALE                     0x10000000UL
1350         #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS                  (0x0UL << 28)
1351         #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
1352         #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST                 FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
1353         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1354         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT         29
1355         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
1356         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
1357         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
1358         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
1359         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1360         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
1361         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
1362         __le16  async_event_cr;
1363         u8      vlan_antispoof_mode;
1364         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK                 0x0UL
1365         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN           0x1UL
1366         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE       0x2UL
1367         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
1368         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST                   FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
1369         u8      allowed_vlan_pris;
1370         u8      evb_mode;
1371         #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
1372         #define FUNC_CFG_REQ_EVB_MODE_VEB    0x1UL
1373         #define FUNC_CFG_REQ_EVB_MODE_VEPA   0x2UL
1374         #define FUNC_CFG_REQ_EVB_MODE_LAST  FUNC_CFG_REQ_EVB_MODE_VEPA
1375         u8      options;
1376         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK         0x3UL
1377         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT          0
1378         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64        0x0UL
1379         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128       0x1UL
1380         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST          FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
1381         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK       0xcUL
1382         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT        2
1383         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (0x0UL << 2)
1384         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP    (0x1UL << 2)
1385         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO         (0x2UL << 2)
1386         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST        FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
1387         #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK                   0xf0UL
1388         #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT                    4
1389         __le16  num_mcast_filters;
1390 };
1391 
1392 /* hwrm_func_cfg_output (size:128b/16B) */
1393 struct hwrm_func_cfg_output {
1394         __le16  error_code;
1395         __le16  req_type;
1396         __le16  seq_id;
1397         __le16  resp_len;
1398         u8      unused_0[7];
1399         u8      valid;
1400 };
1401 
1402 /* hwrm_func_qstats_input (size:192b/24B) */
1403 struct hwrm_func_qstats_input {
1404         __le16  req_type;
1405         __le16  cmpl_ring;
1406         __le16  seq_id;
1407         __le16  target_id;
1408         __le64  resp_addr;
1409         __le16  fid;
1410         u8      flags;
1411         #define FUNC_QSTATS_REQ_FLAGS_UNUSED    0x0UL
1412         #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL
1413         #define FUNC_QSTATS_REQ_FLAGS_LAST     FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY
1414         u8      unused_0[5];
1415 };
1416 
1417 /* hwrm_func_qstats_output (size:1408b/176B) */
1418 struct hwrm_func_qstats_output {
1419         __le16  error_code;
1420         __le16  req_type;
1421         __le16  seq_id;
1422         __le16  resp_len;
1423         __le64  tx_ucast_pkts;
1424         __le64  tx_mcast_pkts;
1425         __le64  tx_bcast_pkts;
1426         __le64  tx_discard_pkts;
1427         __le64  tx_drop_pkts;
1428         __le64  tx_ucast_bytes;
1429         __le64  tx_mcast_bytes;
1430         __le64  tx_bcast_bytes;
1431         __le64  rx_ucast_pkts;
1432         __le64  rx_mcast_pkts;
1433         __le64  rx_bcast_pkts;
1434         __le64  rx_discard_pkts;
1435         __le64  rx_drop_pkts;
1436         __le64  rx_ucast_bytes;
1437         __le64  rx_mcast_bytes;
1438         __le64  rx_bcast_bytes;
1439         __le64  rx_agg_pkts;
1440         __le64  rx_agg_bytes;
1441         __le64  rx_agg_events;
1442         __le64  rx_agg_aborts;
1443         u8      unused_0[7];
1444         u8      valid;
1445 };
1446 
1447 /* hwrm_func_clr_stats_input (size:192b/24B) */
1448 struct hwrm_func_clr_stats_input {
1449         __le16  req_type;
1450         __le16  cmpl_ring;
1451         __le16  seq_id;
1452         __le16  target_id;
1453         __le64  resp_addr;
1454         __le16  fid;
1455         u8      unused_0[6];
1456 };
1457 
1458 /* hwrm_func_clr_stats_output (size:128b/16B) */
1459 struct hwrm_func_clr_stats_output {
1460         __le16  error_code;
1461         __le16  req_type;
1462         __le16  seq_id;
1463         __le16  resp_len;
1464         u8      unused_0[7];
1465         u8      valid;
1466 };
1467 
1468 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
1469 struct hwrm_func_vf_resc_free_input {
1470         __le16  req_type;
1471         __le16  cmpl_ring;
1472         __le16  seq_id;
1473         __le16  target_id;
1474         __le64  resp_addr;
1475         __le16  vf_id;
1476         u8      unused_0[6];
1477 };
1478 
1479 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
1480 struct hwrm_func_vf_resc_free_output {
1481         __le16  error_code;
1482         __le16  req_type;
1483         __le16  seq_id;
1484         __le16  resp_len;
1485         u8      unused_0[7];
1486         u8      valid;
1487 };
1488 
1489 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
1490 struct hwrm_func_drv_rgtr_input {
1491         __le16  req_type;
1492         __le16  cmpl_ring;
1493         __le16  seq_id;
1494         __le16  target_id;
1495         __le64  resp_addr;
1496         __le32  flags;
1497         #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE               0x1UL
1498         #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE              0x2UL
1499         #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE             0x4UL
1500         #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE     0x8UL
1501         #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT          0x10UL
1502         #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT     0x20UL
1503         __le32  enables;
1504         #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE             0x1UL
1505         #define FUNC_DRV_RGTR_REQ_ENABLES_VER                 0x2UL
1506         #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP           0x4UL
1507         #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD          0x8UL
1508         #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD     0x10UL
1509         __le16  os_type;
1510         #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN   0x0UL
1511         #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER     0x1UL
1512         #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS     0xeUL
1513         #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS   0x12UL
1514         #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS   0x1dUL
1515         #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX     0x24UL
1516         #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD   0x2aUL
1517         #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI      0x68UL
1518         #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864    0x73UL
1519         #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
1520         #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI      0x8000UL
1521         #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST     FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
1522         u8      ver_maj_8b;
1523         u8      ver_min_8b;
1524         u8      ver_upd_8b;
1525         u8      unused_0[3];
1526         __le32  timestamp;
1527         u8      unused_1[4];
1528         __le32  vf_req_fwd[8];
1529         __le32  async_event_fwd[8];
1530         __le16  ver_maj;
1531         __le16  ver_min;
1532         __le16  ver_upd;
1533         __le16  ver_patch;
1534 };
1535 
1536 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
1537 struct hwrm_func_drv_rgtr_output {
1538         __le16  error_code;
1539         __le16  req_type;
1540         __le16  seq_id;
1541         __le16  resp_len;
1542         __le32  flags;
1543         #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED     0x1UL
1544         u8      unused_0[3];
1545         u8      valid;
1546 };
1547 
1548 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
1549 struct hwrm_func_drv_unrgtr_input {
1550         __le16  req_type;
1551         __le16  cmpl_ring;
1552         __le16  seq_id;
1553         __le16  target_id;
1554         __le64  resp_addr;
1555         __le32  flags;
1556         #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN     0x1UL
1557         u8      unused_0[4];
1558 };
1559 
1560 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
1561 struct hwrm_func_drv_unrgtr_output {
1562         __le16  error_code;
1563         __le16  req_type;
1564         __le16  seq_id;
1565         __le16  resp_len;
1566         u8      unused_0[7];
1567         u8      valid;
1568 };
1569 
1570 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
1571 struct hwrm_func_buf_rgtr_input {
1572         __le16  req_type;
1573         __le16  cmpl_ring;
1574         __le16  seq_id;
1575         __le16  target_id;
1576         __le64  resp_addr;
1577         __le32  enables;
1578         #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID            0x1UL
1579         #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR     0x2UL
1580         __le16  vf_id;
1581         __le16  req_buf_num_pages;
1582         __le16  req_buf_page_size;
1583         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
1584         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K  0xcUL
1585         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K  0xdUL
1586         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
1587         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M  0x15UL
1588         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M  0x16UL
1589         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G  0x1eUL
1590         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
1591         __le16  req_buf_len;
1592         __le16  resp_buf_len;
1593         u8      unused_0[2];
1594         __le64  req_buf_page_addr0;
1595         __le64  req_buf_page_addr1;
1596         __le64  req_buf_page_addr2;
1597         __le64  req_buf_page_addr3;
1598         __le64  req_buf_page_addr4;
1599         __le64  req_buf_page_addr5;
1600         __le64  req_buf_page_addr6;
1601         __le64  req_buf_page_addr7;
1602         __le64  req_buf_page_addr8;
1603         __le64  req_buf_page_addr9;
1604         __le64  error_buf_addr;
1605         __le64  resp_buf_addr;
1606 };
1607 
1608 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
1609 struct hwrm_func_buf_rgtr_output {
1610         __le16  error_code;
1611         __le16  req_type;
1612         __le16  seq_id;
1613         __le16  resp_len;
1614         u8      unused_0[7];
1615         u8      valid;
1616 };
1617 
1618 /* hwrm_func_drv_qver_input (size:192b/24B) */
1619 struct hwrm_func_drv_qver_input {
1620         __le16  req_type;
1621         __le16  cmpl_ring;
1622         __le16  seq_id;
1623         __le16  target_id;
1624         __le64  resp_addr;
1625         __le32  reserved;
1626         __le16  fid;
1627         u8      unused_0[2];
1628 };
1629 
1630 /* hwrm_func_drv_qver_output (size:256b/32B) */
1631 struct hwrm_func_drv_qver_output {
1632         __le16  error_code;
1633         __le16  req_type;
1634         __le16  seq_id;
1635         __le16  resp_len;
1636         __le16  os_type;
1637         #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN   0x0UL
1638         #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER     0x1UL
1639         #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS     0xeUL
1640         #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS   0x12UL
1641         #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS   0x1dUL
1642         #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX     0x24UL
1643         #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD   0x2aUL
1644         #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI      0x68UL
1645         #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864    0x73UL
1646         #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
1647         #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI      0x8000UL
1648         #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST     FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
1649         u8      ver_maj_8b;
1650         u8      ver_min_8b;
1651         u8      ver_upd_8b;
1652         u8      unused_0[3];
1653         __le16  ver_maj;
1654         __le16  ver_min;
1655         __le16  ver_upd;
1656         __le16  ver_patch;
1657         u8      unused_1[7];
1658         u8      valid;
1659 };
1660 
1661 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
1662 struct hwrm_func_resource_qcaps_input {
1663         __le16  req_type;
1664         __le16  cmpl_ring;
1665         __le16  seq_id;
1666         __le16  target_id;
1667         __le64  resp_addr;
1668         __le16  fid;
1669         u8      unused_0[6];
1670 };
1671 
1672 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
1673 struct hwrm_func_resource_qcaps_output {
1674         __le16  error_code;
1675         __le16  req_type;
1676         __le16  seq_id;
1677         __le16  resp_len;
1678         __le16  max_vfs;
1679         __le16  max_msix;
1680         __le16  vf_reservation_strategy;
1681         #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL        0x0UL
1682         #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL        0x1UL
1683         #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
1684         #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST          FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
1685         __le16  min_rsscos_ctx;
1686         __le16  max_rsscos_ctx;
1687         __le16  min_cmpl_rings;
1688         __le16  max_cmpl_rings;
1689         __le16  min_tx_rings;
1690         __le16  max_tx_rings;
1691         __le16  min_rx_rings;
1692         __le16  max_rx_rings;
1693         __le16  min_l2_ctxs;
1694         __le16  max_l2_ctxs;
1695         __le16  min_vnics;
1696         __le16  max_vnics;
1697         __le16  min_stat_ctx;
1698         __le16  max_stat_ctx;
1699         __le16  min_hw_ring_grps;
1700         __le16  max_hw_ring_grps;
1701         __le16  max_tx_scheduler_inputs;
1702         __le16  flags;
1703         #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED     0x1UL
1704         u8      unused_0[5];
1705         u8      valid;
1706 };
1707 
1708 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
1709 struct hwrm_func_vf_resource_cfg_input {
1710         __le16  req_type;
1711         __le16  cmpl_ring;
1712         __le16  seq_id;
1713         __le16  target_id;
1714         __le64  resp_addr;
1715         __le16  vf_id;
1716         __le16  max_msix;
1717         __le16  min_rsscos_ctx;
1718         __le16  max_rsscos_ctx;
1719         __le16  min_cmpl_rings;
1720         __le16  max_cmpl_rings;
1721         __le16  min_tx_rings;
1722         __le16  max_tx_rings;
1723         __le16  min_rx_rings;
1724         __le16  max_rx_rings;
1725         __le16  min_l2_ctxs;
1726         __le16  max_l2_ctxs;
1727         __le16  min_vnics;
1728         __le16  max_vnics;
1729         __le16  min_stat_ctx;
1730         __le16  max_stat_ctx;
1731         __le16  min_hw_ring_grps;
1732         __le16  max_hw_ring_grps;
1733         __le16  flags;
1734         #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED     0x1UL
1735         u8      unused_0[2];
1736 };
1737 
1738 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
1739 struct hwrm_func_vf_resource_cfg_output {
1740         __le16  error_code;
1741         __le16  req_type;
1742         __le16  seq_id;
1743         __le16  resp_len;
1744         __le16  reserved_rsscos_ctx;
1745         __le16  reserved_cmpl_rings;
1746         __le16  reserved_tx_rings;
1747         __le16  reserved_rx_rings;
1748         __le16  reserved_l2_ctxs;
1749         __le16  reserved_vnics;
1750         __le16  reserved_stat_ctx;
1751         __le16  reserved_hw_ring_grps;
1752         u8      unused_0[7];
1753         u8      valid;
1754 };
1755 
1756 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
1757 struct hwrm_func_backing_store_qcaps_input {
1758         __le16  req_type;
1759         __le16  cmpl_ring;
1760         __le16  seq_id;
1761         __le16  target_id;
1762         __le64  resp_addr;
1763 };
1764 
1765 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
1766 struct hwrm_func_backing_store_qcaps_output {
1767         __le16  error_code;
1768         __le16  req_type;
1769         __le16  seq_id;
1770         __le16  resp_len;
1771         __le32  qp_max_entries;
1772         __le16  qp_min_qp1_entries;
1773         __le16  qp_max_l2_entries;
1774         __le16  qp_entry_size;
1775         __le16  srq_max_l2_entries;
1776         __le32  srq_max_entries;
1777         __le16  srq_entry_size;
1778         __le16  cq_max_l2_entries;
1779         __le32  cq_max_entries;
1780         __le16  cq_entry_size;
1781         __le16  vnic_max_vnic_entries;
1782         __le16  vnic_max_ring_table_entries;
1783         __le16  vnic_entry_size;
1784         __le32  stat_max_entries;
1785         __le16  stat_entry_size;
1786         __le16  tqm_entry_size;
1787         __le32  tqm_min_entries_per_ring;
1788         __le32  tqm_max_entries_per_ring;
1789         __le32  mrav_max_entries;
1790         __le16  mrav_entry_size;
1791         __le16  tim_entry_size;
1792         __le32  tim_max_entries;
1793         __le16  mrav_num_entries_units;
1794         u8      tqm_entries_multiple;
1795         u8      valid;
1796 };
1797 
1798 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
1799 struct hwrm_func_backing_store_cfg_input {
1800         __le16  req_type;
1801         __le16  cmpl_ring;
1802         __le16  seq_id;
1803         __le16  target_id;
1804         __le64  resp_addr;
1805         __le32  flags;
1806         #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE               0x1UL
1807         #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT     0x2UL
1808         __le32  enables;
1809         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP            0x1UL
1810         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ           0x2UL
1811         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ            0x4UL
1812         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC          0x8UL
1813         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT          0x10UL
1814         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP        0x20UL
1815         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0     0x40UL
1816         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1     0x80UL
1817         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2     0x100UL
1818         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3     0x200UL
1819         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4     0x400UL
1820         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5     0x800UL
1821         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6     0x1000UL
1822         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7     0x2000UL
1823         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV          0x4000UL
1824         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM           0x8000UL
1825         u8      qpc_pg_size_qpc_lvl;
1826         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK      0xfUL
1827         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT       0
1828         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0       0x0UL
1829         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1       0x1UL
1830         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2       0x2UL
1831         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
1832         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK  0xf0UL
1833         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT   4
1834         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K   (0x0UL << 4)
1835         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K   (0x1UL << 4)
1836         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K  (0x2UL << 4)
1837         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M   (0x3UL << 4)
1838         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M   (0x4UL << 4)
1839         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G   (0x5UL << 4)
1840         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
1841         u8      srq_pg_size_srq_lvl;
1842         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK      0xfUL
1843         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT       0
1844         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0       0x0UL
1845         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1       0x1UL
1846         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2       0x2UL
1847         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
1848         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK  0xf0UL
1849         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT   4
1850         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K   (0x0UL << 4)
1851         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K   (0x1UL << 4)
1852         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K  (0x2UL << 4)
1853         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M   (0x3UL << 4)
1854         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M   (0x4UL << 4)
1855         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G   (0x5UL << 4)
1856         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
1857         u8      cq_pg_size_cq_lvl;
1858         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK      0xfUL
1859         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT       0
1860         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0       0x0UL
1861         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1       0x1UL
1862         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2       0x2UL
1863         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
1864         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK  0xf0UL
1865         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT   4
1866         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K   (0x0UL << 4)
1867         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K   (0x1UL << 4)
1868         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K  (0x2UL << 4)
1869         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M   (0x3UL << 4)
1870         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M   (0x4UL << 4)
1871         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G   (0x5UL << 4)
1872         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
1873         u8      vnic_pg_size_vnic_lvl;
1874         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK      0xfUL
1875         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT       0
1876         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0       0x0UL
1877         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1       0x1UL
1878         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2       0x2UL
1879         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
1880         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK  0xf0UL
1881         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT   4
1882         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K   (0x0UL << 4)
1883         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K   (0x1UL << 4)
1884         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K  (0x2UL << 4)
1885         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M   (0x3UL << 4)
1886         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M   (0x4UL << 4)
1887         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G   (0x5UL << 4)
1888         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
1889         u8      stat_pg_size_stat_lvl;
1890         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK      0xfUL
1891         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT       0
1892         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0       0x0UL
1893         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1       0x1UL
1894         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2       0x2UL
1895         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
1896         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK  0xf0UL
1897         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT   4
1898         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K   (0x0UL << 4)
1899         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K   (0x1UL << 4)
1900         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K  (0x2UL << 4)
1901         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M   (0x3UL << 4)
1902         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M   (0x4UL << 4)
1903         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G   (0x5UL << 4)
1904         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
1905         u8      tqm_sp_pg_size_tqm_sp_lvl;
1906         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK      0xfUL
1907         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT       0
1908         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0       0x0UL
1909         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1       0x1UL
1910         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2       0x2UL
1911         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
1912         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK  0xf0UL
1913         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT   4
1914         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K   (0x0UL << 4)
1915         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K   (0x1UL << 4)
1916         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K  (0x2UL << 4)
1917         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M   (0x3UL << 4)
1918         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M   (0x4UL << 4)
1919         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G   (0x5UL << 4)
1920         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
1921         u8      tqm_ring0_pg_size_tqm_ring0_lvl;
1922         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK      0xfUL
1923         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT       0
1924         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0       0x0UL
1925         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1       0x1UL
1926         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2       0x2UL
1927         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
1928         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK  0xf0UL
1929         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT   4
1930         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K   (0x0UL << 4)
1931         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K   (0x1UL << 4)
1932         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K  (0x2UL << 4)
1933         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M   (0x3UL << 4)
1934         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M   (0x4UL << 4)
1935         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G   (0x5UL << 4)
1936         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
1937         u8      tqm_ring1_pg_size_tqm_ring1_lvl;
1938         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK      0xfUL
1939         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT       0
1940         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0       0x0UL
1941         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1       0x1UL
1942         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2       0x2UL
1943         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
1944         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK  0xf0UL
1945         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT   4
1946         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K   (0x0UL << 4)
1947         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K   (0x1UL << 4)
1948         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K  (0x2UL << 4)
1949         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M   (0x3UL << 4)
1950         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M   (0x4UL << 4)
1951         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G   (0x5UL << 4)
1952         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
1953         u8      tqm_ring2_pg_size_tqm_ring2_lvl;
1954         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK      0xfUL
1955         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT       0
1956         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0       0x0UL
1957         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1       0x1UL
1958         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2       0x2UL
1959         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
1960         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK  0xf0UL
1961         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT   4
1962         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K   (0x0UL << 4)
1963         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K   (0x1UL << 4)
1964         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K  (0x2UL << 4)
1965         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M   (0x3UL << 4)
1966         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M   (0x4UL << 4)
1967         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G   (0x5UL << 4)
1968         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
1969         u8      tqm_ring3_pg_size_tqm_ring3_lvl;
1970         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK      0xfUL
1971         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT       0
1972         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0       0x0UL
1973         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1       0x1UL
1974         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2       0x2UL
1975         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
1976         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK  0xf0UL
1977         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT   4
1978         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K   (0x0UL << 4)
1979         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K   (0x1UL << 4)
1980         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K  (0x2UL << 4)
1981         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M   (0x3UL << 4)
1982         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M   (0x4UL << 4)
1983         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G   (0x5UL << 4)
1984         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
1985         u8      tqm_ring4_pg_size_tqm_ring4_lvl;
1986         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK      0xfUL
1987         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT       0
1988         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0       0x0UL
1989         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1       0x1UL
1990         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2       0x2UL
1991         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
1992         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK  0xf0UL
1993         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT   4
1994         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K   (0x0UL << 4)
1995         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K   (0x1UL << 4)
1996         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K  (0x2UL << 4)
1997         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M   (0x3UL << 4)
1998         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M   (0x4UL << 4)
1999         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G   (0x5UL << 4)
2000         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
2001         u8      tqm_ring5_pg_size_tqm_ring5_lvl;
2002         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK      0xfUL
2003         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT       0
2004         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0       0x0UL
2005         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1       0x1UL
2006         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2       0x2UL
2007         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
2008         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK  0xf0UL
2009         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT   4
2010         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K   (0x0UL << 4)
2011         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K   (0x1UL << 4)
2012         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K  (0x2UL << 4)
2013         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M   (0x3UL << 4)
2014         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M   (0x4UL << 4)
2015         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G   (0x5UL << 4)
2016         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
2017         u8      tqm_ring6_pg_size_tqm_ring6_lvl;
2018         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK      0xfUL
2019         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT       0
2020         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0       0x0UL
2021         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1       0x1UL
2022         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2       0x2UL
2023         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
2024         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK  0xf0UL
2025         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT   4
2026         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K   (0x0UL << 4)
2027         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K   (0x1UL << 4)
2028         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K  (0x2UL << 4)
2029         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M   (0x3UL << 4)
2030         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M   (0x4UL << 4)
2031         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G   (0x5UL << 4)
2032         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
2033         u8      tqm_ring7_pg_size_tqm_ring7_lvl;
2034         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK      0xfUL
2035         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT       0
2036         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0       0x0UL
2037         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1       0x1UL
2038         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2       0x2UL
2039         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
2040         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK  0xf0UL
2041         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT   4
2042         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K   (0x0UL << 4)
2043         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K   (0x1UL << 4)
2044         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K  (0x2UL << 4)
2045         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M   (0x3UL << 4)
2046         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M   (0x4UL << 4)
2047         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G   (0x5UL << 4)
2048         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
2049         u8      mrav_pg_size_mrav_lvl;
2050         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK      0xfUL
2051         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT       0
2052         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0       0x0UL
2053         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1       0x1UL
2054         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2       0x2UL
2055         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
2056         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK  0xf0UL
2057         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT   4
2058         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K   (0x0UL << 4)
2059         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K   (0x1UL << 4)
2060         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K  (0x2UL << 4)
2061         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M   (0x3UL << 4)
2062         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M   (0x4UL << 4)
2063         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G   (0x5UL << 4)
2064         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
2065         u8      tim_pg_size_tim_lvl;
2066         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK      0xfUL
2067         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT       0
2068         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0       0x0UL
2069         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1       0x1UL
2070         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2       0x2UL
2071         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
2072         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK  0xf0UL
2073         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT   4
2074         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K   (0x0UL << 4)
2075         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K   (0x1UL << 4)
2076         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K  (0x2UL << 4)
2077         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M   (0x3UL << 4)
2078         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M   (0x4UL << 4)
2079         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G   (0x5UL << 4)
2080         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
2081         __le64  qpc_page_dir;
2082         __le64  srq_page_dir;
2083         __le64  cq_page_dir;
2084         __le64  vnic_page_dir;
2085         __le64  stat_page_dir;
2086         __le64  tqm_sp_page_dir;
2087         __le64  tqm_ring0_page_dir;
2088         __le64  tqm_ring1_page_dir;
2089         __le64  tqm_ring2_page_dir;
2090         __le64  tqm_ring3_page_dir;
2091         __le64  tqm_ring4_page_dir;
2092         __le64  tqm_ring5_page_dir;
2093         __le64  tqm_ring6_page_dir;
2094         __le64  tqm_ring7_page_dir;
2095         __le64  mrav_page_dir;
2096         __le64  tim_page_dir;
2097         __le32  qp_num_entries;
2098         __le32  srq_num_entries;
2099         __le32  cq_num_entries;
2100         __le32  stat_num_entries;
2101         __le32  tqm_sp_num_entries;
2102         __le32  tqm_ring0_num_entries;
2103         __le32  tqm_ring1_num_entries;
2104         __le32  tqm_ring2_num_entries;
2105         __le32  tqm_ring3_num_entries;
2106         __le32  tqm_ring4_num_entries;
2107         __le32  tqm_ring5_num_entries;
2108         __le32  tqm_ring6_num_entries;
2109         __le32  tqm_ring7_num_entries;
2110         __le32  mrav_num_entries;
2111         __le32  tim_num_entries;
2112         __le16  qp_num_qp1_entries;
2113         __le16  qp_num_l2_entries;
2114         __le16  qp_entry_size;
2115         __le16  srq_num_l2_entries;
2116         __le16  srq_entry_size;
2117         __le16  cq_num_l2_entries;
2118         __le16  cq_entry_size;
2119         __le16  vnic_num_vnic_entries;
2120         __le16  vnic_num_ring_table_entries;
2121         __le16  vnic_entry_size;
2122         __le16  stat_entry_size;
2123         __le16  tqm_entry_size;
2124         __le16  mrav_entry_size;
2125         __le16  tim_entry_size;
2126 };
2127 
2128 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
2129 struct hwrm_func_backing_store_cfg_output {
2130         __le16  error_code;
2131         __le16  req_type;
2132         __le16  seq_id;
2133         __le16  resp_len;
2134         u8      unused_0[7];
2135         u8      valid;
2136 };
2137 
2138 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
2139 struct hwrm_error_recovery_qcfg_input {
2140         __le16  req_type;
2141         __le16  cmpl_ring;
2142         __le16  seq_id;
2143         __le16  target_id;
2144         __le64  resp_addr;
2145         u8      unused_0[8];
2146 };
2147 
2148 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
2149 struct hwrm_error_recovery_qcfg_output {
2150         __le16  error_code;
2151         __le16  req_type;
2152         __le16  seq_id;
2153         __le16  resp_len;
2154         __le32  flags;
2155         #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST       0x1UL
2156         #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU     0x2UL
2157         __le32  driver_polling_freq;
2158         __le32  master_func_wait_period;
2159         __le32  normal_func_wait_period;
2160         __le32  master_func_wait_period_after_reset;
2161         __le32  max_bailout_time_after_reset;
2162         __le32  fw_health_status_reg;
2163         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK    0x3UL
2164         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT     0
2165         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG  0x0UL
2166         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC       0x1UL
2167         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0      0x2UL
2168         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1      0x3UL
2169         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
2170         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK          0xfffffffcUL
2171         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT           2
2172         __le32  fw_heartbeat_reg;
2173         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK    0x3UL
2174         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT     0
2175         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG  0x0UL
2176         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC       0x1UL
2177         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0      0x2UL
2178         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1      0x3UL
2179         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
2180         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK          0xfffffffcUL
2181         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT           2
2182         __le32  fw_reset_cnt_reg;
2183         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK    0x3UL
2184         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT     0
2185         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG  0x0UL
2186         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC       0x1UL
2187         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0      0x2UL
2188         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1      0x3UL
2189         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
2190         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK          0xfffffffcUL
2191         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT           2
2192         __le32  reset_inprogress_reg;
2193         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK    0x3UL
2194         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT     0
2195         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG  0x0UL
2196         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC       0x1UL
2197         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0      0x2UL
2198         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1      0x3UL
2199         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
2200         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK          0xfffffffcUL
2201         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT           2
2202         __le32  reset_inprogress_reg_mask;
2203         u8      unused_0[3];
2204         u8      reg_array_cnt;
2205         __le32  reset_reg[16];
2206         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK    0x3UL
2207         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT     0
2208         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG  0x0UL
2209         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC       0x1UL
2210         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0      0x2UL
2211         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1      0x3UL
2212         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1
2213         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK          0xfffffffcUL
2214         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT           2
2215         __le32  reset_reg_val[16];
2216         u8      delay_after_reset[16];
2217         u8      unused_1[7];
2218         u8      valid;
2219 };
2220 
2221 /* hwrm_func_drv_if_change_input (size:192b/24B) */
2222 struct hwrm_func_drv_if_change_input {
2223         __le16  req_type;
2224         __le16  cmpl_ring;
2225         __le16  seq_id;
2226         __le16  target_id;
2227         __le64  resp_addr;
2228         __le32  flags;
2229         #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP     0x1UL
2230         __le32  unused;
2231 };
2232 
2233 /* hwrm_func_drv_if_change_output (size:128b/16B) */
2234 struct hwrm_func_drv_if_change_output {
2235         __le16  error_code;
2236         __le16  req_type;
2237         __le16  seq_id;
2238         __le16  resp_len;
2239         __le32  flags;
2240         #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE           0x1UL
2241         #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE     0x2UL
2242         u8      unused_0[3];
2243         u8      valid;
2244 };
2245 
2246 /* hwrm_port_phy_cfg_input (size:448b/56B) */
2247 struct hwrm_port_phy_cfg_input {
2248         __le16  req_type;
2249         __le16  cmpl_ring;
2250         __le16  seq_id;
2251         __le16  target_id;
2252         __le64  resp_addr;
2253         __le32  flags;
2254         #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY                0x1UL
2255         #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED               0x2UL
2256         #define PORT_PHY_CFG_REQ_FLAGS_FORCE                    0x4UL
2257         #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG          0x8UL
2258         #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE               0x10UL
2259         #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE              0x20UL
2260         #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE        0x40UL
2261         #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE       0x80UL
2262         #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE       0x100UL
2263         #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE      0x200UL
2264         #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE      0x400UL
2265         #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE     0x800UL
2266         #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE      0x1000UL
2267         #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE     0x2000UL
2268         #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN           0x4000UL
2269         __le32  enables;
2270         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE                0x1UL
2271         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX              0x2UL
2272         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE               0x4UL
2273         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED          0x8UL
2274         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK     0x10UL
2275         #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED                0x20UL
2276         #define PORT_PHY_CFG_REQ_ENABLES_LPBK                     0x40UL
2277         #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS              0x80UL
2278         #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE              0x100UL
2279         #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK      0x200UL
2280         #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER             0x400UL
2281         __le16  port_id;
2282         __le16  force_link_speed;
2283         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
2284         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB   0xaUL
2285         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB   0x14UL
2286         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
2287         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB  0x64UL
2288         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB  0xc8UL
2289         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB  0xfaUL
2290         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB  0x190UL
2291         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB  0x1f4UL
2292         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
2293         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL
2294         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB  0xffffUL
2295         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
2296         u8      auto_mode;
2297         #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE         0x0UL
2298         #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS   0x1UL
2299         #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED    0x2UL
2300         #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
2301         #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK   0x4UL
2302         #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST        PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
2303         u8      auto_duplex;
2304         #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
2305         #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
2306         #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
2307         #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
2308         u8      auto_pause;
2309         #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX                0x1UL
2310         #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX                0x2UL
2311         #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL
2312         u8      unused_0;
2313         __le16  auto_link_speed;
2314         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
2315         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB   0xaUL
2316         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB   0x14UL
2317         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
2318         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB  0x64UL
2319         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB  0xc8UL
2320         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB  0xfaUL
2321         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB  0x190UL
2322         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB  0x1f4UL
2323         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
2324         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL
2325         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB  0xffffUL
2326         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
2327         __le16  auto_link_speed_mask;
2328         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD     0x1UL
2329         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB       0x2UL
2330         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD       0x4UL
2331         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB         0x8UL
2332         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB         0x10UL
2333         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB       0x20UL
2334         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB        0x40UL
2335         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB        0x80UL
2336         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB        0x100UL
2337         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB        0x200UL
2338         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB        0x400UL
2339         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB       0x800UL
2340         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD      0x1000UL
2341         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB        0x2000UL
2342         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB       0x4000UL
2343         u8      wirespeed;
2344         #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
2345         #define PORT_PHY_CFG_REQ_WIRESPEED_ON  0x1UL
2346         #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
2347         u8      lpbk;
2348         #define PORT_PHY_CFG_REQ_LPBK_NONE     0x0UL
2349         #define PORT_PHY_CFG_REQ_LPBK_LOCAL    0x1UL
2350         #define PORT_PHY_CFG_REQ_LPBK_REMOTE   0x2UL
2351         #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
2352         #define PORT_PHY_CFG_REQ_LPBK_LAST    PORT_PHY_CFG_REQ_LPBK_EXTERNAL
2353         u8      force_pause;
2354         #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX     0x1UL
2355         #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX     0x2UL
2356         u8      unused_1;
2357         __le32  preemphasis;
2358         __le16  eee_link_speed_mask;
2359         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1     0x1UL
2360         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB     0x2UL
2361         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2     0x4UL
2362         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB       0x8UL
2363         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3     0x10UL
2364         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4     0x20UL
2365         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB      0x40UL
2366         u8      unused_2[2];
2367         __le32  tx_lpi_timer;
2368         #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
2369         #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
2370         __le32  unused_3;
2371 };
2372 
2373 /* hwrm_port_phy_cfg_output (size:128b/16B) */
2374 struct hwrm_port_phy_cfg_output {
2375         __le16  error_code;
2376         __le16  req_type;
2377         __le16  seq_id;
2378         __le16  resp_len;
2379         u8      unused_0[7];
2380         u8      valid;
2381 };
2382 
2383 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
2384 struct hwrm_port_phy_cfg_cmd_err {
2385         u8      code;
2386         #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN       0x0UL
2387         #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
2388         #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY         0x2UL
2389         #define PORT_PHY_CFG_CMD_ERR_CODE_LAST         PORT_PHY_CFG_CMD_ERR_CODE_RETRY
2390         u8      unused_0[7];
2391 };
2392 
2393 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
2394 struct hwrm_port_phy_qcfg_input {
2395         __le16  req_type;
2396         __le16  cmpl_ring;
2397         __le16  seq_id;
2398         __le16  target_id;
2399         __le64  resp_addr;
2400         __le16  port_id;
2401         u8      unused_0[6];
2402 };
2403 
2404 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
2405 struct hwrm_port_phy_qcfg_output {
2406         __le16  error_code;
2407         __le16  req_type;
2408         __le16  seq_id;
2409         __le16  resp_len;
2410         u8      link;
2411         #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
2412         #define PORT_PHY_QCFG_RESP_LINK_SIGNAL  0x1UL
2413         #define PORT_PHY_QCFG_RESP_LINK_LINK    0x2UL
2414         #define PORT_PHY_QCFG_RESP_LINK_LAST   PORT_PHY_QCFG_RESP_LINK_LINK
2415         u8      unused_0;
2416         __le16  link_speed;
2417         #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
2418         #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB   0xaUL
2419         #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB   0x14UL
2420         #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
2421         #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB  0x64UL
2422         #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB  0xc8UL
2423         #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB  0xfaUL
2424         #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB  0x190UL
2425         #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB  0x1f4UL
2426         #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
2427         #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
2428         #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB  0xffffUL
2429         #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
2430         u8      duplex_cfg;
2431         #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
2432         #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
2433         #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
2434         u8      pause;
2435         #define PORT_PHY_QCFG_RESP_PAUSE_TX     0x1UL
2436         #define PORT_PHY_QCFG_RESP_PAUSE_RX     0x2UL
2437         __le16  support_speeds;
2438         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD     0x1UL
2439         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB       0x2UL
2440         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD       0x4UL
2441         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB         0x8UL
2442         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB         0x10UL
2443         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB       0x20UL
2444         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB        0x40UL
2445         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB        0x80UL
2446         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB        0x100UL
2447         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB        0x200UL
2448         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB        0x400UL
2449         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB       0x800UL
2450         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD      0x1000UL
2451         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB        0x2000UL
2452         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB       0x4000UL
2453         __le16  force_link_speed;
2454         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
2455         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB   0xaUL
2456         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB   0x14UL
2457         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
2458         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB  0x64UL
2459         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB  0xc8UL
2460         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB  0xfaUL
2461         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB  0x190UL
2462         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB  0x1f4UL
2463         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
2464         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL
2465         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB  0xffffUL
2466         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
2467         u8      auto_mode;
2468         #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE         0x0UL
2469         #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS   0x1UL
2470         #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED    0x2UL
2471         #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
2472         #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK   0x4UL
2473         #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST        PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
2474         u8      auto_pause;
2475         #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX                0x1UL
2476         #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX                0x2UL
2477         #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL
2478         __le16  auto_link_speed;
2479         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
2480         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB   0xaUL
2481         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB   0x14UL
2482         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
2483         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB  0x64UL
2484         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB  0xc8UL
2485         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB  0xfaUL
2486         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB  0x190UL
2487         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB  0x1f4UL
2488         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
2489         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL
2490         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB  0xffffUL
2491         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
2492         __le16  auto_link_speed_mask;
2493         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD     0x1UL
2494         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB       0x2UL
2495         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD       0x4UL
2496         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB         0x8UL
2497         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB         0x10UL
2498         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB       0x20UL
2499         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB        0x40UL
2500         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB        0x80UL
2501         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB        0x100UL
2502         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB        0x200UL
2503         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB        0x400UL
2504         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB       0x800UL
2505         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD      0x1000UL
2506         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB        0x2000UL
2507         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB       0x4000UL
2508         u8      wirespeed;
2509         #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
2510         #define PORT_PHY_QCFG_RESP_WIRESPEED_ON  0x1UL
2511         #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
2512         u8      lpbk;
2513         #define PORT_PHY_QCFG_RESP_LPBK_NONE     0x0UL
2514         #define PORT_PHY_QCFG_RESP_LPBK_LOCAL    0x1UL
2515         #define PORT_PHY_QCFG_RESP_LPBK_REMOTE   0x2UL
2516         #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
2517         #define PORT_PHY_QCFG_RESP_LPBK_LAST    PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
2518         u8      force_pause;
2519         #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX     0x1UL
2520         #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX     0x2UL
2521         u8      module_status;
2522         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE          0x0UL
2523         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX     0x1UL
2524         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG    0x2UL
2525         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN       0x3UL
2526         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED   0x4UL
2527         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
2528         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST         PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
2529         __le32  preemphasis;
2530         u8      phy_maj;
2531         u8      phy_min;
2532         u8      phy_bld;
2533         u8      phy_type;
2534         #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN          0x0UL
2535         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR           0x1UL
2536         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4          0x2UL
2537         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR           0x3UL
2538         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR           0x4UL
2539         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2          0x5UL
2540         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX           0x6UL
2541         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR           0x7UL
2542         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET            0x8UL
2543         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE           0x9UL
2544         #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY      0xaUL
2545         #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L  0xbUL
2546         #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S  0xcUL
2547         #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N  0xdUL
2548         #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR       0xeUL
2549         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4     0xfUL
2550         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4     0x10UL
2551         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4     0x11UL
2552         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4     0x12UL
2553         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10    0x13UL
2554         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4      0x14UL
2555         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4      0x15UL
2556         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4      0x16UL
2557         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4      0x17UL
2558         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
2559         #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET         0x19UL
2560         #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX        0x1aUL
2561         #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX        0x1bUL
2562         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4     0x1cUL
2563         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4     0x1dUL
2564         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4     0x1eUL
2565         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4     0x1fUL
2566         #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST            PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4
2567         u8      media_type;
2568         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
2569         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP      0x1UL
2570         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC     0x2UL
2571         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE   0x3UL
2572         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST   PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
2573         u8      xcvr_pkg_type;
2574         #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
2575         #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
2576         #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST         PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
2577         u8      eee_config_phy_addr;
2578         #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK              0x1fUL
2579         #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT               0
2580         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK            0xe0UL
2581         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT             5
2582         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED      0x20UL
2583         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE       0x40UL
2584         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI       0x80UL
2585         u8      parallel_detect;
2586         #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT     0x1UL
2587         __le16  link_partner_adv_speeds;
2588         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD     0x1UL
2589         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB       0x2UL
2590         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD       0x4UL
2591         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB         0x8UL
2592         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB         0x10UL
2593         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB       0x20UL
2594         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB        0x40UL
2595         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB        0x80UL
2596         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB        0x100UL
2597         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB        0x200UL
2598         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB        0x400UL
2599         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB       0x800UL
2600         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD      0x1000UL
2601         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB        0x2000UL
2602         u8      link_partner_adv_auto_mode;
2603         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE         0x0UL
2604         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS   0x1UL
2605         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED    0x2UL
2606         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
2607         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK   0x4UL
2608         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST        PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
2609         u8      link_partner_adv_pause;
2610         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX     0x1UL
2611         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX     0x2UL
2612         __le16  adv_eee_link_speed_mask;
2613         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1     0x1UL
2614         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB     0x2UL
2615         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2     0x4UL
2616         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB       0x8UL
2617         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3     0x10UL
2618         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4     0x20UL
2619         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB      0x40UL
2620         __le16  link_partner_adv_eee_link_speed_mask;
2621         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1     0x1UL
2622         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB     0x2UL
2623         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2     0x4UL
2624         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB       0x8UL
2625         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3     0x10UL
2626         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4     0x20UL
2627         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB      0x40UL
2628         __le32  xcvr_identifier_type_tx_lpi_timer;
2629         #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK            0xffffffUL
2630         #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT             0
2631         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK    0xff000000UL
2632         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT     24
2633         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN   (0x0UL << 24)
2634         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP       (0x3UL << 24)
2635         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP      (0xcUL << 24)
2636         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS  (0xdUL << 24)
2637         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28    (0x11UL << 24)
2638         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST     PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
2639         __le16  fec_cfg;
2640         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED         0x1UL
2641         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED      0x2UL
2642         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED        0x4UL
2643         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED     0x8UL
2644         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED       0x10UL
2645         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED     0x20UL
2646         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED       0x40UL
2647         u8      duplex_state;
2648         #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
2649         #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
2650         #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
2651         u8      option_flags;
2652         #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT     0x1UL
2653         char    phy_vendor_name[16];
2654         char    phy_vendor_partnumber[16];
2655         u8      unused_2[7];
2656         u8      valid;
2657 };
2658 
2659 /* hwrm_port_mac_cfg_input (size:384b/48B) */
2660 struct hwrm_port_mac_cfg_input {
2661         __le16  req_type;
2662         __le16  cmpl_ring;
2663         __le16  seq_id;
2664         __le16  target_id;
2665         __le64  resp_addr;
2666         __le32  flags;
2667         #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK                    0x1UL
2668         #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE           0x2UL
2669         #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE         0x4UL
2670         #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE            0x8UL
2671         #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE      0x10UL
2672         #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE     0x20UL
2673         #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE      0x40UL
2674         #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE     0x80UL
2675         #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE                0x100UL
2676         #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE               0x200UL
2677         #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE          0x400UL
2678         #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE        0x800UL
2679         #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE           0x1000UL
2680         #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS            0x2000UL
2681         __le32  enables;
2682         #define PORT_MAC_CFG_REQ_ENABLES_IPG                            0x1UL
2683         #define PORT_MAC_CFG_REQ_ENABLES_LPBK                           0x2UL
2684         #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI           0x4UL
2685         #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI         0x10UL
2686         #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI               0x20UL
2687         #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE     0x40UL
2688         #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE     0x80UL
2689         #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG                  0x100UL
2690         #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB               0x200UL
2691         __le16  port_id;
2692         u8      ipg;
2693         u8      lpbk;
2694         #define PORT_MAC_CFG_REQ_LPBK_NONE   0x0UL
2695         #define PORT_MAC_CFG_REQ_LPBK_LOCAL  0x1UL
2696         #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
2697         #define PORT_MAC_CFG_REQ_LPBK_LAST  PORT_MAC_CFG_REQ_LPBK_REMOTE
2698         u8      vlan_pri2cos_map_pri;
2699         u8      reserved1;
2700         u8      tunnel_pri2cos_map_pri;
2701         u8      dscp2pri_map_pri;
2702         __le16  rx_ts_capture_ptp_msg_type;
2703         __le16  tx_ts_capture_ptp_msg_type;
2704         u8      cos_field_cfg;
2705         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1                     0x1UL
2706         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK         0x6UL
2707         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT          1
2708         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST      (0x0UL << 1)
2709         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER          (0x1UL << 1)
2710         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST      (0x2UL << 1)
2711         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED    (0x3UL << 1)
2712         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST          PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
2713         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK       0x18UL
2714         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT        3
2715         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST    (0x0UL << 3)
2716         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER        (0x1UL << 3)
2717         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST    (0x2UL << 3)
2718         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED  (0x3UL << 3)
2719         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST        PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
2720         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK          0xe0UL
2721         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT           5
2722         u8      unused_0[3];
2723         __s32   ptp_freq_adj_ppb;
2724         u8      unused_1[4];
2725 };
2726 
2727 /* hwrm_port_mac_cfg_output (size:128b/16B) */
2728 struct hwrm_port_mac_cfg_output {
2729         __le16  error_code;
2730         __le16  req_type;
2731         __le16  seq_id;
2732         __le16  resp_len;
2733         __le16  mru;
2734         __le16  mtu;
2735         u8      ipg;
2736         u8      lpbk;
2737         #define PORT_MAC_CFG_RESP_LPBK_NONE   0x0UL
2738         #define PORT_MAC_CFG_RESP_LPBK_LOCAL  0x1UL
2739         #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
2740         #define PORT_MAC_CFG_RESP_LPBK_LAST  PORT_MAC_CFG_RESP_LPBK_REMOTE
2741         u8      unused_0;
2742         u8      valid;
2743 };
2744 
2745 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
2746 struct hwrm_port_mac_ptp_qcfg_input {
2747         __le16  req_type;
2748         __le16  cmpl_ring;
2749         __le16  seq_id;
2750         __le16  target_id;
2751         __le64  resp_addr;
2752         __le16  port_id;
2753         u8      unused_0[6];
2754 };
2755 
2756 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
2757 struct hwrm_port_mac_ptp_qcfg_output {
2758         __le16  error_code;
2759         __le16  req_type;
2760         __le16  seq_id;
2761         __le16  resp_len;
2762         u8      flags;
2763         #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS      0x1UL
2764         #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS        0x2UL
2765         #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS     0x4UL
2766         u8      unused_0[3];
2767         __le32  rx_ts_reg_off_lower;
2768         __le32  rx_ts_reg_off_upper;
2769         __le32  rx_ts_reg_off_seq_id;
2770         __le32  rx_ts_reg_off_src_id_0;
2771         __le32  rx_ts_reg_off_src_id_1;
2772         __le32  rx_ts_reg_off_src_id_2;
2773         __le32  rx_ts_reg_off_domain_id;
2774         __le32  rx_ts_reg_off_fifo;
2775         __le32  rx_ts_reg_off_fifo_adv;
2776         __le32  rx_ts_reg_off_granularity;
2777         __le32  tx_ts_reg_off_lower;
2778         __le32  tx_ts_reg_off_upper;
2779         __le32  tx_ts_reg_off_seq_id;
2780         __le32  tx_ts_reg_off_fifo;
2781         __le32  tx_ts_reg_off_granularity;
2782         u8      unused_1[7];
2783         u8      valid;
2784 };
2785 
2786 /* tx_port_stats (size:3264b/408B) */
2787 struct tx_port_stats {
2788         __le64  tx_64b_frames;
2789         __le64  tx_65b_127b_frames;
2790         __le64  tx_128b_255b_frames;
2791         __le64  tx_256b_511b_frames;
2792         __le64  tx_512b_1023b_frames;
2793         __le64  tx_1024b_1518b_frames;
2794         __le64  tx_good_vlan_frames;
2795         __le64  tx_1519b_2047b_frames;
2796         __le64  tx_2048b_4095b_frames;
2797         __le64  tx_4096b_9216b_frames;
2798         __le64  tx_9217b_16383b_frames;
2799         __le64  tx_good_frames;
2800         __le64  tx_total_frames;
2801         __le64  tx_ucast_frames;
2802         __le64  tx_mcast_frames;
2803         __le64  tx_bcast_frames;
2804         __le64  tx_pause_frames;
2805         __le64  tx_pfc_frames;
2806         __le64  tx_jabber_frames;
2807         __le64  tx_fcs_err_frames;
2808         __le64  tx_control_frames;
2809         __le64  tx_oversz_frames;
2810         __le64  tx_single_dfrl_frames;
2811         __le64  tx_multi_dfrl_frames;
2812         __le64  tx_single_coll_frames;
2813         __le64  tx_multi_coll_frames;
2814         __le64  tx_late_coll_frames;
2815         __le64  tx_excessive_coll_frames;
2816         __le64  tx_frag_frames;
2817         __le64  tx_err;
2818         __le64  tx_tagged_frames;
2819         __le64  tx_dbl_tagged_frames;
2820         __le64  tx_runt_frames;
2821         __le64  tx_fifo_underruns;
2822         __le64  tx_pfc_ena_frames_pri0;
2823         __le64  tx_pfc_ena_frames_pri1;
2824         __le64  tx_pfc_ena_frames_pri2;
2825         __le64  tx_pfc_ena_frames_pri3;
2826         __le64  tx_pfc_ena_frames_pri4;
2827         __le64  tx_pfc_ena_frames_pri5;
2828         __le64  tx_pfc_ena_frames_pri6;
2829         __le64  tx_pfc_ena_frames_pri7;
2830         __le64  tx_eee_lpi_events;
2831         __le64  tx_eee_lpi_duration;
2832         __le64  tx_llfc_logical_msgs;
2833         __le64  tx_hcfc_msgs;
2834         __le64  tx_total_collisions;
2835         __le64  tx_bytes;
2836         __le64  tx_xthol_frames;
2837         __le64  tx_stat_discard;
2838         __le64  tx_stat_error;
2839 };
2840 
2841 /* rx_port_stats (size:4224b/528B) */
2842 struct rx_port_stats {
2843         __le64  rx_64b_frames;
2844         __le64  rx_65b_127b_frames;
2845         __le64  rx_128b_255b_frames;
2846         __le64  rx_256b_511b_frames;
2847         __le64  rx_512b_1023b_frames;
2848         __le64  rx_1024b_1518b_frames;
2849         __le64  rx_good_vlan_frames;
2850         __le64  rx_1519b_2047b_frames;
2851         __le64  rx_2048b_4095b_frames;
2852         __le64  rx_4096b_9216b_frames;
2853         __le64  rx_9217b_16383b_frames;
2854         __le64  rx_total_frames;
2855         __le64  rx_ucast_frames;
2856         __le64  rx_mcast_frames;
2857         __le64  rx_bcast_frames;
2858         __le64  rx_fcs_err_frames;
2859         __le64  rx_ctrl_frames;
2860         __le64  rx_pause_frames;
2861         __le64  rx_pfc_frames;
2862         __le64  rx_unsupported_opcode_frames;
2863         __le64  rx_unsupported_da_pausepfc_frames;
2864         __le64  rx_wrong_sa_frames;
2865         __le64  rx_align_err_frames;
2866         __le64  rx_oor_len_frames;
2867         __le64  rx_code_err_frames;
2868         __le64  rx_false_carrier_frames;
2869         __le64  rx_ovrsz_frames;
2870         __le64  rx_jbr_frames;
2871         __le64  rx_mtu_err_frames;
2872         __le64  rx_match_crc_frames;
2873         __le64  rx_promiscuous_frames;
2874         __le64  rx_tagged_frames;
2875         __le64  rx_double_tagged_frames;
2876         __le64  rx_trunc_frames;
2877         __le64  rx_good_frames;
2878         __le64  rx_pfc_xon2xoff_frames_pri0;
2879         __le64  rx_pfc_xon2xoff_frames_pri1;
2880         __le64  rx_pfc_xon2xoff_frames_pri2;
2881         __le64  rx_pfc_xon2xoff_frames_pri3;
2882         __le64  rx_pfc_xon2xoff_frames_pri4;
2883         __le64  rx_pfc_xon2xoff_frames_pri5;
2884         __le64  rx_pfc_xon2xoff_frames_pri6;
2885         __le64  rx_pfc_xon2xoff_frames_pri7;
2886         __le64  rx_pfc_ena_frames_pri0;
2887         __le64  rx_pfc_ena_frames_pri1;
2888         __le64  rx_pfc_ena_frames_pri2;
2889         __le64  rx_pfc_ena_frames_pri3;
2890         __le64  rx_pfc_ena_frames_pri4;
2891         __le64  rx_pfc_ena_frames_pri5;
2892         __le64  rx_pfc_ena_frames_pri6;
2893         __le64  rx_pfc_ena_frames_pri7;
2894         __le64  rx_sch_crc_err_frames;
2895         __le64  rx_undrsz_frames;
2896         __le64  rx_frag_frames;
2897         __le64  rx_eee_lpi_events;
2898         __le64  rx_eee_lpi_duration;
2899         __le64  rx_llfc_physical_msgs;
2900         __le64  rx_llfc_logical_msgs;
2901         __le64  rx_llfc_msgs_with_crc_err;
2902         __le64  rx_hcfc_msgs;
2903         __le64  rx_hcfc_msgs_with_crc_err;
2904         __le64  rx_bytes;
2905         __le64  rx_runt_bytes;
2906         __le64  rx_runt_frames;
2907         __le64  rx_stat_discard;
2908         __le64  rx_stat_err;
2909 };
2910 
2911 /* hwrm_port_qstats_input (size:320b/40B) */
2912 struct hwrm_port_qstats_input {
2913         __le16  req_type;
2914         __le16  cmpl_ring;
2915         __le16  seq_id;
2916         __le16  target_id;
2917         __le64  resp_addr;
2918         __le16  port_id;
2919         u8      unused_0[6];
2920         __le64  tx_stat_host_addr;
2921         __le64  rx_stat_host_addr;
2922 };
2923 
2924 /* hwrm_port_qstats_output (size:128b/16B) */
2925 struct hwrm_port_qstats_output {
2926         __le16  error_code;
2927         __le16  req_type;
2928         __le16  seq_id;
2929         __le16  resp_len;
2930         __le16  tx_stat_size;
2931         __le16  rx_stat_size;
2932         u8      unused_0[3];
2933         u8      valid;
2934 };
2935 
2936 /* tx_port_stats_ext (size:2048b/256B) */
2937 struct tx_port_stats_ext {
2938         __le64  tx_bytes_cos0;
2939         __le64  tx_bytes_cos1;
2940         __le64  tx_bytes_cos2;
2941         __le64  tx_bytes_cos3;
2942         __le64  tx_bytes_cos4;
2943         __le64  tx_bytes_cos5;
2944         __le64  tx_bytes_cos6;
2945         __le64  tx_bytes_cos7;
2946         __le64  tx_packets_cos0;
2947         __le64  tx_packets_cos1;
2948         __le64  tx_packets_cos2;
2949         __le64  tx_packets_cos3;
2950         __le64  tx_packets_cos4;
2951         __le64  tx_packets_cos5;
2952         __le64  tx_packets_cos6;
2953         __le64  tx_packets_cos7;
2954         __le64  pfc_pri0_tx_duration_us;
2955         __le64  pfc_pri0_tx_transitions;
2956         __le64  pfc_pri1_tx_duration_us;
2957         __le64  pfc_pri1_tx_transitions;
2958         __le64  pfc_pri2_tx_duration_us;
2959         __le64  pfc_pri2_tx_transitions;
2960         __le64  pfc_pri3_tx_duration_us;
2961         __le64  pfc_pri3_tx_transitions;
2962         __le64  pfc_pri4_tx_duration_us;
2963         __le64  pfc_pri4_tx_transitions;
2964         __le64  pfc_pri5_tx_duration_us;
2965         __le64  pfc_pri5_tx_transitions;
2966         __le64  pfc_pri6_tx_duration_us;
2967         __le64  pfc_pri6_tx_transitions;
2968         __le64  pfc_pri7_tx_duration_us;
2969         __le64  pfc_pri7_tx_transitions;
2970 };
2971 
2972 /* rx_port_stats_ext (size:3648b/456B) */
2973 struct rx_port_stats_ext {
2974         __le64  link_down_events;
2975         __le64  continuous_pause_events;
2976         __le64  resume_pause_events;
2977         __le64  continuous_roce_pause_events;
2978         __le64  resume_roce_pause_events;
2979         __le64  rx_bytes_cos0;
2980         __le64  rx_bytes_cos1;
2981         __le64  rx_bytes_cos2;
2982         __le64  rx_bytes_cos3;
2983         __le64  rx_bytes_cos4;
2984         __le64  rx_bytes_cos5;
2985         __le64  rx_bytes_cos6;
2986         __le64  rx_bytes_cos7;
2987         __le64  rx_packets_cos0;
2988         __le64  rx_packets_cos1;
2989         __le64  rx_packets_cos2;
2990         __le64  rx_packets_cos3;
2991         __le64  rx_packets_cos4;
2992         __le64  rx_packets_cos5;
2993         __le64  rx_packets_cos6;
2994         __le64  rx_packets_cos7;
2995         __le64  pfc_pri0_rx_duration_us;
2996         __le64  pfc_pri0_rx_transitions;
2997         __le64  pfc_pri1_rx_duration_us;
2998         __le64  pfc_pri1_rx_transitions;
2999         __le64  pfc_pri2_rx_duration_us;
3000         __le64  pfc_pri2_rx_transitions;
3001         __le64  pfc_pri3_rx_duration_us;
3002         __le64  pfc_pri3_rx_transitions;
3003         __le64  pfc_pri4_rx_duration_us;
3004         __le64  pfc_pri4_rx_transitions;
3005         __le64  pfc_pri5_rx_duration_us;
3006         __le64  pfc_pri5_rx_transitions;
3007         __le64  pfc_pri6_rx_duration_us;
3008         __le64  pfc_pri6_rx_transitions;
3009         __le64  pfc_pri7_rx_duration_us;
3010         __le64  pfc_pri7_rx_transitions;
3011         __le64  rx_bits;
3012         __le64  rx_buffer_passed_threshold;
3013         __le64  rx_pcs_symbol_err;
3014         __le64  rx_corrected_bits;
3015         __le64  rx_discard_bytes_cos0;
3016         __le64  rx_discard_bytes_cos1;
3017         __le64  rx_discard_bytes_cos2;
3018         __le64  rx_discard_bytes_cos3;
3019         __le64  rx_discard_bytes_cos4;
3020         __le64  rx_discard_bytes_cos5;
3021         __le64  rx_discard_bytes_cos6;
3022         __le64  rx_discard_bytes_cos7;
3023         __le64  rx_discard_packets_cos0;
3024         __le64  rx_discard_packets_cos1;
3025         __le64  rx_discard_packets_cos2;
3026         __le64  rx_discard_packets_cos3;
3027         __le64  rx_discard_packets_cos4;
3028         __le64  rx_discard_packets_cos5;
3029         __le64  rx_discard_packets_cos6;
3030         __le64  rx_discard_packets_cos7;
3031 };
3032 
3033 /* hwrm_port_qstats_ext_input (size:320b/40B) */
3034 struct hwrm_port_qstats_ext_input {
3035         __le16  req_type;
3036         __le16  cmpl_ring;
3037         __le16  seq_id;
3038         __le16  target_id;
3039         __le64  resp_addr;
3040         __le16  port_id;
3041         __le16  tx_stat_size;
3042         __le16  rx_stat_size;
3043         u8      unused_0[2];
3044         __le64  tx_stat_host_addr;
3045         __le64  rx_stat_host_addr;
3046 };
3047 
3048 /* hwrm_port_qstats_ext_output (size:128b/16B) */
3049 struct hwrm_port_qstats_ext_output {
3050         __le16  error_code;
3051         __le16  req_type;
3052         __le16  seq_id;
3053         __le16  resp_len;
3054         __le16  tx_stat_size;
3055         __le16  rx_stat_size;
3056         __le16  total_active_cos_queues;
3057         u8      flags;
3058         #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED     0x1UL
3059         u8      valid;
3060 };
3061 
3062 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
3063 struct hwrm_port_lpbk_qstats_input {
3064         __le16  req_type;
3065         __le16  cmpl_ring;
3066         __le16  seq_id;
3067         __le16  target_id;
3068         __le64  resp_addr;
3069 };
3070 
3071 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
3072 struct hwrm_port_lpbk_qstats_output {
3073         __le16  error_code;
3074         __le16  req_type;
3075         __le16  seq_id;
3076         __le16  resp_len;
3077         __le64  lpbk_ucast_frames;
3078         __le64  lpbk_mcast_frames;
3079         __le64  lpbk_bcast_frames;
3080         __le64  lpbk_ucast_bytes;
3081         __le64  lpbk_mcast_bytes;
3082         __le64  lpbk_bcast_bytes;
3083         __le64  tx_stat_discard;
3084         __le64  tx_stat_error;
3085         __le64  rx_stat_discard;
3086         __le64  rx_stat_error;
3087         u8      unused_0[7];
3088         u8      valid;
3089 };
3090 
3091 /* hwrm_port_clr_stats_input (size:192b/24B) */
3092 struct hwrm_port_clr_stats_input {
3093         __le16  req_type;
3094         __le16  cmpl_ring;
3095         __le16  seq_id;
3096         __le16  target_id;
3097         __le64  resp_addr;
3098         __le16  port_id;
3099         u8      flags;
3100         #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS     0x1UL
3101         u8      unused_0[5];
3102 };
3103 
3104 /* hwrm_port_clr_stats_output (size:128b/16B) */
3105 struct hwrm_port_clr_stats_output {
3106         __le16  error_code;
3107         __le16  req_type;
3108         __le16  seq_id;
3109         __le16  resp_len;
3110         u8      unused_0[7];
3111         u8      valid;
3112 };
3113 
3114 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
3115 struct hwrm_port_lpbk_clr_stats_input {
3116         __le16  req_type;
3117         __le16  cmpl_ring;
3118         __le16  seq_id;
3119         __le16  target_id;
3120         __le64  resp_addr;
3121 };
3122 
3123 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
3124 struct hwrm_port_lpbk_clr_stats_output {
3125         __le16  error_code;
3126         __le16  req_type;
3127         __le16  seq_id;
3128         __le16  resp_len;
3129         u8      unused_0[7];
3130         u8      valid;
3131 };
3132 
3133 /* hwrm_port_ts_query_input (size:192b/24B) */
3134 struct hwrm_port_ts_query_input {
3135         __le16  req_type;
3136         __le16  cmpl_ring;
3137         __le16  seq_id;
3138         __le16  target_id;
3139         __le64  resp_addr;
3140         __le32  flags;
3141         #define PORT_TS_QUERY_REQ_FLAGS_PATH             0x1UL
3142         #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX            0x0UL
3143         #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX            0x1UL
3144         #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST         PORT_TS_QUERY_REQ_FLAGS_PATH_RX
3145         #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME     0x2UL
3146         __le16  port_id;
3147         u8      unused_0[2];
3148 };
3149 
3150 /* hwrm_port_ts_query_output (size:192b/24B) */
3151 struct hwrm_port_ts_query_output {
3152         __le16  error_code;
3153         __le16  req_type;
3154         __le16  seq_id;
3155         __le16  resp_len;
3156         __le64  ptp_msg_ts;
3157         __le16  ptp_msg_seqid;
3158         u8      unused_0[5];
3159         u8      valid;
3160 };
3161 
3162 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
3163 struct hwrm_port_phy_qcaps_input {
3164         __le16  req_type;
3165         __le16  cmpl_ring;
3166         __le16  seq_id;
3167         __le16  target_id;
3168         __le64  resp_addr;
3169         __le16  port_id;
3170         u8      unused_0[6];
3171 };
3172 
3173 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
3174 struct hwrm_port_phy_qcaps_output {
3175         __le16  error_code;
3176         __le16  req_type;
3177         __le16  seq_id;
3178         __le16  resp_len;
3179         u8      flags;
3180         #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED               0x1UL
3181         #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED     0x2UL
3182         #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK                  0xfcUL
3183         #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT                   2
3184         u8      port_cnt;
3185         #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
3186         #define PORT_PHY_QCAPS_RESP_PORT_CNT_1       0x1UL
3187         #define PORT_PHY_QCAPS_RESP_PORT_CNT_2       0x2UL
3188         #define PORT_PHY_QCAPS_RESP_PORT_CNT_3       0x3UL
3189         #define PORT_PHY_QCAPS_RESP_PORT_CNT_4       0x4UL
3190         #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST   PORT_PHY_QCAPS_RESP_PORT_CNT_4
3191         __le16  supported_speeds_force_mode;
3192         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD     0x1UL
3193         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB       0x2UL
3194         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD       0x4UL
3195         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB         0x8UL
3196         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB         0x10UL
3197         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB       0x20UL
3198         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB        0x40UL
3199         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB        0x80UL
3200         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB        0x100UL
3201         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB        0x200UL
3202         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB        0x400UL
3203         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB       0x800UL
3204         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD      0x1000UL
3205         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB        0x2000UL
3206         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_200GB       0x4000UL
3207         __le16  supported_speeds_auto_mode;
3208         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD     0x1UL
3209         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB       0x2UL
3210         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD       0x4UL
3211         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB         0x8UL
3212         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB         0x10UL
3213         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB       0x20UL
3214         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB        0x40UL
3215         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB        0x80UL
3216         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB        0x100UL
3217         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB        0x200UL
3218         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB        0x400UL
3219         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB       0x800UL
3220         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD      0x1000UL
3221         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB        0x2000UL
3222         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_200GB       0x4000UL
3223         __le16  supported_speeds_eee_mode;
3224         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1     0x1UL
3225         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB     0x2UL
3226         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2     0x4UL
3227         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB       0x8UL
3228         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3     0x10UL
3229         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4     0x20UL
3230         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB      0x40UL
3231         __le32  tx_lpi_timer_low;
3232         #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
3233         #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
3234         #define PORT_PHY_QCAPS_RESP_RSVD2_MASK           0xff000000UL
3235         #define PORT_PHY_QCAPS_RESP_RSVD2_SFT            24
3236         __le32  valid_tx_lpi_timer_high;
3237         #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
3238         #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
3239         #define PORT_PHY_QCAPS_RESP_VALID_MASK            0xff000000UL
3240         #define PORT_PHY_QCAPS_RESP_VALID_SFT             24
3241 };
3242 
3243 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
3244 struct hwrm_port_phy_i2c_read_input {
3245         __le16  req_type;
3246         __le16  cmpl_ring;
3247         __le16  seq_id;
3248         __le16  target_id;
3249         __le64  resp_addr;
3250         __le32  flags;
3251         __le32  enables;
3252         #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET     0x1UL
3253         __le16  port_id;
3254         u8      i2c_slave_addr;
3255         u8      unused_0;
3256         __le16  page_number;
3257         __le16  page_offset;
3258         u8      data_length;
3259         u8      unused_1[7];
3260 };
3261 
3262 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
3263 struct hwrm_port_phy_i2c_read_output {
3264         __le16  error_code;
3265         __le16  req_type;
3266         __le16  seq_id;
3267         __le16  resp_len;
3268         __le32  data[16];
3269         u8      unused_0[7];
3270         u8      valid;
3271 };
3272 
3273 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
3274 struct hwrm_port_phy_mdio_write_input {
3275         __le16  req_type;
3276         __le16  cmpl_ring;
3277         __le16  seq_id;
3278         __le16  target_id;
3279         __le64  resp_addr;
3280         __le32  unused_0[2];
3281         __le16  port_id;
3282         u8      phy_addr;
3283         u8      dev_addr;
3284         __le16  reg_addr;
3285         __le16  reg_data;
3286         u8      cl45_mdio;
3287         u8      unused_1[7];
3288 };
3289 
3290 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
3291 struct hwrm_port_phy_mdio_write_output {
3292         __le16  error_code;
3293         __le16  req_type;
3294         __le16  seq_id;
3295         __le16  resp_len;
3296         u8      unused_0[7];
3297         u8      valid;
3298 };
3299 
3300 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
3301 struct hwrm_port_phy_mdio_read_input {
3302         __le16  req_type;
3303         __le16  cmpl_ring;
3304         __le16  seq_id;
3305         __le16  target_id;
3306         __le64  resp_addr;
3307         __le32  unused_0[2];
3308         __le16  port_id;
3309         u8      phy_addr;
3310         u8      dev_addr;
3311         __le16  reg_addr;
3312         u8      cl45_mdio;
3313         u8      unused_1;
3314 };
3315 
3316 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
3317 struct hwrm_port_phy_mdio_read_output {
3318         __le16  error_code;
3319         __le16  req_type;
3320         __le16  seq_id;
3321         __le16  resp_len;
3322         __le16  reg_data;
3323         u8      unused_0[5];
3324         u8      valid;
3325 };
3326 
3327 /* hwrm_port_led_cfg_input (size:512b/64B) */
3328 struct hwrm_port_led_cfg_input {
3329         __le16  req_type;
3330         __le16  cmpl_ring;
3331         __le16  seq_id;
3332         __le16  target_id;
3333         __le64  resp_addr;
3334         __le32  enables;
3335         #define PORT_LED_CFG_REQ_ENABLES_LED0_ID            0x1UL
3336         #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE         0x2UL
3337         #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR         0x4UL
3338         #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON      0x8UL
3339         #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF     0x10UL
3340         #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID      0x20UL
3341         #define PORT_LED_CFG_REQ_ENABLES_LED1_ID            0x40UL
3342         #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE         0x80UL
3343         #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR         0x100UL
3344         #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON      0x200UL
3345         #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF     0x400UL
3346         #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID      0x800UL
3347         #define PORT_LED_CFG_REQ_ENABLES_LED2_ID            0x1000UL
3348         #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE         0x2000UL
3349         #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR         0x4000UL
3350         #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON      0x8000UL
3351         #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF     0x10000UL
3352         #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID      0x20000UL
3353         #define PORT_LED_CFG_REQ_ENABLES_LED3_ID            0x40000UL
3354         #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE         0x80000UL
3355         #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR         0x100000UL
3356         #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON      0x200000UL
3357         #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF     0x400000UL
3358         #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID      0x800000UL
3359         __le16  port_id;
3360         u8      num_leds;
3361         u8      rsvd;
3362         u8      led0_id;
3363         u8      led0_state;
3364         #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT  0x0UL
3365         #define PORT_LED_CFG_REQ_LED0_STATE_OFF      0x1UL
3366         #define PORT_LED_CFG_REQ_LED0_STATE_ON       0x2UL
3367         #define PORT_LED_CFG_REQ_LED0_STATE_BLINK    0x3UL
3368         #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
3369         #define PORT_LED_CFG_REQ_LED0_STATE_LAST    PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
3370         u8      led0_color;
3371         #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT    0x0UL
3372         #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER      0x1UL
3373         #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN      0x2UL
3374         #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
3375         #define PORT_LED_CFG_REQ_LED0_COLOR_LAST      PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
3376         u8      unused_0;
3377         __le16  led0_blink_on;
3378         __le16  led0_blink_off;
3379         u8      led0_group_id;
3380         u8      rsvd0;
3381         u8      led1_id;
3382         u8      led1_state;
3383         #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT  0x0UL
3384         #define PORT_LED_CFG_REQ_LED1_STATE_OFF      0x1UL
3385         #define PORT_LED_CFG_REQ_LED1_STATE_ON       0x2UL
3386         #define PORT_LED_CFG_REQ_LED1_STATE_BLINK    0x3UL
3387         #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
3388         #define PORT_LED_CFG_REQ_LED1_STATE_LAST    PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
3389         u8      led1_color;
3390         #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT    0x0UL
3391         #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER      0x1UL
3392         #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN      0x2UL
3393         #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
3394         #define PORT_LED_CFG_REQ_LED1_COLOR_LAST      PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
3395         u8      unused_1;
3396         __le16  led1_blink_on;
3397         __le16  led1_blink_off;
3398         u8      led1_group_id;
3399         u8      rsvd1;
3400         u8      led2_id;
3401         u8      led2_state;
3402         #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT  0x0UL
3403         #define PORT_LED_CFG_REQ_LED2_STATE_OFF      0x1UL
3404         #define PORT_LED_CFG_REQ_LED2_STATE_ON       0x2UL
3405         #define PORT_LED_CFG_REQ_LED2_STATE_BLINK    0x3UL
3406         #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
3407         #define PORT_LED_CFG_REQ_LED2_STATE_LAST    PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
3408         u8      led2_color;
3409         #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT    0x0UL
3410         #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER      0x1UL
3411         #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN      0x2UL
3412         #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
3413         #define PORT_LED_CFG_REQ_LED2_COLOR_LAST      PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
3414         u8      unused_2;
3415         __le16  led2_blink_on;
3416         __le16  led2_blink_off;
3417         u8      led2_group_id;
3418         u8      rsvd2;
3419         u8      led3_id;
3420         u8      led3_state;
3421         #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT  0x0UL
3422         #define PORT_LED_CFG_REQ_LED3_STATE_OFF      0x1UL
3423         #define PORT_LED_CFG_REQ_LED3_STATE_ON       0x2UL
3424         #define PORT_LED_CFG_REQ_LED3_STATE_BLINK    0x3UL
3425         #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
3426         #define PORT_LED_CFG_REQ_LED3_STATE_LAST    PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
3427         u8      led3_color;
3428         #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT    0x0UL
3429         #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER      0x1UL
3430         #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN      0x2UL
3431         #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
3432         #define PORT_LED_CFG_REQ_LED3_COLOR_LAST      PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
3433         u8      unused_3;
3434         __le16  led3_blink_on;
3435         __le16  led3_blink_off;
3436         u8      led3_group_id;
3437         u8      rsvd3;
3438 };
3439 
3440 /* hwrm_port_led_cfg_output (size:128b/16B) */
3441 struct hwrm_port_led_cfg_output {
3442         __le16  error_code;
3443         __le16  req_type;
3444         __le16  seq_id;
3445         __le16  resp_len;
3446         u8      unused_0[7];
3447         u8      valid;
3448 };
3449 
3450 /* hwrm_port_led_qcfg_input (size:192b/24B) */
3451 struct hwrm_port_led_qcfg_input {
3452         __le16  req_type;
3453         __le16  cmpl_ring;
3454         __le16  seq_id;
3455         __le16  target_id;
3456         __le64  resp_addr;
3457         __le16  port_id;
3458         u8      unused_0[6];
3459 };
3460 
3461 /* hwrm_port_led_qcfg_output (size:448b/56B) */
3462 struct hwrm_port_led_qcfg_output {
3463         __le16  error_code;
3464         __le16  req_type;
3465         __le16  seq_id;
3466         __le16  resp_len;
3467         u8      num_leds;
3468         u8      led0_id;
3469         u8      led0_type;
3470         #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED    0x0UL
3471         #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL
3472         #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID  0xffUL
3473         #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST    PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
3474         u8      led0_state;
3475         #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT  0x0UL
3476         #define PORT_LED_QCFG_RESP_LED0_STATE_OFF      0x1UL
3477         #define PORT_LED_QCFG_RESP_LED0_STATE_ON       0x2UL
3478         #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK    0x3UL
3479         #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL
3480         #define PORT_LED_QCFG_RESP_LED0_STATE_LAST    PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
3481         u8      led0_color;
3482         #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT    0x0UL
3483         #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER      0x1UL
3484         #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN      0x2UL
3485         #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL
3486         #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST      PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
3487         u8      unused_0;
3488         __le16  led0_blink_on;
3489         __le16  led0_blink_off;
3490         u8      led0_group_id;
3491         u8      led1_id;
3492         u8      led1_type;
3493         #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED    0x0UL
3494         #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL
3495         #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID  0xffUL
3496         #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST    PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
3497         u8      led1_state;
3498         #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT  0x0UL
3499         #define PORT_LED_QCFG_RESP_LED1_STATE_OFF      0x1UL
3500         #define PORT_LED_QCFG_RESP_LED1_STATE_ON       0x2UL
3501         #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK    0x3UL
3502         #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL
3503         #define PORT_LED_QCFG_RESP_LED1_STATE_LAST    PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
3504         u8      led1_color;
3505         #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT    0x0UL
3506         #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER      0x1UL
3507         #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN      0x2UL
3508         #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL
3509         #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST      PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
3510         u8      unused_1;
3511         __le16  led1_blink_on;
3512         __le16  led1_blink_off;
3513         u8      led1_group_id;
3514         u8      led2_id;
3515         u8      led2_type;
3516         #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED    0x0UL
3517         #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL
3518         #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID  0xffUL
3519         #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST    PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
3520         u8      led2_state;
3521         #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT  0x0UL
3522         #define PORT_LED_QCFG_RESP_LED2_STATE_OFF      0x1UL
3523         #define PORT_LED_QCFG_RESP_LED2_STATE_ON       0x2UL
3524         #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK    0x3UL
3525         #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL
3526         #define PORT_LED_QCFG_RESP_LED2_STATE_LAST    PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
3527         u8      led2_color;
3528         #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT    0x0UL
3529         #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER      0x1UL
3530         #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN      0x2UL
3531         #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL
3532         #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST      PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
3533         u8      unused_2;
3534         __le16  led2_blink_on;
3535         __le16  led2_blink_off;
3536         u8      led2_group_id;
3537         u8      led3_id;
3538         u8      led3_type;
3539         #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED    0x0UL
3540         #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL
3541         #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID  0xffUL
3542         #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST    PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
3543         u8      led3_state;
3544         #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT  0x0UL
3545         #define PORT_LED_QCFG_RESP_LED3_STATE_OFF      0x1UL
3546         #define PORT_LED_QCFG_RESP_LED3_STATE_ON       0x2UL
3547         #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK    0x3UL
3548         #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL
3549         #define PORT_LED_QCFG_RESP_LED3_STATE_LAST    PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
3550         u8      led3_color;
3551         #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT    0x0UL
3552         #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER      0x1UL
3553         #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN      0x2UL
3554         #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL
3555         #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST      PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
3556         u8      unused_3;
3557         __le16  led3_blink_on;
3558         __le16  led3_blink_off;
3559         u8      led3_group_id;
3560         u8      unused_4[6];
3561         u8      valid;
3562 };
3563 
3564 /* hwrm_port_led_qcaps_input (size:192b/24B) */
3565 struct hwrm_port_led_qcaps_input {
3566         __le16  req_type;
3567         __le16  cmpl_ring;
3568         __le16  seq_id;
3569         __le16  target_id;
3570         __le64  resp_addr;
3571         __le16  port_id;
3572         u8      unused_0[6];
3573 };
3574 
3575 /* hwrm_port_led_qcaps_output (size:384b/48B) */
3576 struct hwrm_port_led_qcaps_output {
3577         __le16  error_code;
3578         __le16  req_type;
3579         __le16  seq_id;
3580         __le16  resp_len;
3581         u8      num_leds;
3582         u8      unused[3];
3583         u8      led0_id;
3584         u8      led0_type;
3585         #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED    0x0UL
3586         #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
3587         #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID  0xffUL
3588         #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST    PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
3589         u8      led0_group_id;
3590         u8      unused_0;
3591         __le16  led0_state_caps;
3592         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED                 0x1UL
3593         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED           0x2UL
3594         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED            0x4UL
3595         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED         0x8UL
3596         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL
3597         __le16  led0_color_caps;
3598         #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD                0x1UL
3599         #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED     0x2UL
3600         #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED     0x4UL
3601         u8      led1_id;
3602         u8      led1_type;
3603         #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED    0x0UL
3604         #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
3605         #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID  0xffUL
3606         #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST    PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
3607         u8      led1_group_id;
3608         u8      unused_1;
3609         __le16  led1_state_caps;
3610         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED                 0x1UL
3611         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED           0x2UL
3612         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED            0x4UL
3613         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED         0x8UL
3614         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL
3615         __le16  led1_color_caps;
3616         #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD                0x1UL
3617         #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED     0x2UL
3618         #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED     0x4UL
3619         u8      led2_id;
3620         u8      led2_type;
3621         #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED    0x0UL
3622         #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
3623         #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID  0xffUL
3624         #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST    PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
3625         u8      led2_group_id;
3626         u8      unused_2;
3627         __le16  led2_state_caps;
3628         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED                 0x1UL
3629         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED           0x2UL
3630         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED            0x4UL
3631         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED         0x8UL
3632         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL
3633         __le16  led2_color_caps;
3634         #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD                0x1UL
3635         #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED     0x2UL
3636         #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED     0x4UL
3637         u8      led3_id;
3638         u8      led3_type;
3639         #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED    0x0UL
3640         #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
3641         #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID  0xffUL
3642         #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST    PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
3643         u8      led3_group_id;
3644         u8      unused_3;
3645         __le16  led3_state_caps;
3646         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED                 0x1UL
3647         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED           0x2UL
3648         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED            0x4UL
3649         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED         0x8UL
3650         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL
3651         __le16  led3_color_caps;
3652         #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD                0x1UL
3653         #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED     0x2UL
3654         #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED     0x4UL
3655         u8      unused_4[3];
3656         u8      valid;
3657 };
3658 
3659 /* hwrm_queue_qportcfg_input (size:192b/24B) */
3660 struct hwrm_queue_qportcfg_input {
3661         __le16  req_type;
3662         __le16  cmpl_ring;
3663         __le16  seq_id;
3664         __le16  target_id;
3665         __le64  resp_addr;
3666         __le32  flags;
3667         #define QUEUE_QPORTCFG_REQ_FLAGS_PATH     0x1UL
3668         #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX    0x0UL
3669         #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX    0x1UL
3670         #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
3671         __le16  port_id;
3672         u8      drv_qmap_cap;
3673         #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL
3674         #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED  0x1UL
3675         #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST    QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED
3676         u8      unused_0;
3677 };
3678 
3679 /* hwrm_queue_qportcfg_output (size:256b/32B) */
3680 struct hwrm_queue_qportcfg_output {
3681         __le16  error_code;
3682         __le16  req_type;
3683         __le16  seq_id;
3684         __le16  resp_len;
3685         u8      max_configurable_queues;
3686         u8      max_configurable_lossless_queues;
3687         u8      queue_cfg_allowed;
3688         u8      queue_cfg_info;
3689         #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG     0x1UL
3690         u8      queue_pfcenable_cfg_allowed;
3691         u8      queue_pri2cos_cfg_allowed;
3692         u8      queue_cos2bw_cfg_allowed;
3693         u8      queue_id0;
3694         u8      queue_id0_service_profile;
3695         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY          0x0UL
3696         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS       0x1UL
3697         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
3698         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3699         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
3700         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN        0xffUL
3701         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
3702         u8      queue_id1;
3703         u8      queue_id1_service_profile;
3704         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY          0x0UL
3705         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS       0x1UL
3706         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
3707         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3708         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
3709         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN        0xffUL
3710         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
3711         u8      queue_id2;
3712         u8      queue_id2_service_profile;
3713         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY          0x0UL
3714         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS       0x1UL
3715         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
3716         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3717         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
3718         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN        0xffUL
3719         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
3720         u8      queue_id3;
3721         u8      queue_id3_service_profile;
3722         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY          0x0UL
3723         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS       0x1UL
3724         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
3725         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3726         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
3727         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN        0xffUL
3728         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
3729         u8      queue_id4;
3730         u8      queue_id4_service_profile;
3731         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY          0x0UL
3732         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS       0x1UL
3733         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
3734         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3735         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
3736         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN        0xffUL
3737         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
3738         u8      queue_id5;
3739         u8      queue_id5_service_profile;
3740         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY          0x0UL
3741         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS       0x1UL
3742         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
3743         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3744         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
3745         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN        0xffUL
3746         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
3747         u8      queue_id6;
3748         u8      queue_id6_service_profile;
3749         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY          0x0UL
3750         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS       0x1UL
3751         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
3752         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3753         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
3754         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN        0xffUL
3755         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
3756         u8      queue_id7;
3757         u8      queue_id7_service_profile;
3758         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY          0x0UL
3759         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS       0x1UL
3760         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
3761         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3762         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
3763         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN        0xffUL
3764         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
3765         u8      valid;
3766 };
3767 
3768 /* hwrm_queue_cfg_input (size:320b/40B) */
3769 struct hwrm_queue_cfg_input {
3770         __le16  req_type;
3771         __le16  cmpl_ring;
3772         __le16  seq_id;
3773         __le16  target_id;
3774         __le64  resp_addr;
3775         __le32  flags;
3776         #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL
3777         #define QUEUE_CFG_REQ_FLAGS_PATH_SFT  0
3778         #define QUEUE_CFG_REQ_FLAGS_PATH_TX     0x0UL
3779         #define QUEUE_CFG_REQ_FLAGS_PATH_RX     0x1UL
3780         #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR  0x2UL
3781         #define QUEUE_CFG_REQ_FLAGS_PATH_LAST  QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
3782         __le32  enables;
3783         #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN            0x1UL
3784         #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE     0x2UL
3785         __le32  queue_id;
3786         __le32  dflt_len;
3787         u8      service_profile;
3788         #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY    0x0UL
3789         #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL
3790         #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN  0xffUL
3791         #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST    QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN
3792         u8      unused_0[7];
3793 };
3794 
3795 /* hwrm_queue_cfg_output (size:128b/16B) */
3796 struct hwrm_queue_cfg_output {
3797         __le16  error_code;
3798         __le16  req_type;
3799         __le16  seq_id;
3800         __le16  resp_len;
3801         u8      unused_0[7];
3802         u8      valid;
3803 };
3804 
3805 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
3806 struct hwrm_queue_pfcenable_qcfg_input {
3807         __le16  req_type;
3808         __le16  cmpl_ring;
3809         __le16  seq_id;
3810         __le16  target_id;
3811         __le64  resp_addr;
3812         __le16  port_id;
3813         u8      unused_0[6];
3814 };
3815 
3816 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
3817 struct hwrm_queue_pfcenable_qcfg_output {
3818         __le16  error_code;
3819         __le16  req_type;
3820         __le16  seq_id;
3821         __le16  resp_len;
3822         __le32  flags;
3823         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED     0x1UL
3824         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED     0x2UL
3825         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED     0x4UL
3826         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED     0x8UL
3827         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED     0x10UL
3828         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED     0x20UL
3829         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED     0x40UL
3830         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED     0x80UL
3831         u8      unused_0[3];
3832         u8      valid;
3833 };
3834 
3835 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
3836 struct hwrm_queue_pfcenable_cfg_input {
3837         __le16  req_type;
3838         __le16  cmpl_ring;
3839         __le16  seq_id;
3840         __le16  target_id;
3841         __le64  resp_addr;
3842         __le32  flags;
3843         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED     0x1UL
3844         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED     0x2UL
3845         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED     0x4UL
3846         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED     0x8UL
3847         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED     0x10UL
3848         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED     0x20UL
3849         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED     0x40UL
3850         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED     0x80UL
3851         __le16  port_id;
3852         u8      unused_0[2];
3853 };
3854 
3855 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
3856 struct hwrm_queue_pfcenable_cfg_output {
3857         __le16  error_code;
3858         __le16  req_type;
3859         __le16  seq_id;
3860         __le16  resp_len;
3861         u8      unused_0[7];
3862         u8      valid;
3863 };
3864 
3865 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
3866 struct hwrm_queue_pri2cos_qcfg_input {
3867         __le16  req_type;
3868         __le16  cmpl_ring;
3869         __le16  seq_id;
3870         __le16  target_id;
3871         __le64  resp_addr;
3872         __le32  flags;
3873         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH      0x1UL
3874         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX     0x0UL
3875         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX     0x1UL
3876         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST  QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX
3877         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN     0x2UL
3878         u8      port_id;
3879         u8      unused_0[3];
3880 };
3881 
3882 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
3883 struct hwrm_queue_pri2cos_qcfg_output {
3884         __le16  error_code;
3885         __le16  req_type;
3886         __le16  seq_id;
3887         __le16  resp_len;
3888         u8      pri0_cos_queue_id;
3889         u8      pri1_cos_queue_id;
3890         u8      pri2_cos_queue_id;
3891         u8      pri3_cos_queue_id;
3892         u8      pri4_cos_queue_id;
3893         u8      pri5_cos_queue_id;
3894         u8      pri6_cos_queue_id;
3895         u8      pri7_cos_queue_id;
3896         u8      queue_cfg_info;
3897         #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG     0x1UL
3898         u8      unused_0[6];
3899         u8      valid;
3900 };
3901 
3902 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
3903 struct hwrm_queue_pri2cos_cfg_input {
3904         __le16  req_type;
3905         __le16  cmpl_ring;
3906         __le16  seq_id;
3907         __le16  target_id;
3908         __le64  resp_addr;
3909         __le32  flags;
3910         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL
3911         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT  0
3912         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX     0x0UL
3913         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX     0x1UL
3914         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR  0x2UL
3915         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST  QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
3916         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN     0x4UL
3917         __le32  enables;
3918         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID     0x1UL
3919         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID     0x2UL
3920         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID     0x4UL
3921         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID     0x8UL
3922         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID     0x10UL
3923         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID     0x20UL
3924         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID     0x40UL
3925         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID     0x80UL
3926         u8      port_id;
3927         u8      pri0_cos_queue_id;
3928         u8      pri1_cos_queue_id;
3929         u8      pri2_cos_queue_id;
3930         u8      pri3_cos_queue_id;
3931         u8      pri4_cos_queue_id;
3932         u8      pri5_cos_queue_id;
3933         u8      pri6_cos_queue_id;
3934         u8      pri7_cos_queue_id;
3935         u8      unused_0[7];
3936 };
3937 
3938 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
3939 struct hwrm_queue_pri2cos_cfg_output {
3940         __le16  error_code;
3941         __le16  req_type;
3942         __le16  seq_id;
3943         __le16  resp_len;
3944         u8      unused_0[7];
3945         u8      valid;
3946 };
3947 
3948 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
3949 struct hwrm_queue_cos2bw_qcfg_input {
3950         __le16  req_type;
3951         __le16  cmpl_ring;
3952         __le16  seq_id;
3953         __le16  target_id;
3954         __le64  resp_addr;
3955         __le16  port_id;
3956         u8      unused_0[6];
3957 };
3958 
3959 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
3960 struct hwrm_queue_cos2bw_qcfg_output {
3961         __le16  error_code;
3962         __le16  req_type;
3963         __le16  seq_id;
3964         __le16  resp_len;
3965         u8      queue_id0;
3966         u8      unused_0;
3967         __le16  unused_1;
3968         __le32  queue_id0_min_bw;
3969         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK             0xfffffffUL
3970         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT              0
3971         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE                     0x10000000UL
3972         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS                  (0x0UL << 28)
3973         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
3974         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES
3975         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
3976         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT         29
3977         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
3978         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
3979         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
3980         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
3981         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
3982         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
3983         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
3984         __le32  queue_id0_max_bw;
3985         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK             0xfffffffUL
3986         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT              0
3987         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE                     0x10000000UL
3988         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS                  (0x0UL << 28)
3989         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
3990         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES
3991         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
3992         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT         29
3993         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
3994         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
3995         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
3996         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
3997         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
3998         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
3999         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
4000         u8      queue_id0_tsa_assign;
4001         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP             0x0UL
4002         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS            0x1UL
4003         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4004         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST  0xffUL
4005         u8      queue_id0_pri_lvl;
4006         u8      queue_id0_bw_weight;
4007         u8      queue_id1;
4008         __le32  queue_id1_min_bw;
4009         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4010         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT              0
4011         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE                     0x10000000UL
4012         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4013         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4014         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES
4015         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4016         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT         29
4017         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4018         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4019         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4020         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4021         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4022         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4023         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
4024         __le32  queue_id1_max_bw;
4025         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4026         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT              0
4027         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE                     0x10000000UL
4028         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4029         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4030         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES
4031         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4032         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT         29
4033         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4034         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4035         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4036         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4037         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4038         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4039         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
4040         u8      queue_id1_tsa_assign;
4041         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP             0x0UL
4042         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS            0x1UL
4043         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4044         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST  0xffUL
4045         u8      queue_id1_pri_lvl;
4046         u8      queue_id1_bw_weight;
4047         u8      queue_id2;
4048         __le32  queue_id2_min_bw;
4049         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4050         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT              0
4051         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE                     0x10000000UL
4052         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4053         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4054         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES
4055         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4056         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT         29
4057         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4058         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4059         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4060         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4061         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4062         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4063         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
4064         __le32  queue_id2_max_bw;
4065         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4066         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT              0
4067         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE                     0x10000000UL
4068         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4069         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4070         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES
4071         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4072         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT         29
4073         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4074         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4075         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4076         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4077         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4078         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4079         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
4080         u8      queue_id2_tsa_assign;
4081         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP             0x0UL
4082         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS            0x1UL
4083         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4084         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST  0xffUL
4085         u8      queue_id2_pri_lvl;
4086         u8      queue_id2_bw_weight;
4087         u8      queue_id3;
4088         __le32  queue_id3_min_bw;
4089         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4090         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT              0
4091         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE                     0x10000000UL
4092         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4093         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4094         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES
4095         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4096         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT         29
4097         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4098         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4099         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4100         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4101         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4102         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4103         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
4104         __le32  queue_id3_max_bw;
4105         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4106         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT              0
4107         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE                     0x10000000UL
4108         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4109         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4110         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES
4111         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4112         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT         29
4113         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4114         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4115         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4116         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4117         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4118         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4119         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
4120         u8      queue_id3_tsa_assign;
4121         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP             0x0UL
4122         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS            0x1UL
4123         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4124         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST  0xffUL
4125         u8      queue_id3_pri_lvl;
4126         u8      queue_id3_bw_weight;
4127         u8      queue_id4;
4128         __le32  queue_id4_min_bw;
4129         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4130         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT              0
4131         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE                     0x10000000UL
4132         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4133         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4134         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES
4135         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4136         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT         29
4137         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4138         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4139         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4140         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4141         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4142         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4143         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
4144         __le32  queue_id4_max_bw;
4145         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4146         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT              0
4147         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE                     0x10000000UL
4148         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4149         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4150         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES
4151         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4152         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT         29
4153         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4154         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4155         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4156         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4157         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4158         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4159         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
4160         u8      queue_id4_tsa_assign;
4161         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP             0x0UL
4162         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS            0x1UL
4163         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4164         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST  0xffUL
4165         u8      queue_id4_pri_lvl;
4166         u8      queue_id4_bw_weight;
4167         u8      queue_id5;
4168         __le32  queue_id5_min_bw;
4169         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4170         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT              0
4171         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE                     0x10000000UL
4172         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4173         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4174         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES
4175         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4176         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT         29
4177         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4178         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4179         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4180         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4181         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4182         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4183         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
4184         __le32  queue_id5_max_bw;
4185         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4186         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT              0
4187         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE                     0x10000000UL
4188         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4189         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4190         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES
4191         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4192         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT         29
4193         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4194         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4195         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4196         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4197         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4198         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4199         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
4200         u8      queue_id5_tsa_assign;
4201         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP             0x0UL
4202         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS            0x1UL
4203         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4204         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST  0xffUL
4205         u8      queue_id5_pri_lvl;
4206         u8      queue_id5_bw_weight;
4207         u8      queue_id6;
4208         __le32  queue_id6_min_bw;
4209         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4210         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT              0
4211         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE                     0x10000000UL
4212         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4213         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4214         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES
4215         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4216         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT         29
4217         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4218         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4219         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4220         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4221         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4222         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4223         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
4224         __le32  queue_id6_max_bw;
4225         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4226         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT              0
4227         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE                     0x10000000UL
4228         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4229         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4230         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES
4231         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4232         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT         29
4233         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4234         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4235         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4236         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4237         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4238         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4239         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
4240         u8      queue_id6_tsa_assign;
4241         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP             0x0UL
4242         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS            0x1UL
4243         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4244         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST  0xffUL
4245         u8      queue_id6_pri_lvl;
4246         u8      queue_id6_bw_weight;
4247         u8      queue_id7;
4248         __le32  queue_id7_min_bw;
4249         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4250         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT              0
4251         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE                     0x10000000UL
4252         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4253         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4254         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES
4255         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4256         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT         29
4257         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4258         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4259         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4260         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4261         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4262         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4263         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
4264         __le32  queue_id7_max_bw;
4265         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4266         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT              0
4267         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE                     0x10000000UL
4268         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4269         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4270         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES
4271         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4272         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT         29
4273         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4274         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4275         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4276         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4277         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4278         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4279         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
4280         u8      queue_id7_tsa_assign;
4281         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP             0x0UL
4282         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS            0x1UL
4283         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4284         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST  0xffUL
4285         u8      queue_id7_pri_lvl;
4286         u8      queue_id7_bw_weight;
4287         u8      unused_2[4];
4288         u8      valid;
4289 };
4290 
4291 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
4292 struct hwrm_queue_cos2bw_cfg_input {
4293         __le16  req_type;
4294         __le16  cmpl_ring;
4295         __le16  seq_id;
4296         __le16  target_id;
4297         __le64  resp_addr;
4298         __le32  flags;
4299         __le32  enables;
4300         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID     0x1UL
4301         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID     0x2UL
4302         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID     0x4UL
4303         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID     0x8UL
4304         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID     0x10UL
4305         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID     0x20UL
4306         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID     0x40UL
4307         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID     0x80UL
4308         __le16  port_id;
4309         u8      queue_id0;
4310         u8      unused_0;
4311         __le32  queue_id0_min_bw;
4312         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4313         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT              0
4314         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE                     0x10000000UL
4315         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4316         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4317         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES
4318         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4319         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT         29
4320         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4321         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4322         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4323         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4324         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4325         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4326         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
4327         __le32  queue_id0_max_bw;
4328         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4329         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT              0
4330         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE                     0x10000000UL
4331         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4332         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4333         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES
4334         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4335         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT         29
4336         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4337         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4338         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4339         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4340         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4341         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4342         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
4343         u8      queue_id0_tsa_assign;
4344         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP             0x0UL
4345         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS            0x1UL
4346         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4347         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST  0xffUL
4348         u8      queue_id0_pri_lvl;
4349         u8      queue_id0_bw_weight;
4350         u8      queue_id1;
4351         __le32  queue_id1_min_bw;
4352         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4353         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT              0
4354         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE                     0x10000000UL
4355         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4356         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4357         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES
4358         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4359         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT         29
4360         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4361         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4362         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4363         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4364         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4365         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4366         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
4367         __le32  queue_id1_max_bw;
4368         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4369         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT              0
4370         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE                     0x10000000UL
4371         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4372         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4373         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES
4374         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4375         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT         29
4376         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4377         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4378         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4379         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4380         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4381         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4382         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
4383         u8      queue_id1_tsa_assign;
4384         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP             0x0UL
4385         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS            0x1UL
4386         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4387         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST  0xffUL
4388         u8      queue_id1_pri_lvl;
4389         u8      queue_id1_bw_weight;
4390         u8      queue_id2;
4391         __le32  queue_id2_min_bw;
4392         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4393         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT              0
4394         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE                     0x10000000UL
4395         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4396         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4397         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES
4398         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4399         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT         29
4400         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4401         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4402         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4403         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4404         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4405         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4406         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
4407         __le32  queue_id2_max_bw;
4408         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4409         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT              0
4410         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE                     0x10000000UL
4411         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4412         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4413         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES
4414         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4415         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT         29
4416         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4417         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4418         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4419         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4420         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4421         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4422         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
4423         u8      queue_id2_tsa_assign;
4424         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP             0x0UL
4425         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS            0x1UL
4426         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4427         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST  0xffUL
4428         u8      queue_id2_pri_lvl;
4429         u8      queue_id2_bw_weight;
4430         u8      queue_id3;
4431         __le32  queue_id3_min_bw;
4432         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4433         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT              0
4434         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE                     0x10000000UL
4435         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4436         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4437         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES
4438         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4439         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT         29
4440         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4441         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4442         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4443         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4444         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4445         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4446         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
4447         __le32  queue_id3_max_bw;
4448         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4449         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT              0
4450         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE                     0x10000000UL
4451         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4452         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4453         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES
4454         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4455         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT         29
4456         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4457         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4458         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4459         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4460         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4461         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4462         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
4463         u8      queue_id3_tsa_assign;
4464         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP             0x0UL
4465         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS            0x1UL
4466         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4467         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST  0xffUL
4468         u8      queue_id3_pri_lvl;
4469         u8      queue_id3_bw_weight;
4470         u8      queue_id4;
4471         __le32  queue_id4_min_bw;
4472         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4473         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT              0
4474         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE                     0x10000000UL
4475         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4476         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4477         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES
4478         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4479         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT         29
4480         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4481         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4482         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4483         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4484         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4485         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4486         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
4487         __le32  queue_id4_max_bw;
4488         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4489         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT              0
4490         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE                     0x10000000UL
4491         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4492         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4493         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES
4494         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4495         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT         29
4496         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4497         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4498         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4499         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4500         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4501         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4502         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
4503         u8      queue_id4_tsa_assign;
4504         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP             0x0UL
4505         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS            0x1UL
4506         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4507         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST  0xffUL
4508         u8      queue_id4_pri_lvl;
4509         u8      queue_id4_bw_weight;
4510         u8      queue_id5;
4511         __le32  queue_id5_min_bw;
4512         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4513         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT              0
4514         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE                     0x10000000UL
4515         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4516         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4517         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES
4518         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4519         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT         29
4520         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4521         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4522         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4523         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4524         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4525         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4526         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
4527         __le32  queue_id5_max_bw;
4528         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4529         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT              0
4530         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE                     0x10000000UL
4531         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4532         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4533         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES
4534         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4535         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT         29
4536         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4537         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4538         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4539         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4540         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4541         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4542         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
4543         u8      queue_id5_tsa_assign;
4544         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP             0x0UL
4545         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS            0x1UL
4546         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4547         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST  0xffUL
4548         u8      queue_id5_pri_lvl;
4549         u8      queue_id5_bw_weight;
4550         u8      queue_id6;
4551         __le32  queue_id6_min_bw;
4552         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4553         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT              0
4554         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE                     0x10000000UL
4555         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4556         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4557         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES
4558         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4559         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT         29
4560         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4561         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4562         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4563         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4564         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4565         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4566         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
4567         __le32  queue_id6_max_bw;
4568         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4569         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT              0
4570         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE                     0x10000000UL
4571         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4572         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4573         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES
4574         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4575         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT         29
4576         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4577         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4578         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4579         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4580         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4581         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4582         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
4583         u8      queue_id6_tsa_assign;
4584         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP             0x0UL
4585         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS            0x1UL
4586         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4587         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST  0xffUL
4588         u8      queue_id6_pri_lvl;
4589         u8      queue_id6_bw_weight;
4590         u8      queue_id7;
4591         __le32  queue_id7_min_bw;
4592         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK             0xfffffffUL
4593         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT              0
4594         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE                     0x10000000UL
4595         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS                  (0x0UL << 28)
4596         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
4597         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES
4598         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4599         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT         29
4600         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4601         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4602         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4603         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4604         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4605         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4606         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
4607         __le32  queue_id7_max_bw;
4608         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK             0xfffffffUL
4609         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT              0
4610         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE                     0x10000000UL
4611         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS                  (0x0UL << 28)
4612         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
4613         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES
4614         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
4615         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT         29
4616         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
4617         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
4618         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
4619         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
4620         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
4621         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
4622         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
4623         u8      queue_id7_tsa_assign;
4624         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP             0x0UL
4625         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS            0x1UL
4626         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4627         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST  0xffUL
4628         u8      queue_id7_pri_lvl;
4629         u8      queue_id7_bw_weight;
4630         u8      unused_1[5];
4631 };
4632 
4633 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
4634 struct hwrm_queue_cos2bw_cfg_output {
4635         __le16  error_code;
4636         __le16  req_type;
4637         __le16  seq_id;
4638         __le16  resp_len;
4639         u8      unused_0[7];
4640         u8      valid;
4641 };
4642 
4643 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
4644 struct hwrm_queue_dscp_qcaps_input {
4645         __le16  req_type;
4646         __le16  cmpl_ring;
4647         __le16  seq_id;
4648         __le16  target_id;
4649         __le64  resp_addr;
4650         u8      port_id;
4651         u8      unused_0[7];
4652 };
4653 
4654 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
4655 struct hwrm_queue_dscp_qcaps_output {
4656         __le16  error_code;
4657         __le16  req_type;
4658         __le16  seq_id;
4659         __le16  resp_len;
4660         u8      num_dscp_bits;
4661         u8      unused_0;
4662         __le16  max_entries;
4663         u8      unused_1[3];
4664         u8      valid;
4665 };
4666 
4667 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
4668 struct hwrm_queue_dscp2pri_qcfg_input {
4669         __le16  req_type;
4670         __le16  cmpl_ring;
4671         __le16  seq_id;
4672         __le16  target_id;
4673         __le64  resp_addr;
4674         __le64  dest_data_addr;
4675         u8      port_id;
4676         u8      unused_0;
4677         __le16  dest_data_buffer_size;
4678         u8      unused_1[4];
4679 };
4680 
4681 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
4682 struct hwrm_queue_dscp2pri_qcfg_output {
4683         __le16  error_code;
4684         __le16  req_type;
4685         __le16  seq_id;
4686         __le16  resp_len;
4687         __le16  entry_cnt;
4688         u8      default_pri;
4689         u8      unused_0[4];
4690         u8      valid;
4691 };
4692 
4693 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
4694 struct hwrm_queue_dscp2pri_cfg_input {
4695         __le16  req_type;
4696         __le16  cmpl_ring;
4697         __le16  seq_id;
4698         __le16  target_id;
4699         __le64  resp_addr;
4700         __le64  src_data_addr;
4701         __le32  flags;
4702         #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI     0x1UL
4703         __le32  enables;
4704         #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI     0x1UL
4705         u8      port_id;
4706         u8      default_pri;
4707         __le16  entry_cnt;
4708         u8      unused_0[4];
4709 };
4710 
4711 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
4712 struct hwrm_queue_dscp2pri_cfg_output {
4713         __le16  error_code;
4714         __le16  req_type;
4715         __le16  seq_id;
4716         __le16  resp_len;
4717         u8      unused_0[7];
4718         u8      valid;
4719 };
4720 
4721 /* hwrm_vnic_alloc_input (size:192b/24B) */
4722 struct hwrm_vnic_alloc_input {
4723         __le16  req_type;
4724         __le16  cmpl_ring;
4725         __le16  seq_id;
4726         __le16  target_id;
4727         __le64  resp_addr;
4728         __le32  flags;
4729         #define VNIC_ALLOC_REQ_FLAGS_DEFAULT     0x1UL
4730         u8      unused_0[4];
4731 };
4732 
4733 /* hwrm_vnic_alloc_output (size:128b/16B) */
4734 struct hwrm_vnic_alloc_output {
4735         __le16  error_code;
4736         __le16  req_type;
4737         __le16  seq_id;
4738         __le16  resp_len;
4739         __le32  vnic_id;
4740         u8      unused_0[3];
4741         u8      valid;
4742 };
4743 
4744 /* hwrm_vnic_free_input (size:192b/24B) */
4745 struct hwrm_vnic_free_input {
4746         __le16  req_type;
4747         __le16  cmpl_ring;
4748         __le16  seq_id;
4749         __le16  target_id;
4750         __le64  resp_addr;
4751         __le32  vnic_id;
4752         u8      unused_0[4];
4753 };
4754 
4755 /* hwrm_vnic_free_output (size:128b/16B) */
4756 struct hwrm_vnic_free_output {
4757         __le16  error_code;
4758         __le16  req_type;
4759         __le16  seq_id;
4760         __le16  resp_len;
4761         u8      unused_0[7];
4762         u8      valid;
4763 };
4764 
4765 /* hwrm_vnic_cfg_input (size:384b/48B) */
4766 struct hwrm_vnic_cfg_input {
4767         __le16  req_type;
4768         __le16  cmpl_ring;
4769         __le16  seq_id;
4770         __le16  target_id;
4771         __le64  resp_addr;
4772         __le32  flags;
4773         #define VNIC_CFG_REQ_FLAGS_DEFAULT                              0x1UL
4774         #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE                      0x2UL
4775         #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE                        0x4UL
4776         #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE                  0x8UL
4777         #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE                  0x10UL
4778         #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE                     0x20UL
4779         #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE     0x40UL
4780         __le32  enables;
4781         #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP            0x1UL
4782         #define VNIC_CFG_REQ_ENABLES_RSS_RULE                 0x2UL
4783         #define VNIC_CFG_REQ_ENABLES_COS_RULE                 0x4UL
4784         #define VNIC_CFG_REQ_ENABLES_LB_RULE                  0x8UL
4785         #define VNIC_CFG_REQ_ENABLES_MRU                      0x10UL
4786         #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID       0x20UL
4787         #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID     0x40UL
4788         #define VNIC_CFG_REQ_ENABLES_QUEUE_ID                 0x80UL
4789         __le16  vnic_id;
4790         __le16  dflt_ring_grp;
4791         __le16  rss_rule;
4792         __le16  cos_rule;
4793         __le16  lb_rule;
4794         __le16  mru;
4795         __le16  default_rx_ring_id;
4796         __le16  default_cmpl_ring_id;
4797         __le16  queue_id;
4798         u8      unused0[6];
4799 };
4800 
4801 /* hwrm_vnic_cfg_output (size:128b/16B) */
4802 struct hwrm_vnic_cfg_output {
4803         __le16  error_code;
4804         __le16  req_type;
4805         __le16  seq_id;
4806         __le16  resp_len;
4807         u8      unused_0[7];
4808         u8      valid;
4809 };
4810 
4811 /* hwrm_vnic_qcaps_input (size:192b/24B) */
4812 struct hwrm_vnic_qcaps_input {
4813         __le16  req_type;
4814         __le16  cmpl_ring;
4815         __le16  seq_id;
4816         __le16  target_id;
4817         __le64  resp_addr;
4818         __le32  enables;
4819         u8      unused_0[4];
4820 };
4821 
4822 /* hwrm_vnic_qcaps_output (size:192b/24B) */
4823 struct hwrm_vnic_qcaps_output {
4824         __le16  error_code;
4825         __le16  req_type;
4826         __le16  seq_id;
4827         __le16  resp_len;
4828         __le16  mru;
4829         u8      unused_0[2];
4830         __le32  flags;
4831         #define VNIC_QCAPS_RESP_FLAGS_UNUSED                              0x1UL
4832         #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP                      0x2UL
4833         #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP                        0x4UL
4834         #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP                  0x8UL
4835         #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP                  0x10UL
4836         #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP                     0x20UL
4837         #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP     0x40UL
4838         #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP                   0x80UL
4839         #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP                  0x100UL
4840         __le16  max_aggs_supported;
4841         u8      unused_1[5];
4842         u8      valid;
4843 };
4844 
4845 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
4846 struct hwrm_vnic_tpa_cfg_input {
4847         __le16  req_type;
4848         __le16  cmpl_ring;
4849         __le16  seq_id;
4850         __le16  target_id;
4851         __le64  resp_addr;
4852         __le32  flags;
4853         #define VNIC_TPA_CFG_REQ_FLAGS_TPA                       0x1UL
4854         #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA                 0x2UL
4855         #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE            0x4UL
4856         #define VNIC_TPA_CFG_REQ_FLAGS_GRO                       0x8UL
4857         #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN              0x10UL
4858         #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ     0x20UL
4859         #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK            0x40UL
4860         #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK             0x80UL
4861         #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO           0x100UL
4862         __le32  enables;
4863         #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS      0x1UL
4864         #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS          0x2UL
4865         #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER     0x4UL
4866         #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN       0x8UL
4867         __le16  vnic_id;
4868         __le16  max_agg_segs;
4869         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1   0x0UL
4870         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2   0x1UL
4871         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4   0x2UL
4872         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8   0x3UL
4873         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL
4874         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
4875         __le16  max_aggs;
4876         #define VNIC_TPA_CFG_REQ_MAX_AGGS_1   0x0UL
4877         #define VNIC_TPA_CFG_REQ_MAX_AGGS_2   0x1UL
4878         #define VNIC_TPA_CFG_REQ_MAX_AGGS_4   0x2UL
4879         #define VNIC_TPA_CFG_REQ_MAX_AGGS_8   0x3UL
4880         #define VNIC_TPA_CFG_REQ_MAX_AGGS_16  0x4UL
4881         #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL
4882         #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
4883         u8      unused_0[2];
4884         __le32  max_agg_timer;
4885         __le32  min_agg_len;
4886 };
4887 
4888 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
4889 struct hwrm_vnic_tpa_cfg_output {
4890         __le16  error_code;
4891         __le16  req_type;
4892         __le16  seq_id;
4893         __le16  resp_len;
4894         u8      unused_0[7];
4895         u8      valid;
4896 };
4897 
4898 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
4899 struct hwrm_vnic_tpa_qcfg_input {
4900         __le16  req_type;
4901         __le16  cmpl_ring;
4902         __le16  seq_id;
4903         __le16  target_id;
4904         __le64  resp_addr;
4905         __le16  vnic_id;
4906         u8      unused_0[6];
4907 };
4908 
4909 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
4910 struct hwrm_vnic_tpa_qcfg_output {
4911         __le16  error_code;
4912         __le16  req_type;
4913         __le16  seq_id;
4914         __le16  resp_len;
4915         __le32  flags;
4916         #define VNIC_TPA_QCFG_RESP_FLAGS_TPA                       0x1UL
4917         #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA                 0x2UL
4918         #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE            0x4UL
4919         #define VNIC_TPA_QCFG_RESP_FLAGS_GRO                       0x8UL
4920         #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN              0x10UL
4921         #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ     0x20UL
4922         #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK            0x40UL
4923         #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK             0x80UL
4924         __le16  max_agg_segs;
4925         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1   0x0UL
4926         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2   0x1UL
4927         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4   0x2UL
4928         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8   0x3UL
4929         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL
4930         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
4931         __le16  max_aggs;
4932         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1   0x0UL
4933         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2   0x1UL
4934         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4   0x2UL
4935         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8   0x3UL
4936         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16  0x4UL
4937         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL
4938         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
4939         __le32  max_agg_timer;
4940         __le32  min_agg_len;
4941         u8      unused_0[7];
4942         u8      valid;
4943 };
4944 
4945 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
4946 struct hwrm_vnic_rss_cfg_input {
4947         __le16  req_type;
4948         __le16  cmpl_ring;
4949         __le16  seq_id;
4950         __le16  target_id;
4951         __le64  resp_addr;
4952         __le32  hash_type;
4953         #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4         0x1UL
4954         #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4     0x2UL
4955         #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4     0x4UL
4956         #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6         0x8UL
4957         #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6     0x10UL
4958         #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6     0x20UL
4959         __le16  vnic_id;
4960         u8      ring_table_pair_index;
4961         u8      hash_mode_flags;
4962         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT         0x1UL
4963         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4     0x2UL
4964         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2     0x4UL
4965         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4     0x8UL
4966         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2     0x10UL
4967         __le64  ring_grp_tbl_addr;
4968         __le64  hash_key_tbl_addr;
4969         __le16  rss_ctx_idx;
4970         u8      unused_1[6];
4971 };
4972 
4973 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
4974 struct hwrm_vnic_rss_cfg_output {
4975         __le16  error_code;
4976         __le16  req_type;
4977         __le16  seq_id;
4978         __le16  resp_len;
4979         u8      unused_0[7];
4980         u8      valid;
4981 };
4982 
4983 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
4984 struct hwrm_vnic_plcmodes_cfg_input {
4985         __le16  req_type;
4986         __le16  cmpl_ring;
4987         __le16  seq_id;
4988         __le16  target_id;
4989         __le64  resp_addr;
4990         __le32  flags;
4991         #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT     0x1UL
4992         #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT       0x2UL
4993         #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4              0x4UL
4994         #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6              0x8UL
4995         #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE              0x10UL
4996         #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE              0x20UL
4997         __le32  enables;
4998         #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID      0x1UL
4999         #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID        0x2UL
5000         #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID     0x4UL
5001         __le32  vnic_id;
5002         __le16  jumbo_thresh;
5003         __le16  hds_offset;
5004         __le16  hds_threshold;
5005         u8      unused_0[6];
5006 };
5007 
5008 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
5009 struct hwrm_vnic_plcmodes_cfg_output {
5010         __le16  error_code;
5011         __le16  req_type;
5012         __le16  seq_id;
5013         __le16  resp_len;
5014         u8      unused_0[7];
5015         u8      valid;
5016 };
5017 
5018 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
5019 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
5020         __le16  req_type;
5021         __le16  cmpl_ring;
5022         __le16  seq_id;
5023         __le16  target_id;
5024         __le64  resp_addr;
5025 };
5026 
5027 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
5028 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
5029         __le16  error_code;
5030         __le16  req_type;
5031         __le16  seq_id;
5032         __le16  resp_len;
5033         __le16  rss_cos_lb_ctx_id;
5034         u8      unused_0[5];
5035         u8      valid;
5036 };
5037 
5038 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
5039 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
5040         __le16  req_type;
5041         __le16  cmpl_ring;
5042         __le16  seq_id;
5043         __le16  target_id;
5044         __le64  resp_addr;
5045         __le16  rss_cos_lb_ctx_id;
5046         u8      unused_0[6];
5047 };
5048 
5049 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
5050 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
5051         __le16  error_code;
5052         __le16  req_type;
5053         __le16  seq_id;
5054         __le16  resp_len;
5055         u8      unused_0[7];
5056         u8      valid;
5057 };
5058 
5059 /* hwrm_ring_alloc_input (size:704b/88B) */
5060 struct hwrm_ring_alloc_input {
5061         __le16  req_type;
5062         __le16  cmpl_ring;
5063         __le16  seq_id;
5064         __le16  target_id;
5065         __le64  resp_addr;
5066         __le32  enables;
5067         #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG          0x2UL
5068         #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID     0x8UL
5069         #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID          0x20UL
5070         #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID      0x40UL
5071         #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID      0x80UL
5072         #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID     0x100UL
5073         u8      ring_type;
5074         #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL   0x0UL
5075         #define RING_ALLOC_REQ_RING_TYPE_TX        0x1UL
5076         #define RING_ALLOC_REQ_RING_TYPE_RX        0x2UL
5077         #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
5078         #define RING_ALLOC_REQ_RING_TYPE_RX_AGG    0x4UL
5079         #define RING_ALLOC_REQ_RING_TYPE_NQ        0x5UL
5080         #define RING_ALLOC_REQ_RING_TYPE_LAST     RING_ALLOC_REQ_RING_TYPE_NQ
5081         u8      unused_0;
5082         __le16  flags;
5083         #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD     0x1UL
5084         __le64  page_tbl_addr;
5085         __le32  fbo;
5086         u8      page_size;
5087         u8      page_tbl_depth;
5088         u8      unused_1[2];
5089         __le32  length;
5090         __le16  logical_id;
5091         __le16  cmpl_ring_id;
5092         __le16  queue_id;
5093         __le16  rx_buf_size;
5094         __le16  rx_ring_id;
5095         __le16  nq_ring_id;
5096         __le16  ring_arb_cfg;
5097         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK      0xfUL
5098         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT       0
5099         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP          0x1UL
5100         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ         0x2UL
5101         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST       RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
5102         #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK            0xf0UL
5103         #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT             4
5104         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL
5105         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
5106         __le16  unused_3;
5107         __le32  reserved3;
5108         __le32  stat_ctx_id;
5109         __le32  reserved4;
5110         __le32  max_bw;
5111         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK             0xfffffffUL
5112         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT              0
5113         #define RING_ALLOC_REQ_MAX_BW_SCALE                     0x10000000UL
5114         #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS                  (0x0UL << 28)
5115         #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
5116         #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST                 RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
5117         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
5118         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT         29
5119         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
5120         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
5121         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
5122         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
5123         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
5124         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
5125         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST         RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
5126         u8      int_mode;
5127         #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL
5128         #define RING_ALLOC_REQ_INT_MODE_RSVD   0x1UL
5129         #define RING_ALLOC_REQ_INT_MODE_MSIX   0x2UL
5130         #define RING_ALLOC_REQ_INT_MODE_POLL   0x3UL
5131         #define RING_ALLOC_REQ_INT_MODE_LAST  RING_ALLOC_REQ_INT_MODE_POLL
5132         u8      unused_4[3];
5133         __le64  cq_handle;
5134 };
5135 
5136 /* hwrm_ring_alloc_output (size:128b/16B) */
5137 struct hwrm_ring_alloc_output {
5138         __le16  error_code;
5139         __le16  req_type;
5140         __le16  seq_id;
5141         __le16  resp_len;
5142         __le16  ring_id;
5143         __le16  logical_ring_id;
5144         u8      unused_0[3];
5145         u8      valid;
5146 };
5147 
5148 /* hwrm_ring_free_input (size:192b/24B) */
5149 struct hwrm_ring_free_input {
5150         __le16  req_type;
5151         __le16  cmpl_ring;
5152         __le16  seq_id;
5153         __le16  target_id;
5154         __le64  resp_addr;
5155         u8      ring_type;
5156         #define RING_FREE_REQ_RING_TYPE_L2_CMPL   0x0UL
5157         #define RING_FREE_REQ_RING_TYPE_TX        0x1UL
5158         #define RING_FREE_REQ_RING_TYPE_RX        0x2UL
5159         #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
5160         #define RING_FREE_REQ_RING_TYPE_RX_AGG    0x4UL
5161         #define RING_FREE_REQ_RING_TYPE_NQ        0x5UL
5162         #define RING_FREE_REQ_RING_TYPE_LAST     RING_FREE_REQ_RING_TYPE_NQ
5163         u8      unused_0;
5164         __le16  ring_id;
5165         u8      unused_1[4];
5166 };
5167 
5168 /* hwrm_ring_free_output (size:128b/16B) */
5169 struct hwrm_ring_free_output {
5170         __le16  error_code;
5171         __le16  req_type;
5172         __le16  seq_id;
5173         __le16  resp_len;
5174         u8      unused_0[7];
5175         u8      valid;
5176 };
5177 
5178 /* hwrm_ring_reset_input (size:192b/24B) */
5179 struct hwrm_ring_reset_input {
5180         __le16  req_type;
5181         __le16  cmpl_ring;
5182         __le16  seq_id;
5183         __le16  target_id;
5184         __le64  resp_addr;
5185         u8      ring_type;
5186         #define RING_RESET_REQ_RING_TYPE_L2_CMPL   0x0UL
5187         #define RING_RESET_REQ_RING_TYPE_TX        0x1UL
5188         #define RING_RESET_REQ_RING_TYPE_RX        0x2UL
5189         #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL
5190         #define RING_RESET_REQ_RING_TYPE_LAST     RING_RESET_REQ_RING_TYPE_ROCE_CMPL
5191         u8      unused_0;
5192         __le16  ring_id;
5193         u8      unused_1[4];
5194 };
5195 
5196 /* hwrm_ring_reset_output (size:128b/16B) */
5197 struct hwrm_ring_reset_output {
5198         __le16  error_code;
5199         __le16  req_type;
5200         __le16  seq_id;
5201         __le16  resp_len;
5202         u8      unused_0[4];
5203         u8      consumer_idx[3];
5204         u8      valid;
5205 };
5206 
5207 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
5208 struct hwrm_ring_aggint_qcaps_input {
5209         __le16  req_type;
5210         __le16  cmpl_ring;
5211         __le16  seq_id;
5212         __le16  target_id;
5213         __le64  resp_addr;
5214 };
5215 
5216 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
5217 struct hwrm_ring_aggint_qcaps_output {
5218         __le16  error_code;
5219         __le16  req_type;
5220         __le16  seq_id;
5221         __le16  resp_len;
5222         __le32  cmpl_params;
5223         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN                  0x1UL
5224         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX                  0x2UL
5225         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET                      0x4UL
5226         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE                        0x8UL
5227         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR                0x10UL
5228         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT     0x20UL
5229         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR                0x40UL
5230         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT     0x80UL
5231         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT                0x100UL
5232         __le32  nq_params;
5233         #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN     0x1UL
5234         __le16  num_cmpl_dma_aggr_min;
5235         __le16  num_cmpl_dma_aggr_max;
5236         __le16  num_cmpl_dma_aggr_during_int_min;
5237         __le16  num_cmpl_dma_aggr_during_int_max;
5238         __le16  cmpl_aggr_dma_tmr_min;
5239         __le16  cmpl_aggr_dma_tmr_max;
5240         __le16  cmpl_aggr_dma_tmr_during_int_min;
5241         __le16  cmpl_aggr_dma_tmr_during_int_max;
5242         __le16  int_lat_tmr_min_min;
5243         __le16  int_lat_tmr_min_max;
5244         __le16  int_lat_tmr_max_min;
5245         __le16  int_lat_tmr_max_max;
5246         __le16  num_cmpl_aggr_int_min;
5247         __le16  num_cmpl_aggr_int_max;
5248         __le16  timer_units;
5249         u8      unused_0[1];
5250         u8      valid;
5251 };
5252 
5253 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
5254 struct hwrm_ring_cmpl_ring_qaggint_params_input {
5255         __le16  req_type;
5256         __le16  cmpl_ring;
5257         __le16  seq_id;
5258         __le16  target_id;
5259         __le64  resp_addr;
5260         __le16  ring_id;
5261         u8      unused_0[6];
5262 };
5263 
5264 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
5265 struct hwrm_ring_cmpl_ring_qaggint_params_output {
5266         __le16  error_code;
5267         __le16  req_type;
5268         __le16  seq_id;
5269         __le16  resp_len;
5270         __le16  flags;
5271         #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET     0x1UL
5272         #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE       0x2UL
5273         __le16  num_cmpl_dma_aggr;
5274         __le16  num_cmpl_dma_aggr_during_int;
5275         __le16  cmpl_aggr_dma_tmr;
5276         __le16  cmpl_aggr_dma_tmr_during_int;
5277         __le16  int_lat_tmr_min;
5278         __le16  int_lat_tmr_max;
5279         __le16  num_cmpl_aggr_int;
5280         u8      unused_0[7];
5281         u8      valid;
5282 };
5283 
5284 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
5285 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
5286         __le16  req_type;
5287         __le16  cmpl_ring;
5288         __le16  seq_id;
5289         __le16  target_id;
5290         __le64  resp_addr;
5291         __le16  ring_id;
5292         __le16  flags;
5293         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET     0x1UL
5294         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE       0x2UL
5295         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ           0x4UL
5296         __le16  num_cmpl_dma_aggr;
5297         __le16  num_cmpl_dma_aggr_during_int;
5298         __le16  cmpl_aggr_dma_tmr;
5299         __le16  cmpl_aggr_dma_tmr_during_int;
5300         __le16  int_lat_tmr_min;
5301         __le16  int_lat_tmr_max;
5302         __le16  num_cmpl_aggr_int;
5303         __le16  enables;
5304         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR                0x1UL
5305         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT     0x2UL
5306         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR                0x4UL
5307         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN                  0x8UL
5308         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX                  0x10UL
5309         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT                0x20UL
5310         u8      unused_0[4];
5311 };
5312 
5313 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
5314 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
5315         __le16  error_code;
5316         __le16  req_type;
5317         __le16  seq_id;
5318         __le16  resp_len;
5319         u8      unused_0[7];
5320         u8      valid;
5321 };
5322 
5323 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
5324 struct hwrm_ring_grp_alloc_input {
5325         __le16  req_type;
5326         __le16  cmpl_ring;
5327         __le16  seq_id;
5328         __le16  target_id;
5329         __le64  resp_addr;
5330         __le16  cr;
5331         __le16  rr;
5332         __le16  ar;
5333         __le16  sc;
5334 };
5335 
5336 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
5337 struct hwrm_ring_grp_alloc_output {
5338         __le16  error_code;
5339         __le16  req_type;
5340         __le16  seq_id;
5341         __le16  resp_len;
5342         __le32  ring_group_id;
5343         u8      unused_0[3];
5344         u8      valid;
5345 };
5346 
5347 /* hwrm_ring_grp_free_input (size:192b/24B) */
5348 struct hwrm_ring_grp_free_input {
5349         __le16  req_type;
5350         __le16  cmpl_ring;
5351         __le16  seq_id;
5352         __le16  target_id;
5353         __le64  resp_addr;
5354         __le32  ring_group_id;
5355         u8      unused_0[4];
5356 };
5357 
5358 /* hwrm_ring_grp_free_output (size:128b/16B) */
5359 struct hwrm_ring_grp_free_output {
5360         __le16  error_code;
5361         __le16  req_type;
5362         __le16  seq_id;
5363         __le16  resp_len;
5364         u8      unused_0[7];
5365         u8      valid;
5366 };
5367 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
5368 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
5369 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
5370 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
5371 
5372 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
5373 struct hwrm_cfa_l2_filter_alloc_input {
5374         __le16  req_type;
5375         __le16  cmpl_ring;
5376         __le16  seq_id;
5377         __le16  target_id;
5378         __le64  resp_addr;
5379         __le32  flags;
5380         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH              0x1UL
5381         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX             0x0UL
5382         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX             0x1UL
5383         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST          CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
5384         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK          0x2UL
5385         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP              0x4UL
5386         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST         0x8UL
5387         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK      0x30UL
5388         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT       4
5389         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2  (0x0UL << 4)
5390         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2          (0x1UL << 4)
5391         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE        (0x2UL << 4)
5392         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST       CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE
5393         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE       0x40UL
5394         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID      0x80UL
5395         __le32  enables;
5396         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR             0x1UL
5397         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK        0x2UL
5398         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN            0x4UL
5399         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK       0x8UL
5400         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN            0x10UL
5401         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK       0x20UL
5402         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR           0x40UL
5403         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK      0x80UL
5404         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN          0x100UL
5405         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK     0x200UL
5406         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN          0x400UL
5407         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK     0x800UL
5408         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE            0x1000UL
5409         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID              0x2000UL
5410         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE         0x4000UL
5411         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID              0x8000UL
5412         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID      0x10000UL
5413         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS           0x20000UL
5414         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS         0x40000UL
5415         u8      l2_addr[6];
5416         u8      num_vlans;
5417         u8      t_num_vlans;
5418         u8      l2_addr_mask[6];
5419         __le16  l2_ovlan;
5420         __le16  l2_ovlan_mask;
5421         __le16  l2_ivlan;
5422         __le16  l2_ivlan_mask;
5423         u8      unused_1[2];
5424         u8      t_l2_addr[6];
5425         u8      unused_2[2];
5426         u8      t_l2_addr_mask[6];
5427         __le16  t_l2_ovlan;
5428         __le16  t_l2_ovlan_mask;
5429         __le16  t_l2_ivlan;
5430         __le16  t_l2_ivlan_mask;
5431         u8      src_type;
5432         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
5433         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF    0x1UL
5434         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF    0x2UL
5435         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC  0x3UL
5436         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG  0x4UL
5437         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE   0x5UL
5438         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO  0x6UL
5439         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG  0x7UL
5440         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG
5441         u8      unused_3;
5442         __le32  src_id;
5443         u8      tunnel_type;
5444         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL
5445         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL
5446         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL
5447         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL
5448         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL
5449         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL
5450         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL
5451         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL
5452         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL
5453         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
5454         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
5455         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
5456         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5457         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL
5458         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5459         u8      unused_4;
5460         __le16  dst_id;
5461         __le16  mirror_vnic_id;
5462         u8      pri_hint;
5463         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER    0x0UL
5464         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL
5465         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL
5466         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX          0x3UL
5467         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN          0x4UL
5468         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST        CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN
5469         u8      unused_5;
5470         __le32  unused_6;
5471         __le64  l2_filter_id_hint;
5472 };
5473 
5474 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
5475 struct hwrm_cfa_l2_filter_alloc_output {
5476         __le16  error_code;
5477         __le16  req_type;
5478         __le16  seq_id;
5479         __le16  resp_len;
5480         __le64  l2_filter_id;
5481         __le32  flow_id;
5482         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
5483         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
5484         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE      0x40000000UL
5485         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT    (0x0UL << 30)
5486         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT    (0x1UL << 30)
5487         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST  CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
5488         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR       0x80000000UL
5489         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX      (0x0UL << 31)
5490         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX      (0x1UL << 31)
5491         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST   CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
5492         u8      unused_0[3];
5493         u8      valid;
5494 };
5495 
5496 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
5497 struct hwrm_cfa_l2_filter_free_input {
5498         __le16  req_type;
5499         __le16  cmpl_ring;
5500         __le16  seq_id;
5501         __le16  target_id;
5502         __le64  resp_addr;
5503         __le64  l2_filter_id;
5504 };
5505 
5506 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
5507 struct hwrm_cfa_l2_filter_free_output {
5508         __le16  error_code;
5509         __le16  req_type;
5510         __le16  seq_id;
5511         __le16  resp_len;
5512         u8      unused_0[7];
5513         u8      valid;
5514 };
5515 
5516 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
5517 struct hwrm_cfa_l2_filter_cfg_input {
5518         __le16  req_type;
5519         __le16  cmpl_ring;
5520         __le16  seq_id;
5521         __le16  target_id;
5522         __le64  resp_addr;
5523         __le32  flags;
5524         #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH              0x1UL
5525         #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX             0x0UL
5526         #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX             0x1UL
5527         #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST          CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
5528         #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP              0x2UL
5529         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK      0xcUL
5530         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT       2
5531         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2  (0x0UL << 2)
5532         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2          (0x1UL << 2)
5533         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE        (0x2UL << 2)
5534         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST       CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE
5535         __le32  enables;
5536         #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID                 0x1UL
5537         #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID     0x2UL
5538         __le64  l2_filter_id;
5539         __le32  dst_id;
5540         __le32  new_mirror_vnic_id;
5541 };
5542 
5543 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
5544 struct hwrm_cfa_l2_filter_cfg_output {
5545         __le16  error_code;
5546         __le16  req_type;
5547         __le16  seq_id;
5548         __le16  resp_len;
5549         u8      unused_0[7];
5550         u8      valid;
5551 };
5552 
5553 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
5554 struct hwrm_cfa_l2_set_rx_mask_input {
5555         __le16  req_type;
5556         __le16  cmpl_ring;
5557         __le16  seq_id;
5558         __le16  target_id;
5559         __le64  resp_addr;
5560         __le32  vnic_id;
5561         __le32  mask;
5562         #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST               0x2UL
5563         #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST           0x4UL
5564         #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST               0x8UL
5565         #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS         0x10UL
5566         #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST           0x20UL
5567         #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY            0x40UL
5568         #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN        0x80UL
5569         #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN     0x100UL
5570         __le64  mc_tbl_addr;
5571         __le32  num_mc_entries;
5572         u8      unused_0[4];
5573         __le64  vlan_tag_tbl_addr;
5574         __le32  num_vlan_tags;
5575         u8      unused_1[4];
5576 };
5577 
5578 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
5579 struct hwrm_cfa_l2_set_rx_mask_output {
5580         __le16  error_code;
5581         __le16  req_type;
5582         __le16  seq_id;
5583         __le16  resp_len;
5584         u8      unused_0[7];
5585         u8      valid;
5586 };
5587 
5588 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
5589 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
5590         u8      code;
5591         #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN                    0x0UL
5592         #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL
5593         #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST                      CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
5594         u8      unused_0[7];
5595 };
5596 
5597 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
5598 struct hwrm_cfa_tunnel_filter_alloc_input {
5599         __le16  req_type;
5600         __le16  cmpl_ring;
5601         __le16  seq_id;
5602         __le16  target_id;
5603         __le64  resp_addr;
5604         __le32  flags;
5605         #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL
5606         __le32  enables;
5607         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID       0x1UL
5608         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR            0x2UL
5609         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN           0x4UL
5610         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR            0x8UL
5611         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE       0x10UL
5612         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE     0x20UL
5613         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR          0x40UL
5614         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE        0x80UL
5615         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI                0x100UL
5616         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID        0x200UL
5617         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID     0x400UL
5618         __le64  l2_filter_id;
5619         u8      l2_addr[6];
5620         __le16  l2_ivlan;
5621         __le32  l3_addr[4];
5622         __le32  t_l3_addr[4];
5623         u8      l3_addr_type;
5624         u8      t_l3_addr_type;
5625         u8      tunnel_type;
5626         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL
5627         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL
5628         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL
5629         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL
5630         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL
5631         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL
5632         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL
5633         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL
5634         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL
5635         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
5636         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
5637         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
5638         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5639         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL
5640         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5641         u8      tunnel_flags;
5642         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR     0x1UL
5643         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1          0x2UL
5644         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0         0x4UL
5645         __le32  vni;
5646         __le32  dst_vnic_id;
5647         __le32  mirror_vnic_id;
5648 };
5649 
5650 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
5651 struct hwrm_cfa_tunnel_filter_alloc_output {
5652         __le16  error_code;
5653         __le16  req_type;
5654         __le16  seq_id;
5655         __le16  resp_len;
5656         __le64  tunnel_filter_id;
5657         __le32  flow_id;
5658         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
5659         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
5660         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE      0x40000000UL
5661         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT    (0x0UL << 30)
5662         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT    (0x1UL << 30)
5663         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST  CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
5664         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR       0x80000000UL
5665         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX      (0x0UL << 31)
5666         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX      (0x1UL << 31)
5667         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST   CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
5668         u8      unused_0[3];
5669         u8      valid;
5670 };
5671 
5672 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
5673 struct hwrm_cfa_tunnel_filter_free_input {
5674         __le16  req_type;
5675         __le16  cmpl_ring;
5676         __le16  seq_id;
5677         __le16  target_id;
5678         __le64  resp_addr;
5679         __le64  tunnel_filter_id;
5680 };
5681 
5682 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
5683 struct hwrm_cfa_tunnel_filter_free_output {
5684         __le16  error_code;
5685         __le16  req_type;
5686         __le16  seq_id;
5687         __le16  resp_len;
5688         u8      unused_0[7];
5689         u8      valid;
5690 };
5691 
5692 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
5693 struct hwrm_vxlan_ipv4_hdr {
5694         u8      ver_hlen;
5695         #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL
5696         #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
5697         #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK      0xf0UL
5698         #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT       4
5699         u8      tos;
5700         __be16  ip_id;
5701         __be16  flags_frag_offset;
5702         u8      ttl;
5703         u8      protocol;
5704         __be32  src_ip_addr;
5705         __be32  dest_ip_addr;
5706 };
5707 
5708 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
5709 struct hwrm_vxlan_ipv6_hdr {
5710         __be32  ver_tc_flow_label;
5711         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT         0x1cUL
5712         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK        0xf0000000UL
5713         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT          0x14UL
5714         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK         0xff00000UL
5715         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT  0x0UL
5716         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL
5717         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST           VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
5718         __be16  payload_len;
5719         u8      next_hdr;
5720         u8      ttl;
5721         __be32  src_ip_addr[4];
5722         __be32  dest_ip_addr[4];
5723 };
5724 
5725 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
5726 struct hwrm_cfa_encap_data_vxlan {
5727         u8      src_mac_addr[6];
5728         __le16  unused_0;
5729         u8      dst_mac_addr[6];
5730         u8      num_vlan_tags;
5731         u8      unused_1;
5732         __be16  ovlan_tpid;
5733         __be16  ovlan_tci;
5734         __be16  ivlan_tpid;
5735         __be16  ivlan_tci;
5736         __le32  l3[10];
5737         #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL
5738         #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL
5739         #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL
5740         #define CFA_ENCAP_DATA_VXLAN_L3_LAST    CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
5741         __be16  src_port;
5742         __be16  dst_port;
5743         __be32  vni;
5744         u8      hdr_rsvd0[3];
5745         u8      hdr_rsvd1;
5746         u8      hdr_flags;
5747         u8      unused[3];
5748 };
5749 
5750 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
5751 struct hwrm_cfa_encap_record_alloc_input {
5752         __le16  req_type;
5753         __le16  cmpl_ring;
5754         __le16  seq_id;
5755         __le16  target_id;
5756         __le64  resp_addr;
5757         __le32  flags;
5758         #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL
5759         #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL     0x2UL
5760         u8      encap_type;
5761         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN        0x1UL
5762         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE        0x2UL
5763         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE        0x3UL
5764         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP         0x4UL
5765         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE       0x5UL
5766         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS         0x6UL
5767         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN         0x7UL
5768         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE        0x8UL
5769         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4     0x9UL
5770         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1     0xaUL
5771         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE     0xbUL
5772         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL
5773         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST        CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6
5774         u8      unused_0[3];
5775         __le32  encap_data[20];
5776 };
5777 
5778 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
5779 struct hwrm_cfa_encap_record_alloc_output {
5780         __le16  error_code;
5781         __le16  req_type;
5782         __le16  seq_id;
5783         __le16  resp_len;
5784         __le32  encap_record_id;
5785         u8      unused_0[3];
5786         u8      valid;
5787 };
5788 
5789 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
5790 struct hwrm_cfa_encap_record_free_input {
5791         __le16  req_type;
5792         __le16  cmpl_ring;
5793         __le16  seq_id;
5794         __le16  target_id;
5795         __le64  resp_addr;
5796         __le32  encap_record_id;
5797         u8      unused_0[4];
5798 };
5799 
5800 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
5801 struct hwrm_cfa_encap_record_free_output {
5802         __le16  error_code;
5803         __le16  req_type;
5804         __le16  seq_id;
5805         __le16  resp_len;
5806         u8      unused_0[7];
5807         u8      valid;
5808 };
5809 
5810 /* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */
5811 struct hwrm_cfa_ntuple_filter_alloc_input {
5812         __le16  req_type;
5813         __le16  cmpl_ring;
5814         __le16  seq_id;
5815         __le16  target_id;
5816         __le64  resp_addr;
5817         __le32  flags;
5818         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL
5819         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP         0x2UL
5820         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER        0x4UL
5821         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID     0x8UL
5822         __le32  enables;
5823         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID         0x1UL
5824         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE            0x2UL
5825         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE          0x4UL
5826         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR          0x8UL
5827         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE          0x10UL
5828         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR           0x20UL
5829         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK      0x40UL
5830         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR           0x80UL
5831         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK      0x100UL
5832         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL          0x200UL
5833         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT             0x400UL
5834         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK        0x800UL
5835         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT             0x1000UL
5836         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK        0x2000UL
5837         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT             0x4000UL
5838         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID     0x8000UL
5839         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID               0x10000UL
5840         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID       0x20000UL
5841         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR          0x40000UL
5842         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX     0x80000UL
5843         __le64  l2_filter_id;
5844         u8      src_macaddr[6];
5845         __be16  ethertype;
5846         u8      ip_addr_type;
5847         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
5848         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4    0x4UL
5849         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6    0x6UL
5850         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST   CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
5851         u8      ip_protocol;
5852         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
5853         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP     0x6UL
5854         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP     0x11UL
5855         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
5856         __le16  dst_id;
5857         __le16  mirror_vnic_id;
5858         u8      tunnel_type;
5859         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL
5860         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL
5861         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL
5862         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL
5863         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL
5864         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL
5865         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL
5866         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL
5867         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL
5868         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
5869         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
5870         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
5871         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5872         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL
5873         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5874         u8      pri_hint;
5875         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
5876         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE     0x1UL
5877         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW     0x2UL
5878         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST   0x3UL
5879         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST    0x4UL
5880         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST     CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST
5881         __be32  src_ipaddr[4];
5882         __be32  src_ipaddr_mask[4];
5883         __be32  dst_ipaddr[4];
5884         __be32  dst_ipaddr_mask[4];
5885         __be16  src_port;
5886         __be16  src_port_mask;
5887         __be16  dst_port;
5888         __be16  dst_port_mask;
5889         __le64  ntuple_filter_id_hint;
5890         __le16  rfs_ring_tbl_idx;
5891         u8      unused_0[6];
5892 };
5893 
5894 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
5895 struct hwrm_cfa_ntuple_filter_alloc_output {
5896         __le16  error_code;
5897         __le16  req_type;
5898         __le16  seq_id;
5899         __le16  resp_len;
5900         __le64  ntuple_filter_id;
5901         __le32  flow_id;
5902         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
5903         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
5904         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE      0x40000000UL
5905         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT    (0x0UL << 30)
5906         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT    (0x1UL << 30)
5907         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST  CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
5908         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR       0x80000000UL
5909         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX      (0x0UL << 31)
5910         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX      (0x1UL << 31)
5911         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST   CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
5912         u8      unused_0[3];
5913         u8      valid;
5914 };
5915 
5916 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
5917 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
5918         u8      code;
5919         #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN                   0x0UL
5920         #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL
5921         #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST                     CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
5922         u8      unused_0[7];
5923 };
5924 
5925 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
5926 struct hwrm_cfa_ntuple_filter_free_input {
5927         __le16  req_type;
5928         __le16  cmpl_ring;
5929         __le16  seq_id;
5930         __le16  target_id;
5931         __le64  resp_addr;
5932         __le64  ntuple_filter_id;
5933 };
5934 
5935 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
5936 struct hwrm_cfa_ntuple_filter_free_output {
5937         __le16  error_code;
5938         __le16  req_type;
5939         __le16  seq_id;
5940         __le16  resp_len;
5941         u8      unused_0[7];
5942         u8      valid;
5943 };
5944 
5945 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
5946 struct hwrm_cfa_ntuple_filter_cfg_input {
5947         __le16  req_type;
5948         __le16  cmpl_ring;
5949         __le16  seq_id;
5950         __le16  target_id;
5951         __le64  resp_addr;
5952         __le32  enables;
5953         #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID                0x1UL
5954         #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID        0x2UL
5955         #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID     0x4UL
5956         __le32  flags;
5957         #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID     0x1UL
5958         __le64  ntuple_filter_id;
5959         __le32  new_dst_id;
5960         __le32  new_mirror_vnic_id;
5961         __le16  new_meter_instance_id;
5962         #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
5963         #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST   CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
5964         u8      unused_1[6];
5965 };
5966 
5967 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
5968 struct hwrm_cfa_ntuple_filter_cfg_output {
5969         __le16  error_code;
5970         __le16  req_type;
5971         __le16  seq_id;
5972         __le16  resp_len;
5973         u8      unused_0[7];
5974         u8      valid;
5975 };
5976 
5977 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
5978 struct hwrm_cfa_decap_filter_alloc_input {
5979         __le16  req_type;
5980         __le16  cmpl_ring;
5981         __le16  seq_id;
5982         __le16  target_id;
5983         __le64  resp_addr;
5984         __le32  flags;
5985         #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL     0x1UL
5986         __le32  enables;
5987         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE        0x1UL
5988         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID          0x2UL
5989         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR        0x4UL
5990         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR        0x8UL
5991         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID          0x10UL
5992         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID          0x20UL
5993         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID        0x40UL
5994         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID        0x80UL
5995         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE          0x100UL
5996         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR         0x200UL
5997         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR         0x400UL
5998         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE        0x800UL
5999         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL        0x1000UL
6000         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT           0x2000UL
6001         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT           0x4000UL
6002         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID             0x8000UL
6003         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID     0x10000UL
6004         __be32  tunnel_id;
6005         u8      tunnel_type;
6006         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL
6007         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL
6008         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL
6009         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL
6010         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL
6011         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL
6012         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL
6013         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL
6014         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL
6015         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
6016         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
6017         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
6018         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6019         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL
6020         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6021         u8      unused_0;
6022         __le16  unused_1;
6023         u8      src_macaddr[6];
6024         u8      unused_2[2];
6025         u8      dst_macaddr[6];
6026         __be16  ovlan_vid;
6027         __be16  ivlan_vid;
6028         __be16  t_ovlan_vid;
6029         __be16  t_ivlan_vid;
6030         __be16  ethertype;
6031         u8      ip_addr_type;
6032         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
6033         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4    0x4UL
6034         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6    0x6UL
6035         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST   CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
6036         u8      ip_protocol;
6037         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
6038         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP     0x6UL
6039         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP     0x11UL
6040         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
6041         __le16  unused_3;
6042         __le32  unused_4;
6043         __be32  src_ipaddr[4];
6044         __be32  dst_ipaddr[4];
6045         __be16  src_port;
6046         __be16  dst_port;
6047         __le16  dst_id;
6048         __le16  l2_ctxt_ref_id;
6049 };
6050 
6051 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
6052 struct hwrm_cfa_decap_filter_alloc_output {
6053         __le16  error_code;
6054         __le16  req_type;
6055         __le16  seq_id;
6056         __le16  resp_len;
6057         __le32  decap_filter_id;
6058         u8      unused_0[3];
6059         u8      valid;
6060 };
6061 
6062 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
6063 struct hwrm_cfa_decap_filter_free_input {
6064         __le16  req_type;
6065         __le16  cmpl_ring;
6066         __le16  seq_id;
6067         __le16  target_id;
6068         __le64  resp_addr;
6069         __le32  decap_filter_id;
6070         u8      unused_0[4];
6071 };
6072 
6073 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
6074 struct hwrm_cfa_decap_filter_free_output {
6075         __le16  error_code;
6076         __le16  req_type;
6077         __le16  seq_id;
6078         __le16  resp_len;
6079         u8      unused_0[7];
6080         u8      valid;
6081 };
6082 
6083 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
6084 struct hwrm_cfa_flow_alloc_input {
6085         __le16  req_type;
6086         __le16  cmpl_ring;
6087         __le16  seq_id;
6088         __le16  target_id;
6089         __le64  resp_addr;
6090         __le16  flags;
6091         #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL                 0x1UL
6092         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK          0x6UL
6093         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT           1
6094         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE            (0x0UL << 1)
6095         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE             (0x1UL << 1)
6096         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO             (0x2UL << 1)
6097         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST           CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
6098         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK          0x38UL
6099         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT           3
6100         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2              (0x0UL << 3)
6101         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4            (0x1UL << 3)
6102         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6            (0x2UL << 3)
6103         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST           CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
6104         #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX                0x40UL
6105         #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX                0x80UL
6106         #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI     0x100UL
6107         #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN      0x200UL
6108         __le16  src_fid;
6109         __le32  tunnel_handle;
6110         __le16  action_flags;
6111         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD                       0x1UL
6112         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE                   0x2UL
6113         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP                      0x4UL
6114         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER                     0x8UL
6115         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL                    0x10UL
6116         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC                   0x20UL
6117         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST                  0x40UL
6118         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS          0x80UL
6119         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE         0x100UL
6120         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT             0x200UL
6121         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP                 0x400UL
6122         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED        0x800UL
6123         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT                  0x1000UL
6124         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC     0x2000UL
6125         __le16  dst_fid;
6126         __be16  l2_rewrite_vlan_tpid;
6127         __be16  l2_rewrite_vlan_tci;
6128         __le16  act_meter_id;
6129         __le16  ref_flow_handle;
6130         __be16  ethertype;
6131         __be16  outer_vlan_tci;
6132         __be16  dmac[3];
6133         __be16  inner_vlan_tci;
6134         __be16  smac[3];
6135         u8      ip_dst_mask_len;
6136         u8      ip_src_mask_len;
6137         __be32  ip_dst[4];
6138         __be32  ip_src[4];
6139         __be16  l4_src_port;
6140         __be16  l4_src_port_mask;
6141         __be16  l4_dst_port;
6142         __be16  l4_dst_port_mask;
6143         __be32  nat_ip_address[4];
6144         __be16  l2_rewrite_dmac[3];
6145         __be16  nat_port;
6146         __be16  l2_rewrite_smac[3];
6147         u8      ip_proto;
6148         u8      tunnel_type;
6149         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL
6150         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL
6151         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL
6152         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL
6153         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL
6154         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL
6155         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL
6156         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL
6157         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL
6158         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
6159         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
6160         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
6161         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6162         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL
6163         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6164 };
6165 
6166 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
6167 struct hwrm_cfa_flow_alloc_output {
6168         __le16  error_code;
6169         __le16  req_type;
6170         __le16  seq_id;
6171         __le16  resp_len;
6172         __le16  flow_handle;
6173         u8      unused_0[2];
6174         __le32  flow_id;
6175         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
6176         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
6177         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE      0x40000000UL
6178         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT    (0x0UL << 30)
6179         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT    (0x1UL << 30)
6180         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST  CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT
6181         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR       0x80000000UL
6182         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX      (0x0UL << 31)
6183         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX      (0x1UL << 31)
6184         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST   CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX
6185         __le64  ext_flow_handle;
6186         __le32  flow_counter_id;
6187         u8      unused_1[3];
6188         u8      valid;
6189 };
6190 
6191 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
6192 struct hwrm_cfa_flow_alloc_cmd_err {
6193         u8      code;
6194         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN         0x0UL
6195         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL
6196         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD   0x2UL
6197         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER    0x3UL
6198         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM  0x4UL
6199         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION  0x5UL
6200         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS      0x6UL
6201         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB    0x7UL
6202         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST           CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
6203         u8      unused_0[7];
6204 };
6205 
6206 /* hwrm_cfa_flow_free_input (size:256b/32B) */
6207 struct hwrm_cfa_flow_free_input {
6208         __le16  req_type;
6209         __le16  cmpl_ring;
6210         __le16  seq_id;
6211         __le16  target_id;
6212         __le64  resp_addr;
6213         __le16  flow_handle;
6214         __le16  unused_0;
6215         __le32  flow_counter_id;
6216         __le64  ext_flow_handle;
6217 };
6218 
6219 /* hwrm_cfa_flow_free_output (size:256b/32B) */
6220 struct hwrm_cfa_flow_free_output {
6221         __le16  error_code;
6222         __le16  req_type;
6223         __le16  seq_id;
6224         __le16  resp_len;
6225         __le64  packet;
6226         __le64  byte;
6227         u8      unused_0[7];
6228         u8      valid;
6229 };
6230 
6231 /* hwrm_cfa_flow_info_input (size:256b/32B) */
6232 struct hwrm_cfa_flow_info_input {
6233         __le16  req_type;
6234         __le16  cmpl_ring;
6235         __le16  seq_id;
6236         __le16  target_id;
6237         __le64  resp_addr;
6238         __le16  flow_handle;
6239         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK       0xfffUL
6240         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT        0
6241         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT        0x1000UL
6242         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT     0x2000UL
6243         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT     0x4000UL
6244         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX         0x8000UL
6245         u8      unused_0[6];
6246         __le64  ext_flow_handle;
6247 };
6248 
6249 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
6250 struct hwrm_cfa_flow_info_output {
6251         __le16  error_code;
6252         __le16  req_type;
6253         __le16  seq_id;
6254         __le16  resp_len;
6255         u8      flags;
6256         #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX     0x1UL
6257         #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX     0x2UL
6258         u8      profile;
6259         __le16  src_fid;
6260         __le16  dst_fid;
6261         __le16  l2_ctxt_id;
6262         __le64  em_info;
6263         __le64  tcam_info;
6264         __le64  vfp_tcam_info;
6265         __le16  ar_id;
6266         __le16  flow_handle;
6267         __le32  tunnel_handle;
6268         __le16  flow_timer;
6269         u8      unused_0[6];
6270         __le32  flow_key_data[130];
6271         __le32  flow_action_info[30];
6272         u8      unused_1[7];
6273         u8      valid;
6274 };
6275 
6276 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
6277 struct hwrm_cfa_flow_stats_input {
6278         __le16  req_type;
6279         __le16  cmpl_ring;
6280         __le16  seq_id;
6281         __le16  target_id;
6282         __le64  resp_addr;
6283         __le16  num_flows;
6284         __le16  flow_handle_0;
6285         __le16  flow_handle_1;
6286         __le16  flow_handle_2;
6287         __le16  flow_handle_3;
6288         __le16  flow_handle_4;
6289         __le16  flow_handle_5;
6290         __le16  flow_handle_6;
6291         __le16  flow_handle_7;
6292         __le16  flow_handle_8;
6293         __le16  flow_handle_9;
6294         u8      unused_0[2];
6295         __le32  flow_id_0;
6296         __le32  flow_id_1;
6297         __le32  flow_id_2;
6298         __le32  flow_id_3;
6299         __le32  flow_id_4;
6300         __le32  flow_id_5;
6301         __le32  flow_id_6;
6302         __le32  flow_id_7;
6303         __le32  flow_id_8;
6304         __le32  flow_id_9;
6305 };
6306 
6307 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
6308 struct hwrm_cfa_flow_stats_output {
6309         __le16  error_code;
6310         __le16  req_type;
6311         __le16  seq_id;
6312         __le16  resp_len;
6313         __le64  packet_0;
6314         __le64  packet_1;
6315         __le64  packet_2;
6316         __le64  packet_3;
6317         __le64  packet_4;
6318         __le64  packet_5;
6319         __le64  packet_6;
6320         __le64  packet_7;
6321         __le64  packet_8;
6322         __le64  packet_9;
6323         __le64  byte_0;
6324         __le64  byte_1;
6325         __le64  byte_2;
6326         __le64  byte_3;
6327         __le64  byte_4;
6328         __le64  byte_5;
6329         __le64  byte_6;
6330         __le64  byte_7;
6331         __le64  byte_8;
6332         __le64  byte_9;
6333         u8      unused_0[7];
6334         u8      valid;
6335 };
6336 
6337 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
6338 struct hwrm_cfa_vfr_alloc_input {
6339         __le16  req_type;
6340         __le16  cmpl_ring;
6341         __le16  seq_id;
6342         __le16  target_id;
6343         __le64  resp_addr;
6344         __le16  vf_id;
6345         __le16  reserved;
6346         u8      unused_0[4];
6347         char    vfr_name[32];
6348 };
6349 
6350 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
6351 struct hwrm_cfa_vfr_alloc_output {
6352         __le16  error_code;
6353         __le16  req_type;
6354         __le16  seq_id;
6355         __le16  resp_len;
6356         __le16  rx_cfa_code;
6357         __le16  tx_cfa_action;
6358         u8      unused_0[3];
6359         u8      valid;
6360 };
6361 
6362 /* hwrm_cfa_vfr_free_input (size:384b/48B) */
6363 struct hwrm_cfa_vfr_free_input {
6364         __le16  req_type;
6365         __le16  cmpl_ring;
6366         __le16  seq_id;
6367         __le16  target_id;
6368         __le64  resp_addr;
6369         char    vfr_name[32];
6370 };
6371 
6372 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
6373 struct hwrm_cfa_vfr_free_output {
6374         __le16  error_code;
6375         __le16  req_type;
6376         __le16  seq_id;
6377         __le16  resp_len;
6378         u8      unused_0[7];
6379         u8      valid;
6380 };
6381 
6382 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
6383 struct hwrm_cfa_eem_qcaps_input {
6384         __le16  req_type;
6385         __le16  cmpl_ring;
6386         __le16  seq_id;
6387         __le16  target_id;
6388         __le64  resp_addr;
6389         __le32  flags;
6390         #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX               0x1UL
6391         #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX               0x2UL
6392         #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD     0x4UL
6393         __le32  unused_0;
6394 };
6395 
6396 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
6397 struct hwrm_cfa_eem_qcaps_output {
6398         __le16  error_code;
6399         __le16  req_type;
6400         __le16  seq_id;
6401         __le16  resp_len;
6402         __le32  flags;
6403         #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX                                         0x1UL
6404         #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX                                         0x2UL
6405         #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED              0x4UL
6406         #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED     0x8UL
6407         __le32  unused_0;
6408         __le32  supported;
6409         #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE                       0x1UL
6410         #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE                       0x2UL
6411         #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE            0x4UL
6412         #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE     0x8UL
6413         #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE                        0x10UL
6414         __le32  max_entries_supported;
6415         __le16  key_entry_size;
6416         __le16  record_entry_size;
6417         __le16  efc_entry_size;
6418         __le16  fid_entry_size;
6419         u8      unused_1[7];
6420         u8      valid;
6421 };
6422 
6423 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
6424 struct hwrm_cfa_eem_cfg_input {
6425         __le16  req_type;
6426         __le16  cmpl_ring;
6427         __le16  seq_id;
6428         __le16  target_id;
6429         __le64  resp_addr;
6430         __le32  flags;
6431         #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX               0x1UL
6432         #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX               0x2UL
6433         #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD     0x4UL
6434         #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF          0x8UL
6435         __le16  group_id;
6436         __le16  unused_0;
6437         __le32  num_entries;
6438         __le32  unused_1;
6439         __le16  key0_ctx_id;
6440         __le16  key1_ctx_id;
6441         __le16  record_ctx_id;
6442         __le16  efc_ctx_id;
6443         __le16  fid_ctx_id;
6444         __le16  unused_2;
6445         __le32  unused_3;
6446 };
6447 
6448 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
6449 struct hwrm_cfa_eem_cfg_output {
6450         __le16  error_code;
6451         __le16  req_type;
6452         __le16  seq_id;
6453         __le16  resp_len;
6454         u8      unused_0[7];
6455         u8      valid;
6456 };
6457 
6458 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
6459 struct hwrm_cfa_eem_qcfg_input {
6460         __le16  req_type;
6461         __le16  cmpl_ring;
6462         __le16  seq_id;
6463         __le16  target_id;
6464         __le64  resp_addr;
6465         __le32  flags;
6466         #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX     0x1UL
6467         #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX     0x2UL
6468         __le32  unused_0;
6469 };
6470 
6471 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
6472 struct hwrm_cfa_eem_qcfg_output {
6473         __le16  error_code;
6474         __le16  req_type;
6475         __le16  seq_id;
6476         __le16  resp_len;
6477         __le32  flags;
6478         #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX               0x1UL
6479         #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX               0x2UL
6480         #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD     0x4UL
6481         __le32  num_entries;
6482         __le16  key0_ctx_id;
6483         __le16  key1_ctx_id;
6484         __le16  record_ctx_id;
6485         __le16  efc_ctx_id;
6486         __le16  fid_ctx_id;
6487         u8      unused_2[5];
6488         u8      valid;
6489 };
6490 
6491 /* hwrm_cfa_eem_op_input (size:192b/24B) */
6492 struct hwrm_cfa_eem_op_input {
6493         __le16  req_type;
6494         __le16  cmpl_ring;
6495         __le16  seq_id;
6496         __le16  target_id;
6497         __le64  resp_addr;
6498         __le32  flags;
6499         #define CFA_EEM_OP_REQ_FLAGS_PATH_TX     0x1UL
6500         #define CFA_EEM_OP_REQ_FLAGS_PATH_RX     0x2UL
6501         __le16  unused_0;
6502         __le16  op;
6503         #define CFA_EEM_OP_REQ_OP_RESERVED    0x0UL
6504         #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL
6505         #define CFA_EEM_OP_REQ_OP_EEM_ENABLE  0x2UL
6506         #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL
6507         #define CFA_EEM_OP_REQ_OP_LAST       CFA_EEM_OP_REQ_OP_EEM_CLEANUP
6508 };
6509 
6510 /* hwrm_cfa_eem_op_output (size:128b/16B) */
6511 struct hwrm_cfa_eem_op_output {
6512         __le16  error_code;
6513         __le16  req_type;
6514         __le16  seq_id;
6515         __le16  resp_len;
6516         u8      unused_0[7];
6517         u8      valid;
6518 };
6519 
6520 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
6521 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
6522         __le16  req_type;
6523         __le16  cmpl_ring;
6524         __le16  seq_id;
6525         __le16  target_id;
6526         __le64  resp_addr;
6527         __le32  unused_0[4];
6528 };
6529 
6530 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
6531 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
6532         __le16  error_code;
6533         __le16  req_type;
6534         __le16  seq_id;
6535         __le16  resp_len;
6536         __le32  flags;
6537         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED              0x1UL
6538         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED              0x2UL
6539         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED           0x4UL
6540         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED              0x8UL
6541         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED       0x10UL
6542         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED                 0x20UL
6543         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED                 0x40UL
6544         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED          0x80UL
6545         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED            0x100UL
6546         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED               0x200UL
6547         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED                         0x400UL
6548         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED     0x800UL
6549         u8      unused_0[3];
6550         u8      valid;
6551 };
6552 
6553 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
6554 struct hwrm_tunnel_dst_port_query_input {
6555         __le16  req_type;
6556         __le16  cmpl_ring;
6557         __le16  seq_id;
6558         __le16  target_id;
6559         __le64  resp_addr;
6560         u8      tunnel_type;
6561         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN        0x1UL
6562         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE       0x5UL
6563         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
6564         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
6565         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
6566         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6567         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST        TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
6568         u8      unused_0[7];
6569 };
6570 
6571 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
6572 struct hwrm_tunnel_dst_port_query_output {
6573         __le16  error_code;
6574         __le16  req_type;
6575         __le16  seq_id;
6576         __le16  resp_len;
6577         __le16  tunnel_dst_port_id;
6578         __be16  tunnel_dst_port_val;
6579         u8      unused_0[3];
6580         u8      valid;
6581 };
6582 
6583 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
6584 struct hwrm_tunnel_dst_port_alloc_input {
6585         __le16  req_type;
6586         __le16  cmpl_ring;
6587         __le16  seq_id;
6588         __le16  target_id;
6589         __le64  resp_addr;
6590         u8      tunnel_type;
6591         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL
6592         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL
6593         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
6594         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
6595         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
6596         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6597         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST        TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
6598         u8      unused_0;
6599         __be16  tunnel_dst_port_val;
6600         u8      unused_1[4];
6601 };
6602 
6603 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
6604 struct hwrm_tunnel_dst_port_alloc_output {
6605         __le16  error_code;
6606         __le16  req_type;
6607         __le16  seq_id;
6608         __le16  resp_len;
6609         __le16  tunnel_dst_port_id;
6610         u8      unused_0[5];
6611         u8      valid;
6612 };
6613 
6614 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
6615 struct hwrm_tunnel_dst_port_free_input {
6616         __le16  req_type;
6617         __le16  cmpl_ring;
6618         __le16  seq_id;
6619         __le16  target_id;
6620         __le64  resp_addr;
6621         u8      tunnel_type;
6622         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN        0x1UL
6623         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE       0x5UL
6624         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
6625         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
6626         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
6627         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6628         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST        TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
6629         u8      unused_0;
6630         __le16  tunnel_dst_port_id;
6631         u8      unused_1[4];
6632 };
6633 
6634 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
6635 struct hwrm_tunnel_dst_port_free_output {
6636         __le16  error_code;
6637         __le16  req_type;
6638         __le16  seq_id;
6639         __le16  resp_len;
6640         u8      unused_1[7];
6641         u8      valid;
6642 };
6643 
6644 /* ctx_hw_stats (size:1280b/160B) */
6645 struct ctx_hw_stats {
6646         __le64  rx_ucast_pkts;
6647         __le64  rx_mcast_pkts;
6648         __le64  rx_bcast_pkts;
6649         __le64  rx_discard_pkts;
6650         __le64  rx_drop_pkts;
6651         __le64  rx_ucast_bytes;
6652         __le64  rx_mcast_bytes;
6653         __le64  rx_bcast_bytes;
6654         __le64  tx_ucast_pkts;
6655         __le64  tx_mcast_pkts;
6656         __le64  tx_bcast_pkts;
6657         __le64  tx_discard_pkts;
6658         __le64  tx_drop_pkts;
6659         __le64  tx_ucast_bytes;
6660         __le64  tx_mcast_bytes;
6661         __le64  tx_bcast_bytes;
6662         __le64  tpa_pkts;
6663         __le64  tpa_bytes;
6664         __le64  tpa_events;
6665         __le64  tpa_aborts;
6666 };
6667 
6668 /* ctx_hw_stats_ext (size:1344b/168B) */
6669 struct ctx_hw_stats_ext {
6670         __le64  rx_ucast_pkts;
6671         __le64  rx_mcast_pkts;
6672         __le64  rx_bcast_pkts;
6673         __le64  rx_discard_pkts;
6674         __le64  rx_drop_pkts;
6675         __le64  rx_ucast_bytes;
6676         __le64  rx_mcast_bytes;
6677         __le64  rx_bcast_bytes;
6678         __le64  tx_ucast_pkts;
6679         __le64  tx_mcast_pkts;
6680         __le64  tx_bcast_pkts;
6681         __le64  tx_discard_pkts;
6682         __le64  tx_drop_pkts;
6683         __le64  tx_ucast_bytes;
6684         __le64  tx_mcast_bytes;
6685         __le64  tx_bcast_bytes;
6686         __le64  rx_tpa_eligible_pkt;
6687         __le64  rx_tpa_eligible_bytes;
6688         __le64  rx_tpa_pkt;
6689         __le64  rx_tpa_bytes;
6690         __le64  rx_tpa_errors;
6691 };
6692 
6693 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
6694 struct hwrm_stat_ctx_alloc_input {
6695         __le16  req_type;
6696         __le16  cmpl_ring;
6697         __le16  seq_id;
6698         __le16  target_id;
6699         __le64  resp_addr;
6700         __le64  stats_dma_addr;
6701         __le32  update_period_ms;
6702         u8      stat_ctx_flags;
6703         #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE     0x1UL
6704         u8      unused_0;
6705         __le16  stats_dma_length;
6706 };
6707 
6708 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
6709 struct hwrm_stat_ctx_alloc_output {
6710         __le16  error_code;
6711         __le16  req_type;
6712         __le16  seq_id;
6713         __le16  resp_len;
6714         __le32  stat_ctx_id;
6715         u8      unused_0[3];
6716         u8      valid;
6717 };
6718 
6719 /* hwrm_stat_ctx_free_input (size:192b/24B) */
6720 struct hwrm_stat_ctx_free_input {
6721         __le16  req_type;
6722         __le16  cmpl_ring;
6723         __le16  seq_id;
6724         __le16  target_id;
6725         __le64  resp_addr;
6726         __le32  stat_ctx_id;
6727         u8      unused_0[4];
6728 };
6729 
6730 /* hwrm_stat_ctx_free_output (size:128b/16B) */
6731 struct hwrm_stat_ctx_free_output {
6732         __le16  error_code;
6733         __le16  req_type;
6734         __le16  seq_id;
6735         __le16  resp_len;
6736         __le32  stat_ctx_id;
6737         u8      unused_0[3];
6738         u8      valid;
6739 };
6740 
6741 /* hwrm_stat_ctx_query_input (size:192b/24B) */
6742 struct hwrm_stat_ctx_query_input {
6743         __le16  req_type;
6744         __le16  cmpl_ring;
6745         __le16  seq_id;
6746         __le16  target_id;
6747         __le64  resp_addr;
6748         __le32  stat_ctx_id;
6749         u8      unused_0[4];
6750 };
6751 
6752 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
6753 struct hwrm_stat_ctx_query_output {
6754         __le16  error_code;
6755         __le16  req_type;
6756         __le16  seq_id;
6757         __le16  resp_len;
6758         __le64  tx_ucast_pkts;
6759         __le64  tx_mcast_pkts;
6760         __le64  tx_bcast_pkts;
6761         __le64  tx_err_pkts;
6762         __le64  tx_drop_pkts;
6763         __le64  tx_ucast_bytes;
6764         __le64  tx_mcast_bytes;
6765         __le64  tx_bcast_bytes;
6766         __le64  rx_ucast_pkts;
6767         __le64  rx_mcast_pkts;
6768         __le64  rx_bcast_pkts;
6769         __le64  rx_err_pkts;
6770         __le64  rx_drop_pkts;
6771         __le64  rx_ucast_bytes;
6772         __le64  rx_mcast_bytes;
6773         __le64  rx_bcast_bytes;
6774         __le64  rx_agg_pkts;
6775         __le64  rx_agg_bytes;
6776         __le64  rx_agg_events;
6777         __le64  rx_agg_aborts;
6778         u8      unused_0[7];
6779         u8      valid;
6780 };
6781 
6782 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
6783 struct hwrm_stat_ctx_clr_stats_input {
6784         __le16  req_type;
6785         __le16  cmpl_ring;
6786         __le16  seq_id;
6787         __le16  target_id;
6788         __le64  resp_addr;
6789         __le32  stat_ctx_id;
6790         u8      unused_0[4];
6791 };
6792 
6793 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
6794 struct hwrm_stat_ctx_clr_stats_output {
6795         __le16  error_code;
6796         __le16  req_type;
6797         __le16  seq_id;
6798         __le16  resp_len;
6799         u8      unused_0[7];
6800         u8      valid;
6801 };
6802 
6803 /* hwrm_pcie_qstats_input (size:256b/32B) */
6804 struct hwrm_pcie_qstats_input {
6805         __le16  req_type;
6806         __le16  cmpl_ring;
6807         __le16  seq_id;
6808         __le16  target_id;
6809         __le64  resp_addr;
6810         __le16  pcie_stat_size;
6811         u8      unused_0[6];
6812         __le64  pcie_stat_host_addr;
6813 };
6814 
6815 /* hwrm_pcie_qstats_output (size:128b/16B) */
6816 struct hwrm_pcie_qstats_output {
6817         __le16  error_code;
6818         __le16  req_type;
6819         __le16  seq_id;
6820         __le16  resp_len;
6821         __le16  pcie_stat_size;
6822         u8      unused_0[5];
6823         u8      valid;
6824 };
6825 
6826 /* pcie_ctx_hw_stats (size:768b/96B) */
6827 struct pcie_ctx_hw_stats {
6828         __le64  pcie_pl_signal_integrity;
6829         __le64  pcie_dl_signal_integrity;
6830         __le64  pcie_tl_signal_integrity;
6831         __le64  pcie_link_integrity;
6832         __le64  pcie_tx_traffic_rate;
6833         __le64  pcie_rx_traffic_rate;
6834         __le64  pcie_tx_dllp_statistics;
6835         __le64  pcie_rx_dllp_statistics;
6836         __le64  pcie_equalization_time;
6837         __le32  pcie_ltssm_histogram[4];
6838         __le64  pcie_recovery_histogram;
6839 };
6840 
6841 /* hwrm_fw_reset_input (size:192b/24B) */
6842 struct hwrm_fw_reset_input {
6843         __le16  req_type;
6844         __le16  cmpl_ring;
6845         __le16  seq_id;
6846         __le16  target_id;
6847         __le64  resp_addr;
6848         u8      embedded_proc_type;
6849         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT                  0x0UL
6850         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT                  0x1UL
6851         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL               0x2UL
6852         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE                  0x3UL
6853         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST                  0x4UL
6854         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP                    0x5UL
6855         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP                  0x6UL
6856         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT  0x7UL
6857         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL
6858         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST                 FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION
6859         u8      selfrst_status;
6860         #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE      0x0UL
6861         #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP      0x1UL
6862         #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST   0x2UL
6863         #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
6864         #define FW_RESET_REQ_SELFRST_STATUS_LAST            FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
6865         u8      host_idx;
6866         u8      flags;
6867         #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL     0x1UL
6868         u8      unused_0[4];
6869 };
6870 
6871 /* hwrm_fw_reset_output (size:128b/16B) */
6872 struct hwrm_fw_reset_output {
6873         __le16  error_code;
6874         __le16  req_type;
6875         __le16  seq_id;
6876         __le16  resp_len;
6877         u8      selfrst_status;
6878         #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE      0x0UL
6879         #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP      0x1UL
6880         #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST   0x2UL
6881         #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
6882         #define FW_RESET_RESP_SELFRST_STATUS_LAST            FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE
6883         u8      unused_0[6];
6884         u8      valid;
6885 };
6886 
6887 /* hwrm_fw_qstatus_input (size:192b/24B) */
6888 struct hwrm_fw_qstatus_input {
6889         __le16  req_type;
6890         __le16  cmpl_ring;
6891         __le16  seq_id;
6892         __le16  target_id;
6893         __le64  resp_addr;
6894         u8      embedded_proc_type;
6895         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT    0x0UL
6896         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT    0x1UL
6897         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
6898         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE    0x3UL
6899         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST    0x4UL
6900         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP      0x5UL
6901         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP    0x6UL
6902         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST   FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP
6903         u8      unused_0[7];
6904 };
6905 
6906 /* hwrm_fw_qstatus_output (size:128b/16B) */
6907 struct hwrm_fw_qstatus_output {
6908         __le16  error_code;
6909         __le16  req_type;
6910         __le16  seq_id;
6911         __le16  resp_len;
6912         u8      selfrst_status;
6913         #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE    0x0UL
6914         #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP    0x1UL
6915         #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
6916         #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER   0x3UL
6917         #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST          FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER
6918         u8      unused_0[6];
6919         u8      valid;
6920 };
6921 
6922 /* hwrm_fw_set_time_input (size:256b/32B) */
6923 struct hwrm_fw_set_time_input {
6924         __le16  req_type;
6925         __le16  cmpl_ring;
6926         __le16  seq_id;
6927         __le16  target_id;
6928         __le64  resp_addr;
6929         __le16  year;
6930         #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL
6931         #define FW_SET_TIME_REQ_YEAR_LAST   FW_SET_TIME_REQ_YEAR_UNKNOWN
6932         u8      month;
6933         u8      day;
6934         u8      hour;
6935         u8      minute;
6936         u8      second;
6937         u8      unused_0;
6938         __le16  millisecond;
6939         __le16  zone;
6940         #define FW_SET_TIME_REQ_ZONE_UTC     0
6941         #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535
6942         #define FW_SET_TIME_REQ_ZONE_LAST   FW_SET_TIME_REQ_ZONE_UNKNOWN
6943         u8      unused_1[4];
6944 };
6945 
6946 /* hwrm_fw_set_time_output (size:128b/16B) */
6947 struct hwrm_fw_set_time_output {
6948         __le16  error_code;
6949         __le16  req_type;
6950         __le16  seq_id;
6951         __le16  resp_len;
6952         u8      unused_0[7];
6953         u8      valid;
6954 };
6955 
6956 /* hwrm_struct_hdr (size:128b/16B) */
6957 struct hwrm_struct_hdr {
6958         __le16  struct_id;
6959         #define STRUCT_HDR_STRUCT_ID_LLDP_CFG           0x41bUL
6960         #define STRUCT_HDR_STRUCT_ID_DCBX_ETS           0x41dUL
6961         #define STRUCT_HDR_STRUCT_ID_DCBX_PFC           0x41fUL
6962         #define STRUCT_HDR_STRUCT_ID_DCBX_APP           0x421UL
6963         #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
6964         #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC       0x424UL
6965         #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE        0x426UL
6966         #define STRUCT_HDR_STRUCT_ID_POWER_BKUP         0x427UL
6967         #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE         0x1UL
6968         #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION   0xaUL
6969         #define STRUCT_HDR_STRUCT_ID_RSS_V2             0x64UL
6970         #define STRUCT_HDR_STRUCT_ID_LAST              STRUCT_HDR_STRUCT_ID_RSS_V2
6971         __le16  len;
6972         u8      version;
6973         u8      count;
6974         __le16  subtype;
6975         __le16  next_offset;
6976         #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
6977         u8      unused_0[6];
6978 };
6979 
6980 /* hwrm_struct_data_dcbx_app (size:64b/8B) */
6981 struct hwrm_struct_data_dcbx_app {
6982         __be16  protocol_id;
6983         u8      protocol_selector;
6984         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE   0x1UL
6985         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT     0x2UL
6986         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT     0x3UL
6987         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
6988         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST        STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT
6989         u8      priority;
6990         u8      valid;
6991         u8      unused_0[3];
6992 };
6993 
6994 /* hwrm_fw_set_structured_data_input (size:256b/32B) */
6995 struct hwrm_fw_set_structured_data_input {
6996         __le16  req_type;
6997         __le16  cmpl_ring;
6998         __le16  seq_id;
6999         __le16  target_id;
7000         __le64  resp_addr;
7001         __le64  src_data_addr;
7002         __le16  data_len;
7003         u8      hdr_cnt;
7004         u8      unused_0[5];
7005 };
7006 
7007 /* hwrm_fw_set_structured_data_output (size:128b/16B) */
7008 struct hwrm_fw_set_structured_data_output {
7009         __le16  error_code;
7010         __le16  req_type;
7011         __le16  seq_id;
7012         __le16  resp_len;
7013         u8      unused_0[7];
7014         u8      valid;
7015 };
7016 
7017 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */
7018 struct hwrm_fw_set_structured_data_cmd_err {
7019         u8      code;
7020         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN     0x0UL
7021         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL
7022         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT     0x2UL
7023         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID      0x3UL
7024         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST       FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
7025         u8      unused_0[7];
7026 };
7027 
7028 /* hwrm_fw_get_structured_data_input (size:256b/32B) */
7029 struct hwrm_fw_get_structured_data_input {
7030         __le16  req_type;
7031         __le16  cmpl_ring;
7032         __le16  seq_id;
7033         __le16  target_id;
7034         __le64  resp_addr;
7035         __le64  dest_data_addr;
7036         __le16  data_len;
7037         __le16  structure_id;
7038         __le16  subtype;
7039         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED                  0x0UL
7040         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL                     0xffffUL
7041         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN       0x100UL
7042         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER        0x101UL
7043         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL
7044         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN          0x200UL
7045         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER           0x201UL
7046         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL    0x202UL
7047         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL        0x300UL
7048         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST                   FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL
7049         u8      count;
7050         u8      unused_0;
7051 };
7052 
7053 /* hwrm_fw_get_structured_data_output (size:128b/16B) */
7054 struct hwrm_fw_get_structured_data_output {
7055         __le16  error_code;
7056         __le16  req_type;
7057         __le16  seq_id;
7058         __le16  resp_len;
7059         u8      hdr_cnt;
7060         u8      unused_0[6];
7061         u8      valid;
7062 };
7063 
7064 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */
7065 struct hwrm_fw_get_structured_data_cmd_err {
7066         u8      code;
7067         #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
7068         #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID  0x3UL
7069         #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST   FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
7070         u8      unused_0[7];
7071 };
7072 
7073 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
7074 struct hwrm_exec_fwd_resp_input {
7075         __le16  req_type;
7076         __le16  cmpl_ring;
7077         __le16  seq_id;
7078         __le16  target_id;
7079         __le64  resp_addr;
7080         __le32  encap_request[26];
7081         __le16  encap_resp_target_id;
7082         u8      unused_0[6];
7083 };
7084 
7085 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
7086 struct hwrm_exec_fwd_resp_output {
7087         __le16  error_code;
7088         __le16  req_type;
7089         __le16  seq_id;
7090         __le16  resp_len;
7091         u8      unused_0[7];
7092         u8      valid;
7093 };
7094 
7095 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
7096 struct hwrm_reject_fwd_resp_input {
7097         __le16  req_type;
7098         __le16  cmpl_ring;
7099         __le16  seq_id;
7100         __le16  target_id;
7101         __le64  resp_addr;
7102         __le32  encap_request[26];
7103         __le16  encap_resp_target_id;
7104         u8      unused_0[6];
7105 };
7106 
7107 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
7108 struct hwrm_reject_fwd_resp_output {
7109         __le16  error_code;
7110         __le16  req_type;
7111         __le16  seq_id;
7112         __le16  resp_len;
7113         u8      unused_0[7];
7114         u8      valid;
7115 };
7116 
7117 /* hwrm_fwd_resp_input (size:1024b/128B) */
7118 struct hwrm_fwd_resp_input {
7119         __le16  req_type;
7120         __le16  cmpl_ring;
7121         __le16  seq_id;
7122         __le16  target_id;
7123         __le64  resp_addr;
7124         __le16  encap_resp_target_id;
7125         __le16  encap_resp_cmpl_ring;
7126         __le16  encap_resp_len;
7127         u8      unused_0;
7128         u8      unused_1;
7129         __le64  encap_resp_addr;
7130         __le32  encap_resp[24];
7131 };
7132 
7133 /* hwrm_fwd_resp_output (size:128b/16B) */
7134 struct hwrm_fwd_resp_output {
7135         __le16  error_code;
7136         __le16  req_type;
7137         __le16  seq_id;
7138         __le16  resp_len;
7139         u8      unused_0[7];
7140         u8      valid;
7141 };
7142 
7143 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
7144 struct hwrm_fwd_async_event_cmpl_input {
7145         __le16  req_type;
7146         __le16  cmpl_ring;
7147         __le16  seq_id;
7148         __le16  target_id;
7149         __le64  resp_addr;
7150         __le16  encap_async_event_target_id;
7151         u8      unused_0[6];
7152         __le32  encap_async_event_cmpl[4];
7153 };
7154 
7155 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
7156 struct hwrm_fwd_async_event_cmpl_output {
7157         __le16  error_code;
7158         __le16  req_type;
7159         __le16  seq_id;
7160         __le16  resp_len;
7161         u8      unused_0[7];
7162         u8      valid;
7163 };
7164 
7165 /* hwrm_temp_monitor_query_input (size:128b/16B) */
7166 struct hwrm_temp_monitor_query_input {
7167         __le16  req_type;
7168         __le16  cmpl_ring;
7169         __le16  seq_id;
7170         __le16  target_id;
7171         __le64  resp_addr;
7172 };
7173 
7174 /* hwrm_temp_monitor_query_output (size:128b/16B) */
7175 struct hwrm_temp_monitor_query_output {
7176         __le16  error_code;
7177         __le16  req_type;
7178         __le16  seq_id;
7179         __le16  resp_len;
7180         u8      temp;
7181         u8      phy_temp;
7182         u8      om_temp;
7183         u8      flags;
7184         #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE         0x1UL
7185         #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE     0x2UL
7186         #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT             0x4UL
7187         #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE      0x8UL
7188         u8      unused_0[3];
7189         u8      valid;
7190 };
7191 
7192 /* hwrm_wol_filter_alloc_input (size:512b/64B) */
7193 struct hwrm_wol_filter_alloc_input {
7194         __le16  req_type;
7195         __le16  cmpl_ring;
7196         __le16  seq_id;
7197         __le16  target_id;
7198         __le64  resp_addr;
7199         __le32  flags;
7200         __le32  enables;
7201         #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS           0x1UL
7202         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET        0x2UL
7203         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE      0x4UL
7204         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR      0x8UL
7205         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR     0x10UL
7206         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE     0x20UL
7207         __le16  port_id;
7208         u8      wol_type;
7209         #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL
7210         #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP      0x1UL
7211         #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID  0xffUL
7212         #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST    WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID
7213         u8      unused_0[5];
7214         u8      mac_address[6];
7215         __le16  pattern_offset;
7216         __le16  pattern_buf_size;
7217         __le16  pattern_mask_size;
7218         u8      unused_1[4];
7219         __le64  pattern_buf_addr;
7220         __le64  pattern_mask_addr;
7221 };
7222 
7223 /* hwrm_wol_filter_alloc_output (size:128b/16B) */
7224 struct hwrm_wol_filter_alloc_output {
7225         __le16  error_code;
7226         __le16  req_type;
7227         __le16  seq_id;
7228         __le16  resp_len;
7229         u8      wol_filter_id;
7230         u8      unused_0[6];
7231         u8      valid;
7232 };
7233 
7234 /* hwrm_wol_filter_free_input (size:256b/32B) */
7235 struct hwrm_wol_filter_free_input {
7236         __le16  req_type;
7237         __le16  cmpl_ring;
7238         __le16  seq_id;
7239         __le16  target_id;
7240         __le64  resp_addr;
7241         __le32  flags;
7242         #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS     0x1UL
7243         __le32  enables;
7244         #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID     0x1UL
7245         __le16  port_id;
7246         u8      wol_filter_id;
7247         u8      unused_0[5];
7248 };
7249 
7250 /* hwrm_wol_filter_free_output (size:128b/16B) */
7251 struct hwrm_wol_filter_free_output {
7252         __le16  error_code;
7253         __le16  req_type;
7254         __le16  seq_id;
7255         __le16  resp_len;
7256         u8      unused_0[7];
7257         u8      valid;
7258 };
7259 
7260 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */
7261 struct hwrm_wol_filter_qcfg_input {
7262         __le16  req_type;
7263         __le16  cmpl_ring;
7264         __le16  seq_id;
7265         __le16  target_id;
7266         __le64  resp_addr;
7267         __le16  port_id;
7268         __le16  handle;
7269         u8      unused_0[4];
7270         __le64  pattern_buf_addr;
7271         __le16  pattern_buf_size;
7272         u8      unused_1[6];
7273         __le64  pattern_mask_addr;
7274         __le16  pattern_mask_size;
7275         u8      unused_2[6];
7276 };
7277 
7278 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */
7279 struct hwrm_wol_filter_qcfg_output {
7280         __le16  error_code;
7281         __le16  req_type;
7282         __le16  seq_id;
7283         __le16  resp_len;
7284         __le16  next_handle;
7285         u8      wol_filter_id;
7286         u8      wol_type;
7287         #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL
7288         #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP      0x1UL
7289         #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID  0xffUL
7290         #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST    WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID
7291         __le32  unused_0;
7292         u8      mac_address[6];
7293         __le16  pattern_offset;
7294         __le16  pattern_size;
7295         __le16  pattern_mask_size;
7296         u8      unused_1[3];
7297         u8      valid;
7298 };
7299 
7300 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */
7301 struct hwrm_wol_reason_qcfg_input {
7302         __le16  req_type;
7303         __le16  cmpl_ring;
7304         __le16  seq_id;
7305         __le16  target_id;
7306         __le64  resp_addr;
7307         __le16  port_id;
7308         u8      unused_0[6];
7309         __le64  wol_pkt_buf_addr;
7310         __le16  wol_pkt_buf_size;
7311         u8      unused_1[6];
7312 };
7313 
7314 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */
7315 struct hwrm_wol_reason_qcfg_output {
7316         __le16  error_code;
7317         __le16  req_type;
7318         __le16  seq_id;
7319         __le16  resp_len;
7320         u8      wol_filter_id;
7321         u8      wol_reason;
7322         #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL
7323         #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP      0x1UL
7324         #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID  0xffUL
7325         #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST    WOL_REASON_QCFG_RESP_WOL_REASON_INVALID
7326         u8      wol_pkt_len;
7327         u8      unused_0[4];
7328         u8      valid;
7329 };
7330 
7331 /* coredump_segment_record (size:128b/16B) */
7332 struct coredump_segment_record {
7333         __le16  component_id;
7334         __le16  segment_id;
7335         __le16  max_instances;
7336         u8      version_hi;
7337         u8      version_low;
7338         u8      seg_flags;
7339         u8      compress_flags;
7340         #define SFLAG_COMPRESSED_ZLIB     0x1UL
7341         u8      unused_0[6];
7342 };
7343 
7344 /* hwrm_dbg_coredump_list_input (size:256b/32B) */
7345 struct hwrm_dbg_coredump_list_input {
7346         __le16  req_type;
7347         __le16  cmpl_ring;
7348         __le16  seq_id;
7349         __le16  target_id;
7350         __le64  resp_addr;
7351         __le64  host_dest_addr;
7352         __le32  host_buf_len;
7353         __le16  seq_no;
7354         u8      flags;
7355         #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP     0x1UL
7356         u8      unused_0[1];
7357 };
7358 
7359 /* hwrm_dbg_coredump_list_output (size:128b/16B) */
7360 struct hwrm_dbg_coredump_list_output {
7361         __le16  error_code;
7362         __le16  req_type;
7363         __le16  seq_id;
7364         __le16  resp_len;
7365         u8      flags;
7366         #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE     0x1UL
7367         u8      unused_0;
7368         __le16  total_segments;
7369         __le16  data_len;
7370         u8      unused_1;
7371         u8      valid;
7372 };
7373 
7374 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */
7375 struct hwrm_dbg_coredump_initiate_input {
7376         __le16  req_type;
7377         __le16  cmpl_ring;
7378         __le16  seq_id;
7379         __le16  target_id;
7380         __le64  resp_addr;
7381         __le16  component_id;
7382         __le16  segment_id;
7383         __le16  instance;
7384         __le16  unused_0;
7385         u8      seg_flags;
7386         u8      unused_1[7];
7387 };
7388 
7389 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */
7390 struct hwrm_dbg_coredump_initiate_output {
7391         __le16  error_code;
7392         __le16  req_type;
7393         __le16  seq_id;
7394         __le16  resp_len;
7395         u8      unused_0[7];
7396         u8      valid;
7397 };
7398 
7399 /* coredump_data_hdr (size:128b/16B) */
7400 struct coredump_data_hdr {
7401         __le32  address;
7402         __le32  flags_length;
7403         __le32  instance;
7404         __le32  next_offset;
7405 };
7406 
7407 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */
7408 struct hwrm_dbg_coredump_retrieve_input {
7409         __le16  req_type;
7410         __le16  cmpl_ring;
7411         __le16  seq_id;
7412         __le16  target_id;
7413         __le64  resp_addr;
7414         __le64  host_dest_addr;
7415         __le32  host_buf_len;
7416         __le32  unused_0;
7417         __le16  component_id;
7418         __le16  segment_id;
7419         __le16  instance;
7420         __le16  unused_1;
7421         u8      seg_flags;
7422         u8      unused_2;
7423         __le16  unused_3;
7424         __le32  unused_4;
7425         __le32  seq_no;
7426         __le32  unused_5;
7427 };
7428 
7429 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */
7430 struct hwrm_dbg_coredump_retrieve_output {
7431         __le16  error_code;
7432         __le16  req_type;
7433         __le16  seq_id;
7434         __le16  resp_len;
7435         u8      flags;
7436         #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE     0x1UL
7437         u8      unused_0;
7438         __le16  data_len;
7439         u8      unused_1[3];
7440         u8      valid;
7441 };
7442 
7443 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */
7444 struct hwrm_dbg_ring_info_get_input {
7445         __le16  req_type;
7446         __le16  cmpl_ring;
7447         __le16  seq_id;
7448         __le16  target_id;
7449         __le64  resp_addr;
7450         u8      ring_type;
7451         #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL
7452         #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX      0x1UL
7453         #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX      0x2UL
7454         #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST   DBG_RING_INFO_GET_REQ_RING_TYPE_RX
7455         u8      unused_0[3];
7456         __le32  fw_ring_id;
7457 };
7458 
7459 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */
7460 struct hwrm_dbg_ring_info_get_output {
7461         __le16  error_code;
7462         __le16  req_type;
7463         __le16  seq_id;
7464         __le16  resp_len;
7465         __le32  producer_index;
7466         __le32  consumer_index;
7467         u8      unused_0[7];
7468         u8      valid;
7469 };
7470 
7471 /* hwrm_nvm_read_input (size:320b/40B) */
7472 struct hwrm_nvm_read_input {
7473         __le16  req_type;
7474         __le16  cmpl_ring;
7475         __le16  seq_id;
7476         __le16  target_id;
7477         __le64  resp_addr;
7478         __le64  host_dest_addr;
7479         __le16  dir_idx;
7480         u8      unused_0[2];
7481         __le32  offset;
7482         __le32  len;
7483         u8      unused_1[4];
7484 };
7485 
7486 /* hwrm_nvm_read_output (size:128b/16B) */
7487 struct hwrm_nvm_read_output {
7488         __le16  error_code;
7489         __le16  req_type;
7490         __le16  seq_id;
7491         __le16  resp_len;
7492         u8      unused_0[7];
7493         u8      valid;
7494 };
7495 
7496 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
7497 struct hwrm_nvm_get_dir_entries_input {
7498         __le16  req_type;
7499         __le16  cmpl_ring;
7500         __le16  seq_id;
7501         __le16  target_id;
7502         __le64  resp_addr;
7503         __le64  host_dest_addr;
7504 };
7505 
7506 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
7507 struct hwrm_nvm_get_dir_entries_output {
7508         __le16  error_code;
7509         __le16  req_type;
7510         __le16  seq_id;
7511         __le16  resp_len;
7512         u8      unused_0[7];
7513         u8      valid;
7514 };
7515 
7516 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
7517 struct hwrm_nvm_get_dir_info_input {
7518         __le16  req_type;
7519         __le16  cmpl_ring;
7520         __le16  seq_id;
7521         __le16  target_id;
7522         __le64  resp_addr;
7523 };
7524 
7525 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
7526 struct hwrm_nvm_get_dir_info_output {
7527         __le16  error_code;
7528         __le16  req_type;
7529         __le16  seq_id;
7530         __le16  resp_len;
7531         __le32  entries;
7532         __le32  entry_length;
7533         u8      unused_0[7];
7534         u8      valid;
7535 };
7536 
7537 /* hwrm_nvm_write_input (size:384b/48B) */
7538 struct hwrm_nvm_write_input {
7539         __le16  req_type;
7540         __le16  cmpl_ring;
7541         __le16  seq_id;
7542         __le16  target_id;
7543         __le64  resp_addr;
7544         __le64  host_src_addr;
7545         __le16  dir_type;
7546         __le16  dir_ordinal;
7547         __le16  dir_ext;
7548         __le16  dir_attr;
7549         __le32  dir_data_length;
7550         __le16  option;
7551         __le16  flags;
7552         #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG     0x1UL
7553         __le32  dir_item_length;
7554         __le32  unused_0;
7555 };
7556 
7557 /* hwrm_nvm_write_output (size:128b/16B) */
7558 struct hwrm_nvm_write_output {
7559         __le16  error_code;
7560         __le16  req_type;
7561         __le16  seq_id;
7562         __le16  resp_len;
7563         __le32  dir_item_length;
7564         __le16  dir_idx;
7565         u8      unused_0;
7566         u8      valid;
7567 };
7568 
7569 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
7570 struct hwrm_nvm_write_cmd_err {
7571         u8      code;
7572         #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN  0x0UL
7573         #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL
7574         #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL
7575         #define NVM_WRITE_CMD_ERR_CODE_LAST    NVM_WRITE_CMD_ERR_CODE_NO_SPACE
7576         u8      unused_0[7];
7577 };
7578 
7579 /* hwrm_nvm_modify_input (size:320b/40B) */
7580 struct hwrm_nvm_modify_input {
7581         __le16  req_type;
7582         __le16  cmpl_ring;
7583         __le16  seq_id;
7584         __le16  target_id;
7585         __le64  resp_addr;
7586         __le64  host_src_addr;
7587         __le16  dir_idx;
7588         u8      unused_0[2];
7589         __le32  offset;
7590         __le32  len;
7591         u8      unused_1[4];
7592 };
7593 
7594 /* hwrm_nvm_modify_output (size:128b/16B) */
7595 struct hwrm_nvm_modify_output {
7596         __le16  error_code;
7597         __le16  req_type;
7598         __le16  seq_id;
7599         __le16  resp_len;
7600         u8      unused_0[7];
7601         u8      valid;
7602 };
7603 
7604 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
7605 struct hwrm_nvm_find_dir_entry_input {
7606         __le16  req_type;
7607         __le16  cmpl_ring;
7608         __le16  seq_id;
7609         __le16  target_id;
7610         __le64  resp_addr;
7611         __le32  enables;
7612         #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID     0x1UL
7613         __le16  dir_idx;
7614         __le16  dir_type;
7615         __le16  dir_ordinal;
7616         __le16  dir_ext;
7617         u8      opt_ordinal;
7618         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
7619         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
7620         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ    0x0UL
7621         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE    0x1UL
7622         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT    0x2UL
7623         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT
7624         u8      unused_0[3];
7625 };
7626 
7627 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
7628 struct hwrm_nvm_find_dir_entry_output {
7629         __le16  error_code;
7630         __le16  req_type;
7631         __le16  seq_id;
7632         __le16  resp_len;
7633         __le32  dir_item_length;
7634         __le32  dir_data_length;
7635         __le32  fw_ver;
7636         __le16  dir_ordinal;
7637         __le16  dir_idx;
7638         u8      unused_0[7];
7639         u8      valid;
7640 };
7641 
7642 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
7643 struct hwrm_nvm_erase_dir_entry_input {
7644         __le16  req_type;
7645         __le16  cmpl_ring;
7646         __le16  seq_id;
7647         __le16  target_id;
7648         __le64  resp_addr;
7649         __le16  dir_idx;
7650         u8      unused_0[6];
7651 };
7652 
7653 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
7654 struct hwrm_nvm_erase_dir_entry_output {
7655         __le16  error_code;
7656         __le16  req_type;
7657         __le16  seq_id;
7658         __le16  resp_len;
7659         u8      unused_0[7];
7660         u8      valid;
7661 };
7662 
7663 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
7664 struct hwrm_nvm_get_dev_info_input {
7665         __le16  req_type;
7666         __le16  cmpl_ring;
7667         __le16  seq_id;
7668         __le16  target_id;
7669         __le64  resp_addr;
7670 };
7671 
7672 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
7673 struct hwrm_nvm_get_dev_info_output {
7674         __le16  error_code;
7675         __le16  req_type;
7676         __le16  seq_id;
7677         __le16  resp_len;
7678         __le16  manufacturer_id;
7679         __le16  device_id;
7680         __le32  sector_size;
7681         __le32  nvram_size;
7682         __le32  reserved_size;
7683         __le32  available_size;
7684         u8      nvm_cfg_ver_maj;
7685         u8      nvm_cfg_ver_min;
7686         u8      nvm_cfg_ver_upd;
7687         u8      valid;
7688 };
7689 
7690 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
7691 struct hwrm_nvm_mod_dir_entry_input {
7692         __le16  req_type;
7693         __le16  cmpl_ring;
7694         __le16  seq_id;
7695         __le16  target_id;
7696         __le64  resp_addr;
7697         __le32  enables;
7698         #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM     0x1UL
7699         __le16  dir_idx;
7700         __le16  dir_ordinal;
7701         __le16  dir_ext;
7702         __le16  dir_attr;
7703         __le32  checksum;
7704 };
7705 
7706 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
7707 struct hwrm_nvm_mod_dir_entry_output {
7708         __le16  error_code;
7709         __le16  req_type;
7710         __le16  seq_id;
7711         __le16  resp_len;
7712         u8      unused_0[7];
7713         u8      valid;
7714 };
7715 
7716 /* hwrm_nvm_verify_update_input (size:192b/24B) */
7717 struct hwrm_nvm_verify_update_input {
7718         __le16  req_type;
7719         __le16  cmpl_ring;
7720         __le16  seq_id;
7721         __le16  target_id;
7722         __le64  resp_addr;
7723         __le16  dir_type;
7724         __le16  dir_ordinal;
7725         __le16  dir_ext;
7726         u8      unused_0[2];
7727 };
7728 
7729 /* hwrm_nvm_verify_update_output (size:128b/16B) */
7730 struct hwrm_nvm_verify_update_output {
7731         __le16  error_code;
7732         __le16  req_type;
7733         __le16  seq_id;
7734         __le16  resp_len;
7735         u8      unused_0[7];
7736         u8      valid;
7737 };
7738 
7739 /* hwrm_nvm_install_update_input (size:192b/24B) */
7740 struct hwrm_nvm_install_update_input {
7741         __le16  req_type;
7742         __le16  cmpl_ring;
7743         __le16  seq_id;
7744         __le16  target_id;
7745         __le64  resp_addr;
7746         __le32  install_type;
7747         #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
7748         #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL    0xffffffffUL
7749         #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST  NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL
7750         __le16  flags;
7751         #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE     0x1UL
7752         #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG      0x2UL
7753         #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG      0x4UL
7754         u8      unused_0[2];
7755 };
7756 
7757 /* hwrm_nvm_install_update_output (size:192b/24B) */
7758 struct hwrm_nvm_install_update_output {
7759         __le16  error_code;
7760         __le16  req_type;
7761         __le16  seq_id;
7762         __le16  resp_len;
7763         __le64  installed_items;
7764         u8      result;
7765         #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
7766         #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST   NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS
7767         u8      problem_item;
7768         #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE    0x0UL
7769         #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
7770         #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST   NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE
7771         u8      reset_required;
7772         #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE  0x0UL
7773         #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI   0x1UL
7774         #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL
7775         #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER
7776         u8      unused_0[4];
7777         u8      valid;
7778 };
7779 
7780 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
7781 struct hwrm_nvm_install_update_cmd_err {
7782         u8      code;
7783         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN  0x0UL
7784         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
7785         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
7786         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST    NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
7787         u8      unused_0[7];
7788 };
7789 
7790 /* hwrm_nvm_get_variable_input (size:320b/40B) */
7791 struct hwrm_nvm_get_variable_input {
7792         __le16  req_type;
7793         __le16  cmpl_ring;
7794         __le16  seq_id;
7795         __le16  target_id;
7796         __le64  resp_addr;
7797         __le64  dest_data_addr;
7798         __le16  data_len;
7799         __le16  option_num;
7800         #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0    0x0UL
7801         #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
7802         #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST     NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
7803         __le16  dimensions;
7804         __le16  index_0;
7805         __le16  index_1;
7806         __le16  index_2;
7807         __le16  index_3;
7808         u8      flags;
7809         #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT     0x1UL
7810         u8      unused_0;
7811 };
7812 
7813 /* hwrm_nvm_get_variable_output (size:128b/16B) */
7814 struct hwrm_nvm_get_variable_output {
7815         __le16  error_code;
7816         __le16  req_type;
7817         __le16  seq_id;
7818         __le16  resp_len;
7819         __le16  data_len;
7820         __le16  option_num;
7821         #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0    0x0UL
7822         #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL
7823         #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST     NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF
7824         u8      unused_0[3];
7825         u8      valid;
7826 };
7827 
7828 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
7829 struct hwrm_nvm_get_variable_cmd_err {
7830         u8      code;
7831         #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN       0x0UL
7832         #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
7833         #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   0x2UL
7834         #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
7835         #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST         NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
7836         u8      unused_0[7];
7837 };
7838 
7839 /* hwrm_nvm_set_variable_input (size:320b/40B) */
7840 struct hwrm_nvm_set_variable_input {
7841         __le16  req_type;
7842         __le16  cmpl_ring;
7843         __le16  seq_id;
7844         __le16  target_id;
7845         __le64  resp_addr;
7846         __le64  src_data_addr;
7847         __le16  data_len;
7848         __le16  option_num;
7849         #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0    0x0UL
7850         #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
7851         #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST     NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
7852         __le16  dimensions;
7853         __le16  index_0;
7854         __le16  index_1;
7855         __le16  index_2;
7856         __le16  index_3;
7857         u8      flags;
7858         #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH                0x1UL
7859         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK          0xeUL
7860         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT           1
7861         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE            (0x0UL << 1)
7862         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1       (0x1UL << 1)
7863         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256          (0x2UL << 1)
7864         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH  (0x3UL << 1)
7865         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST           NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
7866         #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK        0x70UL
7867         #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT         4
7868         #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT            0x80UL
7869         u8      unused_0;
7870 };
7871 
7872 /* hwrm_nvm_set_variable_output (size:128b/16B) */
7873 struct hwrm_nvm_set_variable_output {
7874         __le16  error_code;
7875         __le16  req_type;
7876         __le16  seq_id;
7877         __le16  resp_len;
7878         u8      unused_0[7];
7879         u8      valid;
7880 };
7881 
7882 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
7883 struct hwrm_nvm_set_variable_cmd_err {
7884         u8      code;
7885         #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN       0x0UL
7886         #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
7887         #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   0x2UL
7888         #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST         NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
7889         u8      unused_0[7];
7890 };
7891 
7892 /* hwrm_selftest_qlist_input (size:128b/16B) */
7893 struct hwrm_selftest_qlist_input {
7894         __le16  req_type;
7895         __le16  cmpl_ring;
7896         __le16  seq_id;
7897         __le16  target_id;
7898         __le64  resp_addr;
7899 };
7900 
7901 /* hwrm_selftest_qlist_output (size:2240b/280B) */
7902 struct hwrm_selftest_qlist_output {
7903         __le16  error_code;
7904         __le16  req_type;
7905         __le16  seq_id;
7906         __le16  resp_len;
7907         u8      num_tests;
7908         u8      available_tests;
7909         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST                 0x1UL
7910         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST                0x2UL
7911         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST            0x4UL
7912         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST              0x8UL
7913         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST         0x10UL
7914         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST     0x20UL
7915         u8      offline_tests;
7916         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST                 0x1UL
7917         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST                0x2UL
7918         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST            0x4UL
7919         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST              0x8UL
7920         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST         0x10UL
7921         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST     0x20UL
7922         u8      unused_0;
7923         __le16  test_timeout;
7924         u8      unused_1[2];
7925         char    test0_name[32];
7926         char    test1_name[32];
7927         char    test2_name[32];
7928         char    test3_name[32];
7929         char    test4_name[32];
7930         char    test5_name[32];
7931         char    test6_name[32];
7932         char    test7_name[32];
7933         u8      unused_2[7];
7934         u8      valid;
7935 };
7936 
7937 /* hwrm_selftest_exec_input (size:192b/24B) */
7938 struct hwrm_selftest_exec_input {
7939         __le16  req_type;
7940         __le16  cmpl_ring;
7941         __le16  seq_id;
7942         __le16  target_id;
7943         __le64  resp_addr;
7944         u8      flags;
7945         #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST                 0x1UL
7946         #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST                0x2UL
7947         #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST            0x4UL
7948         #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST              0x8UL
7949         #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST         0x10UL
7950         #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST     0x20UL
7951         u8      unused_0[7];
7952 };
7953 
7954 /* hwrm_selftest_exec_output (size:128b/16B) */
7955 struct hwrm_selftest_exec_output {
7956         __le16  error_code;
7957         __le16  req_type;
7958         __le16  seq_id;
7959         __le16  resp_len;
7960         u8      requested_tests;
7961         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST                 0x1UL
7962         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST                0x2UL
7963         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST            0x4UL
7964         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST              0x8UL
7965         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST         0x10UL
7966         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST     0x20UL
7967         u8      test_success;
7968         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST                 0x1UL
7969         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST                0x2UL
7970         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST            0x4UL
7971         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST              0x8UL
7972         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST         0x10UL
7973         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST     0x20UL
7974         u8      unused_0[5];
7975         u8      valid;
7976 };
7977 
7978 /* hwrm_selftest_irq_input (size:128b/16B) */
7979 struct hwrm_selftest_irq_input {
7980         __le16  req_type;
7981         __le16  cmpl_ring;
7982         __le16  seq_id;
7983         __le16  target_id;
7984         __le64  resp_addr;
7985 };
7986 
7987 /* hwrm_selftest_irq_output (size:128b/16B) */
7988 struct hwrm_selftest_irq_output {
7989         __le16  error_code;
7990         __le16  req_type;
7991         __le16  seq_id;
7992         __le16  resp_len;
7993         u8      unused_0[7];
7994         u8      valid;
7995 };
7996 
7997 #endif /* _BNXT_HSI_H_ */

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