This source file includes following definitions.
- bnxt_vf_pciid
- bnxt_db_nq
- bnxt_db_nq_arm
- bnxt_db_cq
- bnxt_xmit_get_cfa_action
- bnxt_start_xmit
- bnxt_tx_int
- __bnxt_alloc_rx_page
- __bnxt_alloc_rx_data
- bnxt_alloc_rx_data
- bnxt_reuse_rx_data
- bnxt_find_next_agg_idx
- bnxt_alloc_rx_page
- bnxt_get_agg
- bnxt_get_tpa_agg_p5
- bnxt_reuse_rx_agg_bufs
- bnxt_rx_page_skb
- bnxt_rx_skb
- bnxt_rx_pages
- bnxt_agg_bufs_valid
- bnxt_copy_skb
- bnxt_discard_rx
- bnxt_queue_fw_reset_work
- bnxt_queue_sp_work
- bnxt_cancel_sp_work
- bnxt_sched_reset
- bnxt_alloc_agg_idx
- bnxt_free_agg_idx
- bnxt_lookup_agg_idx
- bnxt_tpa_start
- bnxt_abort_tpa
- bnxt_gro_tunnel
- bnxt_gro_func_5731x
- bnxt_gro_func_5750x
- bnxt_gro_skb
- bnxt_get_pkt_dev
- bnxt_tpa_end
- bnxt_tpa_agg
- bnxt_deliver_skb
- bnxt_rx_pkt
- bnxt_force_rx_discard
- bnxt_fw_health_readl
- bnxt_async_event_process
- bnxt_hwrm_handler
- bnxt_msix
- bnxt_has_work
- bnxt_inta
- __bnxt_poll_work
- __bnxt_poll_work_done
- bnxt_poll_work
- bnxt_poll_nitroa0
- bnxt_poll
- __bnxt_poll_cqs
- __bnxt_poll_cqs_done
- bnxt_poll_p5
- bnxt_free_tx_skbs
- bnxt_free_rx_skbs
- bnxt_free_skbs
- bnxt_free_ring
- bnxt_alloc_ring
- bnxt_free_tpa_info
- bnxt_alloc_tpa_info
- bnxt_free_rx_rings
- bnxt_alloc_rx_page_pool
- bnxt_alloc_rx_rings
- bnxt_free_tx_rings
- bnxt_alloc_tx_rings
- bnxt_free_cp_rings
- bnxt_alloc_cp_sub_ring
- bnxt_alloc_cp_rings
- bnxt_init_ring_struct
- bnxt_init_rxbd_pages
- bnxt_init_one_rx_ring
- bnxt_init_cp_rings
- bnxt_init_rx_rings
- bnxt_init_tx_rings
- bnxt_free_ring_grps
- bnxt_init_ring_grps
- bnxt_free_vnics
- bnxt_alloc_vnics
- bnxt_init_vnics
- bnxt_calc_nr_ring_pages
- bnxt_set_tpa_flags
- bnxt_set_ring_params
- bnxt_set_rx_skb_mode
- bnxt_free_vnic_attributes
- bnxt_alloc_vnic_attributes
- bnxt_free_hwrm_resources
- bnxt_alloc_kong_hwrm_resources
- bnxt_alloc_hwrm_resources
- bnxt_free_hwrm_short_cmd_req
- bnxt_alloc_hwrm_short_cmd_req
- bnxt_free_port_stats
- bnxt_free_ring_stats
- bnxt_alloc_stats
- bnxt_clear_ring_indices
- bnxt_free_ntp_fltrs
- bnxt_alloc_ntp_fltrs
- bnxt_free_mem
- bnxt_alloc_mem
- bnxt_disable_int
- bnxt_cp_num_to_irq_num
- bnxt_disable_int_sync
- bnxt_enable_int
- bnxt_hwrm_cmd_hdr_init
- bnxt_hwrm_to_stderr
- bnxt_hwrm_do_send_msg
- _hwrm_send_message
- _hwrm_send_message_silent
- hwrm_send_message
- hwrm_send_message_silent
- bnxt_hwrm_func_rgtr_async_events
- bnxt_hwrm_func_drv_rgtr
- bnxt_hwrm_func_drv_unrgtr
- bnxt_hwrm_tunnel_dst_port_free
- bnxt_hwrm_tunnel_dst_port_alloc
- bnxt_hwrm_cfa_l2_set_rx_mask
- bnxt_hwrm_cfa_ntuple_filter_free
- bnxt_hwrm_cfa_ntuple_filter_alloc
- bnxt_hwrm_set_vnic_filter
- bnxt_hwrm_clear_vnic_filter
- bnxt_hwrm_vnic_set_tpa
- bnxt_cp_ring_from_grp
- bnxt_cp_ring_for_rx
- bnxt_cp_ring_for_tx
- bnxt_hwrm_vnic_set_rss
- bnxt_hwrm_vnic_set_rss_p5
- bnxt_hwrm_vnic_set_hds
- bnxt_hwrm_vnic_ctx_free_one
- bnxt_hwrm_vnic_ctx_free
- bnxt_hwrm_vnic_ctx_alloc
- bnxt_get_roce_vnic_mode
- bnxt_hwrm_vnic_cfg
- bnxt_hwrm_vnic_free_one
- bnxt_hwrm_vnic_free
- bnxt_hwrm_vnic_alloc
- bnxt_hwrm_vnic_qcaps
- bnxt_hwrm_ring_grp_alloc
- bnxt_hwrm_ring_grp_free
- hwrm_ring_alloc_send_msg
- bnxt_hwrm_set_async_event_cr
- bnxt_set_db
- bnxt_hwrm_ring_alloc
- hwrm_ring_free_send_msg
- bnxt_hwrm_ring_free
- bnxt_hwrm_get_rings
- __bnxt_hwrm_get_tx_rings
- __bnxt_hwrm_reserve_pf_rings
- __bnxt_hwrm_reserve_vf_rings
- bnxt_hwrm_reserve_pf_rings
- bnxt_hwrm_reserve_vf_rings
- bnxt_hwrm_reserve_rings
- bnxt_nq_rings_in_use
- bnxt_cp_rings_in_use
- bnxt_get_func_stat_ctxs
- bnxt_need_reserve_rings
- __bnxt_reserve_rings
- bnxt_hwrm_check_vf_rings
- bnxt_hwrm_check_pf_rings
- bnxt_hwrm_check_rings
- bnxt_hwrm_coal_params_qcaps
- bnxt_usec_to_coal_tmr
- bnxt_hwrm_set_coal_params
- __bnxt_hwrm_set_coal_nq
- bnxt_hwrm_set_ring_coal
- bnxt_hwrm_set_coal
- bnxt_hwrm_stat_ctx_free
- bnxt_hwrm_stat_ctx_alloc
- bnxt_hwrm_func_qcfg
- bnxt_hwrm_func_backing_store_qcaps
- bnxt_hwrm_set_pg_attr
- bnxt_hwrm_func_backing_store_cfg
- bnxt_alloc_ctx_mem_blk
- bnxt_alloc_ctx_pg_tbls
- bnxt_free_ctx_pg_tbls
- bnxt_free_ctx_mem
- bnxt_alloc_ctx_mem
- bnxt_hwrm_func_resc_qcaps
- __bnxt_hwrm_func_qcaps
- bnxt_hwrm_func_qcaps
- bnxt_hwrm_cfa_adv_flow_mgnt_qcaps
- bnxt_map_fw_health_regs
- bnxt_hwrm_error_recovery_qcfg
- bnxt_hwrm_func_reset
- bnxt_hwrm_queue_qportcfg
- __bnxt_hwrm_ver_get
- bnxt_hwrm_ver_get
- bnxt_hwrm_fw_set_time
- bnxt_hwrm_port_qstats
- bnxt_hwrm_port_qstats_ext
- bnxt_hwrm_pcie_qstats
- bnxt_hwrm_free_tunnel_ports
- bnxt_set_tpa
- bnxt_hwrm_clear_vnic_rss
- bnxt_clear_vnic
- bnxt_hwrm_resource_free
- bnxt_hwrm_set_br_mode
- bnxt_hwrm_set_cache_line_size
- __bnxt_setup_vnic
- __bnxt_setup_vnic_p5
- bnxt_setup_vnic
- bnxt_alloc_rfs_vnics
- bnxt_promisc_ok
- bnxt_setup_nitroa0_vnic
- bnxt_init_chip
- bnxt_shutdown_nic
- bnxt_init_nic
- bnxt_set_real_num_queues
- bnxt_trim_rings
- bnxt_setup_msix
- bnxt_setup_inta
- bnxt_setup_int_mode
- bnxt_get_max_func_rss_ctxs
- bnxt_get_max_func_vnics
- bnxt_get_max_func_stat_ctxs
- bnxt_get_max_func_cp_rings
- bnxt_get_max_func_cp_rings_for_en
- bnxt_get_max_func_irqs
- bnxt_set_max_func_irqs
- bnxt_get_avail_cp_rings_for_en
- bnxt_get_avail_stat_ctxs_for_en
- bnxt_get_avail_msix
- bnxt_get_num_msix
- bnxt_init_msix
- bnxt_init_inta
- bnxt_init_int_mode
- bnxt_clear_int_mode
- bnxt_reserve_rings
- bnxt_free_irq
- bnxt_request_irq
- bnxt_del_napi
- bnxt_init_napi
- bnxt_disable_napi
- bnxt_enable_napi
- bnxt_tx_disable
- bnxt_tx_enable
- bnxt_report_link
- bnxt_hwrm_phy_qcaps
- bnxt_update_link
- bnxt_get_port_module_status
- bnxt_hwrm_set_pause_common
- bnxt_hwrm_set_link_common
- bnxt_hwrm_set_pause
- bnxt_hwrm_set_eee
- bnxt_hwrm_set_link_setting
- bnxt_hwrm_shutdown_link
- bnxt_hwrm_if_change
- bnxt_hwrm_port_led_qcaps
- bnxt_hwrm_alloc_wol_fltr
- bnxt_hwrm_free_wol_fltr
- bnxt_hwrm_get_wol_fltrs
- bnxt_get_wol_settings
- bnxt_show_temp
- bnxt_hwmon_close
- bnxt_hwmon_open
- bnxt_hwmon_close
- bnxt_hwmon_open
- bnxt_eee_config_ok
- bnxt_update_phy_setting
- bnxt_preset_reg_win
- __bnxt_open_nic
- bnxt_open_nic
- bnxt_half_open_nic
- bnxt_half_close_nic
- bnxt_open
- bnxt_drv_busy
- __bnxt_close_nic
- bnxt_close_nic
- bnxt_close
- bnxt_hwrm_port_phy_read
- bnxt_hwrm_port_phy_write
- bnxt_ioctl
- bnxt_get_ring_stats
- bnxt_add_prev_stats
- bnxt_get_stats64
- bnxt_mc_list_updated
- bnxt_uc_list_updated
- bnxt_set_rx_mode
- bnxt_cfg_rx_mode
- bnxt_can_reserve_rings
- bnxt_rfs_supported
- bnxt_rfs_capable
- bnxt_fix_features
- bnxt_set_features
- bnxt_dbg_hwrm_ring_info_get
- bnxt_dump_tx_sw_state
- bnxt_dump_rx_sw_state
- bnxt_dump_cp_sw_state
- bnxt_dbg_dump_states
- bnxt_reset_task
- bnxt_tx_timeout
- bnxt_fw_health_check
- bnxt_timer
- bnxt_rtnl_lock_sp
- bnxt_rtnl_unlock_sp
- bnxt_reset
- bnxt_fw_reset_close
- is_bnxt_fw_ok
- bnxt_force_fw_reset
- bnxt_fw_exception
- bnxt_get_registered_vfs
- bnxt_fw_reset
- bnxt_chk_missed_irq
- bnxt_sp_task
- bnxt_check_rings
- bnxt_unmap_bars
- bnxt_cleanup_pci
- bnxt_init_dflt_coal
- bnxt_alloc_fw_health
- bnxt_fw_init_one_p1
- bnxt_fw_init_one_p2
- bnxt_set_dflt_rss_hash_type
- bnxt_set_dflt_rfs
- bnxt_fw_init_one_p3
- bnxt_fw_init_one
- bnxt_fw_reset_writel
- bnxt_reset_all
- bnxt_fw_reset_task
- bnxt_init_board
- bnxt_change_mac_addr
- bnxt_change_mtu
- bnxt_setup_mq_tc
- bnxt_setup_tc_block_cb
- bnxt_setup_tc
- bnxt_fltr_match
- bnxt_rx_flow_steer
- bnxt_cfg_ntp_filters
- bnxt_cfg_ntp_filters
- bnxt_udp_tunnel_add
- bnxt_udp_tunnel_del
- bnxt_bridge_getlink
- bnxt_bridge_setlink
- bnxt_get_port_parent_id
- bnxt_get_devlink_port
- bnxt_remove_one
- bnxt_probe_phy
- bnxt_get_max_irq
- _bnxt_get_max_rings
- bnxt_get_max_rings
- bnxt_get_dflt_rings
- bnxt_trim_dflt_sh_rings
- bnxt_set_dflt_rings
- bnxt_init_dflt_ring_mode
- bnxt_restore_pf_fw_resources
- bnxt_init_mac_addr
- bnxt_pcie_dsn_get
- bnxt_init_one
- bnxt_shutdown
- bnxt_suspend
- bnxt_resume
- bnxt_io_error_detected
- bnxt_io_slot_reset
- bnxt_io_resume
- bnxt_init
- bnxt_exit
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10
11 #include <linux/module.h>
12
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
31 #include <asm/page.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/mdio.h>
35 #include <linux/if.h>
36 #include <linux/if_vlan.h>
37 #include <linux/if_bridge.h>
38 #include <linux/rtc.h>
39 #include <linux/bpf.h>
40 #include <net/ip.h>
41 #include <net/tcp.h>
42 #include <net/udp.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <net/udp_tunnel.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
53 #include <linux/cpumask.h>
54 #include <net/pkt_cls.h>
55 #include <linux/hwmon.h>
56 #include <linux/hwmon-sysfs.h>
57 #include <net/page_pool.h>
58
59 #include "bnxt_hsi.h"
60 #include "bnxt.h"
61 #include "bnxt_ulp.h"
62 #include "bnxt_sriov.h"
63 #include "bnxt_ethtool.h"
64 #include "bnxt_dcb.h"
65 #include "bnxt_xdp.h"
66 #include "bnxt_vfr.h"
67 #include "bnxt_tc.h"
68 #include "bnxt_devlink.h"
69 #include "bnxt_debugfs.h"
70
71 #define BNXT_TX_TIMEOUT (5 * HZ)
72
73 static const char version[] =
74 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
75
76 MODULE_LICENSE("GPL");
77 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
78 MODULE_VERSION(DRV_MODULE_VERSION);
79
80 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
81 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
82 #define BNXT_RX_COPY_THRESH 256
83
84 #define BNXT_TX_PUSH_THRESH 164
85
86 enum board_idx {
87 BCM57301,
88 BCM57302,
89 BCM57304,
90 BCM57417_NPAR,
91 BCM58700,
92 BCM57311,
93 BCM57312,
94 BCM57402,
95 BCM57404,
96 BCM57406,
97 BCM57402_NPAR,
98 BCM57407,
99 BCM57412,
100 BCM57414,
101 BCM57416,
102 BCM57417,
103 BCM57412_NPAR,
104 BCM57314,
105 BCM57417_SFP,
106 BCM57416_SFP,
107 BCM57404_NPAR,
108 BCM57406_NPAR,
109 BCM57407_SFP,
110 BCM57407_NPAR,
111 BCM57414_NPAR,
112 BCM57416_NPAR,
113 BCM57452,
114 BCM57454,
115 BCM5745x_NPAR,
116 BCM57508,
117 BCM57504,
118 BCM57502,
119 BCM57508_NPAR,
120 BCM57504_NPAR,
121 BCM57502_NPAR,
122 BCM58802,
123 BCM58804,
124 BCM58808,
125 NETXTREME_E_VF,
126 NETXTREME_C_VF,
127 NETXTREME_S_VF,
128 NETXTREME_E_P5_VF,
129 };
130
131
132 static const struct {
133 char *name;
134 } board_info[] = {
135 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
136 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
137 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
138 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
139 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
140 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
141 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
142 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
143 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
144 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
145 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
146 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
147 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
148 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
149 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
150 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
151 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
152 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
153 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
154 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
155 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
156 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
157 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
158 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
159 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
160 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
161 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
162 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
163 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
164 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
165 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
166 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
167 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" },
168 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" },
169 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" },
170 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
171 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
172 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
173 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
174 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
175 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
176 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
177 };
178
179 static const struct pci_device_id bnxt_pci_tbl[] = {
180 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
181 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
182 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
183 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
184 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
185 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
186 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
187 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
188 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
189 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
190 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
191 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
192 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
193 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
194 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
195 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
196 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
197 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
198 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
199 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
200 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
201 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
202 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
203 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
204 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
205 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
206 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
207 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
208 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
209 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
210 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
211 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
212 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
213 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
214 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
215 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
216 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
217 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
218 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR },
219 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR },
220 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR },
221 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR },
222 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR },
223 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR },
224 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
225 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
226 #ifdef CONFIG_BNXT_SRIOV
227 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
228 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
229 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
230 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
231 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
232 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
233 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
234 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
235 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
236 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
237 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
238 #endif
239 { 0 }
240 };
241
242 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
243
244 static const u16 bnxt_vf_req_snif[] = {
245 HWRM_FUNC_CFG,
246 HWRM_FUNC_VF_CFG,
247 HWRM_PORT_PHY_QCFG,
248 HWRM_CFA_L2_FILTER_ALLOC,
249 };
250
251 static const u16 bnxt_async_events_arr[] = {
252 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
253 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
254 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
255 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
256 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
257 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY,
258 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY,
259 };
260
261 static struct workqueue_struct *bnxt_pf_wq;
262
263 static bool bnxt_vf_pciid(enum board_idx idx)
264 {
265 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
266 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
267 }
268
269 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
270 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
271 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
272
273 #define BNXT_CP_DB_IRQ_DIS(db) \
274 writel(DB_CP_IRQ_DIS_FLAGS, db)
275
276 #define BNXT_DB_CQ(db, idx) \
277 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
278
279 #define BNXT_DB_NQ_P5(db, idx) \
280 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
281
282 #define BNXT_DB_CQ_ARM(db, idx) \
283 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
284
285 #define BNXT_DB_NQ_ARM_P5(db, idx) \
286 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
287
288 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
289 {
290 if (bp->flags & BNXT_FLAG_CHIP_P5)
291 BNXT_DB_NQ_P5(db, idx);
292 else
293 BNXT_DB_CQ(db, idx);
294 }
295
296 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
297 {
298 if (bp->flags & BNXT_FLAG_CHIP_P5)
299 BNXT_DB_NQ_ARM_P5(db, idx);
300 else
301 BNXT_DB_CQ_ARM(db, idx);
302 }
303
304 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
305 {
306 if (bp->flags & BNXT_FLAG_CHIP_P5)
307 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
308 db->doorbell);
309 else
310 BNXT_DB_CQ(db, idx);
311 }
312
313 const u16 bnxt_lhint_arr[] = {
314 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
315 TX_BD_FLAGS_LHINT_512_TO_1023,
316 TX_BD_FLAGS_LHINT_1024_TO_2047,
317 TX_BD_FLAGS_LHINT_1024_TO_2047,
318 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
319 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
320 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
321 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
322 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
323 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
324 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
325 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
326 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
327 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
328 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
329 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
330 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
331 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
332 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
333 };
334
335 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
336 {
337 struct metadata_dst *md_dst = skb_metadata_dst(skb);
338
339 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
340 return 0;
341
342 return md_dst->u.port_info.port_id;
343 }
344
345 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
346 {
347 struct bnxt *bp = netdev_priv(dev);
348 struct tx_bd *txbd;
349 struct tx_bd_ext *txbd1;
350 struct netdev_queue *txq;
351 int i;
352 dma_addr_t mapping;
353 unsigned int length, pad = 0;
354 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
355 u16 prod, last_frag;
356 struct pci_dev *pdev = bp->pdev;
357 struct bnxt_tx_ring_info *txr;
358 struct bnxt_sw_tx_bd *tx_buf;
359
360 i = skb_get_queue_mapping(skb);
361 if (unlikely(i >= bp->tx_nr_rings)) {
362 dev_kfree_skb_any(skb);
363 return NETDEV_TX_OK;
364 }
365
366 txq = netdev_get_tx_queue(dev, i);
367 txr = &bp->tx_ring[bp->tx_ring_map[i]];
368 prod = txr->tx_prod;
369
370 free_size = bnxt_tx_avail(bp, txr);
371 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
372 netif_tx_stop_queue(txq);
373 return NETDEV_TX_BUSY;
374 }
375
376 length = skb->len;
377 len = skb_headlen(skb);
378 last_frag = skb_shinfo(skb)->nr_frags;
379
380 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
381
382 txbd->tx_bd_opaque = prod;
383
384 tx_buf = &txr->tx_buf_ring[prod];
385 tx_buf->skb = skb;
386 tx_buf->nr_frags = last_frag;
387
388 vlan_tag_flags = 0;
389 cfa_action = bnxt_xmit_get_cfa_action(skb);
390 if (skb_vlan_tag_present(skb)) {
391 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
392 skb_vlan_tag_get(skb);
393
394
395
396 if (skb->vlan_proto == htons(ETH_P_8021Q))
397 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
398 }
399
400 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
401 struct tx_push_buffer *tx_push_buf = txr->tx_push;
402 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
403 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
404 void __iomem *db = txr->tx_db.doorbell;
405 void *pdata = tx_push_buf->data;
406 u64 *end;
407 int j, push_len;
408
409
410 tx_push->tx_bd_len_flags_type =
411 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
412 TX_BD_TYPE_LONG_TX_BD |
413 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
414 TX_BD_FLAGS_COAL_NOW |
415 TX_BD_FLAGS_PACKET_END |
416 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
417
418 if (skb->ip_summed == CHECKSUM_PARTIAL)
419 tx_push1->tx_bd_hsize_lflags =
420 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
421 else
422 tx_push1->tx_bd_hsize_lflags = 0;
423
424 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
425 tx_push1->tx_bd_cfa_action =
426 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
427
428 end = pdata + length;
429 end = PTR_ALIGN(end, 8) - 1;
430 *end = 0;
431
432 skb_copy_from_linear_data(skb, pdata, len);
433 pdata += len;
434 for (j = 0; j < last_frag; j++) {
435 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
436 void *fptr;
437
438 fptr = skb_frag_address_safe(frag);
439 if (!fptr)
440 goto normal_tx;
441
442 memcpy(pdata, fptr, skb_frag_size(frag));
443 pdata += skb_frag_size(frag);
444 }
445
446 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
447 txbd->tx_bd_haddr = txr->data_mapping;
448 prod = NEXT_TX(prod);
449 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
450 memcpy(txbd, tx_push1, sizeof(*txbd));
451 prod = NEXT_TX(prod);
452 tx_push->doorbell =
453 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
454 txr->tx_prod = prod;
455
456 tx_buf->is_push = 1;
457 netdev_tx_sent_queue(txq, skb->len);
458 wmb();
459
460 push_len = (length + sizeof(*tx_push) + 7) / 8;
461 if (push_len > 16) {
462 __iowrite64_copy(db, tx_push_buf, 16);
463 __iowrite32_copy(db + 4, tx_push_buf + 1,
464 (push_len - 16) << 1);
465 } else {
466 __iowrite64_copy(db, tx_push_buf, push_len);
467 }
468
469 goto tx_done;
470 }
471
472 normal_tx:
473 if (length < BNXT_MIN_PKT_SIZE) {
474 pad = BNXT_MIN_PKT_SIZE - length;
475 if (skb_pad(skb, pad)) {
476
477 tx_buf->skb = NULL;
478 return NETDEV_TX_OK;
479 }
480 length = BNXT_MIN_PKT_SIZE;
481 }
482
483 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
484
485 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
486 dev_kfree_skb_any(skb);
487 tx_buf->skb = NULL;
488 return NETDEV_TX_OK;
489 }
490
491 dma_unmap_addr_set(tx_buf, mapping, mapping);
492 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
493 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
494
495 txbd->tx_bd_haddr = cpu_to_le64(mapping);
496
497 prod = NEXT_TX(prod);
498 txbd1 = (struct tx_bd_ext *)
499 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
500
501 txbd1->tx_bd_hsize_lflags = 0;
502 if (skb_is_gso(skb)) {
503 u32 hdr_len;
504
505 if (skb->encapsulation)
506 hdr_len = skb_inner_network_offset(skb) +
507 skb_inner_network_header_len(skb) +
508 inner_tcp_hdrlen(skb);
509 else
510 hdr_len = skb_transport_offset(skb) +
511 tcp_hdrlen(skb);
512
513 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
514 TX_BD_FLAGS_T_IPID |
515 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
516 length = skb_shinfo(skb)->gso_size;
517 txbd1->tx_bd_mss = cpu_to_le32(length);
518 length += hdr_len;
519 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
520 txbd1->tx_bd_hsize_lflags =
521 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
522 txbd1->tx_bd_mss = 0;
523 }
524
525 length >>= 9;
526 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
527 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
528 skb->len);
529 i = 0;
530 goto tx_dma_error;
531 }
532 flags |= bnxt_lhint_arr[length];
533 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
534
535 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
536 txbd1->tx_bd_cfa_action =
537 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
538 for (i = 0; i < last_frag; i++) {
539 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
540
541 prod = NEXT_TX(prod);
542 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
543
544 len = skb_frag_size(frag);
545 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
546 DMA_TO_DEVICE);
547
548 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
549 goto tx_dma_error;
550
551 tx_buf = &txr->tx_buf_ring[prod];
552 dma_unmap_addr_set(tx_buf, mapping, mapping);
553
554 txbd->tx_bd_haddr = cpu_to_le64(mapping);
555
556 flags = len << TX_BD_LEN_SHIFT;
557 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
558 }
559
560 flags &= ~TX_BD_LEN;
561 txbd->tx_bd_len_flags_type =
562 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
563 TX_BD_FLAGS_PACKET_END);
564
565 netdev_tx_sent_queue(txq, skb->len);
566
567
568 wmb();
569
570 prod = NEXT_TX(prod);
571 txr->tx_prod = prod;
572
573 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
574 bnxt_db_write(bp, &txr->tx_db, prod);
575
576 tx_done:
577
578 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
579 if (netdev_xmit_more() && !tx_buf->is_push)
580 bnxt_db_write(bp, &txr->tx_db, prod);
581
582 netif_tx_stop_queue(txq);
583
584
585
586
587
588
589 smp_mb();
590 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
591 netif_tx_wake_queue(txq);
592 }
593 return NETDEV_TX_OK;
594
595 tx_dma_error:
596 last_frag = i;
597
598
599 prod = txr->tx_prod;
600 tx_buf = &txr->tx_buf_ring[prod];
601 tx_buf->skb = NULL;
602 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
603 skb_headlen(skb), PCI_DMA_TODEVICE);
604 prod = NEXT_TX(prod);
605
606
607 for (i = 0; i < last_frag; i++) {
608 prod = NEXT_TX(prod);
609 tx_buf = &txr->tx_buf_ring[prod];
610 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
611 skb_frag_size(&skb_shinfo(skb)->frags[i]),
612 PCI_DMA_TODEVICE);
613 }
614
615 dev_kfree_skb_any(skb);
616 return NETDEV_TX_OK;
617 }
618
619 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
620 {
621 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
622 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
623 u16 cons = txr->tx_cons;
624 struct pci_dev *pdev = bp->pdev;
625 int i;
626 unsigned int tx_bytes = 0;
627
628 for (i = 0; i < nr_pkts; i++) {
629 struct bnxt_sw_tx_bd *tx_buf;
630 struct sk_buff *skb;
631 int j, last;
632
633 tx_buf = &txr->tx_buf_ring[cons];
634 cons = NEXT_TX(cons);
635 skb = tx_buf->skb;
636 tx_buf->skb = NULL;
637
638 if (tx_buf->is_push) {
639 tx_buf->is_push = 0;
640 goto next_tx_int;
641 }
642
643 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
644 skb_headlen(skb), PCI_DMA_TODEVICE);
645 last = tx_buf->nr_frags;
646
647 for (j = 0; j < last; j++) {
648 cons = NEXT_TX(cons);
649 tx_buf = &txr->tx_buf_ring[cons];
650 dma_unmap_page(
651 &pdev->dev,
652 dma_unmap_addr(tx_buf, mapping),
653 skb_frag_size(&skb_shinfo(skb)->frags[j]),
654 PCI_DMA_TODEVICE);
655 }
656
657 next_tx_int:
658 cons = NEXT_TX(cons);
659
660 tx_bytes += skb->len;
661 dev_kfree_skb_any(skb);
662 }
663
664 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
665 txr->tx_cons = cons;
666
667
668
669
670
671
672 smp_mb();
673
674 if (unlikely(netif_tx_queue_stopped(txq)) &&
675 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
676 __netif_tx_lock(txq, smp_processor_id());
677 if (netif_tx_queue_stopped(txq) &&
678 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
679 txr->dev_state != BNXT_DEV_STATE_CLOSING)
680 netif_tx_wake_queue(txq);
681 __netif_tx_unlock(txq);
682 }
683 }
684
685 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
686 struct bnxt_rx_ring_info *rxr,
687 gfp_t gfp)
688 {
689 struct device *dev = &bp->pdev->dev;
690 struct page *page;
691
692 page = page_pool_dev_alloc_pages(rxr->page_pool);
693 if (!page)
694 return NULL;
695
696 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
697 DMA_ATTR_WEAK_ORDERING);
698 if (dma_mapping_error(dev, *mapping)) {
699 page_pool_recycle_direct(rxr->page_pool, page);
700 return NULL;
701 }
702 *mapping += bp->rx_dma_offset;
703 return page;
704 }
705
706 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
707 gfp_t gfp)
708 {
709 u8 *data;
710 struct pci_dev *pdev = bp->pdev;
711
712 data = kmalloc(bp->rx_buf_size, gfp);
713 if (!data)
714 return NULL;
715
716 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
717 bp->rx_buf_use_size, bp->rx_dir,
718 DMA_ATTR_WEAK_ORDERING);
719
720 if (dma_mapping_error(&pdev->dev, *mapping)) {
721 kfree(data);
722 data = NULL;
723 }
724 return data;
725 }
726
727 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
728 u16 prod, gfp_t gfp)
729 {
730 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
731 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
732 dma_addr_t mapping;
733
734 if (BNXT_RX_PAGE_MODE(bp)) {
735 struct page *page =
736 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
737
738 if (!page)
739 return -ENOMEM;
740
741 rx_buf->data = page;
742 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
743 } else {
744 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
745
746 if (!data)
747 return -ENOMEM;
748
749 rx_buf->data = data;
750 rx_buf->data_ptr = data + bp->rx_offset;
751 }
752 rx_buf->mapping = mapping;
753
754 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
755 return 0;
756 }
757
758 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
759 {
760 u16 prod = rxr->rx_prod;
761 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
762 struct rx_bd *cons_bd, *prod_bd;
763
764 prod_rx_buf = &rxr->rx_buf_ring[prod];
765 cons_rx_buf = &rxr->rx_buf_ring[cons];
766
767 prod_rx_buf->data = data;
768 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
769
770 prod_rx_buf->mapping = cons_rx_buf->mapping;
771
772 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
773 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
774
775 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
776 }
777
778 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
779 {
780 u16 next, max = rxr->rx_agg_bmap_size;
781
782 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
783 if (next >= max)
784 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
785 return next;
786 }
787
788 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
789 struct bnxt_rx_ring_info *rxr,
790 u16 prod, gfp_t gfp)
791 {
792 struct rx_bd *rxbd =
793 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
794 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
795 struct pci_dev *pdev = bp->pdev;
796 struct page *page;
797 dma_addr_t mapping;
798 u16 sw_prod = rxr->rx_sw_agg_prod;
799 unsigned int offset = 0;
800
801 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
802 page = rxr->rx_page;
803 if (!page) {
804 page = alloc_page(gfp);
805 if (!page)
806 return -ENOMEM;
807 rxr->rx_page = page;
808 rxr->rx_page_offset = 0;
809 }
810 offset = rxr->rx_page_offset;
811 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
812 if (rxr->rx_page_offset == PAGE_SIZE)
813 rxr->rx_page = NULL;
814 else
815 get_page(page);
816 } else {
817 page = alloc_page(gfp);
818 if (!page)
819 return -ENOMEM;
820 }
821
822 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
823 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
824 DMA_ATTR_WEAK_ORDERING);
825 if (dma_mapping_error(&pdev->dev, mapping)) {
826 __free_page(page);
827 return -EIO;
828 }
829
830 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
831 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
832
833 __set_bit(sw_prod, rxr->rx_agg_bmap);
834 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
835 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
836
837 rx_agg_buf->page = page;
838 rx_agg_buf->offset = offset;
839 rx_agg_buf->mapping = mapping;
840 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
841 rxbd->rx_bd_opaque = sw_prod;
842 return 0;
843 }
844
845 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp,
846 struct bnxt_cp_ring_info *cpr,
847 u16 cp_cons, u16 curr)
848 {
849 struct rx_agg_cmp *agg;
850
851 cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr));
852 agg = (struct rx_agg_cmp *)
853 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
854 return agg;
855 }
856
857 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp,
858 struct bnxt_rx_ring_info *rxr,
859 u16 agg_id, u16 curr)
860 {
861 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id];
862
863 return &tpa_info->agg_arr[curr];
864 }
865
866 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx,
867 u16 start, u32 agg_bufs, bool tpa)
868 {
869 struct bnxt_napi *bnapi = cpr->bnapi;
870 struct bnxt *bp = bnapi->bp;
871 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
872 u16 prod = rxr->rx_agg_prod;
873 u16 sw_prod = rxr->rx_sw_agg_prod;
874 bool p5_tpa = false;
875 u32 i;
876
877 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
878 p5_tpa = true;
879
880 for (i = 0; i < agg_bufs; i++) {
881 u16 cons;
882 struct rx_agg_cmp *agg;
883 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
884 struct rx_bd *prod_bd;
885 struct page *page;
886
887 if (p5_tpa)
888 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i);
889 else
890 agg = bnxt_get_agg(bp, cpr, idx, start + i);
891 cons = agg->rx_agg_cmp_opaque;
892 __clear_bit(cons, rxr->rx_agg_bmap);
893
894 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
895 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
896
897 __set_bit(sw_prod, rxr->rx_agg_bmap);
898 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
899 cons_rx_buf = &rxr->rx_agg_ring[cons];
900
901
902
903
904 page = cons_rx_buf->page;
905 cons_rx_buf->page = NULL;
906 prod_rx_buf->page = page;
907 prod_rx_buf->offset = cons_rx_buf->offset;
908
909 prod_rx_buf->mapping = cons_rx_buf->mapping;
910
911 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
912
913 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
914 prod_bd->rx_bd_opaque = sw_prod;
915
916 prod = NEXT_RX_AGG(prod);
917 sw_prod = NEXT_RX_AGG(sw_prod);
918 }
919 rxr->rx_agg_prod = prod;
920 rxr->rx_sw_agg_prod = sw_prod;
921 }
922
923 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
924 struct bnxt_rx_ring_info *rxr,
925 u16 cons, void *data, u8 *data_ptr,
926 dma_addr_t dma_addr,
927 unsigned int offset_and_len)
928 {
929 unsigned int payload = offset_and_len >> 16;
930 unsigned int len = offset_and_len & 0xffff;
931 skb_frag_t *frag;
932 struct page *page = data;
933 u16 prod = rxr->rx_prod;
934 struct sk_buff *skb;
935 int off, err;
936
937 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
938 if (unlikely(err)) {
939 bnxt_reuse_rx_data(rxr, cons, data);
940 return NULL;
941 }
942 dma_addr -= bp->rx_dma_offset;
943 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
944 DMA_ATTR_WEAK_ORDERING);
945 page_pool_release_page(rxr->page_pool, page);
946
947 if (unlikely(!payload))
948 payload = eth_get_headlen(bp->dev, data_ptr, len);
949
950 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
951 if (!skb) {
952 __free_page(page);
953 return NULL;
954 }
955
956 off = (void *)data_ptr - page_address(page);
957 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
958 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
959 payload + NET_IP_ALIGN);
960
961 frag = &skb_shinfo(skb)->frags[0];
962 skb_frag_size_sub(frag, payload);
963 skb_frag_off_add(frag, payload);
964 skb->data_len -= payload;
965 skb->tail += payload;
966
967 return skb;
968 }
969
970 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
971 struct bnxt_rx_ring_info *rxr, u16 cons,
972 void *data, u8 *data_ptr,
973 dma_addr_t dma_addr,
974 unsigned int offset_and_len)
975 {
976 u16 prod = rxr->rx_prod;
977 struct sk_buff *skb;
978 int err;
979
980 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
981 if (unlikely(err)) {
982 bnxt_reuse_rx_data(rxr, cons, data);
983 return NULL;
984 }
985
986 skb = build_skb(data, 0);
987 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
988 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
989 if (!skb) {
990 kfree(data);
991 return NULL;
992 }
993
994 skb_reserve(skb, bp->rx_offset);
995 skb_put(skb, offset_and_len & 0xffff);
996 return skb;
997 }
998
999 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
1000 struct bnxt_cp_ring_info *cpr,
1001 struct sk_buff *skb, u16 idx,
1002 u32 agg_bufs, bool tpa)
1003 {
1004 struct bnxt_napi *bnapi = cpr->bnapi;
1005 struct pci_dev *pdev = bp->pdev;
1006 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1007 u16 prod = rxr->rx_agg_prod;
1008 bool p5_tpa = false;
1009 u32 i;
1010
1011 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
1012 p5_tpa = true;
1013
1014 for (i = 0; i < agg_bufs; i++) {
1015 u16 cons, frag_len;
1016 struct rx_agg_cmp *agg;
1017 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
1018 struct page *page;
1019 dma_addr_t mapping;
1020
1021 if (p5_tpa)
1022 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i);
1023 else
1024 agg = bnxt_get_agg(bp, cpr, idx, i);
1025 cons = agg->rx_agg_cmp_opaque;
1026 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
1027 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
1028
1029 cons_rx_buf = &rxr->rx_agg_ring[cons];
1030 skb_fill_page_desc(skb, i, cons_rx_buf->page,
1031 cons_rx_buf->offset, frag_len);
1032 __clear_bit(cons, rxr->rx_agg_bmap);
1033
1034
1035
1036
1037
1038 mapping = cons_rx_buf->mapping;
1039 page = cons_rx_buf->page;
1040 cons_rx_buf->page = NULL;
1041
1042 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
1043 struct skb_shared_info *shinfo;
1044 unsigned int nr_frags;
1045
1046 shinfo = skb_shinfo(skb);
1047 nr_frags = --shinfo->nr_frags;
1048 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
1049
1050 dev_kfree_skb(skb);
1051
1052 cons_rx_buf->page = page;
1053
1054
1055
1056
1057 rxr->rx_agg_prod = prod;
1058 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa);
1059 return NULL;
1060 }
1061
1062 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1063 PCI_DMA_FROMDEVICE,
1064 DMA_ATTR_WEAK_ORDERING);
1065
1066 skb->data_len += frag_len;
1067 skb->len += frag_len;
1068 skb->truesize += PAGE_SIZE;
1069
1070 prod = NEXT_RX_AGG(prod);
1071 }
1072 rxr->rx_agg_prod = prod;
1073 return skb;
1074 }
1075
1076 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1077 u8 agg_bufs, u32 *raw_cons)
1078 {
1079 u16 last;
1080 struct rx_agg_cmp *agg;
1081
1082 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1083 last = RING_CMP(*raw_cons);
1084 agg = (struct rx_agg_cmp *)
1085 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1086 return RX_AGG_CMP_VALID(agg, *raw_cons);
1087 }
1088
1089 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1090 unsigned int len,
1091 dma_addr_t mapping)
1092 {
1093 struct bnxt *bp = bnapi->bp;
1094 struct pci_dev *pdev = bp->pdev;
1095 struct sk_buff *skb;
1096
1097 skb = napi_alloc_skb(&bnapi->napi, len);
1098 if (!skb)
1099 return NULL;
1100
1101 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1102 bp->rx_dir);
1103
1104 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1105 len + NET_IP_ALIGN);
1106
1107 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1108 bp->rx_dir);
1109
1110 skb_put(skb, len);
1111 return skb;
1112 }
1113
1114 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1115 u32 *raw_cons, void *cmp)
1116 {
1117 struct rx_cmp *rxcmp = cmp;
1118 u32 tmp_raw_cons = *raw_cons;
1119 u8 cmp_type, agg_bufs = 0;
1120
1121 cmp_type = RX_CMP_TYPE(rxcmp);
1122
1123 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1124 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1125 RX_CMP_AGG_BUFS) >>
1126 RX_CMP_AGG_BUFS_SHIFT;
1127 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1128 struct rx_tpa_end_cmp *tpa_end = cmp;
1129
1130 if (bp->flags & BNXT_FLAG_CHIP_P5)
1131 return 0;
1132
1133 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1134 }
1135
1136 if (agg_bufs) {
1137 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1138 return -EBUSY;
1139 }
1140 *raw_cons = tmp_raw_cons;
1141 return 0;
1142 }
1143
1144 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay)
1145 {
1146 if (BNXT_PF(bp))
1147 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay);
1148 else
1149 schedule_delayed_work(&bp->fw_reset_task, delay);
1150 }
1151
1152 static void bnxt_queue_sp_work(struct bnxt *bp)
1153 {
1154 if (BNXT_PF(bp))
1155 queue_work(bnxt_pf_wq, &bp->sp_task);
1156 else
1157 schedule_work(&bp->sp_task);
1158 }
1159
1160 static void bnxt_cancel_sp_work(struct bnxt *bp)
1161 {
1162 if (BNXT_PF(bp))
1163 flush_workqueue(bnxt_pf_wq);
1164 else
1165 cancel_work_sync(&bp->sp_task);
1166 }
1167
1168 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1169 {
1170 if (!rxr->bnapi->in_reset) {
1171 rxr->bnapi->in_reset = true;
1172 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1173 bnxt_queue_sp_work(bp);
1174 }
1175 rxr->rx_next_cons = 0xffff;
1176 }
1177
1178 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1179 {
1180 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1181 u16 idx = agg_id & MAX_TPA_P5_MASK;
1182
1183 if (test_bit(idx, map->agg_idx_bmap))
1184 idx = find_first_zero_bit(map->agg_idx_bmap,
1185 BNXT_AGG_IDX_BMAP_SIZE);
1186 __set_bit(idx, map->agg_idx_bmap);
1187 map->agg_id_tbl[agg_id] = idx;
1188 return idx;
1189 }
1190
1191 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
1192 {
1193 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1194
1195 __clear_bit(idx, map->agg_idx_bmap);
1196 }
1197
1198 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1199 {
1200 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1201
1202 return map->agg_id_tbl[agg_id];
1203 }
1204
1205 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1206 struct rx_tpa_start_cmp *tpa_start,
1207 struct rx_tpa_start_cmp_ext *tpa_start1)
1208 {
1209 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1210 struct bnxt_tpa_info *tpa_info;
1211 u16 cons, prod, agg_id;
1212 struct rx_bd *prod_bd;
1213 dma_addr_t mapping;
1214
1215 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1216 agg_id = TPA_START_AGG_ID_P5(tpa_start);
1217 agg_id = bnxt_alloc_agg_idx(rxr, agg_id);
1218 } else {
1219 agg_id = TPA_START_AGG_ID(tpa_start);
1220 }
1221 cons = tpa_start->rx_tpa_start_cmp_opaque;
1222 prod = rxr->rx_prod;
1223 cons_rx_buf = &rxr->rx_buf_ring[cons];
1224 prod_rx_buf = &rxr->rx_buf_ring[prod];
1225 tpa_info = &rxr->rx_tpa[agg_id];
1226
1227 if (unlikely(cons != rxr->rx_next_cons ||
1228 TPA_START_ERROR(tpa_start))) {
1229 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n",
1230 cons, rxr->rx_next_cons,
1231 TPA_START_ERROR_CODE(tpa_start1));
1232 bnxt_sched_reset(bp, rxr);
1233 return;
1234 }
1235
1236
1237
1238 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1239 prod_rx_buf->data = tpa_info->data;
1240 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1241
1242 mapping = tpa_info->mapping;
1243 prod_rx_buf->mapping = mapping;
1244
1245 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1246
1247 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1248
1249 tpa_info->data = cons_rx_buf->data;
1250 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1251 cons_rx_buf->data = NULL;
1252 tpa_info->mapping = cons_rx_buf->mapping;
1253
1254 tpa_info->len =
1255 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1256 RX_TPA_START_CMP_LEN_SHIFT;
1257 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1258 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1259
1260 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1261 tpa_info->gso_type = SKB_GSO_TCPV4;
1262
1263 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1264 tpa_info->gso_type = SKB_GSO_TCPV6;
1265 tpa_info->rss_hash =
1266 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1267 } else {
1268 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1269 tpa_info->gso_type = 0;
1270 if (netif_msg_rx_err(bp))
1271 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1272 }
1273 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1274 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1275 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1276 tpa_info->agg_count = 0;
1277
1278 rxr->rx_prod = NEXT_RX(prod);
1279 cons = NEXT_RX(cons);
1280 rxr->rx_next_cons = NEXT_RX(cons);
1281 cons_rx_buf = &rxr->rx_buf_ring[cons];
1282
1283 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1284 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1285 cons_rx_buf->data = NULL;
1286 }
1287
1288 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs)
1289 {
1290 if (agg_bufs)
1291 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true);
1292 }
1293
1294 #ifdef CONFIG_INET
1295 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto)
1296 {
1297 struct udphdr *uh = NULL;
1298
1299 if (ip_proto == htons(ETH_P_IP)) {
1300 struct iphdr *iph = (struct iphdr *)skb->data;
1301
1302 if (iph->protocol == IPPROTO_UDP)
1303 uh = (struct udphdr *)(iph + 1);
1304 } else {
1305 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1306
1307 if (iph->nexthdr == IPPROTO_UDP)
1308 uh = (struct udphdr *)(iph + 1);
1309 }
1310 if (uh) {
1311 if (uh->check)
1312 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM;
1313 else
1314 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1315 }
1316 }
1317 #endif
1318
1319 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1320 int payload_off, int tcp_ts,
1321 struct sk_buff *skb)
1322 {
1323 #ifdef CONFIG_INET
1324 struct tcphdr *th;
1325 int len, nw_off;
1326 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1327 u32 hdr_info = tpa_info->hdr_info;
1328 bool loopback = false;
1329
1330 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1331 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1332 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1333
1334
1335
1336
1337 if (inner_mac_off == 4) {
1338 loopback = true;
1339 } else if (inner_mac_off > 4) {
1340 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1341 ETH_HLEN - 2));
1342
1343
1344
1345
1346
1347 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1348 loopback = true;
1349 }
1350 if (loopback) {
1351
1352 inner_ip_off -= 4;
1353 inner_mac_off -= 4;
1354 outer_ip_off -= 4;
1355 }
1356
1357 nw_off = inner_ip_off - ETH_HLEN;
1358 skb_set_network_header(skb, nw_off);
1359 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1360 struct ipv6hdr *iph = ipv6_hdr(skb);
1361
1362 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1363 len = skb->len - skb_transport_offset(skb);
1364 th = tcp_hdr(skb);
1365 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1366 } else {
1367 struct iphdr *iph = ip_hdr(skb);
1368
1369 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1370 len = skb->len - skb_transport_offset(skb);
1371 th = tcp_hdr(skb);
1372 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1373 }
1374
1375 if (inner_mac_off) {
1376 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1377 ETH_HLEN - 2));
1378
1379 bnxt_gro_tunnel(skb, proto);
1380 }
1381 #endif
1382 return skb;
1383 }
1384
1385 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info,
1386 int payload_off, int tcp_ts,
1387 struct sk_buff *skb)
1388 {
1389 #ifdef CONFIG_INET
1390 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1391 u32 hdr_info = tpa_info->hdr_info;
1392 int iphdr_len, nw_off;
1393
1394 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1395 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1396 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1397
1398 nw_off = inner_ip_off - ETH_HLEN;
1399 skb_set_network_header(skb, nw_off);
1400 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ?
1401 sizeof(struct ipv6hdr) : sizeof(struct iphdr);
1402 skb_set_transport_header(skb, nw_off + iphdr_len);
1403
1404 if (inner_mac_off) {
1405 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1406 ETH_HLEN - 2));
1407
1408 bnxt_gro_tunnel(skb, proto);
1409 }
1410 #endif
1411 return skb;
1412 }
1413
1414 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1415 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1416
1417 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1418 int payload_off, int tcp_ts,
1419 struct sk_buff *skb)
1420 {
1421 #ifdef CONFIG_INET
1422 struct tcphdr *th;
1423 int len, nw_off, tcp_opt_len = 0;
1424
1425 if (tcp_ts)
1426 tcp_opt_len = 12;
1427
1428 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1429 struct iphdr *iph;
1430
1431 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1432 ETH_HLEN;
1433 skb_set_network_header(skb, nw_off);
1434 iph = ip_hdr(skb);
1435 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1436 len = skb->len - skb_transport_offset(skb);
1437 th = tcp_hdr(skb);
1438 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1439 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1440 struct ipv6hdr *iph;
1441
1442 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1443 ETH_HLEN;
1444 skb_set_network_header(skb, nw_off);
1445 iph = ipv6_hdr(skb);
1446 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1447 len = skb->len - skb_transport_offset(skb);
1448 th = tcp_hdr(skb);
1449 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1450 } else {
1451 dev_kfree_skb_any(skb);
1452 return NULL;
1453 }
1454
1455 if (nw_off)
1456 bnxt_gro_tunnel(skb, skb->protocol);
1457 #endif
1458 return skb;
1459 }
1460
1461 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1462 struct bnxt_tpa_info *tpa_info,
1463 struct rx_tpa_end_cmp *tpa_end,
1464 struct rx_tpa_end_cmp_ext *tpa_end1,
1465 struct sk_buff *skb)
1466 {
1467 #ifdef CONFIG_INET
1468 int payload_off;
1469 u16 segs;
1470
1471 segs = TPA_END_TPA_SEGS(tpa_end);
1472 if (segs == 1)
1473 return skb;
1474
1475 NAPI_GRO_CB(skb)->count = segs;
1476 skb_shinfo(skb)->gso_size =
1477 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1478 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1479 if (bp->flags & BNXT_FLAG_CHIP_P5)
1480 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1);
1481 else
1482 payload_off = TPA_END_PAYLOAD_OFF(tpa_end);
1483 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1484 if (likely(skb))
1485 tcp_gro_complete(skb);
1486 #endif
1487 return skb;
1488 }
1489
1490
1491
1492
1493 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1494 {
1495 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1496
1497
1498 return dev ? dev : bp->dev;
1499 }
1500
1501 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1502 struct bnxt_cp_ring_info *cpr,
1503 u32 *raw_cons,
1504 struct rx_tpa_end_cmp *tpa_end,
1505 struct rx_tpa_end_cmp_ext *tpa_end1,
1506 u8 *event)
1507 {
1508 struct bnxt_napi *bnapi = cpr->bnapi;
1509 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1510 u8 *data_ptr, agg_bufs;
1511 unsigned int len;
1512 struct bnxt_tpa_info *tpa_info;
1513 dma_addr_t mapping;
1514 struct sk_buff *skb;
1515 u16 idx = 0, agg_id;
1516 void *data;
1517 bool gro;
1518
1519 if (unlikely(bnapi->in_reset)) {
1520 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1521
1522 if (rc < 0)
1523 return ERR_PTR(-EBUSY);
1524 return NULL;
1525 }
1526
1527 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1528 agg_id = TPA_END_AGG_ID_P5(tpa_end);
1529 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1530 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1);
1531 tpa_info = &rxr->rx_tpa[agg_id];
1532 if (unlikely(agg_bufs != tpa_info->agg_count)) {
1533 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n",
1534 agg_bufs, tpa_info->agg_count);
1535 agg_bufs = tpa_info->agg_count;
1536 }
1537 tpa_info->agg_count = 0;
1538 *event |= BNXT_AGG_EVENT;
1539 bnxt_free_agg_idx(rxr, agg_id);
1540 idx = agg_id;
1541 gro = !!(bp->flags & BNXT_FLAG_GRO);
1542 } else {
1543 agg_id = TPA_END_AGG_ID(tpa_end);
1544 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1545 tpa_info = &rxr->rx_tpa[agg_id];
1546 idx = RING_CMP(*raw_cons);
1547 if (agg_bufs) {
1548 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1549 return ERR_PTR(-EBUSY);
1550
1551 *event |= BNXT_AGG_EVENT;
1552 idx = NEXT_CMP(idx);
1553 }
1554 gro = !!TPA_END_GRO(tpa_end);
1555 }
1556 data = tpa_info->data;
1557 data_ptr = tpa_info->data_ptr;
1558 prefetch(data_ptr);
1559 len = tpa_info->len;
1560 mapping = tpa_info->mapping;
1561
1562 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1563 bnxt_abort_tpa(cpr, idx, agg_bufs);
1564 if (agg_bufs > MAX_SKB_FRAGS)
1565 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1566 agg_bufs, (int)MAX_SKB_FRAGS);
1567 return NULL;
1568 }
1569
1570 if (len <= bp->rx_copy_thresh) {
1571 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1572 if (!skb) {
1573 bnxt_abort_tpa(cpr, idx, agg_bufs);
1574 return NULL;
1575 }
1576 } else {
1577 u8 *new_data;
1578 dma_addr_t new_mapping;
1579
1580 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1581 if (!new_data) {
1582 bnxt_abort_tpa(cpr, idx, agg_bufs);
1583 return NULL;
1584 }
1585
1586 tpa_info->data = new_data;
1587 tpa_info->data_ptr = new_data + bp->rx_offset;
1588 tpa_info->mapping = new_mapping;
1589
1590 skb = build_skb(data, 0);
1591 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1592 bp->rx_buf_use_size, bp->rx_dir,
1593 DMA_ATTR_WEAK_ORDERING);
1594
1595 if (!skb) {
1596 kfree(data);
1597 bnxt_abort_tpa(cpr, idx, agg_bufs);
1598 return NULL;
1599 }
1600 skb_reserve(skb, bp->rx_offset);
1601 skb_put(skb, len);
1602 }
1603
1604 if (agg_bufs) {
1605 skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true);
1606 if (!skb) {
1607
1608 return NULL;
1609 }
1610 }
1611
1612 skb->protocol =
1613 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1614
1615 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1616 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1617
1618 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1619 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1620 u16 vlan_proto = tpa_info->metadata >>
1621 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1622 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1623
1624 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1625 }
1626
1627 skb_checksum_none_assert(skb);
1628 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1629 skb->ip_summed = CHECKSUM_UNNECESSARY;
1630 skb->csum_level =
1631 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1632 }
1633
1634 if (gro)
1635 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1636
1637 return skb;
1638 }
1639
1640 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1641 struct rx_agg_cmp *rx_agg)
1642 {
1643 u16 agg_id = TPA_AGG_AGG_ID(rx_agg);
1644 struct bnxt_tpa_info *tpa_info;
1645
1646 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1647 tpa_info = &rxr->rx_tpa[agg_id];
1648 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS);
1649 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
1650 }
1651
1652 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1653 struct sk_buff *skb)
1654 {
1655 if (skb->dev != bp->dev) {
1656
1657 bnxt_vf_rep_rx(bp, skb);
1658 return;
1659 }
1660 skb_record_rx_queue(skb, bnapi->index);
1661 napi_gro_receive(&bnapi->napi, skb);
1662 }
1663
1664
1665
1666
1667
1668
1669
1670
1671 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1672 u32 *raw_cons, u8 *event)
1673 {
1674 struct bnxt_napi *bnapi = cpr->bnapi;
1675 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1676 struct net_device *dev = bp->dev;
1677 struct rx_cmp *rxcmp;
1678 struct rx_cmp_ext *rxcmp1;
1679 u32 tmp_raw_cons = *raw_cons;
1680 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1681 struct bnxt_sw_rx_bd *rx_buf;
1682 unsigned int len;
1683 u8 *data_ptr, agg_bufs, cmp_type;
1684 dma_addr_t dma_addr;
1685 struct sk_buff *skb;
1686 void *data;
1687 int rc = 0;
1688 u32 misc;
1689
1690 rxcmp = (struct rx_cmp *)
1691 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1692
1693 cmp_type = RX_CMP_TYPE(rxcmp);
1694
1695 if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) {
1696 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp);
1697 goto next_rx_no_prod_no_len;
1698 }
1699
1700 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1701 cp_cons = RING_CMP(tmp_raw_cons);
1702 rxcmp1 = (struct rx_cmp_ext *)
1703 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1704
1705 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1706 return -EBUSY;
1707
1708 prod = rxr->rx_prod;
1709
1710 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1711 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1712 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1713
1714 *event |= BNXT_RX_EVENT;
1715 goto next_rx_no_prod_no_len;
1716
1717 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1718 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1719 (struct rx_tpa_end_cmp *)rxcmp,
1720 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1721
1722 if (IS_ERR(skb))
1723 return -EBUSY;
1724
1725 rc = -ENOMEM;
1726 if (likely(skb)) {
1727 bnxt_deliver_skb(bp, bnapi, skb);
1728 rc = 1;
1729 }
1730 *event |= BNXT_RX_EVENT;
1731 goto next_rx_no_prod_no_len;
1732 }
1733
1734 cons = rxcmp->rx_cmp_opaque;
1735 if (unlikely(cons != rxr->rx_next_cons)) {
1736 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1737
1738 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1739 cons, rxr->rx_next_cons);
1740 bnxt_sched_reset(bp, rxr);
1741 return rc1;
1742 }
1743 rx_buf = &rxr->rx_buf_ring[cons];
1744 data = rx_buf->data;
1745 data_ptr = rx_buf->data_ptr;
1746 prefetch(data_ptr);
1747
1748 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1749 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1750
1751 if (agg_bufs) {
1752 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1753 return -EBUSY;
1754
1755 cp_cons = NEXT_CMP(cp_cons);
1756 *event |= BNXT_AGG_EVENT;
1757 }
1758 *event |= BNXT_RX_EVENT;
1759
1760 rx_buf->data = NULL;
1761 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1762 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1763
1764 bnxt_reuse_rx_data(rxr, cons, data);
1765 if (agg_bufs)
1766 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs,
1767 false);
1768
1769 rc = -EIO;
1770 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1771 bnapi->cp_ring.rx_buf_errors++;
1772 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) {
1773 netdev_warn(bp->dev, "RX buffer error %x\n",
1774 rx_err);
1775 bnxt_sched_reset(bp, rxr);
1776 }
1777 }
1778 goto next_rx_no_len;
1779 }
1780
1781 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1782 dma_addr = rx_buf->mapping;
1783
1784 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1785 rc = 1;
1786 goto next_rx;
1787 }
1788
1789 if (len <= bp->rx_copy_thresh) {
1790 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1791 bnxt_reuse_rx_data(rxr, cons, data);
1792 if (!skb) {
1793 if (agg_bufs)
1794 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0,
1795 agg_bufs, false);
1796 rc = -ENOMEM;
1797 goto next_rx;
1798 }
1799 } else {
1800 u32 payload;
1801
1802 if (rx_buf->data_ptr == data_ptr)
1803 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1804 else
1805 payload = 0;
1806 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1807 payload | len);
1808 if (!skb) {
1809 rc = -ENOMEM;
1810 goto next_rx;
1811 }
1812 }
1813
1814 if (agg_bufs) {
1815 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false);
1816 if (!skb) {
1817 rc = -ENOMEM;
1818 goto next_rx;
1819 }
1820 }
1821
1822 if (RX_CMP_HASH_VALID(rxcmp)) {
1823 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1824 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1825
1826
1827 if (hash_type != 1 && hash_type != 3)
1828 type = PKT_HASH_TYPE_L3;
1829 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1830 }
1831
1832 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1833 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1834
1835 if ((rxcmp1->rx_cmp_flags2 &
1836 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1837 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1838 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1839 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1840 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1841
1842 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1843 }
1844
1845 skb_checksum_none_assert(skb);
1846 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1847 if (dev->features & NETIF_F_RXCSUM) {
1848 skb->ip_summed = CHECKSUM_UNNECESSARY;
1849 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1850 }
1851 } else {
1852 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1853 if (dev->features & NETIF_F_RXCSUM)
1854 bnapi->cp_ring.rx_l4_csum_errors++;
1855 }
1856 }
1857
1858 bnxt_deliver_skb(bp, bnapi, skb);
1859 rc = 1;
1860
1861 next_rx:
1862 cpr->rx_packets += 1;
1863 cpr->rx_bytes += len;
1864
1865 next_rx_no_len:
1866 rxr->rx_prod = NEXT_RX(prod);
1867 rxr->rx_next_cons = NEXT_RX(cons);
1868
1869 next_rx_no_prod_no_len:
1870 *raw_cons = tmp_raw_cons;
1871
1872 return rc;
1873 }
1874
1875
1876
1877
1878 static int bnxt_force_rx_discard(struct bnxt *bp,
1879 struct bnxt_cp_ring_info *cpr,
1880 u32 *raw_cons, u8 *event)
1881 {
1882 u32 tmp_raw_cons = *raw_cons;
1883 struct rx_cmp_ext *rxcmp1;
1884 struct rx_cmp *rxcmp;
1885 u16 cp_cons;
1886 u8 cmp_type;
1887
1888 cp_cons = RING_CMP(tmp_raw_cons);
1889 rxcmp = (struct rx_cmp *)
1890 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1891
1892 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1893 cp_cons = RING_CMP(tmp_raw_cons);
1894 rxcmp1 = (struct rx_cmp_ext *)
1895 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1896
1897 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1898 return -EBUSY;
1899
1900 cmp_type = RX_CMP_TYPE(rxcmp);
1901 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1902 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1903 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1904 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1905 struct rx_tpa_end_cmp_ext *tpa_end1;
1906
1907 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1908 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1909 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1910 }
1911 return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1912 }
1913
1914 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx)
1915 {
1916 struct bnxt_fw_health *fw_health = bp->fw_health;
1917 u32 reg = fw_health->regs[reg_idx];
1918 u32 reg_type, reg_off, val = 0;
1919
1920 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
1921 reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
1922 switch (reg_type) {
1923 case BNXT_FW_HEALTH_REG_TYPE_CFG:
1924 pci_read_config_dword(bp->pdev, reg_off, &val);
1925 break;
1926 case BNXT_FW_HEALTH_REG_TYPE_GRC:
1927 reg_off = fw_health->mapped_regs[reg_idx];
1928
1929 case BNXT_FW_HEALTH_REG_TYPE_BAR0:
1930 val = readl(bp->bar0 + reg_off);
1931 break;
1932 case BNXT_FW_HEALTH_REG_TYPE_BAR1:
1933 val = readl(bp->bar1 + reg_off);
1934 break;
1935 }
1936 if (reg_idx == BNXT_FW_RESET_INPROG_REG)
1937 val &= fw_health->fw_reset_inprog_reg_mask;
1938 return val;
1939 }
1940
1941 #define BNXT_GET_EVENT_PORT(data) \
1942 ((data) & \
1943 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1944
1945 static int bnxt_async_event_process(struct bnxt *bp,
1946 struct hwrm_async_event_cmpl *cmpl)
1947 {
1948 u16 event_id = le16_to_cpu(cmpl->event_id);
1949
1950
1951 switch (event_id) {
1952 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1953 u32 data1 = le32_to_cpu(cmpl->event_data1);
1954 struct bnxt_link_info *link_info = &bp->link_info;
1955
1956 if (BNXT_VF(bp))
1957 goto async_event_process_exit;
1958
1959
1960 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1961 (data1 & 0x20000)) {
1962 u16 fw_speed = link_info->force_link_speed;
1963 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1964
1965 if (speed != SPEED_UNKNOWN)
1966 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1967 speed);
1968 }
1969 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1970 }
1971
1972 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1973 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1974 break;
1975 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1976 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1977 break;
1978 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1979 u32 data1 = le32_to_cpu(cmpl->event_data1);
1980 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1981
1982 if (BNXT_VF(bp))
1983 break;
1984
1985 if (bp->pf.port_id != port_id)
1986 break;
1987
1988 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1989 break;
1990 }
1991 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1992 if (BNXT_PF(bp))
1993 goto async_event_process_exit;
1994 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1995 break;
1996 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: {
1997 u32 data1 = le32_to_cpu(cmpl->event_data1);
1998
1999 if (!bp->fw_health)
2000 goto async_event_process_exit;
2001
2002 bp->fw_reset_timestamp = jiffies;
2003 bp->fw_reset_min_dsecs = cmpl->timestamp_lo;
2004 if (!bp->fw_reset_min_dsecs)
2005 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS;
2006 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi);
2007 if (!bp->fw_reset_max_dsecs)
2008 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS;
2009 if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) {
2010 netdev_warn(bp->dev, "Firmware fatal reset event received\n");
2011 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
2012 } else {
2013 netdev_warn(bp->dev, "Firmware non-fatal reset event received, max wait time %d msec\n",
2014 bp->fw_reset_max_dsecs * 100);
2015 }
2016 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event);
2017 break;
2018 }
2019 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: {
2020 struct bnxt_fw_health *fw_health = bp->fw_health;
2021 u32 data1 = le32_to_cpu(cmpl->event_data1);
2022
2023 if (!fw_health)
2024 goto async_event_process_exit;
2025
2026 fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1);
2027 fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1);
2028 if (!fw_health->enabled)
2029 break;
2030
2031 if (netif_msg_drv(bp))
2032 netdev_info(bp->dev, "Error recovery info: error recovery[%d], master[%d], reset count[0x%x], health status: 0x%x\n",
2033 fw_health->enabled, fw_health->master,
2034 bnxt_fw_health_readl(bp,
2035 BNXT_FW_RESET_CNT_REG),
2036 bnxt_fw_health_readl(bp,
2037 BNXT_FW_HEALTH_REG));
2038 fw_health->tmr_multiplier =
2039 DIV_ROUND_UP(fw_health->polling_dsecs * HZ,
2040 bp->current_interval * 10);
2041 fw_health->tmr_counter = fw_health->tmr_multiplier;
2042 fw_health->last_fw_heartbeat =
2043 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
2044 fw_health->last_fw_reset_cnt =
2045 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
2046 goto async_event_process_exit;
2047 }
2048 default:
2049 goto async_event_process_exit;
2050 }
2051 bnxt_queue_sp_work(bp);
2052 async_event_process_exit:
2053 bnxt_ulp_async_events(bp, cmpl);
2054 return 0;
2055 }
2056
2057 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
2058 {
2059 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
2060 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
2061 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
2062 (struct hwrm_fwd_req_cmpl *)txcmp;
2063
2064 switch (cmpl_type) {
2065 case CMPL_BASE_TYPE_HWRM_DONE:
2066 seq_id = le16_to_cpu(h_cmpl->sequence_id);
2067 if (seq_id == bp->hwrm_intr_seq_id)
2068 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
2069 else
2070 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
2071 break;
2072
2073 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
2074 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
2075
2076 if ((vf_id < bp->pf.first_vf_id) ||
2077 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
2078 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
2079 vf_id);
2080 return -EINVAL;
2081 }
2082
2083 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
2084 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
2085 bnxt_queue_sp_work(bp);
2086 break;
2087
2088 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
2089 bnxt_async_event_process(bp,
2090 (struct hwrm_async_event_cmpl *)txcmp);
2091
2092 default:
2093 break;
2094 }
2095
2096 return 0;
2097 }
2098
2099 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
2100 {
2101 struct bnxt_napi *bnapi = dev_instance;
2102 struct bnxt *bp = bnapi->bp;
2103 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2104 u32 cons = RING_CMP(cpr->cp_raw_cons);
2105
2106 cpr->event_ctr++;
2107 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2108 napi_schedule(&bnapi->napi);
2109 return IRQ_HANDLED;
2110 }
2111
2112 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2113 {
2114 u32 raw_cons = cpr->cp_raw_cons;
2115 u16 cons = RING_CMP(raw_cons);
2116 struct tx_cmp *txcmp;
2117
2118 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2119
2120 return TX_CMP_VALID(txcmp, raw_cons);
2121 }
2122
2123 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
2124 {
2125 struct bnxt_napi *bnapi = dev_instance;
2126 struct bnxt *bp = bnapi->bp;
2127 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2128 u32 cons = RING_CMP(cpr->cp_raw_cons);
2129 u32 int_status;
2130
2131 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2132
2133 if (!bnxt_has_work(bp, cpr)) {
2134 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
2135
2136 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
2137 return IRQ_NONE;
2138 }
2139
2140
2141 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
2142
2143
2144 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2145 return IRQ_HANDLED;
2146
2147 napi_schedule(&bnapi->napi);
2148 return IRQ_HANDLED;
2149 }
2150
2151 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2152 int budget)
2153 {
2154 struct bnxt_napi *bnapi = cpr->bnapi;
2155 u32 raw_cons = cpr->cp_raw_cons;
2156 u32 cons;
2157 int tx_pkts = 0;
2158 int rx_pkts = 0;
2159 u8 event = 0;
2160 struct tx_cmp *txcmp;
2161
2162 cpr->has_more_work = 0;
2163 while (1) {
2164 int rc;
2165
2166 cons = RING_CMP(raw_cons);
2167 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2168
2169 if (!TX_CMP_VALID(txcmp, raw_cons))
2170 break;
2171
2172
2173
2174
2175 dma_rmb();
2176 cpr->had_work_done = 1;
2177 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
2178 tx_pkts++;
2179
2180 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
2181 rx_pkts = budget;
2182 raw_cons = NEXT_RAW_CMP(raw_cons);
2183 if (budget)
2184 cpr->has_more_work = 1;
2185 break;
2186 }
2187 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2188 if (likely(budget))
2189 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2190 else
2191 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
2192 &event);
2193 if (likely(rc >= 0))
2194 rx_pkts += rc;
2195
2196
2197
2198
2199
2200 else if (rc == -ENOMEM && budget)
2201 rx_pkts++;
2202 else if (rc == -EBUSY)
2203 break;
2204 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
2205 CMPL_BASE_TYPE_HWRM_DONE) ||
2206 (TX_CMP_TYPE(txcmp) ==
2207 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
2208 (TX_CMP_TYPE(txcmp) ==
2209 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
2210 bnxt_hwrm_handler(bp, txcmp);
2211 }
2212 raw_cons = NEXT_RAW_CMP(raw_cons);
2213
2214 if (rx_pkts && rx_pkts == budget) {
2215 cpr->has_more_work = 1;
2216 break;
2217 }
2218 }
2219
2220 if (event & BNXT_REDIRECT_EVENT)
2221 xdp_do_flush_map();
2222
2223 if (event & BNXT_TX_EVENT) {
2224 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
2225 u16 prod = txr->tx_prod;
2226
2227
2228 wmb();
2229
2230 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2231 }
2232
2233 cpr->cp_raw_cons = raw_cons;
2234 bnapi->tx_pkts += tx_pkts;
2235 bnapi->events |= event;
2236 return rx_pkts;
2237 }
2238
2239 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2240 {
2241 if (bnapi->tx_pkts) {
2242 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2243 bnapi->tx_pkts = 0;
2244 }
2245
2246 if (bnapi->events & BNXT_RX_EVENT) {
2247 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2248
2249 if (bnapi->events & BNXT_AGG_EVENT)
2250 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2251 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2252 }
2253 bnapi->events = 0;
2254 }
2255
2256 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2257 int budget)
2258 {
2259 struct bnxt_napi *bnapi = cpr->bnapi;
2260 int rx_pkts;
2261
2262 rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2263
2264
2265
2266
2267
2268 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2269
2270 __bnxt_poll_work_done(bp, bnapi);
2271 return rx_pkts;
2272 }
2273
2274 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2275 {
2276 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2277 struct bnxt *bp = bnapi->bp;
2278 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2279 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2280 struct tx_cmp *txcmp;
2281 struct rx_cmp_ext *rxcmp1;
2282 u32 cp_cons, tmp_raw_cons;
2283 u32 raw_cons = cpr->cp_raw_cons;
2284 u32 rx_pkts = 0;
2285 u8 event = 0;
2286
2287 while (1) {
2288 int rc;
2289
2290 cp_cons = RING_CMP(raw_cons);
2291 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2292
2293 if (!TX_CMP_VALID(txcmp, raw_cons))
2294 break;
2295
2296 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2297 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2298 cp_cons = RING_CMP(tmp_raw_cons);
2299 rxcmp1 = (struct rx_cmp_ext *)
2300 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2301
2302 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2303 break;
2304
2305
2306 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2307 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2308
2309 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2310 if (likely(rc == -EIO) && budget)
2311 rx_pkts++;
2312 else if (rc == -EBUSY)
2313 break;
2314 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2315 CMPL_BASE_TYPE_HWRM_DONE)) {
2316 bnxt_hwrm_handler(bp, txcmp);
2317 } else {
2318 netdev_err(bp->dev,
2319 "Invalid completion received on special ring\n");
2320 }
2321 raw_cons = NEXT_RAW_CMP(raw_cons);
2322
2323 if (rx_pkts == budget)
2324 break;
2325 }
2326
2327 cpr->cp_raw_cons = raw_cons;
2328 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2329 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2330
2331 if (event & BNXT_AGG_EVENT)
2332 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2333
2334 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2335 napi_complete_done(napi, rx_pkts);
2336 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2337 }
2338 return rx_pkts;
2339 }
2340
2341 static int bnxt_poll(struct napi_struct *napi, int budget)
2342 {
2343 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2344 struct bnxt *bp = bnapi->bp;
2345 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2346 int work_done = 0;
2347
2348 while (1) {
2349 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2350
2351 if (work_done >= budget) {
2352 if (!budget)
2353 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2354 break;
2355 }
2356
2357 if (!bnxt_has_work(bp, cpr)) {
2358 if (napi_complete_done(napi, work_done))
2359 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2360 break;
2361 }
2362 }
2363 if (bp->flags & BNXT_FLAG_DIM) {
2364 struct dim_sample dim_sample = {};
2365
2366 dim_update_sample(cpr->event_ctr,
2367 cpr->rx_packets,
2368 cpr->rx_bytes,
2369 &dim_sample);
2370 net_dim(&cpr->dim, dim_sample);
2371 }
2372 return work_done;
2373 }
2374
2375 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2376 {
2377 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2378 int i, work_done = 0;
2379
2380 for (i = 0; i < 2; i++) {
2381 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2382
2383 if (cpr2) {
2384 work_done += __bnxt_poll_work(bp, cpr2,
2385 budget - work_done);
2386 cpr->has_more_work |= cpr2->has_more_work;
2387 }
2388 }
2389 return work_done;
2390 }
2391
2392 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2393 u64 dbr_type, bool all)
2394 {
2395 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2396 int i;
2397
2398 for (i = 0; i < 2; i++) {
2399 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2400 struct bnxt_db_info *db;
2401
2402 if (cpr2 && (all || cpr2->had_work_done)) {
2403 db = &cpr2->cp_db;
2404 writeq(db->db_key64 | dbr_type |
2405 RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2406 cpr2->had_work_done = 0;
2407 }
2408 }
2409 __bnxt_poll_work_done(bp, bnapi);
2410 }
2411
2412 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2413 {
2414 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2415 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2416 u32 raw_cons = cpr->cp_raw_cons;
2417 struct bnxt *bp = bnapi->bp;
2418 struct nqe_cn *nqcmp;
2419 int work_done = 0;
2420 u32 cons;
2421
2422 if (cpr->has_more_work) {
2423 cpr->has_more_work = 0;
2424 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2425 if (cpr->has_more_work) {
2426 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false);
2427 return work_done;
2428 }
2429 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true);
2430 if (napi_complete_done(napi, work_done))
2431 BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons);
2432 return work_done;
2433 }
2434 while (1) {
2435 cons = RING_CMP(raw_cons);
2436 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2437
2438 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2439 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL,
2440 false);
2441 cpr->cp_raw_cons = raw_cons;
2442 if (napi_complete_done(napi, work_done))
2443 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2444 cpr->cp_raw_cons);
2445 return work_done;
2446 }
2447
2448
2449
2450
2451 dma_rmb();
2452
2453 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2454 u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2455 struct bnxt_cp_ring_info *cpr2;
2456
2457 cpr2 = cpr->cp_ring_arr[idx];
2458 work_done += __bnxt_poll_work(bp, cpr2,
2459 budget - work_done);
2460 cpr->has_more_work = cpr2->has_more_work;
2461 } else {
2462 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2463 }
2464 raw_cons = NEXT_RAW_CMP(raw_cons);
2465 if (cpr->has_more_work)
2466 break;
2467 }
2468 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true);
2469 cpr->cp_raw_cons = raw_cons;
2470 return work_done;
2471 }
2472
2473 static void bnxt_free_tx_skbs(struct bnxt *bp)
2474 {
2475 int i, max_idx;
2476 struct pci_dev *pdev = bp->pdev;
2477
2478 if (!bp->tx_ring)
2479 return;
2480
2481 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2482 for (i = 0; i < bp->tx_nr_rings; i++) {
2483 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2484 int j;
2485
2486 for (j = 0; j < max_idx;) {
2487 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2488 struct sk_buff *skb;
2489 int k, last;
2490
2491 if (i < bp->tx_nr_rings_xdp &&
2492 tx_buf->action == XDP_REDIRECT) {
2493 dma_unmap_single(&pdev->dev,
2494 dma_unmap_addr(tx_buf, mapping),
2495 dma_unmap_len(tx_buf, len),
2496 PCI_DMA_TODEVICE);
2497 xdp_return_frame(tx_buf->xdpf);
2498 tx_buf->action = 0;
2499 tx_buf->xdpf = NULL;
2500 j++;
2501 continue;
2502 }
2503
2504 skb = tx_buf->skb;
2505 if (!skb) {
2506 j++;
2507 continue;
2508 }
2509
2510 tx_buf->skb = NULL;
2511
2512 if (tx_buf->is_push) {
2513 dev_kfree_skb(skb);
2514 j += 2;
2515 continue;
2516 }
2517
2518 dma_unmap_single(&pdev->dev,
2519 dma_unmap_addr(tx_buf, mapping),
2520 skb_headlen(skb),
2521 PCI_DMA_TODEVICE);
2522
2523 last = tx_buf->nr_frags;
2524 j += 2;
2525 for (k = 0; k < last; k++, j++) {
2526 int ring_idx = j & bp->tx_ring_mask;
2527 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2528
2529 tx_buf = &txr->tx_buf_ring[ring_idx];
2530 dma_unmap_page(
2531 &pdev->dev,
2532 dma_unmap_addr(tx_buf, mapping),
2533 skb_frag_size(frag), PCI_DMA_TODEVICE);
2534 }
2535 dev_kfree_skb(skb);
2536 }
2537 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2538 }
2539 }
2540
2541 static void bnxt_free_rx_skbs(struct bnxt *bp)
2542 {
2543 int i, max_idx, max_agg_idx;
2544 struct pci_dev *pdev = bp->pdev;
2545
2546 if (!bp->rx_ring)
2547 return;
2548
2549 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2550 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2551 for (i = 0; i < bp->rx_nr_rings; i++) {
2552 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2553 struct bnxt_tpa_idx_map *map;
2554 int j;
2555
2556 if (rxr->rx_tpa) {
2557 for (j = 0; j < bp->max_tpa; j++) {
2558 struct bnxt_tpa_info *tpa_info =
2559 &rxr->rx_tpa[j];
2560 u8 *data = tpa_info->data;
2561
2562 if (!data)
2563 continue;
2564
2565 dma_unmap_single_attrs(&pdev->dev,
2566 tpa_info->mapping,
2567 bp->rx_buf_use_size,
2568 bp->rx_dir,
2569 DMA_ATTR_WEAK_ORDERING);
2570
2571 tpa_info->data = NULL;
2572
2573 kfree(data);
2574 }
2575 }
2576
2577 for (j = 0; j < max_idx; j++) {
2578 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2579 dma_addr_t mapping = rx_buf->mapping;
2580 void *data = rx_buf->data;
2581
2582 if (!data)
2583 continue;
2584
2585 rx_buf->data = NULL;
2586
2587 if (BNXT_RX_PAGE_MODE(bp)) {
2588 mapping -= bp->rx_dma_offset;
2589 dma_unmap_page_attrs(&pdev->dev, mapping,
2590 PAGE_SIZE, bp->rx_dir,
2591 DMA_ATTR_WEAK_ORDERING);
2592 page_pool_recycle_direct(rxr->page_pool, data);
2593 } else {
2594 dma_unmap_single_attrs(&pdev->dev, mapping,
2595 bp->rx_buf_use_size,
2596 bp->rx_dir,
2597 DMA_ATTR_WEAK_ORDERING);
2598 kfree(data);
2599 }
2600 }
2601
2602 for (j = 0; j < max_agg_idx; j++) {
2603 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2604 &rxr->rx_agg_ring[j];
2605 struct page *page = rx_agg_buf->page;
2606
2607 if (!page)
2608 continue;
2609
2610 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2611 BNXT_RX_PAGE_SIZE,
2612 PCI_DMA_FROMDEVICE,
2613 DMA_ATTR_WEAK_ORDERING);
2614
2615 rx_agg_buf->page = NULL;
2616 __clear_bit(j, rxr->rx_agg_bmap);
2617
2618 __free_page(page);
2619 }
2620 if (rxr->rx_page) {
2621 __free_page(rxr->rx_page);
2622 rxr->rx_page = NULL;
2623 }
2624 map = rxr->rx_tpa_idx_map;
2625 if (map)
2626 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap));
2627 }
2628 }
2629
2630 static void bnxt_free_skbs(struct bnxt *bp)
2631 {
2632 bnxt_free_tx_skbs(bp);
2633 bnxt_free_rx_skbs(bp);
2634 }
2635
2636 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2637 {
2638 struct pci_dev *pdev = bp->pdev;
2639 int i;
2640
2641 for (i = 0; i < rmem->nr_pages; i++) {
2642 if (!rmem->pg_arr[i])
2643 continue;
2644
2645 dma_free_coherent(&pdev->dev, rmem->page_size,
2646 rmem->pg_arr[i], rmem->dma_arr[i]);
2647
2648 rmem->pg_arr[i] = NULL;
2649 }
2650 if (rmem->pg_tbl) {
2651 size_t pg_tbl_size = rmem->nr_pages * 8;
2652
2653 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2654 pg_tbl_size = rmem->page_size;
2655 dma_free_coherent(&pdev->dev, pg_tbl_size,
2656 rmem->pg_tbl, rmem->pg_tbl_map);
2657 rmem->pg_tbl = NULL;
2658 }
2659 if (rmem->vmem_size && *rmem->vmem) {
2660 vfree(*rmem->vmem);
2661 *rmem->vmem = NULL;
2662 }
2663 }
2664
2665 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2666 {
2667 struct pci_dev *pdev = bp->pdev;
2668 u64 valid_bit = 0;
2669 int i;
2670
2671 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2672 valid_bit = PTU_PTE_VALID;
2673 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2674 size_t pg_tbl_size = rmem->nr_pages * 8;
2675
2676 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2677 pg_tbl_size = rmem->page_size;
2678 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2679 &rmem->pg_tbl_map,
2680 GFP_KERNEL);
2681 if (!rmem->pg_tbl)
2682 return -ENOMEM;
2683 }
2684
2685 for (i = 0; i < rmem->nr_pages; i++) {
2686 u64 extra_bits = valid_bit;
2687
2688 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2689 rmem->page_size,
2690 &rmem->dma_arr[i],
2691 GFP_KERNEL);
2692 if (!rmem->pg_arr[i])
2693 return -ENOMEM;
2694
2695 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2696 if (i == rmem->nr_pages - 2 &&
2697 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2698 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2699 else if (i == rmem->nr_pages - 1 &&
2700 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2701 extra_bits |= PTU_PTE_LAST;
2702 rmem->pg_tbl[i] =
2703 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2704 }
2705 }
2706
2707 if (rmem->vmem_size) {
2708 *rmem->vmem = vzalloc(rmem->vmem_size);
2709 if (!(*rmem->vmem))
2710 return -ENOMEM;
2711 }
2712 return 0;
2713 }
2714
2715 static void bnxt_free_tpa_info(struct bnxt *bp)
2716 {
2717 int i;
2718
2719 for (i = 0; i < bp->rx_nr_rings; i++) {
2720 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2721
2722 kfree(rxr->rx_tpa_idx_map);
2723 rxr->rx_tpa_idx_map = NULL;
2724 if (rxr->rx_tpa) {
2725 kfree(rxr->rx_tpa[0].agg_arr);
2726 rxr->rx_tpa[0].agg_arr = NULL;
2727 }
2728 kfree(rxr->rx_tpa);
2729 rxr->rx_tpa = NULL;
2730 }
2731 }
2732
2733 static int bnxt_alloc_tpa_info(struct bnxt *bp)
2734 {
2735 int i, j, total_aggs = 0;
2736
2737 bp->max_tpa = MAX_TPA;
2738 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2739 if (!bp->max_tpa_v2)
2740 return 0;
2741 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5);
2742 total_aggs = bp->max_tpa * MAX_SKB_FRAGS;
2743 }
2744
2745 for (i = 0; i < bp->rx_nr_rings; i++) {
2746 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2747 struct rx_agg_cmp *agg;
2748
2749 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info),
2750 GFP_KERNEL);
2751 if (!rxr->rx_tpa)
2752 return -ENOMEM;
2753
2754 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2755 continue;
2756 agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL);
2757 rxr->rx_tpa[0].agg_arr = agg;
2758 if (!agg)
2759 return -ENOMEM;
2760 for (j = 1; j < bp->max_tpa; j++)
2761 rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS;
2762 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map),
2763 GFP_KERNEL);
2764 if (!rxr->rx_tpa_idx_map)
2765 return -ENOMEM;
2766 }
2767 return 0;
2768 }
2769
2770 static void bnxt_free_rx_rings(struct bnxt *bp)
2771 {
2772 int i;
2773
2774 if (!bp->rx_ring)
2775 return;
2776
2777 bnxt_free_tpa_info(bp);
2778 for (i = 0; i < bp->rx_nr_rings; i++) {
2779 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2780 struct bnxt_ring_struct *ring;
2781
2782 if (rxr->xdp_prog)
2783 bpf_prog_put(rxr->xdp_prog);
2784
2785 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2786 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2787
2788 page_pool_destroy(rxr->page_pool);
2789 rxr->page_pool = NULL;
2790
2791 kfree(rxr->rx_agg_bmap);
2792 rxr->rx_agg_bmap = NULL;
2793
2794 ring = &rxr->rx_ring_struct;
2795 bnxt_free_ring(bp, &ring->ring_mem);
2796
2797 ring = &rxr->rx_agg_ring_struct;
2798 bnxt_free_ring(bp, &ring->ring_mem);
2799 }
2800 }
2801
2802 static int bnxt_alloc_rx_page_pool(struct bnxt *bp,
2803 struct bnxt_rx_ring_info *rxr)
2804 {
2805 struct page_pool_params pp = { 0 };
2806
2807 pp.pool_size = bp->rx_ring_size;
2808 pp.nid = dev_to_node(&bp->pdev->dev);
2809 pp.dev = &bp->pdev->dev;
2810 pp.dma_dir = DMA_BIDIRECTIONAL;
2811
2812 rxr->page_pool = page_pool_create(&pp);
2813 if (IS_ERR(rxr->page_pool)) {
2814 int err = PTR_ERR(rxr->page_pool);
2815
2816 rxr->page_pool = NULL;
2817 return err;
2818 }
2819 return 0;
2820 }
2821
2822 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2823 {
2824 int i, rc = 0, agg_rings = 0;
2825
2826 if (!bp->rx_ring)
2827 return -ENOMEM;
2828
2829 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2830 agg_rings = 1;
2831
2832 for (i = 0; i < bp->rx_nr_rings; i++) {
2833 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2834 struct bnxt_ring_struct *ring;
2835
2836 ring = &rxr->rx_ring_struct;
2837
2838 rc = bnxt_alloc_rx_page_pool(bp, rxr);
2839 if (rc)
2840 return rc;
2841
2842 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2843 if (rc < 0)
2844 return rc;
2845
2846 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
2847 MEM_TYPE_PAGE_POOL,
2848 rxr->page_pool);
2849 if (rc) {
2850 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2851 return rc;
2852 }
2853
2854 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2855 if (rc)
2856 return rc;
2857
2858 ring->grp_idx = i;
2859 if (agg_rings) {
2860 u16 mem_size;
2861
2862 ring = &rxr->rx_agg_ring_struct;
2863 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2864 if (rc)
2865 return rc;
2866
2867 ring->grp_idx = i;
2868 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2869 mem_size = rxr->rx_agg_bmap_size / 8;
2870 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2871 if (!rxr->rx_agg_bmap)
2872 return -ENOMEM;
2873 }
2874 }
2875 if (bp->flags & BNXT_FLAG_TPA)
2876 rc = bnxt_alloc_tpa_info(bp);
2877 return rc;
2878 }
2879
2880 static void bnxt_free_tx_rings(struct bnxt *bp)
2881 {
2882 int i;
2883 struct pci_dev *pdev = bp->pdev;
2884
2885 if (!bp->tx_ring)
2886 return;
2887
2888 for (i = 0; i < bp->tx_nr_rings; i++) {
2889 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2890 struct bnxt_ring_struct *ring;
2891
2892 if (txr->tx_push) {
2893 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2894 txr->tx_push, txr->tx_push_mapping);
2895 txr->tx_push = NULL;
2896 }
2897
2898 ring = &txr->tx_ring_struct;
2899
2900 bnxt_free_ring(bp, &ring->ring_mem);
2901 }
2902 }
2903
2904 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2905 {
2906 int i, j, rc;
2907 struct pci_dev *pdev = bp->pdev;
2908
2909 bp->tx_push_size = 0;
2910 if (bp->tx_push_thresh) {
2911 int push_size;
2912
2913 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2914 bp->tx_push_thresh);
2915
2916 if (push_size > 256) {
2917 push_size = 0;
2918 bp->tx_push_thresh = 0;
2919 }
2920
2921 bp->tx_push_size = push_size;
2922 }
2923
2924 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2925 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2926 struct bnxt_ring_struct *ring;
2927 u8 qidx;
2928
2929 ring = &txr->tx_ring_struct;
2930
2931 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2932 if (rc)
2933 return rc;
2934
2935 ring->grp_idx = txr->bnapi->index;
2936 if (bp->tx_push_size) {
2937 dma_addr_t mapping;
2938
2939
2940
2941
2942 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2943 bp->tx_push_size,
2944 &txr->tx_push_mapping,
2945 GFP_KERNEL);
2946
2947 if (!txr->tx_push)
2948 return -ENOMEM;
2949
2950 mapping = txr->tx_push_mapping +
2951 sizeof(struct tx_push_bd);
2952 txr->data_mapping = cpu_to_le64(mapping);
2953 }
2954 qidx = bp->tc_to_qidx[j];
2955 ring->queue_id = bp->q_info[qidx].queue_id;
2956 if (i < bp->tx_nr_rings_xdp)
2957 continue;
2958 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2959 j++;
2960 }
2961 return 0;
2962 }
2963
2964 static void bnxt_free_cp_rings(struct bnxt *bp)
2965 {
2966 int i;
2967
2968 if (!bp->bnapi)
2969 return;
2970
2971 for (i = 0; i < bp->cp_nr_rings; i++) {
2972 struct bnxt_napi *bnapi = bp->bnapi[i];
2973 struct bnxt_cp_ring_info *cpr;
2974 struct bnxt_ring_struct *ring;
2975 int j;
2976
2977 if (!bnapi)
2978 continue;
2979
2980 cpr = &bnapi->cp_ring;
2981 ring = &cpr->cp_ring_struct;
2982
2983 bnxt_free_ring(bp, &ring->ring_mem);
2984
2985 for (j = 0; j < 2; j++) {
2986 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2987
2988 if (cpr2) {
2989 ring = &cpr2->cp_ring_struct;
2990 bnxt_free_ring(bp, &ring->ring_mem);
2991 kfree(cpr2);
2992 cpr->cp_ring_arr[j] = NULL;
2993 }
2994 }
2995 }
2996 }
2997
2998 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
2999 {
3000 struct bnxt_ring_mem_info *rmem;
3001 struct bnxt_ring_struct *ring;
3002 struct bnxt_cp_ring_info *cpr;
3003 int rc;
3004
3005 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
3006 if (!cpr)
3007 return NULL;
3008
3009 ring = &cpr->cp_ring_struct;
3010 rmem = &ring->ring_mem;
3011 rmem->nr_pages = bp->cp_nr_pages;
3012 rmem->page_size = HW_CMPD_RING_SIZE;
3013 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3014 rmem->dma_arr = cpr->cp_desc_mapping;
3015 rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
3016 rc = bnxt_alloc_ring(bp, rmem);
3017 if (rc) {
3018 bnxt_free_ring(bp, rmem);
3019 kfree(cpr);
3020 cpr = NULL;
3021 }
3022 return cpr;
3023 }
3024
3025 static int bnxt_alloc_cp_rings(struct bnxt *bp)
3026 {
3027 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
3028 int i, rc, ulp_base_vec, ulp_msix;
3029
3030 ulp_msix = bnxt_get_ulp_msix_num(bp);
3031 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
3032 for (i = 0; i < bp->cp_nr_rings; i++) {
3033 struct bnxt_napi *bnapi = bp->bnapi[i];
3034 struct bnxt_cp_ring_info *cpr;
3035 struct bnxt_ring_struct *ring;
3036
3037 if (!bnapi)
3038 continue;
3039
3040 cpr = &bnapi->cp_ring;
3041 cpr->bnapi = bnapi;
3042 ring = &cpr->cp_ring_struct;
3043
3044 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3045 if (rc)
3046 return rc;
3047
3048 if (ulp_msix && i >= ulp_base_vec)
3049 ring->map_idx = i + ulp_msix;
3050 else
3051 ring->map_idx = i;
3052
3053 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
3054 continue;
3055
3056 if (i < bp->rx_nr_rings) {
3057 struct bnxt_cp_ring_info *cpr2 =
3058 bnxt_alloc_cp_sub_ring(bp);
3059
3060 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
3061 if (!cpr2)
3062 return -ENOMEM;
3063 cpr2->bnapi = bnapi;
3064 }
3065 if ((sh && i < bp->tx_nr_rings) ||
3066 (!sh && i >= bp->rx_nr_rings)) {
3067 struct bnxt_cp_ring_info *cpr2 =
3068 bnxt_alloc_cp_sub_ring(bp);
3069
3070 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
3071 if (!cpr2)
3072 return -ENOMEM;
3073 cpr2->bnapi = bnapi;
3074 }
3075 }
3076 return 0;
3077 }
3078
3079 static void bnxt_init_ring_struct(struct bnxt *bp)
3080 {
3081 int i;
3082
3083 for (i = 0; i < bp->cp_nr_rings; i++) {
3084 struct bnxt_napi *bnapi = bp->bnapi[i];
3085 struct bnxt_ring_mem_info *rmem;
3086 struct bnxt_cp_ring_info *cpr;
3087 struct bnxt_rx_ring_info *rxr;
3088 struct bnxt_tx_ring_info *txr;
3089 struct bnxt_ring_struct *ring;
3090
3091 if (!bnapi)
3092 continue;
3093
3094 cpr = &bnapi->cp_ring;
3095 ring = &cpr->cp_ring_struct;
3096 rmem = &ring->ring_mem;
3097 rmem->nr_pages = bp->cp_nr_pages;
3098 rmem->page_size = HW_CMPD_RING_SIZE;
3099 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3100 rmem->dma_arr = cpr->cp_desc_mapping;
3101 rmem->vmem_size = 0;
3102
3103 rxr = bnapi->rx_ring;
3104 if (!rxr)
3105 goto skip_rx;
3106
3107 ring = &rxr->rx_ring_struct;
3108 rmem = &ring->ring_mem;
3109 rmem->nr_pages = bp->rx_nr_pages;
3110 rmem->page_size = HW_RXBD_RING_SIZE;
3111 rmem->pg_arr = (void **)rxr->rx_desc_ring;
3112 rmem->dma_arr = rxr->rx_desc_mapping;
3113 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
3114 rmem->vmem = (void **)&rxr->rx_buf_ring;
3115
3116 ring = &rxr->rx_agg_ring_struct;
3117 rmem = &ring->ring_mem;
3118 rmem->nr_pages = bp->rx_agg_nr_pages;
3119 rmem->page_size = HW_RXBD_RING_SIZE;
3120 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
3121 rmem->dma_arr = rxr->rx_agg_desc_mapping;
3122 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
3123 rmem->vmem = (void **)&rxr->rx_agg_ring;
3124
3125 skip_rx:
3126 txr = bnapi->tx_ring;
3127 if (!txr)
3128 continue;
3129
3130 ring = &txr->tx_ring_struct;
3131 rmem = &ring->ring_mem;
3132 rmem->nr_pages = bp->tx_nr_pages;
3133 rmem->page_size = HW_RXBD_RING_SIZE;
3134 rmem->pg_arr = (void **)txr->tx_desc_ring;
3135 rmem->dma_arr = txr->tx_desc_mapping;
3136 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
3137 rmem->vmem = (void **)&txr->tx_buf_ring;
3138 }
3139 }
3140
3141 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
3142 {
3143 int i;
3144 u32 prod;
3145 struct rx_bd **rx_buf_ring;
3146
3147 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
3148 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
3149 int j;
3150 struct rx_bd *rxbd;
3151
3152 rxbd = rx_buf_ring[i];
3153 if (!rxbd)
3154 continue;
3155
3156 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
3157 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
3158 rxbd->rx_bd_opaque = prod;
3159 }
3160 }
3161 }
3162
3163 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
3164 {
3165 struct net_device *dev = bp->dev;
3166 struct bnxt_rx_ring_info *rxr;
3167 struct bnxt_ring_struct *ring;
3168 u32 prod, type;
3169 int i;
3170
3171 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
3172 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
3173
3174 if (NET_IP_ALIGN == 2)
3175 type |= RX_BD_FLAGS_SOP;
3176
3177 rxr = &bp->rx_ring[ring_nr];
3178 ring = &rxr->rx_ring_struct;
3179 bnxt_init_rxbd_pages(ring, type);
3180
3181 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
3182 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
3183 if (IS_ERR(rxr->xdp_prog)) {
3184 int rc = PTR_ERR(rxr->xdp_prog);
3185
3186 rxr->xdp_prog = NULL;
3187 return rc;
3188 }
3189 }
3190 prod = rxr->rx_prod;
3191 for (i = 0; i < bp->rx_ring_size; i++) {
3192 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
3193 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
3194 ring_nr, i, bp->rx_ring_size);
3195 break;
3196 }
3197 prod = NEXT_RX(prod);
3198 }
3199 rxr->rx_prod = prod;
3200 ring->fw_ring_id = INVALID_HW_RING_ID;
3201
3202 ring = &rxr->rx_agg_ring_struct;
3203 ring->fw_ring_id = INVALID_HW_RING_ID;
3204
3205 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
3206 return 0;
3207
3208 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
3209 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
3210
3211 bnxt_init_rxbd_pages(ring, type);
3212
3213 prod = rxr->rx_agg_prod;
3214 for (i = 0; i < bp->rx_agg_ring_size; i++) {
3215 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
3216 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
3217 ring_nr, i, bp->rx_ring_size);
3218 break;
3219 }
3220 prod = NEXT_RX_AGG(prod);
3221 }
3222 rxr->rx_agg_prod = prod;
3223
3224 if (bp->flags & BNXT_FLAG_TPA) {
3225 if (rxr->rx_tpa) {
3226 u8 *data;
3227 dma_addr_t mapping;
3228
3229 for (i = 0; i < bp->max_tpa; i++) {
3230 data = __bnxt_alloc_rx_data(bp, &mapping,
3231 GFP_KERNEL);
3232 if (!data)
3233 return -ENOMEM;
3234
3235 rxr->rx_tpa[i].data = data;
3236 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
3237 rxr->rx_tpa[i].mapping = mapping;
3238 }
3239 } else {
3240 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
3241 return -ENOMEM;
3242 }
3243 }
3244
3245 return 0;
3246 }
3247
3248 static void bnxt_init_cp_rings(struct bnxt *bp)
3249 {
3250 int i, j;
3251
3252 for (i = 0; i < bp->cp_nr_rings; i++) {
3253 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
3254 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3255
3256 ring->fw_ring_id = INVALID_HW_RING_ID;
3257 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3258 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3259 for (j = 0; j < 2; j++) {
3260 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3261
3262 if (!cpr2)
3263 continue;
3264
3265 ring = &cpr2->cp_ring_struct;
3266 ring->fw_ring_id = INVALID_HW_RING_ID;
3267 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3268 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3269 }
3270 }
3271 }
3272
3273 static int bnxt_init_rx_rings(struct bnxt *bp)
3274 {
3275 int i, rc = 0;
3276
3277 if (BNXT_RX_PAGE_MODE(bp)) {
3278 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
3279 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
3280 } else {
3281 bp->rx_offset = BNXT_RX_OFFSET;
3282 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
3283 }
3284
3285 for (i = 0; i < bp->rx_nr_rings; i++) {
3286 rc = bnxt_init_one_rx_ring(bp, i);
3287 if (rc)
3288 break;
3289 }
3290
3291 return rc;
3292 }
3293
3294 static int bnxt_init_tx_rings(struct bnxt *bp)
3295 {
3296 u16 i;
3297
3298 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
3299 MAX_SKB_FRAGS + 1);
3300
3301 for (i = 0; i < bp->tx_nr_rings; i++) {
3302 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3303 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3304
3305 ring->fw_ring_id = INVALID_HW_RING_ID;
3306 }
3307
3308 return 0;
3309 }
3310
3311 static void bnxt_free_ring_grps(struct bnxt *bp)
3312 {
3313 kfree(bp->grp_info);
3314 bp->grp_info = NULL;
3315 }
3316
3317 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
3318 {
3319 int i;
3320
3321 if (irq_re_init) {
3322 bp->grp_info = kcalloc(bp->cp_nr_rings,
3323 sizeof(struct bnxt_ring_grp_info),
3324 GFP_KERNEL);
3325 if (!bp->grp_info)
3326 return -ENOMEM;
3327 }
3328 for (i = 0; i < bp->cp_nr_rings; i++) {
3329 if (irq_re_init)
3330 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3331 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3332 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3333 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3334 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3335 }
3336 return 0;
3337 }
3338
3339 static void bnxt_free_vnics(struct bnxt *bp)
3340 {
3341 kfree(bp->vnic_info);
3342 bp->vnic_info = NULL;
3343 bp->nr_vnics = 0;
3344 }
3345
3346 static int bnxt_alloc_vnics(struct bnxt *bp)
3347 {
3348 int num_vnics = 1;
3349
3350 #ifdef CONFIG_RFS_ACCEL
3351 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
3352 num_vnics += bp->rx_nr_rings;
3353 #endif
3354
3355 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3356 num_vnics++;
3357
3358 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3359 GFP_KERNEL);
3360 if (!bp->vnic_info)
3361 return -ENOMEM;
3362
3363 bp->nr_vnics = num_vnics;
3364 return 0;
3365 }
3366
3367 static void bnxt_init_vnics(struct bnxt *bp)
3368 {
3369 int i;
3370
3371 for (i = 0; i < bp->nr_vnics; i++) {
3372 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3373 int j;
3374
3375 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3376 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3377 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3378
3379 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3380
3381 if (bp->vnic_info[i].rss_hash_key) {
3382 if (i == 0)
3383 prandom_bytes(vnic->rss_hash_key,
3384 HW_HASH_KEY_SIZE);
3385 else
3386 memcpy(vnic->rss_hash_key,
3387 bp->vnic_info[0].rss_hash_key,
3388 HW_HASH_KEY_SIZE);
3389 }
3390 }
3391 }
3392
3393 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3394 {
3395 int pages;
3396
3397 pages = ring_size / desc_per_pg;
3398
3399 if (!pages)
3400 return 1;
3401
3402 pages++;
3403
3404 while (pages & (pages - 1))
3405 pages++;
3406
3407 return pages;
3408 }
3409
3410 void bnxt_set_tpa_flags(struct bnxt *bp)
3411 {
3412 bp->flags &= ~BNXT_FLAG_TPA;
3413 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3414 return;
3415 if (bp->dev->features & NETIF_F_LRO)
3416 bp->flags |= BNXT_FLAG_LRO;
3417 else if (bp->dev->features & NETIF_F_GRO_HW)
3418 bp->flags |= BNXT_FLAG_GRO;
3419 }
3420
3421
3422
3423
3424 void bnxt_set_ring_params(struct bnxt *bp)
3425 {
3426 u32 ring_size, rx_size, rx_space;
3427 u32 agg_factor = 0, agg_ring_size = 0;
3428
3429
3430 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3431
3432 rx_space = rx_size + NET_SKB_PAD +
3433 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3434
3435 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3436 ring_size = bp->rx_ring_size;
3437 bp->rx_agg_ring_size = 0;
3438 bp->rx_agg_nr_pages = 0;
3439
3440 if (bp->flags & BNXT_FLAG_TPA)
3441 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3442
3443 bp->flags &= ~BNXT_FLAG_JUMBO;
3444 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3445 u32 jumbo_factor;
3446
3447 bp->flags |= BNXT_FLAG_JUMBO;
3448 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3449 if (jumbo_factor > agg_factor)
3450 agg_factor = jumbo_factor;
3451 }
3452 agg_ring_size = ring_size * agg_factor;
3453
3454 if (agg_ring_size) {
3455 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3456 RX_DESC_CNT);
3457 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3458 u32 tmp = agg_ring_size;
3459
3460 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3461 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3462 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3463 tmp, agg_ring_size);
3464 }
3465 bp->rx_agg_ring_size = agg_ring_size;
3466 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3467 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3468 rx_space = rx_size + NET_SKB_PAD +
3469 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3470 }
3471
3472 bp->rx_buf_use_size = rx_size;
3473 bp->rx_buf_size = rx_space;
3474
3475 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3476 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3477
3478 ring_size = bp->tx_ring_size;
3479 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3480 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3481
3482 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
3483 bp->cp_ring_size = ring_size;
3484
3485 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3486 if (bp->cp_nr_pages > MAX_CP_PAGES) {
3487 bp->cp_nr_pages = MAX_CP_PAGES;
3488 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3489 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3490 ring_size, bp->cp_ring_size);
3491 }
3492 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3493 bp->cp_ring_mask = bp->cp_bit - 1;
3494 }
3495
3496
3497
3498
3499 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3500 {
3501 if (page_mode) {
3502 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3503 return -EOPNOTSUPP;
3504 bp->dev->max_mtu =
3505 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3506 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3507 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3508 bp->rx_dir = DMA_BIDIRECTIONAL;
3509 bp->rx_skb_func = bnxt_rx_page_skb;
3510
3511 netdev_update_features(bp->dev);
3512 } else {
3513 bp->dev->max_mtu = bp->max_mtu;
3514 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3515 bp->rx_dir = DMA_FROM_DEVICE;
3516 bp->rx_skb_func = bnxt_rx_skb;
3517 }
3518 return 0;
3519 }
3520
3521 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3522 {
3523 int i;
3524 struct bnxt_vnic_info *vnic;
3525 struct pci_dev *pdev = bp->pdev;
3526
3527 if (!bp->vnic_info)
3528 return;
3529
3530 for (i = 0; i < bp->nr_vnics; i++) {
3531 vnic = &bp->vnic_info[i];
3532
3533 kfree(vnic->fw_grp_ids);
3534 vnic->fw_grp_ids = NULL;
3535
3536 kfree(vnic->uc_list);
3537 vnic->uc_list = NULL;
3538
3539 if (vnic->mc_list) {
3540 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3541 vnic->mc_list, vnic->mc_list_mapping);
3542 vnic->mc_list = NULL;
3543 }
3544
3545 if (vnic->rss_table) {
3546 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3547 vnic->rss_table,
3548 vnic->rss_table_dma_addr);
3549 vnic->rss_table = NULL;
3550 }
3551
3552 vnic->rss_hash_key = NULL;
3553 vnic->flags = 0;
3554 }
3555 }
3556
3557 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3558 {
3559 int i, rc = 0, size;
3560 struct bnxt_vnic_info *vnic;
3561 struct pci_dev *pdev = bp->pdev;
3562 int max_rings;
3563
3564 for (i = 0; i < bp->nr_vnics; i++) {
3565 vnic = &bp->vnic_info[i];
3566
3567 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3568 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3569
3570 if (mem_size > 0) {
3571 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3572 if (!vnic->uc_list) {
3573 rc = -ENOMEM;
3574 goto out;
3575 }
3576 }
3577 }
3578
3579 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3580 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3581 vnic->mc_list =
3582 dma_alloc_coherent(&pdev->dev,
3583 vnic->mc_list_size,
3584 &vnic->mc_list_mapping,
3585 GFP_KERNEL);
3586 if (!vnic->mc_list) {
3587 rc = -ENOMEM;
3588 goto out;
3589 }
3590 }
3591
3592 if (bp->flags & BNXT_FLAG_CHIP_P5)
3593 goto vnic_skip_grps;
3594
3595 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3596 max_rings = bp->rx_nr_rings;
3597 else
3598 max_rings = 1;
3599
3600 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3601 if (!vnic->fw_grp_ids) {
3602 rc = -ENOMEM;
3603 goto out;
3604 }
3605 vnic_skip_grps:
3606 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3607 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3608 continue;
3609
3610
3611 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3612 &vnic->rss_table_dma_addr,
3613 GFP_KERNEL);
3614 if (!vnic->rss_table) {
3615 rc = -ENOMEM;
3616 goto out;
3617 }
3618
3619 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3620
3621 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3622 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3623 }
3624 return 0;
3625
3626 out:
3627 return rc;
3628 }
3629
3630 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3631 {
3632 struct pci_dev *pdev = bp->pdev;
3633
3634 if (bp->hwrm_cmd_resp_addr) {
3635 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3636 bp->hwrm_cmd_resp_dma_addr);
3637 bp->hwrm_cmd_resp_addr = NULL;
3638 }
3639
3640 if (bp->hwrm_cmd_kong_resp_addr) {
3641 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3642 bp->hwrm_cmd_kong_resp_addr,
3643 bp->hwrm_cmd_kong_resp_dma_addr);
3644 bp->hwrm_cmd_kong_resp_addr = NULL;
3645 }
3646 }
3647
3648 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3649 {
3650 struct pci_dev *pdev = bp->pdev;
3651
3652 if (bp->hwrm_cmd_kong_resp_addr)
3653 return 0;
3654
3655 bp->hwrm_cmd_kong_resp_addr =
3656 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3657 &bp->hwrm_cmd_kong_resp_dma_addr,
3658 GFP_KERNEL);
3659 if (!bp->hwrm_cmd_kong_resp_addr)
3660 return -ENOMEM;
3661
3662 return 0;
3663 }
3664
3665 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3666 {
3667 struct pci_dev *pdev = bp->pdev;
3668
3669 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3670 &bp->hwrm_cmd_resp_dma_addr,
3671 GFP_KERNEL);
3672 if (!bp->hwrm_cmd_resp_addr)
3673 return -ENOMEM;
3674
3675 return 0;
3676 }
3677
3678 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3679 {
3680 if (bp->hwrm_short_cmd_req_addr) {
3681 struct pci_dev *pdev = bp->pdev;
3682
3683 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3684 bp->hwrm_short_cmd_req_addr,
3685 bp->hwrm_short_cmd_req_dma_addr);
3686 bp->hwrm_short_cmd_req_addr = NULL;
3687 }
3688 }
3689
3690 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3691 {
3692 struct pci_dev *pdev = bp->pdev;
3693
3694 if (bp->hwrm_short_cmd_req_addr)
3695 return 0;
3696
3697 bp->hwrm_short_cmd_req_addr =
3698 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3699 &bp->hwrm_short_cmd_req_dma_addr,
3700 GFP_KERNEL);
3701 if (!bp->hwrm_short_cmd_req_addr)
3702 return -ENOMEM;
3703
3704 return 0;
3705 }
3706
3707 static void bnxt_free_port_stats(struct bnxt *bp)
3708 {
3709 struct pci_dev *pdev = bp->pdev;
3710
3711 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3712 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3713
3714 if (bp->hw_rx_port_stats) {
3715 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3716 bp->hw_rx_port_stats,
3717 bp->hw_rx_port_stats_map);
3718 bp->hw_rx_port_stats = NULL;
3719 }
3720
3721 if (bp->hw_tx_port_stats_ext) {
3722 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3723 bp->hw_tx_port_stats_ext,
3724 bp->hw_tx_port_stats_ext_map);
3725 bp->hw_tx_port_stats_ext = NULL;
3726 }
3727
3728 if (bp->hw_rx_port_stats_ext) {
3729 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3730 bp->hw_rx_port_stats_ext,
3731 bp->hw_rx_port_stats_ext_map);
3732 bp->hw_rx_port_stats_ext = NULL;
3733 }
3734
3735 if (bp->hw_pcie_stats) {
3736 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3737 bp->hw_pcie_stats, bp->hw_pcie_stats_map);
3738 bp->hw_pcie_stats = NULL;
3739 }
3740 }
3741
3742 static void bnxt_free_ring_stats(struct bnxt *bp)
3743 {
3744 struct pci_dev *pdev = bp->pdev;
3745 int size, i;
3746
3747 if (!bp->bnapi)
3748 return;
3749
3750 size = bp->hw_ring_stats_size;
3751
3752 for (i = 0; i < bp->cp_nr_rings; i++) {
3753 struct bnxt_napi *bnapi = bp->bnapi[i];
3754 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3755
3756 if (cpr->hw_stats) {
3757 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3758 cpr->hw_stats_map);
3759 cpr->hw_stats = NULL;
3760 }
3761 }
3762 }
3763
3764 static int bnxt_alloc_stats(struct bnxt *bp)
3765 {
3766 u32 size, i;
3767 struct pci_dev *pdev = bp->pdev;
3768
3769 size = bp->hw_ring_stats_size;
3770
3771 for (i = 0; i < bp->cp_nr_rings; i++) {
3772 struct bnxt_napi *bnapi = bp->bnapi[i];
3773 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3774
3775 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3776 &cpr->hw_stats_map,
3777 GFP_KERNEL);
3778 if (!cpr->hw_stats)
3779 return -ENOMEM;
3780
3781 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3782 }
3783
3784 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
3785 return 0;
3786
3787 if (bp->hw_rx_port_stats)
3788 goto alloc_ext_stats;
3789
3790 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3791 sizeof(struct tx_port_stats) + 1024;
3792
3793 bp->hw_rx_port_stats =
3794 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3795 &bp->hw_rx_port_stats_map,
3796 GFP_KERNEL);
3797 if (!bp->hw_rx_port_stats)
3798 return -ENOMEM;
3799
3800 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512;
3801 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3802 sizeof(struct rx_port_stats) + 512;
3803 bp->flags |= BNXT_FLAG_PORT_STATS;
3804
3805 alloc_ext_stats:
3806
3807 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
3808 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
3809 return 0;
3810
3811 if (bp->hw_rx_port_stats_ext)
3812 goto alloc_tx_ext_stats;
3813
3814 bp->hw_rx_port_stats_ext =
3815 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3816 &bp->hw_rx_port_stats_ext_map, GFP_KERNEL);
3817 if (!bp->hw_rx_port_stats_ext)
3818 return 0;
3819
3820 alloc_tx_ext_stats:
3821 if (bp->hw_tx_port_stats_ext)
3822 goto alloc_pcie_stats;
3823
3824 if (bp->hwrm_spec_code >= 0x10902 ||
3825 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
3826 bp->hw_tx_port_stats_ext =
3827 dma_alloc_coherent(&pdev->dev,
3828 sizeof(struct tx_port_stats_ext),
3829 &bp->hw_tx_port_stats_ext_map,
3830 GFP_KERNEL);
3831 }
3832 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3833
3834 alloc_pcie_stats:
3835 if (bp->hw_pcie_stats ||
3836 !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
3837 return 0;
3838
3839 bp->hw_pcie_stats =
3840 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3841 &bp->hw_pcie_stats_map, GFP_KERNEL);
3842 if (!bp->hw_pcie_stats)
3843 return 0;
3844
3845 bp->flags |= BNXT_FLAG_PCIE_STATS;
3846 return 0;
3847 }
3848
3849 static void bnxt_clear_ring_indices(struct bnxt *bp)
3850 {
3851 int i;
3852
3853 if (!bp->bnapi)
3854 return;
3855
3856 for (i = 0; i < bp->cp_nr_rings; i++) {
3857 struct bnxt_napi *bnapi = bp->bnapi[i];
3858 struct bnxt_cp_ring_info *cpr;
3859 struct bnxt_rx_ring_info *rxr;
3860 struct bnxt_tx_ring_info *txr;
3861
3862 if (!bnapi)
3863 continue;
3864
3865 cpr = &bnapi->cp_ring;
3866 cpr->cp_raw_cons = 0;
3867
3868 txr = bnapi->tx_ring;
3869 if (txr) {
3870 txr->tx_prod = 0;
3871 txr->tx_cons = 0;
3872 }
3873
3874 rxr = bnapi->rx_ring;
3875 if (rxr) {
3876 rxr->rx_prod = 0;
3877 rxr->rx_agg_prod = 0;
3878 rxr->rx_sw_agg_prod = 0;
3879 rxr->rx_next_cons = 0;
3880 }
3881 }
3882 }
3883
3884 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3885 {
3886 #ifdef CONFIG_RFS_ACCEL
3887 int i;
3888
3889
3890
3891
3892 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3893 struct hlist_head *head;
3894 struct hlist_node *tmp;
3895 struct bnxt_ntuple_filter *fltr;
3896
3897 head = &bp->ntp_fltr_hash_tbl[i];
3898 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3899 hlist_del(&fltr->hash);
3900 kfree(fltr);
3901 }
3902 }
3903 if (irq_reinit) {
3904 kfree(bp->ntp_fltr_bmap);
3905 bp->ntp_fltr_bmap = NULL;
3906 }
3907 bp->ntp_fltr_count = 0;
3908 #endif
3909 }
3910
3911 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3912 {
3913 #ifdef CONFIG_RFS_ACCEL
3914 int i, rc = 0;
3915
3916 if (!(bp->flags & BNXT_FLAG_RFS))
3917 return 0;
3918
3919 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3920 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3921
3922 bp->ntp_fltr_count = 0;
3923 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3924 sizeof(long),
3925 GFP_KERNEL);
3926
3927 if (!bp->ntp_fltr_bmap)
3928 rc = -ENOMEM;
3929
3930 return rc;
3931 #else
3932 return 0;
3933 #endif
3934 }
3935
3936 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3937 {
3938 bnxt_free_vnic_attributes(bp);
3939 bnxt_free_tx_rings(bp);
3940 bnxt_free_rx_rings(bp);
3941 bnxt_free_cp_rings(bp);
3942 bnxt_free_ntp_fltrs(bp, irq_re_init);
3943 if (irq_re_init) {
3944 bnxt_free_ring_stats(bp);
3945 bnxt_free_ring_grps(bp);
3946 bnxt_free_vnics(bp);
3947 kfree(bp->tx_ring_map);
3948 bp->tx_ring_map = NULL;
3949 kfree(bp->tx_ring);
3950 bp->tx_ring = NULL;
3951 kfree(bp->rx_ring);
3952 bp->rx_ring = NULL;
3953 kfree(bp->bnapi);
3954 bp->bnapi = NULL;
3955 } else {
3956 bnxt_clear_ring_indices(bp);
3957 }
3958 }
3959
3960 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3961 {
3962 int i, j, rc, size, arr_size;
3963 void *bnapi;
3964
3965 if (irq_re_init) {
3966
3967
3968
3969 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3970 bp->cp_nr_rings);
3971 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3972 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3973 if (!bnapi)
3974 return -ENOMEM;
3975
3976 bp->bnapi = bnapi;
3977 bnapi += arr_size;
3978 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3979 bp->bnapi[i] = bnapi;
3980 bp->bnapi[i]->index = i;
3981 bp->bnapi[i]->bp = bp;
3982 if (bp->flags & BNXT_FLAG_CHIP_P5) {
3983 struct bnxt_cp_ring_info *cpr =
3984 &bp->bnapi[i]->cp_ring;
3985
3986 cpr->cp_ring_struct.ring_mem.flags =
3987 BNXT_RMEM_RING_PTE_FLAG;
3988 }
3989 }
3990
3991 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3992 sizeof(struct bnxt_rx_ring_info),
3993 GFP_KERNEL);
3994 if (!bp->rx_ring)
3995 return -ENOMEM;
3996
3997 for (i = 0; i < bp->rx_nr_rings; i++) {
3998 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3999
4000 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4001 rxr->rx_ring_struct.ring_mem.flags =
4002 BNXT_RMEM_RING_PTE_FLAG;
4003 rxr->rx_agg_ring_struct.ring_mem.flags =
4004 BNXT_RMEM_RING_PTE_FLAG;
4005 }
4006 rxr->bnapi = bp->bnapi[i];
4007 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
4008 }
4009
4010 bp->tx_ring = kcalloc(bp->tx_nr_rings,
4011 sizeof(struct bnxt_tx_ring_info),
4012 GFP_KERNEL);
4013 if (!bp->tx_ring)
4014 return -ENOMEM;
4015
4016 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
4017 GFP_KERNEL);
4018
4019 if (!bp->tx_ring_map)
4020 return -ENOMEM;
4021
4022 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4023 j = 0;
4024 else
4025 j = bp->rx_nr_rings;
4026
4027 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
4028 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4029
4030 if (bp->flags & BNXT_FLAG_CHIP_P5)
4031 txr->tx_ring_struct.ring_mem.flags =
4032 BNXT_RMEM_RING_PTE_FLAG;
4033 txr->bnapi = bp->bnapi[j];
4034 bp->bnapi[j]->tx_ring = txr;
4035 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
4036 if (i >= bp->tx_nr_rings_xdp) {
4037 txr->txq_index = i - bp->tx_nr_rings_xdp;
4038 bp->bnapi[j]->tx_int = bnxt_tx_int;
4039 } else {
4040 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
4041 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
4042 }
4043 }
4044
4045 rc = bnxt_alloc_stats(bp);
4046 if (rc)
4047 goto alloc_mem_err;
4048
4049 rc = bnxt_alloc_ntp_fltrs(bp);
4050 if (rc)
4051 goto alloc_mem_err;
4052
4053 rc = bnxt_alloc_vnics(bp);
4054 if (rc)
4055 goto alloc_mem_err;
4056 }
4057
4058 bnxt_init_ring_struct(bp);
4059
4060 rc = bnxt_alloc_rx_rings(bp);
4061 if (rc)
4062 goto alloc_mem_err;
4063
4064 rc = bnxt_alloc_tx_rings(bp);
4065 if (rc)
4066 goto alloc_mem_err;
4067
4068 rc = bnxt_alloc_cp_rings(bp);
4069 if (rc)
4070 goto alloc_mem_err;
4071
4072 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
4073 BNXT_VNIC_UCAST_FLAG;
4074 rc = bnxt_alloc_vnic_attributes(bp);
4075 if (rc)
4076 goto alloc_mem_err;
4077 return 0;
4078
4079 alloc_mem_err:
4080 bnxt_free_mem(bp, true);
4081 return rc;
4082 }
4083
4084 static void bnxt_disable_int(struct bnxt *bp)
4085 {
4086 int i;
4087
4088 if (!bp->bnapi)
4089 return;
4090
4091 for (i = 0; i < bp->cp_nr_rings; i++) {
4092 struct bnxt_napi *bnapi = bp->bnapi[i];
4093 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4094 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4095
4096 if (ring->fw_ring_id != INVALID_HW_RING_ID)
4097 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
4098 }
4099 }
4100
4101 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
4102 {
4103 struct bnxt_napi *bnapi = bp->bnapi[n];
4104 struct bnxt_cp_ring_info *cpr;
4105
4106 cpr = &bnapi->cp_ring;
4107 return cpr->cp_ring_struct.map_idx;
4108 }
4109
4110 static void bnxt_disable_int_sync(struct bnxt *bp)
4111 {
4112 int i;
4113
4114 atomic_inc(&bp->intr_sem);
4115
4116 bnxt_disable_int(bp);
4117 for (i = 0; i < bp->cp_nr_rings; i++) {
4118 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
4119
4120 synchronize_irq(bp->irq_tbl[map_idx].vector);
4121 }
4122 }
4123
4124 static void bnxt_enable_int(struct bnxt *bp)
4125 {
4126 int i;
4127
4128 atomic_set(&bp->intr_sem, 0);
4129 for (i = 0; i < bp->cp_nr_rings; i++) {
4130 struct bnxt_napi *bnapi = bp->bnapi[i];
4131 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4132
4133 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
4134 }
4135 }
4136
4137 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
4138 u16 cmpl_ring, u16 target_id)
4139 {
4140 struct input *req = request;
4141
4142 req->req_type = cpu_to_le16(req_type);
4143 req->cmpl_ring = cpu_to_le16(cmpl_ring);
4144 req->target_id = cpu_to_le16(target_id);
4145 if (bnxt_kong_hwrm_message(bp, req))
4146 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
4147 else
4148 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
4149 }
4150
4151 static int bnxt_hwrm_to_stderr(u32 hwrm_err)
4152 {
4153 switch (hwrm_err) {
4154 case HWRM_ERR_CODE_SUCCESS:
4155 return 0;
4156 case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED:
4157 return -EACCES;
4158 case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR:
4159 return -ENOSPC;
4160 case HWRM_ERR_CODE_INVALID_PARAMS:
4161 case HWRM_ERR_CODE_INVALID_FLAGS:
4162 case HWRM_ERR_CODE_INVALID_ENABLES:
4163 case HWRM_ERR_CODE_UNSUPPORTED_TLV:
4164 case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR:
4165 return -EINVAL;
4166 case HWRM_ERR_CODE_NO_BUFFER:
4167 return -ENOMEM;
4168 case HWRM_ERR_CODE_HOT_RESET_PROGRESS:
4169 return -EAGAIN;
4170 case HWRM_ERR_CODE_CMD_NOT_SUPPORTED:
4171 return -EOPNOTSUPP;
4172 default:
4173 return -EIO;
4174 }
4175 }
4176
4177 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
4178 int timeout, bool silent)
4179 {
4180 int i, intr_process, rc, tmo_count;
4181 struct input *req = msg;
4182 u32 *data = msg;
4183 __le32 *resp_len;
4184 u8 *valid;
4185 u16 cp_ring_id, len = 0;
4186 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
4187 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
4188 struct hwrm_short_input short_input = {0};
4189 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
4190 u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr;
4191 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
4192 u16 dst = BNXT_HWRM_CHNL_CHIMP;
4193
4194 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
4195 return -EBUSY;
4196
4197 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
4198 if (msg_len > bp->hwrm_max_ext_req_len ||
4199 !bp->hwrm_short_cmd_req_addr)
4200 return -EINVAL;
4201 }
4202
4203 if (bnxt_hwrm_kong_chnl(bp, req)) {
4204 dst = BNXT_HWRM_CHNL_KONG;
4205 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
4206 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
4207 resp = bp->hwrm_cmd_kong_resp_addr;
4208 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr;
4209 }
4210
4211 memset(resp, 0, PAGE_SIZE);
4212 cp_ring_id = le16_to_cpu(req->cmpl_ring);
4213 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
4214
4215 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
4216
4217 if (intr_process)
4218 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
4219
4220 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
4221 msg_len > BNXT_HWRM_MAX_REQ_LEN) {
4222 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
4223 u16 max_msg_len;
4224
4225
4226
4227
4228
4229 max_msg_len = bp->hwrm_max_ext_req_len;
4230
4231 memcpy(short_cmd_req, req, msg_len);
4232 if (msg_len < max_msg_len)
4233 memset(short_cmd_req + msg_len, 0,
4234 max_msg_len - msg_len);
4235
4236 short_input.req_type = req->req_type;
4237 short_input.signature =
4238 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
4239 short_input.size = cpu_to_le16(msg_len);
4240 short_input.req_addr =
4241 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
4242
4243 data = (u32 *)&short_input;
4244 msg_len = sizeof(short_input);
4245
4246
4247 wmb();
4248
4249 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
4250 }
4251
4252
4253 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
4254
4255 for (i = msg_len; i < max_req_len; i += 4)
4256 writel(0, bp->bar0 + bar_offset + i);
4257
4258
4259 writel(1, bp->bar0 + doorbell_offset);
4260
4261 if (!pci_is_enabled(bp->pdev))
4262 return 0;
4263
4264 if (!timeout)
4265 timeout = DFLT_HWRM_CMD_TIMEOUT;
4266
4267 timeout *= 1000;
4268
4269 i = 0;
4270
4271
4272
4273
4274 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
4275 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
4276 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
4277 resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET);
4278
4279 if (intr_process) {
4280 u16 seq_id = bp->hwrm_intr_seq_id;
4281
4282
4283 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
4284 i++ < tmo_count) {
4285
4286 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
4287 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4288 HWRM_SHORT_MAX_TIMEOUT);
4289 else
4290 usleep_range(HWRM_MIN_TIMEOUT,
4291 HWRM_MAX_TIMEOUT);
4292 }
4293
4294 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
4295 if (!silent)
4296 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
4297 le16_to_cpu(req->req_type));
4298 return -EBUSY;
4299 }
4300 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
4301 HWRM_RESP_LEN_SFT;
4302 valid = resp_addr + len - 1;
4303 } else {
4304 int j;
4305
4306
4307 for (i = 0; i < tmo_count; i++) {
4308 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
4309 HWRM_RESP_LEN_SFT;
4310 if (len)
4311 break;
4312
4313 if (i < HWRM_SHORT_TIMEOUT_COUNTER)
4314 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4315 HWRM_SHORT_MAX_TIMEOUT);
4316 else
4317 usleep_range(HWRM_MIN_TIMEOUT,
4318 HWRM_MAX_TIMEOUT);
4319 }
4320
4321 if (i >= tmo_count) {
4322 if (!silent)
4323 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
4324 HWRM_TOTAL_TIMEOUT(i),
4325 le16_to_cpu(req->req_type),
4326 le16_to_cpu(req->seq_id), len);
4327 return -EBUSY;
4328 }
4329
4330
4331 valid = resp_addr + len - 1;
4332 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
4333
4334 dma_rmb();
4335 if (*valid)
4336 break;
4337 usleep_range(1, 5);
4338 }
4339
4340 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
4341 if (!silent)
4342 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
4343 HWRM_TOTAL_TIMEOUT(i),
4344 le16_to_cpu(req->req_type),
4345 le16_to_cpu(req->seq_id), len,
4346 *valid);
4347 return -EBUSY;
4348 }
4349 }
4350
4351
4352
4353
4354
4355 *valid = 0;
4356 rc = le16_to_cpu(resp->error_code);
4357 if (rc && !silent)
4358 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
4359 le16_to_cpu(resp->req_type),
4360 le16_to_cpu(resp->seq_id), rc);
4361 return bnxt_hwrm_to_stderr(rc);
4362 }
4363
4364 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4365 {
4366 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
4367 }
4368
4369 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4370 int timeout)
4371 {
4372 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4373 }
4374
4375 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4376 {
4377 int rc;
4378
4379 mutex_lock(&bp->hwrm_cmd_lock);
4380 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
4381 mutex_unlock(&bp->hwrm_cmd_lock);
4382 return rc;
4383 }
4384
4385 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4386 int timeout)
4387 {
4388 int rc;
4389
4390 mutex_lock(&bp->hwrm_cmd_lock);
4391 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4392 mutex_unlock(&bp->hwrm_cmd_lock);
4393 return rc;
4394 }
4395
4396 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
4397 int bmap_size)
4398 {
4399 struct hwrm_func_drv_rgtr_input req = {0};
4400 DECLARE_BITMAP(async_events_bmap, 256);
4401 u32 *events = (u32 *)async_events_bmap;
4402 int i;
4403
4404 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4405
4406 req.enables =
4407 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4408
4409 memset(async_events_bmap, 0, sizeof(async_events_bmap));
4410 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) {
4411 u16 event_id = bnxt_async_events_arr[i];
4412
4413 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY &&
4414 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4415 continue;
4416 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4417 }
4418 if (bmap && bmap_size) {
4419 for (i = 0; i < bmap_size; i++) {
4420 if (test_bit(i, bmap))
4421 __set_bit(i, async_events_bmap);
4422 }
4423 }
4424
4425 for (i = 0; i < 8; i++)
4426 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4427
4428 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4429 }
4430
4431 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
4432 {
4433 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4434 struct hwrm_func_drv_rgtr_input req = {0};
4435 u32 flags;
4436 int rc;
4437
4438 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4439
4440 req.enables =
4441 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4442 FUNC_DRV_RGTR_REQ_ENABLES_VER);
4443
4444 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4445 flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE;
4446 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
4447 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT;
4448 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
4449 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT;
4450 req.flags = cpu_to_le32(flags);
4451 req.ver_maj_8b = DRV_VER_MAJ;
4452 req.ver_min_8b = DRV_VER_MIN;
4453 req.ver_upd_8b = DRV_VER_UPD;
4454 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4455 req.ver_min = cpu_to_le16(DRV_VER_MIN);
4456 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4457
4458 if (BNXT_PF(bp)) {
4459 u32 data[8];
4460 int i;
4461
4462 memset(data, 0, sizeof(data));
4463 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4464 u16 cmd = bnxt_vf_req_snif[i];
4465 unsigned int bit, idx;
4466
4467 idx = cmd / 32;
4468 bit = cmd % 32;
4469 data[idx] |= 1 << bit;
4470 }
4471
4472 for (i = 0; i < 8; i++)
4473 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4474
4475 req.enables |=
4476 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4477 }
4478
4479 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4480 req.flags |= cpu_to_le32(
4481 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4482
4483 mutex_lock(&bp->hwrm_cmd_lock);
4484 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4485 if (!rc && (resp->flags &
4486 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED)))
4487 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4488 mutex_unlock(&bp->hwrm_cmd_lock);
4489 return rc;
4490 }
4491
4492 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4493 {
4494 struct hwrm_func_drv_unrgtr_input req = {0};
4495
4496 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4497 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4498 }
4499
4500 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4501 {
4502 u32 rc = 0;
4503 struct hwrm_tunnel_dst_port_free_input req = {0};
4504
4505 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4506 req.tunnel_type = tunnel_type;
4507
4508 switch (tunnel_type) {
4509 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4510 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
4511 break;
4512 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4513 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
4514 break;
4515 default:
4516 break;
4517 }
4518
4519 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4520 if (rc)
4521 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4522 rc);
4523 return rc;
4524 }
4525
4526 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4527 u8 tunnel_type)
4528 {
4529 u32 rc = 0;
4530 struct hwrm_tunnel_dst_port_alloc_input req = {0};
4531 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4532
4533 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4534
4535 req.tunnel_type = tunnel_type;
4536 req.tunnel_dst_port_val = port;
4537
4538 mutex_lock(&bp->hwrm_cmd_lock);
4539 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4540 if (rc) {
4541 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4542 rc);
4543 goto err_out;
4544 }
4545
4546 switch (tunnel_type) {
4547 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4548 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
4549 break;
4550 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4551 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
4552 break;
4553 default:
4554 break;
4555 }
4556
4557 err_out:
4558 mutex_unlock(&bp->hwrm_cmd_lock);
4559 return rc;
4560 }
4561
4562 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4563 {
4564 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4565 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4566
4567 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4568 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4569
4570 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4571 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4572 req.mask = cpu_to_le32(vnic->rx_mask);
4573 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4574 }
4575
4576 #ifdef CONFIG_RFS_ACCEL
4577 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4578 struct bnxt_ntuple_filter *fltr)
4579 {
4580 struct hwrm_cfa_ntuple_filter_free_input req = {0};
4581
4582 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4583 req.ntuple_filter_id = fltr->filter_id;
4584 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4585 }
4586
4587 #define BNXT_NTP_FLTR_FLAGS \
4588 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
4589 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
4590 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
4591 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
4592 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
4593 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
4594 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
4595 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
4596 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
4597 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
4598 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
4599 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
4600 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
4601 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4602
4603 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
4604 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4605
4606 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4607 struct bnxt_ntuple_filter *fltr)
4608 {
4609 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4610 struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4611 struct flow_keys *keys = &fltr->fkeys;
4612 struct bnxt_vnic_info *vnic;
4613 u32 dst_ena = 0;
4614 int rc = 0;
4615
4616 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4617 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4618
4619 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) {
4620 dst_ena = CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX;
4621 req.rfs_ring_tbl_idx = cpu_to_le16(fltr->rxq);
4622 vnic = &bp->vnic_info[0];
4623 } else {
4624 vnic = &bp->vnic_info[fltr->rxq + 1];
4625 }
4626 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4627 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS | dst_ena);
4628
4629 req.ethertype = htons(ETH_P_IP);
4630 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4631 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4632 req.ip_protocol = keys->basic.ip_proto;
4633
4634 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4635 int i;
4636
4637 req.ethertype = htons(ETH_P_IPV6);
4638 req.ip_addr_type =
4639 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4640 *(struct in6_addr *)&req.src_ipaddr[0] =
4641 keys->addrs.v6addrs.src;
4642 *(struct in6_addr *)&req.dst_ipaddr[0] =
4643 keys->addrs.v6addrs.dst;
4644 for (i = 0; i < 4; i++) {
4645 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4646 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4647 }
4648 } else {
4649 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4650 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4651 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4652 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4653 }
4654 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4655 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4656 req.tunnel_type =
4657 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4658 }
4659
4660 req.src_port = keys->ports.src;
4661 req.src_port_mask = cpu_to_be16(0xffff);
4662 req.dst_port = keys->ports.dst;
4663 req.dst_port_mask = cpu_to_be16(0xffff);
4664
4665 mutex_lock(&bp->hwrm_cmd_lock);
4666 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4667 if (!rc) {
4668 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4669 fltr->filter_id = resp->ntuple_filter_id;
4670 }
4671 mutex_unlock(&bp->hwrm_cmd_lock);
4672 return rc;
4673 }
4674 #endif
4675
4676 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4677 u8 *mac_addr)
4678 {
4679 u32 rc = 0;
4680 struct hwrm_cfa_l2_filter_alloc_input req = {0};
4681 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4682
4683 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4684 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4685 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4686 req.flags |=
4687 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4688 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4689 req.enables =
4690 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4691 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4692 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4693 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4694 req.l2_addr_mask[0] = 0xff;
4695 req.l2_addr_mask[1] = 0xff;
4696 req.l2_addr_mask[2] = 0xff;
4697 req.l2_addr_mask[3] = 0xff;
4698 req.l2_addr_mask[4] = 0xff;
4699 req.l2_addr_mask[5] = 0xff;
4700
4701 mutex_lock(&bp->hwrm_cmd_lock);
4702 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4703 if (!rc)
4704 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4705 resp->l2_filter_id;
4706 mutex_unlock(&bp->hwrm_cmd_lock);
4707 return rc;
4708 }
4709
4710 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4711 {
4712 u16 i, j, num_of_vnics = 1;
4713 int rc = 0;
4714
4715
4716 mutex_lock(&bp->hwrm_cmd_lock);
4717 for (i = 0; i < num_of_vnics; i++) {
4718 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4719
4720 for (j = 0; j < vnic->uc_filter_count; j++) {
4721 struct hwrm_cfa_l2_filter_free_input req = {0};
4722
4723 bnxt_hwrm_cmd_hdr_init(bp, &req,
4724 HWRM_CFA_L2_FILTER_FREE, -1, -1);
4725
4726 req.l2_filter_id = vnic->fw_l2_filter_id[j];
4727
4728 rc = _hwrm_send_message(bp, &req, sizeof(req),
4729 HWRM_CMD_TIMEOUT);
4730 }
4731 vnic->uc_filter_count = 0;
4732 }
4733 mutex_unlock(&bp->hwrm_cmd_lock);
4734
4735 return rc;
4736 }
4737
4738 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4739 {
4740 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4741 u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX;
4742 struct hwrm_vnic_tpa_cfg_input req = {0};
4743
4744 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4745 return 0;
4746
4747 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4748
4749 if (tpa_flags) {
4750 u16 mss = bp->dev->mtu - 40;
4751 u32 nsegs, n, segs = 0, flags;
4752
4753 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4754 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4755 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4756 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4757 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4758 if (tpa_flags & BNXT_FLAG_GRO)
4759 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4760
4761 req.flags = cpu_to_le32(flags);
4762
4763 req.enables =
4764 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4765 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4766 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4767
4768
4769
4770
4771 if (mss <= BNXT_RX_PAGE_SIZE) {
4772 n = BNXT_RX_PAGE_SIZE / mss;
4773 nsegs = (MAX_SKB_FRAGS - 1) * n;
4774 } else {
4775 n = mss / BNXT_RX_PAGE_SIZE;
4776 if (mss & (BNXT_RX_PAGE_SIZE - 1))
4777 n++;
4778 nsegs = (MAX_SKB_FRAGS - n) / n;
4779 }
4780
4781 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4782 segs = MAX_TPA_SEGS_P5;
4783 max_aggs = bp->max_tpa;
4784 } else {
4785 segs = ilog2(nsegs);
4786 }
4787 req.max_agg_segs = cpu_to_le16(segs);
4788 req.max_aggs = cpu_to_le16(max_aggs);
4789
4790 req.min_agg_len = cpu_to_le32(512);
4791 }
4792 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4793
4794 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4795 }
4796
4797 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4798 {
4799 struct bnxt_ring_grp_info *grp_info;
4800
4801 grp_info = &bp->grp_info[ring->grp_idx];
4802 return grp_info->cp_fw_ring_id;
4803 }
4804
4805 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4806 {
4807 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4808 struct bnxt_napi *bnapi = rxr->bnapi;
4809 struct bnxt_cp_ring_info *cpr;
4810
4811 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4812 return cpr->cp_ring_struct.fw_ring_id;
4813 } else {
4814 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4815 }
4816 }
4817
4818 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4819 {
4820 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4821 struct bnxt_napi *bnapi = txr->bnapi;
4822 struct bnxt_cp_ring_info *cpr;
4823
4824 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4825 return cpr->cp_ring_struct.fw_ring_id;
4826 } else {
4827 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
4828 }
4829 }
4830
4831 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4832 {
4833 u32 i, j, max_rings;
4834 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4835 struct hwrm_vnic_rss_cfg_input req = {0};
4836
4837 if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
4838 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4839 return 0;
4840
4841 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4842 if (set_rss) {
4843 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4844 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4845 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4846 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4847 max_rings = bp->rx_nr_rings - 1;
4848 else
4849 max_rings = bp->rx_nr_rings;
4850 } else {
4851 max_rings = 1;
4852 }
4853
4854
4855 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4856 if (j == max_rings)
4857 j = 0;
4858 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4859 }
4860
4861 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4862 req.hash_key_tbl_addr =
4863 cpu_to_le64(vnic->rss_hash_key_dma_addr);
4864 }
4865 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4866 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4867 }
4868
4869 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
4870 {
4871 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4872 u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings;
4873 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4874 struct hwrm_vnic_rss_cfg_input req = {0};
4875
4876 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4877 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4878 if (!set_rss) {
4879 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4880 return 0;
4881 }
4882 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4883 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4884 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4885 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
4886 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
4887 for (i = 0, k = 0; i < nr_ctxs; i++) {
4888 __le16 *ring_tbl = vnic->rss_table;
4889 int rc;
4890
4891 req.ring_table_pair_index = i;
4892 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
4893 for (j = 0; j < 64; j++) {
4894 u16 ring_id;
4895
4896 ring_id = rxr->rx_ring_struct.fw_ring_id;
4897 *ring_tbl++ = cpu_to_le16(ring_id);
4898 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
4899 *ring_tbl++ = cpu_to_le16(ring_id);
4900 rxr++;
4901 k++;
4902 if (k == max_rings) {
4903 k = 0;
4904 rxr = &bp->rx_ring[0];
4905 }
4906 }
4907 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4908 if (rc)
4909 return rc;
4910 }
4911 return 0;
4912 }
4913
4914 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4915 {
4916 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4917 struct hwrm_vnic_plcmodes_cfg_input req = {0};
4918
4919 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4920 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4921 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4922 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4923 req.enables =
4924 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4925 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4926
4927 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4928 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4929 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4930 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4931 }
4932
4933 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4934 u16 ctx_idx)
4935 {
4936 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4937
4938 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4939 req.rss_cos_lb_ctx_id =
4940 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4941
4942 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4943 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4944 }
4945
4946 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4947 {
4948 int i, j;
4949
4950 for (i = 0; i < bp->nr_vnics; i++) {
4951 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4952
4953 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4954 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4955 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4956 }
4957 }
4958 bp->rsscos_nr_ctxs = 0;
4959 }
4960
4961 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4962 {
4963 int rc;
4964 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4965 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4966 bp->hwrm_cmd_resp_addr;
4967
4968 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4969 -1);
4970
4971 mutex_lock(&bp->hwrm_cmd_lock);
4972 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4973 if (!rc)
4974 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4975 le16_to_cpu(resp->rss_cos_lb_ctx_id);
4976 mutex_unlock(&bp->hwrm_cmd_lock);
4977
4978 return rc;
4979 }
4980
4981 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4982 {
4983 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4984 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4985 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4986 }
4987
4988 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4989 {
4990 unsigned int ring = 0, grp_idx;
4991 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4992 struct hwrm_vnic_cfg_input req = {0};
4993 u16 def_vlan = 0;
4994
4995 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4996
4997 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4998 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4999
5000 req.default_rx_ring_id =
5001 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
5002 req.default_cmpl_ring_id =
5003 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
5004 req.enables =
5005 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
5006 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
5007 goto vnic_mru;
5008 }
5009 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
5010
5011 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
5012 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5013 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5014 VNIC_CFG_REQ_ENABLES_MRU);
5015 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
5016 req.rss_rule =
5017 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
5018 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5019 VNIC_CFG_REQ_ENABLES_MRU);
5020 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
5021 } else {
5022 req.rss_rule = cpu_to_le16(0xffff);
5023 }
5024
5025 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
5026 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
5027 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
5028 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
5029 } else {
5030 req.cos_rule = cpu_to_le16(0xffff);
5031 }
5032
5033 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
5034 ring = 0;
5035 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
5036 ring = vnic_id - 1;
5037 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
5038 ring = bp->rx_nr_rings - 1;
5039
5040 grp_idx = bp->rx_ring[ring].bnapi->index;
5041 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
5042 req.lb_rule = cpu_to_le16(0xffff);
5043 vnic_mru:
5044 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
5045 VLAN_HLEN);
5046
5047 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5048 #ifdef CONFIG_BNXT_SRIOV
5049 if (BNXT_VF(bp))
5050 def_vlan = bp->vf.vlan;
5051 #endif
5052 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
5053 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
5054 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
5055 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
5056
5057 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5058 }
5059
5060 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
5061 {
5062 u32 rc = 0;
5063
5064 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
5065 struct hwrm_vnic_free_input req = {0};
5066
5067 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
5068 req.vnic_id =
5069 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
5070
5071 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5072 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
5073 }
5074 return rc;
5075 }
5076
5077 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
5078 {
5079 u16 i;
5080
5081 for (i = 0; i < bp->nr_vnics; i++)
5082 bnxt_hwrm_vnic_free_one(bp, i);
5083 }
5084
5085 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
5086 unsigned int start_rx_ring_idx,
5087 unsigned int nr_rings)
5088 {
5089 int rc = 0;
5090 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
5091 struct hwrm_vnic_alloc_input req = {0};
5092 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5093 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5094
5095 if (bp->flags & BNXT_FLAG_CHIP_P5)
5096 goto vnic_no_ring_grps;
5097
5098
5099 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
5100 grp_idx = bp->rx_ring[i].bnapi->index;
5101 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
5102 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
5103 j, nr_rings);
5104 break;
5105 }
5106 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
5107 }
5108
5109 vnic_no_ring_grps:
5110 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
5111 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
5112 if (vnic_id == 0)
5113 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
5114
5115 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
5116
5117 mutex_lock(&bp->hwrm_cmd_lock);
5118 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5119 if (!rc)
5120 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
5121 mutex_unlock(&bp->hwrm_cmd_lock);
5122 return rc;
5123 }
5124
5125 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
5126 {
5127 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5128 struct hwrm_vnic_qcaps_input req = {0};
5129 int rc;
5130
5131 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats);
5132 bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP);
5133 if (bp->hwrm_spec_code < 0x10600)
5134 return 0;
5135
5136 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
5137 mutex_lock(&bp->hwrm_cmd_lock);
5138 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5139 if (!rc) {
5140 u32 flags = le32_to_cpu(resp->flags);
5141
5142 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
5143 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
5144 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
5145 if (flags &
5146 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
5147 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
5148 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported);
5149 if (bp->max_tpa_v2)
5150 bp->hw_ring_stats_size =
5151 sizeof(struct ctx_hw_stats_ext);
5152 }
5153 mutex_unlock(&bp->hwrm_cmd_lock);
5154 return rc;
5155 }
5156
5157 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
5158 {
5159 u16 i;
5160 u32 rc = 0;
5161
5162 if (bp->flags & BNXT_FLAG_CHIP_P5)
5163 return 0;
5164
5165 mutex_lock(&bp->hwrm_cmd_lock);
5166 for (i = 0; i < bp->rx_nr_rings; i++) {
5167 struct hwrm_ring_grp_alloc_input req = {0};
5168 struct hwrm_ring_grp_alloc_output *resp =
5169 bp->hwrm_cmd_resp_addr;
5170 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
5171
5172 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
5173
5174 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
5175 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
5176 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
5177 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
5178
5179 rc = _hwrm_send_message(bp, &req, sizeof(req),
5180 HWRM_CMD_TIMEOUT);
5181 if (rc)
5182 break;
5183
5184 bp->grp_info[grp_idx].fw_grp_id =
5185 le32_to_cpu(resp->ring_group_id);
5186 }
5187 mutex_unlock(&bp->hwrm_cmd_lock);
5188 return rc;
5189 }
5190
5191 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
5192 {
5193 u16 i;
5194 u32 rc = 0;
5195 struct hwrm_ring_grp_free_input req = {0};
5196
5197 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
5198 return 0;
5199
5200 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
5201
5202 mutex_lock(&bp->hwrm_cmd_lock);
5203 for (i = 0; i < bp->cp_nr_rings; i++) {
5204 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
5205 continue;
5206 req.ring_group_id =
5207 cpu_to_le32(bp->grp_info[i].fw_grp_id);
5208
5209 rc = _hwrm_send_message(bp, &req, sizeof(req),
5210 HWRM_CMD_TIMEOUT);
5211 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
5212 }
5213 mutex_unlock(&bp->hwrm_cmd_lock);
5214 return rc;
5215 }
5216
5217 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
5218 struct bnxt_ring_struct *ring,
5219 u32 ring_type, u32 map_index)
5220 {
5221 int rc = 0, err = 0;
5222 struct hwrm_ring_alloc_input req = {0};
5223 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5224 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
5225 struct bnxt_ring_grp_info *grp_info;
5226 u16 ring_id;
5227
5228 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
5229
5230 req.enables = 0;
5231 if (rmem->nr_pages > 1) {
5232 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
5233
5234 req.page_size = BNXT_PAGE_SHIFT;
5235 req.page_tbl_depth = 1;
5236 } else {
5237 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
5238 }
5239 req.fbo = 0;
5240
5241 req.logical_id = cpu_to_le16(map_index);
5242
5243 switch (ring_type) {
5244 case HWRM_RING_ALLOC_TX: {
5245 struct bnxt_tx_ring_info *txr;
5246
5247 txr = container_of(ring, struct bnxt_tx_ring_info,
5248 tx_ring_struct);
5249 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
5250
5251 grp_info = &bp->grp_info[ring->grp_idx];
5252 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
5253 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
5254 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5255 req.queue_id = cpu_to_le16(ring->queue_id);
5256 break;
5257 }
5258 case HWRM_RING_ALLOC_RX:
5259 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5260 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
5261 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5262 u16 flags = 0;
5263
5264
5265 grp_info = &bp->grp_info[ring->grp_idx];
5266 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
5267 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5268 req.enables |= cpu_to_le32(
5269 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5270 if (NET_IP_ALIGN == 2)
5271 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
5272 req.flags = cpu_to_le16(flags);
5273 }
5274 break;
5275 case HWRM_RING_ALLOC_AGG:
5276 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5277 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
5278
5279 grp_info = &bp->grp_info[ring->grp_idx];
5280 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
5281 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
5282 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5283 req.enables |= cpu_to_le32(
5284 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
5285 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5286 } else {
5287 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5288 }
5289 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
5290 break;
5291 case HWRM_RING_ALLOC_CMPL:
5292 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
5293 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
5294 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5295
5296 grp_info = &bp->grp_info[map_index];
5297 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
5298 req.cq_handle = cpu_to_le64(ring->handle);
5299 req.enables |= cpu_to_le32(
5300 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
5301 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
5302 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5303 }
5304 break;
5305 case HWRM_RING_ALLOC_NQ:
5306 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
5307 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
5308 if (bp->flags & BNXT_FLAG_USING_MSIX)
5309 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5310 break;
5311 default:
5312 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
5313 ring_type);
5314 return -1;
5315 }
5316
5317 mutex_lock(&bp->hwrm_cmd_lock);
5318 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5319 err = le16_to_cpu(resp->error_code);
5320 ring_id = le16_to_cpu(resp->ring_id);
5321 mutex_unlock(&bp->hwrm_cmd_lock);
5322
5323 if (rc || err) {
5324 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
5325 ring_type, rc, err);
5326 return -EIO;
5327 }
5328 ring->fw_ring_id = ring_id;
5329 return rc;
5330 }
5331
5332 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
5333 {
5334 int rc;
5335
5336 if (BNXT_PF(bp)) {
5337 struct hwrm_func_cfg_input req = {0};
5338
5339 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5340 req.fid = cpu_to_le16(0xffff);
5341 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5342 req.async_event_cr = cpu_to_le16(idx);
5343 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5344 } else {
5345 struct hwrm_func_vf_cfg_input req = {0};
5346
5347 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
5348 req.enables =
5349 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5350 req.async_event_cr = cpu_to_le16(idx);
5351 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5352 }
5353 return rc;
5354 }
5355
5356 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
5357 u32 map_idx, u32 xid)
5358 {
5359 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5360 if (BNXT_PF(bp))
5361 db->doorbell = bp->bar1 + 0x10000;
5362 else
5363 db->doorbell = bp->bar1 + 0x4000;
5364 switch (ring_type) {
5365 case HWRM_RING_ALLOC_TX:
5366 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
5367 break;
5368 case HWRM_RING_ALLOC_RX:
5369 case HWRM_RING_ALLOC_AGG:
5370 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
5371 break;
5372 case HWRM_RING_ALLOC_CMPL:
5373 db->db_key64 = DBR_PATH_L2;
5374 break;
5375 case HWRM_RING_ALLOC_NQ:
5376 db->db_key64 = DBR_PATH_L2;
5377 break;
5378 }
5379 db->db_key64 |= (u64)xid << DBR_XID_SFT;
5380 } else {
5381 db->doorbell = bp->bar1 + map_idx * 0x80;
5382 switch (ring_type) {
5383 case HWRM_RING_ALLOC_TX:
5384 db->db_key32 = DB_KEY_TX;
5385 break;
5386 case HWRM_RING_ALLOC_RX:
5387 case HWRM_RING_ALLOC_AGG:
5388 db->db_key32 = DB_KEY_RX;
5389 break;
5390 case HWRM_RING_ALLOC_CMPL:
5391 db->db_key32 = DB_KEY_CP;
5392 break;
5393 }
5394 }
5395 }
5396
5397 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5398 {
5399 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
5400 int i, rc = 0;
5401 u32 type;
5402
5403 if (bp->flags & BNXT_FLAG_CHIP_P5)
5404 type = HWRM_RING_ALLOC_NQ;
5405 else
5406 type = HWRM_RING_ALLOC_CMPL;
5407 for (i = 0; i < bp->cp_nr_rings; i++) {
5408 struct bnxt_napi *bnapi = bp->bnapi[i];
5409 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5410 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5411 u32 map_idx = ring->map_idx;
5412 unsigned int vector;
5413
5414 vector = bp->irq_tbl[map_idx].vector;
5415 disable_irq_nosync(vector);
5416 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5417 if (rc) {
5418 enable_irq(vector);
5419 goto err_out;
5420 }
5421 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5422 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5423 enable_irq(vector);
5424 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5425
5426 if (!i) {
5427 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5428 if (rc)
5429 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5430 }
5431 }
5432
5433 type = HWRM_RING_ALLOC_TX;
5434 for (i = 0; i < bp->tx_nr_rings; i++) {
5435 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5436 struct bnxt_ring_struct *ring;
5437 u32 map_idx;
5438
5439 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5440 struct bnxt_napi *bnapi = txr->bnapi;
5441 struct bnxt_cp_ring_info *cpr, *cpr2;
5442 u32 type2 = HWRM_RING_ALLOC_CMPL;
5443
5444 cpr = &bnapi->cp_ring;
5445 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5446 ring = &cpr2->cp_ring_struct;
5447 ring->handle = BNXT_TX_HDL;
5448 map_idx = bnapi->index;
5449 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5450 if (rc)
5451 goto err_out;
5452 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5453 ring->fw_ring_id);
5454 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5455 }
5456 ring = &txr->tx_ring_struct;
5457 map_idx = i;
5458 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5459 if (rc)
5460 goto err_out;
5461 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5462 }
5463
5464 type = HWRM_RING_ALLOC_RX;
5465 for (i = 0; i < bp->rx_nr_rings; i++) {
5466 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5467 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5468 struct bnxt_napi *bnapi = rxr->bnapi;
5469 u32 map_idx = bnapi->index;
5470
5471 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5472 if (rc)
5473 goto err_out;
5474 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5475
5476 if (!agg_rings)
5477 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5478 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5479 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5480 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5481 u32 type2 = HWRM_RING_ALLOC_CMPL;
5482 struct bnxt_cp_ring_info *cpr2;
5483
5484 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5485 ring = &cpr2->cp_ring_struct;
5486 ring->handle = BNXT_RX_HDL;
5487 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5488 if (rc)
5489 goto err_out;
5490 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5491 ring->fw_ring_id);
5492 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5493 }
5494 }
5495
5496 if (agg_rings) {
5497 type = HWRM_RING_ALLOC_AGG;
5498 for (i = 0; i < bp->rx_nr_rings; i++) {
5499 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5500 struct bnxt_ring_struct *ring =
5501 &rxr->rx_agg_ring_struct;
5502 u32 grp_idx = ring->grp_idx;
5503 u32 map_idx = grp_idx + bp->rx_nr_rings;
5504
5505 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5506 if (rc)
5507 goto err_out;
5508
5509 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5510 ring->fw_ring_id);
5511 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5512 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5513 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5514 }
5515 }
5516 err_out:
5517 return rc;
5518 }
5519
5520 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5521 struct bnxt_ring_struct *ring,
5522 u32 ring_type, int cmpl_ring_id)
5523 {
5524 int rc;
5525 struct hwrm_ring_free_input req = {0};
5526 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5527 u16 error_code;
5528
5529 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
5530 return 0;
5531
5532 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5533 req.ring_type = ring_type;
5534 req.ring_id = cpu_to_le16(ring->fw_ring_id);
5535
5536 mutex_lock(&bp->hwrm_cmd_lock);
5537 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5538 error_code = le16_to_cpu(resp->error_code);
5539 mutex_unlock(&bp->hwrm_cmd_lock);
5540
5541 if (rc || error_code) {
5542 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5543 ring_type, rc, error_code);
5544 return -EIO;
5545 }
5546 return 0;
5547 }
5548
5549 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5550 {
5551 u32 type;
5552 int i;
5553
5554 if (!bp->bnapi)
5555 return;
5556
5557 for (i = 0; i < bp->tx_nr_rings; i++) {
5558 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5559 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5560
5561 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5562 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5563
5564 hwrm_ring_free_send_msg(bp, ring,
5565 RING_FREE_REQ_RING_TYPE_TX,
5566 close_path ? cmpl_ring_id :
5567 INVALID_HW_RING_ID);
5568 ring->fw_ring_id = INVALID_HW_RING_ID;
5569 }
5570 }
5571
5572 for (i = 0; i < bp->rx_nr_rings; i++) {
5573 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5574 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5575 u32 grp_idx = rxr->bnapi->index;
5576
5577 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5578 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5579
5580 hwrm_ring_free_send_msg(bp, ring,
5581 RING_FREE_REQ_RING_TYPE_RX,
5582 close_path ? cmpl_ring_id :
5583 INVALID_HW_RING_ID);
5584 ring->fw_ring_id = INVALID_HW_RING_ID;
5585 bp->grp_info[grp_idx].rx_fw_ring_id =
5586 INVALID_HW_RING_ID;
5587 }
5588 }
5589
5590 if (bp->flags & BNXT_FLAG_CHIP_P5)
5591 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5592 else
5593 type = RING_FREE_REQ_RING_TYPE_RX;
5594 for (i = 0; i < bp->rx_nr_rings; i++) {
5595 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5596 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5597 u32 grp_idx = rxr->bnapi->index;
5598
5599 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5600 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5601
5602 hwrm_ring_free_send_msg(bp, ring, type,
5603 close_path ? cmpl_ring_id :
5604 INVALID_HW_RING_ID);
5605 ring->fw_ring_id = INVALID_HW_RING_ID;
5606 bp->grp_info[grp_idx].agg_fw_ring_id =
5607 INVALID_HW_RING_ID;
5608 }
5609 }
5610
5611
5612
5613
5614
5615 bnxt_disable_int_sync(bp);
5616
5617 if (bp->flags & BNXT_FLAG_CHIP_P5)
5618 type = RING_FREE_REQ_RING_TYPE_NQ;
5619 else
5620 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5621 for (i = 0; i < bp->cp_nr_rings; i++) {
5622 struct bnxt_napi *bnapi = bp->bnapi[i];
5623 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5624 struct bnxt_ring_struct *ring;
5625 int j;
5626
5627 for (j = 0; j < 2; j++) {
5628 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5629
5630 if (cpr2) {
5631 ring = &cpr2->cp_ring_struct;
5632 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5633 continue;
5634 hwrm_ring_free_send_msg(bp, ring,
5635 RING_FREE_REQ_RING_TYPE_L2_CMPL,
5636 INVALID_HW_RING_ID);
5637 ring->fw_ring_id = INVALID_HW_RING_ID;
5638 }
5639 }
5640 ring = &cpr->cp_ring_struct;
5641 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5642 hwrm_ring_free_send_msg(bp, ring, type,
5643 INVALID_HW_RING_ID);
5644 ring->fw_ring_id = INVALID_HW_RING_ID;
5645 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5646 }
5647 }
5648 }
5649
5650 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5651 bool shared);
5652
5653 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5654 {
5655 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5656 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5657 struct hwrm_func_qcfg_input req = {0};
5658 int rc;
5659
5660 if (bp->hwrm_spec_code < 0x10601)
5661 return 0;
5662
5663 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5664 req.fid = cpu_to_le16(0xffff);
5665 mutex_lock(&bp->hwrm_cmd_lock);
5666 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5667 if (rc) {
5668 mutex_unlock(&bp->hwrm_cmd_lock);
5669 return rc;
5670 }
5671
5672 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5673 if (BNXT_NEW_RM(bp)) {
5674 u16 cp, stats;
5675
5676 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5677 hw_resc->resv_hw_ring_grps =
5678 le32_to_cpu(resp->alloc_hw_ring_grps);
5679 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5680 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5681 stats = le16_to_cpu(resp->alloc_stat_ctx);
5682 hw_resc->resv_irqs = cp;
5683 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5684 int rx = hw_resc->resv_rx_rings;
5685 int tx = hw_resc->resv_tx_rings;
5686
5687 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5688 rx >>= 1;
5689 if (cp < (rx + tx)) {
5690 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5691 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5692 rx <<= 1;
5693 hw_resc->resv_rx_rings = rx;
5694 hw_resc->resv_tx_rings = tx;
5695 }
5696 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
5697 hw_resc->resv_hw_ring_grps = rx;
5698 }
5699 hw_resc->resv_cp_rings = cp;
5700 hw_resc->resv_stat_ctxs = stats;
5701 }
5702 mutex_unlock(&bp->hwrm_cmd_lock);
5703 return 0;
5704 }
5705
5706
5707 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5708 {
5709 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5710 struct hwrm_func_qcfg_input req = {0};
5711 int rc;
5712
5713 if (bp->hwrm_spec_code < 0x10601)
5714 return 0;
5715
5716 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5717 req.fid = cpu_to_le16(fid);
5718 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5719 if (!rc)
5720 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5721
5722 return rc;
5723 }
5724
5725 static bool bnxt_rfs_supported(struct bnxt *bp);
5726
5727 static void
5728 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5729 int tx_rings, int rx_rings, int ring_grps,
5730 int cp_rings, int stats, int vnics)
5731 {
5732 u32 enables = 0;
5733
5734 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5735 req->fid = cpu_to_le16(0xffff);
5736 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5737 req->num_tx_rings = cpu_to_le16(tx_rings);
5738 if (BNXT_NEW_RM(bp)) {
5739 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
5740 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5741 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5742 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5743 enables |= tx_rings + ring_grps ?
5744 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5745 enables |= rx_rings ?
5746 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5747 } else {
5748 enables |= cp_rings ?
5749 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5750 enables |= ring_grps ?
5751 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
5752 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5753 }
5754 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
5755
5756 req->num_rx_rings = cpu_to_le16(rx_rings);
5757 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5758 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5759 req->num_msix = cpu_to_le16(cp_rings);
5760 req->num_rsscos_ctxs =
5761 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5762 } else {
5763 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5764 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5765 req->num_rsscos_ctxs = cpu_to_le16(1);
5766 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
5767 bnxt_rfs_supported(bp))
5768 req->num_rsscos_ctxs =
5769 cpu_to_le16(ring_grps + 1);
5770 }
5771 req->num_stat_ctxs = cpu_to_le16(stats);
5772 req->num_vnics = cpu_to_le16(vnics);
5773 }
5774 req->enables = cpu_to_le32(enables);
5775 }
5776
5777 static void
5778 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
5779 struct hwrm_func_vf_cfg_input *req, int tx_rings,
5780 int rx_rings, int ring_grps, int cp_rings,
5781 int stats, int vnics)
5782 {
5783 u32 enables = 0;
5784
5785 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
5786 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5787 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
5788 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5789 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5790 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5791 enables |= tx_rings + ring_grps ?
5792 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5793 } else {
5794 enables |= cp_rings ?
5795 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5796 enables |= ring_grps ?
5797 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
5798 }
5799 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
5800 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
5801
5802 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
5803 req->num_tx_rings = cpu_to_le16(tx_rings);
5804 req->num_rx_rings = cpu_to_le16(rx_rings);
5805 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5806 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5807 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5808 } else {
5809 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5810 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5811 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
5812 }
5813 req->num_stat_ctxs = cpu_to_le16(stats);
5814 req->num_vnics = cpu_to_le16(vnics);
5815
5816 req->enables = cpu_to_le32(enables);
5817 }
5818
5819 static int
5820 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5821 int ring_grps, int cp_rings, int stats, int vnics)
5822 {
5823 struct hwrm_func_cfg_input req = {0};
5824 int rc;
5825
5826 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5827 cp_rings, stats, vnics);
5828 if (!req.enables)
5829 return 0;
5830
5831 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5832 if (rc)
5833 return rc;
5834
5835 if (bp->hwrm_spec_code < 0x10601)
5836 bp->hw_resc.resv_tx_rings = tx_rings;
5837
5838 rc = bnxt_hwrm_get_rings(bp);
5839 return rc;
5840 }
5841
5842 static int
5843 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5844 int ring_grps, int cp_rings, int stats, int vnics)
5845 {
5846 struct hwrm_func_vf_cfg_input req = {0};
5847 int rc;
5848
5849 if (!BNXT_NEW_RM(bp)) {
5850 bp->hw_resc.resv_tx_rings = tx_rings;
5851 return 0;
5852 }
5853
5854 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5855 cp_rings, stats, vnics);
5856 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5857 if (rc)
5858 return rc;
5859
5860 rc = bnxt_hwrm_get_rings(bp);
5861 return rc;
5862 }
5863
5864 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
5865 int cp, int stat, int vnic)
5866 {
5867 if (BNXT_PF(bp))
5868 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
5869 vnic);
5870 else
5871 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
5872 vnic);
5873 }
5874
5875 int bnxt_nq_rings_in_use(struct bnxt *bp)
5876 {
5877 int cp = bp->cp_nr_rings;
5878 int ulp_msix, ulp_base;
5879
5880 ulp_msix = bnxt_get_ulp_msix_num(bp);
5881 if (ulp_msix) {
5882 ulp_base = bnxt_get_ulp_msix_base(bp);
5883 cp += ulp_msix;
5884 if ((ulp_base + ulp_msix) > cp)
5885 cp = ulp_base + ulp_msix;
5886 }
5887 return cp;
5888 }
5889
5890 static int bnxt_cp_rings_in_use(struct bnxt *bp)
5891 {
5892 int cp;
5893
5894 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5895 return bnxt_nq_rings_in_use(bp);
5896
5897 cp = bp->tx_nr_rings + bp->rx_nr_rings;
5898 return cp;
5899 }
5900
5901 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
5902 {
5903 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
5904 int cp = bp->cp_nr_rings;
5905
5906 if (!ulp_stat)
5907 return cp;
5908
5909 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
5910 return bnxt_get_ulp_msix_base(bp) + ulp_stat;
5911
5912 return cp + ulp_stat;
5913 }
5914
5915 static bool bnxt_need_reserve_rings(struct bnxt *bp)
5916 {
5917 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5918 int cp = bnxt_cp_rings_in_use(bp);
5919 int nq = bnxt_nq_rings_in_use(bp);
5920 int rx = bp->rx_nr_rings, stat;
5921 int vnic = 1, grp = rx;
5922
5923 if (bp->hwrm_spec_code < 0x10601)
5924 return false;
5925
5926 if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
5927 return true;
5928
5929 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5930 vnic = rx + 1;
5931 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5932 rx <<= 1;
5933 stat = bnxt_get_func_stat_ctxs(bp);
5934 if (BNXT_NEW_RM(bp) &&
5935 (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
5936 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
5937 (hw_resc->resv_hw_ring_grps != grp &&
5938 !(bp->flags & BNXT_FLAG_CHIP_P5))))
5939 return true;
5940 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
5941 hw_resc->resv_irqs != nq)
5942 return true;
5943 return false;
5944 }
5945
5946 static int __bnxt_reserve_rings(struct bnxt *bp)
5947 {
5948 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5949 int cp = bnxt_nq_rings_in_use(bp);
5950 int tx = bp->tx_nr_rings;
5951 int rx = bp->rx_nr_rings;
5952 int grp, rx_rings, rc;
5953 int vnic = 1, stat;
5954 bool sh = false;
5955
5956 if (!bnxt_need_reserve_rings(bp))
5957 return 0;
5958
5959 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5960 sh = true;
5961 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5962 vnic = rx + 1;
5963 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5964 rx <<= 1;
5965 grp = bp->rx_nr_rings;
5966 stat = bnxt_get_func_stat_ctxs(bp);
5967
5968 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
5969 if (rc)
5970 return rc;
5971
5972 tx = hw_resc->resv_tx_rings;
5973 if (BNXT_NEW_RM(bp)) {
5974 rx = hw_resc->resv_rx_rings;
5975 cp = hw_resc->resv_irqs;
5976 grp = hw_resc->resv_hw_ring_grps;
5977 vnic = hw_resc->resv_vnics;
5978 stat = hw_resc->resv_stat_ctxs;
5979 }
5980
5981 rx_rings = rx;
5982 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5983 if (rx >= 2) {
5984 rx_rings = rx >> 1;
5985 } else {
5986 if (netif_running(bp->dev))
5987 return -ENOMEM;
5988
5989 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
5990 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
5991 bp->dev->hw_features &= ~NETIF_F_LRO;
5992 bp->dev->features &= ~NETIF_F_LRO;
5993 bnxt_set_ring_params(bp);
5994 }
5995 }
5996 rx_rings = min_t(int, rx_rings, grp);
5997 cp = min_t(int, cp, bp->cp_nr_rings);
5998 if (stat > bnxt_get_ulp_stat_ctxs(bp))
5999 stat -= bnxt_get_ulp_stat_ctxs(bp);
6000 cp = min_t(int, cp, stat);
6001 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
6002 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6003 rx = rx_rings << 1;
6004 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
6005 bp->tx_nr_rings = tx;
6006 bp->rx_nr_rings = rx_rings;
6007 bp->cp_nr_rings = cp;
6008
6009 if (!tx || !rx || !cp || !grp || !vnic || !stat)
6010 return -ENOMEM;
6011
6012 return rc;
6013 }
6014
6015 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6016 int ring_grps, int cp_rings, int stats,
6017 int vnics)
6018 {
6019 struct hwrm_func_vf_cfg_input req = {0};
6020 u32 flags;
6021 int rc;
6022
6023 if (!BNXT_NEW_RM(bp))
6024 return 0;
6025
6026 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6027 cp_rings, stats, vnics);
6028 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
6029 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6030 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6031 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6032 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
6033 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
6034 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6035 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6036
6037 req.flags = cpu_to_le32(flags);
6038 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6039 return rc;
6040 }
6041
6042 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6043 int ring_grps, int cp_rings, int stats,
6044 int vnics)
6045 {
6046 struct hwrm_func_cfg_input req = {0};
6047 u32 flags;
6048 int rc;
6049
6050 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6051 cp_rings, stats, vnics);
6052 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
6053 if (BNXT_NEW_RM(bp)) {
6054 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6055 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6056 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6057 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
6058 if (bp->flags & BNXT_FLAG_CHIP_P5)
6059 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
6060 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
6061 else
6062 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6063 }
6064
6065 req.flags = cpu_to_le32(flags);
6066 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6067 return rc;
6068 }
6069
6070 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6071 int ring_grps, int cp_rings, int stats,
6072 int vnics)
6073 {
6074 if (bp->hwrm_spec_code < 0x10801)
6075 return 0;
6076
6077 if (BNXT_PF(bp))
6078 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
6079 ring_grps, cp_rings, stats,
6080 vnics);
6081
6082 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6083 cp_rings, stats, vnics);
6084 }
6085
6086 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
6087 {
6088 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6089 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6090 struct hwrm_ring_aggint_qcaps_input req = {0};
6091 int rc;
6092
6093 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
6094 coal_cap->num_cmpl_dma_aggr_max = 63;
6095 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
6096 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
6097 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
6098 coal_cap->int_lat_tmr_min_max = 65535;
6099 coal_cap->int_lat_tmr_max_max = 65535;
6100 coal_cap->num_cmpl_aggr_int_max = 65535;
6101 coal_cap->timer_units = 80;
6102
6103 if (bp->hwrm_spec_code < 0x10902)
6104 return;
6105
6106 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
6107 mutex_lock(&bp->hwrm_cmd_lock);
6108 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6109 if (!rc) {
6110 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
6111 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
6112 coal_cap->num_cmpl_dma_aggr_max =
6113 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
6114 coal_cap->num_cmpl_dma_aggr_during_int_max =
6115 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
6116 coal_cap->cmpl_aggr_dma_tmr_max =
6117 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
6118 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
6119 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
6120 coal_cap->int_lat_tmr_min_max =
6121 le16_to_cpu(resp->int_lat_tmr_min_max);
6122 coal_cap->int_lat_tmr_max_max =
6123 le16_to_cpu(resp->int_lat_tmr_max_max);
6124 coal_cap->num_cmpl_aggr_int_max =
6125 le16_to_cpu(resp->num_cmpl_aggr_int_max);
6126 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
6127 }
6128 mutex_unlock(&bp->hwrm_cmd_lock);
6129 }
6130
6131 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
6132 {
6133 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6134
6135 return usec * 1000 / coal_cap->timer_units;
6136 }
6137
6138 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
6139 struct bnxt_coal *hw_coal,
6140 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
6141 {
6142 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6143 u32 cmpl_params = coal_cap->cmpl_params;
6144 u16 val, tmr, max, flags = 0;
6145
6146 max = hw_coal->bufs_per_record * 128;
6147 if (hw_coal->budget)
6148 max = hw_coal->bufs_per_record * hw_coal->budget;
6149 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
6150
6151 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
6152 req->num_cmpl_aggr_int = cpu_to_le16(val);
6153
6154 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
6155 req->num_cmpl_dma_aggr = cpu_to_le16(val);
6156
6157 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
6158 coal_cap->num_cmpl_dma_aggr_during_int_max);
6159 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
6160
6161 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
6162 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
6163 req->int_lat_tmr_max = cpu_to_le16(tmr);
6164
6165
6166 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
6167 val = tmr / 2;
6168 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
6169 req->int_lat_tmr_min = cpu_to_le16(val);
6170 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6171 }
6172
6173
6174 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
6175 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
6176
6177 if (cmpl_params &
6178 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
6179 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
6180 val = clamp_t(u16, tmr, 1,
6181 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
6182 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val);
6183 req->enables |=
6184 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
6185 }
6186
6187 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
6188 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
6189 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
6190 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
6191 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
6192 req->flags = cpu_to_le16(flags);
6193 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
6194 }
6195
6196
6197 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
6198 struct bnxt_coal *hw_coal)
6199 {
6200 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
6201 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6202 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6203 u32 nq_params = coal_cap->nq_params;
6204 u16 tmr;
6205
6206 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
6207 return 0;
6208
6209 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
6210 -1, -1);
6211 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
6212 req.flags =
6213 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
6214
6215 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
6216 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
6217 req.int_lat_tmr_min = cpu_to_le16(tmr);
6218 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6219 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6220 }
6221
6222 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
6223 {
6224 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
6225 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6226 struct bnxt_coal coal;
6227
6228
6229
6230
6231 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
6232
6233 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
6234 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
6235
6236 if (!bnapi->rx_ring)
6237 return -ENODEV;
6238
6239 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
6240 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6241
6242 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
6243
6244 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
6245
6246 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
6247 HWRM_CMD_TIMEOUT);
6248 }
6249
6250 int bnxt_hwrm_set_coal(struct bnxt *bp)
6251 {
6252 int i, rc = 0;
6253 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
6254 req_tx = {0}, *req;
6255
6256 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
6257 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6258 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
6259 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6260
6261 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
6262 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
6263
6264 mutex_lock(&bp->hwrm_cmd_lock);
6265 for (i = 0; i < bp->cp_nr_rings; i++) {
6266 struct bnxt_napi *bnapi = bp->bnapi[i];
6267 struct bnxt_coal *hw_coal;
6268 u16 ring_id;
6269
6270 req = &req_rx;
6271 if (!bnapi->rx_ring) {
6272 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6273 req = &req_tx;
6274 } else {
6275 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
6276 }
6277 req->ring_id = cpu_to_le16(ring_id);
6278
6279 rc = _hwrm_send_message(bp, req, sizeof(*req),
6280 HWRM_CMD_TIMEOUT);
6281 if (rc)
6282 break;
6283
6284 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6285 continue;
6286
6287 if (bnapi->rx_ring && bnapi->tx_ring) {
6288 req = &req_tx;
6289 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6290 req->ring_id = cpu_to_le16(ring_id);
6291 rc = _hwrm_send_message(bp, req, sizeof(*req),
6292 HWRM_CMD_TIMEOUT);
6293 if (rc)
6294 break;
6295 }
6296 if (bnapi->rx_ring)
6297 hw_coal = &bp->rx_coal;
6298 else
6299 hw_coal = &bp->tx_coal;
6300 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
6301 }
6302 mutex_unlock(&bp->hwrm_cmd_lock);
6303 return rc;
6304 }
6305
6306 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
6307 {
6308 int rc = 0, i;
6309 struct hwrm_stat_ctx_free_input req = {0};
6310
6311 if (!bp->bnapi)
6312 return 0;
6313
6314 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6315 return 0;
6316
6317 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
6318
6319 mutex_lock(&bp->hwrm_cmd_lock);
6320 for (i = 0; i < bp->cp_nr_rings; i++) {
6321 struct bnxt_napi *bnapi = bp->bnapi[i];
6322 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6323
6324 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
6325 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
6326
6327 rc = _hwrm_send_message(bp, &req, sizeof(req),
6328 HWRM_CMD_TIMEOUT);
6329
6330 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
6331 }
6332 }
6333 mutex_unlock(&bp->hwrm_cmd_lock);
6334 return rc;
6335 }
6336
6337 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
6338 {
6339 int rc = 0, i;
6340 struct hwrm_stat_ctx_alloc_input req = {0};
6341 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6342
6343 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6344 return 0;
6345
6346 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
6347
6348 req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size);
6349 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
6350
6351 mutex_lock(&bp->hwrm_cmd_lock);
6352 for (i = 0; i < bp->cp_nr_rings; i++) {
6353 struct bnxt_napi *bnapi = bp->bnapi[i];
6354 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6355
6356 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
6357
6358 rc = _hwrm_send_message(bp, &req, sizeof(req),
6359 HWRM_CMD_TIMEOUT);
6360 if (rc)
6361 break;
6362
6363 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
6364
6365 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
6366 }
6367 mutex_unlock(&bp->hwrm_cmd_lock);
6368 return rc;
6369 }
6370
6371 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
6372 {
6373 struct hwrm_func_qcfg_input req = {0};
6374 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6375 u16 flags;
6376 int rc;
6377
6378 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6379 req.fid = cpu_to_le16(0xffff);
6380 mutex_lock(&bp->hwrm_cmd_lock);
6381 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6382 if (rc)
6383 goto func_qcfg_exit;
6384
6385 #ifdef CONFIG_BNXT_SRIOV
6386 if (BNXT_VF(bp)) {
6387 struct bnxt_vf_info *vf = &bp->vf;
6388
6389 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
6390 } else {
6391 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs);
6392 }
6393 #endif
6394 flags = le16_to_cpu(resp->flags);
6395 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
6396 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
6397 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6398 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6399 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6400 }
6401 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6402 bp->flags |= BNXT_FLAG_MULTI_HOST;
6403
6404 switch (resp->port_partition_type) {
6405 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6406 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6407 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6408 bp->port_partition_type = resp->port_partition_type;
6409 break;
6410 }
6411 if (bp->hwrm_spec_code < 0x10707 ||
6412 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
6413 bp->br_mode = BRIDGE_MODE_VEB;
6414 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
6415 bp->br_mode = BRIDGE_MODE_VEPA;
6416 else
6417 bp->br_mode = BRIDGE_MODE_UNDEF;
6418
6419 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
6420 if (!bp->max_mtu)
6421 bp->max_mtu = BNXT_MAX_MTU;
6422
6423 func_qcfg_exit:
6424 mutex_unlock(&bp->hwrm_cmd_lock);
6425 return rc;
6426 }
6427
6428 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
6429 {
6430 struct hwrm_func_backing_store_qcaps_input req = {0};
6431 struct hwrm_func_backing_store_qcaps_output *resp =
6432 bp->hwrm_cmd_resp_addr;
6433 int rc;
6434
6435 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
6436 return 0;
6437
6438 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
6439 mutex_lock(&bp->hwrm_cmd_lock);
6440 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6441 if (!rc) {
6442 struct bnxt_ctx_pg_info *ctx_pg;
6443 struct bnxt_ctx_mem_info *ctx;
6444 int i;
6445
6446 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6447 if (!ctx) {
6448 rc = -ENOMEM;
6449 goto ctx_err;
6450 }
6451 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
6452 if (!ctx_pg) {
6453 kfree(ctx);
6454 rc = -ENOMEM;
6455 goto ctx_err;
6456 }
6457 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
6458 ctx->tqm_mem[i] = ctx_pg;
6459
6460 bp->ctx = ctx;
6461 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6462 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6463 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6464 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6465 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6466 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6467 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6468 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6469 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6470 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6471 ctx->vnic_max_vnic_entries =
6472 le16_to_cpu(resp->vnic_max_vnic_entries);
6473 ctx->vnic_max_ring_table_entries =
6474 le16_to_cpu(resp->vnic_max_ring_table_entries);
6475 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6476 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6477 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6478 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6479 ctx->tqm_min_entries_per_ring =
6480 le32_to_cpu(resp->tqm_min_entries_per_ring);
6481 ctx->tqm_max_entries_per_ring =
6482 le32_to_cpu(resp->tqm_max_entries_per_ring);
6483 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6484 if (!ctx->tqm_entries_multiple)
6485 ctx->tqm_entries_multiple = 1;
6486 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6487 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6488 ctx->mrav_num_entries_units =
6489 le16_to_cpu(resp->mrav_num_entries_units);
6490 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6491 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6492 } else {
6493 rc = 0;
6494 }
6495 ctx_err:
6496 mutex_unlock(&bp->hwrm_cmd_lock);
6497 return rc;
6498 }
6499
6500 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6501 __le64 *pg_dir)
6502 {
6503 u8 pg_size = 0;
6504
6505 if (BNXT_PAGE_SHIFT == 13)
6506 pg_size = 1 << 4;
6507 else if (BNXT_PAGE_SIZE == 16)
6508 pg_size = 2 << 4;
6509
6510 *pg_attr = pg_size;
6511 if (rmem->depth >= 1) {
6512 if (rmem->depth == 2)
6513 *pg_attr |= 2;
6514 else
6515 *pg_attr |= 1;
6516 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6517 } else {
6518 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6519 }
6520 }
6521
6522 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
6523 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \
6524 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \
6525 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \
6526 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \
6527 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6528
6529 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6530 {
6531 struct hwrm_func_backing_store_cfg_input req = {0};
6532 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6533 struct bnxt_ctx_pg_info *ctx_pg;
6534 __le32 *num_entries;
6535 __le64 *pg_dir;
6536 u32 flags = 0;
6537 u8 *pg_attr;
6538 int i, rc;
6539 u32 ena;
6540
6541 if (!ctx)
6542 return 0;
6543
6544 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6545 req.enables = cpu_to_le32(enables);
6546
6547 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6548 ctx_pg = &ctx->qp_mem;
6549 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6550 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6551 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6552 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6553 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6554 &req.qpc_pg_size_qpc_lvl,
6555 &req.qpc_page_dir);
6556 }
6557 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6558 ctx_pg = &ctx->srq_mem;
6559 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6560 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6561 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6562 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6563 &req.srq_pg_size_srq_lvl,
6564 &req.srq_page_dir);
6565 }
6566 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6567 ctx_pg = &ctx->cq_mem;
6568 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6569 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6570 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6571 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6572 &req.cq_page_dir);
6573 }
6574 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6575 ctx_pg = &ctx->vnic_mem;
6576 req.vnic_num_vnic_entries =
6577 cpu_to_le16(ctx->vnic_max_vnic_entries);
6578 req.vnic_num_ring_table_entries =
6579 cpu_to_le16(ctx->vnic_max_ring_table_entries);
6580 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6581 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6582 &req.vnic_pg_size_vnic_lvl,
6583 &req.vnic_page_dir);
6584 }
6585 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6586 ctx_pg = &ctx->stat_mem;
6587 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
6588 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
6589 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6590 &req.stat_pg_size_stat_lvl,
6591 &req.stat_page_dir);
6592 }
6593 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
6594 ctx_pg = &ctx->mrav_mem;
6595 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
6596 if (ctx->mrav_num_entries_units)
6597 flags |=
6598 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
6599 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
6600 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6601 &req.mrav_pg_size_mrav_lvl,
6602 &req.mrav_page_dir);
6603 }
6604 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
6605 ctx_pg = &ctx->tim_mem;
6606 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
6607 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
6608 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6609 &req.tim_pg_size_tim_lvl,
6610 &req.tim_page_dir);
6611 }
6612 for (i = 0, num_entries = &req.tqm_sp_num_entries,
6613 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
6614 pg_dir = &req.tqm_sp_page_dir,
6615 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
6616 i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
6617 if (!(enables & ena))
6618 continue;
6619
6620 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
6621 ctx_pg = ctx->tqm_mem[i];
6622 *num_entries = cpu_to_le32(ctx_pg->entries);
6623 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
6624 }
6625 req.flags = cpu_to_le32(flags);
6626 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6627 return rc;
6628 }
6629
6630 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
6631 struct bnxt_ctx_pg_info *ctx_pg)
6632 {
6633 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6634
6635 rmem->page_size = BNXT_PAGE_SIZE;
6636 rmem->pg_arr = ctx_pg->ctx_pg_arr;
6637 rmem->dma_arr = ctx_pg->ctx_dma_arr;
6638 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
6639 if (rmem->depth >= 1)
6640 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
6641 return bnxt_alloc_ring(bp, rmem);
6642 }
6643
6644 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
6645 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
6646 u8 depth)
6647 {
6648 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6649 int rc;
6650
6651 if (!mem_size)
6652 return -EINVAL;
6653
6654 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6655 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
6656 ctx_pg->nr_pages = 0;
6657 return -EINVAL;
6658 }
6659 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
6660 int nr_tbls, i;
6661
6662 rmem->depth = 2;
6663 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
6664 GFP_KERNEL);
6665 if (!ctx_pg->ctx_pg_tbl)
6666 return -ENOMEM;
6667 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
6668 rmem->nr_pages = nr_tbls;
6669 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6670 if (rc)
6671 return rc;
6672 for (i = 0; i < nr_tbls; i++) {
6673 struct bnxt_ctx_pg_info *pg_tbl;
6674
6675 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
6676 if (!pg_tbl)
6677 return -ENOMEM;
6678 ctx_pg->ctx_pg_tbl[i] = pg_tbl;
6679 rmem = &pg_tbl->ring_mem;
6680 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
6681 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
6682 rmem->depth = 1;
6683 rmem->nr_pages = MAX_CTX_PAGES;
6684 if (i == (nr_tbls - 1)) {
6685 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
6686
6687 if (rem)
6688 rmem->nr_pages = rem;
6689 }
6690 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
6691 if (rc)
6692 break;
6693 }
6694 } else {
6695 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6696 if (rmem->nr_pages > 1 || depth)
6697 rmem->depth = 1;
6698 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6699 }
6700 return rc;
6701 }
6702
6703 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
6704 struct bnxt_ctx_pg_info *ctx_pg)
6705 {
6706 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6707
6708 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
6709 ctx_pg->ctx_pg_tbl) {
6710 int i, nr_tbls = rmem->nr_pages;
6711
6712 for (i = 0; i < nr_tbls; i++) {
6713 struct bnxt_ctx_pg_info *pg_tbl;
6714 struct bnxt_ring_mem_info *rmem2;
6715
6716 pg_tbl = ctx_pg->ctx_pg_tbl[i];
6717 if (!pg_tbl)
6718 continue;
6719 rmem2 = &pg_tbl->ring_mem;
6720 bnxt_free_ring(bp, rmem2);
6721 ctx_pg->ctx_pg_arr[i] = NULL;
6722 kfree(pg_tbl);
6723 ctx_pg->ctx_pg_tbl[i] = NULL;
6724 }
6725 kfree(ctx_pg->ctx_pg_tbl);
6726 ctx_pg->ctx_pg_tbl = NULL;
6727 }
6728 bnxt_free_ring(bp, rmem);
6729 ctx_pg->nr_pages = 0;
6730 }
6731
6732 static void bnxt_free_ctx_mem(struct bnxt *bp)
6733 {
6734 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6735 int i;
6736
6737 if (!ctx)
6738 return;
6739
6740 if (ctx->tqm_mem[0]) {
6741 for (i = 0; i < bp->max_q + 1; i++)
6742 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
6743 kfree(ctx->tqm_mem[0]);
6744 ctx->tqm_mem[0] = NULL;
6745 }
6746
6747 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
6748 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
6749 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
6750 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
6751 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
6752 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
6753 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
6754 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
6755 }
6756
6757 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
6758 {
6759 struct bnxt_ctx_pg_info *ctx_pg;
6760 struct bnxt_ctx_mem_info *ctx;
6761 u32 mem_size, ena, entries;
6762 u32 num_mr, num_ah;
6763 u32 extra_srqs = 0;
6764 u32 extra_qps = 0;
6765 u8 pg_lvl = 1;
6766 int i, rc;
6767
6768 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
6769 if (rc) {
6770 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
6771 rc);
6772 return rc;
6773 }
6774 ctx = bp->ctx;
6775 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
6776 return 0;
6777
6778 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
6779 pg_lvl = 2;
6780 extra_qps = 65536;
6781 extra_srqs = 8192;
6782 }
6783
6784 ctx_pg = &ctx->qp_mem;
6785 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
6786 extra_qps;
6787 mem_size = ctx->qp_entry_size * ctx_pg->entries;
6788 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6789 if (rc)
6790 return rc;
6791
6792 ctx_pg = &ctx->srq_mem;
6793 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
6794 mem_size = ctx->srq_entry_size * ctx_pg->entries;
6795 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6796 if (rc)
6797 return rc;
6798
6799 ctx_pg = &ctx->cq_mem;
6800 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
6801 mem_size = ctx->cq_entry_size * ctx_pg->entries;
6802 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6803 if (rc)
6804 return rc;
6805
6806 ctx_pg = &ctx->vnic_mem;
6807 ctx_pg->entries = ctx->vnic_max_vnic_entries +
6808 ctx->vnic_max_ring_table_entries;
6809 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
6810 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6811 if (rc)
6812 return rc;
6813
6814 ctx_pg = &ctx->stat_mem;
6815 ctx_pg->entries = ctx->stat_max_entries;
6816 mem_size = ctx->stat_entry_size * ctx_pg->entries;
6817 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6818 if (rc)
6819 return rc;
6820
6821 ena = 0;
6822 if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
6823 goto skip_rdma;
6824
6825 ctx_pg = &ctx->mrav_mem;
6826
6827
6828
6829 num_mr = 1024 * 256;
6830 num_ah = 1024 * 128;
6831 ctx_pg->entries = num_mr + num_ah;
6832 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
6833 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2);
6834 if (rc)
6835 return rc;
6836 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
6837 if (ctx->mrav_num_entries_units)
6838 ctx_pg->entries =
6839 ((num_mr / ctx->mrav_num_entries_units) << 16) |
6840 (num_ah / ctx->mrav_num_entries_units);
6841
6842 ctx_pg = &ctx->tim_mem;
6843 ctx_pg->entries = ctx->qp_mem.entries;
6844 mem_size = ctx->tim_entry_size * ctx_pg->entries;
6845 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6846 if (rc)
6847 return rc;
6848 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
6849
6850 skip_rdma:
6851 entries = ctx->qp_max_l2_entries + extra_qps;
6852 entries = roundup(entries, ctx->tqm_entries_multiple);
6853 entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
6854 ctx->tqm_max_entries_per_ring);
6855 for (i = 0; i < bp->max_q + 1; i++) {
6856 ctx_pg = ctx->tqm_mem[i];
6857 ctx_pg->entries = entries;
6858 mem_size = ctx->tqm_entry_size * entries;
6859 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6860 if (rc)
6861 return rc;
6862 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
6863 }
6864 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
6865 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
6866 if (rc) {
6867 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
6868 rc);
6869 return rc;
6870 }
6871 ctx->flags |= BNXT_CTX_FLAG_INITED;
6872 return 0;
6873 }
6874
6875 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
6876 {
6877 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6878 struct hwrm_func_resource_qcaps_input req = {0};
6879 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6880 int rc;
6881
6882 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
6883 req.fid = cpu_to_le16(0xffff);
6884
6885 mutex_lock(&bp->hwrm_cmd_lock);
6886 rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
6887 HWRM_CMD_TIMEOUT);
6888 if (rc)
6889 goto hwrm_func_resc_qcaps_exit;
6890
6891 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
6892 if (!all)
6893 goto hwrm_func_resc_qcaps_exit;
6894
6895 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
6896 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6897 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
6898 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6899 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
6900 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6901 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
6902 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6903 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
6904 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
6905 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
6906 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6907 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
6908 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6909 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
6910 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6911
6912 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6913 u16 max_msix = le16_to_cpu(resp->max_msix);
6914
6915 hw_resc->max_nqs = max_msix;
6916 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
6917 }
6918
6919 if (BNXT_PF(bp)) {
6920 struct bnxt_pf_info *pf = &bp->pf;
6921
6922 pf->vf_resv_strategy =
6923 le16_to_cpu(resp->vf_reservation_strategy);
6924 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
6925 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
6926 }
6927 hwrm_func_resc_qcaps_exit:
6928 mutex_unlock(&bp->hwrm_cmd_lock);
6929 return rc;
6930 }
6931
6932 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
6933 {
6934 int rc = 0;
6935 struct hwrm_func_qcaps_input req = {0};
6936 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6937 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6938 u32 flags;
6939
6940 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
6941 req.fid = cpu_to_le16(0xffff);
6942
6943 mutex_lock(&bp->hwrm_cmd_lock);
6944 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6945 if (rc)
6946 goto hwrm_func_qcaps_exit;
6947
6948 flags = le32_to_cpu(resp->flags);
6949 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
6950 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6951 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
6952 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
6953 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
6954 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
6955 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
6956 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
6957 if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE)
6958 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
6959 if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD)
6960 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
6961
6962 bp->tx_push_thresh = 0;
6963 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
6964 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
6965
6966 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6967 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6968 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6969 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6970 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
6971 if (!hw_resc->max_hw_ring_grps)
6972 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
6973 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6974 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6975 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6976
6977 if (BNXT_PF(bp)) {
6978 struct bnxt_pf_info *pf = &bp->pf;
6979
6980 pf->fw_fid = le16_to_cpu(resp->fid);
6981 pf->port_id = le16_to_cpu(resp->port_id);
6982 bp->dev->dev_port = pf->port_id;
6983 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
6984 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
6985 pf->max_vfs = le16_to_cpu(resp->max_vfs);
6986 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
6987 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
6988 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
6989 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
6990 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
6991 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6992 bp->flags &= ~BNXT_FLAG_WOL_CAP;
6993 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
6994 bp->flags |= BNXT_FLAG_WOL_CAP;
6995 } else {
6996 #ifdef CONFIG_BNXT_SRIOV
6997 struct bnxt_vf_info *vf = &bp->vf;
6998
6999 vf->fw_fid = le16_to_cpu(resp->fid);
7000 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
7001 #endif
7002 }
7003
7004 hwrm_func_qcaps_exit:
7005 mutex_unlock(&bp->hwrm_cmd_lock);
7006 return rc;
7007 }
7008
7009 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
7010
7011 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
7012 {
7013 int rc;
7014
7015 rc = __bnxt_hwrm_func_qcaps(bp);
7016 if (rc)
7017 return rc;
7018 rc = bnxt_hwrm_queue_qportcfg(bp);
7019 if (rc) {
7020 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
7021 return rc;
7022 }
7023 if (bp->hwrm_spec_code >= 0x10803) {
7024 rc = bnxt_alloc_ctx_mem(bp);
7025 if (rc)
7026 return rc;
7027 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
7028 if (!rc)
7029 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
7030 }
7031 return 0;
7032 }
7033
7034 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
7035 {
7036 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
7037 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
7038 int rc = 0;
7039 u32 flags;
7040
7041 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
7042 return 0;
7043
7044 resp = bp->hwrm_cmd_resp_addr;
7045 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1);
7046
7047 mutex_lock(&bp->hwrm_cmd_lock);
7048 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7049 if (rc)
7050 goto hwrm_cfa_adv_qcaps_exit;
7051
7052 flags = le32_to_cpu(resp->flags);
7053 if (flags &
7054 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED)
7055 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX;
7056
7057 hwrm_cfa_adv_qcaps_exit:
7058 mutex_unlock(&bp->hwrm_cmd_lock);
7059 return rc;
7060 }
7061
7062 static int bnxt_map_fw_health_regs(struct bnxt *bp)
7063 {
7064 struct bnxt_fw_health *fw_health = bp->fw_health;
7065 u32 reg_base = 0xffffffff;
7066 int i;
7067
7068
7069 for (i = 0; i < 4; i++) {
7070 u32 reg = fw_health->regs[i];
7071
7072 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC)
7073 continue;
7074 if (reg_base == 0xffffffff)
7075 reg_base = reg & BNXT_GRC_BASE_MASK;
7076 if ((reg & BNXT_GRC_BASE_MASK) != reg_base)
7077 return -ERANGE;
7078 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_BASE +
7079 (reg & BNXT_GRC_OFFSET_MASK);
7080 }
7081 if (reg_base == 0xffffffff)
7082 return 0;
7083
7084 writel(reg_base, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT +
7085 BNXT_FW_HEALTH_WIN_MAP_OFF);
7086 return 0;
7087 }
7088
7089 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
7090 {
7091 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7092 struct bnxt_fw_health *fw_health = bp->fw_health;
7093 struct hwrm_error_recovery_qcfg_input req = {0};
7094 int rc, i;
7095
7096 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
7097 return 0;
7098
7099 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1);
7100 mutex_lock(&bp->hwrm_cmd_lock);
7101 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7102 if (rc)
7103 goto err_recovery_out;
7104 fw_health->flags = le32_to_cpu(resp->flags);
7105 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) &&
7106 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) {
7107 rc = -EINVAL;
7108 goto err_recovery_out;
7109 }
7110 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq);
7111 fw_health->master_func_wait_dsecs =
7112 le32_to_cpu(resp->master_func_wait_period);
7113 fw_health->normal_func_wait_dsecs =
7114 le32_to_cpu(resp->normal_func_wait_period);
7115 fw_health->post_reset_wait_dsecs =
7116 le32_to_cpu(resp->master_func_wait_period_after_reset);
7117 fw_health->post_reset_max_wait_dsecs =
7118 le32_to_cpu(resp->max_bailout_time_after_reset);
7119 fw_health->regs[BNXT_FW_HEALTH_REG] =
7120 le32_to_cpu(resp->fw_health_status_reg);
7121 fw_health->regs[BNXT_FW_HEARTBEAT_REG] =
7122 le32_to_cpu(resp->fw_heartbeat_reg);
7123 fw_health->regs[BNXT_FW_RESET_CNT_REG] =
7124 le32_to_cpu(resp->fw_reset_cnt_reg);
7125 fw_health->regs[BNXT_FW_RESET_INPROG_REG] =
7126 le32_to_cpu(resp->reset_inprogress_reg);
7127 fw_health->fw_reset_inprog_reg_mask =
7128 le32_to_cpu(resp->reset_inprogress_reg_mask);
7129 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt;
7130 if (fw_health->fw_reset_seq_cnt >= 16) {
7131 rc = -EINVAL;
7132 goto err_recovery_out;
7133 }
7134 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) {
7135 fw_health->fw_reset_seq_regs[i] =
7136 le32_to_cpu(resp->reset_reg[i]);
7137 fw_health->fw_reset_seq_vals[i] =
7138 le32_to_cpu(resp->reset_reg_val[i]);
7139 fw_health->fw_reset_seq_delay_msec[i] =
7140 resp->delay_after_reset[i];
7141 }
7142 err_recovery_out:
7143 mutex_unlock(&bp->hwrm_cmd_lock);
7144 if (!rc)
7145 rc = bnxt_map_fw_health_regs(bp);
7146 if (rc)
7147 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
7148 return rc;
7149 }
7150
7151 static int bnxt_hwrm_func_reset(struct bnxt *bp)
7152 {
7153 struct hwrm_func_reset_input req = {0};
7154
7155 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
7156 req.enables = 0;
7157
7158 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
7159 }
7160
7161 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
7162 {
7163 int rc = 0;
7164 struct hwrm_queue_qportcfg_input req = {0};
7165 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
7166 u8 i, j, *qptr;
7167 bool no_rdma;
7168
7169 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
7170
7171 mutex_lock(&bp->hwrm_cmd_lock);
7172 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7173 if (rc)
7174 goto qportcfg_exit;
7175
7176 if (!resp->max_configurable_queues) {
7177 rc = -EINVAL;
7178 goto qportcfg_exit;
7179 }
7180 bp->max_tc = resp->max_configurable_queues;
7181 bp->max_lltc = resp->max_configurable_lossless_queues;
7182 if (bp->max_tc > BNXT_MAX_QUEUE)
7183 bp->max_tc = BNXT_MAX_QUEUE;
7184
7185 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
7186 qptr = &resp->queue_id0;
7187 for (i = 0, j = 0; i < bp->max_tc; i++) {
7188 bp->q_info[j].queue_id = *qptr;
7189 bp->q_ids[i] = *qptr++;
7190 bp->q_info[j].queue_profile = *qptr++;
7191 bp->tc_to_qidx[j] = j;
7192 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
7193 (no_rdma && BNXT_PF(bp)))
7194 j++;
7195 }
7196 bp->max_q = bp->max_tc;
7197 bp->max_tc = max_t(u8, j, 1);
7198
7199 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
7200 bp->max_tc = 1;
7201
7202 if (bp->max_lltc > bp->max_tc)
7203 bp->max_lltc = bp->max_tc;
7204
7205 qportcfg_exit:
7206 mutex_unlock(&bp->hwrm_cmd_lock);
7207 return rc;
7208 }
7209
7210 static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent)
7211 {
7212 struct hwrm_ver_get_input req = {0};
7213 int rc;
7214
7215 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
7216 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
7217 req.hwrm_intf_min = HWRM_VERSION_MINOR;
7218 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
7219
7220 rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT,
7221 silent);
7222 return rc;
7223 }
7224
7225 static int bnxt_hwrm_ver_get(struct bnxt *bp)
7226 {
7227 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
7228 u32 dev_caps_cfg;
7229 int rc;
7230
7231 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
7232 mutex_lock(&bp->hwrm_cmd_lock);
7233 rc = __bnxt_hwrm_ver_get(bp, false);
7234 if (rc)
7235 goto hwrm_ver_get_exit;
7236
7237 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
7238
7239 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
7240 resp->hwrm_intf_min_8b << 8 |
7241 resp->hwrm_intf_upd_8b;
7242 if (resp->hwrm_intf_maj_8b < 1) {
7243 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
7244 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
7245 resp->hwrm_intf_upd_8b);
7246 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
7247 }
7248 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
7249 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
7250 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
7251
7252 if (strlen(resp->active_pkg_name)) {
7253 int fw_ver_len = strlen(bp->fw_ver_str);
7254
7255 snprintf(bp->fw_ver_str + fw_ver_len,
7256 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
7257 resp->active_pkg_name);
7258 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
7259 }
7260
7261 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
7262 if (!bp->hwrm_cmd_timeout)
7263 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
7264
7265 if (resp->hwrm_intf_maj_8b >= 1) {
7266 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
7267 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
7268 }
7269 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
7270 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
7271
7272 bp->chip_num = le16_to_cpu(resp->chip_num);
7273 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
7274 !resp->chip_metal)
7275 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
7276
7277 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
7278 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
7279 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
7280 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
7281
7282 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
7283 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
7284
7285 if (dev_caps_cfg &
7286 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
7287 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
7288
7289 if (dev_caps_cfg &
7290 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
7291 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
7292
7293 if (dev_caps_cfg &
7294 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
7295 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
7296
7297 hwrm_ver_get_exit:
7298 mutex_unlock(&bp->hwrm_cmd_lock);
7299 return rc;
7300 }
7301
7302 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
7303 {
7304 struct hwrm_fw_set_time_input req = {0};
7305 struct tm tm;
7306 time64_t now = ktime_get_real_seconds();
7307
7308 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
7309 bp->hwrm_spec_code < 0x10400)
7310 return -EOPNOTSUPP;
7311
7312 time64_to_tm(now, 0, &tm);
7313 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
7314 req.year = cpu_to_le16(1900 + tm.tm_year);
7315 req.month = 1 + tm.tm_mon;
7316 req.day = tm.tm_mday;
7317 req.hour = tm.tm_hour;
7318 req.minute = tm.tm_min;
7319 req.second = tm.tm_sec;
7320 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7321 }
7322
7323 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
7324 {
7325 int rc;
7326 struct bnxt_pf_info *pf = &bp->pf;
7327 struct hwrm_port_qstats_input req = {0};
7328
7329 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
7330 return 0;
7331
7332 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
7333 req.port_id = cpu_to_le16(pf->port_id);
7334 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
7335 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
7336 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7337 return rc;
7338 }
7339
7340 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
7341 {
7342 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
7343 struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
7344 struct hwrm_port_qstats_ext_input req = {0};
7345 struct bnxt_pf_info *pf = &bp->pf;
7346 u32 tx_stat_size;
7347 int rc;
7348
7349 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
7350 return 0;
7351
7352 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
7353 req.port_id = cpu_to_le16(pf->port_id);
7354 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
7355 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
7356 tx_stat_size = bp->hw_tx_port_stats_ext ?
7357 sizeof(*bp->hw_tx_port_stats_ext) : 0;
7358 req.tx_stat_size = cpu_to_le16(tx_stat_size);
7359 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
7360 mutex_lock(&bp->hwrm_cmd_lock);
7361 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7362 if (!rc) {
7363 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
7364 bp->fw_tx_stats_ext_size = tx_stat_size ?
7365 le16_to_cpu(resp->tx_stat_size) / 8 : 0;
7366 } else {
7367 bp->fw_rx_stats_ext_size = 0;
7368 bp->fw_tx_stats_ext_size = 0;
7369 }
7370 if (bp->fw_tx_stats_ext_size <=
7371 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
7372 mutex_unlock(&bp->hwrm_cmd_lock);
7373 bp->pri2cos_valid = 0;
7374 return rc;
7375 }
7376
7377 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
7378 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
7379
7380 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
7381 if (!rc) {
7382 struct hwrm_queue_pri2cos_qcfg_output *resp2;
7383 u8 *pri2cos;
7384 int i, j;
7385
7386 resp2 = bp->hwrm_cmd_resp_addr;
7387 pri2cos = &resp2->pri0_cos_queue_id;
7388 for (i = 0; i < 8; i++) {
7389 u8 queue_id = pri2cos[i];
7390 u8 queue_idx;
7391
7392
7393 queue_idx = queue_id % 10;
7394 if (queue_idx > BNXT_MAX_QUEUE) {
7395 bp->pri2cos_valid = false;
7396 goto qstats_done;
7397 }
7398 for (j = 0; j < bp->max_q; j++) {
7399 if (bp->q_ids[j] == queue_id)
7400 bp->pri2cos_idx[i] = queue_idx;
7401 }
7402 }
7403 bp->pri2cos_valid = 1;
7404 }
7405 qstats_done:
7406 mutex_unlock(&bp->hwrm_cmd_lock);
7407 return rc;
7408 }
7409
7410 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp)
7411 {
7412 struct hwrm_pcie_qstats_input req = {0};
7413
7414 if (!(bp->flags & BNXT_FLAG_PCIE_STATS))
7415 return 0;
7416
7417 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1);
7418 req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats));
7419 req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map);
7420 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7421 }
7422
7423 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
7424 {
7425 if (bp->vxlan_port_cnt) {
7426 bnxt_hwrm_tunnel_dst_port_free(
7427 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7428 }
7429 bp->vxlan_port_cnt = 0;
7430 if (bp->nge_port_cnt) {
7431 bnxt_hwrm_tunnel_dst_port_free(
7432 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7433 }
7434 bp->nge_port_cnt = 0;
7435 }
7436
7437 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
7438 {
7439 int rc, i;
7440 u32 tpa_flags = 0;
7441
7442 if (set_tpa)
7443 tpa_flags = bp->flags & BNXT_FLAG_TPA;
7444 else if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
7445 return 0;
7446 for (i = 0; i < bp->nr_vnics; i++) {
7447 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
7448 if (rc) {
7449 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
7450 i, rc);
7451 return rc;
7452 }
7453 }
7454 return 0;
7455 }
7456
7457 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
7458 {
7459 int i;
7460
7461 for (i = 0; i < bp->nr_vnics; i++)
7462 bnxt_hwrm_vnic_set_rss(bp, i, false);
7463 }
7464
7465 static void bnxt_clear_vnic(struct bnxt *bp)
7466 {
7467 if (!bp->vnic_info)
7468 return;
7469
7470 bnxt_hwrm_clear_vnic_filter(bp);
7471 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) {
7472
7473 bnxt_hwrm_clear_vnic_rss(bp);
7474 bnxt_hwrm_vnic_ctx_free(bp);
7475 }
7476
7477 if (bp->flags & BNXT_FLAG_TPA)
7478 bnxt_set_tpa(bp, false);
7479 bnxt_hwrm_vnic_free(bp);
7480 if (bp->flags & BNXT_FLAG_CHIP_P5)
7481 bnxt_hwrm_vnic_ctx_free(bp);
7482 }
7483
7484 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
7485 bool irq_re_init)
7486 {
7487 bnxt_clear_vnic(bp);
7488 bnxt_hwrm_ring_free(bp, close_path);
7489 bnxt_hwrm_ring_grp_free(bp);
7490 if (irq_re_init) {
7491 bnxt_hwrm_stat_ctx_free(bp);
7492 bnxt_hwrm_free_tunnel_ports(bp);
7493 }
7494 }
7495
7496 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
7497 {
7498 struct hwrm_func_cfg_input req = {0};
7499 int rc;
7500
7501 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
7502 req.fid = cpu_to_le16(0xffff);
7503 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
7504 if (br_mode == BRIDGE_MODE_VEB)
7505 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
7506 else if (br_mode == BRIDGE_MODE_VEPA)
7507 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
7508 else
7509 return -EINVAL;
7510 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7511 return rc;
7512 }
7513
7514 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
7515 {
7516 struct hwrm_func_cfg_input req = {0};
7517 int rc;
7518
7519 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
7520 return 0;
7521
7522 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
7523 req.fid = cpu_to_le16(0xffff);
7524 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
7525 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
7526 if (size == 128)
7527 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
7528
7529 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7530 return rc;
7531 }
7532
7533 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7534 {
7535 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
7536 int rc;
7537
7538 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
7539 goto skip_rss_ctx;
7540
7541
7542 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
7543 if (rc) {
7544 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7545 vnic_id, rc);
7546 goto vnic_setup_err;
7547 }
7548 bp->rsscos_nr_ctxs++;
7549
7550 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7551 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
7552 if (rc) {
7553 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
7554 vnic_id, rc);
7555 goto vnic_setup_err;
7556 }
7557 bp->rsscos_nr_ctxs++;
7558 }
7559
7560 skip_rss_ctx:
7561
7562 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7563 if (rc) {
7564 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7565 vnic_id, rc);
7566 goto vnic_setup_err;
7567 }
7568
7569
7570 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
7571 if (rc) {
7572 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
7573 vnic_id, rc);
7574 goto vnic_setup_err;
7575 }
7576
7577 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7578 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7579 if (rc) {
7580 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7581 vnic_id, rc);
7582 }
7583 }
7584
7585 vnic_setup_err:
7586 return rc;
7587 }
7588
7589 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
7590 {
7591 int rc, i, nr_ctxs;
7592
7593 nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
7594 for (i = 0; i < nr_ctxs; i++) {
7595 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
7596 if (rc) {
7597 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
7598 vnic_id, i, rc);
7599 break;
7600 }
7601 bp->rsscos_nr_ctxs++;
7602 }
7603 if (i < nr_ctxs)
7604 return -ENOMEM;
7605
7606 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
7607 if (rc) {
7608 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
7609 vnic_id, rc);
7610 return rc;
7611 }
7612 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7613 if (rc) {
7614 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7615 vnic_id, rc);
7616 return rc;
7617 }
7618 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7619 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7620 if (rc) {
7621 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7622 vnic_id, rc);
7623 }
7624 }
7625 return rc;
7626 }
7627
7628 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7629 {
7630 if (bp->flags & BNXT_FLAG_CHIP_P5)
7631 return __bnxt_setup_vnic_p5(bp, vnic_id);
7632 else
7633 return __bnxt_setup_vnic(bp, vnic_id);
7634 }
7635
7636 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
7637 {
7638 #ifdef CONFIG_RFS_ACCEL
7639 int i, rc = 0;
7640
7641 if (bp->flags & BNXT_FLAG_CHIP_P5)
7642 return 0;
7643
7644 for (i = 0; i < bp->rx_nr_rings; i++) {
7645 struct bnxt_vnic_info *vnic;
7646 u16 vnic_id = i + 1;
7647 u16 ring_id = i;
7648
7649 if (vnic_id >= bp->nr_vnics)
7650 break;
7651
7652 vnic = &bp->vnic_info[vnic_id];
7653 vnic->flags |= BNXT_VNIC_RFS_FLAG;
7654 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7655 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
7656 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
7657 if (rc) {
7658 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7659 vnic_id, rc);
7660 break;
7661 }
7662 rc = bnxt_setup_vnic(bp, vnic_id);
7663 if (rc)
7664 break;
7665 }
7666 return rc;
7667 #else
7668 return 0;
7669 #endif
7670 }
7671
7672
7673 static bool bnxt_promisc_ok(struct bnxt *bp)
7674 {
7675 #ifdef CONFIG_BNXT_SRIOV
7676 if (BNXT_VF(bp) && !bp->vf.vlan)
7677 return false;
7678 #endif
7679 return true;
7680 }
7681
7682 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
7683 {
7684 unsigned int rc = 0;
7685
7686 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
7687 if (rc) {
7688 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7689 rc);
7690 return rc;
7691 }
7692
7693 rc = bnxt_hwrm_vnic_cfg(bp, 1);
7694 if (rc) {
7695 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7696 rc);
7697 return rc;
7698 }
7699 return rc;
7700 }
7701
7702 static int bnxt_cfg_rx_mode(struct bnxt *);
7703 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
7704
7705 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
7706 {
7707 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7708 int rc = 0;
7709 unsigned int rx_nr_rings = bp->rx_nr_rings;
7710
7711 if (irq_re_init) {
7712 rc = bnxt_hwrm_stat_ctx_alloc(bp);
7713 if (rc) {
7714 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
7715 rc);
7716 goto err_out;
7717 }
7718 }
7719
7720 rc = bnxt_hwrm_ring_alloc(bp);
7721 if (rc) {
7722 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
7723 goto err_out;
7724 }
7725
7726 rc = bnxt_hwrm_ring_grp_alloc(bp);
7727 if (rc) {
7728 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
7729 goto err_out;
7730 }
7731
7732 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7733 rx_nr_rings--;
7734
7735
7736 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
7737 if (rc) {
7738 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
7739 goto err_out;
7740 }
7741
7742 rc = bnxt_setup_vnic(bp, 0);
7743 if (rc)
7744 goto err_out;
7745
7746 if (bp->flags & BNXT_FLAG_RFS) {
7747 rc = bnxt_alloc_rfs_vnics(bp);
7748 if (rc)
7749 goto err_out;
7750 }
7751
7752 if (bp->flags & BNXT_FLAG_TPA) {
7753 rc = bnxt_set_tpa(bp, true);
7754 if (rc)
7755 goto err_out;
7756 }
7757
7758 if (BNXT_VF(bp))
7759 bnxt_update_vf_mac(bp);
7760
7761
7762 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
7763 if (rc) {
7764 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
7765 goto err_out;
7766 }
7767 vnic->uc_filter_count = 1;
7768
7769 vnic->rx_mask = 0;
7770 if (bp->dev->flags & IFF_BROADCAST)
7771 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7772
7773 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7774 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7775
7776 if (bp->dev->flags & IFF_ALLMULTI) {
7777 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7778 vnic->mc_list_count = 0;
7779 } else {
7780 u32 mask = 0;
7781
7782 bnxt_mc_list_updated(bp, &mask);
7783 vnic->rx_mask |= mask;
7784 }
7785
7786 rc = bnxt_cfg_rx_mode(bp);
7787 if (rc)
7788 goto err_out;
7789
7790 rc = bnxt_hwrm_set_coal(bp);
7791 if (rc)
7792 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
7793 rc);
7794
7795 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7796 rc = bnxt_setup_nitroa0_vnic(bp);
7797 if (rc)
7798 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
7799 rc);
7800 }
7801
7802 if (BNXT_VF(bp)) {
7803 bnxt_hwrm_func_qcfg(bp);
7804 netdev_update_features(bp->dev);
7805 }
7806
7807 return 0;
7808
7809 err_out:
7810 bnxt_hwrm_resource_free(bp, 0, true);
7811
7812 return rc;
7813 }
7814
7815 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
7816 {
7817 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
7818 return 0;
7819 }
7820
7821 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
7822 {
7823 bnxt_init_cp_rings(bp);
7824 bnxt_init_rx_rings(bp);
7825 bnxt_init_tx_rings(bp);
7826 bnxt_init_ring_grps(bp, irq_re_init);
7827 bnxt_init_vnics(bp);
7828
7829 return bnxt_init_chip(bp, irq_re_init);
7830 }
7831
7832 static int bnxt_set_real_num_queues(struct bnxt *bp)
7833 {
7834 int rc;
7835 struct net_device *dev = bp->dev;
7836
7837 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
7838 bp->tx_nr_rings_xdp);
7839 if (rc)
7840 return rc;
7841
7842 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
7843 if (rc)
7844 return rc;
7845
7846 #ifdef CONFIG_RFS_ACCEL
7847 if (bp->flags & BNXT_FLAG_RFS)
7848 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
7849 #endif
7850
7851 return rc;
7852 }
7853
7854 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
7855 bool shared)
7856 {
7857 int _rx = *rx, _tx = *tx;
7858
7859 if (shared) {
7860 *rx = min_t(int, _rx, max);
7861 *tx = min_t(int, _tx, max);
7862 } else {
7863 if (max < 2)
7864 return -ENOMEM;
7865
7866 while (_rx + _tx > max) {
7867 if (_rx > _tx && _rx > 1)
7868 _rx--;
7869 else if (_tx > 1)
7870 _tx--;
7871 }
7872 *rx = _rx;
7873 *tx = _tx;
7874 }
7875 return 0;
7876 }
7877
7878 static void bnxt_setup_msix(struct bnxt *bp)
7879 {
7880 const int len = sizeof(bp->irq_tbl[0].name);
7881 struct net_device *dev = bp->dev;
7882 int tcs, i;
7883
7884 tcs = netdev_get_num_tc(dev);
7885 if (tcs) {
7886 int i, off, count;
7887
7888 for (i = 0; i < tcs; i++) {
7889 count = bp->tx_nr_rings_per_tc;
7890 off = i * count;
7891 netdev_set_tc_queue(dev, i, count, off);
7892 }
7893 }
7894
7895 for (i = 0; i < bp->cp_nr_rings; i++) {
7896 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7897 char *attr;
7898
7899 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7900 attr = "TxRx";
7901 else if (i < bp->rx_nr_rings)
7902 attr = "rx";
7903 else
7904 attr = "tx";
7905
7906 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
7907 attr, i);
7908 bp->irq_tbl[map_idx].handler = bnxt_msix;
7909 }
7910 }
7911
7912 static void bnxt_setup_inta(struct bnxt *bp)
7913 {
7914 const int len = sizeof(bp->irq_tbl[0].name);
7915
7916 if (netdev_get_num_tc(bp->dev))
7917 netdev_reset_tc(bp->dev);
7918
7919 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
7920 0);
7921 bp->irq_tbl[0].handler = bnxt_inta;
7922 }
7923
7924 static int bnxt_setup_int_mode(struct bnxt *bp)
7925 {
7926 int rc;
7927
7928 if (bp->flags & BNXT_FLAG_USING_MSIX)
7929 bnxt_setup_msix(bp);
7930 else
7931 bnxt_setup_inta(bp);
7932
7933 rc = bnxt_set_real_num_queues(bp);
7934 return rc;
7935 }
7936
7937 #ifdef CONFIG_RFS_ACCEL
7938 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
7939 {
7940 return bp->hw_resc.max_rsscos_ctxs;
7941 }
7942
7943 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
7944 {
7945 return bp->hw_resc.max_vnics;
7946 }
7947 #endif
7948
7949 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
7950 {
7951 return bp->hw_resc.max_stat_ctxs;
7952 }
7953
7954 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
7955 {
7956 return bp->hw_resc.max_cp_rings;
7957 }
7958
7959 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
7960 {
7961 unsigned int cp = bp->hw_resc.max_cp_rings;
7962
7963 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7964 cp -= bnxt_get_ulp_msix_num(bp);
7965
7966 return cp;
7967 }
7968
7969 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
7970 {
7971 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7972
7973 if (bp->flags & BNXT_FLAG_CHIP_P5)
7974 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
7975
7976 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7977 }
7978
7979 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
7980 {
7981 bp->hw_resc.max_irqs = max_irqs;
7982 }
7983
7984 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
7985 {
7986 unsigned int cp;
7987
7988 cp = bnxt_get_max_func_cp_rings_for_en(bp);
7989 if (bp->flags & BNXT_FLAG_CHIP_P5)
7990 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
7991 else
7992 return cp - bp->cp_nr_rings;
7993 }
7994
7995 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
7996 {
7997 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
7998 }
7999
8000 int bnxt_get_avail_msix(struct bnxt *bp, int num)
8001 {
8002 int max_cp = bnxt_get_max_func_cp_rings(bp);
8003 int max_irq = bnxt_get_max_func_irqs(bp);
8004 int total_req = bp->cp_nr_rings + num;
8005 int max_idx, avail_msix;
8006
8007 max_idx = bp->total_irqs;
8008 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
8009 max_idx = min_t(int, bp->total_irqs, max_cp);
8010 avail_msix = max_idx - bp->cp_nr_rings;
8011 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
8012 return avail_msix;
8013
8014 if (max_irq < total_req) {
8015 num = max_irq - bp->cp_nr_rings;
8016 if (num <= 0)
8017 return 0;
8018 }
8019 return num;
8020 }
8021
8022 static int bnxt_get_num_msix(struct bnxt *bp)
8023 {
8024 if (!BNXT_NEW_RM(bp))
8025 return bnxt_get_max_func_irqs(bp);
8026
8027 return bnxt_nq_rings_in_use(bp);
8028 }
8029
8030 static int bnxt_init_msix(struct bnxt *bp)
8031 {
8032 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
8033 struct msix_entry *msix_ent;
8034
8035 total_vecs = bnxt_get_num_msix(bp);
8036 max = bnxt_get_max_func_irqs(bp);
8037 if (total_vecs > max)
8038 total_vecs = max;
8039
8040 if (!total_vecs)
8041 return 0;
8042
8043 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
8044 if (!msix_ent)
8045 return -ENOMEM;
8046
8047 for (i = 0; i < total_vecs; i++) {
8048 msix_ent[i].entry = i;
8049 msix_ent[i].vector = 0;
8050 }
8051
8052 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
8053 min = 2;
8054
8055 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
8056 ulp_msix = bnxt_get_ulp_msix_num(bp);
8057 if (total_vecs < 0 || total_vecs < ulp_msix) {
8058 rc = -ENODEV;
8059 goto msix_setup_exit;
8060 }
8061
8062 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
8063 if (bp->irq_tbl) {
8064 for (i = 0; i < total_vecs; i++)
8065 bp->irq_tbl[i].vector = msix_ent[i].vector;
8066
8067 bp->total_irqs = total_vecs;
8068
8069 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
8070 total_vecs - ulp_msix, min == 1);
8071 if (rc)
8072 goto msix_setup_exit;
8073
8074 bp->cp_nr_rings = (min == 1) ?
8075 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
8076 bp->tx_nr_rings + bp->rx_nr_rings;
8077
8078 } else {
8079 rc = -ENOMEM;
8080 goto msix_setup_exit;
8081 }
8082 bp->flags |= BNXT_FLAG_USING_MSIX;
8083 kfree(msix_ent);
8084 return 0;
8085
8086 msix_setup_exit:
8087 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
8088 kfree(bp->irq_tbl);
8089 bp->irq_tbl = NULL;
8090 pci_disable_msix(bp->pdev);
8091 kfree(msix_ent);
8092 return rc;
8093 }
8094
8095 static int bnxt_init_inta(struct bnxt *bp)
8096 {
8097 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
8098 if (!bp->irq_tbl)
8099 return -ENOMEM;
8100
8101 bp->total_irqs = 1;
8102 bp->rx_nr_rings = 1;
8103 bp->tx_nr_rings = 1;
8104 bp->cp_nr_rings = 1;
8105 bp->flags |= BNXT_FLAG_SHARED_RINGS;
8106 bp->irq_tbl[0].vector = bp->pdev->irq;
8107 return 0;
8108 }
8109
8110 static int bnxt_init_int_mode(struct bnxt *bp)
8111 {
8112 int rc = 0;
8113
8114 if (bp->flags & BNXT_FLAG_MSIX_CAP)
8115 rc = bnxt_init_msix(bp);
8116
8117 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
8118
8119 rc = bnxt_init_inta(bp);
8120 }
8121 return rc;
8122 }
8123
8124 static void bnxt_clear_int_mode(struct bnxt *bp)
8125 {
8126 if (bp->flags & BNXT_FLAG_USING_MSIX)
8127 pci_disable_msix(bp->pdev);
8128
8129 kfree(bp->irq_tbl);
8130 bp->irq_tbl = NULL;
8131 bp->flags &= ~BNXT_FLAG_USING_MSIX;
8132 }
8133
8134 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
8135 {
8136 int tcs = netdev_get_num_tc(bp->dev);
8137 bool irq_cleared = false;
8138 int rc;
8139
8140 if (!bnxt_need_reserve_rings(bp))
8141 return 0;
8142
8143 if (irq_re_init && BNXT_NEW_RM(bp) &&
8144 bnxt_get_num_msix(bp) != bp->total_irqs) {
8145 bnxt_ulp_irq_stop(bp);
8146 bnxt_clear_int_mode(bp);
8147 irq_cleared = true;
8148 }
8149 rc = __bnxt_reserve_rings(bp);
8150 if (irq_cleared) {
8151 if (!rc)
8152 rc = bnxt_init_int_mode(bp);
8153 bnxt_ulp_irq_restart(bp, rc);
8154 }
8155 if (rc) {
8156 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
8157 return rc;
8158 }
8159 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
8160 netdev_err(bp->dev, "tx ring reservation failure\n");
8161 netdev_reset_tc(bp->dev);
8162 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8163 return -ENOMEM;
8164 }
8165 return 0;
8166 }
8167
8168 static void bnxt_free_irq(struct bnxt *bp)
8169 {
8170 struct bnxt_irq *irq;
8171 int i;
8172
8173 #ifdef CONFIG_RFS_ACCEL
8174 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
8175 bp->dev->rx_cpu_rmap = NULL;
8176 #endif
8177 if (!bp->irq_tbl || !bp->bnapi)
8178 return;
8179
8180 for (i = 0; i < bp->cp_nr_rings; i++) {
8181 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
8182
8183 irq = &bp->irq_tbl[map_idx];
8184 if (irq->requested) {
8185 if (irq->have_cpumask) {
8186 irq_set_affinity_hint(irq->vector, NULL);
8187 free_cpumask_var(irq->cpu_mask);
8188 irq->have_cpumask = 0;
8189 }
8190 free_irq(irq->vector, bp->bnapi[i]);
8191 }
8192
8193 irq->requested = 0;
8194 }
8195 }
8196
8197 static int bnxt_request_irq(struct bnxt *bp)
8198 {
8199 int i, j, rc = 0;
8200 unsigned long flags = 0;
8201 #ifdef CONFIG_RFS_ACCEL
8202 struct cpu_rmap *rmap;
8203 #endif
8204
8205 rc = bnxt_setup_int_mode(bp);
8206 if (rc) {
8207 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
8208 rc);
8209 return rc;
8210 }
8211 #ifdef CONFIG_RFS_ACCEL
8212 rmap = bp->dev->rx_cpu_rmap;
8213 #endif
8214 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
8215 flags = IRQF_SHARED;
8216
8217 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
8218 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
8219 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
8220
8221 #ifdef CONFIG_RFS_ACCEL
8222 if (rmap && bp->bnapi[i]->rx_ring) {
8223 rc = irq_cpu_rmap_add(rmap, irq->vector);
8224 if (rc)
8225 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
8226 j);
8227 j++;
8228 }
8229 #endif
8230 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
8231 bp->bnapi[i]);
8232 if (rc)
8233 break;
8234
8235 irq->requested = 1;
8236
8237 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
8238 int numa_node = dev_to_node(&bp->pdev->dev);
8239
8240 irq->have_cpumask = 1;
8241 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
8242 irq->cpu_mask);
8243 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
8244 if (rc) {
8245 netdev_warn(bp->dev,
8246 "Set affinity failed, IRQ = %d\n",
8247 irq->vector);
8248 break;
8249 }
8250 }
8251 }
8252 return rc;
8253 }
8254
8255 static void bnxt_del_napi(struct bnxt *bp)
8256 {
8257 int i;
8258
8259 if (!bp->bnapi)
8260 return;
8261
8262 for (i = 0; i < bp->cp_nr_rings; i++) {
8263 struct bnxt_napi *bnapi = bp->bnapi[i];
8264
8265 napi_hash_del(&bnapi->napi);
8266 netif_napi_del(&bnapi->napi);
8267 }
8268
8269
8270
8271 synchronize_net();
8272 }
8273
8274 static void bnxt_init_napi(struct bnxt *bp)
8275 {
8276 int i;
8277 unsigned int cp_nr_rings = bp->cp_nr_rings;
8278 struct bnxt_napi *bnapi;
8279
8280 if (bp->flags & BNXT_FLAG_USING_MSIX) {
8281 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
8282
8283 if (bp->flags & BNXT_FLAG_CHIP_P5)
8284 poll_fn = bnxt_poll_p5;
8285 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
8286 cp_nr_rings--;
8287 for (i = 0; i < cp_nr_rings; i++) {
8288 bnapi = bp->bnapi[i];
8289 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
8290 }
8291 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8292 bnapi = bp->bnapi[cp_nr_rings];
8293 netif_napi_add(bp->dev, &bnapi->napi,
8294 bnxt_poll_nitroa0, 64);
8295 }
8296 } else {
8297 bnapi = bp->bnapi[0];
8298 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
8299 }
8300 }
8301
8302 static void bnxt_disable_napi(struct bnxt *bp)
8303 {
8304 int i;
8305
8306 if (!bp->bnapi)
8307 return;
8308
8309 for (i = 0; i < bp->cp_nr_rings; i++) {
8310 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
8311
8312 if (bp->bnapi[i]->rx_ring)
8313 cancel_work_sync(&cpr->dim.work);
8314
8315 napi_disable(&bp->bnapi[i]->napi);
8316 }
8317 }
8318
8319 static void bnxt_enable_napi(struct bnxt *bp)
8320 {
8321 int i;
8322
8323 for (i = 0; i < bp->cp_nr_rings; i++) {
8324 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
8325 bp->bnapi[i]->in_reset = false;
8326
8327 if (bp->bnapi[i]->rx_ring) {
8328 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
8329 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
8330 }
8331 napi_enable(&bp->bnapi[i]->napi);
8332 }
8333 }
8334
8335 void bnxt_tx_disable(struct bnxt *bp)
8336 {
8337 int i;
8338 struct bnxt_tx_ring_info *txr;
8339
8340 if (bp->tx_ring) {
8341 for (i = 0; i < bp->tx_nr_rings; i++) {
8342 txr = &bp->tx_ring[i];
8343 txr->dev_state = BNXT_DEV_STATE_CLOSING;
8344 }
8345 }
8346
8347 netif_tx_disable(bp->dev);
8348 netif_carrier_off(bp->dev);
8349 }
8350
8351 void bnxt_tx_enable(struct bnxt *bp)
8352 {
8353 int i;
8354 struct bnxt_tx_ring_info *txr;
8355
8356 for (i = 0; i < bp->tx_nr_rings; i++) {
8357 txr = &bp->tx_ring[i];
8358 txr->dev_state = 0;
8359 }
8360 netif_tx_wake_all_queues(bp->dev);
8361 if (bp->link_info.link_up)
8362 netif_carrier_on(bp->dev);
8363 }
8364
8365 static void bnxt_report_link(struct bnxt *bp)
8366 {
8367 if (bp->link_info.link_up) {
8368 const char *duplex;
8369 const char *flow_ctrl;
8370 u32 speed;
8371 u16 fec;
8372
8373 netif_carrier_on(bp->dev);
8374 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
8375 duplex = "full";
8376 else
8377 duplex = "half";
8378 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
8379 flow_ctrl = "ON - receive & transmit";
8380 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
8381 flow_ctrl = "ON - transmit";
8382 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
8383 flow_ctrl = "ON - receive";
8384 else
8385 flow_ctrl = "none";
8386 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
8387 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
8388 speed, duplex, flow_ctrl);
8389 if (bp->flags & BNXT_FLAG_EEE_CAP)
8390 netdev_info(bp->dev, "EEE is %s\n",
8391 bp->eee.eee_active ? "active" :
8392 "not active");
8393 fec = bp->link_info.fec_cfg;
8394 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
8395 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
8396 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
8397 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
8398 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
8399 } else {
8400 netif_carrier_off(bp->dev);
8401 netdev_err(bp->dev, "NIC Link is Down\n");
8402 }
8403 }
8404
8405 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
8406 {
8407 int rc = 0;
8408 struct hwrm_port_phy_qcaps_input req = {0};
8409 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8410 struct bnxt_link_info *link_info = &bp->link_info;
8411
8412 bp->flags &= ~BNXT_FLAG_EEE_CAP;
8413 if (bp->test_info)
8414 bp->test_info->flags &= ~BNXT_TEST_FL_EXT_LPBK;
8415 if (bp->hwrm_spec_code < 0x10201)
8416 return 0;
8417
8418 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
8419
8420 mutex_lock(&bp->hwrm_cmd_lock);
8421 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8422 if (rc)
8423 goto hwrm_phy_qcaps_exit;
8424
8425 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
8426 struct ethtool_eee *eee = &bp->eee;
8427 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
8428
8429 bp->flags |= BNXT_FLAG_EEE_CAP;
8430 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8431 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
8432 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
8433 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
8434 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
8435 }
8436 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
8437 if (bp->test_info)
8438 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
8439 }
8440 if (resp->supported_speeds_auto_mode)
8441 link_info->support_auto_speeds =
8442 le16_to_cpu(resp->supported_speeds_auto_mode);
8443
8444 bp->port_count = resp->port_cnt;
8445
8446 hwrm_phy_qcaps_exit:
8447 mutex_unlock(&bp->hwrm_cmd_lock);
8448 return rc;
8449 }
8450
8451 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
8452 {
8453 int rc = 0;
8454 struct bnxt_link_info *link_info = &bp->link_info;
8455 struct hwrm_port_phy_qcfg_input req = {0};
8456 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8457 u8 link_up = link_info->link_up;
8458 u16 diff;
8459
8460 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
8461
8462 mutex_lock(&bp->hwrm_cmd_lock);
8463 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8464 if (rc) {
8465 mutex_unlock(&bp->hwrm_cmd_lock);
8466 return rc;
8467 }
8468
8469 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
8470 link_info->phy_link_status = resp->link;
8471 link_info->duplex = resp->duplex_cfg;
8472 if (bp->hwrm_spec_code >= 0x10800)
8473 link_info->duplex = resp->duplex_state;
8474 link_info->pause = resp->pause;
8475 link_info->auto_mode = resp->auto_mode;
8476 link_info->auto_pause_setting = resp->auto_pause;
8477 link_info->lp_pause = resp->link_partner_adv_pause;
8478 link_info->force_pause_setting = resp->force_pause;
8479 link_info->duplex_setting = resp->duplex_cfg;
8480 if (link_info->phy_link_status == BNXT_LINK_LINK)
8481 link_info->link_speed = le16_to_cpu(resp->link_speed);
8482 else
8483 link_info->link_speed = 0;
8484 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
8485 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
8486 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
8487 link_info->lp_auto_link_speeds =
8488 le16_to_cpu(resp->link_partner_adv_speeds);
8489 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
8490 link_info->phy_ver[0] = resp->phy_maj;
8491 link_info->phy_ver[1] = resp->phy_min;
8492 link_info->phy_ver[2] = resp->phy_bld;
8493 link_info->media_type = resp->media_type;
8494 link_info->phy_type = resp->phy_type;
8495 link_info->transceiver = resp->xcvr_pkg_type;
8496 link_info->phy_addr = resp->eee_config_phy_addr &
8497 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
8498 link_info->module_status = resp->module_status;
8499
8500 if (bp->flags & BNXT_FLAG_EEE_CAP) {
8501 struct ethtool_eee *eee = &bp->eee;
8502 u16 fw_speeds;
8503
8504 eee->eee_active = 0;
8505 if (resp->eee_config_phy_addr &
8506 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
8507 eee->eee_active = 1;
8508 fw_speeds = le16_to_cpu(
8509 resp->link_partner_adv_eee_link_speed_mask);
8510 eee->lp_advertised =
8511 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8512 }
8513
8514
8515 if (!chng_link_state) {
8516 if (resp->eee_config_phy_addr &
8517 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
8518 eee->eee_enabled = 1;
8519
8520 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
8521 eee->advertised =
8522 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8523
8524 if (resp->eee_config_phy_addr &
8525 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
8526 __le32 tmr;
8527
8528 eee->tx_lpi_enabled = 1;
8529 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
8530 eee->tx_lpi_timer = le32_to_cpu(tmr) &
8531 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
8532 }
8533 }
8534 }
8535
8536 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
8537 if (bp->hwrm_spec_code >= 0x10504)
8538 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
8539
8540
8541 if (chng_link_state) {
8542 if (link_info->phy_link_status == BNXT_LINK_LINK)
8543 link_info->link_up = 1;
8544 else
8545 link_info->link_up = 0;
8546 if (link_up != link_info->link_up)
8547 bnxt_report_link(bp);
8548 } else {
8549
8550 link_info->link_up = 0;
8551 }
8552 mutex_unlock(&bp->hwrm_cmd_lock);
8553
8554 if (!BNXT_SINGLE_PF(bp))
8555 return 0;
8556
8557 diff = link_info->support_auto_speeds ^ link_info->advertising;
8558 if ((link_info->support_auto_speeds | diff) !=
8559 link_info->support_auto_speeds) {
8560
8561
8562
8563
8564 link_info->advertising = link_info->support_auto_speeds;
8565 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
8566 bnxt_hwrm_set_link_setting(bp, true, false);
8567 }
8568 return 0;
8569 }
8570
8571 static void bnxt_get_port_module_status(struct bnxt *bp)
8572 {
8573 struct bnxt_link_info *link_info = &bp->link_info;
8574 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
8575 u8 module_status;
8576
8577 if (bnxt_update_link(bp, true))
8578 return;
8579
8580 module_status = link_info->module_status;
8581 switch (module_status) {
8582 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
8583 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
8584 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
8585 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
8586 bp->pf.port_id);
8587 if (bp->hwrm_spec_code >= 0x10201) {
8588 netdev_warn(bp->dev, "Module part number %s\n",
8589 resp->phy_vendor_partnumber);
8590 }
8591 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
8592 netdev_warn(bp->dev, "TX is disabled\n");
8593 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
8594 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
8595 }
8596 }
8597
8598 static void
8599 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
8600 {
8601 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
8602 if (bp->hwrm_spec_code >= 0x10201)
8603 req->auto_pause =
8604 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
8605 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8606 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
8607 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8608 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
8609 req->enables |=
8610 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8611 } else {
8612 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8613 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
8614 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8615 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
8616 req->enables |=
8617 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
8618 if (bp->hwrm_spec_code >= 0x10201) {
8619 req->auto_pause = req->force_pause;
8620 req->enables |= cpu_to_le32(
8621 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8622 }
8623 }
8624 }
8625
8626 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
8627 struct hwrm_port_phy_cfg_input *req)
8628 {
8629 u8 autoneg = bp->link_info.autoneg;
8630 u16 fw_link_speed = bp->link_info.req_link_speed;
8631 u16 advertising = bp->link_info.advertising;
8632
8633 if (autoneg & BNXT_AUTONEG_SPEED) {
8634 req->auto_mode |=
8635 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
8636
8637 req->enables |= cpu_to_le32(
8638 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
8639 req->auto_link_speed_mask = cpu_to_le16(advertising);
8640
8641 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
8642 req->flags |=
8643 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
8644 } else {
8645 req->force_link_speed = cpu_to_le16(fw_link_speed);
8646 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
8647 }
8648
8649
8650 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
8651 }
8652
8653 int bnxt_hwrm_set_pause(struct bnxt *bp)
8654 {
8655 struct hwrm_port_phy_cfg_input req = {0};
8656 int rc;
8657
8658 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8659 bnxt_hwrm_set_pause_common(bp, &req);
8660
8661 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
8662 bp->link_info.force_link_chng)
8663 bnxt_hwrm_set_link_common(bp, &req);
8664
8665 mutex_lock(&bp->hwrm_cmd_lock);
8666 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8667 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
8668
8669
8670
8671
8672 bp->link_info.pause =
8673 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
8674 bp->link_info.auto_pause_setting = 0;
8675 if (!bp->link_info.force_link_chng)
8676 bnxt_report_link(bp);
8677 }
8678 bp->link_info.force_link_chng = false;
8679 mutex_unlock(&bp->hwrm_cmd_lock);
8680 return rc;
8681 }
8682
8683 static void bnxt_hwrm_set_eee(struct bnxt *bp,
8684 struct hwrm_port_phy_cfg_input *req)
8685 {
8686 struct ethtool_eee *eee = &bp->eee;
8687
8688 if (eee->eee_enabled) {
8689 u16 eee_speeds;
8690 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
8691
8692 if (eee->tx_lpi_enabled)
8693 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
8694 else
8695 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
8696
8697 req->flags |= cpu_to_le32(flags);
8698 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
8699 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
8700 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
8701 } else {
8702 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
8703 }
8704 }
8705
8706 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
8707 {
8708 struct hwrm_port_phy_cfg_input req = {0};
8709
8710 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8711 if (set_pause)
8712 bnxt_hwrm_set_pause_common(bp, &req);
8713
8714 bnxt_hwrm_set_link_common(bp, &req);
8715
8716 if (set_eee)
8717 bnxt_hwrm_set_eee(bp, &req);
8718 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8719 }
8720
8721 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
8722 {
8723 struct hwrm_port_phy_cfg_input req = {0};
8724
8725 if (!BNXT_SINGLE_PF(bp))
8726 return 0;
8727
8728 if (pci_num_vf(bp->pdev))
8729 return 0;
8730
8731 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8732 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
8733 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8734 }
8735
8736 static int bnxt_fw_init_one(struct bnxt *bp);
8737
8738 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
8739 {
8740 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
8741 struct hwrm_func_drv_if_change_input req = {0};
8742 bool resc_reinit = false, fw_reset = false;
8743 u32 flags = 0;
8744 int rc;
8745
8746 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
8747 return 0;
8748
8749 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
8750 if (up)
8751 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
8752 mutex_lock(&bp->hwrm_cmd_lock);
8753 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8754 if (!rc)
8755 flags = le32_to_cpu(resp->flags);
8756 mutex_unlock(&bp->hwrm_cmd_lock);
8757 if (rc)
8758 return rc;
8759
8760 if (!up)
8761 return 0;
8762
8763 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)
8764 resc_reinit = true;
8765 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE)
8766 fw_reset = true;
8767
8768 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) {
8769 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n");
8770 return -ENODEV;
8771 }
8772 if (resc_reinit || fw_reset) {
8773 if (fw_reset) {
8774 bnxt_free_ctx_mem(bp);
8775 kfree(bp->ctx);
8776 bp->ctx = NULL;
8777 rc = bnxt_fw_init_one(bp);
8778 if (rc) {
8779 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
8780 return rc;
8781 }
8782 bnxt_clear_int_mode(bp);
8783 rc = bnxt_init_int_mode(bp);
8784 if (rc) {
8785 netdev_err(bp->dev, "init int mode failed\n");
8786 return rc;
8787 }
8788 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
8789 }
8790 if (BNXT_NEW_RM(bp)) {
8791 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8792
8793 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
8794 hw_resc->resv_cp_rings = 0;
8795 hw_resc->resv_stat_ctxs = 0;
8796 hw_resc->resv_irqs = 0;
8797 hw_resc->resv_tx_rings = 0;
8798 hw_resc->resv_rx_rings = 0;
8799 hw_resc->resv_hw_ring_grps = 0;
8800 hw_resc->resv_vnics = 0;
8801 if (!fw_reset) {
8802 bp->tx_nr_rings = 0;
8803 bp->rx_nr_rings = 0;
8804 }
8805 }
8806 }
8807 return 0;
8808 }
8809
8810 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
8811 {
8812 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8813 struct hwrm_port_led_qcaps_input req = {0};
8814 struct bnxt_pf_info *pf = &bp->pf;
8815 int rc;
8816
8817 bp->num_leds = 0;
8818 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
8819 return 0;
8820
8821 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
8822 req.port_id = cpu_to_le16(pf->port_id);
8823 mutex_lock(&bp->hwrm_cmd_lock);
8824 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8825 if (rc) {
8826 mutex_unlock(&bp->hwrm_cmd_lock);
8827 return rc;
8828 }
8829 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
8830 int i;
8831
8832 bp->num_leds = resp->num_leds;
8833 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
8834 bp->num_leds);
8835 for (i = 0; i < bp->num_leds; i++) {
8836 struct bnxt_led_info *led = &bp->leds[i];
8837 __le16 caps = led->led_state_caps;
8838
8839 if (!led->led_group_id ||
8840 !BNXT_LED_ALT_BLINK_CAP(caps)) {
8841 bp->num_leds = 0;
8842 break;
8843 }
8844 }
8845 }
8846 mutex_unlock(&bp->hwrm_cmd_lock);
8847 return 0;
8848 }
8849
8850 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
8851 {
8852 struct hwrm_wol_filter_alloc_input req = {0};
8853 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
8854 int rc;
8855
8856 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
8857 req.port_id = cpu_to_le16(bp->pf.port_id);
8858 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
8859 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
8860 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
8861 mutex_lock(&bp->hwrm_cmd_lock);
8862 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8863 if (!rc)
8864 bp->wol_filter_id = resp->wol_filter_id;
8865 mutex_unlock(&bp->hwrm_cmd_lock);
8866 return rc;
8867 }
8868
8869 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
8870 {
8871 struct hwrm_wol_filter_free_input req = {0};
8872 int rc;
8873
8874 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
8875 req.port_id = cpu_to_le16(bp->pf.port_id);
8876 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
8877 req.wol_filter_id = bp->wol_filter_id;
8878 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8879 return rc;
8880 }
8881
8882 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
8883 {
8884 struct hwrm_wol_filter_qcfg_input req = {0};
8885 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8886 u16 next_handle = 0;
8887 int rc;
8888
8889 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
8890 req.port_id = cpu_to_le16(bp->pf.port_id);
8891 req.handle = cpu_to_le16(handle);
8892 mutex_lock(&bp->hwrm_cmd_lock);
8893 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8894 if (!rc) {
8895 next_handle = le16_to_cpu(resp->next_handle);
8896 if (next_handle != 0) {
8897 if (resp->wol_type ==
8898 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
8899 bp->wol = 1;
8900 bp->wol_filter_id = resp->wol_filter_id;
8901 }
8902 }
8903 }
8904 mutex_unlock(&bp->hwrm_cmd_lock);
8905 return next_handle;
8906 }
8907
8908 static void bnxt_get_wol_settings(struct bnxt *bp)
8909 {
8910 u16 handle = 0;
8911
8912 bp->wol = 0;
8913 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
8914 return;
8915
8916 do {
8917 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
8918 } while (handle && handle != 0xffff);
8919 }
8920
8921 #ifdef CONFIG_BNXT_HWMON
8922 static ssize_t bnxt_show_temp(struct device *dev,
8923 struct device_attribute *devattr, char *buf)
8924 {
8925 struct hwrm_temp_monitor_query_input req = {0};
8926 struct hwrm_temp_monitor_query_output *resp;
8927 struct bnxt *bp = dev_get_drvdata(dev);
8928 u32 temp = 0;
8929
8930 resp = bp->hwrm_cmd_resp_addr;
8931 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
8932 mutex_lock(&bp->hwrm_cmd_lock);
8933 if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
8934 temp = resp->temp * 1000;
8935 mutex_unlock(&bp->hwrm_cmd_lock);
8936
8937 return sprintf(buf, "%u\n", temp);
8938 }
8939 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
8940
8941 static struct attribute *bnxt_attrs[] = {
8942 &sensor_dev_attr_temp1_input.dev_attr.attr,
8943 NULL
8944 };
8945 ATTRIBUTE_GROUPS(bnxt);
8946
8947 static void bnxt_hwmon_close(struct bnxt *bp)
8948 {
8949 if (bp->hwmon_dev) {
8950 hwmon_device_unregister(bp->hwmon_dev);
8951 bp->hwmon_dev = NULL;
8952 }
8953 }
8954
8955 static void bnxt_hwmon_open(struct bnxt *bp)
8956 {
8957 struct pci_dev *pdev = bp->pdev;
8958
8959 if (bp->hwmon_dev)
8960 return;
8961
8962 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
8963 DRV_MODULE_NAME, bp,
8964 bnxt_groups);
8965 if (IS_ERR(bp->hwmon_dev)) {
8966 bp->hwmon_dev = NULL;
8967 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
8968 }
8969 }
8970 #else
8971 static void bnxt_hwmon_close(struct bnxt *bp)
8972 {
8973 }
8974
8975 static void bnxt_hwmon_open(struct bnxt *bp)
8976 {
8977 }
8978 #endif
8979
8980 static bool bnxt_eee_config_ok(struct bnxt *bp)
8981 {
8982 struct ethtool_eee *eee = &bp->eee;
8983 struct bnxt_link_info *link_info = &bp->link_info;
8984
8985 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
8986 return true;
8987
8988 if (eee->eee_enabled) {
8989 u32 advertising =
8990 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
8991
8992 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8993 eee->eee_enabled = 0;
8994 return false;
8995 }
8996 if (eee->advertised & ~advertising) {
8997 eee->advertised = advertising & eee->supported;
8998 return false;
8999 }
9000 }
9001 return true;
9002 }
9003
9004 static int bnxt_update_phy_setting(struct bnxt *bp)
9005 {
9006 int rc;
9007 bool update_link = false;
9008 bool update_pause = false;
9009 bool update_eee = false;
9010 struct bnxt_link_info *link_info = &bp->link_info;
9011
9012 rc = bnxt_update_link(bp, true);
9013 if (rc) {
9014 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
9015 rc);
9016 return rc;
9017 }
9018 if (!BNXT_SINGLE_PF(bp))
9019 return 0;
9020
9021 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
9022 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
9023 link_info->req_flow_ctrl)
9024 update_pause = true;
9025 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
9026 link_info->force_pause_setting != link_info->req_flow_ctrl)
9027 update_pause = true;
9028 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
9029 if (BNXT_AUTO_MODE(link_info->auto_mode))
9030 update_link = true;
9031 if (link_info->req_link_speed != link_info->force_link_speed)
9032 update_link = true;
9033 if (link_info->req_duplex != link_info->duplex_setting)
9034 update_link = true;
9035 } else {
9036 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
9037 update_link = true;
9038 if (link_info->advertising != link_info->auto_link_speeds)
9039 update_link = true;
9040 }
9041
9042
9043
9044
9045 if (!netif_carrier_ok(bp->dev))
9046 update_link = true;
9047
9048 if (!bnxt_eee_config_ok(bp))
9049 update_eee = true;
9050
9051 if (update_link)
9052 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
9053 else if (update_pause)
9054 rc = bnxt_hwrm_set_pause(bp);
9055 if (rc) {
9056 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
9057 rc);
9058 return rc;
9059 }
9060
9061 return rc;
9062 }
9063
9064
9065
9066
9067
9068
9069 static void bnxt_preset_reg_win(struct bnxt *bp)
9070 {
9071 if (BNXT_PF(bp)) {
9072
9073 writel(BNXT_CAG_REG_BASE,
9074 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
9075 }
9076 }
9077
9078 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
9079
9080 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
9081 {
9082 int rc = 0;
9083
9084 bnxt_preset_reg_win(bp);
9085 netif_carrier_off(bp->dev);
9086 if (irq_re_init) {
9087
9088 rc = bnxt_init_dflt_ring_mode(bp);
9089 if (rc) {
9090 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
9091 return rc;
9092 }
9093 }
9094 rc = bnxt_reserve_rings(bp, irq_re_init);
9095 if (rc)
9096 return rc;
9097 if ((bp->flags & BNXT_FLAG_RFS) &&
9098 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
9099
9100 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
9101 bp->flags &= ~BNXT_FLAG_RFS;
9102 }
9103
9104 rc = bnxt_alloc_mem(bp, irq_re_init);
9105 if (rc) {
9106 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
9107 goto open_err_free_mem;
9108 }
9109
9110 if (irq_re_init) {
9111 bnxt_init_napi(bp);
9112 rc = bnxt_request_irq(bp);
9113 if (rc) {
9114 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
9115 goto open_err_irq;
9116 }
9117 }
9118
9119 bnxt_enable_napi(bp);
9120 bnxt_debug_dev_init(bp);
9121
9122 rc = bnxt_init_nic(bp, irq_re_init);
9123 if (rc) {
9124 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
9125 goto open_err;
9126 }
9127
9128 if (link_re_init) {
9129 mutex_lock(&bp->link_lock);
9130 rc = bnxt_update_phy_setting(bp);
9131 mutex_unlock(&bp->link_lock);
9132 if (rc) {
9133 netdev_warn(bp->dev, "failed to update phy settings\n");
9134 if (BNXT_SINGLE_PF(bp)) {
9135 bp->link_info.phy_retry = true;
9136 bp->link_info.phy_retry_expires =
9137 jiffies + 5 * HZ;
9138 }
9139 }
9140 }
9141
9142 if (irq_re_init)
9143 udp_tunnel_get_rx_info(bp->dev);
9144
9145 set_bit(BNXT_STATE_OPEN, &bp->state);
9146 bnxt_enable_int(bp);
9147
9148 bnxt_tx_enable(bp);
9149 mod_timer(&bp->timer, jiffies + bp->current_interval);
9150
9151 bnxt_get_port_module_status(bp);
9152
9153
9154 if (BNXT_PF(bp))
9155 bnxt_vf_reps_open(bp);
9156 return 0;
9157
9158 open_err:
9159 bnxt_debug_dev_exit(bp);
9160 bnxt_disable_napi(bp);
9161
9162 open_err_irq:
9163 bnxt_del_napi(bp);
9164
9165 open_err_free_mem:
9166 bnxt_free_skbs(bp);
9167 bnxt_free_irq(bp);
9168 bnxt_free_mem(bp, true);
9169 return rc;
9170 }
9171
9172
9173 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
9174 {
9175 int rc = 0;
9176
9177 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
9178 if (rc) {
9179 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
9180 dev_close(bp->dev);
9181 }
9182 return rc;
9183 }
9184
9185
9186
9187
9188
9189 int bnxt_half_open_nic(struct bnxt *bp)
9190 {
9191 int rc = 0;
9192
9193 rc = bnxt_alloc_mem(bp, false);
9194 if (rc) {
9195 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
9196 goto half_open_err;
9197 }
9198 rc = bnxt_init_nic(bp, false);
9199 if (rc) {
9200 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
9201 goto half_open_err;
9202 }
9203 return 0;
9204
9205 half_open_err:
9206 bnxt_free_skbs(bp);
9207 bnxt_free_mem(bp, false);
9208 dev_close(bp->dev);
9209 return rc;
9210 }
9211
9212
9213
9214
9215 void bnxt_half_close_nic(struct bnxt *bp)
9216 {
9217 bnxt_hwrm_resource_free(bp, false, false);
9218 bnxt_free_skbs(bp);
9219 bnxt_free_mem(bp, false);
9220 }
9221
9222 static int bnxt_open(struct net_device *dev)
9223 {
9224 struct bnxt *bp = netdev_priv(dev);
9225 int rc;
9226
9227 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
9228 netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n");
9229 return -ENODEV;
9230 }
9231
9232 rc = bnxt_hwrm_if_change(bp, true);
9233 if (rc)
9234 return rc;
9235 rc = __bnxt_open_nic(bp, true, true);
9236 if (rc) {
9237 bnxt_hwrm_if_change(bp, false);
9238 } else {
9239 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state) &&
9240 BNXT_PF(bp)) {
9241 struct bnxt_pf_info *pf = &bp->pf;
9242 int n = pf->active_vfs;
9243
9244 if (n)
9245 bnxt_cfg_hw_sriov(bp, &n, true);
9246 }
9247 bnxt_hwmon_open(bp);
9248 }
9249
9250 return rc;
9251 }
9252
9253 static bool bnxt_drv_busy(struct bnxt *bp)
9254 {
9255 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
9256 test_bit(BNXT_STATE_READ_STATS, &bp->state));
9257 }
9258
9259 static void bnxt_get_ring_stats(struct bnxt *bp,
9260 struct rtnl_link_stats64 *stats);
9261
9262 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
9263 bool link_re_init)
9264 {
9265
9266 if (BNXT_PF(bp))
9267 bnxt_vf_reps_close(bp);
9268
9269
9270 bnxt_tx_disable(bp);
9271
9272 clear_bit(BNXT_STATE_OPEN, &bp->state);
9273 smp_mb__after_atomic();
9274 while (bnxt_drv_busy(bp))
9275 msleep(20);
9276
9277
9278 bnxt_shutdown_nic(bp, irq_re_init);
9279
9280
9281
9282 bnxt_debug_dev_exit(bp);
9283 bnxt_disable_napi(bp);
9284 del_timer_sync(&bp->timer);
9285 bnxt_free_skbs(bp);
9286
9287
9288 if (bp->bnapi && irq_re_init)
9289 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
9290 if (irq_re_init) {
9291 bnxt_free_irq(bp);
9292 bnxt_del_napi(bp);
9293 }
9294 bnxt_free_mem(bp, irq_re_init);
9295 }
9296
9297 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
9298 {
9299 int rc = 0;
9300
9301 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
9302
9303
9304
9305
9306
9307
9308
9309 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n");
9310 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
9311 }
9312
9313 #ifdef CONFIG_BNXT_SRIOV
9314 if (bp->sriov_cfg) {
9315 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
9316 !bp->sriov_cfg,
9317 BNXT_SRIOV_CFG_WAIT_TMO);
9318 if (rc)
9319 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
9320 }
9321 #endif
9322 __bnxt_close_nic(bp, irq_re_init, link_re_init);
9323 return rc;
9324 }
9325
9326 static int bnxt_close(struct net_device *dev)
9327 {
9328 struct bnxt *bp = netdev_priv(dev);
9329
9330 bnxt_hwmon_close(bp);
9331 bnxt_close_nic(bp, true, true);
9332 bnxt_hwrm_shutdown_link(bp);
9333 bnxt_hwrm_if_change(bp, false);
9334 return 0;
9335 }
9336
9337 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
9338 u16 *val)
9339 {
9340 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
9341 struct hwrm_port_phy_mdio_read_input req = {0};
9342 int rc;
9343
9344 if (bp->hwrm_spec_code < 0x10a00)
9345 return -EOPNOTSUPP;
9346
9347 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
9348 req.port_id = cpu_to_le16(bp->pf.port_id);
9349 req.phy_addr = phy_addr;
9350 req.reg_addr = cpu_to_le16(reg & 0x1f);
9351 if (mdio_phy_id_is_c45(phy_addr)) {
9352 req.cl45_mdio = 1;
9353 req.phy_addr = mdio_phy_id_prtad(phy_addr);
9354 req.dev_addr = mdio_phy_id_devad(phy_addr);
9355 req.reg_addr = cpu_to_le16(reg);
9356 }
9357
9358 mutex_lock(&bp->hwrm_cmd_lock);
9359 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9360 if (!rc)
9361 *val = le16_to_cpu(resp->reg_data);
9362 mutex_unlock(&bp->hwrm_cmd_lock);
9363 return rc;
9364 }
9365
9366 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
9367 u16 val)
9368 {
9369 struct hwrm_port_phy_mdio_write_input req = {0};
9370
9371 if (bp->hwrm_spec_code < 0x10a00)
9372 return -EOPNOTSUPP;
9373
9374 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
9375 req.port_id = cpu_to_le16(bp->pf.port_id);
9376 req.phy_addr = phy_addr;
9377 req.reg_addr = cpu_to_le16(reg & 0x1f);
9378 if (mdio_phy_id_is_c45(phy_addr)) {
9379 req.cl45_mdio = 1;
9380 req.phy_addr = mdio_phy_id_prtad(phy_addr);
9381 req.dev_addr = mdio_phy_id_devad(phy_addr);
9382 req.reg_addr = cpu_to_le16(reg);
9383 }
9384 req.reg_data = cpu_to_le16(val);
9385
9386 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9387 }
9388
9389
9390 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9391 {
9392 struct mii_ioctl_data *mdio = if_mii(ifr);
9393 struct bnxt *bp = netdev_priv(dev);
9394 int rc;
9395
9396 switch (cmd) {
9397 case SIOCGMIIPHY:
9398 mdio->phy_id = bp->link_info.phy_addr;
9399
9400
9401 case SIOCGMIIREG: {
9402 u16 mii_regval = 0;
9403
9404 if (!netif_running(dev))
9405 return -EAGAIN;
9406
9407 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
9408 &mii_regval);
9409 mdio->val_out = mii_regval;
9410 return rc;
9411 }
9412
9413 case SIOCSMIIREG:
9414 if (!netif_running(dev))
9415 return -EAGAIN;
9416
9417 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
9418 mdio->val_in);
9419
9420 default:
9421
9422 break;
9423 }
9424 return -EOPNOTSUPP;
9425 }
9426
9427 static void bnxt_get_ring_stats(struct bnxt *bp,
9428 struct rtnl_link_stats64 *stats)
9429 {
9430 int i;
9431
9432
9433 for (i = 0; i < bp->cp_nr_rings; i++) {
9434 struct bnxt_napi *bnapi = bp->bnapi[i];
9435 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
9436 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
9437
9438 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
9439 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
9440 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
9441
9442 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
9443 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
9444 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
9445
9446 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
9447 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
9448 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
9449
9450 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
9451 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
9452 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
9453
9454 stats->rx_missed_errors +=
9455 le64_to_cpu(hw_stats->rx_discard_pkts);
9456
9457 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
9458
9459 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
9460 }
9461 }
9462
9463 static void bnxt_add_prev_stats(struct bnxt *bp,
9464 struct rtnl_link_stats64 *stats)
9465 {
9466 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
9467
9468 stats->rx_packets += prev_stats->rx_packets;
9469 stats->tx_packets += prev_stats->tx_packets;
9470 stats->rx_bytes += prev_stats->rx_bytes;
9471 stats->tx_bytes += prev_stats->tx_bytes;
9472 stats->rx_missed_errors += prev_stats->rx_missed_errors;
9473 stats->multicast += prev_stats->multicast;
9474 stats->tx_dropped += prev_stats->tx_dropped;
9475 }
9476
9477 static void
9478 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
9479 {
9480 struct bnxt *bp = netdev_priv(dev);
9481
9482 set_bit(BNXT_STATE_READ_STATS, &bp->state);
9483
9484
9485
9486 smp_mb__after_atomic();
9487 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9488 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
9489 *stats = bp->net_stats_prev;
9490 return;
9491 }
9492
9493 bnxt_get_ring_stats(bp, stats);
9494 bnxt_add_prev_stats(bp, stats);
9495
9496 if (bp->flags & BNXT_FLAG_PORT_STATS) {
9497 struct rx_port_stats *rx = bp->hw_rx_port_stats;
9498 struct tx_port_stats *tx = bp->hw_tx_port_stats;
9499
9500 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
9501 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
9502 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
9503 le64_to_cpu(rx->rx_ovrsz_frames) +
9504 le64_to_cpu(rx->rx_runt_frames);
9505 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
9506 le64_to_cpu(rx->rx_jbr_frames);
9507 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
9508 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
9509 stats->tx_errors = le64_to_cpu(tx->tx_err);
9510 }
9511 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
9512 }
9513
9514 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
9515 {
9516 struct net_device *dev = bp->dev;
9517 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9518 struct netdev_hw_addr *ha;
9519 u8 *haddr;
9520 int mc_count = 0;
9521 bool update = false;
9522 int off = 0;
9523
9524 netdev_for_each_mc_addr(ha, dev) {
9525 if (mc_count >= BNXT_MAX_MC_ADDRS) {
9526 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9527 vnic->mc_list_count = 0;
9528 return false;
9529 }
9530 haddr = ha->addr;
9531 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
9532 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
9533 update = true;
9534 }
9535 off += ETH_ALEN;
9536 mc_count++;
9537 }
9538 if (mc_count)
9539 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
9540
9541 if (mc_count != vnic->mc_list_count) {
9542 vnic->mc_list_count = mc_count;
9543 update = true;
9544 }
9545 return update;
9546 }
9547
9548 static bool bnxt_uc_list_updated(struct bnxt *bp)
9549 {
9550 struct net_device *dev = bp->dev;
9551 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9552 struct netdev_hw_addr *ha;
9553 int off = 0;
9554
9555 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
9556 return true;
9557
9558 netdev_for_each_uc_addr(ha, dev) {
9559 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
9560 return true;
9561
9562 off += ETH_ALEN;
9563 }
9564 return false;
9565 }
9566
9567 static void bnxt_set_rx_mode(struct net_device *dev)
9568 {
9569 struct bnxt *bp = netdev_priv(dev);
9570 struct bnxt_vnic_info *vnic;
9571 bool mc_update = false;
9572 bool uc_update;
9573 u32 mask;
9574
9575 if (!test_bit(BNXT_STATE_OPEN, &bp->state))
9576 return;
9577
9578 vnic = &bp->vnic_info[0];
9579 mask = vnic->rx_mask;
9580 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
9581 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
9582 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
9583 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
9584
9585 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
9586 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9587
9588 uc_update = bnxt_uc_list_updated(bp);
9589
9590 if (dev->flags & IFF_BROADCAST)
9591 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
9592 if (dev->flags & IFF_ALLMULTI) {
9593 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9594 vnic->mc_list_count = 0;
9595 } else {
9596 mc_update = bnxt_mc_list_updated(bp, &mask);
9597 }
9598
9599 if (mask != vnic->rx_mask || uc_update || mc_update) {
9600 vnic->rx_mask = mask;
9601
9602 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
9603 bnxt_queue_sp_work(bp);
9604 }
9605 }
9606
9607 static int bnxt_cfg_rx_mode(struct bnxt *bp)
9608 {
9609 struct net_device *dev = bp->dev;
9610 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9611 struct netdev_hw_addr *ha;
9612 int i, off = 0, rc;
9613 bool uc_update;
9614
9615 netif_addr_lock_bh(dev);
9616 uc_update = bnxt_uc_list_updated(bp);
9617 netif_addr_unlock_bh(dev);
9618
9619 if (!uc_update)
9620 goto skip_uc;
9621
9622 mutex_lock(&bp->hwrm_cmd_lock);
9623 for (i = 1; i < vnic->uc_filter_count; i++) {
9624 struct hwrm_cfa_l2_filter_free_input req = {0};
9625
9626 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
9627 -1);
9628
9629 req.l2_filter_id = vnic->fw_l2_filter_id[i];
9630
9631 rc = _hwrm_send_message(bp, &req, sizeof(req),
9632 HWRM_CMD_TIMEOUT);
9633 }
9634 mutex_unlock(&bp->hwrm_cmd_lock);
9635
9636 vnic->uc_filter_count = 1;
9637
9638 netif_addr_lock_bh(dev);
9639 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
9640 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9641 } else {
9642 netdev_for_each_uc_addr(ha, dev) {
9643 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
9644 off += ETH_ALEN;
9645 vnic->uc_filter_count++;
9646 }
9647 }
9648 netif_addr_unlock_bh(dev);
9649
9650 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
9651 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
9652 if (rc) {
9653 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
9654 rc);
9655 vnic->uc_filter_count = i;
9656 return rc;
9657 }
9658 }
9659
9660 skip_uc:
9661 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9662 if (rc && vnic->mc_list_count) {
9663 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
9664 rc);
9665 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9666 vnic->mc_list_count = 0;
9667 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9668 }
9669 if (rc)
9670 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
9671 rc);
9672
9673 return rc;
9674 }
9675
9676 static bool bnxt_can_reserve_rings(struct bnxt *bp)
9677 {
9678 #ifdef CONFIG_BNXT_SRIOV
9679 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
9680 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9681
9682
9683
9684
9685 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
9686 return true;
9687
9688 if (!netif_running(bp->dev))
9689 return false;
9690 }
9691 #endif
9692 return true;
9693 }
9694
9695
9696 static bool bnxt_rfs_supported(struct bnxt *bp)
9697 {
9698 if (bp->flags & BNXT_FLAG_CHIP_P5) {
9699 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX)
9700 return true;
9701 return false;
9702 }
9703 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
9704 return true;
9705 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9706 return true;
9707 return false;
9708 }
9709
9710
9711 static bool bnxt_rfs_capable(struct bnxt *bp)
9712 {
9713 #ifdef CONFIG_RFS_ACCEL
9714 int vnics, max_vnics, max_rss_ctxs;
9715
9716 if (bp->flags & BNXT_FLAG_CHIP_P5)
9717 return bnxt_rfs_supported(bp);
9718 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
9719 return false;
9720
9721 vnics = 1 + bp->rx_nr_rings;
9722 max_vnics = bnxt_get_max_func_vnics(bp);
9723 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
9724
9725
9726 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9727 max_rss_ctxs = max_vnics;
9728 if (vnics > max_vnics || vnics > max_rss_ctxs) {
9729 if (bp->rx_nr_rings > 1)
9730 netdev_warn(bp->dev,
9731 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
9732 min(max_rss_ctxs - 1, max_vnics - 1));
9733 return false;
9734 }
9735
9736 if (!BNXT_NEW_RM(bp))
9737 return true;
9738
9739 if (vnics == bp->hw_resc.resv_vnics)
9740 return true;
9741
9742 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
9743 if (vnics <= bp->hw_resc.resv_vnics)
9744 return true;
9745
9746 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
9747 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
9748 return false;
9749 #else
9750 return false;
9751 #endif
9752 }
9753
9754 static netdev_features_t bnxt_fix_features(struct net_device *dev,
9755 netdev_features_t features)
9756 {
9757 struct bnxt *bp = netdev_priv(dev);
9758 netdev_features_t vlan_features;
9759
9760 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
9761 features &= ~NETIF_F_NTUPLE;
9762
9763 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9764 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
9765
9766 if (!(features & NETIF_F_GRO))
9767 features &= ~NETIF_F_GRO_HW;
9768
9769 if (features & NETIF_F_GRO_HW)
9770 features &= ~NETIF_F_LRO;
9771
9772
9773
9774
9775 vlan_features = features & (NETIF_F_HW_VLAN_CTAG_RX |
9776 NETIF_F_HW_VLAN_STAG_RX);
9777 if (vlan_features != (NETIF_F_HW_VLAN_CTAG_RX |
9778 NETIF_F_HW_VLAN_STAG_RX)) {
9779 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
9780 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9781 NETIF_F_HW_VLAN_STAG_RX);
9782 else if (vlan_features)
9783 features |= NETIF_F_HW_VLAN_CTAG_RX |
9784 NETIF_F_HW_VLAN_STAG_RX;
9785 }
9786 #ifdef CONFIG_BNXT_SRIOV
9787 if (BNXT_VF(bp)) {
9788 if (bp->vf.vlan) {
9789 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9790 NETIF_F_HW_VLAN_STAG_RX);
9791 }
9792 }
9793 #endif
9794 return features;
9795 }
9796
9797 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
9798 {
9799 struct bnxt *bp = netdev_priv(dev);
9800 u32 flags = bp->flags;
9801 u32 changes;
9802 int rc = 0;
9803 bool re_init = false;
9804 bool update_tpa = false;
9805
9806 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
9807 if (features & NETIF_F_GRO_HW)
9808 flags |= BNXT_FLAG_GRO;
9809 else if (features & NETIF_F_LRO)
9810 flags |= BNXT_FLAG_LRO;
9811
9812 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9813 flags &= ~BNXT_FLAG_TPA;
9814
9815 if (features & NETIF_F_HW_VLAN_CTAG_RX)
9816 flags |= BNXT_FLAG_STRIP_VLAN;
9817
9818 if (features & NETIF_F_NTUPLE)
9819 flags |= BNXT_FLAG_RFS;
9820
9821 changes = flags ^ bp->flags;
9822 if (changes & BNXT_FLAG_TPA) {
9823 update_tpa = true;
9824 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
9825 (flags & BNXT_FLAG_TPA) == 0 ||
9826 (bp->flags & BNXT_FLAG_CHIP_P5))
9827 re_init = true;
9828 }
9829
9830 if (changes & ~BNXT_FLAG_TPA)
9831 re_init = true;
9832
9833 if (flags != bp->flags) {
9834 u32 old_flags = bp->flags;
9835
9836 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9837 bp->flags = flags;
9838 if (update_tpa)
9839 bnxt_set_ring_params(bp);
9840 return rc;
9841 }
9842
9843 if (re_init) {
9844 bnxt_close_nic(bp, false, false);
9845 bp->flags = flags;
9846 if (update_tpa)
9847 bnxt_set_ring_params(bp);
9848
9849 return bnxt_open_nic(bp, false, false);
9850 }
9851 if (update_tpa) {
9852 bp->flags = flags;
9853 rc = bnxt_set_tpa(bp,
9854 (flags & BNXT_FLAG_TPA) ?
9855 true : false);
9856 if (rc)
9857 bp->flags = old_flags;
9858 }
9859 }
9860 return rc;
9861 }
9862
9863 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
9864 u32 ring_id, u32 *prod, u32 *cons)
9865 {
9866 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
9867 struct hwrm_dbg_ring_info_get_input req = {0};
9868 int rc;
9869
9870 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
9871 req.ring_type = ring_type;
9872 req.fw_ring_id = cpu_to_le32(ring_id);
9873 mutex_lock(&bp->hwrm_cmd_lock);
9874 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9875 if (!rc) {
9876 *prod = le32_to_cpu(resp->producer_index);
9877 *cons = le32_to_cpu(resp->consumer_index);
9878 }
9879 mutex_unlock(&bp->hwrm_cmd_lock);
9880 return rc;
9881 }
9882
9883 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
9884 {
9885 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9886 int i = bnapi->index;
9887
9888 if (!txr)
9889 return;
9890
9891 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
9892 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
9893 txr->tx_cons);
9894 }
9895
9896 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
9897 {
9898 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9899 int i = bnapi->index;
9900
9901 if (!rxr)
9902 return;
9903
9904 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
9905 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
9906 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
9907 rxr->rx_sw_agg_prod);
9908 }
9909
9910 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
9911 {
9912 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
9913 int i = bnapi->index;
9914
9915 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
9916 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
9917 }
9918
9919 static void bnxt_dbg_dump_states(struct bnxt *bp)
9920 {
9921 int i;
9922 struct bnxt_napi *bnapi;
9923
9924 for (i = 0; i < bp->cp_nr_rings; i++) {
9925 bnapi = bp->bnapi[i];
9926 if (netif_msg_drv(bp)) {
9927 bnxt_dump_tx_sw_state(bnapi);
9928 bnxt_dump_rx_sw_state(bnapi);
9929 bnxt_dump_cp_sw_state(bnapi);
9930 }
9931 }
9932 }
9933
9934 static void bnxt_reset_task(struct bnxt *bp, bool silent)
9935 {
9936 if (!silent)
9937 bnxt_dbg_dump_states(bp);
9938 if (netif_running(bp->dev)) {
9939 int rc;
9940
9941 if (!silent)
9942 bnxt_ulp_stop(bp);
9943 bnxt_close_nic(bp, false, false);
9944 rc = bnxt_open_nic(bp, false, false);
9945 if (!silent && !rc)
9946 bnxt_ulp_start(bp);
9947 }
9948 }
9949
9950 static void bnxt_tx_timeout(struct net_device *dev)
9951 {
9952 struct bnxt *bp = netdev_priv(dev);
9953
9954 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
9955 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
9956 bnxt_queue_sp_work(bp);
9957 }
9958
9959 static void bnxt_fw_health_check(struct bnxt *bp)
9960 {
9961 struct bnxt_fw_health *fw_health = bp->fw_health;
9962 u32 val;
9963
9964 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
9965 return;
9966
9967 if (fw_health->tmr_counter) {
9968 fw_health->tmr_counter--;
9969 return;
9970 }
9971
9972 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
9973 if (val == fw_health->last_fw_heartbeat)
9974 goto fw_reset;
9975
9976 fw_health->last_fw_heartbeat = val;
9977
9978 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
9979 if (val != fw_health->last_fw_reset_cnt)
9980 goto fw_reset;
9981
9982 fw_health->tmr_counter = fw_health->tmr_multiplier;
9983 return;
9984
9985 fw_reset:
9986 set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event);
9987 bnxt_queue_sp_work(bp);
9988 }
9989
9990 static void bnxt_timer(struct timer_list *t)
9991 {
9992 struct bnxt *bp = from_timer(bp, t, timer);
9993 struct net_device *dev = bp->dev;
9994
9995 if (!netif_running(dev))
9996 return;
9997
9998 if (atomic_read(&bp->intr_sem) != 0)
9999 goto bnxt_restart_timer;
10000
10001 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
10002 bnxt_fw_health_check(bp);
10003
10004 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
10005 bp->stats_coal_ticks) {
10006 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
10007 bnxt_queue_sp_work(bp);
10008 }
10009
10010 if (bnxt_tc_flower_enabled(bp)) {
10011 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
10012 bnxt_queue_sp_work(bp);
10013 }
10014
10015 if (bp->link_info.phy_retry) {
10016 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
10017 bp->link_info.phy_retry = 0;
10018 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
10019 } else {
10020 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
10021 bnxt_queue_sp_work(bp);
10022 }
10023 }
10024
10025 if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) {
10026 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
10027 bnxt_queue_sp_work(bp);
10028 }
10029 bnxt_restart_timer:
10030 mod_timer(&bp->timer, jiffies + bp->current_interval);
10031 }
10032
10033 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
10034 {
10035
10036
10037
10038
10039
10040 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
10041 rtnl_lock();
10042 }
10043
10044 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
10045 {
10046 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
10047 rtnl_unlock();
10048 }
10049
10050
10051 static void bnxt_reset(struct bnxt *bp, bool silent)
10052 {
10053 bnxt_rtnl_lock_sp(bp);
10054 if (test_bit(BNXT_STATE_OPEN, &bp->state))
10055 bnxt_reset_task(bp, silent);
10056 bnxt_rtnl_unlock_sp(bp);
10057 }
10058
10059 static void bnxt_fw_reset_close(struct bnxt *bp)
10060 {
10061 __bnxt_close_nic(bp, true, false);
10062 bnxt_ulp_irq_stop(bp);
10063
10064
10065
10066 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
10067 pci_disable_device(bp->pdev);
10068 bnxt_clear_int_mode(bp);
10069 bnxt_hwrm_func_drv_unrgtr(bp);
10070 if (pci_is_enabled(bp->pdev))
10071 pci_disable_device(bp->pdev);
10072 bnxt_free_ctx_mem(bp);
10073 kfree(bp->ctx);
10074 bp->ctx = NULL;
10075 }
10076
10077 static bool is_bnxt_fw_ok(struct bnxt *bp)
10078 {
10079 struct bnxt_fw_health *fw_health = bp->fw_health;
10080 bool no_heartbeat = false, has_reset = false;
10081 u32 val;
10082
10083 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
10084 if (val == fw_health->last_fw_heartbeat)
10085 no_heartbeat = true;
10086
10087 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
10088 if (val != fw_health->last_fw_reset_cnt)
10089 has_reset = true;
10090
10091 if (!no_heartbeat && has_reset)
10092 return true;
10093
10094 return false;
10095 }
10096
10097
10098 static void bnxt_force_fw_reset(struct bnxt *bp)
10099 {
10100 struct bnxt_fw_health *fw_health = bp->fw_health;
10101 u32 wait_dsecs;
10102
10103 if (!test_bit(BNXT_STATE_OPEN, &bp->state) ||
10104 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
10105 return;
10106
10107 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
10108 bnxt_fw_reset_close(bp);
10109 wait_dsecs = fw_health->master_func_wait_dsecs;
10110 if (fw_health->master) {
10111 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU)
10112 wait_dsecs = 0;
10113 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
10114 } else {
10115 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10;
10116 wait_dsecs = fw_health->normal_func_wait_dsecs;
10117 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
10118 }
10119
10120 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs;
10121 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs;
10122 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
10123 }
10124
10125 void bnxt_fw_exception(struct bnxt *bp)
10126 {
10127 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
10128 bnxt_rtnl_lock_sp(bp);
10129 bnxt_force_fw_reset(bp);
10130 bnxt_rtnl_unlock_sp(bp);
10131 }
10132
10133
10134
10135
10136 static int bnxt_get_registered_vfs(struct bnxt *bp)
10137 {
10138 #ifdef CONFIG_BNXT_SRIOV
10139 int rc;
10140
10141 if (!BNXT_PF(bp))
10142 return 0;
10143
10144 rc = bnxt_hwrm_func_qcfg(bp);
10145 if (rc) {
10146 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc);
10147 return rc;
10148 }
10149 if (bp->pf.registered_vfs)
10150 return bp->pf.registered_vfs;
10151 if (bp->sriov_cfg)
10152 return 1;
10153 #endif
10154 return 0;
10155 }
10156
10157 void bnxt_fw_reset(struct bnxt *bp)
10158 {
10159 bnxt_rtnl_lock_sp(bp);
10160 if (test_bit(BNXT_STATE_OPEN, &bp->state) &&
10161 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10162 int n = 0, tmo;
10163
10164 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
10165 if (bp->pf.active_vfs &&
10166 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
10167 n = bnxt_get_registered_vfs(bp);
10168 if (n < 0) {
10169 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n",
10170 n);
10171 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
10172 dev_close(bp->dev);
10173 goto fw_reset_exit;
10174 } else if (n > 0) {
10175 u16 vf_tmo_dsecs = n * 10;
10176
10177 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs)
10178 bp->fw_reset_max_dsecs = vf_tmo_dsecs;
10179 bp->fw_reset_state =
10180 BNXT_FW_RESET_STATE_POLL_VF;
10181 bnxt_queue_fw_reset_work(bp, HZ / 10);
10182 goto fw_reset_exit;
10183 }
10184 bnxt_fw_reset_close(bp);
10185 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
10186 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
10187 tmo = HZ / 10;
10188 } else {
10189 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
10190 tmo = bp->fw_reset_min_dsecs * HZ / 10;
10191 }
10192 bnxt_queue_fw_reset_work(bp, tmo);
10193 }
10194 fw_reset_exit:
10195 bnxt_rtnl_unlock_sp(bp);
10196 }
10197
10198 static void bnxt_chk_missed_irq(struct bnxt *bp)
10199 {
10200 int i;
10201
10202 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
10203 return;
10204
10205 for (i = 0; i < bp->cp_nr_rings; i++) {
10206 struct bnxt_napi *bnapi = bp->bnapi[i];
10207 struct bnxt_cp_ring_info *cpr;
10208 u32 fw_ring_id;
10209 int j;
10210
10211 if (!bnapi)
10212 continue;
10213
10214 cpr = &bnapi->cp_ring;
10215 for (j = 0; j < 2; j++) {
10216 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
10217 u32 val[2];
10218
10219 if (!cpr2 || cpr2->has_more_work ||
10220 !bnxt_has_work(bp, cpr2))
10221 continue;
10222
10223 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
10224 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
10225 continue;
10226 }
10227 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
10228 bnxt_dbg_hwrm_ring_info_get(bp,
10229 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
10230 fw_ring_id, &val[0], &val[1]);
10231 cpr->missed_irqs++;
10232 }
10233 }
10234 }
10235
10236 static void bnxt_cfg_ntp_filters(struct bnxt *);
10237
10238 static void bnxt_sp_task(struct work_struct *work)
10239 {
10240 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
10241
10242 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
10243 smp_mb__after_atomic();
10244 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
10245 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
10246 return;
10247 }
10248
10249 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
10250 bnxt_cfg_rx_mode(bp);
10251
10252 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
10253 bnxt_cfg_ntp_filters(bp);
10254 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
10255 bnxt_hwrm_exec_fwd_req(bp);
10256 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
10257 bnxt_hwrm_tunnel_dst_port_alloc(
10258 bp, bp->vxlan_port,
10259 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
10260 }
10261 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
10262 bnxt_hwrm_tunnel_dst_port_free(
10263 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
10264 }
10265 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
10266 bnxt_hwrm_tunnel_dst_port_alloc(
10267 bp, bp->nge_port,
10268 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
10269 }
10270 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
10271 bnxt_hwrm_tunnel_dst_port_free(
10272 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
10273 }
10274 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
10275 bnxt_hwrm_port_qstats(bp);
10276 bnxt_hwrm_port_qstats_ext(bp);
10277 bnxt_hwrm_pcie_qstats(bp);
10278 }
10279
10280 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
10281 int rc;
10282
10283 mutex_lock(&bp->link_lock);
10284 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
10285 &bp->sp_event))
10286 bnxt_hwrm_phy_qcaps(bp);
10287
10288 rc = bnxt_update_link(bp, true);
10289 mutex_unlock(&bp->link_lock);
10290 if (rc)
10291 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
10292 rc);
10293 }
10294 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
10295 int rc;
10296
10297 mutex_lock(&bp->link_lock);
10298 rc = bnxt_update_phy_setting(bp);
10299 mutex_unlock(&bp->link_lock);
10300 if (rc) {
10301 netdev_warn(bp->dev, "update phy settings retry failed\n");
10302 } else {
10303 bp->link_info.phy_retry = false;
10304 netdev_info(bp->dev, "update phy settings retry succeeded\n");
10305 }
10306 }
10307 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
10308 mutex_lock(&bp->link_lock);
10309 bnxt_get_port_module_status(bp);
10310 mutex_unlock(&bp->link_lock);
10311 }
10312
10313 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
10314 bnxt_tc_flow_stats_work(bp);
10315
10316 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
10317 bnxt_chk_missed_irq(bp);
10318
10319
10320
10321
10322 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
10323 bnxt_reset(bp, false);
10324
10325 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
10326 bnxt_reset(bp, true);
10327
10328 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event))
10329 bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT);
10330
10331 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) {
10332 if (!is_bnxt_fw_ok(bp))
10333 bnxt_devlink_health_report(bp,
10334 BNXT_FW_EXCEPTION_SP_EVENT);
10335 }
10336
10337 smp_mb__before_atomic();
10338 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
10339 }
10340
10341
10342 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
10343 int tx_xdp)
10344 {
10345 int max_rx, max_tx, tx_sets = 1;
10346 int tx_rings_needed, stats;
10347 int rx_rings = rx;
10348 int cp, vnics, rc;
10349
10350 if (tcs)
10351 tx_sets = tcs;
10352
10353 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
10354 if (rc)
10355 return rc;
10356
10357 if (max_rx < rx)
10358 return -ENOMEM;
10359
10360 tx_rings_needed = tx * tx_sets + tx_xdp;
10361 if (max_tx < tx_rings_needed)
10362 return -ENOMEM;
10363
10364 vnics = 1;
10365 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
10366 vnics += rx_rings;
10367
10368 if (bp->flags & BNXT_FLAG_AGG_RINGS)
10369 rx_rings <<= 1;
10370 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
10371 stats = cp;
10372 if (BNXT_NEW_RM(bp)) {
10373 cp += bnxt_get_ulp_msix_num(bp);
10374 stats += bnxt_get_ulp_stat_ctxs(bp);
10375 }
10376 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
10377 stats, vnics);
10378 }
10379
10380 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
10381 {
10382 if (bp->bar2) {
10383 pci_iounmap(pdev, bp->bar2);
10384 bp->bar2 = NULL;
10385 }
10386
10387 if (bp->bar1) {
10388 pci_iounmap(pdev, bp->bar1);
10389 bp->bar1 = NULL;
10390 }
10391
10392 if (bp->bar0) {
10393 pci_iounmap(pdev, bp->bar0);
10394 bp->bar0 = NULL;
10395 }
10396 }
10397
10398 static void bnxt_cleanup_pci(struct bnxt *bp)
10399 {
10400 bnxt_unmap_bars(bp, bp->pdev);
10401 pci_release_regions(bp->pdev);
10402 if (pci_is_enabled(bp->pdev))
10403 pci_disable_device(bp->pdev);
10404 }
10405
10406 static void bnxt_init_dflt_coal(struct bnxt *bp)
10407 {
10408 struct bnxt_coal *coal;
10409
10410
10411
10412
10413 coal = &bp->rx_coal;
10414 coal->coal_ticks = 10;
10415 coal->coal_bufs = 30;
10416 coal->coal_ticks_irq = 1;
10417 coal->coal_bufs_irq = 2;
10418 coal->idle_thresh = 50;
10419 coal->bufs_per_record = 2;
10420 coal->budget = 64;
10421
10422 coal = &bp->tx_coal;
10423 coal->coal_ticks = 28;
10424 coal->coal_bufs = 30;
10425 coal->coal_ticks_irq = 2;
10426 coal->coal_bufs_irq = 2;
10427 coal->bufs_per_record = 1;
10428
10429 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
10430 }
10431
10432 static void bnxt_alloc_fw_health(struct bnxt *bp)
10433 {
10434 if (bp->fw_health)
10435 return;
10436
10437 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) &&
10438 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
10439 return;
10440
10441 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL);
10442 if (!bp->fw_health) {
10443 netdev_warn(bp->dev, "Failed to allocate fw_health\n");
10444 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET;
10445 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
10446 }
10447 }
10448
10449 static int bnxt_fw_init_one_p1(struct bnxt *bp)
10450 {
10451 int rc;
10452
10453 bp->fw_cap = 0;
10454 rc = bnxt_hwrm_ver_get(bp);
10455 if (rc)
10456 return rc;
10457
10458 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
10459 rc = bnxt_alloc_kong_hwrm_resources(bp);
10460 if (rc)
10461 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
10462 }
10463
10464 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
10465 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
10466 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
10467 if (rc)
10468 return rc;
10469 }
10470 rc = bnxt_hwrm_func_reset(bp);
10471 if (rc)
10472 return -ENODEV;
10473
10474 bnxt_hwrm_fw_set_time(bp);
10475 return 0;
10476 }
10477
10478 static int bnxt_fw_init_one_p2(struct bnxt *bp)
10479 {
10480 int rc;
10481
10482
10483 rc = bnxt_hwrm_func_qcaps(bp);
10484 if (rc) {
10485 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
10486 rc);
10487 return -ENODEV;
10488 }
10489
10490 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
10491 if (rc)
10492 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
10493 rc);
10494
10495 bnxt_alloc_fw_health(bp);
10496 rc = bnxt_hwrm_error_recovery_qcfg(bp);
10497 if (rc)
10498 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n",
10499 rc);
10500
10501 rc = bnxt_hwrm_func_drv_rgtr(bp);
10502 if (rc)
10503 return -ENODEV;
10504
10505 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
10506 if (rc)
10507 return -ENODEV;
10508
10509 bnxt_hwrm_func_qcfg(bp);
10510 bnxt_hwrm_vnic_qcaps(bp);
10511 bnxt_hwrm_port_led_qcaps(bp);
10512 bnxt_ethtool_init(bp);
10513 bnxt_dcb_init(bp);
10514 return 0;
10515 }
10516
10517 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp)
10518 {
10519 bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP;
10520 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
10521 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
10522 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
10523 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
10524 if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
10525 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
10526 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
10527 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
10528 }
10529 }
10530
10531 static void bnxt_set_dflt_rfs(struct bnxt *bp)
10532 {
10533 struct net_device *dev = bp->dev;
10534
10535 dev->hw_features &= ~NETIF_F_NTUPLE;
10536 dev->features &= ~NETIF_F_NTUPLE;
10537 bp->flags &= ~BNXT_FLAG_RFS;
10538 if (bnxt_rfs_supported(bp)) {
10539 dev->hw_features |= NETIF_F_NTUPLE;
10540 if (bnxt_rfs_capable(bp)) {
10541 bp->flags |= BNXT_FLAG_RFS;
10542 dev->features |= NETIF_F_NTUPLE;
10543 }
10544 }
10545 }
10546
10547 static void bnxt_fw_init_one_p3(struct bnxt *bp)
10548 {
10549 struct pci_dev *pdev = bp->pdev;
10550
10551 bnxt_set_dflt_rss_hash_type(bp);
10552 bnxt_set_dflt_rfs(bp);
10553
10554 bnxt_get_wol_settings(bp);
10555 if (bp->flags & BNXT_FLAG_WOL_CAP)
10556 device_set_wakeup_enable(&pdev->dev, bp->wol);
10557 else
10558 device_set_wakeup_capable(&pdev->dev, false);
10559
10560 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
10561 bnxt_hwrm_coal_params_qcaps(bp);
10562 }
10563
10564 static int bnxt_fw_init_one(struct bnxt *bp)
10565 {
10566 int rc;
10567
10568 rc = bnxt_fw_init_one_p1(bp);
10569 if (rc) {
10570 netdev_err(bp->dev, "Firmware init phase 1 failed\n");
10571 return rc;
10572 }
10573 rc = bnxt_fw_init_one_p2(bp);
10574 if (rc) {
10575 netdev_err(bp->dev, "Firmware init phase 2 failed\n");
10576 return rc;
10577 }
10578 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false);
10579 if (rc)
10580 return rc;
10581
10582
10583
10584
10585 bnxt_dl_fw_reporters_destroy(bp, false);
10586 bnxt_dl_fw_reporters_create(bp);
10587 bnxt_fw_init_one_p3(bp);
10588 return 0;
10589 }
10590
10591 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx)
10592 {
10593 struct bnxt_fw_health *fw_health = bp->fw_health;
10594 u32 reg = fw_health->fw_reset_seq_regs[reg_idx];
10595 u32 val = fw_health->fw_reset_seq_vals[reg_idx];
10596 u32 reg_type, reg_off, delay_msecs;
10597
10598 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx];
10599 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
10600 reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
10601 switch (reg_type) {
10602 case BNXT_FW_HEALTH_REG_TYPE_CFG:
10603 pci_write_config_dword(bp->pdev, reg_off, val);
10604 break;
10605 case BNXT_FW_HEALTH_REG_TYPE_GRC:
10606 writel(reg_off & BNXT_GRC_BASE_MASK,
10607 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
10608 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000;
10609
10610 case BNXT_FW_HEALTH_REG_TYPE_BAR0:
10611 writel(val, bp->bar0 + reg_off);
10612 break;
10613 case BNXT_FW_HEALTH_REG_TYPE_BAR1:
10614 writel(val, bp->bar1 + reg_off);
10615 break;
10616 }
10617 if (delay_msecs) {
10618 pci_read_config_dword(bp->pdev, 0, &val);
10619 msleep(delay_msecs);
10620 }
10621 }
10622
10623 static void bnxt_reset_all(struct bnxt *bp)
10624 {
10625 struct bnxt_fw_health *fw_health = bp->fw_health;
10626 int i;
10627
10628 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) {
10629 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++)
10630 bnxt_fw_reset_writel(bp, i);
10631 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) {
10632 struct hwrm_fw_reset_input req = {0};
10633 int rc;
10634
10635 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1);
10636 req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
10637 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP;
10638 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP;
10639 req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
10640 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10641 if (rc)
10642 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc);
10643 }
10644 bp->fw_reset_timestamp = jiffies;
10645 }
10646
10647 static void bnxt_fw_reset_task(struct work_struct *work)
10648 {
10649 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work);
10650 int rc;
10651
10652 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10653 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n");
10654 return;
10655 }
10656
10657 switch (bp->fw_reset_state) {
10658 case BNXT_FW_RESET_STATE_POLL_VF: {
10659 int n = bnxt_get_registered_vfs(bp);
10660 int tmo;
10661
10662 if (n < 0) {
10663 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n",
10664 n, jiffies_to_msecs(jiffies -
10665 bp->fw_reset_timestamp));
10666 goto fw_reset_abort;
10667 } else if (n > 0) {
10668 if (time_after(jiffies, bp->fw_reset_timestamp +
10669 (bp->fw_reset_max_dsecs * HZ / 10))) {
10670 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
10671 bp->fw_reset_state = 0;
10672 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n",
10673 n);
10674 return;
10675 }
10676 bnxt_queue_fw_reset_work(bp, HZ / 10);
10677 return;
10678 }
10679 bp->fw_reset_timestamp = jiffies;
10680 rtnl_lock();
10681 bnxt_fw_reset_close(bp);
10682 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
10683 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
10684 tmo = HZ / 10;
10685 } else {
10686 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
10687 tmo = bp->fw_reset_min_dsecs * HZ / 10;
10688 }
10689 rtnl_unlock();
10690 bnxt_queue_fw_reset_work(bp, tmo);
10691 return;
10692 }
10693 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: {
10694 u32 val;
10695
10696 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
10697 if (!(val & BNXT_FW_STATUS_SHUTDOWN) &&
10698 !time_after(jiffies, bp->fw_reset_timestamp +
10699 (bp->fw_reset_max_dsecs * HZ / 10))) {
10700 bnxt_queue_fw_reset_work(bp, HZ / 5);
10701 return;
10702 }
10703
10704 if (!bp->fw_health->master) {
10705 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs;
10706
10707 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
10708 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
10709 return;
10710 }
10711 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
10712 }
10713
10714 case BNXT_FW_RESET_STATE_RESET_FW:
10715 bnxt_reset_all(bp);
10716 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
10717 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10);
10718 return;
10719 case BNXT_FW_RESET_STATE_ENABLE_DEV:
10720 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) {
10721 u32 val;
10722
10723 val = bnxt_fw_health_readl(bp,
10724 BNXT_FW_RESET_INPROG_REG);
10725 if (val)
10726 netdev_warn(bp->dev, "FW reset inprog %x after min wait time.\n",
10727 val);
10728 }
10729 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
10730 if (pci_enable_device(bp->pdev)) {
10731 netdev_err(bp->dev, "Cannot re-enable PCI device\n");
10732 goto fw_reset_abort;
10733 }
10734 pci_set_master(bp->pdev);
10735 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW;
10736
10737 case BNXT_FW_RESET_STATE_POLL_FW:
10738 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
10739 rc = __bnxt_hwrm_ver_get(bp, true);
10740 if (rc) {
10741 if (time_after(jiffies, bp->fw_reset_timestamp +
10742 (bp->fw_reset_max_dsecs * HZ / 10))) {
10743 netdev_err(bp->dev, "Firmware reset aborted\n");
10744 goto fw_reset_abort;
10745 }
10746 bnxt_queue_fw_reset_work(bp, HZ / 5);
10747 return;
10748 }
10749 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
10750 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING;
10751
10752 case BNXT_FW_RESET_STATE_OPENING:
10753 while (!rtnl_trylock()) {
10754 bnxt_queue_fw_reset_work(bp, HZ / 10);
10755 return;
10756 }
10757 rc = bnxt_open(bp->dev);
10758 if (rc) {
10759 netdev_err(bp->dev, "bnxt_open_nic() failed\n");
10760 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
10761 dev_close(bp->dev);
10762 }
10763 bnxt_ulp_irq_restart(bp, rc);
10764 rtnl_unlock();
10765
10766 bp->fw_reset_state = 0;
10767
10768 smp_mb__before_atomic();
10769 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
10770 break;
10771 }
10772 return;
10773
10774 fw_reset_abort:
10775 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
10776 bp->fw_reset_state = 0;
10777 rtnl_lock();
10778 dev_close(bp->dev);
10779 rtnl_unlock();
10780 }
10781
10782 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
10783 {
10784 int rc;
10785 struct bnxt *bp = netdev_priv(dev);
10786
10787 SET_NETDEV_DEV(dev, &pdev->dev);
10788
10789
10790 rc = pci_enable_device(pdev);
10791 if (rc) {
10792 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
10793 goto init_err;
10794 }
10795
10796 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10797 dev_err(&pdev->dev,
10798 "Cannot find PCI device base address, aborting\n");
10799 rc = -ENODEV;
10800 goto init_err_disable;
10801 }
10802
10803 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10804 if (rc) {
10805 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
10806 goto init_err_disable;
10807 }
10808
10809 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
10810 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
10811 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
10812 goto init_err_disable;
10813 }
10814
10815 pci_set_master(pdev);
10816
10817 bp->dev = dev;
10818 bp->pdev = pdev;
10819
10820 bp->bar0 = pci_ioremap_bar(pdev, 0);
10821 if (!bp->bar0) {
10822 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
10823 rc = -ENOMEM;
10824 goto init_err_release;
10825 }
10826
10827 bp->bar1 = pci_ioremap_bar(pdev, 2);
10828 if (!bp->bar1) {
10829 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
10830 rc = -ENOMEM;
10831 goto init_err_release;
10832 }
10833
10834 bp->bar2 = pci_ioremap_bar(pdev, 4);
10835 if (!bp->bar2) {
10836 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
10837 rc = -ENOMEM;
10838 goto init_err_release;
10839 }
10840
10841 pci_enable_pcie_error_reporting(pdev);
10842
10843 INIT_WORK(&bp->sp_task, bnxt_sp_task);
10844 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task);
10845
10846 spin_lock_init(&bp->ntp_fltr_lock);
10847 #if BITS_PER_LONG == 32
10848 spin_lock_init(&bp->db_lock);
10849 #endif
10850
10851 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
10852 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
10853
10854 bnxt_init_dflt_coal(bp);
10855
10856 timer_setup(&bp->timer, bnxt_timer, 0);
10857 bp->current_interval = BNXT_TIMER_INTERVAL;
10858
10859 clear_bit(BNXT_STATE_OPEN, &bp->state);
10860 return 0;
10861
10862 init_err_release:
10863 bnxt_unmap_bars(bp, pdev);
10864 pci_release_regions(pdev);
10865
10866 init_err_disable:
10867 pci_disable_device(pdev);
10868
10869 init_err:
10870 return rc;
10871 }
10872
10873
10874 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
10875 {
10876 struct sockaddr *addr = p;
10877 struct bnxt *bp = netdev_priv(dev);
10878 int rc = 0;
10879
10880 if (!is_valid_ether_addr(addr->sa_data))
10881 return -EADDRNOTAVAIL;
10882
10883 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
10884 return 0;
10885
10886 rc = bnxt_approve_mac(bp, addr->sa_data, true);
10887 if (rc)
10888 return rc;
10889
10890 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
10891 if (netif_running(dev)) {
10892 bnxt_close_nic(bp, false, false);
10893 rc = bnxt_open_nic(bp, false, false);
10894 }
10895
10896 return rc;
10897 }
10898
10899
10900 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
10901 {
10902 struct bnxt *bp = netdev_priv(dev);
10903
10904 if (netif_running(dev))
10905 bnxt_close_nic(bp, true, false);
10906
10907 dev->mtu = new_mtu;
10908 bnxt_set_ring_params(bp);
10909
10910 if (netif_running(dev))
10911 return bnxt_open_nic(bp, true, false);
10912
10913 return 0;
10914 }
10915
10916 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
10917 {
10918 struct bnxt *bp = netdev_priv(dev);
10919 bool sh = false;
10920 int rc;
10921
10922 if (tc > bp->max_tc) {
10923 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
10924 tc, bp->max_tc);
10925 return -EINVAL;
10926 }
10927
10928 if (netdev_get_num_tc(dev) == tc)
10929 return 0;
10930
10931 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
10932 sh = true;
10933
10934 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
10935 sh, tc, bp->tx_nr_rings_xdp);
10936 if (rc)
10937 return rc;
10938
10939
10940 if (netif_running(bp->dev))
10941 bnxt_close_nic(bp, true, false);
10942
10943 if (tc) {
10944 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
10945 netdev_set_num_tc(dev, tc);
10946 } else {
10947 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10948 netdev_reset_tc(dev);
10949 }
10950 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
10951 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
10952 bp->tx_nr_rings + bp->rx_nr_rings;
10953
10954 if (netif_running(bp->dev))
10955 return bnxt_open_nic(bp, true, false);
10956
10957 return 0;
10958 }
10959
10960 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
10961 void *cb_priv)
10962 {
10963 struct bnxt *bp = cb_priv;
10964
10965 if (!bnxt_tc_flower_enabled(bp) ||
10966 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
10967 return -EOPNOTSUPP;
10968
10969 switch (type) {
10970 case TC_SETUP_CLSFLOWER:
10971 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
10972 default:
10973 return -EOPNOTSUPP;
10974 }
10975 }
10976
10977 static LIST_HEAD(bnxt_block_cb_list);
10978
10979 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
10980 void *type_data)
10981 {
10982 struct bnxt *bp = netdev_priv(dev);
10983
10984 switch (type) {
10985 case TC_SETUP_BLOCK:
10986 return flow_block_cb_setup_simple(type_data,
10987 &bnxt_block_cb_list,
10988 bnxt_setup_tc_block_cb,
10989 bp, bp, true);
10990 case TC_SETUP_QDISC_MQPRIO: {
10991 struct tc_mqprio_qopt *mqprio = type_data;
10992
10993 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
10994
10995 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
10996 }
10997 default:
10998 return -EOPNOTSUPP;
10999 }
11000 }
11001
11002 #ifdef CONFIG_RFS_ACCEL
11003 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
11004 struct bnxt_ntuple_filter *f2)
11005 {
11006 struct flow_keys *keys1 = &f1->fkeys;
11007 struct flow_keys *keys2 = &f2->fkeys;
11008
11009 if (keys1->basic.n_proto != keys2->basic.n_proto ||
11010 keys1->basic.ip_proto != keys2->basic.ip_proto)
11011 return false;
11012
11013 if (keys1->basic.n_proto == htons(ETH_P_IP)) {
11014 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src ||
11015 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst)
11016 return false;
11017 } else {
11018 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src,
11019 sizeof(keys1->addrs.v6addrs.src)) ||
11020 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst,
11021 sizeof(keys1->addrs.v6addrs.dst)))
11022 return false;
11023 }
11024
11025 if (keys1->ports.ports == keys2->ports.ports &&
11026 keys1->control.flags == keys2->control.flags &&
11027 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
11028 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
11029 return true;
11030
11031 return false;
11032 }
11033
11034 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
11035 u16 rxq_index, u32 flow_id)
11036 {
11037 struct bnxt *bp = netdev_priv(dev);
11038 struct bnxt_ntuple_filter *fltr, *new_fltr;
11039 struct flow_keys *fkeys;
11040 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
11041 int rc = 0, idx, bit_id, l2_idx = 0;
11042 struct hlist_head *head;
11043
11044 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
11045 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
11046 int off = 0, j;
11047
11048 netif_addr_lock_bh(dev);
11049 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
11050 if (ether_addr_equal(eth->h_dest,
11051 vnic->uc_list + off)) {
11052 l2_idx = j + 1;
11053 break;
11054 }
11055 }
11056 netif_addr_unlock_bh(dev);
11057 if (!l2_idx)
11058 return -EINVAL;
11059 }
11060 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
11061 if (!new_fltr)
11062 return -ENOMEM;
11063
11064 fkeys = &new_fltr->fkeys;
11065 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
11066 rc = -EPROTONOSUPPORT;
11067 goto err_free;
11068 }
11069
11070 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
11071 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
11072 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
11073 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
11074 rc = -EPROTONOSUPPORT;
11075 goto err_free;
11076 }
11077 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
11078 bp->hwrm_spec_code < 0x10601) {
11079 rc = -EPROTONOSUPPORT;
11080 goto err_free;
11081 }
11082 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
11083 bp->hwrm_spec_code < 0x10601) {
11084 rc = -EPROTONOSUPPORT;
11085 goto err_free;
11086 }
11087
11088 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
11089 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
11090
11091 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
11092 head = &bp->ntp_fltr_hash_tbl[idx];
11093 rcu_read_lock();
11094 hlist_for_each_entry_rcu(fltr, head, hash) {
11095 if (bnxt_fltr_match(fltr, new_fltr)) {
11096 rcu_read_unlock();
11097 rc = 0;
11098 goto err_free;
11099 }
11100 }
11101 rcu_read_unlock();
11102
11103 spin_lock_bh(&bp->ntp_fltr_lock);
11104 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
11105 BNXT_NTP_FLTR_MAX_FLTR, 0);
11106 if (bit_id < 0) {
11107 spin_unlock_bh(&bp->ntp_fltr_lock);
11108 rc = -ENOMEM;
11109 goto err_free;
11110 }
11111
11112 new_fltr->sw_id = (u16)bit_id;
11113 new_fltr->flow_id = flow_id;
11114 new_fltr->l2_fltr_idx = l2_idx;
11115 new_fltr->rxq = rxq_index;
11116 hlist_add_head_rcu(&new_fltr->hash, head);
11117 bp->ntp_fltr_count++;
11118 spin_unlock_bh(&bp->ntp_fltr_lock);
11119
11120 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
11121 bnxt_queue_sp_work(bp);
11122
11123 return new_fltr->sw_id;
11124
11125 err_free:
11126 kfree(new_fltr);
11127 return rc;
11128 }
11129
11130 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
11131 {
11132 int i;
11133
11134 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
11135 struct hlist_head *head;
11136 struct hlist_node *tmp;
11137 struct bnxt_ntuple_filter *fltr;
11138 int rc;
11139
11140 head = &bp->ntp_fltr_hash_tbl[i];
11141 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
11142 bool del = false;
11143
11144 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
11145 if (rps_may_expire_flow(bp->dev, fltr->rxq,
11146 fltr->flow_id,
11147 fltr->sw_id)) {
11148 bnxt_hwrm_cfa_ntuple_filter_free(bp,
11149 fltr);
11150 del = true;
11151 }
11152 } else {
11153 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
11154 fltr);
11155 if (rc)
11156 del = true;
11157 else
11158 set_bit(BNXT_FLTR_VALID, &fltr->state);
11159 }
11160
11161 if (del) {
11162 spin_lock_bh(&bp->ntp_fltr_lock);
11163 hlist_del_rcu(&fltr->hash);
11164 bp->ntp_fltr_count--;
11165 spin_unlock_bh(&bp->ntp_fltr_lock);
11166 synchronize_rcu();
11167 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
11168 kfree(fltr);
11169 }
11170 }
11171 }
11172 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
11173 netdev_info(bp->dev, "Receive PF driver unload event!");
11174 }
11175
11176 #else
11177
11178 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
11179 {
11180 }
11181
11182 #endif
11183
11184 static void bnxt_udp_tunnel_add(struct net_device *dev,
11185 struct udp_tunnel_info *ti)
11186 {
11187 struct bnxt *bp = netdev_priv(dev);
11188
11189 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
11190 return;
11191
11192 if (!netif_running(dev))
11193 return;
11194
11195 switch (ti->type) {
11196 case UDP_TUNNEL_TYPE_VXLAN:
11197 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
11198 return;
11199
11200 bp->vxlan_port_cnt++;
11201 if (bp->vxlan_port_cnt == 1) {
11202 bp->vxlan_port = ti->port;
11203 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
11204 bnxt_queue_sp_work(bp);
11205 }
11206 break;
11207 case UDP_TUNNEL_TYPE_GENEVE:
11208 if (bp->nge_port_cnt && bp->nge_port != ti->port)
11209 return;
11210
11211 bp->nge_port_cnt++;
11212 if (bp->nge_port_cnt == 1) {
11213 bp->nge_port = ti->port;
11214 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
11215 }
11216 break;
11217 default:
11218 return;
11219 }
11220
11221 bnxt_queue_sp_work(bp);
11222 }
11223
11224 static void bnxt_udp_tunnel_del(struct net_device *dev,
11225 struct udp_tunnel_info *ti)
11226 {
11227 struct bnxt *bp = netdev_priv(dev);
11228
11229 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
11230 return;
11231
11232 if (!netif_running(dev))
11233 return;
11234
11235 switch (ti->type) {
11236 case UDP_TUNNEL_TYPE_VXLAN:
11237 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
11238 return;
11239 bp->vxlan_port_cnt--;
11240
11241 if (bp->vxlan_port_cnt != 0)
11242 return;
11243
11244 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
11245 break;
11246 case UDP_TUNNEL_TYPE_GENEVE:
11247 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
11248 return;
11249 bp->nge_port_cnt--;
11250
11251 if (bp->nge_port_cnt != 0)
11252 return;
11253
11254 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
11255 break;
11256 default:
11257 return;
11258 }
11259
11260 bnxt_queue_sp_work(bp);
11261 }
11262
11263 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
11264 struct net_device *dev, u32 filter_mask,
11265 int nlflags)
11266 {
11267 struct bnxt *bp = netdev_priv(dev);
11268
11269 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
11270 nlflags, filter_mask, NULL);
11271 }
11272
11273 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
11274 u16 flags, struct netlink_ext_ack *extack)
11275 {
11276 struct bnxt *bp = netdev_priv(dev);
11277 struct nlattr *attr, *br_spec;
11278 int rem, rc = 0;
11279
11280 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
11281 return -EOPNOTSUPP;
11282
11283 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
11284 if (!br_spec)
11285 return -EINVAL;
11286
11287 nla_for_each_nested(attr, br_spec, rem) {
11288 u16 mode;
11289
11290 if (nla_type(attr) != IFLA_BRIDGE_MODE)
11291 continue;
11292
11293 if (nla_len(attr) < sizeof(mode))
11294 return -EINVAL;
11295
11296 mode = nla_get_u16(attr);
11297 if (mode == bp->br_mode)
11298 break;
11299
11300 rc = bnxt_hwrm_set_br_mode(bp, mode);
11301 if (!rc)
11302 bp->br_mode = mode;
11303 break;
11304 }
11305 return rc;
11306 }
11307
11308 int bnxt_get_port_parent_id(struct net_device *dev,
11309 struct netdev_phys_item_id *ppid)
11310 {
11311 struct bnxt *bp = netdev_priv(dev);
11312
11313 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
11314 return -EOPNOTSUPP;
11315
11316
11317 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID))
11318 return -EOPNOTSUPP;
11319
11320 ppid->id_len = sizeof(bp->switch_id);
11321 memcpy(ppid->id, bp->switch_id, ppid->id_len);
11322
11323 return 0;
11324 }
11325
11326 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
11327 {
11328 struct bnxt *bp = netdev_priv(dev);
11329
11330 return &bp->dl_port;
11331 }
11332
11333 static const struct net_device_ops bnxt_netdev_ops = {
11334 .ndo_open = bnxt_open,
11335 .ndo_start_xmit = bnxt_start_xmit,
11336 .ndo_stop = bnxt_close,
11337 .ndo_get_stats64 = bnxt_get_stats64,
11338 .ndo_set_rx_mode = bnxt_set_rx_mode,
11339 .ndo_do_ioctl = bnxt_ioctl,
11340 .ndo_validate_addr = eth_validate_addr,
11341 .ndo_set_mac_address = bnxt_change_mac_addr,
11342 .ndo_change_mtu = bnxt_change_mtu,
11343 .ndo_fix_features = bnxt_fix_features,
11344 .ndo_set_features = bnxt_set_features,
11345 .ndo_tx_timeout = bnxt_tx_timeout,
11346 #ifdef CONFIG_BNXT_SRIOV
11347 .ndo_get_vf_config = bnxt_get_vf_config,
11348 .ndo_set_vf_mac = bnxt_set_vf_mac,
11349 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
11350 .ndo_set_vf_rate = bnxt_set_vf_bw,
11351 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
11352 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
11353 .ndo_set_vf_trust = bnxt_set_vf_trust,
11354 #endif
11355 .ndo_setup_tc = bnxt_setup_tc,
11356 #ifdef CONFIG_RFS_ACCEL
11357 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
11358 #endif
11359 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
11360 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
11361 .ndo_bpf = bnxt_xdp,
11362 .ndo_xdp_xmit = bnxt_xdp_xmit,
11363 .ndo_bridge_getlink = bnxt_bridge_getlink,
11364 .ndo_bridge_setlink = bnxt_bridge_setlink,
11365 .ndo_get_devlink_port = bnxt_get_devlink_port,
11366 };
11367
11368 static void bnxt_remove_one(struct pci_dev *pdev)
11369 {
11370 struct net_device *dev = pci_get_drvdata(pdev);
11371 struct bnxt *bp = netdev_priv(dev);
11372
11373 if (BNXT_PF(bp))
11374 bnxt_sriov_disable(bp);
11375
11376 bnxt_dl_fw_reporters_destroy(bp, true);
11377 pci_disable_pcie_error_reporting(pdev);
11378 unregister_netdev(dev);
11379 bnxt_dl_unregister(bp);
11380 bnxt_shutdown_tc(bp);
11381 bnxt_cancel_sp_work(bp);
11382 bp->sp_event = 0;
11383
11384 bnxt_clear_int_mode(bp);
11385 bnxt_hwrm_func_drv_unrgtr(bp);
11386 bnxt_free_hwrm_resources(bp);
11387 bnxt_free_hwrm_short_cmd_req(bp);
11388 bnxt_ethtool_free(bp);
11389 bnxt_dcb_free(bp);
11390 kfree(bp->edev);
11391 bp->edev = NULL;
11392 kfree(bp->fw_health);
11393 bp->fw_health = NULL;
11394 bnxt_cleanup_pci(bp);
11395 bnxt_free_ctx_mem(bp);
11396 kfree(bp->ctx);
11397 bp->ctx = NULL;
11398 bnxt_free_port_stats(bp);
11399 free_netdev(dev);
11400 }
11401
11402 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt)
11403 {
11404 int rc = 0;
11405 struct bnxt_link_info *link_info = &bp->link_info;
11406
11407 rc = bnxt_hwrm_phy_qcaps(bp);
11408 if (rc) {
11409 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
11410 rc);
11411 return rc;
11412 }
11413 rc = bnxt_update_link(bp, false);
11414 if (rc) {
11415 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
11416 rc);
11417 return rc;
11418 }
11419
11420
11421
11422
11423 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
11424 link_info->support_auto_speeds = link_info->support_speeds;
11425
11426 if (!fw_dflt)
11427 return 0;
11428
11429
11430 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
11431 link_info->autoneg = BNXT_AUTONEG_SPEED;
11432 if (bp->hwrm_spec_code >= 0x10201) {
11433 if (link_info->auto_pause_setting &
11434 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
11435 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
11436 } else {
11437 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
11438 }
11439 link_info->advertising = link_info->auto_link_speeds;
11440 } else {
11441 link_info->req_link_speed = link_info->force_link_speed;
11442 link_info->req_duplex = link_info->duplex_setting;
11443 }
11444 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
11445 link_info->req_flow_ctrl =
11446 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
11447 else
11448 link_info->req_flow_ctrl = link_info->force_pause_setting;
11449 return 0;
11450 }
11451
11452 static int bnxt_get_max_irq(struct pci_dev *pdev)
11453 {
11454 u16 ctrl;
11455
11456 if (!pdev->msix_cap)
11457 return 1;
11458
11459 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
11460 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
11461 }
11462
11463 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
11464 int *max_cp)
11465 {
11466 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
11467 int max_ring_grps = 0, max_irq;
11468
11469 *max_tx = hw_resc->max_tx_rings;
11470 *max_rx = hw_resc->max_rx_rings;
11471 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
11472 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
11473 bnxt_get_ulp_msix_num(bp),
11474 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
11475 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
11476 *max_cp = min_t(int, *max_cp, max_irq);
11477 max_ring_grps = hw_resc->max_hw_ring_grps;
11478 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
11479 *max_cp -= 1;
11480 *max_rx -= 2;
11481 }
11482 if (bp->flags & BNXT_FLAG_AGG_RINGS)
11483 *max_rx >>= 1;
11484 if (bp->flags & BNXT_FLAG_CHIP_P5) {
11485 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
11486
11487 *max_cp = max_irq;
11488 }
11489 *max_rx = min_t(int, *max_rx, max_ring_grps);
11490 }
11491
11492 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
11493 {
11494 int rx, tx, cp;
11495
11496 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
11497 *max_rx = rx;
11498 *max_tx = tx;
11499 if (!rx || !tx || !cp)
11500 return -ENOMEM;
11501
11502 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
11503 }
11504
11505 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
11506 bool shared)
11507 {
11508 int rc;
11509
11510 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
11511 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
11512
11513 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
11514 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
11515 if (rc) {
11516
11517 bp->flags |= BNXT_FLAG_AGG_RINGS;
11518 return rc;
11519 }
11520 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
11521 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
11522 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
11523 bnxt_set_ring_params(bp);
11524 }
11525
11526 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
11527 int max_cp, max_stat, max_irq;
11528
11529
11530 max_cp = bnxt_get_max_func_cp_rings(bp);
11531 max_stat = bnxt_get_max_func_stat_ctxs(bp);
11532 max_irq = bnxt_get_max_func_irqs(bp);
11533 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
11534 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
11535 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
11536 return 0;
11537
11538 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
11539 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
11540 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
11541 max_cp = min_t(int, max_cp, max_irq);
11542 max_cp = min_t(int, max_cp, max_stat);
11543 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
11544 if (rc)
11545 rc = 0;
11546 }
11547 return rc;
11548 }
11549
11550
11551
11552
11553 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
11554 {
11555 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
11556 bp->rx_nr_rings = bp->cp_nr_rings;
11557 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
11558 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
11559 }
11560
11561 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
11562 {
11563 int dflt_rings, max_rx_rings, max_tx_rings, rc;
11564
11565 if (!bnxt_can_reserve_rings(bp))
11566 return 0;
11567
11568 if (sh)
11569 bp->flags |= BNXT_FLAG_SHARED_RINGS;
11570 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
11571
11572
11573
11574 if (bp->port_count > 1) {
11575 int max_rings =
11576 max_t(int, num_online_cpus() / bp->port_count, 1);
11577
11578 dflt_rings = min_t(int, dflt_rings, max_rings);
11579 }
11580 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
11581 if (rc)
11582 return rc;
11583 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
11584 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
11585 if (sh)
11586 bnxt_trim_dflt_sh_rings(bp);
11587 else
11588 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
11589 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
11590
11591 rc = __bnxt_reserve_rings(bp);
11592 if (rc)
11593 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
11594 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
11595 if (sh)
11596 bnxt_trim_dflt_sh_rings(bp);
11597
11598
11599 if (bnxt_need_reserve_rings(bp)) {
11600 rc = __bnxt_reserve_rings(bp);
11601 if (rc)
11602 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
11603 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
11604 }
11605 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
11606 bp->rx_nr_rings++;
11607 bp->cp_nr_rings++;
11608 }
11609 if (rc) {
11610 bp->tx_nr_rings = 0;
11611 bp->rx_nr_rings = 0;
11612 }
11613 return rc;
11614 }
11615
11616 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
11617 {
11618 int rc;
11619
11620 if (bp->tx_nr_rings)
11621 return 0;
11622
11623 bnxt_ulp_irq_stop(bp);
11624 bnxt_clear_int_mode(bp);
11625 rc = bnxt_set_dflt_rings(bp, true);
11626 if (rc) {
11627 netdev_err(bp->dev, "Not enough rings available.\n");
11628 goto init_dflt_ring_err;
11629 }
11630 rc = bnxt_init_int_mode(bp);
11631 if (rc)
11632 goto init_dflt_ring_err;
11633
11634 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
11635 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
11636 bp->flags |= BNXT_FLAG_RFS;
11637 bp->dev->features |= NETIF_F_NTUPLE;
11638 }
11639 init_dflt_ring_err:
11640 bnxt_ulp_irq_restart(bp, rc);
11641 return rc;
11642 }
11643
11644 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
11645 {
11646 int rc;
11647
11648 ASSERT_RTNL();
11649 bnxt_hwrm_func_qcaps(bp);
11650
11651 if (netif_running(bp->dev))
11652 __bnxt_close_nic(bp, true, false);
11653
11654 bnxt_ulp_irq_stop(bp);
11655 bnxt_clear_int_mode(bp);
11656 rc = bnxt_init_int_mode(bp);
11657 bnxt_ulp_irq_restart(bp, rc);
11658
11659 if (netif_running(bp->dev)) {
11660 if (rc)
11661 dev_close(bp->dev);
11662 else
11663 rc = bnxt_open_nic(bp, true, false);
11664 }
11665
11666 return rc;
11667 }
11668
11669 static int bnxt_init_mac_addr(struct bnxt *bp)
11670 {
11671 int rc = 0;
11672
11673 if (BNXT_PF(bp)) {
11674 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
11675 } else {
11676 #ifdef CONFIG_BNXT_SRIOV
11677 struct bnxt_vf_info *vf = &bp->vf;
11678 bool strict_approval = true;
11679
11680 if (is_valid_ether_addr(vf->mac_addr)) {
11681
11682 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
11683
11684
11685
11686 strict_approval = false;
11687 } else {
11688 eth_hw_addr_random(bp->dev);
11689 }
11690 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
11691 #endif
11692 }
11693 return rc;
11694 }
11695
11696 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
11697 {
11698 struct pci_dev *pdev = bp->pdev;
11699 int pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN);
11700 u32 dw;
11701
11702 if (!pos) {
11703 netdev_info(bp->dev, "Unable do read adapter's DSN");
11704 return -EOPNOTSUPP;
11705 }
11706
11707
11708 pos += 4;
11709 pci_read_config_dword(pdev, pos, &dw);
11710 put_unaligned_le32(dw, &dsn[0]);
11711 pci_read_config_dword(pdev, pos + 4, &dw);
11712 put_unaligned_le32(dw, &dsn[4]);
11713 bp->flags |= BNXT_FLAG_DSN_VALID;
11714 return 0;
11715 }
11716
11717 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
11718 {
11719 static int version_printed;
11720 struct net_device *dev;
11721 struct bnxt *bp;
11722 int rc, max_irqs;
11723
11724 if (pci_is_bridge(pdev))
11725 return -ENODEV;
11726
11727 if (version_printed++ == 0)
11728 pr_info("%s", version);
11729
11730
11731
11732
11733 if (is_kdump_kernel()) {
11734 pci_clear_master(pdev);
11735 pcie_flr(pdev);
11736 }
11737
11738 max_irqs = bnxt_get_max_irq(pdev);
11739 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
11740 if (!dev)
11741 return -ENOMEM;
11742
11743 bp = netdev_priv(dev);
11744 bnxt_set_max_func_irqs(bp, max_irqs);
11745
11746 if (bnxt_vf_pciid(ent->driver_data))
11747 bp->flags |= BNXT_FLAG_VF;
11748
11749 if (pdev->msix_cap)
11750 bp->flags |= BNXT_FLAG_MSIX_CAP;
11751
11752 rc = bnxt_init_board(pdev, dev);
11753 if (rc < 0)
11754 goto init_err_free;
11755
11756 dev->netdev_ops = &bnxt_netdev_ops;
11757 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
11758 dev->ethtool_ops = &bnxt_ethtool_ops;
11759 pci_set_drvdata(pdev, dev);
11760
11761 rc = bnxt_alloc_hwrm_resources(bp);
11762 if (rc)
11763 goto init_err_pci_clean;
11764
11765 mutex_init(&bp->hwrm_cmd_lock);
11766 mutex_init(&bp->link_lock);
11767
11768 rc = bnxt_fw_init_one_p1(bp);
11769 if (rc)
11770 goto init_err_pci_clean;
11771
11772 if (BNXT_CHIP_P5(bp))
11773 bp->flags |= BNXT_FLAG_CHIP_P5;
11774
11775 rc = bnxt_fw_init_one_p2(bp);
11776 if (rc)
11777 goto init_err_pci_clean;
11778
11779 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
11780 NETIF_F_TSO | NETIF_F_TSO6 |
11781 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
11782 NETIF_F_GSO_IPXIP4 |
11783 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
11784 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
11785 NETIF_F_RXCSUM | NETIF_F_GRO;
11786
11787 if (BNXT_SUPPORTS_TPA(bp))
11788 dev->hw_features |= NETIF_F_LRO;
11789
11790 dev->hw_enc_features =
11791 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
11792 NETIF_F_TSO | NETIF_F_TSO6 |
11793 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
11794 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
11795 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
11796 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
11797 NETIF_F_GSO_GRE_CSUM;
11798 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
11799 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
11800 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
11801 if (BNXT_SUPPORTS_TPA(bp))
11802 dev->hw_features |= NETIF_F_GRO_HW;
11803 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
11804 if (dev->features & NETIF_F_GRO_HW)
11805 dev->features &= ~NETIF_F_LRO;
11806 dev->priv_flags |= IFF_UNICAST_FLT;
11807
11808 #ifdef CONFIG_BNXT_SRIOV
11809 init_waitqueue_head(&bp->sriov_cfg_wait);
11810 mutex_init(&bp->sriov_lock);
11811 #endif
11812 if (BNXT_SUPPORTS_TPA(bp)) {
11813 bp->gro_func = bnxt_gro_func_5730x;
11814 if (BNXT_CHIP_P4(bp))
11815 bp->gro_func = bnxt_gro_func_5731x;
11816 else if (BNXT_CHIP_P5(bp))
11817 bp->gro_func = bnxt_gro_func_5750x;
11818 }
11819 if (!BNXT_CHIP_P4_PLUS(bp))
11820 bp->flags |= BNXT_FLAG_DOUBLE_DB;
11821
11822 bp->ulp_probe = bnxt_ulp_probe;
11823
11824 rc = bnxt_init_mac_addr(bp);
11825 if (rc) {
11826 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
11827 rc = -EADDRNOTAVAIL;
11828 goto init_err_pci_clean;
11829 }
11830
11831 if (BNXT_PF(bp)) {
11832
11833 bnxt_pcie_dsn_get(bp, bp->switch_id);
11834 }
11835
11836
11837 dev->min_mtu = ETH_ZLEN;
11838 dev->max_mtu = bp->max_mtu;
11839
11840 rc = bnxt_probe_phy(bp, true);
11841 if (rc)
11842 goto init_err_pci_clean;
11843
11844 bnxt_set_rx_skb_mode(bp, false);
11845 bnxt_set_tpa_flags(bp);
11846 bnxt_set_ring_params(bp);
11847 rc = bnxt_set_dflt_rings(bp, true);
11848 if (rc) {
11849 netdev_err(bp->dev, "Not enough rings available.\n");
11850 rc = -ENOMEM;
11851 goto init_err_pci_clean;
11852 }
11853
11854 bnxt_fw_init_one_p3(bp);
11855
11856 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
11857 bp->flags |= BNXT_FLAG_STRIP_VLAN;
11858
11859 rc = bnxt_init_int_mode(bp);
11860 if (rc)
11861 goto init_err_pci_clean;
11862
11863
11864
11865
11866 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
11867
11868 if (BNXT_PF(bp)) {
11869 if (!bnxt_pf_wq) {
11870 bnxt_pf_wq =
11871 create_singlethread_workqueue("bnxt_pf_wq");
11872 if (!bnxt_pf_wq) {
11873 dev_err(&pdev->dev, "Unable to create workqueue.\n");
11874 goto init_err_pci_clean;
11875 }
11876 }
11877 bnxt_init_tc(bp);
11878 }
11879
11880 bnxt_dl_register(bp);
11881
11882 rc = register_netdev(dev);
11883 if (rc)
11884 goto init_err_cleanup;
11885
11886 if (BNXT_PF(bp))
11887 devlink_port_type_eth_set(&bp->dl_port, bp->dev);
11888 bnxt_dl_fw_reporters_create(bp);
11889
11890 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
11891 board_info[ent->driver_data].name,
11892 (long)pci_resource_start(pdev, 0), dev->dev_addr);
11893 pcie_print_link_status(pdev);
11894
11895 return 0;
11896
11897 init_err_cleanup:
11898 bnxt_dl_unregister(bp);
11899 bnxt_shutdown_tc(bp);
11900 bnxt_clear_int_mode(bp);
11901
11902 init_err_pci_clean:
11903 bnxt_free_hwrm_short_cmd_req(bp);
11904 bnxt_free_hwrm_resources(bp);
11905 kfree(bp->fw_health);
11906 bp->fw_health = NULL;
11907 bnxt_cleanup_pci(bp);
11908 bnxt_free_ctx_mem(bp);
11909 kfree(bp->ctx);
11910 bp->ctx = NULL;
11911
11912 init_err_free:
11913 free_netdev(dev);
11914 return rc;
11915 }
11916
11917 static void bnxt_shutdown(struct pci_dev *pdev)
11918 {
11919 struct net_device *dev = pci_get_drvdata(pdev);
11920 struct bnxt *bp;
11921
11922 if (!dev)
11923 return;
11924
11925 rtnl_lock();
11926 bp = netdev_priv(dev);
11927 if (!bp)
11928 goto shutdown_exit;
11929
11930 if (netif_running(dev))
11931 dev_close(dev);
11932
11933 bnxt_ulp_shutdown(bp);
11934 bnxt_clear_int_mode(bp);
11935 pci_disable_device(pdev);
11936
11937 if (system_state == SYSTEM_POWER_OFF) {
11938 pci_wake_from_d3(pdev, bp->wol);
11939 pci_set_power_state(pdev, PCI_D3hot);
11940 }
11941
11942 shutdown_exit:
11943 rtnl_unlock();
11944 }
11945
11946 #ifdef CONFIG_PM_SLEEP
11947 static int bnxt_suspend(struct device *device)
11948 {
11949 struct net_device *dev = dev_get_drvdata(device);
11950 struct bnxt *bp = netdev_priv(dev);
11951 int rc = 0;
11952
11953 rtnl_lock();
11954 if (netif_running(dev)) {
11955 netif_device_detach(dev);
11956 rc = bnxt_close(dev);
11957 }
11958 bnxt_hwrm_func_drv_unrgtr(bp);
11959 rtnl_unlock();
11960 return rc;
11961 }
11962
11963 static int bnxt_resume(struct device *device)
11964 {
11965 struct net_device *dev = dev_get_drvdata(device);
11966 struct bnxt *bp = netdev_priv(dev);
11967 int rc = 0;
11968
11969 rtnl_lock();
11970 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
11971 rc = -ENODEV;
11972 goto resume_exit;
11973 }
11974 rc = bnxt_hwrm_func_reset(bp);
11975 if (rc) {
11976 rc = -EBUSY;
11977 goto resume_exit;
11978 }
11979 bnxt_get_wol_settings(bp);
11980 if (netif_running(dev)) {
11981 rc = bnxt_open(dev);
11982 if (!rc)
11983 netif_device_attach(dev);
11984 }
11985
11986 resume_exit:
11987 rtnl_unlock();
11988 return rc;
11989 }
11990
11991 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
11992 #define BNXT_PM_OPS (&bnxt_pm_ops)
11993
11994 #else
11995
11996 #define BNXT_PM_OPS NULL
11997
11998 #endif
11999
12000
12001
12002
12003
12004
12005
12006
12007
12008 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
12009 pci_channel_state_t state)
12010 {
12011 struct net_device *netdev = pci_get_drvdata(pdev);
12012 struct bnxt *bp = netdev_priv(netdev);
12013
12014 netdev_info(netdev, "PCI I/O error detected\n");
12015
12016 rtnl_lock();
12017 netif_device_detach(netdev);
12018
12019 bnxt_ulp_stop(bp);
12020
12021 if (state == pci_channel_io_perm_failure) {
12022 rtnl_unlock();
12023 return PCI_ERS_RESULT_DISCONNECT;
12024 }
12025
12026 if (netif_running(netdev))
12027 bnxt_close(netdev);
12028
12029 pci_disable_device(pdev);
12030 rtnl_unlock();
12031
12032
12033 return PCI_ERS_RESULT_NEED_RESET;
12034 }
12035
12036
12037
12038
12039
12040
12041
12042
12043
12044
12045 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
12046 {
12047 struct net_device *netdev = pci_get_drvdata(pdev);
12048 struct bnxt *bp = netdev_priv(netdev);
12049 int err = 0;
12050 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
12051
12052 netdev_info(bp->dev, "PCI Slot Reset\n");
12053
12054 rtnl_lock();
12055
12056 if (pci_enable_device(pdev)) {
12057 dev_err(&pdev->dev,
12058 "Cannot re-enable PCI device after reset.\n");
12059 } else {
12060 pci_set_master(pdev);
12061
12062 err = bnxt_hwrm_func_reset(bp);
12063 if (!err && netif_running(netdev))
12064 err = bnxt_open(netdev);
12065
12066 if (!err) {
12067 result = PCI_ERS_RESULT_RECOVERED;
12068 bnxt_ulp_start(bp);
12069 }
12070 }
12071
12072 if (result != PCI_ERS_RESULT_RECOVERED) {
12073 if (netif_running(netdev))
12074 dev_close(netdev);
12075 pci_disable_device(pdev);
12076 }
12077
12078 rtnl_unlock();
12079
12080 return result;
12081 }
12082
12083
12084
12085
12086
12087
12088
12089
12090 static void bnxt_io_resume(struct pci_dev *pdev)
12091 {
12092 struct net_device *netdev = pci_get_drvdata(pdev);
12093
12094 rtnl_lock();
12095
12096 netif_device_attach(netdev);
12097
12098 rtnl_unlock();
12099 }
12100
12101 static const struct pci_error_handlers bnxt_err_handler = {
12102 .error_detected = bnxt_io_error_detected,
12103 .slot_reset = bnxt_io_slot_reset,
12104 .resume = bnxt_io_resume
12105 };
12106
12107 static struct pci_driver bnxt_pci_driver = {
12108 .name = DRV_MODULE_NAME,
12109 .id_table = bnxt_pci_tbl,
12110 .probe = bnxt_init_one,
12111 .remove = bnxt_remove_one,
12112 .shutdown = bnxt_shutdown,
12113 .driver.pm = BNXT_PM_OPS,
12114 .err_handler = &bnxt_err_handler,
12115 #if defined(CONFIG_BNXT_SRIOV)
12116 .sriov_configure = bnxt_sriov_configure,
12117 #endif
12118 };
12119
12120 static int __init bnxt_init(void)
12121 {
12122 bnxt_debug_init();
12123 return pci_register_driver(&bnxt_pci_driver);
12124 }
12125
12126 static void __exit bnxt_exit(void)
12127 {
12128 pci_unregister_driver(&bnxt_pci_driver);
12129 if (bnxt_pf_wq)
12130 destroy_workqueue(bnxt_pf_wq);
12131 bnxt_debug_exit();
12132 }
12133
12134 module_init(bnxt_init);
12135 module_exit(bnxt_exit);