1 /* bnx2x_reg.h: Qlogic Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
11 * The registers description starts with the register Access type followed
12 * by size in bits. For example [RW 32]. The access types are:
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
19 * read/write in consecutive 32 bits accesses
20 * WR - Write Clear (write 1 to clear the bit)
21 *
22 */
23 #ifndef BNX2X_REG_H
24 #define BNX2X_REG_H
25
26 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
27 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
30 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
31 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
33 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
34 /* [R 1] ATC initialization done */
35 #define ATC_REG_ATC_INIT_DONE 0x1100bc
36 /* [RC 6] Interrupt register #0 read clear */
37 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
38 /* [RW 5] Parity mask register #0 read/write */
39 #define ATC_REG_ATC_PRTY_MASK 0x1101d8
40 /* [R 5] Parity register #0 read */
41 #define ATC_REG_ATC_PRTY_STS 0x1101cc
42 /* [RC 5] Parity register #0 read clear */
43 #define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0
44 /* [RW 19] Interrupt mask register #0 read/write */
45 #define BRB1_REG_BRB1_INT_MASK 0x60128
46 /* [R 19] Interrupt register #0 read */
47 #define BRB1_REG_BRB1_INT_STS 0x6011c
48 /* [RW 4] Parity mask register #0 read/write */
49 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
50 /* [R 4] Parity register #0 read */
51 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
52 /* [RC 4] Parity register #0 read clear */
53 #define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
54 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
55 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
57 * following reset the first rbc access to this reg must be write; there can
58 * be no more rbc writes after the first one; there can be any number of rbc
59 * read following the first write; rbc access not following these rules will
60 * result in hang condition. */
61 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
62 /* [RW 10] The number of free blocks below which the full signal to class 0
63 * is asserted */
64 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
65 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230
66 /* [RW 11] The number of free blocks above which the full signal to class 0
67 * is de-asserted */
68 #define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
69 #define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234
70 /* [RW 11] The number of free blocks below which the full signal to class 1
71 * is asserted */
72 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
73 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238
74 /* [RW 11] The number of free blocks above which the full signal to class 1
75 * is de-asserted */
76 #define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
77 #define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c
78 /* [RW 11] The number of free blocks below which the full signal to the LB
79 * port is asserted */
80 #define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
81 /* [RW 10] The number of free blocks above which the full signal to the LB
82 * port is de-asserted */
83 #define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4
84 /* [RW 10] The number of free blocks above which the High_llfc signal to
85 interface #n is de-asserted. */
86 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
87 /* [RW 10] The number of free blocks below which the High_llfc signal to
88 interface #n is asserted. */
89 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
90 /* [RW 11] The number of blocks guarantied for the LB port */
91 #define BRB1_REG_LB_GUARANTIED 0x601ec
92 /* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
93 * before signaling XON. */
94 #define BRB1_REG_LB_GUARANTIED_HYST 0x60264
95 /* [RW 24] LL RAM data. */
96 #define BRB1_REG_LL_RAM 0x61000
97 /* [RW 10] The number of free blocks above which the Low_llfc signal to
98 interface #n is de-asserted. */
99 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
100 /* [RW 10] The number of free blocks below which the Low_llfc signal to
101 interface #n is asserted. */
102 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
103 /* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
104 * register is applicable only when per_class_guaranty_mode is set. */
105 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244
106 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
107 * 1 before signaling XON. The register is applicable only when
108 * per_class_guaranty_mode is set. */
109 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254
110 /* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
111 * register is applicable only when per_class_guaranty_mode is set. */
112 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248
113 /* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
114 * before signaling XON. The register is applicable only when
115 * per_class_guaranty_mode is set. */
116 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258
117 /* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
118 * is applicable only when per_class_guaranty_mode is set. */
119 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c
120 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
121 * 1 before signaling XON. The register is applicable only when
122 * per_class_guaranty_mode is set. */
123 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c
124 /* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
125 * register is applicable only when per_class_guaranty_mode is set. */
126 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250
127 /* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
128 * 1 before signaling XON. The register is applicable only when
129 * per_class_guaranty_mode is set. */
130 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260
131 /* [RW 11] The number of blocks guarantied for the MAC port. The register is
132 * applicable only when per_class_guaranty_mode is reset. */
133 #define BRB1_REG_MAC_GUARANTIED_0 0x601e8
134 #define BRB1_REG_MAC_GUARANTIED_1 0x60240
135 /* [R 24] The number of full blocks. */
136 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
137 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
138 was asserted. */
139 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
140 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
141 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
142 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
143 asserted. */
144 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
145 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
146 /* [RW 10] The number of free blocks below which the pause signal to class 0
147 * is asserted */
148 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
149 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220
150 /* [RW 11] The number of free blocks above which the pause signal to class 0
151 * is de-asserted */
152 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
153 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224
154 /* [RW 11] The number of free blocks below which the pause signal to class 1
155 * is asserted */
156 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
157 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228
158 /* [RW 11] The number of free blocks above which the pause signal to class 1
159 * is de-asserted */
160 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
161 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c
162 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
163 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
164 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
165 /* [RW 10] Write client 0: Assert pause threshold. */
166 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
167 /* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC
168 * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC
169 * mode). 1=per-class guaranty mode (new mode). */
170 #define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268
171 /* [R 24] The number of full blocks occpied by port. */
172 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
173 /* [RW 1] Reset the design by software. */
174 #define BRB1_REG_SOFT_RESET 0x600dc
175 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
176 #define CCM_REG_CAM_OCCUP 0xd0188
177 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
178 acknowledge output is deasserted; all other signals are treated as usual;
179 if 1 - normal activity. */
180 #define CCM_REG_CCM_CFC_IFEN 0xd003c
181 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
182 disregarded; valid is deasserted; all other signals are treated as usual;
183 if 1 - normal activity. */
184 #define CCM_REG_CCM_CQM_IFEN 0xd000c
185 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
186 Otherwise 0 is inserted. */
187 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
188 /* [RW 11] Interrupt mask register #0 read/write */
189 #define CCM_REG_CCM_INT_MASK 0xd01e4
190 /* [R 11] Interrupt register #0 read */
191 #define CCM_REG_CCM_INT_STS 0xd01d8
192 /* [RW 27] Parity mask register #0 read/write */
193 #define CCM_REG_CCM_PRTY_MASK 0xd01f4
194 /* [R 27] Parity register #0 read */
195 #define CCM_REG_CCM_PRTY_STS 0xd01e8
196 /* [RC 27] Parity register #0 read clear */
197 #define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
198 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
199 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
200 Is used to determine the number of the AG context REG-pairs written back;
201 when the input message Reg1WbFlg isn't set. */
202 #define CCM_REG_CCM_REG0_SZ 0xd00c4
203 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
204 disregarded; valid is deasserted; all other signals are treated as usual;
205 if 1 - normal activity. */
206 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
207 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
208 disregarded; valid is deasserted; all other signals are treated as usual;
209 if 1 - normal activity. */
210 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
211 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
212 disregarded; valid output is deasserted; all other signals are treated as
213 usual; if 1 - normal activity. */
214 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
215 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
216 are disregarded; all other signals are treated as usual; if 1 - normal
217 activity. */
218 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
219 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
220 disregarded; valid output is deasserted; all other signals are treated as
221 usual; if 1 - normal activity. */
222 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
223 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
224 input is disregarded; all other signals are treated as usual; if 1 -
225 normal activity. */
226 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
227 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
228 the initial credit value; read returns the current value of the credit
229 counter. Must be initialized to 1 at start-up. */
230 #define CCM_REG_CFC_INIT_CRD 0xd0204
231 /* [RW 2] Auxiliary counter flag Q number 1. */
232 #define CCM_REG_CNT_AUX1_Q 0xd00c8
233 /* [RW 2] Auxiliary counter flag Q number 2. */
234 #define CCM_REG_CNT_AUX2_Q 0xd00cc
235 /* [RW 28] The CM header value for QM request (primary). */
236 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
237 /* [RW 28] The CM header value for QM request (secondary). */
238 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
239 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
240 acknowledge output is deasserted; all other signals are treated as usual;
241 if 1 - normal activity. */
242 #define CCM_REG_CQM_CCM_IFEN 0xd0014
243 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
244 the initial credit value; read returns the current value of the credit
245 counter. Must be initialized to 32 at start-up. */
246 #define CCM_REG_CQM_INIT_CRD 0xd020c
247 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
248 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
249 prioritised); 2 stands for weight 2; tc. */
250 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
251 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
252 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
253 prioritised); 2 stands for weight 2; tc. */
254 #define CCM_REG_CQM_S_WEIGHT 0xd00bc
255 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
256 acknowledge output is deasserted; all other signals are treated as usual;
257 if 1 - normal activity. */
258 #define CCM_REG_CSDM_IFEN 0xd0018
259 /* [RC 1] Set when the message length mismatch (relative to last indication)
260 at the SDM interface is detected. */
261 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
262 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
263 weight 8 (the most prioritised); 1 stands for weight 1(least
264 prioritised); 2 stands for weight 2; tc. */
265 #define CCM_REG_CSDM_WEIGHT 0xd00b4
266 /* [RW 28] The CM header for QM formatting in case of an error in the QM
267 inputs. */
268 #define CCM_REG_ERR_CCM_HDR 0xd0094
269 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
270 #define CCM_REG_ERR_EVNT_ID 0xd0098
271 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
272 writes the initial credit value; read returns the current value of the
273 credit counter. Must be initialized to 64 at start-up. */
274 #define CCM_REG_FIC0_INIT_CRD 0xd0210
275 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
276 writes the initial credit value; read returns the current value of the
277 credit counter. Must be initialized to 64 at start-up. */
278 #define CCM_REG_FIC1_INIT_CRD 0xd0214
279 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
280 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
281 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
282 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
283 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
284 #define CCM_REG_GR_ARB_TYPE 0xd015c
285 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
286 highest priority is 3. It is supposed; that the Store channel priority is
287 the compliment to 4 of the rest priorities - Aggregation channel; Load
288 (FIC0) channel and Load (FIC1). */
289 #define CCM_REG_GR_LD0_PR 0xd0164
290 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
291 highest priority is 3. It is supposed; that the Store channel priority is
292 the compliment to 4 of the rest priorities - Aggregation channel; Load
293 (FIC0) channel and Load (FIC1). */
294 #define CCM_REG_GR_LD1_PR 0xd0168
295 /* [RW 2] General flags index. */
296 #define CCM_REG_INV_DONE_Q 0xd0108
297 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
298 context and sent to STORM; for a specific connection type. The double
299 REG-pairs are used in order to align to STORM context row size of 128
300 bits. The offset of these data in the STORM context is always 0. Index
301 _(0..15) stands for the connection type (one of 16). */
302 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
303 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
304 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
305 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
306 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
307 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
308 acknowledge output is deasserted; all other signals are treated as usual;
309 if 1 - normal activity. */
310 #define CCM_REG_PBF_IFEN 0xd0028
311 /* [RC 1] Set when the message length mismatch (relative to last indication)
312 at the pbf interface is detected. */
313 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
314 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
315 weight 8 (the most prioritised); 1 stands for weight 1(least
316 prioritised); 2 stands for weight 2; tc. */
317 #define CCM_REG_PBF_WEIGHT 0xd00ac
318 #define CCM_REG_PHYS_QNUM1_0 0xd0134
319 #define CCM_REG_PHYS_QNUM1_1 0xd0138
320 #define CCM_REG_PHYS_QNUM2_0 0xd013c
321 #define CCM_REG_PHYS_QNUM2_1 0xd0140
322 #define CCM_REG_PHYS_QNUM3_0 0xd0144
323 #define CCM_REG_PHYS_QNUM3_1 0xd0148
324 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
325 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
326 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
327 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
328 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
329 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
330 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
331 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
332 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
333 disregarded; acknowledge output is deasserted; all other signals are
334 treated as usual; if 1 - normal activity. */
335 #define CCM_REG_STORM_CCM_IFEN 0xd0010
336 /* [RC 1] Set when the message length mismatch (relative to last indication)
337 at the STORM interface is detected. */
338 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
339 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
340 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
341 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
342 tc. */
343 #define CCM_REG_STORM_WEIGHT 0xd009c
344 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
345 disregarded; acknowledge output is deasserted; all other signals are
346 treated as usual; if 1 - normal activity. */
347 #define CCM_REG_TSEM_IFEN 0xd001c
348 /* [RC 1] Set when the message length mismatch (relative to last indication)
349 at the tsem interface is detected. */
350 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
351 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
352 weight 8 (the most prioritised); 1 stands for weight 1(least
353 prioritised); 2 stands for weight 2; tc. */
354 #define CCM_REG_TSEM_WEIGHT 0xd00a0
355 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
356 disregarded; acknowledge output is deasserted; all other signals are
357 treated as usual; if 1 - normal activity. */
358 #define CCM_REG_USEM_IFEN 0xd0024
359 /* [RC 1] Set when message length mismatch (relative to last indication) at
360 the usem interface is detected. */
361 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
362 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
363 weight 8 (the most prioritised); 1 stands for weight 1(least
364 prioritised); 2 stands for weight 2; tc. */
365 #define CCM_REG_USEM_WEIGHT 0xd00a8
366 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
367 disregarded; acknowledge output is deasserted; all other signals are
368 treated as usual; if 1 - normal activity. */
369 #define CCM_REG_XSEM_IFEN 0xd0020
370 /* [RC 1] Set when the message length mismatch (relative to last indication)
371 at the xsem interface is detected. */
372 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
373 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
374 weight 8 (the most prioritised); 1 stands for weight 1(least
375 prioritised); 2 stands for weight 2; tc. */
376 #define CCM_REG_XSEM_WEIGHT 0xd00a4
377 /* [RW 19] Indirect access to the descriptor table of the XX protection
378 mechanism. The fields are: [5:0] - message length; [12:6] - message
379 pointer; 18:13] - next pointer. */
380 #define CCM_REG_XX_DESCR_TABLE 0xd0300
381 #define CCM_REG_XX_DESCR_TABLE_SIZE 24
382 /* [R 7] Used to read the value of XX protection Free counter. */
383 #define CCM_REG_XX_FREE 0xd0184
384 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
385 of the Input Stage XX protection buffer by the XX protection pending
386 messages. Max credit available - 127. Write writes the initial credit
387 value; read returns the current value of the credit counter. Must be
388 initialized to maximum XX protected message size - 2 at start-up. */
389 #define CCM_REG_XX_INIT_CRD 0xd0220
390 /* [RW 7] The maximum number of pending messages; which may be stored in XX
391 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
392 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
393 counter. */
394 #define CCM_REG_XX_MSG_NUM 0xd0224
395 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
396 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
397 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
398 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
399 header pointer. */
400 #define CCM_REG_XX_TABLE 0xd0280
401 #define CDU_REG_CDU_CHK_MASK0 0x101000
402 #define CDU_REG_CDU_CHK_MASK1 0x101004
403 #define CDU_REG_CDU_CONTROL0 0x101008
404 #define CDU_REG_CDU_DEBUG 0x101010
405 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
406 /* [RW 7] Interrupt mask register #0 read/write */
407 #define CDU_REG_CDU_INT_MASK 0x10103c
408 /* [R 7] Interrupt register #0 read */
409 #define CDU_REG_CDU_INT_STS 0x101030
410 /* [RW 5] Parity mask register #0 read/write */
411 #define CDU_REG_CDU_PRTY_MASK 0x10104c
412 /* [R 5] Parity register #0 read */
413 #define CDU_REG_CDU_PRTY_STS 0x101040
414 /* [RC 5] Parity register #0 read clear */
415 #define CDU_REG_CDU_PRTY_STS_CLR 0x101044
416 /* [RC 32] logging of error data in case of a CDU load error:
417 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
418 ype_error; ctual_active; ctual_compressed_context}; */
419 #define CDU_REG_ERROR_DATA 0x101014
420 /* [WB 216] L1TT ram access. each entry has the following format :
421 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
422 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
423 #define CDU_REG_L1TT 0x101800
424 /* [WB 24] MATT ram access. each entry has the following
425 format:{RegionLength[11:0]; egionOffset[11:0]} */
426 #define CDU_REG_MATT 0x101100
427 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
428 #define CDU_REG_MF_MODE 0x101050
429 /* [R 1] indication the initializing the activity counter by the hardware
430 was done. */
431 #define CFC_REG_AC_INIT_DONE 0x104078
432 /* [RW 13] activity counter ram access */
433 #define CFC_REG_ACTIVITY_COUNTER 0x104400
434 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
435 /* [R 1] indication the initializing the cams by the hardware was done. */
436 #define CFC_REG_CAM_INIT_DONE 0x10407c
437 /* [RW 2] Interrupt mask register #0 read/write */
438 #define CFC_REG_CFC_INT_MASK 0x104108
439 /* [R 2] Interrupt register #0 read */
440 #define CFC_REG_CFC_INT_STS 0x1040fc
441 /* [RC 2] Interrupt register #0 read clear */
442 #define CFC_REG_CFC_INT_STS_CLR 0x104100
443 /* [RW 4] Parity mask register #0 read/write */
444 #define CFC_REG_CFC_PRTY_MASK 0x104118
445 /* [R 4] Parity register #0 read */
446 #define CFC_REG_CFC_PRTY_STS 0x10410c
447 /* [RC 4] Parity register #0 read clear */
448 #define CFC_REG_CFC_PRTY_STS_CLR 0x104110
449 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
450 #define CFC_REG_CID_CAM 0x104800
451 #define CFC_REG_CONTROL0 0x104028
452 #define CFC_REG_DEBUG0 0x104050
453 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
454 vector) whether the cfc should be disabled upon it */
455 #define CFC_REG_DISABLE_ON_ERROR 0x104044
456 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
457 set one of these bits. the bit description can be found in CFC
458 specifications */
459 #define CFC_REG_ERROR_VECTOR 0x10403c
460 /* [WB 93] LCID info ram access */
461 #define CFC_REG_INFO_RAM 0x105000
462 #define CFC_REG_INFO_RAM_SIZE 1024
463 #define CFC_REG_INIT_REG 0x10404c
464 #define CFC_REG_INTERFACES 0x104058
465 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
466 field allows changing the priorities of the weighted-round-robin arbiter
467 which selects which CFC load client should be served next */
468 #define CFC_REG_LCREQ_WEIGHTS 0x104084
469 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
470 #define CFC_REG_LINK_LIST 0x104c00
471 #define CFC_REG_LINK_LIST_SIZE 256
472 /* [R 1] indication the initializing the link list by the hardware was done. */
473 #define CFC_REG_LL_INIT_DONE 0x104074
474 /* [R 9] Number of allocated LCIDs which are at empty state */
475 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
476 /* [R 9] Number of Arriving LCIDs in Link List Block */
477 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
478 #define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
479 /* [R 9] Number of Leaving LCIDs in Link List Block */
480 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
481 #define CFC_REG_WEAK_ENABLE_PF 0x104124
482 /* [RW 8] The event id for aggregated interrupt 0 */
483 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
484 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
485 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
486 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
487 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c
488 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
489 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
490 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
491 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
492 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
493 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
494 #define CSDM_REG_AGG_INT_EVENT_5 0xc204c
495 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050
496 #define CSDM_REG_AGG_INT_EVENT_7 0xc2054
497 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058
498 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c
499 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
500 or auto-mask-mode (1) */
501 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0
502 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4
503 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8
504 #define CSDM_REG_AGG_INT_MODE_13 0xc21ec
505 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0
506 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4
507 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8
508 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0
509 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4
510 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8
511 #define CSDM_REG_AGG_INT_MODE_9 0xc21dc
512 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
513 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
514 /* [RW 16] The maximum value of the completion counter #0 */
515 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
516 /* [RW 16] The maximum value of the completion counter #1 */
517 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
518 /* [RW 16] The maximum value of the completion counter #2 */
519 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
520 /* [RW 16] The maximum value of the completion counter #3 */
521 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
522 /* [RW 13] The start address in the internal RAM for the completion
523 counters. */
524 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
525 /* [RW 32] Interrupt mask register #0 read/write */
526 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
527 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
528 /* [R 32] Interrupt register #0 read */
529 #define CSDM_REG_CSDM_INT_STS_0 0xc2290
530 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0
531 /* [RW 11] Parity mask register #0 read/write */
532 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
533 /* [R 11] Parity register #0 read */
534 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
535 /* [RC 11] Parity register #0 read clear */
536 #define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
537 #define CSDM_REG_ENABLE_IN1 0xc2238
538 #define CSDM_REG_ENABLE_IN2 0xc223c
539 #define CSDM_REG_ENABLE_OUT1 0xc2240
540 #define CSDM_REG_ENABLE_OUT2 0xc2244
541 /* [RW 4] The initial number of messages that can be sent to the pxp control
542 interface without receiving any ACK. */
543 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
544 /* [ST 32] The number of ACK after placement messages received */
545 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
546 /* [ST 32] The number of packet end messages received from the parser */
547 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
548 /* [ST 32] The number of requests received from the pxp async if */
549 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
550 /* [ST 32] The number of commands received in queue 0 */
551 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
552 /* [ST 32] The number of commands received in queue 10 */
553 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
554 /* [ST 32] The number of commands received in queue 11 */
555 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
556 /* [ST 32] The number of commands received in queue 1 */
557 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
558 /* [ST 32] The number of commands received in queue 3 */
559 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
560 /* [ST 32] The number of commands received in queue 4 */
561 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
562 /* [ST 32] The number of commands received in queue 5 */
563 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
564 /* [ST 32] The number of commands received in queue 6 */
565 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
566 /* [ST 32] The number of commands received in queue 7 */
567 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
568 /* [ST 32] The number of commands received in queue 8 */
569 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
570 /* [ST 32] The number of commands received in queue 9 */
571 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
572 /* [RW 13] The start address in the internal RAM for queue counters */
573 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
574 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
575 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
576 /* [R 1] parser fifo empty in sdm_sync block */
577 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
578 /* [R 1] parser serial fifo empty in sdm_sync block */
579 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
580 /* [RW 32] Tick for timer counter. Applicable only when
581 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
582 #define CSDM_REG_TIMER_TICK 0xc2000
583 /* [RW 5] The number of time_slots in the arbitration cycle */
584 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
585 /* [RW 3] The source that is associated with arbitration element 0. Source
586 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
587 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
588 #define CSEM_REG_ARB_ELEMENT0 0x200020
589 /* [RW 3] The source that is associated with arbitration element 1. Source
590 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
591 sleeping thread with priority 1; 4- sleeping thread with priority 2.
592 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
593 #define CSEM_REG_ARB_ELEMENT1 0x200024
594 /* [RW 3] The source that is associated with arbitration element 2. Source
595 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
596 sleeping thread with priority 1; 4- sleeping thread with priority 2.
597 Could not be equal to register ~csem_registers_arb_element0.arb_element0
598 and ~csem_registers_arb_element1.arb_element1 */
599 #define CSEM_REG_ARB_ELEMENT2 0x200028
600 /* [RW 3] The source that is associated with arbitration element 3. Source
601 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
602 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
603 not be equal to register ~csem_registers_arb_element0.arb_element0 and
604 ~csem_registers_arb_element1.arb_element1 and
605 ~csem_registers_arb_element2.arb_element2 */
606 #define CSEM_REG_ARB_ELEMENT3 0x20002c
607 /* [RW 3] The source that is associated with arbitration element 4. Source
608 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
609 sleeping thread with priority 1; 4- sleeping thread with priority 2.
610 Could not be equal to register ~csem_registers_arb_element0.arb_element0
611 and ~csem_registers_arb_element1.arb_element1 and
612 ~csem_registers_arb_element2.arb_element2 and
613 ~csem_registers_arb_element3.arb_element3 */
614 #define CSEM_REG_ARB_ELEMENT4 0x200030
615 /* [RW 32] Interrupt mask register #0 read/write */
616 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
617 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
618 /* [R 32] Interrupt register #0 read */
619 #define CSEM_REG_CSEM_INT_STS_0 0x200104
620 #define CSEM_REG_CSEM_INT_STS_1 0x200114
621 /* [RW 32] Parity mask register #0 read/write */
622 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
623 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
624 /* [R 32] Parity register #0 read */
625 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
626 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
627 /* [RC 32] Parity register #0 read clear */
628 #define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
629 #define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
630 #define CSEM_REG_ENABLE_IN 0x2000a4
631 #define CSEM_REG_ENABLE_OUT 0x2000a8
632 /* [RW 32] This address space contains all registers and memories that are
633 placed in SEM_FAST block. The SEM_FAST registers are described in
634 appendix B. In order to access the sem_fast registers the base address
635 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
636 #define CSEM_REG_FAST_MEMORY 0x220000
637 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
638 by the microcode */
639 #define CSEM_REG_FIC0_DISABLE 0x200224
640 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
641 by the microcode */
642 #define CSEM_REG_FIC1_DISABLE 0x200234
643 /* [RW 15] Interrupt table Read and write access to it is not possible in
644 the middle of the work */
645 #define CSEM_REG_INT_TABLE 0x200400
646 /* [ST 24] Statistics register. The number of messages that entered through
647 FIC0 */
648 #define CSEM_REG_MSG_NUM_FIC0 0x200000
649 /* [ST 24] Statistics register. The number of messages that entered through
650 FIC1 */
651 #define CSEM_REG_MSG_NUM_FIC1 0x200004
652 /* [ST 24] Statistics register. The number of messages that were sent to
653 FOC0 */
654 #define CSEM_REG_MSG_NUM_FOC0 0x200008
655 /* [ST 24] Statistics register. The number of messages that were sent to
656 FOC1 */
657 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
658 /* [ST 24] Statistics register. The number of messages that were sent to
659 FOC2 */
660 #define CSEM_REG_MSG_NUM_FOC2 0x200010
661 /* [ST 24] Statistics register. The number of messages that were sent to
662 FOC3 */
663 #define CSEM_REG_MSG_NUM_FOC3 0x200014
664 /* [RW 1] Disables input messages from the passive buffer May be updated
665 during run_time by the microcode */
666 #define CSEM_REG_PAS_DISABLE 0x20024c
667 /* [WB 128] Debug only. Passive buffer memory */
668 #define CSEM_REG_PASSIVE_BUFFER 0x202000
669 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
670 #define CSEM_REG_PRAM 0x240000
671 /* [R 16] Valid sleeping threads indication have bit per thread */
672 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
673 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
674 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
675 /* [RW 16] List of free threads . There is a bit per thread. */
676 #define CSEM_REG_THREADS_LIST 0x2002e4
677 /* [RW 3] The arbitration scheme of time_slot 0 */
678 #define CSEM_REG_TS_0_AS 0x200038
679 /* [RW 3] The arbitration scheme of time_slot 10 */
680 #define CSEM_REG_TS_10_AS 0x200060
681 /* [RW 3] The arbitration scheme of time_slot 11 */
682 #define CSEM_REG_TS_11_AS 0x200064
683 /* [RW 3] The arbitration scheme of time_slot 12 */
684 #define CSEM_REG_TS_12_AS 0x200068
685 /* [RW 3] The arbitration scheme of time_slot 13 */
686 #define CSEM_REG_TS_13_AS 0x20006c
687 /* [RW 3] The arbitration scheme of time_slot 14 */
688 #define CSEM_REG_TS_14_AS 0x200070
689 /* [RW 3] The arbitration scheme of time_slot 15 */
690 #define CSEM_REG_TS_15_AS 0x200074
691 /* [RW 3] The arbitration scheme of time_slot 16 */
692 #define CSEM_REG_TS_16_AS 0x200078
693 /* [RW 3] The arbitration scheme of time_slot 17 */
694 #define CSEM_REG_TS_17_AS 0x20007c
695 /* [RW 3] The arbitration scheme of time_slot 18 */
696 #define CSEM_REG_TS_18_AS 0x200080
697 /* [RW 3] The arbitration scheme of time_slot 1 */
698 #define CSEM_REG_TS_1_AS 0x20003c
699 /* [RW 3] The arbitration scheme of time_slot 2 */
700 #define CSEM_REG_TS_2_AS 0x200040
701 /* [RW 3] The arbitration scheme of time_slot 3 */
702 #define CSEM_REG_TS_3_AS 0x200044
703 /* [RW 3] The arbitration scheme of time_slot 4 */
704 #define CSEM_REG_TS_4_AS 0x200048
705 /* [RW 3] The arbitration scheme of time_slot 5 */
706 #define CSEM_REG_TS_5_AS 0x20004c
707 /* [RW 3] The arbitration scheme of time_slot 6 */
708 #define CSEM_REG_TS_6_AS 0x200050
709 /* [RW 3] The arbitration scheme of time_slot 7 */
710 #define CSEM_REG_TS_7_AS 0x200054
711 /* [RW 3] The arbitration scheme of time_slot 8 */
712 #define CSEM_REG_TS_8_AS 0x200058
713 /* [RW 3] The arbitration scheme of time_slot 9 */
714 #define CSEM_REG_TS_9_AS 0x20005c
715 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
716 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
717 #define CSEM_REG_VFPF_ERR_NUM 0x200380
718 /* [RW 1] Parity mask register #0 read/write */
719 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
720 /* [R 1] Parity register #0 read */
721 #define DBG_REG_DBG_PRTY_STS 0xc09c
722 /* [RC 1] Parity register #0 read clear */
723 #define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
724 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
725 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
726 * 4.Completion function=0; 5.Error handling=0 */
727 #define DMAE_REG_BACKWARD_COMP_EN 0x10207c
728 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
729 as 14*X+Y. */
730 #define DMAE_REG_CMD_MEM 0x102400
731 #define DMAE_REG_CMD_MEM_SIZE 224
732 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
733 initial value is all ones. */
734 #define DMAE_REG_CRC16C_INIT 0x10201c
735 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
736 CRC-16 T10 initial value is all ones. */
737 #define DMAE_REG_CRC16T10_INIT 0x102020
738 /* [RW 2] Interrupt mask register #0 read/write */
739 #define DMAE_REG_DMAE_INT_MASK 0x102054
740 /* [RW 4] Parity mask register #0 read/write */
741 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
742 /* [R 4] Parity register #0 read */
743 #define DMAE_REG_DMAE_PRTY_STS 0x102058
744 /* [RC 4] Parity register #0 read clear */
745 #define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
746 /* [RW 1] Command 0 go. */
747 #define DMAE_REG_GO_C0 0x102080
748 /* [RW 1] Command 1 go. */
749 #define DMAE_REG_GO_C1 0x102084
750 /* [RW 1] Command 10 go. */
751 #define DMAE_REG_GO_C10 0x102088
752 /* [RW 1] Command 11 go. */
753 #define DMAE_REG_GO_C11 0x10208c
754 /* [RW 1] Command 12 go. */
755 #define DMAE_REG_GO_C12 0x102090
756 /* [RW 1] Command 13 go. */
757 #define DMAE_REG_GO_C13 0x102094
758 /* [RW 1] Command 14 go. */
759 #define DMAE_REG_GO_C14 0x102098
760 /* [RW 1] Command 15 go. */
761 #define DMAE_REG_GO_C15 0x10209c
762 /* [RW 1] Command 2 go. */
763 #define DMAE_REG_GO_C2 0x1020a0
764 /* [RW 1] Command 3 go. */
765 #define DMAE_REG_GO_C3 0x1020a4
766 /* [RW 1] Command 4 go. */
767 #define DMAE_REG_GO_C4 0x1020a8
768 /* [RW 1] Command 5 go. */
769 #define DMAE_REG_GO_C5 0x1020ac
770 /* [RW 1] Command 6 go. */
771 #define DMAE_REG_GO_C6 0x1020b0
772 /* [RW 1] Command 7 go. */
773 #define DMAE_REG_GO_C7 0x1020b4
774 /* [RW 1] Command 8 go. */
775 #define DMAE_REG_GO_C8 0x1020b8
776 /* [RW 1] Command 9 go. */
777 #define DMAE_REG_GO_C9 0x1020bc
778 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
779 input is disregarded; valid is deasserted; all other signals are treated
780 as usual; if 1 - normal activity. */
781 #define DMAE_REG_GRC_IFEN 0x102008
782 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
783 acknowledge input is disregarded; valid is deasserted; full is asserted;
784 all other signals are treated as usual; if 1 - normal activity. */
785 #define DMAE_REG_PCI_IFEN 0x102004
786 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
787 initial value to the credit counter; related to the address. Read returns
788 the current value of the counter. */
789 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
790 /* [RW 8] Aggregation command. */
791 #define DORQ_REG_AGG_CMD0 0x170060
792 /* [RW 8] Aggregation command. */
793 #define DORQ_REG_AGG_CMD1 0x170064
794 /* [RW 8] Aggregation command. */
795 #define DORQ_REG_AGG_CMD2 0x170068
796 /* [RW 8] Aggregation command. */
797 #define DORQ_REG_AGG_CMD3 0x17006c
798 /* [RW 28] UCM Header. */
799 #define DORQ_REG_CMHEAD_RX 0x170050
800 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
801 #define DORQ_REG_DB_ADDR0 0x17008c
802 /* [RW 5] Interrupt mask register #0 read/write */
803 #define DORQ_REG_DORQ_INT_MASK 0x170180
804 /* [R 5] Interrupt register #0 read */
805 #define DORQ_REG_DORQ_INT_STS 0x170174
806 /* [RC 5] Interrupt register #0 read clear */
807 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
808 /* [RW 2] Parity mask register #0 read/write */
809 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
810 /* [R 2] Parity register #0 read */
811 #define DORQ_REG_DORQ_PRTY_STS 0x170184
812 /* [RC 2] Parity register #0 read clear */
813 #define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
814 /* [RW 8] The address to write the DPM CID to STORM. */
815 #define DORQ_REG_DPM_CID_ADDR 0x170044
816 /* [RW 5] The DPM mode CID extraction offset. */
817 #define DORQ_REG_DPM_CID_OFST 0x170030
818 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
819 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
820 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
821 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
822 /* [R 13] Current value of the DQ FIFO fill level according to following
823 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
824 doorbell. */
825 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
826 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
827 equal to full threshold; reset on full clear. */
828 #define DORQ_REG_DQ_FULL_ST 0x1700c0
829 /* [RW 28] The value sent to CM header in the case of CFC load error. */
830 #define DORQ_REG_ERR_CMHEAD 0x170058
831 #define DORQ_REG_IF_EN 0x170004
832 #define DORQ_REG_MAX_RVFID_SIZE 0x1701ec
833 #define DORQ_REG_MODE_ACT 0x170008
834 /* [RW 5] The normal mode CID extraction offset. */
835 #define DORQ_REG_NORM_CID_OFST 0x17002c
836 /* [RW 28] TCM Header when only TCP context is loaded. */
837 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
838 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
839 Interface. */
840 #define DORQ_REG_OUTST_REQ 0x17003c
841 #define DORQ_REG_PF_USAGE_CNT 0x1701d0
842 #define DORQ_REG_REGN 0x170038
843 /* [R 4] Current value of response A counter credit. Initial credit is
844 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
845 register. */
846 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
847 /* [R 4] Current value of response B counter credit. Initial credit is
848 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
849 register. */
850 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
851 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
852 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
853 read reads this written value. */
854 #define DORQ_REG_RSP_INIT_CRD 0x170048
855 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
856 #define DORQ_REG_VF_NORM_CID_BASE 0x1701a0
857 #define DORQ_REG_VF_NORM_CID_OFST 0x1701f4
858 #define DORQ_REG_VF_NORM_CID_WND_SIZE 0x1701a4
859 #define DORQ_REG_VF_NORM_MAX_CID_COUNT 0x1701e4
860 #define DORQ_REG_VF_NORM_VF_BASE 0x1701a8
861 /* [RW 10] VF type validation mask value */
862 #define DORQ_REG_VF_TYPE_MASK_0 0x170218
863 /* [RW 17] VF type validation Min MCID value */
864 #define DORQ_REG_VF_TYPE_MAX_MCID_0 0x1702d8
865 /* [RW 17] VF type validation Max MCID value */
866 #define DORQ_REG_VF_TYPE_MIN_MCID_0 0x170298
867 /* [RW 10] VF type validation comp value */
868 #define DORQ_REG_VF_TYPE_VALUE_0 0x170258
869 #define DORQ_REG_VF_USAGE_CT_LIMIT 0x170340
870
871 /* [RW 4] Initial activity counter value on the load request; when the
872 shortcut is done. */
873 #define DORQ_REG_SHRT_ACT_CNT 0x170070
874 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
875 #define DORQ_REG_SHRT_CMHEAD 0x170054
876 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
877 #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
878 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
879 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
880 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
881 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
882 #define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
883 #define DORQ_REG_VF_USAGE_CNT 0x170320
884 #define HC_REG_AGG_INT_0 0x108050
885 #define HC_REG_AGG_INT_1 0x108054
886 #define HC_REG_ATTN_BIT 0x108120
887 #define HC_REG_ATTN_IDX 0x108100
888 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
889 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
890 #define HC_REG_ATTN_NUM_P0 0x108038
891 #define HC_REG_ATTN_NUM_P1 0x10803c
892 #define HC_REG_COMMAND_REG 0x108180
893 #define HC_REG_CONFIG_0 0x108000
894 #define HC_REG_CONFIG_1 0x108004
895 #define HC_REG_FUNC_NUM_P0 0x1080ac
896 #define HC_REG_FUNC_NUM_P1 0x1080b0
897 /* [RW 3] Parity mask register #0 read/write */
898 #define HC_REG_HC_PRTY_MASK 0x1080a0
899 /* [R 3] Parity register #0 read */
900 #define HC_REG_HC_PRTY_STS 0x108094
901 /* [RC 3] Parity register #0 read clear */
902 #define HC_REG_HC_PRTY_STS_CLR 0x108098
903 #define HC_REG_INT_MASK 0x108108
904 #define HC_REG_LEADING_EDGE_0 0x108040
905 #define HC_REG_LEADING_EDGE_1 0x108048
906 #define HC_REG_MAIN_MEMORY 0x108800
907 #define HC_REG_MAIN_MEMORY_SIZE 152
908 #define HC_REG_P0_PROD_CONS 0x108200
909 #define HC_REG_P1_PROD_CONS 0x108400
910 #define HC_REG_PBA_COMMAND 0x108140
911 #define HC_REG_PCI_CONFIG_0 0x108010
912 #define HC_REG_PCI_CONFIG_1 0x108014
913 #define HC_REG_STATISTIC_COUNTERS 0x109000
914 #define HC_REG_TRAILING_EDGE_0 0x108044
915 #define HC_REG_TRAILING_EDGE_1 0x10804c
916 #define HC_REG_UC_RAM_ADDR_0 0x108028
917 #define HC_REG_UC_RAM_ADDR_1 0x108030
918 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
919 #define HC_REG_VQID_0 0x108008
920 #define HC_REG_VQID_1 0x10800c
921 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
922 #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
923 #define IGU_REG_ATTENTION_ACK_BITS 0x130108
924 /* [R 4] Debug: attn_fsm */
925 #define IGU_REG_ATTN_FSM 0x130054
926 #define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
927 #define IGU_REG_ATTN_MSG_ADDR_L 0x130120
928 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
929 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
930 * write done didn't receive. */
931 #define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
932 #define IGU_REG_BLOCK_CONFIGURATION 0x130000
933 #define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
934 #define IGU_REG_COMMAND_REG_CTRL 0x13012c
935 /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
936 * is clear. The bits in this registers are set and clear via the producer
937 * command. Data valid only in addresses 0-4. all the rest are zero. */
938 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
939 /* [R 5] Debug: ctrl_fsm */
940 #define IGU_REG_CTRL_FSM 0x130064
941 /* [R 1] data available for error memory. If this bit is clear do not red
942 * from error_handling_memory. */
943 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
944 /* [RW 11] Parity mask register #0 read/write */
945 #define IGU_REG_IGU_PRTY_MASK 0x1300a8
946 /* [R 11] Parity register #0 read */
947 #define IGU_REG_IGU_PRTY_STS 0x13009c
948 /* [RC 11] Parity register #0 read clear */
949 #define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
950 /* [R 4] Debug: int_handle_fsm */
951 #define IGU_REG_INT_HANDLE_FSM 0x130050
952 #define IGU_REG_LEADING_EDGE_LATCH 0x130134
953 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
954 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
955 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
956 #define IGU_REG_MAPPING_MEMORY 0x131000
957 #define IGU_REG_MAPPING_MEMORY_SIZE 136
958 #define IGU_REG_PBA_STATUS_LSB 0x130138
959 #define IGU_REG_PBA_STATUS_MSB 0x13013c
960 #define IGU_REG_PCI_PF_MSI_EN 0x130140
961 #define IGU_REG_PCI_PF_MSIX_EN 0x130144
962 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
963 /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
964 * pending; 1 = pending. Pendings means interrupt was asserted; and write
965 * done was not received. Data valid only in addresses 0-4. all the rest are
966 * zero. */
967 #define IGU_REG_PENDING_BITS_STATUS 0x130300
968 #define IGU_REG_PF_CONFIGURATION 0x130154
969 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
970 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
971 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
972 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
973 * - In backward compatible mode; for non default SB; each even line in the
974 * memory holds the U producer and each odd line hold the C producer. The
975 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
976 * last 20 producers are for the DSB for each PF. each PF has five segments
977 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
978 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
979 #define IGU_REG_PROD_CONS_MEMORY 0x132000
980 /* [R 3] Debug: pxp_arb_fsm */
981 #define IGU_REG_PXP_ARB_FSM 0x130068
982 /* [RW 6] Write one for each bit will reset the appropriate memory. When the
983 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
984 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
985 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
986 #define IGU_REG_RESET_MEMORIES 0x130158
987 /* [R 4] Debug: sb_ctrl_fsm */
988 #define IGU_REG_SB_CTRL_FSM 0x13004c
989 #define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
990 #define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
991 #define IGU_REG_SB_MASK_LSB 0x130164
992 #define IGU_REG_SB_MASK_MSB 0x130168
993 /* [RW 16] Number of command that were dropped without causing an interrupt
994 * due to: read access for WO BAR address; or write access for RO BAR
995 * address or any access for reserved address or PCI function error is set
996 * and address is not MSIX; PBA or cleanup */
997 #define IGU_REG_SILENT_DROP 0x13016c
998 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
999 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
1000 * PF; 68-71 number of ATTN messages per PF */
1001 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
1002 /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
1003 * timer mask command arrives. Value must be bigger than 100. */
1004 #define IGU_REG_TIMER_MASKING_VALUE 0x13003c
1005 #define IGU_REG_TRAILING_EDGE_LATCH 0x130104
1006 #define IGU_REG_VF_CONFIGURATION 0x130170
1007 /* [WB_R 32] Each bit represent write done pending bits status for that SB
1008 * (MSI/MSIX message was sent and write done was not received yet). 0 =
1009 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
1010 #define IGU_REG_WRITE_DONE_PENDING 0x130480
1011 #define MCP_A_REG_MCPR_SCRATCH 0x3a0000
1012 #define MCP_REG_MCPR_ACCESS_LOCK 0x8009c
1013 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
1014 #define MCP_REG_MCPR_GP_INPUTS 0x800c0
1015 #define MCP_REG_MCPR_GP_OENABLE 0x800c8
1016 #define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
1017 #define MCP_REG_MCPR_IMC_COMMAND 0x85900
1018 #define MCP_REG_MCPR_IMC_DATAREG0 0x85920
1019 #define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
1020 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
1021 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
1022 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
1023 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
1024 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
1025 #define MCP_REG_MCPR_NVM_READ 0x86410
1026 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
1027 #define MCP_REG_MCPR_NVM_WRITE 0x86408
1028 #define MCP_REG_MCPR_SCRATCH 0xa0000
1029 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
1030 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
1031 /* [R 32] read first 32 bit after inversion of function 0. mapped as
1032 follows: [0] NIG attention for function0; [1] NIG attention for
1033 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
1034 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
1035 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
1036 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
1037 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
1038 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
1039 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
1040 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
1041 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
1042 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
1043 Parity error; [31] PBF Hw interrupt; */
1044 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
1045 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
1046 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
1047 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1048 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1049 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1050 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1051 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1052 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1053 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1054 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1055 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1056 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1057 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1058 interrupt; */
1059 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
1060 /* [R 32] read second 32 bit after inversion of function 0. mapped as
1061 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1062 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1063 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1064 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1065 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1066 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1067 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1068 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1069 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1070 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1071 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1072 interrupt; */
1073 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
1074 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
1075 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
1076 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
1077 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
1078 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
1079 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1080 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1081 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1082 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1083 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1084 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1085 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1086 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1087 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
1088 /* [R 32] read third 32 bit after inversion of function 0. mapped as
1089 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
1090 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
1091 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1092 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1093 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1094 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1095 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1096 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1097 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1098 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1099 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1100 attn1; */
1101 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
1102 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
1103 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
1104 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
1105 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
1106 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
1107 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
1108 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
1109 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
1110 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
1111 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1112 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1113 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1114 timers attn_4 func1; [30] General attn0; [31] General attn1; */
1115 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
1116 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1117 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1118 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1119 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1120 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1121 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1122 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1123 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1124 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1125 Latched timeout attention; [27] GRC Latched reserved access attention;
1126 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1127 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1128 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
1129 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
1130 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1131 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1132 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
1133 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
1134 General attn13; [12] General attn14; [13] General attn15; [14] General
1135 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
1136 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
1137 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
1138 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
1139 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1140 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
1141 ump_tx_parity; [31] MCP Latched scpad_parity; */
1142 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
1143 /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1144 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1145 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1146 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1147 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
1148 /* [W 14] write to this register results with the clear of the latched
1149 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
1150 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
1151 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1152 GRC Latched reserved access attention; one in d7 clears Latched
1153 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
1154 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
1155 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
1156 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
1157 from this register return zero */
1158 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
1159 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1160 as follows: [0] NIG attention for function0; [1] NIG attention for
1161 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1162 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1163 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1164 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1165 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1166 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1167 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1168 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1169 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1170 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1171 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1172 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
1173 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
1174 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
1175 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
1176 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
1177 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
1178 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
1179 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1180 as follows: [0] NIG attention for function0; [1] NIG attention for
1181 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1182 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1183 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1184 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1185 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1186 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
1187 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1188 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1189 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1190 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1191 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1192 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
1193 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
1194 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
1195 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
1196 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
1197 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
1198 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
1199 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1200 as follows: [0] NIG attention for function0; [1] NIG attention for
1201 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1202 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1203 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1204 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1205 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1206 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1207 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1208 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1209 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1210 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1211 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1212 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
1213 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
1214 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1215 as follows: [0] NIG attention for function0; [1] NIG attention for
1216 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1217 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1218 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1219 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1220 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1221 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1222 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1223 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1224 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1225 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1226 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1227 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
1228 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
1229 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1230 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1231 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1232 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1233 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1234 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1235 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1236 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1237 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1238 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1239 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1240 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1241 interrupt; */
1242 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1243 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1244 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1245 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1246 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1247 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1248 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1249 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1250 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1251 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1252 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1253 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1254 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1255 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1256 interrupt; */
1257 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1258 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1259 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1260 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1261 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1262 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1263 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1264 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1265 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1266 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1267 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1268 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1269 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1270 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1271 interrupt; */
1272 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1273 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1274 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1275 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1276 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1277 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1278 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1279 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1280 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1281 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1282 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1283 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1284 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1285 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1286 interrupt; */
1287 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1288 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1289 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1290 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1291 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1292 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1293 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1294 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1295 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1296 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1297 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1298 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1299 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1300 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1301 attn1; */
1302 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1303 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1304 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1305 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1306 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1307 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1308 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1309 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1310 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1311 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1312 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1313 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1314 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1315 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1316 attn1; */
1317 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1318 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1319 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1320 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1321 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1322 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1323 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1324 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1325 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1326 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1327 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1328 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1329 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1330 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1331 attn1; */
1332 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1333 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1334 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1335 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1336 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1337 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1338 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1339 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1340 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1341 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1342 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1343 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1344 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1345 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1346 attn1; */
1347 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1348 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1349 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1350 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1351 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1352 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1353 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1354 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1355 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1356 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1357 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1358 Latched timeout attention; [27] GRC Latched reserved access attention;
1359 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1360 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1361 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1362 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1363 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1364 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1365 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1366 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1367 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1368 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1369 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1370 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1371 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1372 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1373 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1374 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1375 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1376 Latched timeout attention; [27] GRC Latched reserved access attention;
1377 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1378 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1379 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1380 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1381 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1382 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1383 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1384 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1385 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1386 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1387 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1388 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1389 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1390 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1391 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1392 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1393 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1394 Latched timeout attention; [27] GRC Latched reserved access attention;
1395 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1396 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1397 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1398 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1399 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1400 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1401 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1402 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1403 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1404 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1405 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1406 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1407 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1408 Latched timeout attention; [27] GRC Latched reserved access attention;
1409 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1410 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1411 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1412 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1413 /* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
1414 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1415 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1416 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1417 * parity; [31-10] Reserved; */
1418 #define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688
1419 /* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
1420 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1421 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1422 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1423 * parity; [31-10] Reserved; */
1424 #define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0
1425 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1426 128 bit vector */
1427 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1428 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1429 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1430 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1431 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1432 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1433 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1434 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1435 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1436 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1437 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1438 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1439 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1440 #define MISC_REG_AEU_GENERAL_MASK 0xa61c
1441 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1442 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1443 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1444 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1445 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1446 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1447 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1448 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1449 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1450 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1451 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1452 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1453 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1454 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1455 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1456 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1457 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1458 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1459 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1460 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1461 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1462 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1463 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1464 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1465 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1466 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1467 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1468 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1469 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1470 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1471 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1472 [9:8] = raserved. Zero = mask; one = unmask */
1473 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1474 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1475 /* [RW 1] If set a system kill occurred */
1476 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1477 /* [RW 32] Represent the status of the input vector to the AEU when a system
1478 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1479 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1480 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1481 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1482 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1483 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1484 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1485 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1486 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1487 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1488 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1489 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1490 interrupt; */
1491 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1492 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1493 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1494 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1495 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1496 Port. */
1497 #define MISC_REG_BOND_ID 0xa400
1498 /* [R 16] These bits indicate the part number for the chip. */
1499 #define MISC_REG_CHIP_NUM 0xa408
1500 /* [R 4] These bits indicate the base revision of the chip. This value
1501 starts at 0x0 for the A0 tape-out and increments by one for each
1502 all-layer tape-out. */
1503 #define MISC_REG_CHIP_REV 0xa40c
1504 /* [R 14] otp_misc_do[100:0] spare bits collection: 13:11-
1505 * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72];
1506 * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */
1507 #define MISC_REG_CHIP_TYPE 0xac60
1508 #define MISC_REG_CHIP_TYPE_57811_MASK (1<<1)
1509 #define MISC_REG_CPMU_LP_DR_ENABLE 0xa858
1510 /* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled
1511 * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk
1512 * 25MHz. Reset on hard reset. */
1513 #define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84c
1514 /* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI
1515 * counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset. */
1516 #define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a0
1517 /* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that
1518 * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM
1519 * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that
1520 * the FW command that all Queues are empty is disabled. When 0 indicates
1521 * that the FW command that all Queues are empty is enabled. [2] - FW Early
1522 * Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early
1523 * Exit command is disabled. When 0 indicates that the FW Early Exit command
1524 * is enabled. This bit applicable only in the EXIT Events Mask registers.
1525 * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication
1526 * is disabled. When 0 indicates that the PBF Request indication is enabled.
1527 * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF
1528 * Request indication is disabled. When 0 indicates that the Tx Other Than
1529 * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1
1530 * indicates that the RX EEE LPI Status indication is disabled. When 0
1531 * indicates that the RX EEE LPI Status indication is enabled. In the EXIT
1532 * Events Masks registers; this bit masks the falling edge detect of the LPI
1533 * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that
1534 * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause
1535 * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the
1536 * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY
1537 * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM
1538 * IDLE indication is disabled. When 0 indicates that the QM IDLE indication
1539 * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When
1540 * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0
1541 * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1
1542 * Status Mask. When 1 indicates that the L1 Status indication from the PCIE
1543 * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication
1544 * from the PCIE CORE is enabled. In the EXIT Events Masks registers; this
1545 * bit masks the falling edge detect of the L1 status (L1 is on - off). [11]
1546 * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE
1547 * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI
1548 * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1
1549 * indicates that the P0 EEE LPI REQ indication is disabled. When =0
1550 * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE
1551 * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is
1552 * disabled. When =0 indicates that the P0 EEE LPI REQ indication is
1553 * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
1554 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
1555 * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1
1556 * REQ indication is disabled. When =0 indicates that the L1 indication is
1557 * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates
1558 * that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx
1559 * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status
1560 * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This
1561 * bit is applicable only in the EXIT Events Masks registers. [17] - L1
1562 * Status Edge Detect Mask. When =1 indicates that the L1 Status Falling
1563 * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off).
1564 * When =0 indicates that the L1 Status Falling Edge Detect indication from
1565 * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in
1566 * the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset. */
1567 #define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa880
1568 /* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates
1569 * that the Vmain SM end state is disabled. When 0 indicates that the Vmain
1570 * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates
1571 * that the FW command that all Queues are empty is disabled. When 0
1572 * indicates that the FW command that all Queues are empty is enabled. [2] -
1573 * FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW
1574 * Early Exit command is disabled. When 0 indicates that the FW Early Exit
1575 * command is enabled. This bit applicable only in the EXIT Events Mask
1576 * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request
1577 * indication is disabled. When 0 indicates that the PBF Request indication
1578 * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other
1579 * Than PBF Request indication is disabled. When 0 indicates that the Tx
1580 * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status
1581 * Mask. When 1 indicates that the RX EEE LPI Status indication is disabled.
1582 * When 0 indicates that the RX LPI Status indication is enabled. In the
1583 * EXIT Events Masks registers; this bit masks the falling edge detect of
1584 * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1
1585 * indicates that the Tx Pause indication is disabled. When 0 indicates that
1586 * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1
1587 * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates
1588 * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1
1589 * indicates that the QM IDLE indication is disabled. When 0 indicates that
1590 * the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9]
1591 * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for
1592 * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for
1593 * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1
1594 * Status indication from the PCIE CORE is disabled. When 0 indicates that
1595 * the RX EEE LPI Status indication from the PCIE CORE is enabled. In the
1596 * EXIT Events Masks registers; this bit masks the falling edge detect of
1597 * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When
1598 * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When
1599 * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1
1600 * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication
1601 * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is
1602 * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
1603 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
1604 * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates
1605 * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that
1606 * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1
1607 * indicates that the L1 REQ indication is disabled. When =0 indicates that
1608 * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask.
1609 * When =1 indicates that the RX EEE LPI Status Falling Edge Detect
1610 * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that
1611 * the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE
1612 * LPI is on - off). This bit is applicable only in the EXIT Events Masks
1613 * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the
1614 * L1 Status Falling Edge Detect indication from the PCIE CORE is disabled
1615 * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge
1616 * Detect indication from the PCIE CORE is enabled (L1 is on - off). This
1617 * bit is applicable only in the EXIT Events Masks registers.Clock 25MHz.
1618 * Reset on hard reset. */
1619 #define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa888
1620 /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
1621 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
1622 * register. Reset on hard reset. */
1623 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8
1624 /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
1625 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
1626 * register. Reset on hard reset. */
1627 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc
1628 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1629 32 clients. Each client can be controlled by one driver only. One in each
1630 bit represent that this driver control the appropriate client (Ex: bit 5
1631 is set means this driver control client number 5). addr1 = set; addr0 =
1632 clear; read from both addresses will give the same result = status. write
1633 to address 1 will set a request to control all the clients that their
1634 appropriate bit (in the write command) is set. if the client is free (the
1635 appropriate bit in all the other drivers is clear) one will be written to
1636 that driver register; if the client isn't free the bit will remain zero.
1637 if the appropriate bit is set (the driver request to gain control on a
1638 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1639 interrupt will be asserted). write to address 0 will set a request to
1640 free all the clients that their appropriate bit (in the write command) is
1641 set. if the appropriate bit is clear (the driver request to free a client
1642 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1643 be asserted). */
1644 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1645 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1646 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1647 only. */
1648 #define MISC_REG_E1HMF_MODE 0xa5f8
1649 /* [R 1] Status of four port mode path swap input pin. */
1650 #define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
1651 /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1652 the path_swap output is equal to 4 port mode path swap input pin; if it
1653 is 1 - the path_swap output is equal to bit[1] of this register; [1] -
1654 Overwrite value. If bit[0] of this register is 1 this is the value that
1655 receives the path_swap output. Reset on Hard reset. */
1656 #define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
1657 /* [R 1] Status of 4 port mode port swap input pin. */
1658 #define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
1659 /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1660 the port_swap output is equal to 4 port mode port swap input pin; if it
1661 is 1 - the port_swap output is equal to bit[1] of this register; [1] -
1662 Overwrite value. If bit[0] of this register is 1 this is the value that
1663 receives the port_swap output. Reset on Hard reset. */
1664 #define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
1665 /* [RW 32] Debug only: spare RW register reset by core reset */
1666 #define MISC_REG_GENERIC_CR_0 0xa460
1667 #define MISC_REG_GENERIC_CR_1 0xa464
1668 /* [RW 32] Debug only: spare RW register reset by por reset */
1669 #define MISC_REG_GENERIC_POR_1 0xa474
1670 /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
1671 use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
1672 can not be configured as an output. Each output has its output enable in
1673 the MCP register space; but this bit needs to be set to make use of that.
1674 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
1675 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
1676 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1677 the i/o to an output and will drive the TimeSync output. Bit[31:7]:
1678 spare. Global register. Reset by hard reset. */
1679 #define MISC_REG_GEN_PURP_HWG 0xa9a0
1680 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1681 these bits is written as a '1'; the corresponding SPIO bit will turn off
1682 it's drivers and become an input. This is the reset state of all GPIO
1683 pins. The read value of these bits will be a '1' if that last command
1684 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1685 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1686 as a '1'; the corresponding GPIO bit will drive low. The read value of
1687 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1688 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1689 SET When any of these bits is written as a '1'; the corresponding GPIO
1690 bit will drive high (if it has that capability). The read value of these
1691 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1692 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1693 RO; These bits indicate the read value of each of the eight GPIO pins.
1694 This is the result value of the pin; not the drive value. Writing these
1695 bits will have not effect. */
1696 #define MISC_REG_GPIO 0xa490
1697 /* [RW 8] These bits enable the GPIO_INTs to signals event to the
1698 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1699 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1700 [7] p1_gpio_3; */
1701 #define MISC_REG_GPIO_EVENT_EN 0xa2bc
1702 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1703 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1704 This will acknowledge an interrupt on the falling edge of corresponding
1705 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1706 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1707 register. This will acknowledge an interrupt on the rising edge of
1708 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1709 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1710 value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1711 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1712 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1713 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1714 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1715 current GPIO interrupt state for each GPIO pin. This bit is cleared when
1716 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1717 set when the GPIO input does not match the current value in #OLD_VALUE
1718 (reset value 0). */
1719 #define MISC_REG_GPIO_INT 0xa494
1720 /* [R 28] this field hold the last information that caused reserved
1721 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1722 [27:24] the master that caused the attention - according to the following
1723 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1724 dbu; 8 = dmae */
1725 #define MISC_REG_GRC_RSV_ATTN 0xa3c0
1726 /* [R 28] this field hold the last information that caused timeout
1727 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1728 [27:24] the master that caused the attention - according to the following
1729 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1730 dbu; 8 = dmae */
1731 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1732 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1733 access that does not finish within
1734 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1735 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1736 assert it attention output. */
1737 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1738 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1739 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1740 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1741 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1742 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1743 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1744 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1745 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1746 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1747 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1748 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1749 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1750 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1751 connected to RESET input directly. [15] capRetry_en (reset value 0)
1752 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1753 value 0) bit to continuously monitor vco freq (inverted). [17]
1754 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1755 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1756 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1757 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1758 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1759 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1760 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1761 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1762 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1763 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1764 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1765 register bits. */
1766 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1767 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1768 /* [RW 1] LCPLL power down. Global register. Active High. Reset on POR
1769 * reset. */
1770 #define MISC_REG_LCPLL_E40_PWRDWN 0xaa74
1771 /* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */
1772 #define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78
1773 /* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
1774 * reset. */
1775 #define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c
1776 /* [RW 4] Interrupt mask register #0 read/write */
1777 #define MISC_REG_MISC_INT_MASK 0xa388
1778 /* [RW 1] Parity mask register #0 read/write */
1779 #define MISC_REG_MISC_PRTY_MASK 0xa398
1780 /* [R 1] Parity register #0 read */
1781 #define MISC_REG_MISC_PRTY_STS 0xa38c
1782 /* [RC 1] Parity register #0 read clear */
1783 #define MISC_REG_MISC_PRTY_STS_CLR 0xa390
1784 #define MISC_REG_NIG_WOL_P0 0xa270
1785 #define MISC_REG_NIG_WOL_P1 0xa274
1786 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1787 assertion */
1788 #define MISC_REG_PCIE_HOT_RESET 0xa618
1789 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1790 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1791 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1792 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1793 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1794 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1795 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1796 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1797 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1798 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1799 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1800 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1801 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1802 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1803 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1804 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1805 testa_en (reset value 0); */
1806 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1807 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1808 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1809 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1810 /* [R 1] Status of 4 port mode enable input pin. */
1811 #define MISC_REG_PORT4MODE_EN 0xa750
1812 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1813 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1814 * the port4mode_en output is equal to bit[1] of this register; [1] -
1815 * Overwrite value. If bit[0] of this register is 1 this is the value that
1816 * receives the port4mode_en output . */
1817 #define MISC_REG_PORT4MODE_EN_OVWR 0xa720
1818 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1819 write/read zero = the specific block is in reset; addr 0-wr- the write
1820 value will be written to the register; addr 1-set - one will be written
1821 to all the bits that have the value of one in the data written (bits that
1822 have the value of zero will not be change) ; addr 2-clear - zero will be
1823 written to all the bits that have the value of one in the data written
1824 (bits that have the value of zero will not be change); addr 3-ignore;
1825 read ignore from all addr except addr 00; inside order of the bits is:
1826 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1827 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1828 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1829 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1830 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1831 rst_pxp_rq_rd_wr; 31:17] reserved */
1832 #define MISC_REG_RESET_REG_1 0xa580
1833 #define MISC_REG_RESET_REG_2 0xa590
1834 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1835 shared with the driver resides */
1836 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1837 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1838 the corresponding SPIO bit will turn off it's drivers and become an
1839 input. This is the reset state of all SPIO pins. The read value of these
1840 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1841 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1842 is written as a '1'; the corresponding SPIO bit will drive low. The read
1843 value of these bits will be a '1' if that last command (#SET; #CLR; or
1844 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1845 these bits is written as a '1'; the corresponding SPIO bit will drive
1846 high (if it has that capability). The read value of these bits will be a
1847 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1848 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1849 each of the eight SPIO pins. This is the result value of the pin; not the
1850 drive value. Writing these bits will have not effect. Each 8 bits field
1851 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1852 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1853 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1854 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1855 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1856 select VAUX supply. (This is an output pin only; it is not controlled by
1857 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1858 field is not applicable for this pin; only the VALUE fields is relevant -
1859 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1860 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1861 device ID select; read by UMP firmware. */
1862 #define MISC_REG_SPIO 0xa4fc
1863 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1864 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1865 [7:0] reserved */
1866 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1867 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1868 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1869 interrupt on the falling edge of corresponding SPIO input (reset value
1870 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1871 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1872 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1873 RO; These bits indicate the old value of the SPIO input value. When the
1874 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1875 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1876 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1877 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1878 RO; These bits indicate the current SPIO interrupt state for each SPIO
1879 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1880 command bit is written. This bit is set when the SPIO input does not
1881 match the current value in #OLD_VALUE (reset value 0). */
1882 #define MISC_REG_SPIO_INT 0xa500
1883 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1884 the counter reached zero and the reload bit
1885 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1886 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1887 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1888 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
1889 timer 8 */
1890 #define MISC_REG_SW_TIMER_VAL 0xa5c0
1891 /* [R 1] Status of two port mode path swap input pin. */
1892 #define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
1893 /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1894 path_swap output is equal to 2 port mode path swap input pin; if it is 1
1895 - the path_swap output is equal to bit[1] of this register; [1] -
1896 Overwrite value. If bit[0] of this register is 1 this is the value that
1897 receives the path_swap output. Reset on Hard reset. */
1898 #define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
1899 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1900 loaded; 0-prepare; -unprepare */
1901 #define MISC_REG_UNPREPARED 0xa424
1902 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1903 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1904 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1905 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1906 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1907 /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1908 * not it is the recipient of the message on the MDIO interface. The value
1909 * is compared to the value on ctrl_md_devad. Drives output
1910 * misc_xgxs0_phy_addr. Global register. */
1911 #define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
1912 #define MISC_REG_WC0_RESET 0xac30
1913 /* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
1914 side. This should be less than or equal to phy_port_mode; if some of the
1915 ports are not used. This enables reduction of frequency on the core side.
1916 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1917 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1918 input for the XMAC_MP core; and should be changed only while reset is
1919 held low. Reset on Hard reset. */
1920 #define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
1921 /* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1922 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1923 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1924 XMAC_MP core; and should be changed only while reset is held low. Reset
1925 on Hard reset. */
1926 #define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
1927 /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1928 * Reads from this register will clear bits 31:0. */
1929 #define MSTAT_REG_RX_STAT_GR64_LO 0x200
1930 /* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1931 * 31:0. Reads from this register will clear bits 31:0. */
1932 #define MSTAT_REG_TX_STAT_GTXPOK_LO 0
1933 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1934 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1935 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1936 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1937 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1938 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1939 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
1940 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1941 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1942 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1943 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1944 /* [RW 1] Input enable for RX_BMAC0 IF */
1945 #define NIG_REG_BMAC0_IN_EN 0x100ac
1946 /* [RW 1] output enable for TX_BMAC0 IF */
1947 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1948 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1949 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1950 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1951 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1952 /* [RW 1] output enable for RX BRB1 port0 IF */
1953 #define NIG_REG_BRB0_OUT_EN 0x100f8
1954 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1955 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1956 /* [RW 1] output enable for RX BRB1 port1 IF */
1957 #define NIG_REG_BRB1_OUT_EN 0x100fc
1958 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1959 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1960 /* [RW 1] output enable for RX BRB1 LP IF */
1961 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1962 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1963 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1964 72:73]-vnic_num; 81:74]-sideband_info */
1965 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1966 /* [RW 1] Input enable for TX Debug packet */
1967 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1968 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1969 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1970 First packet may be deleted from the middle. And last packet will be
1971 always deleted till the end. */
1972 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1973 /* [RW 1] Output enable to EMAC0 */
1974 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1975 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1976 to emac for port0; other way to bmac for port0 */
1977 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1978 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1979 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1980 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1981 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1982 /* [RW 1] Input enable for TX UMP management packet port0 IF */
1983 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
1984 /* [RW 1] Input enable for RX_EMAC0 IF */
1985 #define NIG_REG_EMAC0_IN_EN 0x100a4
1986 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1987 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1988 /* [R 1] status from emac0. This bit is set when MDINT from either the
1989 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1990 be cleared in the attached PHY device that is driving the MINT pin. */
1991 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1992 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1993 are described in appendix A. In order to access the BMAC0 registers; the
1994 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1995 added to each BMAC register offset */
1996 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1997 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1998 are described in appendix A. In order to access the BMAC0 registers; the
1999 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
2000 added to each BMAC register offset */
2001 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
2002 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
2003 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
2004 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
2005 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
2006 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
2007 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
2008 logic for interrupts must be used. Enable per bit of interrupt of
2009 ~latch_status.latch_status */
2010 #define NIG_REG_LATCH_BC_0 0x16210
2011 /* [RW 27] Latch for each interrupt from Unicore.b[0]
2012 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
2013 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
2014 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
2015 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
2016 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
2017 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
2018 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
2019 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
2020 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
2021 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
2022 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
2023 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
2024 #define NIG_REG_LATCH_STATUS_0 0x18000
2025 /* [RW 1] led 10g for port 0 */
2026 #define NIG_REG_LED_10G_P0 0x10320
2027 /* [RW 1] led 10g for port 1 */
2028 #define NIG_REG_LED_10G_P1 0x10324
2029 /* [RW 1] Port0: This bit is set to enable the use of the
2030 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
2031 defined below. If this bit is cleared; then the blink rate will be about
2032 8Hz. */
2033 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
2034 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
2035 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
2036 is reset to 0x080; giving a default blink period of approximately 8Hz. */
2037 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
2038 /* [RW 1] Port0: If set along with the
2039 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
2040 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
2041 bit; the Traffic LED will blink with the blink rate specified in
2042 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
2043 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
2044 fields. */
2045 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
2046 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
2047 Traffic LED will then be controlled via bit ~nig_registers_
2048 led_control_traffic_p0.led_control_traffic_p0 and bit
2049 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
2050 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
2051 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
2052 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
2053 set; the LED will blink with blink rate specified in
2054 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
2055 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
2056 fields. */
2057 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
2058 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
2059 9-11PHY7; 12 MAC4; 13-15 PHY10; */
2060 #define NIG_REG_LED_MODE_P0 0x102f0
2061 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
2062 tsdm enable; b2- usdm enable */
2063 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
2064 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
2065 /* [RW 1] SAFC enable for port0. This register may get 1 only when
2066 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
2067 port */
2068 #define NIG_REG_LLFC_ENABLE_0 0x16208
2069 #define NIG_REG_LLFC_ENABLE_1 0x1620c
2070 /* [RW 16] classes are high-priority for port0 */
2071 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
2072 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
2073 /* [RW 16] classes are low-priority for port0 */
2074 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
2075 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
2076 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
2077 #define NIG_REG_LLFC_OUT_EN_0 0x160c8
2078 #define NIG_REG_LLFC_OUT_EN_1 0x160cc
2079 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
2080 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
2081 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
2082 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
2083 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
2084 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
2085 /* [RW 2] Determine the classification participants. 0: no classification.1:
2086 classification upon VLAN id. 2: classification upon MAC address. 3:
2087 classification upon both VLAN id & MAC addr. */
2088 #define NIG_REG_LLH0_CLS_TYPE 0x16080
2089 /* [RW 32] cm header for llh0 */
2090 #define NIG_REG_LLH0_CM_HEADER 0x1007c
2091 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
2092 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
2093 /* [RW 16] destination TCP address 1. The LLH will look for this address in
2094 all incoming packets. */
2095 #define NIG_REG_LLH0_DEST_TCP_0 0x10220
2096 /* [RW 16] destination UDP address 1 The LLH will look for this address in
2097 all incoming packets. */
2098 #define NIG_REG_LLH0_DEST_UDP_0 0x10214
2099 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
2100 /* [RW 8] event id for llh0 */
2101 #define NIG_REG_LLH0_EVENT_ID 0x10084
2102 #define NIG_REG_LLH0_FUNC_EN 0x160fc
2103 #define NIG_REG_LLH0_FUNC_MEM 0x16180
2104 #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
2105 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
2106 /* [RW 1] Determine the IP version to look for in
2107 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
2108 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
2109 /* [RW 1] t bit for llh0 */
2110 #define NIG_REG_LLH0_T_BIT 0x10074
2111 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
2112 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c
2113 /* [RW 8] init credit counter for port0 in LLH */
2114 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
2115 #define NIG_REG_LLH0_XCM_MASK 0x10130
2116 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
2117 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
2118 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
2119 /* [RW 2] Determine the classification participants. 0: no classification.1:
2120 classification upon VLAN id. 2: classification upon MAC address. 3:
2121 classification upon both VLAN id & MAC addr. */
2122 #define NIG_REG_LLH1_CLS_TYPE 0x16084
2123 /* [RW 32] cm header for llh1 */
2124 #define NIG_REG_LLH1_CM_HEADER 0x10080
2125 #define NIG_REG_LLH1_ERROR_MASK 0x10090
2126 /* [RW 8] event id for llh1 */
2127 #define NIG_REG_LLH1_EVENT_ID 0x10088
2128 #define NIG_REG_LLH1_FUNC_EN 0x16104
2129 #define NIG_REG_LLH1_FUNC_MEM 0x161c0
2130 #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
2131 #define NIG_REG_LLH1_FUNC_MEM_SIZE 16
2132 /* [RW 1] When this bit is set; the LLH will classify the packet before
2133 * sending it to the BRB or calculating WoL on it. This bit controls port 1
2134 * only. The legacy llh_multi_function_mode bit controls port 0. */
2135 #define NIG_REG_LLH1_MF_MODE 0x18614
2136 /* [RW 8] init credit counter for port1 in LLH */
2137 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
2138 #define NIG_REG_LLH1_XCM_MASK 0x10134
2139 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
2140 e1hov */
2141 #define NIG_REG_LLH_E1HOV_MODE 0x160d8
2142 /* [RW 16] Outer VLAN type identifier for multi-function mode. In non
2143 * multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
2144 */
2145 #define NIG_REG_LLH_E1HOV_TYPE_1 0x16028
2146 /* [RW 1] When this bit is set; the LLH will classify the packet before
2147 sending it to the BRB or calculating WoL on it. */
2148 #define NIG_REG_LLH_MF_MODE 0x16024
2149 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
2150 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
2151 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
2152 #define NIG_REG_NIG_EMAC0_EN 0x1003c
2153 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
2154 #define NIG_REG_NIG_EMAC1_EN 0x10040
2155 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
2156 EMAC0 to strip the CRC from the ingress packets. */
2157 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
2158 /* [R 32] Interrupt register #0 read */
2159 #define NIG_REG_NIG_INT_STS_0 0x103b0
2160 #define NIG_REG_NIG_INT_STS_1 0x103c0
2161 /* [RC 32] Interrupt register #0 read clear */
2162 #define NIG_REG_NIG_INT_STS_CLR_0 0x103b4
2163 /* [R 32] Legacy E1 and E1H location for parity error mask register. */
2164 #define NIG_REG_NIG_PRTY_MASK 0x103dc
2165 /* [RW 32] Parity mask register #0 read/write */
2166 #define NIG_REG_NIG_PRTY_MASK_0 0x183c8
2167 #define NIG_REG_NIG_PRTY_MASK_1 0x183d8
2168 /* [R 32] Legacy E1 and E1H location for parity error status register. */
2169 #define NIG_REG_NIG_PRTY_STS 0x103d0
2170 /* [R 32] Parity register #0 read */
2171 #define NIG_REG_NIG_PRTY_STS_0 0x183bc
2172 #define NIG_REG_NIG_PRTY_STS_1 0x183cc
2173 /* [R 32] Legacy E1 and E1H location for parity error status clear register. */
2174 #define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
2175 /* [RC 32] Parity register #0 read clear */
2176 #define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
2177 #define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
2178 #define MCPR_IMC_COMMAND_ENABLE (1L<<31)
2179 #define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
2180 #define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
2181 #define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
2182 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2183 * Ethernet header. */
2184 #define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
2185 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
2186 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
2187 * disabled when this bit is set. */
2188 #define NIG_REG_P0_HWPFC_ENABLE 0x18078
2189 #define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
2190 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
2191 /* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
2192 * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
2193 * indicates the validity of the data in the buffer. Writing a 1 to bit 16
2194 * will clear the buffer.
2195 */
2196 #define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID 0x1875c
2197 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2198 * the host. This location returns the lower 32 bits of timestamp value.
2199 */
2200 #define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB 0x18754
2201 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2202 * the host. This location returns the upper 32 bits of timestamp value.
2203 */
2204 #define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB 0x18758
2205 /* [RW 11] Mask register for the various parameters used in determining PTP
2206 * packet presence. Set each bit to 1 to mask out the particular parameter.
2207 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2208 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2209 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2210 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2211 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2212 * MAC DA 2. The reset default is set to mask out all parameters.
2213 */
2214 #define NIG_REG_P0_LLH_PTP_PARAM_MASK 0x187a0
2215 /* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
2216 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2217 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2218 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2219 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2220 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2221 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2222 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
2223 * packets only and require that the packet is IPv4 for the rules to match.
2224 * Note that rules 4-7 are for IPv6 packets only and require that the packet
2225 * is IPv6 for the rules to match.
2226 */
2227 #define NIG_REG_P0_LLH_PTP_RULE_MASK 0x187a4
2228 /* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
2229 #define NIG_REG_P0_LLH_PTP_TO_HOST 0x187ac
2230 /* [RW 1] Input enable for RX MAC interface. */
2231 #define NIG_REG_P0_MAC_IN_EN 0x185ac
2232 /* [RW 1] Output enable for TX MAC interface */
2233 #define NIG_REG_P0_MAC_OUT_EN 0x185b0
2234 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2235 #define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
2236 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2237 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2238 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2239 * priority field is extracted from the outer-most VLAN in receive packet.
2240 * Only COS 0 and COS 1 are supported in E2. */
2241 #define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
2242 /* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
2243 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
2244 * V1 frame format in timesync event detection on RX side. Bit 2 enables V2
2245 * frame format in timesync event detection on RX side. Bit 3 enables
2246 * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
2247 * detection on TX side. Bit 5 enables V2 frame format in timesync event
2248 * detection on TX side. Note that for HW to detect PTP packet and extract
2249 * data from the packet, at least one of the version bits of that traffic
2250 * direction has to be enabled.
2251 */
2252 #define NIG_REG_P0_PTP_EN 0x18788
2253 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2254 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2255 * than one bit may be set; allowing multiple priorities to be mapped to one
2256 * COS. */
2257 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
2258 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2259 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2260 * than one bit may be set; allowing multiple priorities to be mapped to one
2261 * COS. */
2262 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
2263 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2264 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2265 * than one bit may be set; allowing multiple priorities to be mapped to one
2266 * COS. */
2267 #define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
2268 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2269 * priority is mapped to COS 3 when the corresponding mask bit is 1. More
2270 * than one bit may be set; allowing multiple priorities to be mapped to one
2271 * COS. */
2272 #define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
2273 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2274 * priority is mapped to COS 4 when the corresponding mask bit is 1. More
2275 * than one bit may be set; allowing multiple priorities to be mapped to one
2276 * COS. */
2277 #define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
2278 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2279 * priority is mapped to COS 5 when the corresponding mask bit is 1. More
2280 * than one bit may be set; allowing multiple priorities to be mapped to one
2281 * COS. */
2282 #define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
2283 /* [R 1] RX FIFO for receiving data from MAC is empty. */
2284 /* [RW 15] Specify which of the credit registers the client is to be mapped
2285 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
2286 * clients that are not subject to WFQ credit blocking - their
2287 * specifications here are not used. */
2288 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
2289 /* [RW 32] Specify which of the credit registers the client is to be mapped
2290 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2291 * for client 0; bits [35:32] are for client 8. For clients that are not
2292 * subject to WFQ credit blocking - their specifications here are not used.
2293 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2294 * input clients to ETS arbiter. The reset default is set for management and
2295 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2296 * use credit registers 0-5 respectively (0x543210876). Note that credit
2297 * registers can not be shared between clients. */
2298 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688
2299 /* [RW 4] Specify which of the credit registers the client is to be mapped
2300 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2301 * for client 0; bits [35:32] are for client 8. For clients that are not
2302 * subject to WFQ credit blocking - their specifications here are not used.
2303 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2304 * input clients to ETS arbiter. The reset default is set for management and
2305 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2306 * use credit registers 0-5 respectively (0x543210876). Note that credit
2307 * registers can not be shared between clients. */
2308 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c
2309 /* [RW 5] Specify whether the client competes directly in the strict
2310 * priority arbiter. The bits are mapped according to client ID (client IDs
2311 * are defined in tx_arb_priority_client). Default value is set to enable
2312 * strict priorities for clients 0-2 -- management and debug traffic. */
2313 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
2314 /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
2315 * bits are mapped according to client ID (client IDs are defined in
2316 * tx_arb_priority_client). Default value is 0 for not using WFQ credit
2317 * blocking. */
2318 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
2319 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2320 * reach. */
2321 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
2322 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
2323 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114
2324 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118
2325 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c
2326 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0
2327 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4
2328 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8
2329 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac
2330 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2331 * when it is time to increment. */
2332 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
2333 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
2334 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100
2335 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104
2336 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108
2337 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690
2338 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694
2339 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698
2340 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c
2341 /* [RW 12] Specify the number of strict priority arbitration slots between
2342 * two round-robin arbitration slots to avoid starvation. A value of 0 means
2343 * no strict priority cycles - the strict priority with anti-starvation
2344 * arbiter becomes a round-robin arbiter. */
2345 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
2346 /* [RW 15] Specify the client number to be assigned to each priority of the
2347 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
2348 * are for priority 0 client; bits [14:12] are for priority 4 client. The
2349 * clients are assigned the following IDs: 0-management; 1-debug traffic
2350 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2351 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
2352 * for management at priority 0; debug traffic at priorities 1 and 2; COS0
2353 * traffic at priority 3; and COS1 traffic at priority 4. */
2354 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
2355 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2356 * Ethernet header. */
2357 #define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
2358 #define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
2359 #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460a
2360 /* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
2361 * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
2362 * indicates the validity of the data in the buffer. Writing a 1 to bit 16
2363 * will clear the buffer.
2364 */
2365 #define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID 0x18774
2366 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2367 * the host. This location returns the lower 32 bits of timestamp value.
2368 */
2369 #define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB 0x1876c
2370 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2371 * the host. This location returns the upper 32 bits of timestamp value.
2372 */
2373 #define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB 0x18770
2374 /* [RW 11] Mask register for the various parameters used in determining PTP
2375 * packet presence. Set each bit to 1 to mask out the particular parameter.
2376 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2377 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2378 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2379 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2380 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2381 * MAC DA 2. The reset default is set to mask out all parameters.
2382 */
2383 #define NIG_REG_P1_LLH_PTP_PARAM_MASK 0x187c8
2384 /* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
2385 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2386 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2387 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2388 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2389 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2390 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2391 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
2392 * packets only and require that the packet is IPv4 for the rules to match.
2393 * Note that rules 4-7 are for IPv6 packets only and require that the packet
2394 * is IPv6 for the rules to match.
2395 */
2396 #define NIG_REG_P1_LLH_PTP_RULE_MASK 0x187cc
2397 /* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
2398 #define NIG_REG_P1_LLH_PTP_TO_HOST 0x187d4
2399 /* [RW 32] Specify the client number to be assigned to each priority of the
2400 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2401 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2402 * client; bits [35-32] are for priority 8 client. The clients are assigned
2403 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2404 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2405 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2406 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2407 * accommodate the 9 input clients to ETS arbiter. */
2408 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680
2409 /* [RW 4] Specify the client number to be assigned to each priority of the
2410 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2411 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2412 * client; bits [35-32] are for priority 8 client. The clients are assigned
2413 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2414 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2415 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2416 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2417 * accommodate the 9 input clients to ETS arbiter. */
2418 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
2419 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
2420 * packets to BRB LB interface to forward the packet to the host. All
2421 * packets from MCP are forwarded to the network when this bit is cleared -
2422 * regardless of the configured destination in tx_mng_destination register.
2423 * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter
2424 * for BRB LB interface is bypassed and PBF LB traffic is always selected to
2425 * send to BRB LB.
2426 */
2427 #define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f4
2428 #define NIG_REG_P1_HWPFC_ENABLE 0x181d0
2429 #define NIG_REG_P1_MAC_IN_EN 0x185c0
2430 /* [RW 1] Output enable for TX MAC interface */
2431 #define NIG_REG_P1_MAC_OUT_EN 0x185c4
2432 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2433 #define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
2434 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2435 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2436 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2437 * priority field is extracted from the outer-most VLAN in receive packet.
2438 * Only COS 0 and COS 1 are supported in E2. */
2439 #define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
2440 /* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
2441 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
2442 * V1 frame format in timesync event detection on RX side. Bit 2 enables V2
2443 * frame format in timesync event detection on RX side. Bit 3 enables
2444 * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
2445 * detection on TX side. Bit 5 enables V2 frame format in timesync event
2446 * detection on TX side. Note that for HW to detect PTP packet and extract
2447 * data from the packet, at least one of the version bits of that traffic
2448 * direction has to be enabled.
2449 */
2450 #define NIG_REG_P1_PTP_EN 0x187b0
2451 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2452 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2453 * than one bit may be set; allowing multiple priorities to be mapped to one
2454 * COS. */
2455 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
2456 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2457 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2458 * than one bit may be set; allowing multiple priorities to be mapped to one
2459 * COS. */
2460 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
2461 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2462 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2463 * than one bit may be set; allowing multiple priorities to be mapped to one
2464 * COS. */
2465 #define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
2466 /* [R 1] RX FIFO for receiving data from MAC is empty. */
2467 #define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
2468 /* [R 1] TLLH FIFO is empty. */
2469 #define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
2470 /* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
2471 * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
2472 * indicates the validity of the data in the buffer. Bit 17 indicates that
2473 * the sequence ID is valid and it is waiting for the TX timestamp value.
2474 * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
2475 * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
2476 */
2477 #define NIG_REG_P0_TLLH_PTP_BUF_SEQID 0x187e0
2478 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2479 * MCP. This location returns the lower 32 bits of timestamp value.
2480 */
2481 #define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB 0x187d8
2482 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2483 * MCP. This location returns the upper 32 bits of timestamp value.
2484 */
2485 #define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB 0x187dc
2486 /* [RW 11] Mask register for the various parameters used in determining PTP
2487 * packet presence. Set each bit to 1 to mask out the particular parameter.
2488 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2489 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2490 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2491 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2492 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2493 * MAC DA 2. The reset default is set to mask out all parameters.
2494 */
2495 #define NIG_REG_P0_TLLH_PTP_PARAM_MASK 0x187f0
2496 /* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
2497 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2498 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2499 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2500 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2501 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2502 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2503 * default is to mask out all of the rules.
2504 */
2505 #define NIG_REG_P0_TLLH_PTP_RULE_MASK 0x187f4
2506 /* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
2507 * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
2508 * indicates the validity of the data in the buffer. Bit 17 indicates that
2509 * the sequence ID is valid and it is waiting for the TX timestamp value.
2510 * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
2511 * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
2512 */
2513 #define NIG_REG_P1_TLLH_PTP_BUF_SEQID 0x187ec
2514 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2515 * MCP. This location returns the lower 32 bits of timestamp value.
2516 */
2517 #define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB 0x187e4
2518 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2519 * MCP. This location returns the upper 32 bits of timestamp value.
2520 */
2521 #define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB 0x187e8
2522 /* [RW 11] Mask register for the various parameters used in determining PTP
2523 * packet presence. Set each bit to 1 to mask out the particular parameter.
2524 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2525 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2526 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2527 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2528 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2529 * MAC DA 2. The reset default is set to mask out all parameters.
2530 */
2531 #define NIG_REG_P1_TLLH_PTP_PARAM_MASK 0x187f8
2532 /* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
2533 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2534 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2535 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2536 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2537 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2538 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2539 * default is to mask out all of the rules.
2540 */
2541 #define NIG_REG_P1_TLLH_PTP_RULE_MASK 0x187fc
2542 /* [RW 32] Specify which of the credit registers the client is to be mapped
2543 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2544 * for client 0; bits [35:32] are for client 8. For clients that are not
2545 * subject to WFQ credit blocking - their specifications here are not used.
2546 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2547 * input clients to ETS arbiter. The reset default is set for management and
2548 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2549 * use credit registers 0-5 respectively (0x543210876). Note that credit
2550 * registers can not be shared between clients. Note also that there are
2551 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2552 * credit registers 0-5 are valid. This register should be configured
2553 * appropriately before enabling WFQ. */
2554 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
2555 /* [RW 4] Specify which of the credit registers the client is to be mapped
2556 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2557 * for client 0; bits [35:32] are for client 8. For clients that are not
2558 * subject to WFQ credit blocking - their specifications here are not used.
2559 * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2560 * input clients to ETS arbiter. The reset default is set for management and
2561 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2562 * use credit registers 0-5 respectively (0x543210876). Note that credit
2563 * registers can not be shared between clients. Note also that there are
2564 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2565 * credit registers 0-5 are valid. This register should be configured
2566 * appropriately before enabling WFQ. */
2567 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
2568 /* [RW 9] Specify whether the client competes directly in the strict
2569 * priority arbiter. The bits are mapped according to client ID (client IDs
2570 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2571 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2572 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2573 * Default value is set to enable strict priorities for all clients. */
2574 #define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
2575 /* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
2576 * bits are mapped according to client ID (client IDs are defined in
2577 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2578 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2579 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2580 * 0 for not using WFQ credit blocking. */
2581 #define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
2582 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258
2583 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c
2584 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260
2585 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264
2586 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268
2587 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4
2588 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2589 * when it is time to increment. */
2590 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244
2591 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248
2592 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c
2593 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250
2594 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254
2595 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0
2596 /* [RW 12] Specify the number of strict priority arbitration slots between
2597 two round-robin arbitration slots to avoid starvation. A value of 0 means
2598 no strict priority cycles - the strict priority with anti-starvation
2599 arbiter becomes a round-robin arbiter. */
2600 #define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240
2601 /* [RW 32] Specify the client number to be assigned to each priority of the
2602 strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2603 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2604 client; bits [35-32] are for priority 8 client. The clients are assigned
2605 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2606 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2607 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2608 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2609 accommodate the 9 input clients to ETS arbiter. Note that this register
2610 is the same as the one for port 0, except that port 1 only has COS 0-2
2611 traffic. There is no traffic for COS 3-5 of port 1. */
2612 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0
2613 /* [RW 4] Specify the client number to be assigned to each priority of the
2614 strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2615 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2616 client; bits [35-32] are for priority 8 client. The clients are assigned
2617 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2618 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2619 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2620 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2621 accommodate the 9 input clients to ETS arbiter. Note that this register
2622 is the same as the one for port 0, except that port 1 only has COS 0-2
2623 traffic. There is no traffic for COS 3-5 of port 1. */
2624 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4
2625 /* [R 1] TX FIFO for transmitting data to MAC is empty. */
2626 #define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594
2627 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
2628 * packets to BRB LB interface to forward the packet to the host. All
2629 * packets from MCP are forwarded to the network when this bit is cleared -
2630 * regardless of the configured destination in tx_mng_destination register.
2631 */
2632 #define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f8
2633 /* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
2634 forwarded to the host. */
2635 #define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8
2636 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2637 * reach. */
2638 /* [RW 1] Pause enable for port0. This register may get 1 only when
2639 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
2640 port */
2641 #define NIG_REG_PAUSE_ENABLE_0 0x160c0
2642 #define NIG_REG_PAUSE_ENABLE_1 0x160c4
2643 /* [RW 1] Input enable for RX PBF LP IF */
2644 #define NIG_REG_PBF_LB_IN_EN 0x100b4
2645 /* [RW 1] Value of this register will be transmitted to port swap when
2646 ~nig_registers_strap_override.strap_override =1 */
2647 #define NIG_REG_PORT_SWAP 0x10394
2648 /* [RW 1] PPP enable for port0. This register may get 1 only when
2649 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
2650 * same port */
2651 #define NIG_REG_PPP_ENABLE_0 0x160b0
2652 #define NIG_REG_PPP_ENABLE_1 0x160b4
2653 /* [RW 1] output enable for RX parser descriptor IF */
2654 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
2655 /* [RW 1] Input enable for RX parser request IF */
2656 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
2657 /* [RW 5] control to serdes - CL45 DEVAD */
2658 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
2659 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2660 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
2661 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2662 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
2663 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
2664 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
2665 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2666 for port0 */
2667 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
2668 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
2669 for port0 */
2670 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
2671 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2672 between 1024 and 1522 bytes for port0 */
2673 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
2674 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2675 between 1523 bytes and above for port0 */
2676 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
2677 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2678 for port1 */
2679 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
2680 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2681 between 1024 and 1522 bytes for port1 */
2682 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
2683 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2684 between 1523 bytes and above for port1 */
2685 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
2686 /* [WB_R 64] Rx statistics : User octets received for LP */
2687 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
2688 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
2689 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
2690 /* [RW 1] port swap mux selection. If this register equal to 0 then port
2691 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
2692 ort swap is equal to ~nig_registers_port_swap.port_swap */
2693 #define NIG_REG_STRAP_OVERRIDE 0x10398
2694 /* [WB 64] Addresses for TimeSync related registers in the timesync
2695 * generator sub-module.
2696 */
2697 #define NIG_REG_TIMESYNC_GEN_REG 0x18800
2698 /* [RW 1] output enable for RX_XCM0 IF */
2699 #define NIG_REG_XCM0_OUT_EN 0x100f0
2700 /* [RW 1] output enable for RX_XCM1 IF */
2701 #define NIG_REG_XCM1_OUT_EN 0x100f4
2702 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
2703 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
2704 /* [RW 5] control to xgxs - CL45 DEVAD */
2705 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
2706 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2707 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
2708 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2709 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
2710 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
2711 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
2712 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
2713 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
2714 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2715 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
2716 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2717 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
2718 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
2719 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
2720 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
2721 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
2722 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
2723 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2724 #define PBF_REG_COS0_UPPER_BOUND 0x15c05c
2725 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2726 * of port 0. */
2727 #define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc
2728 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2729 * of port 1. */
2730 #define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4
2731 /* [RW 31] The weight of COS0 in the ETS command arbiter. */
2732 #define PBF_REG_COS0_WEIGHT 0x15c054
2733 /* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
2734 #define PBF_REG_COS0_WEIGHT_P0 0x15c2a8
2735 /* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
2736 #define PBF_REG_COS0_WEIGHT_P1 0x15c2c0
2737 /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2738 #define PBF_REG_COS1_UPPER_BOUND 0x15c060
2739 /* [RW 31] The weight of COS1 in the ETS command arbiter. */
2740 #define PBF_REG_COS1_WEIGHT 0x15c058
2741 /* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
2742 #define PBF_REG_COS1_WEIGHT_P0 0x15c2ac
2743 /* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
2744 #define PBF_REG_COS1_WEIGHT_P1 0x15c2c4
2745 /* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
2746 #define PBF_REG_COS2_WEIGHT_P0 0x15c2b0
2747 /* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
2748 #define PBF_REG_COS2_WEIGHT_P1 0x15c2c8
2749 /* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
2750 #define PBF_REG_COS3_WEIGHT_P0 0x15c2b4
2751 /* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
2752 #define PBF_REG_COS4_WEIGHT_P0 0x15c2b8
2753 /* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
2754 #define PBF_REG_COS5_WEIGHT_P0 0x15c2bc
2755 /* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
2756 * lines. */
2757 #define PBF_REG_CREDIT_LB_Q 0x140338
2758 /* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
2759 * lines. */
2760 #define PBF_REG_CREDIT_Q0 0x14033c
2761 /* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
2762 * lines. */
2763 #define PBF_REG_CREDIT_Q1 0x140340
2764 /* [RW 1] Disable processing further tasks from port 0 (after ending the
2765 current task in process). */
2766 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
2767 /* [RW 1] Disable processing further tasks from port 1 (after ending the
2768 current task in process). */
2769 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
2770 /* [RW 1] Disable processing further tasks from port 4 (after ending the
2771 current task in process). */
2772 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
2773 #define PBF_REG_DISABLE_PF 0x1402e8
2774 #define PBF_REG_DISABLE_VF 0x1402ec
2775 /* [RW 18] For port 0: For each client that is subject to WFQ (the
2776 * corresponding bit is 1); indicates to which of the credit registers this
2777 * client is mapped. For clients which are not credit blocked; their mapping
2778 * is dont care. */
2779 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288
2780 /* [RW 9] For port 1: For each client that is subject to WFQ (the
2781 * corresponding bit is 1); indicates to which of the credit registers this
2782 * client is mapped. For clients which are not credit blocked; their mapping
2783 * is dont care. */
2784 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c
2785 /* [RW 6] For port 0: Bit per client to indicate if the client competes in
2786 * the strict priority arbiter directly (corresponding bit = 1); or first
2787 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2788 * lowest priority in the strict-priority arbiter. */
2789 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278
2790 /* [RW 3] For port 1: Bit per client to indicate if the client competes in
2791 * the strict priority arbiter directly (corresponding bit = 1); or first
2792 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2793 * lowest priority in the strict-priority arbiter. */
2794 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c
2795 /* [RW 6] For port 0: Bit per client to indicate if the client is subject to
2796 * WFQ credit blocking (corresponding bit = 1). */
2797 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280
2798 /* [RW 3] For port 0: Bit per client to indicate if the client is subject to
2799 * WFQ credit blocking (corresponding bit = 1). */
2800 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284
2801 /* [RW 16] For port 0: The number of strict priority arbitration slots
2802 * between 2 RR arbitration slots. A value of 0 means no strict priority
2803 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2804 * arbiter. */
2805 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0
2806 /* [RW 16] For port 1: The number of strict priority arbitration slots
2807 * between 2 RR arbitration slots. A value of 0 means no strict priority
2808 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2809 * arbiter. */
2810 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4
2811 /* [RW 18] For port 0: Indicates which client is connected to each priority
2812 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2813 * priority 5 is the lowest; to which the RR output is connected to (this is
2814 * not configurable). */
2815 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270
2816 /* [RW 9] For port 1: Indicates which client is connected to each priority
2817 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2818 * priority 5 is the lowest; to which the RR output is connected to (this is
2819 * not configurable). */
2820 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274
2821 /* [RW 1] Indicates that ETS is performed between the COSes in the command
2822 * arbiter. If reset strict priority w/ anti-starvation will be performed
2823 * w/o WFQ. */
2824 #define PBF_REG_ETS_ENABLED 0x15c050
2825 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2826 * Ethernet header. */
2827 #define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
2828 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2829 #define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
2830 /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2831 * priority in the command arbiter. */
2832 #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
2833 #define PBF_REG_IF_ENABLE_REG 0x140044
2834 /* [RW 1] Init bit. When set the initial credits are copied to the credit
2835 registers (except the port credits). Should be set and then reset after
2836 the configuration of the block has ended. */
2837 #define PBF_REG_INIT 0x140000
2838 /* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
2839 * lines. */
2840 #define PBF_REG_INIT_CRD_LB_Q 0x15c248
2841 /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2842 * lines. */
2843 #define PBF_REG_INIT_CRD_Q0 0x15c230
2844 /* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
2845 * lines. */
2846 #define PBF_REG_INIT_CRD_Q1 0x15c234
2847 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2848 copied to the credit register. Should be set and then reset after the
2849 configuration of the port has ended. */
2850 #define PBF_REG_INIT_P0 0x140004
2851 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2852 copied to the credit register. Should be set and then reset after the
2853 configuration of the port has ended. */
2854 #define PBF_REG_INIT_P1 0x140008
2855 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2856 copied to the credit register. Should be set and then reset after the
2857 configuration of the port has ended. */
2858 #define PBF_REG_INIT_P4 0x14000c
2859 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2860 * the LB queue. Reset upon init. */
2861 #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
2862 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2863 * queue 0. Reset upon init. */
2864 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
2865 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2866 * queue 1. Reset upon init. */
2867 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
2868 /* [RW 1] Enable for mac interface 0. */
2869 #define PBF_REG_MAC_IF0_ENABLE 0x140030
2870 /* [RW 1] Enable for mac interface 1. */
2871 #define PBF_REG_MAC_IF1_ENABLE 0x140034
2872 /* [RW 1] Enable for the loopback interface. */
2873 #define PBF_REG_MAC_LB_ENABLE 0x140040
2874 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2875 #define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
2876 /* [RW 16] The number of strict priority arbitration slots between 2 RR
2877 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2878 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2879 #define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
2880 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2881 not suppoterd. */
2882 #define PBF_REG_P0_ARB_THRSH 0x1400e4
2883 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2884 #define PBF_REG_P0_CREDIT 0x140200
2885 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2886 lines. */
2887 #define PBF_REG_P0_INIT_CRD 0x1400d0
2888 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2889 * port 0. Reset upon init. */
2890 #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
2891 /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2892 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
2893 /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
2894 #define PBF_REG_P0_TASK_CNT 0x140204
2895 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2896 * freed from the task queue of port 0. Reset upon init. */
2897 #define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
2898 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
2899 #define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
2900 /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2901 * buffers in 16 byte lines. */
2902 #define PBF_REG_P1_CREDIT 0x140208
2903 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2904 * buffers in 16 byte lines. */
2905 #define PBF_REG_P1_INIT_CRD 0x1400d4
2906 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2907 * port 1. Reset upon init. */
2908 #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
2909 /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
2910 #define PBF_REG_P1_TASK_CNT 0x14020c
2911 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2912 * freed from the task queue of port 1. Reset upon init. */
2913 #define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
2914 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
2915 #define PBF_REG_P1_TQ_OCCUPANCY 0x140300
2916 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2917 #define PBF_REG_P4_CREDIT 0x140210
2918 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2919 lines. */
2920 #define PBF_REG_P4_INIT_CRD 0x1400e0
2921 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2922 * port 4. Reset upon init. */
2923 #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
2924 /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
2925 #define PBF_REG_P4_TASK_CNT 0x140214
2926 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2927 * freed from the task queue of port 4. Reset upon init. */
2928 #define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
2929 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
2930 #define PBF_REG_P4_TQ_OCCUPANCY 0x140304
2931 /* [RW 5] Interrupt mask register #0 read/write */
2932 #define PBF_REG_PBF_INT_MASK 0x1401d4
2933 /* [R 5] Interrupt register #0 read */
2934 #define PBF_REG_PBF_INT_STS 0x1401c8
2935 /* [RW 20] Parity mask register #0 read/write */
2936 #define PBF_REG_PBF_PRTY_MASK 0x1401e4
2937 /* [R 28] Parity register #0 read */
2938 #define PBF_REG_PBF_PRTY_STS 0x1401d8
2939 /* [RC 20] Parity register #0 read clear */
2940 #define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
2941 /* [RW 16] The Ethernet type value for L2 tag 0 */
2942 #define PBF_REG_TAG_ETHERTYPE_0 0x15c090
2943 /* [RW 4] The length of the info field for L2 tag 0. The length is between
2944 * 2B and 14B; in 2B granularity */
2945 #define PBF_REG_TAG_LEN_0 0x15c09c
2946 /* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
2947 * queue. Reset upon init. */
2948 #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
2949 /* [R 32] Cyclic counter for number of 8 byte lines freed from the task
2950 * queue 0. Reset upon init. */
2951 #define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
2952 /* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
2953 * Reset upon init. */
2954 #define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
2955 /* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
2956 * queue. */
2957 #define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
2958 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
2959 #define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
2960 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
2961 #define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
2962 /* [RW 16] One of 8 values that should be compared to type in Ethernet
2963 * parsing. If there is a match; the field after Ethernet is the first VLAN.
2964 * Reset value is 0x8100 which is the standard VLAN type. Note that when
2965 * checking second VLAN; type is compared only to 0x8100.
2966 */
2967 #define PBF_REG_VLAN_TYPE_0 0x15c06c
2968 /* [RW 2] Interrupt mask register #0 read/write */
2969 #define PB_REG_PB_INT_MASK 0x28
2970 /* [R 2] Interrupt register #0 read */
2971 #define PB_REG_PB_INT_STS 0x1c
2972 /* [RW 4] Parity mask register #0 read/write */
2973 #define PB_REG_PB_PRTY_MASK 0x38
2974 /* [R 4] Parity register #0 read */
2975 #define PB_REG_PB_PRTY_STS 0x2c
2976 /* [RC 4] Parity register #0 read clear */
2977 #define PB_REG_PB_PRTY_STS_CLR 0x30
2978 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2979 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
2980 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
2981 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
2982 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
2983 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
2984 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
2985 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
2986 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
2987 /* [R 8] Config space A attention dirty bits. Each bit indicates that the
2988 * corresponding PF generates config space A attention. Set by PXP. Reset by
2989 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
2990 * from both paths. */
2991 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
2992 /* [R 8] Config space B attention dirty bits. Each bit indicates that the
2993 * corresponding PF generates config space B attention. Set by PXP. Reset by
2994 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
2995 * from both paths. */
2996 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
2997 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2998 * - enable. */
2999 #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194
3000 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
3001 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
3002 #define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c
3003 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
3004 * - enable. */
3005 #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c
3006 /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
3007 #define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100
3008 /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
3009 #define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108
3010 /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
3011 #define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110
3012 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3013 #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac
3014 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
3015 * that the FLR register of the corresponding PF was set. Set by PXP. Reset
3016 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
3017 * from both paths. */
3018 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
3019 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
3020 * to a bit in this register in order to clear the corresponding bit in
3021 * flr_request_pf_7_0 register. Note: register contains bits from both
3022 * paths. */
3023 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
3024 /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
3025 * indicates that the FLR register of the corresponding VF was set. Set by
3026 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
3027 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
3028 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
3029 * indicates that the FLR register of the corresponding VF was set. Set by
3030 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
3031 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
3032 /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
3033 * indicates that the FLR register of the corresponding VF was set. Set by
3034 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
3035 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
3036 /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
3037 * indicates that the FLR register of the corresponding VF was set. Set by
3038 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
3039 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
3040 /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
3041 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
3042 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
3043 * arrived with a correctable error. Bit 3 - Configuration RW arrived with
3044 * an uncorrectable error. Bit 4 - Completion with Configuration Request
3045 * Retry Status. Bit 5 - Expansion ROM access received with a write request.
3046 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
3047 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
3048 * and pcie_rx_last not asserted. */
3049 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
3050 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
3051 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
3052 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434
3053 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
3054 /* [W 7] Writing 1 to each bit in this register clears a corresponding error
3055 * details register and enables logging new error details. Bit 0 - clears
3056 * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears
3057 * TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS
3058 * TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32
3059 * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 -
3060 * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears
3061 * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6
3062 * - clears TCPL_IN_TWO_RCBS_DETAILS. */
3063 #define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x943c
3064
3065 /* [R 9] Interrupt register #0 read */
3066 #define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
3067 /* [RC 9] Interrupt register #0 read clear */
3068 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
3069 /* [RW 2] Parity mask register #0 read/write */
3070 #define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4
3071 /* [R 2] Parity register #0 read */
3072 #define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
3073 /* [RC 2] Parity register #0 read clear */
3074 #define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac
3075 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
3076 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
3077 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
3078 * completer abort. 3 - Illegal value for this field. [12] valid - indicates
3079 * if there was a completion error since the last time this register was
3080 * cleared. */
3081 #define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
3082 /* [R 18] Details of first ATS Translation Completion request received with
3083 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
3084 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
3085 * unsupported request. 2 - completer abort. 3 - Illegal value for this
3086 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
3087 * completion error since the last time this register was cleared. */
3088 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
3089 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
3090 * a bit in this register in order to clear the corresponding bit in
3091 * shadow_bme_pf_7_0 register. MCP should never use this unless a
3092 * work-around is needed. Note: register contains bits from both paths. */
3093 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
3094 /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
3095 * VF enable register of the corresponding PF is written to 0 and was
3096 * previously 1. Set by PXP. Reset by MCP writing 1 to
3097 * sr_iov_disabled_request_clr. Note: register contains bits from both
3098 * paths. */
3099 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
3100 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
3101 * completion did not return yet. 1 - tag is unused. Same functionality as
3102 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
3103 #define PGLUE_B_REG_TAGS_63_32 0x9244
3104 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
3105 * - enable. */
3106 #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170
3107 /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
3108 #define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4
3109 /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
3110 #define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc
3111 /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
3112 #define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4
3113 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3114 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0
3115 /* [R 32] Address [31:0] of first read request not submitted due to error */
3116 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
3117 /* [R 32] Address [63:32] of first read request not submitted due to error */
3118 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
3119 /* [R 31] Details of first read request not submitted due to error. [4:0]
3120 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
3121 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
3122 * VFID. */
3123 #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
3124 /* [R 26] Details of first read request not submitted due to error. [15:0]
3125 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
3126 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
3127 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
3128 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
3129 * indicates if there was a request not submitted due to error since the
3130 * last time this register was cleared. */
3131 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
3132 /* [R 32] Address [31:0] of first write request not submitted due to error */
3133 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
3134 /* [R 32] Address [63:32] of first write request not submitted due to error */
3135 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
3136 /* [R 31] Details of first write request not submitted due to error. [4:0]
3137 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
3138 * - VFID. */
3139 #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
3140 /* [R 26] Details of first write request not submitted due to error. [15:0]
3141 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
3142 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
3143 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
3144 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
3145 * indicates if there was a request not submitted due to error since the
3146 * last time this register was cleared. */
3147 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
3148 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
3149 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
3150 * value (Byte resolution address). */
3151 #define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128
3152 #define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c
3153 #define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130
3154 #define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134
3155 #define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138
3156 #define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c
3157 #define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140
3158 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
3159 * - enable. */
3160 #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c
3161 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
3162 * - enable. */
3163 #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180
3164 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
3165 * - enable. */
3166 #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184
3167 /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
3168 #define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8
3169 /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
3170 #define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0
3171 /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
3172 #define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8
3173 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3174 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4
3175 /* [R 26] Details of first target VF request accessing VF GRC space that
3176 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
3177 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
3178 * request accessing VF GRC space that failed permission check since the
3179 * last time this register was cleared. Permission checks are: function
3180 * permission; R/W permission; address range permission. */
3181 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
3182 /* [R 31] Details of first target VF request with length violation (too many
3183 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
3184 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
3185 * valid - indicates if there was a request with length violation since the
3186 * last time this register was cleared. Length violations: length of more
3187 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
3188 * length is more than 1 DW. */
3189 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
3190 /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
3191 * that there was a completion with uncorrectable error for the
3192 * corresponding PF. Set by PXP. Reset by MCP writing 1 to
3193 * was_error_pf_7_0_clr. */
3194 #define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
3195 /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
3196 * to a bit in this register in order to clear the corresponding bit in
3197 * flr_request_pf_7_0 register. */
3198 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
3199 /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
3200 * indicates that there was a completion with uncorrectable error for the
3201 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
3202 * was_error_vf_127_96_clr. */
3203 #define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
3204 /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
3205 * writes 1 to a bit in this register in order to clear the corresponding
3206 * bit in was_error_vf_127_96 register. */
3207 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
3208 /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
3209 * indicates that there was a completion with uncorrectable error for the
3210 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
3211 * was_error_vf_31_0_clr. */
3212 #define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
3213 /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
3214 * 1 to a bit in this register in order to clear the corresponding bit in
3215 * was_error_vf_31_0 register. */
3216 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
3217 /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
3218 * indicates that there was a completion with uncorrectable error for the
3219 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
3220 * was_error_vf_63_32_clr. */
3221 #define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
3222 /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
3223 * 1 to a bit in this register in order to clear the corresponding bit in
3224 * was_error_vf_63_32 register. */
3225 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
3226 /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
3227 * indicates that there was a completion with uncorrectable error for the
3228 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
3229 * was_error_vf_95_64_clr. */
3230 #define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
3231 /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
3232 * 1 to a bit in this register in order to clear the corresponding bit in
3233 * was_error_vf_95_64 register. */
3234 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
3235 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
3236 * - enable. */
3237 #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188
3238 /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
3239 #define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec
3240 /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
3241 #define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4
3242 /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
3243 #define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc
3244 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3245 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8
3246 #define PRS_REG_A_PRSU_20 0x40134
3247 /* [R 8] debug only: CFC load request current credit. Transaction based. */
3248 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
3249 /* [R 8] debug only: CFC search request current credit. Transaction based. */
3250 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
3251 /* [RW 6] The initial credit for the search message to the CFC interface.
3252 Credit is transaction based. */
3253 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
3254 /* [RW 24] CID for port 0 if no match */
3255 #define PRS_REG_CID_PORT_0 0x400fc
3256 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
3257 load response is reset and packet type is 0. Used in packet start message
3258 to TCM. */
3259 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
3260 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
3261 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
3262 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
3263 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
3264 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
3265 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
3266 load response is set and packet type is 0. Used in packet start message
3267 to TCM. */
3268 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
3269 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
3270 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
3271 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
3272 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
3273 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
3274 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
3275 Used in packet start message to TCM. */
3276 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
3277 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
3278 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
3279 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
3280 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
3281 message to TCM. */
3282 #define PRS_REG_CM_HDR_TYPE_0 0x40078
3283 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
3284 #define PRS_REG_CM_HDR_TYPE_2 0x40080
3285 #define PRS_REG_CM_HDR_TYPE_3 0x40084
3286 #define PRS_REG_CM_HDR_TYPE_4 0x40088
3287 /* [RW 32] The CM header in case there was not a match on the connection */
3288 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
3289 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
3290 #define PRS_REG_E1HOV_MODE 0x401c8
3291 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
3292 start message to TCM. */
3293 #define PRS_REG_EVENT_ID_1 0x40054
3294 #define PRS_REG_EVENT_ID_2 0x40058
3295 #define PRS_REG_EVENT_ID_3 0x4005c
3296 /* [RW 16] The Ethernet type value for FCoE */
3297 #define PRS_REG_FCOE_TYPE 0x401d0
3298 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
3299 load request message. */
3300 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
3301 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
3302 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
3303 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
3304 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
3305 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
3306 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
3307 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
3308 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3309 * Ethernet header. */
3310 #define PRS_REG_HDRS_AFTER_BASIC 0x40238
3311 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3312 * Ethernet header for port 0 packets. */
3313 #define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
3314 #define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
3315 /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
3316 #define PRS_REG_HDRS_AFTER_TAG_0 0x40248
3317 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
3318 * port 0 packets */
3319 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
3320 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
3321 /* [RW 4] The increment value to send in the CFC load request message */
3322 #define PRS_REG_INC_VALUE 0x40048
3323 /* [RW 6] Bit-map indicating which headers must appear in the packet */
3324 #define PRS_REG_MUST_HAVE_HDRS 0x40254
3325 /* [RW 6] Bit-map indicating which headers must appear in the packet for
3326 * port 0 packets */
3327 #define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
3328 #define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
3329 #define PRS_REG_NIC_MODE 0x40138
3330 /* [RW 8] The 8-bit event ID for cases where there is no match on the
3331 connection. Used in packet start message to TCM. */
3332 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
3333 /* [ST 24] The number of input CFC flush packets */
3334 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
3335 /* [ST 32] The number of cycles the Parser halted its operation since it
3336 could not allocate the next serial number */
3337 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
3338 /* [ST 24] The number of input packets */
3339 #define PRS_REG_NUM_OF_PACKETS 0x40124
3340 /* [ST 24] The number of input transparent flush packets */
3341 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
3342 /* [RW 8] Context region for received Ethernet packet with a match and
3343 packet type 0. Used in CFC load request message */
3344 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
3345 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
3346 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
3347 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
3348 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
3349 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
3350 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
3351 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
3352 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
3353 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
3354 /* [R 2] debug only: Number of pending requests for header parsing. */
3355 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
3356 /* [R 1] Interrupt register #0 read */
3357 #define PRS_REG_PRS_INT_STS 0x40188
3358 /* [RW 8] Parity mask register #0 read/write */
3359 #define PRS_REG_PRS_PRTY_MASK 0x401a4
3360 /* [R 8] Parity register #0 read */
3361 #define PRS_REG_PRS_PRTY_STS 0x40198
3362 /* [RC 8] Parity register #0 read clear */
3363 #define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
3364 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
3365 request message */
3366 #define PRS_REG_PURE_REGIONS 0x40024
3367 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
3368 serail number was released by SDM but cannot be used because a previous
3369 serial number was not released. */
3370 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
3371 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
3372 serail number was released by SDM but cannot be used because a previous
3373 serial number was not released. */
3374 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
3375 /* [R 4] debug only: SRC current credit. Transaction based. */
3376 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
3377 /* [RW 16] The Ethernet type value for L2 tag 0 */
3378 #define PRS_REG_TAG_ETHERTYPE_0 0x401d4
3379 /* [RW 4] The length of the info field for L2 tag 0. The length is between
3380 * 2B and 14B; in 2B granularity */
3381 #define PRS_REG_TAG_LEN_0 0x4022c
3382 /* [R 8] debug only: TCM current credit. Cycle based. */
3383 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
3384 /* [R 8] debug only: TSDM current credit. Transaction based. */
3385 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
3386 /* [RW 16] One of 8 values that should be compared to type in Ethernet
3387 * parsing. If there is a match; the field after Ethernet is the first VLAN.
3388 * Reset value is 0x8100 which is the standard VLAN type. Note that when
3389 * checking second VLAN; type is compared only to 0x8100.
3390 */
3391 #define PRS_REG_VLAN_TYPE_0 0x401a8
3392 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
3393 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
3394 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
3395 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
3396 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
3397 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
3398 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
3399 /* [R 6] Debug only: Number of used entries in the data FIFO */
3400 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
3401 /* [R 7] Debug only: Number of used entries in the header FIFO */
3402 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
3403 #define PXP2_REG_PGL_ADDR_88_F0 0x120534
3404 /* [R 32] GRC address for configuration access to PCIE config address 0x88.
3405 * any write to this PCIE address will cause a GRC write access to the
3406 * address that's in t this register */
3407 #define PXP2_REG_PGL_ADDR_88_F1 0x120544
3408 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538
3409 /* [R 32] GRC address for configuration access to PCIE config address 0x8c.
3410 * any write to this PCIE address will cause a GRC write access to the
3411 * address that's in t this register */
3412 #define PXP2_REG_PGL_ADDR_8C_F1 0x120548
3413 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c
3414 /* [R 32] GRC address for configuration access to PCIE config address 0x90.
3415 * any write to this PCIE address will cause a GRC write access to the
3416 * address that's in t this register */
3417 #define PXP2_REG_PGL_ADDR_90_F1 0x12054c
3418 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
3419 /* [R 32] GRC address for configuration access to PCIE config address 0x94.
3420 * any write to this PCIE address will cause a GRC write access to the
3421 * address that's in t this register */
3422 #define PXP2_REG_PGL_ADDR_94_F1 0x120550
3423 #define PXP2_REG_PGL_CONTROL0 0x120490
3424 #define PXP2_REG_PGL_CONTROL1 0x120514
3425 #define PXP2_REG_PGL_DEBUG 0x120520
3426 /* [RW 32] third dword data of expansion rom request. this register is
3427 special. reading from it provides a vector outstanding read requests. if
3428 a bit is zero it means that a read request on the corresponding tag did
3429 not finish yet (not all completions have arrived for it) */
3430 #define PXP2_REG_PGL_EXP_ROM2 0x120808
3431 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
3432 its[15:0]-address */
3433 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
3434 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
3435 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
3436 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
3437 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
3438 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
3439 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
3440 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
3441 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
3442 its[15:0]-address */
3443 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
3444 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
3445 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
3446 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
3447 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
3448 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
3449 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
3450 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
3451 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
3452 its[15:0]-address */
3453 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
3454 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
3455 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
3456 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
3457 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
3458 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
3459 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
3460 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
3461 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
3462 its[15:0]-address */
3463 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
3464 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
3465 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
3466 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
3467 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
3468 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
3469 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
3470 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
3471 /* [RW 3] this field allows one function to pretend being another function
3472 when accessing any BAR mapped resource within the device. the value of
3473 the field is the number of the function that will be accessed
3474 effectively. after software write to this bit it must read it in order to
3475 know that the new value is updated */
3476 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
3477 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
3478 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
3479 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
3480 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
3481 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
3482 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
3483 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
3484 /* [R 1] this bit indicates that a read request was blocked because of
3485 bus_master_en was deasserted */
3486 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
3487 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
3488 /* [R 18] debug only */
3489 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
3490 /* [R 1] this bit indicates that a write request was blocked because of
3491 bus_master_en was deasserted */
3492 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
3493 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
3494 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
3495 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
3496 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
3497 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
3498 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
3499 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
3500 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
3501 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
3502 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
3503 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
3504 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
3505 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
3506 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
3507 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
3508 #define PXP2_REG_PSWRQ_BW_L28 0x120318
3509 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
3510 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
3511 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
3512 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
3513 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
3514 #define PXP2_REG_PSWRQ_BW_RD 0x120324
3515 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
3516 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
3517 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
3518 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
3519 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
3520 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
3521 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
3522 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
3523 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
3524 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
3525 #define PXP2_REG_PSWRQ_BW_WR 0x120328
3526 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
3527 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
3528 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
3529 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
3530 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
3531 /* [RW 32] Interrupt mask register #0 read/write */
3532 #define PXP2_REG_PXP2_INT_MASK_0 0x120578
3533 /* [R 32] Interrupt register #0 read */
3534 #define PXP2_REG_PXP2_INT_STS_0 0x12056c
3535 #define PXP2_REG_PXP2_INT_STS_1 0x120608
3536 /* [RC 32] Interrupt register #0 read clear */
3537 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
3538 /* [RW 32] Parity mask register #0 read/write */
3539 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
3540 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
3541 /* [R 32] Parity register #0 read */
3542 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
3543 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
3544 /* [RC 32] Parity register #0 read clear */
3545 #define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
3546 #define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
3547 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
3548 indication about backpressure) */
3549 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
3550 /* [R 8] Debug only: The blocks counter - number of unused block ids */
3551 #define PXP2_REG_RD_BLK_CNT 0x120418
3552 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
3553 Must be bigger than 6. Normally should not be changed. */
3554 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
3555 /* [RW 2] CDU byte swapping mode configuration for master read requests */
3556 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
3557 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
3558 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
3559 /* [R 1] PSWRD internal memories initialization is done */
3560 #define PXP2_REG_RD_INIT_DONE 0x120370
3561 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3562 allocated for vq10 */
3563 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
3564 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3565 allocated for vq11 */
3566 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
3567 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3568 allocated for vq17 */
3569 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
3570 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3571 allocated for vq18 */
3572 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
3573 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3574 allocated for vq19 */
3575 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
3576 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3577 allocated for vq22 */
3578 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
3579 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3580 allocated for vq25 */
3581 #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
3582 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3583 allocated for vq6 */
3584 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
3585 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3586 allocated for vq9 */
3587 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
3588 /* [RW 2] PBF byte swapping mode configuration for master read requests */
3589 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
3590 /* [R 1] Debug only: Indication if delivery ports are idle */
3591 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
3592 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
3593 /* [RW 2] QM byte swapping mode configuration for master read requests */
3594 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
3595 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
3596 #define PXP2_REG_RD_SR_CNT 0x120414
3597 /* [RW 2] SRC byte swapping mode configuration for master read requests */
3598 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
3599 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
3600 be bigger than 1. Normally should not be changed. */
3601 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
3602 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
3603 #define PXP2_REG_RD_START_INIT 0x12036c
3604 /* [RW 2] TM byte swapping mode configuration for master read requests */
3605 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
3606 /* [RW 10] Bandwidth addition to VQ0 write requests */
3607 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
3608 /* [RW 10] Bandwidth addition to VQ12 read requests */
3609 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
3610 /* [RW 10] Bandwidth addition to VQ13 read requests */
3611 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
3612 /* [RW 10] Bandwidth addition to VQ14 read requests */
3613 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
3614 /* [RW 10] Bandwidth addition to VQ15 read requests */
3615 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
3616 /* [RW 10] Bandwidth addition to VQ16 read requests */
3617 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
3618 /* [RW 10] Bandwidth addition to VQ17 read requests */
3619 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
3620 /* [RW 10] Bandwidth addition to VQ18 read requests */
3621 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
3622 /* [RW 10] Bandwidth addition to VQ19 read requests */
3623 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
3624 /* [RW 10] Bandwidth addition to VQ20 read requests */
3625 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
3626 /* [RW 10] Bandwidth addition to VQ22 read requests */
3627 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
3628 /* [RW 10] Bandwidth addition to VQ23 read requests */
3629 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
3630 /* [RW 10] Bandwidth addition to VQ24 read requests */
3631 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
3632 /* [RW 10] Bandwidth addition to VQ25 read requests */
3633 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
3634 /* [RW 10] Bandwidth addition to VQ26 read requests */
3635 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
3636 /* [RW 10] Bandwidth addition to VQ27 read requests */
3637 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
3638 /* [RW 10] Bandwidth addition to VQ4 read requests */
3639 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
3640 /* [RW 10] Bandwidth addition to VQ5 read requests */
3641 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
3642 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
3643 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
3644 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
3645 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
3646 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
3647 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
3648 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
3649 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
3650 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
3651 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
3652 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
3653 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
3654 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
3655 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
3656 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
3657 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
3658 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
3659 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
3660 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
3661 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
3662 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
3663 #define PXP2_REG_RQ_BW_RD_L22 0x120300
3664 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
3665 #define PXP2_REG_RQ_BW_RD_L23 0x120304
3666 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
3667 #define PXP2_REG_RQ_BW_RD_L24 0x120308
3668 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
3669 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
3670 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
3671 #define PXP2_REG_RQ_BW_RD_L26 0x120310
3672 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
3673 #define PXP2_REG_RQ_BW_RD_L27 0x120314
3674 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
3675 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
3676 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
3677 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
3678 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
3679 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
3680 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
3681 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
3682 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
3683 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
3684 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
3685 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
3686 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
3687 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
3688 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
3689 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
3690 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
3691 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
3692 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
3693 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
3694 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
3695 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
3696 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
3697 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
3698 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
3699 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
3700 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
3701 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
3702 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
3703 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
3704 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
3705 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
3706 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
3707 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
3708 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
3709 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
3710 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
3711 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
3712 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
3713 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
3714 /* [RW 10] Bandwidth addition to VQ29 write requests */
3715 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
3716 /* [RW 10] Bandwidth addition to VQ30 write requests */
3717 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
3718 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
3719 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
3720 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
3721 #define PXP2_REG_RQ_BW_WR_L30 0x120320
3722 /* [RW 7] Bandwidth upper bound for VQ29 */
3723 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
3724 /* [RW 7] Bandwidth upper bound for VQ30 */
3725 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
3726 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
3727 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
3728 /* [RW 2] Endian mode for cdu */
3729 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
3730 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
3731 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
3732 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
3733 -128k */
3734 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
3735 /* [R 1] 1' indicates that the requester has finished its internal
3736 configuration */
3737 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
3738 /* [RW 2] Endian mode for debug */
3739 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
3740 /* [RW 1] When '1'; requests will enter input buffers but wont get out
3741 towards the glue */
3742 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
3743 /* [RW 4] Determines alignment of write SRs when a request is split into
3744 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3745 * aligned. 4 - 512B aligned. */
3746 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
3747 /* [RW 4] Determines alignment of read SRs when a request is split into
3748 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3749 * aligned. 4 - 512B aligned. */
3750 #define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
3751 /* [RW 1] when set the new alignment method (E2) will be applied; when reset
3752 * the original alignment method (E1 E1H) will be applied */
3753 #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
3754 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
3755 be asserted */
3756 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c
3757 /* [RW 2] Endian mode for hc */
3758 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
3759 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
3760 compatibility needs; Note that different registers are used per mode */
3761 #define PXP2_REG_RQ_ILT_MODE 0x1205b4
3762 /* [WB 53] Onchip address table */
3763 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
3764 /* [WB 53] Onchip address table - B0 */
3765 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
3766 /* [RW 13] Pending read limiter threshold; in Dwords */
3767 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
3768 /* [RW 2] Endian mode for qm */
3769 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
3770 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
3771 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638
3772 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3773 -128k */
3774 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
3775 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
3776 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
3777 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3778 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3779 #define PXP2_REG_RQ_RD_MBS0 0x120160
3780 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3781 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3782 #define PXP2_REG_RQ_RD_MBS1 0x120168
3783 /* [RW 2] Endian mode for src */
3784 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
3785 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
3786 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
3787 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3788 -128k */
3789 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
3790 /* [RW 2] Endian mode for tm */
3791 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
3792 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
3793 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648
3794 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3795 -128k */
3796 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
3797 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
3798 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
3799 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
3800 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
3801 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
3802 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
3803 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
3804 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
3805 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
3806 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
3807 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
3808 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
3809 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
3810 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
3811 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
3812 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
3813 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
3814 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
3815 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
3816 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
3817 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
3818 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
3819 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
3820 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
3821 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
3822 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
3823 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
3824 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
3825 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
3826 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
3827 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
3828 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
3829 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
3830 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
3831 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
3832 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
3833 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
3834 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
3835 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
3836 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
3837 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
3838 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
3839 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
3840 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
3841 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
3842 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
3843 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
3844 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
3845 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
3846 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
3847 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
3848 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
3849 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
3850 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
3851 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
3852 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
3853 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
3854 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
3855 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
3856 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
3857 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
3858 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
3859 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
3860 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
3861 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
3862 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
3863 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
3864 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
3865 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3866 001:256B; 010: 512B; */
3867 #define PXP2_REG_RQ_WR_MBS0 0x12015c
3868 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3869 001:256B; 010: 512B; */
3870 #define PXP2_REG_RQ_WR_MBS1 0x120164
3871 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3872 buffer reaches this number has_payload will be asserted */
3873 #define PXP2_REG_WR_CDU_MPS 0x1205f0
3874 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3875 buffer reaches this number has_payload will be asserted */
3876 #define PXP2_REG_WR_CSDM_MPS 0x1205d0
3877 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3878 buffer reaches this number has_payload will be asserted */
3879 #define PXP2_REG_WR_DBG_MPS 0x1205e8
3880 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3881 buffer reaches this number has_payload will be asserted */
3882 #define PXP2_REG_WR_DMAE_MPS 0x1205ec
3883 /* [RW 10] if Number of entries in dmae fifo will be higher than this
3884 threshold then has_payload indication will be asserted; the default value
3885 should be equal to > write MBS size! */
3886 #define PXP2_REG_WR_DMAE_TH 0x120368
3887 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3888 buffer reaches this number has_payload will be asserted */
3889 #define PXP2_REG_WR_HC_MPS 0x1205c8
3890 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3891 buffer reaches this number has_payload will be asserted */
3892 #define PXP2_REG_WR_QM_MPS 0x1205dc
3893 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
3894 #define PXP2_REG_WR_REV_MODE 0x120670
3895 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3896 buffer reaches this number has_payload will be asserted */
3897 #define PXP2_REG_WR_SRC_MPS 0x1205e4
3898 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3899 buffer reaches this number has_payload will be asserted */
3900 #define PXP2_REG_WR_TM_MPS 0x1205e0
3901 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3902 buffer reaches this number has_payload will be asserted */
3903 #define PXP2_REG_WR_TSDM_MPS 0x1205d4
3904 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
3905 threshold then has_payload indication will be asserted; the default value
3906 should be equal to > write MBS size! */
3907 #define PXP2_REG_WR_USDMDP_TH 0x120348
3908 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3909 buffer reaches this number has_payload will be asserted */
3910 #define PXP2_REG_WR_USDM_MPS 0x1205cc
3911 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3912 buffer reaches this number has_payload will be asserted */
3913 #define PXP2_REG_WR_XSDM_MPS 0x1205d8
3914 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
3915 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
3916 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
3917 this client is waiting for the arbiter. */
3918 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
3919 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
3920 block. Should be used for close the gates. */
3921 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
3922 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
3923 should update according to 'hst_discard_doorbells' register when the state
3924 machine is idle */
3925 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
3926 /* [RW 1] When 1; new internal writes arriving to the block are discarded.
3927 Should be used for close the gates. */
3928 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
3929 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
3930 means this PSWHST is discarding inputs from this client. Each bit should
3931 update according to 'hst_discard_internal_writes' register when the state
3932 machine is idle. */
3933 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
3934 /* [WB 160] Used for initialization of the inbound interrupts memory */
3935 #define PXP_REG_HST_INBOUND_INT 0x103800
3936 /* [RW 7] Indirect access to the permission table. The fields are : {Valid;
3937 * VFID[5:0]}
3938 */
3939 #define PXP_REG_HST_ZONE_PERMISSION_TABLE 0x103400
3940 /* [RW 32] Interrupt mask register #0 read/write */
3941 #define PXP_REG_PXP_INT_MASK_0 0x103074
3942 #define PXP_REG_PXP_INT_MASK_1 0x103084
3943 /* [R 32] Interrupt register #0 read */
3944 #define PXP_REG_PXP_INT_STS_0 0x103068
3945 #define PXP_REG_PXP_INT_STS_1 0x103078
3946 /* [RC 32] Interrupt register #0 read clear */
3947 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
3948 #define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
3949 /* [RW 27] Parity mask register #0 read/write */
3950 #define PXP_REG_PXP_PRTY_MASK 0x103094
3951 /* [R 26] Parity register #0 read */
3952 #define PXP_REG_PXP_PRTY_STS 0x103088
3953 /* [RC 27] Parity register #0 read clear */
3954 #define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
3955 /* [RW 4] The activity counter initial increment value sent in the load
3956 request */
3957 #define QM_REG_ACTCTRINITVAL_0 0x168040
3958 #define QM_REG_ACTCTRINITVAL_1 0x168044
3959 #define QM_REG_ACTCTRINITVAL_2 0x168048
3960 #define QM_REG_ACTCTRINITVAL_3 0x16804c
3961 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3962 index I represents the physical queue number. The 12 lsbs are ignore and
3963 considered zero so practically there are only 20 bits in this register;
3964 queues 63-0 */
3965 #define QM_REG_BASEADDR 0x168900
3966 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3967 index I represents the physical queue number. The 12 lsbs are ignore and
3968 considered zero so practically there are only 20 bits in this register;
3969 queues 127-64 */
3970 #define QM_REG_BASEADDR_EXT_A 0x16e100
3971 /* [RW 16] The byte credit cost for each task. This value is for both ports */
3972 #define QM_REG_BYTECRDCOST 0x168234
3973 /* [RW 16] The initial byte credit value for both ports. */
3974 #define QM_REG_BYTECRDINITVAL 0x168238
3975 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3976 queue uses port 0 else it uses port 1; queues 31-0 */
3977 #define QM_REG_BYTECRDPORT_LSB 0x168228
3978 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3979 queue uses port 0 else it uses port 1; queues 95-64 */
3980 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
3981 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3982 queue uses port 0 else it uses port 1; queues 63-32 */
3983 #define QM_REG_BYTECRDPORT_MSB 0x168224
3984 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3985 queue uses port 0 else it uses port 1; queues 127-96 */
3986 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
3987 /* [RW 16] The byte credit value that if above the QM is considered almost
3988 full */
3989 #define QM_REG_BYTECREDITAFULLTHR 0x168094
3990 /* [RW 4] The initial credit for interface */
3991 #define QM_REG_CMINITCRD_0 0x1680cc
3992 #define QM_REG_BYTECRDCMDQ_0 0x16e6e8
3993 #define QM_REG_CMINITCRD_1 0x1680d0
3994 #define QM_REG_CMINITCRD_2 0x1680d4
3995 #define QM_REG_CMINITCRD_3 0x1680d8
3996 #define QM_REG_CMINITCRD_4 0x1680dc
3997 #define QM_REG_CMINITCRD_5 0x1680e0
3998 #define QM_REG_CMINITCRD_6 0x1680e4
3999 #define QM_REG_CMINITCRD_7 0x1680e8
4000 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
4001 is masked */
4002 #define QM_REG_CMINTEN 0x1680ec
4003 /* [RW 12] A bit vector which indicates which one of the queues are tied to
4004 interface 0 */
4005 #define QM_REG_CMINTVOQMASK_0 0x1681f4
4006 #define QM_REG_CMINTVOQMASK_1 0x1681f8
4007 #define QM_REG_CMINTVOQMASK_2 0x1681fc
4008 #define QM_REG_CMINTVOQMASK_3 0x168200
4009 #define QM_REG_CMINTVOQMASK_4 0x168204
4010 #define QM_REG_CMINTVOQMASK_5 0x168208
4011 #define QM_REG_CMINTVOQMASK_6 0x16820c
4012 #define QM_REG_CMINTVOQMASK_7 0x168210
4013 /* [RW 20] The number of connections divided by 16 which dictates the size
4014 of each queue which belongs to even function number. */
4015 #define QM_REG_CONNNUM_0 0x168020
4016 /* [R 6] Keep the fill level of the fifo from write client 4 */
4017 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
4018 /* [RW 8] The context regions sent in the CFC load request */
4019 #define QM_REG_CTXREG_0 0x168030
4020 #define QM_REG_CTXREG_1 0x168034
4021 #define QM_REG_CTXREG_2 0x168038
4022 #define QM_REG_CTXREG_3 0x16803c
4023 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
4024 bypass enable */
4025 #define QM_REG_ENBYPVOQMASK 0x16823c
4026 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
4027 physical queue uses the byte credit; queues 31-0 */
4028 #define QM_REG_ENBYTECRD_LSB 0x168220
4029 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
4030 physical queue uses the byte credit; queues 95-64 */
4031 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
4032 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
4033 physical queue uses the byte credit; queues 63-32 */
4034 #define QM_REG_ENBYTECRD_MSB 0x16821c
4035 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
4036 physical queue uses the byte credit; queues 127-96 */
4037 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
4038 /* [RW 4] If cleared then the secondary interface will not be served by the
4039 RR arbiter */
4040 #define QM_REG_ENSEC 0x1680f0
4041 /* [RW 32] NA */
4042 #define QM_REG_FUNCNUMSEL_LSB 0x168230
4043 /* [RW 32] NA */
4044 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
4045 /* [RW 32] A mask register to mask the Almost empty signals which will not
4046 be use for the almost empty indication to the HW block; queues 31:0 */
4047 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
4048 /* [RW 32] A mask register to mask the Almost empty signals which will not
4049 be use for the almost empty indication to the HW block; queues 95-64 */
4050 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
4051 /* [RW 32] A mask register to mask the Almost empty signals which will not
4052 be use for the almost empty indication to the HW block; queues 63:32 */
4053 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
4054 /* [RW 32] A mask register to mask the Almost empty signals which will not
4055 be use for the almost empty indication to the HW block; queues 127-96 */
4056 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
4057 /* [RW 4] The number of outstanding request to CFC */
4058 #define QM_REG_OUTLDREQ 0x168804
4059 /* [RC 1] A flag to indicate that overflow error occurred in one of the
4060 queues. */
4061 #define QM_REG_OVFERROR 0x16805c
4062 /* [RC 7] the Q where the overflow occurs */
4063 #define QM_REG_OVFQNUM 0x168058
4064 /* [R 16] Pause state for physical queues 15-0 */
4065 #define QM_REG_PAUSESTATE0 0x168410
4066 /* [R 16] Pause state for physical queues 31-16 */
4067 #define QM_REG_PAUSESTATE1 0x168414
4068 /* [R 16] Pause state for physical queues 47-32 */
4069 #define QM_REG_PAUSESTATE2 0x16e684
4070 /* [R 16] Pause state for physical queues 63-48 */
4071 #define QM_REG_PAUSESTATE3 0x16e688
4072 /* [R 16] Pause state for physical queues 79-64 */
4073 #define QM_REG_PAUSESTATE4 0x16e68c
4074 /* [R 16] Pause state for physical queues 95-80 */
4075 #define QM_REG_PAUSESTATE5 0x16e690
4076 /* [R 16] Pause state for physical queues 111-96 */
4077 #define QM_REG_PAUSESTATE6 0x16e694
4078 /* [R 16] Pause state for physical queues 127-112 */
4079 #define QM_REG_PAUSESTATE7 0x16e698
4080 /* [RW 2] The PCI attributes field used in the PCI request. */
4081 #define QM_REG_PCIREQAT 0x168054
4082 #define QM_REG_PF_EN 0x16e70c
4083 /* [R 24] The number of tasks stored in the QM for the PF. only even
4084 * functions are valid in E2 (odd I registers will be hard wired to 0) */
4085 #define QM_REG_PF_USG_CNT_0 0x16e040
4086 /* [R 16] NOT USED */
4087 #define QM_REG_PORT0BYTECRD 0x168300
4088 /* [R 16] The byte credit of port 1 */
4089 #define QM_REG_PORT1BYTECRD 0x168304
4090 /* [RW 3] pci function number of queues 15-0 */
4091 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc
4092 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0
4093 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4
4094 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8
4095 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc
4096 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0
4097 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4
4098 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8
4099 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
4100 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
4101 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
4102 #define QM_REG_PTRTBL 0x168a00
4103 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
4104 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
4105 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
4106 #define QM_REG_PTRTBL_EXT_A 0x16e200
4107 /* [RW 2] Interrupt mask register #0 read/write */
4108 #define QM_REG_QM_INT_MASK 0x168444
4109 /* [R 2] Interrupt register #0 read */
4110 #define QM_REG_QM_INT_STS 0x168438
4111 /* [RW 12] Parity mask register #0 read/write */
4112 #define QM_REG_QM_PRTY_MASK 0x168454
4113 /* [R 12] Parity register #0 read */
4114 #define QM_REG_QM_PRTY_STS 0x168448
4115 /* [RC 12] Parity register #0 read clear */
4116 #define QM_REG_QM_PRTY_STS_CLR 0x16844c
4117 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
4118 #define QM_REG_QSTATUS_HIGH 0x16802c
4119 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
4120 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
4121 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
4122 #define QM_REG_QSTATUS_LOW 0x168028
4123 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */
4124 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
4125 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
4126 #define QM_REG_QTASKCTR_0 0x168308
4127 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
4128 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584
4129 /* [RW 4] Queue tied to VOQ */
4130 #define QM_REG_QVOQIDX_0 0x1680f4
4131 #define QM_REG_QVOQIDX_10 0x16811c
4132 #define QM_REG_QVOQIDX_100 0x16e49c
4133 #define QM_REG_QVOQIDX_101 0x16e4a0
4134 #define QM_REG_QVOQIDX_102 0x16e4a4
4135 #define QM_REG_QVOQIDX_103 0x16e4a8
4136 #define QM_REG_QVOQIDX_104 0x16e4ac
4137 #define QM_REG_QVOQIDX_105 0x16e4b0
4138 #define QM_REG_QVOQIDX_106 0x16e4b4
4139 #define QM_REG_QVOQIDX_107 0x16e4b8
4140 #define QM_REG_QVOQIDX_108 0x16e4bc
4141 #define QM_REG_QVOQIDX_109 0x16e4c0
4142 #define QM_REG_QVOQIDX_11 0x168120
4143 #define QM_REG_QVOQIDX_110 0x16e4c4
4144 #define QM_REG_QVOQIDX_111 0x16e4c8
4145 #define QM_REG_QVOQIDX_112 0x16e4cc
4146 #define QM_REG_QVOQIDX_113 0x16e4d0
4147 #define QM_REG_QVOQIDX_114 0x16e4d4
4148 #define QM_REG_QVOQIDX_115 0x16e4d8
4149 #define QM_REG_QVOQIDX_116 0x16e4dc
4150 #define QM_REG_QVOQIDX_117 0x16e4e0
4151 #define QM_REG_QVOQIDX_118 0x16e4e4
4152 #define QM_REG_QVOQIDX_119 0x16e4e8
4153 #define QM_REG_QVOQIDX_12 0x168124
4154 #define QM_REG_QVOQIDX_120 0x16e4ec
4155 #define QM_REG_QVOQIDX_121 0x16e4f0
4156 #define QM_REG_QVOQIDX_122 0x16e4f4
4157 #define QM_REG_QVOQIDX_123 0x16e4f8
4158 #define QM_REG_QVOQIDX_124 0x16e4fc
4159 #define QM_REG_QVOQIDX_125 0x16e500
4160 #define QM_REG_QVOQIDX_126 0x16e504
4161 #define QM_REG_QVOQIDX_127 0x16e508
4162 #define QM_REG_QVOQIDX_13 0x168128
4163 #define QM_REG_QVOQIDX_14 0x16812c
4164 #define QM_REG_QVOQIDX_15 0x168130
4165 #define QM_REG_QVOQIDX_16 0x168134
4166 #define QM_REG_QVOQIDX_17 0x168138
4167 #define QM_REG_QVOQIDX_21 0x168148
4168 #define QM_REG_QVOQIDX_22 0x16814c
4169 #define QM_REG_QVOQIDX_23 0x168150
4170 #define QM_REG_QVOQIDX_24 0x168154
4171 #define QM_REG_QVOQIDX_25 0x168158
4172 #define QM_REG_QVOQIDX_26 0x16815c
4173 #define QM_REG_QVOQIDX_27 0x168160
4174 #define QM_REG_QVOQIDX_28 0x168164
4175 #define QM_REG_QVOQIDX_29 0x168168
4176 #define QM_REG_QVOQIDX_30 0x16816c
4177 #define QM_REG_QVOQIDX_31 0x168170
4178 #define QM_REG_QVOQIDX_32 0x168174
4179 #define QM_REG_QVOQIDX_33 0x168178
4180 #define QM_REG_QVOQIDX_34 0x16817c
4181 #define QM_REG_QVOQIDX_35 0x168180
4182 #define QM_REG_QVOQIDX_36 0x168184
4183 #define QM_REG_QVOQIDX_37 0x168188
4184 #define QM_REG_QVOQIDX_38 0x16818c
4185 #define QM_REG_QVOQIDX_39 0x168190
4186 #define QM_REG_QVOQIDX_40 0x168194
4187 #define QM_REG_QVOQIDX_41 0x168198
4188 #define QM_REG_QVOQIDX_42 0x16819c
4189 #define QM_REG_QVOQIDX_43 0x1681a0
4190 #define QM_REG_QVOQIDX_44 0x1681a4
4191 #define QM_REG_QVOQIDX_45 0x1681a8
4192 #define QM_REG_QVOQIDX_46 0x1681ac
4193 #define QM_REG_QVOQIDX_47 0x1681b0
4194 #define QM_REG_QVOQIDX_48 0x1681b4
4195 #define QM_REG_QVOQIDX_49 0x1681b8
4196 #define QM_REG_QVOQIDX_5 0x168108
4197 #define QM_REG_QVOQIDX_50 0x1681bc
4198 #define QM_REG_QVOQIDX_51 0x1681c0
4199 #define QM_REG_QVOQIDX_52 0x1681c4
4200 #define QM_REG_QVOQIDX_53 0x1681c8
4201 #define QM_REG_QVOQIDX_54 0x1681cc
4202 #define QM_REG_QVOQIDX_55 0x1681d0
4203 #define QM_REG_QVOQIDX_56 0x1681d4
4204 #define QM_REG_QVOQIDX_57 0x1681d8
4205 #define QM_REG_QVOQIDX_58 0x1681dc
4206 #define QM_REG_QVOQIDX_59 0x1681e0
4207 #define QM_REG_QVOQIDX_6 0x16810c
4208 #define QM_REG_QVOQIDX_60 0x1681e4
4209 #define QM_REG_QVOQIDX_61 0x1681e8
4210 #define QM_REG_QVOQIDX_62 0x1681ec
4211 #define QM_REG_QVOQIDX_63 0x1681f0
4212 #define QM_REG_QVOQIDX_64 0x16e40c
4213 #define QM_REG_QVOQIDX_65 0x16e410
4214 #define QM_REG_QVOQIDX_69 0x16e420
4215 #define QM_REG_QVOQIDX_7 0x168110
4216 #define QM_REG_QVOQIDX_70 0x16e424
4217 #define QM_REG_QVOQIDX_71 0x16e428
4218 #define QM_REG_QVOQIDX_72 0x16e42c
4219 #define QM_REG_QVOQIDX_73 0x16e430
4220 #define QM_REG_QVOQIDX_74 0x16e434
4221 #define QM_REG_QVOQIDX_75 0x16e438
4222 #define QM_REG_QVOQIDX_76 0x16e43c
4223 #define QM_REG_QVOQIDX_77 0x16e440
4224 #define QM_REG_QVOQIDX_78 0x16e444
4225 #define QM_REG_QVOQIDX_79 0x16e448
4226 #define QM_REG_QVOQIDX_8 0x168114
4227 #define QM_REG_QVOQIDX_80 0x16e44c
4228 #define QM_REG_QVOQIDX_81 0x16e450
4229 #define QM_REG_QVOQIDX_85 0x16e460
4230 #define QM_REG_QVOQIDX_86 0x16e464
4231 #define QM_REG_QVOQIDX_87 0x16e468
4232 #define QM_REG_QVOQIDX_88 0x16e46c
4233 #define QM_REG_QVOQIDX_89 0x16e470
4234 #define QM_REG_QVOQIDX_9 0x168118
4235 #define QM_REG_QVOQIDX_90 0x16e474
4236 #define QM_REG_QVOQIDX_91 0x16e478
4237 #define QM_REG_QVOQIDX_92 0x16e47c
4238 #define QM_REG_QVOQIDX_93 0x16e480
4239 #define QM_REG_QVOQIDX_94 0x16e484
4240 #define QM_REG_QVOQIDX_95 0x16e488
4241 #define QM_REG_QVOQIDX_96 0x16e48c
4242 #define QM_REG_QVOQIDX_97 0x16e490
4243 #define QM_REG_QVOQIDX_98 0x16e494
4244 #define QM_REG_QVOQIDX_99 0x16e498
4245 /* [RW 1] Initialization bit command */
4246 #define QM_REG_SOFT_RESET 0x168428
4247 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
4248 #define QM_REG_TASKCRDCOST_0 0x16809c
4249 #define QM_REG_TASKCRDCOST_1 0x1680a0
4250 #define QM_REG_TASKCRDCOST_2 0x1680a4
4251 #define QM_REG_TASKCRDCOST_4 0x1680ac
4252 #define QM_REG_TASKCRDCOST_5 0x1680b0
4253 /* [R 6] Keep the fill level of the fifo from write client 3 */
4254 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
4255 /* [R 6] Keep the fill level of the fifo from write client 2 */
4256 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
4257 /* [RC 32] Credit update error register */
4258 #define QM_REG_VOQCRDERRREG 0x168408
4259 /* [R 16] The credit value for each VOQ */
4260 #define QM_REG_VOQCREDIT_0 0x1682d0
4261 #define QM_REG_VOQCREDIT_1 0x1682d4
4262 #define QM_REG_VOQCREDIT_4 0x1682e0
4263 /* [RW 16] The credit value that if above the QM is considered almost full */
4264 #define QM_REG_VOQCREDITAFULLTHR 0x168090
4265 /* [RW 16] The init and maximum credit for each VoQ */
4266 #define QM_REG_VOQINITCREDIT_0 0x168060
4267 #define QM_REG_VOQINITCREDIT_1 0x168064
4268 #define QM_REG_VOQINITCREDIT_2 0x168068
4269 #define QM_REG_VOQINITCREDIT_4 0x168070
4270 #define QM_REG_VOQINITCREDIT_5 0x168074
4271 /* [RW 1] The port of which VOQ belongs */
4272 #define QM_REG_VOQPORT_0 0x1682a0
4273 #define QM_REG_VOQPORT_1 0x1682a4
4274 #define QM_REG_VOQPORT_2 0x1682a8
4275 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4276 #define QM_REG_VOQQMASK_0_LSB 0x168240
4277 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4278 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
4279 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4280 #define QM_REG_VOQQMASK_0_MSB 0x168244
4281 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4282 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
4283 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4284 #define QM_REG_VOQQMASK_10_LSB 0x168290
4285 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4286 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
4287 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4288 #define QM_REG_VOQQMASK_10_MSB 0x168294
4289 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4290 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
4291 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4292 #define QM_REG_VOQQMASK_11_LSB 0x168298
4293 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4294 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
4295 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4296 #define QM_REG_VOQQMASK_11_MSB 0x16829c
4297 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4298 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
4299 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4300 #define QM_REG_VOQQMASK_1_LSB 0x168248
4301 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4302 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
4303 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4304 #define QM_REG_VOQQMASK_1_MSB 0x16824c
4305 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4306 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
4307 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4308 #define QM_REG_VOQQMASK_2_LSB 0x168250
4309 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4310 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
4311 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4312 #define QM_REG_VOQQMASK_2_MSB 0x168254
4313 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4314 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
4315 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4316 #define QM_REG_VOQQMASK_3_LSB 0x168258
4317 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4318 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
4319 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4320 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
4321 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4322 #define QM_REG_VOQQMASK_4_LSB 0x168260
4323 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4324 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
4325 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4326 #define QM_REG_VOQQMASK_4_MSB 0x168264
4327 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4328 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
4329 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4330 #define QM_REG_VOQQMASK_5_LSB 0x168268
4331 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4332 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
4333 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4334 #define QM_REG_VOQQMASK_5_MSB 0x16826c
4335 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4336 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
4337 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4338 #define QM_REG_VOQQMASK_6_LSB 0x168270
4339 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4340 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
4341 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4342 #define QM_REG_VOQQMASK_6_MSB 0x168274
4343 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4344 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
4345 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4346 #define QM_REG_VOQQMASK_7_LSB 0x168278
4347 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4348 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
4349 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4350 #define QM_REG_VOQQMASK_7_MSB 0x16827c
4351 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4352 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
4353 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4354 #define QM_REG_VOQQMASK_8_LSB 0x168280
4355 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4356 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
4357 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4358 #define QM_REG_VOQQMASK_8_MSB 0x168284
4359 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4360 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
4361 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4362 #define QM_REG_VOQQMASK_9_LSB 0x168288
4363 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4364 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
4365 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4366 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
4367 /* [RW 32] Wrr weights */
4368 #define QM_REG_WRRWEIGHTS_0 0x16880c
4369 #define QM_REG_WRRWEIGHTS_1 0x168810
4370 #define QM_REG_WRRWEIGHTS_10 0x168814
4371 #define QM_REG_WRRWEIGHTS_11 0x168818
4372 #define QM_REG_WRRWEIGHTS_12 0x16881c
4373 #define QM_REG_WRRWEIGHTS_13 0x168820
4374 #define QM_REG_WRRWEIGHTS_14 0x168824
4375 #define QM_REG_WRRWEIGHTS_15 0x168828
4376 #define QM_REG_WRRWEIGHTS_16 0x16e000
4377 #define QM_REG_WRRWEIGHTS_17 0x16e004
4378 #define QM_REG_WRRWEIGHTS_18 0x16e008
4379 #define QM_REG_WRRWEIGHTS_19 0x16e00c
4380 #define QM_REG_WRRWEIGHTS_2 0x16882c
4381 #define QM_REG_WRRWEIGHTS_20 0x16e010
4382 #define QM_REG_WRRWEIGHTS_21 0x16e014
4383 #define QM_REG_WRRWEIGHTS_22 0x16e018
4384 #define QM_REG_WRRWEIGHTS_23 0x16e01c
4385 #define QM_REG_WRRWEIGHTS_24 0x16e020
4386 #define QM_REG_WRRWEIGHTS_25 0x16e024
4387 #define QM_REG_WRRWEIGHTS_26 0x16e028
4388 #define QM_REG_WRRWEIGHTS_27 0x16e02c
4389 #define QM_REG_WRRWEIGHTS_28 0x16e030
4390 #define QM_REG_WRRWEIGHTS_29 0x16e034
4391 #define QM_REG_WRRWEIGHTS_3 0x168830
4392 #define QM_REG_WRRWEIGHTS_30 0x16e038
4393 #define QM_REG_WRRWEIGHTS_31 0x16e03c
4394 #define QM_REG_WRRWEIGHTS_4 0x168834
4395 #define QM_REG_WRRWEIGHTS_5 0x168838
4396 #define QM_REG_WRRWEIGHTS_6 0x16883c
4397 #define QM_REG_WRRWEIGHTS_7 0x168840
4398 #define QM_REG_WRRWEIGHTS_8 0x168844
4399 #define QM_REG_WRRWEIGHTS_9 0x168848
4400 /* [R 6] Keep the fill level of the fifo from write client 1 */
4401 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
4402 /* [W 1] reset to parity interrupt */
4403 #define SEM_FAST_REG_PARITY_RST 0x18840
4404 #define SRC_REG_COUNTFREE0 0x40500
4405 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
4406 ports. If set the searcher support 8 functions. */
4407 #define SRC_REG_E1HMF_ENABLE 0x404cc
4408 #define SRC_REG_FIRSTFREE0 0x40510
4409 #define SRC_REG_KEYRSS0_0 0x40408
4410 #define SRC_REG_KEYRSS0_7 0x40424
4411 #define SRC_REG_KEYRSS1_9 0x40454
4412 #define SRC_REG_KEYSEARCH_0 0x40458
4413 #define SRC_REG_KEYSEARCH_1 0x4045c
4414 #define SRC_REG_KEYSEARCH_2 0x40460
4415 #define SRC_REG_KEYSEARCH_3 0x40464
4416 #define SRC_REG_KEYSEARCH_4 0x40468
4417 #define SRC_REG_KEYSEARCH_5 0x4046c
4418 #define SRC_REG_KEYSEARCH_6 0x40470
4419 #define SRC_REG_KEYSEARCH_7 0x40474
4420 #define SRC_REG_KEYSEARCH_8 0x40478
4421 #define SRC_REG_KEYSEARCH_9 0x4047c
4422 #define SRC_REG_LASTFREE0 0x40530
4423 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
4424 /* [RW 1] Reset internal state machines. */
4425 #define SRC_REG_SOFT_RST 0x4049c
4426 /* [R 3] Interrupt register #0 read */
4427 #define SRC_REG_SRC_INT_STS 0x404ac
4428 /* [RW 3] Parity mask register #0 read/write */
4429 #define SRC_REG_SRC_PRTY_MASK 0x404c8
4430 /* [R 3] Parity register #0 read */
4431 #define SRC_REG_SRC_PRTY_STS 0x404bc
4432 /* [RC 3] Parity register #0 read clear */
4433 #define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
4434 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
4435 #define TCM_REG_CAM_OCCUP 0x5017c
4436 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4437 disregarded; valid output is deasserted; all other signals are treated as
4438 usual; if 1 - normal activity. */
4439 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
4440 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4441 are disregarded; all other signals are treated as usual; if 1 - normal
4442 activity. */
4443 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
4444 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4445 disregarded; valid output is deasserted; all other signals are treated as
4446 usual; if 1 - normal activity. */
4447 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
4448 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4449 input is disregarded; all other signals are treated as usual; if 1 -
4450 normal activity. */
4451 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
4452 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4453 the initial credit value; read returns the current value of the credit
4454 counter. Must be initialized to 1 at start-up. */
4455 #define TCM_REG_CFC_INIT_CRD 0x50204
4456 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4457 weight 8 (the most prioritised); 1 stands for weight 1(least
4458 prioritised); 2 stands for weight 2; tc. */
4459 #define TCM_REG_CP_WEIGHT 0x500c0
4460 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4461 disregarded; acknowledge output is deasserted; all other signals are
4462 treated as usual; if 1 - normal activity. */
4463 #define TCM_REG_CSEM_IFEN 0x5002c
4464 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
4465 interface. */
4466 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
4467 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4468 weight 8 (the most prioritised); 1 stands for weight 1(least
4469 prioritised); 2 stands for weight 2; tc. */
4470 #define TCM_REG_CSEM_WEIGHT 0x500bc
4471 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
4472 #define TCM_REG_ERR_EVNT_ID 0x500a0
4473 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4474 #define TCM_REG_ERR_TCM_HDR 0x5009c
4475 /* [RW 8] The Event ID for Timers expiration. */
4476 #define TCM_REG_EXPR_EVNT_ID 0x500a4
4477 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4478 writes the initial credit value; read returns the current value of the
4479 credit counter. Must be initialized to 64 at start-up. */
4480 #define TCM_REG_FIC0_INIT_CRD 0x5020c
4481 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4482 writes the initial credit value; read returns the current value of the
4483 credit counter. Must be initialized to 64 at start-up. */
4484 #define TCM_REG_FIC1_INIT_CRD 0x50210
4485 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4486 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
4487 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
4488 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
4489 #define TCM_REG_GR_ARB_TYPE 0x50114
4490 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4491 highest priority is 3. It is supposed that the Store channel is the
4492 compliment of the other 3 groups. */
4493 #define TCM_REG_GR_LD0_PR 0x5011c
4494 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4495 highest priority is 3. It is supposed that the Store channel is the
4496 compliment of the other 3 groups. */
4497 #define TCM_REG_GR_LD1_PR 0x50120
4498 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
4499 sent to STORM; for a specific connection type. The double REG-pairs are
4500 used to align to STORM context row size of 128 bits. The offset of these
4501 data in the STORM context is always 0. Index _i stands for the connection
4502 type (one of 16). */
4503 #define TCM_REG_N_SM_CTX_LD_0 0x50050
4504 #define TCM_REG_N_SM_CTX_LD_1 0x50054
4505 #define TCM_REG_N_SM_CTX_LD_2 0x50058
4506 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
4507 #define TCM_REG_N_SM_CTX_LD_4 0x50060
4508 #define TCM_REG_N_SM_CTX_LD_5 0x50064
4509 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4510 acknowledge output is deasserted; all other signals are treated as usual;
4511 if 1 - normal activity. */
4512 #define TCM_REG_PBF_IFEN 0x50024
4513 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
4514 interface. */
4515 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
4516 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4517 weight 8 (the most prioritised); 1 stands for weight 1(least
4518 prioritised); 2 stands for weight 2; tc. */
4519 #define TCM_REG_PBF_WEIGHT 0x500b4
4520 #define TCM_REG_PHYS_QNUM0_0 0x500e0
4521 #define TCM_REG_PHYS_QNUM0_1 0x500e4
4522 #define TCM_REG_PHYS_QNUM1_0 0x500e8
4523 #define TCM_REG_PHYS_QNUM1_1 0x500ec
4524 #define TCM_REG_PHYS_QNUM2_0 0x500f0
4525 #define TCM_REG_PHYS_QNUM2_1 0x500f4
4526 #define TCM_REG_PHYS_QNUM3_0 0x500f8
4527 #define TCM_REG_PHYS_QNUM3_1 0x500fc
4528 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
4529 acknowledge output is deasserted; all other signals are treated as usual;
4530 if 1 - normal activity. */
4531 #define TCM_REG_PRS_IFEN 0x50020
4532 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
4533 interface. */
4534 #define TCM_REG_PRS_LENGTH_MIS 0x50168
4535 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
4536 weight 8 (the most prioritised); 1 stands for weight 1(least
4537 prioritised); 2 stands for weight 2; tc. */
4538 #define TCM_REG_PRS_WEIGHT 0x500b0
4539 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4540 #define TCM_REG_STOP_EVNT_ID 0x500a8
4541 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
4542 interface. */
4543 #define TCM_REG_STORM_LENGTH_MIS 0x50160
4544 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4545 disregarded; acknowledge output is deasserted; all other signals are
4546 treated as usual; if 1 - normal activity. */
4547 #define TCM_REG_STORM_TCM_IFEN 0x50010
4548 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4549 weight 8 (the most prioritised); 1 stands for weight 1(least
4550 prioritised); 2 stands for weight 2; tc. */
4551 #define TCM_REG_STORM_WEIGHT 0x500ac
4552 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4553 acknowledge output is deasserted; all other signals are treated as usual;
4554 if 1 - normal activity. */
4555 #define TCM_REG_TCM_CFC_IFEN 0x50040
4556 /* [RW 11] Interrupt mask register #0 read/write */
4557 #define TCM_REG_TCM_INT_MASK 0x501dc
4558 /* [R 11] Interrupt register #0 read */
4559 #define TCM_REG_TCM_INT_STS 0x501d0
4560 /* [RW 27] Parity mask register #0 read/write */
4561 #define TCM_REG_TCM_PRTY_MASK 0x501ec
4562 /* [R 27] Parity register #0 read */
4563 #define TCM_REG_TCM_PRTY_STS 0x501e0
4564 /* [RC 27] Parity register #0 read clear */
4565 #define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
4566 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
4567 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4568 Is used to determine the number of the AG context REG-pairs written back;
4569 when the input message Reg1WbFlg isn't set. */
4570 #define TCM_REG_TCM_REG0_SZ 0x500d8
4571 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4572 disregarded; valid is deasserted; all other signals are treated as usual;
4573 if 1 - normal activity. */
4574 #define TCM_REG_TCM_STORM0_IFEN 0x50004
4575 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4576 disregarded; valid is deasserted; all other signals are treated as usual;
4577 if 1 - normal activity. */
4578 #define TCM_REG_TCM_STORM1_IFEN 0x50008
4579 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4580 disregarded; valid is deasserted; all other signals are treated as usual;
4581 if 1 - normal activity. */
4582 #define TCM_REG_TCM_TQM_IFEN 0x5000c
4583 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4584 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
4585 /* [RW 28] The CM header for Timers expiration command. */
4586 #define TCM_REG_TM_TCM_HDR 0x50098
4587 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4588 disregarded; acknowledge output is deasserted; all other signals are
4589 treated as usual; if 1 - normal activity. */
4590 #define TCM_REG_TM_TCM_IFEN 0x5001c
4591 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4592 weight 8 (the most prioritised); 1 stands for weight 1(least
4593 prioritised); 2 stands for weight 2; tc. */
4594 #define TCM_REG_TM_WEIGHT 0x500d0
4595 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4596 the initial credit value; read returns the current value of the credit
4597 counter. Must be initialized to 32 at start-up. */
4598 #define TCM_REG_TQM_INIT_CRD 0x5021c
4599 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4600 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4601 prioritised); 2 stands for weight 2; tc. */
4602 #define TCM_REG_TQM_P_WEIGHT 0x500c8
4603 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4604 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4605 prioritised); 2 stands for weight 2; tc. */
4606 #define TCM_REG_TQM_S_WEIGHT 0x500cc
4607 /* [RW 28] The CM header value for QM request (primary). */
4608 #define TCM_REG_TQM_TCM_HDR_P 0x50090
4609 /* [RW 28] The CM header value for QM request (secondary). */
4610 #define TCM_REG_TQM_TCM_HDR_S 0x50094
4611 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4612 acknowledge output is deasserted; all other signals are treated as usual;
4613 if 1 - normal activity. */
4614 #define TCM_REG_TQM_TCM_IFEN 0x50014
4615 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4616 acknowledge output is deasserted; all other signals are treated as usual;
4617 if 1 - normal activity. */
4618 #define TCM_REG_TSDM_IFEN 0x50018
4619 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
4620 interface. */
4621 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
4622 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4623 weight 8 (the most prioritised); 1 stands for weight 1(least
4624 prioritised); 2 stands for weight 2; tc. */
4625 #define TCM_REG_TSDM_WEIGHT 0x500c4
4626 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4627 disregarded; acknowledge output is deasserted; all other signals are
4628 treated as usual; if 1 - normal activity. */
4629 #define TCM_REG_USEM_IFEN 0x50028
4630 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
4631 interface. */
4632 #define TCM_REG_USEM_LENGTH_MIS 0x50170
4633 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4634 weight 8 (the most prioritised); 1 stands for weight 1(least
4635 prioritised); 2 stands for weight 2; tc. */
4636 #define TCM_REG_USEM_WEIGHT 0x500b8
4637 /* [RW 21] Indirect access to the descriptor table of the XX protection
4638 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
4639 pointer; 20:16] - next pointer. */
4640 #define TCM_REG_XX_DESCR_TABLE 0x50280
4641 #define TCM_REG_XX_DESCR_TABLE_SIZE 29
4642 /* [R 6] Use to read the value of XX protection Free counter. */
4643 #define TCM_REG_XX_FREE 0x50178
4644 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4645 of the Input Stage XX protection buffer by the XX protection pending
4646 messages. Max credit available - 127.Write writes the initial credit
4647 value; read returns the current value of the credit counter. Must be
4648 initialized to 19 at start-up. */
4649 #define TCM_REG_XX_INIT_CRD 0x50220
4650 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
4651 protection. */
4652 #define TCM_REG_XX_MAX_LL_SZ 0x50044
4653 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4654 protection. ~tcm_registers_xx_free.xx_free is read on read. */
4655 #define TCM_REG_XX_MSG_NUM 0x50224
4656 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4657 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
4658 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4659 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
4660 header pointer. */
4661 #define TCM_REG_XX_TABLE 0x50240
4662 /* [RW 4] Load value for cfc ac credit cnt. */
4663 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
4664 /* [RW 4] Load value for cfc cld credit cnt. */
4665 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
4666 /* [RW 8] Client0 context region. */
4667 #define TM_REG_CL0_CONT_REGION 0x164030
4668 /* [RW 8] Client1 context region. */
4669 #define TM_REG_CL1_CONT_REGION 0x164034
4670 /* [RW 8] Client2 context region. */
4671 #define TM_REG_CL2_CONT_REGION 0x164038
4672 /* [RW 2] Client in High priority client number. */
4673 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
4674 /* [RW 4] Load value for clout0 cred cnt. */
4675 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
4676 /* [RW 4] Load value for clout1 cred cnt. */
4677 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
4678 /* [RW 4] Load value for clout2 cred cnt. */
4679 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
4680 /* [RW 1] Enable client0 input. */
4681 #define TM_REG_EN_CL0_INPUT 0x164008
4682 /* [RW 1] Enable client1 input. */
4683 #define TM_REG_EN_CL1_INPUT 0x16400c
4684 /* [RW 1] Enable client2 input. */
4685 #define TM_REG_EN_CL2_INPUT 0x164010
4686 #define TM_REG_EN_LINEAR0_TIMER 0x164014
4687 /* [RW 1] Enable real time counter. */
4688 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
4689 /* [RW 1] Enable for Timers state machines. */
4690 #define TM_REG_EN_TIMERS 0x164000
4691 /* [RW 4] Load value for expiration credit cnt. CFC max number of
4692 outstanding load requests for timers (expiration) context loading. */
4693 #define TM_REG_EXP_CRDCNT_VAL 0x164238
4694 /* [RW 32] Linear0 logic address. */
4695 #define TM_REG_LIN0_LOGIC_ADDR 0x164240
4696 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
4697 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
4698 /* [ST 16] Linear0 Number of scans counter. */
4699 #define TM_REG_LIN0_NUM_SCANS 0x1640a0
4700 /* [WB 64] Linear0 phy address. */
4701 #define TM_REG_LIN0_PHY_ADDR 0x164270
4702 /* [RW 1] Linear0 physical address valid. */
4703 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
4704 #define TM_REG_LIN0_SCAN_ON 0x1640d0
4705 /* [RW 24] Linear0 array scan timeout. */
4706 #define TM_REG_LIN0_SCAN_TIME 0x16403c
4707 #define TM_REG_LIN0_VNIC_UC 0x164128
4708 /* [RW 32] Linear1 logic address. */
4709 #define TM_REG_LIN1_LOGIC_ADDR 0x164250
4710 /* [WB 64] Linear1 phy address. */
4711 #define TM_REG_LIN1_PHY_ADDR 0x164280
4712 /* [RW 1] Linear1 physical address valid. */
4713 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
4714 /* [RW 6] Linear timer set_clear fifo threshold. */
4715 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
4716 /* [RW 2] Load value for pci arbiter credit cnt. */
4717 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
4718 /* [RW 20] The amount of hardware cycles for each timer tick. */
4719 #define TM_REG_TIMER_TICK_SIZE 0x16401c
4720 /* [RW 8] Timers Context region. */
4721 #define TM_REG_TM_CONTEXT_REGION 0x164044
4722 /* [RW 1] Interrupt mask register #0 read/write */
4723 #define TM_REG_TM_INT_MASK 0x1640fc
4724 /* [R 1] Interrupt register #0 read */
4725 #define TM_REG_TM_INT_STS 0x1640f0
4726 /* [RW 7] Parity mask register #0 read/write */
4727 #define TM_REG_TM_PRTY_MASK 0x16410c
4728 /* [R 7] Parity register #0 read */
4729 #define TM_REG_TM_PRTY_STS 0x164100
4730 /* [RC 7] Parity register #0 read clear */
4731 #define TM_REG_TM_PRTY_STS_CLR 0x164104
4732 /* [RW 8] The event id for aggregated interrupt 0 */
4733 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
4734 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c
4735 #define TSDM_REG_AGG_INT_EVENT_2 0x42040
4736 #define TSDM_REG_AGG_INT_EVENT_3 0x42044
4737 #define TSDM_REG_AGG_INT_EVENT_4 0x42048
4738 /* [RW 1] The T bit for aggregated interrupt 0 */
4739 #define TSDM_REG_AGG_INT_T_0 0x420b8
4740 #define TSDM_REG_AGG_INT_T_1 0x420bc
4741 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4742 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
4743 /* [RW 16] The maximum value of the completion counter #0 */
4744 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
4745 /* [RW 16] The maximum value of the completion counter #1 */
4746 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
4747 /* [RW 16] The maximum value of the completion counter #2 */
4748 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
4749 /* [RW 16] The maximum value of the completion counter #3 */
4750 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
4751 /* [RW 13] The start address in the internal RAM for the completion
4752 counters. */
4753 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
4754 #define TSDM_REG_ENABLE_IN1 0x42238
4755 #define TSDM_REG_ENABLE_IN2 0x4223c
4756 #define TSDM_REG_ENABLE_OUT1 0x42240
4757 #define TSDM_REG_ENABLE_OUT2 0x42244
4758 /* [RW 4] The initial number of messages that can be sent to the pxp control
4759 interface without receiving any ACK. */
4760 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
4761 /* [ST 32] The number of ACK after placement messages received */
4762 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
4763 /* [ST 32] The number of packet end messages received from the parser */
4764 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
4765 /* [ST 32] The number of requests received from the pxp async if */
4766 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
4767 /* [ST 32] The number of commands received in queue 0 */
4768 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
4769 /* [ST 32] The number of commands received in queue 10 */
4770 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
4771 /* [ST 32] The number of commands received in queue 11 */
4772 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
4773 /* [ST 32] The number of commands received in queue 1 */
4774 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
4775 /* [ST 32] The number of commands received in queue 3 */
4776 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
4777 /* [ST 32] The number of commands received in queue 4 */
4778 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
4779 /* [ST 32] The number of commands received in queue 5 */
4780 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
4781 /* [ST 32] The number of commands received in queue 6 */
4782 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
4783 /* [ST 32] The number of commands received in queue 7 */
4784 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
4785 /* [ST 32] The number of commands received in queue 8 */
4786 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
4787 /* [ST 32] The number of commands received in queue 9 */
4788 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
4789 /* [RW 13] The start address in the internal RAM for the packet end message */
4790 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
4791 /* [RW 13] The start address in the internal RAM for queue counters */
4792 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
4793 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4794 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
4795 /* [R 1] parser fifo empty in sdm_sync block */
4796 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
4797 /* [R 1] parser serial fifo empty in sdm_sync block */
4798 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
4799 /* [RW 32] Tick for timer counter. Applicable only when
4800 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4801 #define TSDM_REG_TIMER_TICK 0x42000
4802 /* [RW 32] Interrupt mask register #0 read/write */
4803 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
4804 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
4805 /* [R 32] Interrupt register #0 read */
4806 #define TSDM_REG_TSDM_INT_STS_0 0x42290
4807 #define TSDM_REG_TSDM_INT_STS_1 0x422a0
4808 /* [RW 11] Parity mask register #0 read/write */
4809 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
4810 /* [R 11] Parity register #0 read */
4811 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
4812 /* [RC 11] Parity register #0 read clear */
4813 #define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
4814 /* [RW 5] The number of time_slots in the arbitration cycle */
4815 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
4816 /* [RW 3] The source that is associated with arbitration element 0. Source
4817 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4818 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4819 #define TSEM_REG_ARB_ELEMENT0 0x180020
4820 /* [RW 3] The source that is associated with arbitration element 1. Source
4821 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4822 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4823 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
4824 #define TSEM_REG_ARB_ELEMENT1 0x180024
4825 /* [RW 3] The source that is associated with arbitration element 2. Source
4826 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4827 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4828 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4829 and ~tsem_registers_arb_element1.arb_element1 */
4830 #define TSEM_REG_ARB_ELEMENT2 0x180028
4831 /* [RW 3] The source that is associated with arbitration element 3. Source
4832 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4833 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4834 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
4835 ~tsem_registers_arb_element1.arb_element1 and
4836 ~tsem_registers_arb_element2.arb_element2 */
4837 #define TSEM_REG_ARB_ELEMENT3 0x18002c
4838 /* [RW 3] The source that is associated with arbitration element 4. Source
4839 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4840 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4841 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4842 and ~tsem_registers_arb_element1.arb_element1 and
4843 ~tsem_registers_arb_element2.arb_element2 and
4844 ~tsem_registers_arb_element3.arb_element3 */
4845 #define TSEM_REG_ARB_ELEMENT4 0x180030
4846 #define TSEM_REG_ENABLE_IN 0x1800a4
4847 #define TSEM_REG_ENABLE_OUT 0x1800a8
4848 /* [RW 32] This address space contains all registers and memories that are
4849 placed in SEM_FAST block. The SEM_FAST registers are described in
4850 appendix B. In order to access the sem_fast registers the base address
4851 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4852 #define TSEM_REG_FAST_MEMORY 0x1a0000
4853 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4854 by the microcode */
4855 #define TSEM_REG_FIC0_DISABLE 0x180224
4856 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4857 by the microcode */
4858 #define TSEM_REG_FIC1_DISABLE 0x180234
4859 /* [RW 15] Interrupt table Read and write access to it is not possible in
4860 the middle of the work */
4861 #define TSEM_REG_INT_TABLE 0x180400
4862 /* [ST 24] Statistics register. The number of messages that entered through
4863 FIC0 */
4864 #define TSEM_REG_MSG_NUM_FIC0 0x180000
4865 /* [ST 24] Statistics register. The number of messages that entered through
4866 FIC1 */
4867 #define TSEM_REG_MSG_NUM_FIC1 0x180004
4868 /* [ST 24] Statistics register. The number of messages that were sent to
4869 FOC0 */
4870 #define TSEM_REG_MSG_NUM_FOC0 0x180008
4871 /* [ST 24] Statistics register. The number of messages that were sent to
4872 FOC1 */
4873 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
4874 /* [ST 24] Statistics register. The number of messages that were sent to
4875 FOC2 */
4876 #define TSEM_REG_MSG_NUM_FOC2 0x180010
4877 /* [ST 24] Statistics register. The number of messages that were sent to
4878 FOC3 */
4879 #define TSEM_REG_MSG_NUM_FOC3 0x180014
4880 /* [RW 1] Disables input messages from the passive buffer May be updated
4881 during run_time by the microcode */
4882 #define TSEM_REG_PAS_DISABLE 0x18024c
4883 /* [WB 128] Debug only. Passive buffer memory */
4884 #define TSEM_REG_PASSIVE_BUFFER 0x181000
4885 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4886 #define TSEM_REG_PRAM 0x1c0000
4887 /* [R 8] Valid sleeping threads indication have bit per thread */
4888 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
4889 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4890 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
4891 /* [RW 8] List of free threads . There is a bit per thread. */
4892 #define TSEM_REG_THREADS_LIST 0x1802e4
4893 /* [RC 32] Parity register #0 read clear */
4894 #define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
4895 #define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
4896 /* [RW 3] The arbitration scheme of time_slot 0 */
4897 #define TSEM_REG_TS_0_AS 0x180038
4898 /* [RW 3] The arbitration scheme of time_slot 10 */
4899 #define TSEM_REG_TS_10_AS 0x180060
4900 /* [RW 3] The arbitration scheme of time_slot 11 */
4901 #define TSEM_REG_TS_11_AS 0x180064
4902 /* [RW 3] The arbitration scheme of time_slot 12 */
4903 #define TSEM_REG_TS_12_AS 0x180068
4904 /* [RW 3] The arbitration scheme of time_slot 13 */
4905 #define TSEM_REG_TS_13_AS 0x18006c
4906 /* [RW 3] The arbitration scheme of time_slot 14 */
4907 #define TSEM_REG_TS_14_AS 0x180070
4908 /* [RW 3] The arbitration scheme of time_slot 15 */
4909 #define TSEM_REG_TS_15_AS 0x180074
4910 /* [RW 3] The arbitration scheme of time_slot 16 */
4911 #define TSEM_REG_TS_16_AS 0x180078
4912 /* [RW 3] The arbitration scheme of time_slot 17 */
4913 #define TSEM_REG_TS_17_AS 0x18007c
4914 /* [RW 3] The arbitration scheme of time_slot 18 */
4915 #define TSEM_REG_TS_18_AS 0x180080
4916 /* [RW 3] The arbitration scheme of time_slot 1 */
4917 #define TSEM_REG_TS_1_AS 0x18003c
4918 /* [RW 3] The arbitration scheme of time_slot 2 */
4919 #define TSEM_REG_TS_2_AS 0x180040
4920 /* [RW 3] The arbitration scheme of time_slot 3 */
4921 #define TSEM_REG_TS_3_AS 0x180044
4922 /* [RW 3] The arbitration scheme of time_slot 4 */
4923 #define TSEM_REG_TS_4_AS 0x180048
4924 /* [RW 3] The arbitration scheme of time_slot 5 */
4925 #define TSEM_REG_TS_5_AS 0x18004c
4926 /* [RW 3] The arbitration scheme of time_slot 6 */
4927 #define TSEM_REG_TS_6_AS 0x180050
4928 /* [RW 3] The arbitration scheme of time_slot 7 */
4929 #define TSEM_REG_TS_7_AS 0x180054
4930 /* [RW 3] The arbitration scheme of time_slot 8 */
4931 #define TSEM_REG_TS_8_AS 0x180058
4932 /* [RW 3] The arbitration scheme of time_slot 9 */
4933 #define TSEM_REG_TS_9_AS 0x18005c
4934 /* [RW 32] Interrupt mask register #0 read/write */
4935 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
4936 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
4937 /* [R 32] Interrupt register #0 read */
4938 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4939 #define TSEM_REG_TSEM_INT_STS_1 0x180104
4940 /* [RW 32] Parity mask register #0 read/write */
4941 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4942 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
4943 /* [R 32] Parity register #0 read */
4944 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4945 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
4946 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4947 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4948 #define TSEM_REG_VFPF_ERR_NUM 0x180380
4949 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4950 * [10:8] of the address should be the offset within the accessed LCID
4951 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4952 * LCID100. The RBC address should be 12'ha64. */
4953 #define UCM_REG_AG_CTX 0xe2000
4954 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4955 #define UCM_REG_CAM_OCCUP 0xe0170
4956 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4957 disregarded; valid output is deasserted; all other signals are treated as
4958 usual; if 1 - normal activity. */
4959 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4960 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4961 are disregarded; all other signals are treated as usual; if 1 - normal
4962 activity. */
4963 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4964 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4965 disregarded; valid output is deasserted; all other signals are treated as
4966 usual; if 1 - normal activity. */
4967 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4968 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4969 input is disregarded; all other signals are treated as usual; if 1 -
4970 normal activity. */
4971 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4972 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4973 the initial credit value; read returns the current value of the credit
4974 counter. Must be initialized to 1 at start-up. */
4975 #define UCM_REG_CFC_INIT_CRD 0xe0204
4976 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4977 weight 8 (the most prioritised); 1 stands for weight 1(least
4978 prioritised); 2 stands for weight 2; tc. */
4979 #define UCM_REG_CP_WEIGHT 0xe00c4
4980 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4981 disregarded; acknowledge output is deasserted; all other signals are
4982 treated as usual; if 1 - normal activity. */
4983 #define UCM_REG_CSEM_IFEN 0xe0028
4984 /* [RC 1] Set when the message length mismatch (relative to last indication)
4985 at the csem interface is detected. */
4986 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4987 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4988 weight 8 (the most prioritised); 1 stands for weight 1(least
4989 prioritised); 2 stands for weight 2; tc. */
4990 #define UCM_REG_CSEM_WEIGHT 0xe00b8
4991 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4992 disregarded; acknowledge output is deasserted; all other signals are
4993 treated as usual; if 1 - normal activity. */
4994 #define UCM_REG_DORQ_IFEN 0xe0030
4995 /* [RC 1] Set when the message length mismatch (relative to last indication)
4996 at the dorq interface is detected. */
4997 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
4998 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4999 weight 8 (the most prioritised); 1 stands for weight 1(least
5000 prioritised); 2 stands for weight 2; tc. */
5001 #define UCM_REG_DORQ_WEIGHT 0xe00c0
5002 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
5003 #define UCM_REG_ERR_EVNT_ID 0xe00a4
5004 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
5005 #define UCM_REG_ERR_UCM_HDR 0xe00a0
5006 /* [RW 8] The Event ID for Timers expiration. */
5007 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
5008 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5009 writes the initial credit value; read returns the current value of the
5010 credit counter. Must be initialized to 64 at start-up. */
5011 #define UCM_REG_FIC0_INIT_CRD 0xe020c
5012 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5013 writes the initial credit value; read returns the current value of the
5014 credit counter. Must be initialized to 64 at start-up. */
5015 #define UCM_REG_FIC1_INIT_CRD 0xe0210
5016 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
5017 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
5018 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
5019 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
5020 #define UCM_REG_GR_ARB_TYPE 0xe0144
5021 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
5022 highest priority is 3. It is supposed that the Store channel group is
5023 compliment to the others. */
5024 #define UCM_REG_GR_LD0_PR 0xe014c
5025 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
5026 highest priority is 3. It is supposed that the Store channel group is
5027 compliment to the others. */
5028 #define UCM_REG_GR_LD1_PR 0xe0150
5029 /* [RW 2] The queue index for invalidate counter flag decision. */
5030 #define UCM_REG_INV_CFLG_Q 0xe00e4
5031 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5032 sent to STORM; for a specific connection type. the double REG-pairs are
5033 used in order to align to STORM context row size of 128 bits. The offset
5034 of these data in the STORM context is always 0. Index _i stands for the
5035 connection type (one of 16). */
5036 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
5037 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
5038 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
5039 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
5040 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
5041 #define UCM_REG_N_SM_CTX_LD_5 0xe0068
5042 #define UCM_REG_PHYS_QNUM0_0 0xe0110
5043 #define UCM_REG_PHYS_QNUM0_1 0xe0114
5044 #define UCM_REG_PHYS_QNUM1_0 0xe0118
5045 #define UCM_REG_PHYS_QNUM1_1 0xe011c
5046 #define UCM_REG_PHYS_QNUM2_0 0xe0120
5047 #define UCM_REG_PHYS_QNUM2_1 0xe0124
5048 #define UCM_REG_PHYS_QNUM3_0 0xe0128
5049 #define UCM_REG_PHYS_QNUM3_1 0xe012c
5050 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
5051 #define UCM_REG_STOP_EVNT_ID 0xe00ac
5052 /* [RC 1] Set when the message length mismatch (relative to last indication)
5053 at the STORM interface is detected. */
5054 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
5055 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5056 disregarded; acknowledge output is deasserted; all other signals are
5057 treated as usual; if 1 - normal activity. */
5058 #define UCM_REG_STORM_UCM_IFEN 0xe0010
5059 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5060 weight 8 (the most prioritised); 1 stands for weight 1(least
5061 prioritised); 2 stands for weight 2; tc. */
5062 #define UCM_REG_STORM_WEIGHT 0xe00b0
5063 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
5064 writes the initial credit value; read returns the current value of the
5065 credit counter. Must be initialized to 4 at start-up. */
5066 #define UCM_REG_TM_INIT_CRD 0xe021c
5067 /* [RW 28] The CM header for Timers expiration command. */
5068 #define UCM_REG_TM_UCM_HDR 0xe009c
5069 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5070 disregarded; acknowledge output is deasserted; all other signals are
5071 treated as usual; if 1 - normal activity. */
5072 #define UCM_REG_TM_UCM_IFEN 0xe001c
5073 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5074 weight 8 (the most prioritised); 1 stands for weight 1(least
5075 prioritised); 2 stands for weight 2; tc. */
5076 #define UCM_REG_TM_WEIGHT 0xe00d4
5077 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5078 disregarded; acknowledge output is deasserted; all other signals are
5079 treated as usual; if 1 - normal activity. */
5080 #define UCM_REG_TSEM_IFEN 0xe0024
5081 /* [RC 1] Set when the message length mismatch (relative to last indication)
5082 at the tsem interface is detected. */
5083 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
5084 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5085 weight 8 (the most prioritised); 1 stands for weight 1(least
5086 prioritised); 2 stands for weight 2; tc. */
5087 #define UCM_REG_TSEM_WEIGHT 0xe00b4
5088 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5089 acknowledge output is deasserted; all other signals are treated as usual;
5090 if 1 - normal activity. */
5091 #define UCM_REG_UCM_CFC_IFEN 0xe0044
5092 /* [RW 11] Interrupt mask register #0 read/write */
5093 #define UCM_REG_UCM_INT_MASK 0xe01d4
5094 /* [R 11] Interrupt register #0 read */
5095 #define UCM_REG_UCM_INT_STS 0xe01c8
5096 /* [RW 27] Parity mask register #0 read/write */
5097 #define UCM_REG_UCM_PRTY_MASK 0xe01e4
5098 /* [R 27] Parity register #0 read */
5099 #define UCM_REG_UCM_PRTY_STS 0xe01d8
5100 /* [RC 27] Parity register #0 read clear */
5101 #define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
5102 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
5103 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5104 Is used to determine the number of the AG context REG-pairs written back;
5105 when the Reg1WbFlg isn't set. */
5106 #define UCM_REG_UCM_REG0_SZ 0xe00dc
5107 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5108 disregarded; valid is deasserted; all other signals are treated as usual;
5109 if 1 - normal activity. */
5110 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
5111 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5112 disregarded; valid is deasserted; all other signals are treated as usual;
5113 if 1 - normal activity. */
5114 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
5115 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5116 disregarded; acknowledge output is deasserted; all other signals are
5117 treated as usual; if 1 - normal activity. */
5118 #define UCM_REG_UCM_TM_IFEN 0xe0020
5119 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5120 disregarded; valid is deasserted; all other signals are treated as usual;
5121 if 1 - normal activity. */
5122 #define UCM_REG_UCM_UQM_IFEN 0xe000c
5123 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
5124 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
5125 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5126 the initial credit value; read returns the current value of the credit
5127 counter. Must be initialized to 32 at start-up. */
5128 #define UCM_REG_UQM_INIT_CRD 0xe0220
5129 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5130 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5131 prioritised); 2 stands for weight 2; tc. */
5132 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
5133 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5134 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5135 prioritised); 2 stands for weight 2; tc. */
5136 #define UCM_REG_UQM_S_WEIGHT 0xe00d0
5137 /* [RW 28] The CM header value for QM request (primary). */
5138 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
5139 /* [RW 28] The CM header value for QM request (secondary). */
5140 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
5141 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5142 acknowledge output is deasserted; all other signals are treated as usual;
5143 if 1 - normal activity. */
5144 #define UCM_REG_UQM_UCM_IFEN 0xe0014
5145 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5146 acknowledge output is deasserted; all other signals are treated as usual;
5147 if 1 - normal activity. */
5148 #define UCM_REG_USDM_IFEN 0xe0018
5149 /* [RC 1] Set when the message length mismatch (relative to last indication)
5150 at the SDM interface is detected. */
5151 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
5152 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5153 weight 8 (the most prioritised); 1 stands for weight 1(least
5154 prioritised); 2 stands for weight 2; tc. */
5155 #define UCM_REG_USDM_WEIGHT 0xe00c8
5156 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
5157 disregarded; acknowledge output is deasserted; all other signals are
5158 treated as usual; if 1 - normal activity. */
5159 #define UCM_REG_XSEM_IFEN 0xe002c
5160 /* [RC 1] Set when the message length mismatch (relative to last indication)
5161 at the xsem interface isdetected. */
5162 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
5163 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
5164 weight 8 (the most prioritised); 1 stands for weight 1(least
5165 prioritised); 2 stands for weight 2; tc. */
5166 #define UCM_REG_XSEM_WEIGHT 0xe00bc
5167 /* [RW 20] Indirect access to the descriptor table of the XX protection
5168 mechanism. The fields are:[5:0] - message length; 14:6] - message
5169 pointer; 19:15] - next pointer. */
5170 #define UCM_REG_XX_DESCR_TABLE 0xe0280
5171 #define UCM_REG_XX_DESCR_TABLE_SIZE 27
5172 /* [R 6] Use to read the XX protection Free counter. */
5173 #define UCM_REG_XX_FREE 0xe016c
5174 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
5175 of the Input Stage XX protection buffer by the XX protection pending
5176 messages. Write writes the initial credit value; read returns the current
5177 value of the credit counter. Must be initialized to 12 at start-up. */
5178 #define UCM_REG_XX_INIT_CRD 0xe0224
5179 /* [RW 6] The maximum number of pending messages; which may be stored in XX
5180 protection. ~ucm_registers_xx_free.xx_free read on read. */
5181 #define UCM_REG_XX_MSG_NUM 0xe0228
5182 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
5183 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
5184 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
5185 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
5186 header pointer. */
5187 #define UCM_REG_XX_TABLE 0xe0300
5188 #define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1<<10)
5189 #define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28)
5190 #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)
5191 #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)
5192 #define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)
5193 #define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8)
5194 #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)
5195 #define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)
5196 #define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)
5197 #define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)
5198 #define UMAC_REG_COMMAND_CONFIG 0x8
5199 /* [RW 16] This is the duration for which MAC must wait to go back to ACTIVE
5200 * state from LPI state when it receives packet for transmission. The
5201 * decrement unit is 1 micro-second. */
5202 #define UMAC_REG_EEE_WAKE_TIMER 0x6c
5203 /* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers
5204 * to bit 17 of the MAC address etc. */
5205 #define UMAC_REG_MAC_ADDR0 0xc
5206 /* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1
5207 * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */
5208 #define UMAC_REG_MAC_ADDR1 0x10
5209 /* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
5210 * logic to check frames. */
5211 #define UMAC_REG_MAXFR 0x14
5212 #define UMAC_REG_UMAC_EEE_CTRL 0x64
5213 #define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1<<3)
5214 /* [RW 8] The event id for aggregated interrupt 0 */
5215 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
5216 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
5217 #define USDM_REG_AGG_INT_EVENT_2 0xc4040
5218 #define USDM_REG_AGG_INT_EVENT_4 0xc4048
5219 #define USDM_REG_AGG_INT_EVENT_5 0xc404c
5220 #define USDM_REG_AGG_INT_EVENT_6 0xc4050
5221 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5222 or auto-mask-mode (1) */
5223 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
5224 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
5225 #define USDM_REG_AGG_INT_MODE_4 0xc41c8
5226 #define USDM_REG_AGG_INT_MODE_5 0xc41cc
5227 #define USDM_REG_AGG_INT_MODE_6 0xc41d0
5228 /* [RW 1] The T bit for aggregated interrupt 5 */
5229 #define USDM_REG_AGG_INT_T_5 0xc40cc
5230 #define USDM_REG_AGG_INT_T_6 0xc40d0
5231 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
5232 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
5233 /* [RW 16] The maximum value of the completion counter #0 */
5234 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
5235 /* [RW 16] The maximum value of the completion counter #1 */
5236 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
5237 /* [RW 16] The maximum value of the completion counter #2 */
5238 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
5239 /* [RW 16] The maximum value of the completion counter #3 */
5240 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
5241 /* [RW 13] The start address in the internal RAM for the completion
5242 counters. */
5243 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
5244 #define USDM_REG_ENABLE_IN1 0xc4238
5245 #define USDM_REG_ENABLE_IN2 0xc423c
5246 #define USDM_REG_ENABLE_OUT1 0xc4240
5247 #define USDM_REG_ENABLE_OUT2 0xc4244
5248 /* [RW 4] The initial number of messages that can be sent to the pxp control
5249 interface without receiving any ACK. */
5250 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
5251 /* [ST 32] The number of ACK after placement messages received */
5252 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
5253 /* [ST 32] The number of packet end messages received from the parser */
5254 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
5255 /* [ST 32] The number of requests received from the pxp async if */
5256 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
5257 /* [ST 32] The number of commands received in queue 0 */
5258 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
5259 /* [ST 32] The number of commands received in queue 10 */
5260 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
5261 /* [ST 32] The number of commands received in queue 11 */
5262 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
5263 /* [ST 32] The number of commands received in queue 1 */
5264 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
5265 /* [ST 32] The number of commands received in queue 2 */
5266 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
5267 /* [ST 32] The number of commands received in queue 3 */
5268 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
5269 /* [ST 32] The number of commands received in queue 4 */
5270 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
5271 /* [ST 32] The number of commands received in queue 5 */
5272 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
5273 /* [ST 32] The number of commands received in queue 6 */
5274 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
5275 /* [ST 32] The number of commands received in queue 7 */
5276 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
5277 /* [ST 32] The number of commands received in queue 8 */
5278 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
5279 /* [ST 32] The number of commands received in queue 9 */
5280 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
5281 /* [RW 13] The start address in the internal RAM for the packet end message */
5282 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
5283 /* [RW 13] The start address in the internal RAM for queue counters */
5284 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
5285 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
5286 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
5287 /* [R 1] parser fifo empty in sdm_sync block */
5288 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
5289 /* [R 1] parser serial fifo empty in sdm_sync block */
5290 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
5291 /* [RW 32] Tick for timer counter. Applicable only when
5292 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
5293 #define USDM_REG_TIMER_TICK 0xc4000
5294 /* [RW 32] Interrupt mask register #0 read/write */
5295 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
5296 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
5297 /* [R 32] Interrupt register #0 read */
5298 #define USDM_REG_USDM_INT_STS_0 0xc4294
5299 #define USDM_REG_USDM_INT_STS_1 0xc42a4
5300 /* [RW 11] Parity mask register #0 read/write */
5301 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
5302 /* [R 11] Parity register #0 read */
5303 #define USDM_REG_USDM_PRTY_STS 0xc42b4
5304 /* [RC 11] Parity register #0 read clear */
5305 #define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
5306 /* [RW 5] The number of time_slots in the arbitration cycle */
5307 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
5308 /* [RW 3] The source that is associated with arbitration element 0. Source
5309 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5310 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5311 #define USEM_REG_ARB_ELEMENT0 0x300020
5312 /* [RW 3] The source that is associated with arbitration element 1. Source
5313 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5314 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5315 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
5316 #define USEM_REG_ARB_ELEMENT1 0x300024
5317 /* [RW 3] The source that is associated with arbitration element 2. Source
5318 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5319 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5320 Could not be equal to register ~usem_registers_arb_element0.arb_element0
5321 and ~usem_registers_arb_element1.arb_element1 */
5322 #define USEM_REG_ARB_ELEMENT2 0x300028
5323 /* [RW 3] The source that is associated with arbitration element 3. Source
5324 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5325 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5326 not be equal to register ~usem_registers_arb_element0.arb_element0 and
5327 ~usem_registers_arb_element1.arb_element1 and
5328 ~usem_registers_arb_element2.arb_element2 */
5329 #define USEM_REG_ARB_ELEMENT3 0x30002c
5330 /* [RW 3] The source that is associated with arbitration element 4. Source
5331 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5332 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5333 Could not be equal to register ~usem_registers_arb_element0.arb_element0
5334 and ~usem_registers_arb_element1.arb_element1 and
5335 ~usem_registers_arb_element2.arb_element2 and
5336 ~usem_registers_arb_element3.arb_element3 */
5337 #define USEM_REG_ARB_ELEMENT4 0x300030
5338 #define USEM_REG_ENABLE_IN 0x3000a4
5339 #define USEM_REG_ENABLE_OUT 0x3000a8
5340 /* [RW 32] This address space contains all registers and memories that are
5341 placed in SEM_FAST block. The SEM_FAST registers are described in
5342 appendix B. In order to access the sem_fast registers the base address
5343 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
5344 #define USEM_REG_FAST_MEMORY 0x320000
5345 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
5346 by the microcode */
5347 #define USEM_REG_FIC0_DISABLE 0x300224
5348 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
5349 by the microcode */
5350 #define USEM_REG_FIC1_DISABLE 0x300234
5351 /* [RW 15] Interrupt table Read and write access to it is not possible in
5352 the middle of the work */
5353 #define USEM_REG_INT_TABLE 0x300400
5354 /* [ST 24] Statistics register. The number of messages that entered through
5355 FIC0 */
5356 #define USEM_REG_MSG_NUM_FIC0 0x300000
5357 /* [ST 24] Statistics register. The number of messages that entered through
5358 FIC1 */
5359 #define USEM_REG_MSG_NUM_FIC1 0x300004
5360 /* [ST 24] Statistics register. The number of messages that were sent to
5361 FOC0 */
5362 #define USEM_REG_MSG_NUM_FOC0 0x300008
5363 /* [ST 24] Statistics register. The number of messages that were sent to
5364 FOC1 */
5365 #define USEM_REG_MSG_NUM_FOC1 0x30000c
5366 /* [ST 24] Statistics register. The number of messages that were sent to
5367 FOC2 */
5368 #define USEM_REG_MSG_NUM_FOC2 0x300010
5369 /* [ST 24] Statistics register. The number of messages that were sent to
5370 FOC3 */
5371 #define USEM_REG_MSG_NUM_FOC3 0x300014
5372 /* [RW 1] Disables input messages from the passive buffer May be updated
5373 during run_time by the microcode */
5374 #define USEM_REG_PAS_DISABLE 0x30024c
5375 /* [WB 128] Debug only. Passive buffer memory */
5376 #define USEM_REG_PASSIVE_BUFFER 0x302000
5377 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5378 #define USEM_REG_PRAM 0x340000
5379 /* [R 16] Valid sleeping threads indication have bit per thread */
5380 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
5381 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5382 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
5383 /* [RW 16] List of free threads . There is a bit per thread. */
5384 #define USEM_REG_THREADS_LIST 0x3002e4
5385 /* [RW 3] The arbitration scheme of time_slot 0 */
5386 #define USEM_REG_TS_0_AS 0x300038
5387 /* [RW 3] The arbitration scheme of time_slot 10 */
5388 #define USEM_REG_TS_10_AS 0x300060
5389 /* [RW 3] The arbitration scheme of time_slot 11 */
5390 #define USEM_REG_TS_11_AS 0x300064
5391 /* [RW 3] The arbitration scheme of time_slot 12 */
5392 #define USEM_REG_TS_12_AS 0x300068
5393 /* [RW 3] The arbitration scheme of time_slot 13 */
5394 #define USEM_REG_TS_13_AS 0x30006c
5395 /* [RW 3] The arbitration scheme of time_slot 14 */
5396 #define USEM_REG_TS_14_AS 0x300070
5397 /* [RW 3] The arbitration scheme of time_slot 15 */
5398 #define USEM_REG_TS_15_AS 0x300074
5399 /* [RW 3] The arbitration scheme of time_slot 16 */
5400 #define USEM_REG_TS_16_AS 0x300078
5401 /* [RW 3] The arbitration scheme of time_slot 17 */
5402 #define USEM_REG_TS_17_AS 0x30007c
5403 /* [RW 3] The arbitration scheme of time_slot 18 */
5404 #define USEM_REG_TS_18_AS 0x300080
5405 /* [RW 3] The arbitration scheme of time_slot 1 */
5406 #define USEM_REG_TS_1_AS 0x30003c
5407 /* [RW 3] The arbitration scheme of time_slot 2 */
5408 #define USEM_REG_TS_2_AS 0x300040
5409 /* [RW 3] The arbitration scheme of time_slot 3 */
5410 #define USEM_REG_TS_3_AS 0x300044
5411 /* [RW 3] The arbitration scheme of time_slot 4 */
5412 #define USEM_REG_TS_4_AS 0x300048
5413 /* [RW 3] The arbitration scheme of time_slot 5 */
5414 #define USEM_REG_TS_5_AS 0x30004c
5415 /* [RW 3] The arbitration scheme of time_slot 6 */
5416 #define USEM_REG_TS_6_AS 0x300050
5417 /* [RW 3] The arbitration scheme of time_slot 7 */
5418 #define USEM_REG_TS_7_AS 0x300054
5419 /* [RW 3] The arbitration scheme of time_slot 8 */
5420 #define USEM_REG_TS_8_AS 0x300058
5421 /* [RW 3] The arbitration scheme of time_slot 9 */
5422 #define USEM_REG_TS_9_AS 0x30005c
5423 /* [RW 32] Interrupt mask register #0 read/write */
5424 #define USEM_REG_USEM_INT_MASK_0 0x300110
5425 #define USEM_REG_USEM_INT_MASK_1 0x300120
5426 /* [R 32] Interrupt register #0 read */
5427 #define USEM_REG_USEM_INT_STS_0 0x300104
5428 #define USEM_REG_USEM_INT_STS_1 0x300114
5429 /* [RW 32] Parity mask register #0 read/write */
5430 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
5431 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
5432 /* [R 32] Parity register #0 read */
5433 #define USEM_REG_USEM_PRTY_STS_0 0x300124
5434 #define USEM_REG_USEM_PRTY_STS_1 0x300134
5435 /* [RC 32] Parity register #0 read clear */
5436 #define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
5437 #define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
5438 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5439 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5440 #define USEM_REG_VFPF_ERR_NUM 0x300380
5441 #define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
5442 #define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
5443 #define VFC_REG_MEMORIES_RST 0x1943c
5444 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
5445 * [12:8] of the address should be the offset within the accessed LCID
5446 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
5447 * LCID100. The RBC address should be 13'ha64. */
5448 #define XCM_REG_AG_CTX 0x28000
5449 /* [RW 2] The queue index for registration on Aux1 counter flag. */
5450 #define XCM_REG_AUX1_Q 0x20134
5451 /* [RW 2] Per each decision rule the queue index to register to. */
5452 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
5453 /* [R 5] Used to read the XX protection CAM occupancy counter. */
5454 #define XCM_REG_CAM_OCCUP 0x20244
5455 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
5456 disregarded; valid output is deasserted; all other signals are treated as
5457 usual; if 1 - normal activity. */
5458 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
5459 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
5460 are disregarded; all other signals are treated as usual; if 1 - normal
5461 activity. */
5462 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
5463 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
5464 disregarded; valid output is deasserted; all other signals are treated as
5465 usual; if 1 - normal activity. */
5466 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
5467 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
5468 input is disregarded; all other signals are treated as usual; if 1 -
5469 normal activity. */
5470 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
5471 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
5472 the initial credit value; read returns the current value of the credit
5473 counter. Must be initialized to 1 at start-up. */
5474 #define XCM_REG_CFC_INIT_CRD 0x20404
5475 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
5476 weight 8 (the most prioritised); 1 stands for weight 1(least
5477 prioritised); 2 stands for weight 2; tc. */
5478 #define XCM_REG_CP_WEIGHT 0x200dc
5479 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
5480 disregarded; acknowledge output is deasserted; all other signals are
5481 treated as usual; if 1 - normal activity. */
5482 #define XCM_REG_CSEM_IFEN 0x20028
5483 /* [RC 1] Set at message length mismatch (relative to last indication) at
5484 the csem interface. */
5485 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
5486 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
5487 weight 8 (the most prioritised); 1 stands for weight 1(least
5488 prioritised); 2 stands for weight 2; tc. */
5489 #define XCM_REG_CSEM_WEIGHT 0x200c4
5490 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
5491 disregarded; acknowledge output is deasserted; all other signals are
5492 treated as usual; if 1 - normal activity. */
5493 #define XCM_REG_DORQ_IFEN 0x20030
5494 /* [RC 1] Set at message length mismatch (relative to last indication) at
5495 the dorq interface. */
5496 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
5497 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
5498 weight 8 (the most prioritised); 1 stands for weight 1(least
5499 prioritised); 2 stands for weight 2; tc. */
5500 #define XCM_REG_DORQ_WEIGHT 0x200cc
5501 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
5502 #define XCM_REG_ERR_EVNT_ID 0x200b0
5503 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
5504 #define XCM_REG_ERR_XCM_HDR 0x200ac
5505 /* [RW 8] The Event ID for Timers expiration. */
5506 #define XCM_REG_EXPR_EVNT_ID 0x200b4
5507 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5508 writes the initial credit value; read returns the current value of the
5509 credit counter. Must be initialized to 64 at start-up. */
5510 #define XCM_REG_FIC0_INIT_CRD 0x2040c
5511 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5512 writes the initial credit value; read returns the current value of the
5513 credit counter. Must be initialized to 64 at start-up. */
5514 #define XCM_REG_FIC1_INIT_CRD 0x20410
5515 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
5516 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
5517 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
5518 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
5519 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
5520 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
5521 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
5522 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
5523 #define XCM_REG_GR_ARB_TYPE 0x2020c
5524 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
5525 highest priority is 3. It is supposed that the Channel group is the
5526 compliment of the other 3 groups. */
5527 #define XCM_REG_GR_LD0_PR 0x20214
5528 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
5529 highest priority is 3. It is supposed that the Channel group is the
5530 compliment of the other 3 groups. */
5531 #define XCM_REG_GR_LD1_PR 0x20218
5532 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
5533 disregarded; acknowledge output is deasserted; all other signals are
5534 treated as usual; if 1 - normal activity. */
5535 #define XCM_REG_NIG0_IFEN 0x20038
5536 /* [RC 1] Set at message length mismatch (relative to last indication) at
5537 the nig0 interface. */
5538 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
5539 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
5540 weight 8 (the most prioritised); 1 stands for weight 1(least
5541 prioritised); 2 stands for weight 2; tc. */
5542 #define XCM_REG_NIG0_WEIGHT 0x200d4
5543 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
5544 disregarded; acknowledge output is deasserted; all other signals are
5545 treated as usual; if 1 - normal activity. */
5546 #define XCM_REG_NIG1_IFEN 0x2003c
5547 /* [RC 1] Set at message length mismatch (relative to last indication) at
5548 the nig1 interface. */
5549 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
5550 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5551 sent to STORM; for a specific connection type. The double REG-pairs are
5552 used in order to align to STORM context row size of 128 bits. The offset
5553 of these data in the STORM context is always 0. Index _i stands for the
5554 connection type (one of 16). */
5555 #define XCM_REG_N_SM_CTX_LD_0 0x20060
5556 #define XCM_REG_N_SM_CTX_LD_1 0x20064
5557 #define XCM_REG_N_SM_CTX_LD_2 0x20068
5558 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
5559 #define XCM_REG_N_SM_CTX_LD_4 0x20070
5560 #define XCM_REG_N_SM_CTX_LD_5 0x20074
5561 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
5562 acknowledge output is deasserted; all other signals are treated as usual;
5563 if 1 - normal activity. */
5564 #define XCM_REG_PBF_IFEN 0x20034
5565 /* [RC 1] Set at message length mismatch (relative to last indication) at
5566 the pbf interface. */
5567 #define XCM_REG_PBF_LENGTH_MIS 0x20234
5568 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
5569 weight 8 (the most prioritised); 1 stands for weight 1(least
5570 prioritised); 2 stands for weight 2; tc. */
5571 #define XCM_REG_PBF_WEIGHT 0x200d0
5572 #define XCM_REG_PHYS_QNUM3_0 0x20100
5573 #define XCM_REG_PHYS_QNUM3_1 0x20104
5574 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
5575 #define XCM_REG_STOP_EVNT_ID 0x200b8
5576 /* [RC 1] Set at message length mismatch (relative to last indication) at
5577 the STORM interface. */
5578 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
5579 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5580 weight 8 (the most prioritised); 1 stands for weight 1(least
5581 prioritised); 2 stands for weight 2; tc. */
5582 #define XCM_REG_STORM_WEIGHT 0x200bc
5583 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5584 disregarded; acknowledge output is deasserted; all other signals are
5585 treated as usual; if 1 - normal activity. */
5586 #define XCM_REG_STORM_XCM_IFEN 0x20010
5587 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
5588 writes the initial credit value; read returns the current value of the
5589 credit counter. Must be initialized to 4 at start-up. */
5590 #define XCM_REG_TM_INIT_CRD 0x2041c
5591 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5592 weight 8 (the most prioritised); 1 stands for weight 1(least
5593 prioritised); 2 stands for weight 2; tc. */
5594 #define XCM_REG_TM_WEIGHT 0x200ec
5595 /* [RW 28] The CM header for Timers expiration command. */
5596 #define XCM_REG_TM_XCM_HDR 0x200a8
5597 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5598 disregarded; acknowledge output is deasserted; all other signals are
5599 treated as usual; if 1 - normal activity. */
5600 #define XCM_REG_TM_XCM_IFEN 0x2001c
5601 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5602 disregarded; acknowledge output is deasserted; all other signals are
5603 treated as usual; if 1 - normal activity. */
5604 #define XCM_REG_TSEM_IFEN 0x20024
5605 /* [RC 1] Set at message length mismatch (relative to last indication) at
5606 the tsem interface. */
5607 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
5608 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5609 weight 8 (the most prioritised); 1 stands for weight 1(least
5610 prioritised); 2 stands for weight 2; tc. */
5611 #define XCM_REG_TSEM_WEIGHT 0x200c0
5612 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
5613 #define XCM_REG_UNA_GT_NXT_Q 0x20120
5614 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
5615 disregarded; acknowledge output is deasserted; all other signals are
5616 treated as usual; if 1 - normal activity. */
5617 #define XCM_REG_USEM_IFEN 0x2002c
5618 /* [RC 1] Message length mismatch (relative to last indication) at the usem
5619 interface. */
5620 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
5621 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
5622 weight 8 (the most prioritised); 1 stands for weight 1(least
5623 prioritised); 2 stands for weight 2; tc. */
5624 #define XCM_REG_USEM_WEIGHT 0x200c8
5625 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
5626 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
5627 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
5628 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
5629 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
5630 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
5631 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
5632 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
5633 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
5634 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
5635 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
5636 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
5637 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5638 acknowledge output is deasserted; all other signals are treated as usual;
5639 if 1 - normal activity. */
5640 #define XCM_REG_XCM_CFC_IFEN 0x20050
5641 /* [RW 14] Interrupt mask register #0 read/write */
5642 #define XCM_REG_XCM_INT_MASK 0x202b4
5643 /* [R 14] Interrupt register #0 read */
5644 #define XCM_REG_XCM_INT_STS 0x202a8
5645 /* [RW 30] Parity mask register #0 read/write */
5646 #define XCM_REG_XCM_PRTY_MASK 0x202c4
5647 /* [R 30] Parity register #0 read */
5648 #define XCM_REG_XCM_PRTY_STS 0x202b8
5649 /* [RC 30] Parity register #0 read clear */
5650 #define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
5651
5652 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
5653 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5654 Is used to determine the number of the AG context REG-pairs written back;
5655 when the Reg1WbFlg isn't set. */
5656 #define XCM_REG_XCM_REG0_SZ 0x200f4
5657 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5658 disregarded; valid is deasserted; all other signals are treated as usual;
5659 if 1 - normal activity. */
5660 #define XCM_REG_XCM_STORM0_IFEN 0x20004
5661 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5662 disregarded; valid is deasserted; all other signals are treated as usual;
5663 if 1 - normal activity. */
5664 #define XCM_REG_XCM_STORM1_IFEN 0x20008
5665 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5666 disregarded; acknowledge output is deasserted; all other signals are
5667 treated as usual; if 1 - normal activity. */
5668 #define XCM_REG_XCM_TM_IFEN 0x20020
5669 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5670 disregarded; valid is deasserted; all other signals are treated as usual;
5671 if 1 - normal activity. */
5672 #define XCM_REG_XCM_XQM_IFEN 0x2000c
5673 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
5674 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
5675 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
5676 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
5677 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5678 the initial credit value; read returns the current value of the credit
5679 counter. Must be initialized to 32 at start-up. */
5680 #define XCM_REG_XQM_INIT_CRD 0x20420
5681 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5682 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5683 prioritised); 2 stands for weight 2; tc. */
5684 #define XCM_REG_XQM_P_WEIGHT 0x200e4
5685 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5686 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5687 prioritised); 2 stands for weight 2; tc. */
5688 #define XCM_REG_XQM_S_WEIGHT 0x200e8
5689 /* [RW 28] The CM header value for QM request (primary). */
5690 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
5691 /* [RW 28] The CM header value for QM request (secondary). */
5692 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
5693 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5694 acknowledge output is deasserted; all other signals are treated as usual;
5695 if 1 - normal activity. */
5696 #define XCM_REG_XQM_XCM_IFEN 0x20014
5697 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5698 acknowledge output is deasserted; all other signals are treated as usual;
5699 if 1 - normal activity. */
5700 #define XCM_REG_XSDM_IFEN 0x20018
5701 /* [RC 1] Set at message length mismatch (relative to last indication) at
5702 the SDM interface. */
5703 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
5704 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5705 weight 8 (the most prioritised); 1 stands for weight 1(least
5706 prioritised); 2 stands for weight 2; tc. */
5707 #define XCM_REG_XSDM_WEIGHT 0x200e0
5708 /* [RW 17] Indirect access to the descriptor table of the XX protection
5709 mechanism. The fields are: [5:0] - message length; 11:6] - message
5710 pointer; 16:12] - next pointer. */
5711 #define XCM_REG_XX_DESCR_TABLE 0x20480
5712 #define XCM_REG_XX_DESCR_TABLE_SIZE 32
5713 /* [R 6] Used to read the XX protection Free counter. */
5714 #define XCM_REG_XX_FREE 0x20240
5715 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
5716 of the Input Stage XX protection buffer by the XX protection pending
5717 messages. Max credit available - 3.Write writes the initial credit value;
5718 read returns the current value of the credit counter. Must be initialized
5719 to 2 at start-up. */
5720 #define XCM_REG_XX_INIT_CRD 0x20424
5721 /* [RW 6] The maximum number of pending messages; which may be stored in XX
5722 protection. ~xcm_registers_xx_free.xx_free read on read. */
5723 #define XCM_REG_XX_MSG_NUM 0x20428
5724 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
5725 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
5726 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)
5727 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)
5728 #define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2)
5729 #define XMAC_CTRL_REG_RX_EN (0x1<<1)
5730 #define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)
5731 #define XMAC_CTRL_REG_TX_EN (0x1<<0)
5732 #define XMAC_CTRL_REG_XLGMII_ALIGN_ENB (0x1<<7)
5733 #define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
5734 #define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
5735 #define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1<<1)
5736 #define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
5737 #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
5738 #define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
5739 #define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)
5740 #define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60
5741 #define XMAC_REG_CTRL 0
5742 /* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5743 * packets transmitted by the MAC */
5744 #define XMAC_REG_CTRL_SA_HI 0x2c
5745 /* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5746 * packets transmitted by the MAC */
5747 #define XMAC_REG_CTRL_SA_LO 0x28
5748 #define XMAC_REG_EEE_CTRL 0xd8
5749 #define XMAC_REG_EEE_TIMERS_HI 0xe4
5750 #define XMAC_REG_PAUSE_CTRL 0x68
5751 #define XMAC_REG_PFC_CTRL 0x70
5752 #define XMAC_REG_PFC_CTRL_HI 0x74
5753 #define XMAC_REG_RX_LSS_CTRL 0x50
5754 #define XMAC_REG_RX_LSS_STATUS 0x58
5755 /* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
5756 * CRC in strip mode */
5757 #define XMAC_REG_RX_MAX_SIZE 0x40
5758 #define XMAC_REG_TX_CTRL 0x20
5759 #define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE (0x1<<0)
5760 #define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE (0x1<<1)
5761 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
5762 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
5763 header pointer. */
5764 #define XCM_REG_XX_TABLE 0x20500
5765 /* [RW 8] The event id for aggregated interrupt 0 */
5766 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
5767 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
5768 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
5769 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
5770 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
5771 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
5772 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
5773 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
5774 #define XSDM_REG_AGG_INT_EVENT_3 0x166044
5775 #define XSDM_REG_AGG_INT_EVENT_4 0x166048
5776 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c
5777 #define XSDM_REG_AGG_INT_EVENT_6 0x166050
5778 #define XSDM_REG_AGG_INT_EVENT_7 0x166054
5779 #define XSDM_REG_AGG_INT_EVENT_8 0x166058
5780 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c
5781 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5782 or auto-mask-mode (1) */
5783 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
5784 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
5785 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
5786 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
5787 /* [RW 16] The maximum value of the completion counter #0 */
5788 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
5789 /* [RW 16] The maximum value of the completion counter #1 */
5790 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
5791 /* [RW 16] The maximum value of the completion counter #2 */
5792 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
5793 /* [RW 16] The maximum value of the completion counter #3 */
5794 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
5795 /* [RW 13] The start address in the internal RAM for the completion
5796 counters. */
5797 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
5798 #define XSDM_REG_ENABLE_IN1 0x166238
5799 #define XSDM_REG_ENABLE_IN2 0x16623c
5800 #define XSDM_REG_ENABLE_OUT1 0x166240
5801 #define XSDM_REG_ENABLE_OUT2 0x166244
5802 /* [RW 4] The initial number of messages that can be sent to the pxp control
5803 interface without receiving any ACK. */
5804 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
5805 /* [ST 32] The number of ACK after placement messages received */
5806 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
5807 /* [ST 32] The number of packet end messages received from the parser */
5808 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
5809 /* [ST 32] The number of requests received from the pxp async if */
5810 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
5811 /* [ST 32] The number of commands received in queue 0 */
5812 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
5813 /* [ST 32] The number of commands received in queue 10 */
5814 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
5815 /* [ST 32] The number of commands received in queue 11 */
5816 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
5817 /* [ST 32] The number of commands received in queue 1 */
5818 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
5819 /* [ST 32] The number of commands received in queue 3 */
5820 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
5821 /* [ST 32] The number of commands received in queue 4 */
5822 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
5823 /* [ST 32] The number of commands received in queue 5 */
5824 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
5825 /* [ST 32] The number of commands received in queue 6 */
5826 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
5827 /* [ST 32] The number of commands received in queue 7 */
5828 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
5829 /* [ST 32] The number of commands received in queue 8 */
5830 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
5831 /* [ST 32] The number of commands received in queue 9 */
5832 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
5833 /* [RW 13] The start address in the internal RAM for queue counters */
5834 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
5835 /* [W 17] Generate an operation after completion; bit-16 is
5836 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
5837 * bits 4:0 are the T124Param[4:0] */
5838 #define XSDM_REG_OPERATION_GEN 0x1664c4
5839 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
5840 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
5841 /* [R 1] parser fifo empty in sdm_sync block */
5842 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
5843 /* [R 1] parser serial fifo empty in sdm_sync block */
5844 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
5845 /* [RW 32] Tick for timer counter. Applicable only when
5846 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
5847 #define XSDM_REG_TIMER_TICK 0x166000
5848 /* [RW 32] Interrupt mask register #0 read/write */
5849 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
5850 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
5851 /* [R 32] Interrupt register #0 read */
5852 #define XSDM_REG_XSDM_INT_STS_0 0x166290
5853 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0
5854 /* [RW 11] Parity mask register #0 read/write */
5855 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
5856 /* [R 11] Parity register #0 read */
5857 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
5858 /* [RC 11] Parity register #0 read clear */
5859 #define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
5860 /* [RW 5] The number of time_slots in the arbitration cycle */
5861 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
5862 /* [RW 3] The source that is associated with arbitration element 0. Source
5863 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5864 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5865 #define XSEM_REG_ARB_ELEMENT0 0x280020
5866 /* [RW 3] The source that is associated with arbitration element 1. Source
5867 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5868 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5869 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
5870 #define XSEM_REG_ARB_ELEMENT1 0x280024
5871 /* [RW 3] The source that is associated with arbitration element 2. Source
5872 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5873 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5874 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5875 and ~xsem_registers_arb_element1.arb_element1 */
5876 #define XSEM_REG_ARB_ELEMENT2 0x280028
5877 /* [RW 3] The source that is associated with arbitration element 3. Source
5878 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5879 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5880 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
5881 ~xsem_registers_arb_element1.arb_element1 and
5882 ~xsem_registers_arb_element2.arb_element2 */
5883 #define XSEM_REG_ARB_ELEMENT3 0x28002c
5884 /* [RW 3] The source that is associated with arbitration element 4. Source
5885 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5886 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5887 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5888 and ~xsem_registers_arb_element1.arb_element1 and
5889 ~xsem_registers_arb_element2.arb_element2 and
5890 ~xsem_registers_arb_element3.arb_element3 */
5891 #define XSEM_REG_ARB_ELEMENT4 0x280030
5892 #define XSEM_REG_ENABLE_IN 0x2800a4
5893 #define XSEM_REG_ENABLE_OUT 0x2800a8
5894 /* [RW 32] This address space contains all registers and memories that are
5895 placed in SEM_FAST block. The SEM_FAST registers are described in
5896 appendix B. In order to access the sem_fast registers the base address
5897 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
5898 #define XSEM_REG_FAST_MEMORY 0x2a0000
5899 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
5900 by the microcode */
5901 #define XSEM_REG_FIC0_DISABLE 0x280224
5902 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
5903 by the microcode */
5904 #define XSEM_REG_FIC1_DISABLE 0x280234
5905 /* [RW 15] Interrupt table Read and write access to it is not possible in
5906 the middle of the work */
5907 #define XSEM_REG_INT_TABLE 0x280400
5908 /* [ST 24] Statistics register. The number of messages that entered through
5909 FIC0 */
5910 #define XSEM_REG_MSG_NUM_FIC0 0x280000
5911 /* [ST 24] Statistics register. The number of messages that entered through
5912 FIC1 */
5913 #define XSEM_REG_MSG_NUM_FIC1 0x280004
5914 /* [ST 24] Statistics register. The number of messages that were sent to
5915 FOC0 */
5916 #define XSEM_REG_MSG_NUM_FOC0 0x280008
5917 /* [ST 24] Statistics register. The number of messages that were sent to
5918 FOC1 */
5919 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
5920 /* [ST 24] Statistics register. The number of messages that were sent to
5921 FOC2 */
5922 #define XSEM_REG_MSG_NUM_FOC2 0x280010
5923 /* [ST 24] Statistics register. The number of messages that were sent to
5924 FOC3 */
5925 #define XSEM_REG_MSG_NUM_FOC3 0x280014
5926 /* [RW 1] Disables input messages from the passive buffer May be updated
5927 during run_time by the microcode */
5928 #define XSEM_REG_PAS_DISABLE 0x28024c
5929 /* [WB 128] Debug only. Passive buffer memory */
5930 #define XSEM_REG_PASSIVE_BUFFER 0x282000
5931 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5932 #define XSEM_REG_PRAM 0x2c0000
5933 /* [R 16] Valid sleeping threads indication have bit per thread */
5934 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
5935 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5936 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
5937 /* [RW 16] List of free threads . There is a bit per thread. */
5938 #define XSEM_REG_THREADS_LIST 0x2802e4
5939 /* [RW 3] The arbitration scheme of time_slot 0 */
5940 #define XSEM_REG_TS_0_AS 0x280038
5941 /* [RW 3] The arbitration scheme of time_slot 10 */
5942 #define XSEM_REG_TS_10_AS 0x280060
5943 /* [RW 3] The arbitration scheme of time_slot 11 */
5944 #define XSEM_REG_TS_11_AS 0x280064
5945 /* [RW 3] The arbitration scheme of time_slot 12 */
5946 #define XSEM_REG_TS_12_AS 0x280068
5947 /* [RW 3] The arbitration scheme of time_slot 13 */
5948 #define XSEM_REG_TS_13_AS 0x28006c
5949 /* [RW 3] The arbitration scheme of time_slot 14 */
5950 #define XSEM_REG_TS_14_AS 0x280070
5951 /* [RW 3] The arbitration scheme of time_slot 15 */
5952 #define XSEM_REG_TS_15_AS 0x280074
5953 /* [RW 3] The arbitration scheme of time_slot 16 */
5954 #define XSEM_REG_TS_16_AS 0x280078
5955 /* [RW 3] The arbitration scheme of time_slot 17 */
5956 #define XSEM_REG_TS_17_AS 0x28007c
5957 /* [RW 3] The arbitration scheme of time_slot 18 */
5958 #define XSEM_REG_TS_18_AS 0x280080
5959 /* [RW 3] The arbitration scheme of time_slot 1 */
5960 #define XSEM_REG_TS_1_AS 0x28003c
5961 /* [RW 3] The arbitration scheme of time_slot 2 */
5962 #define XSEM_REG_TS_2_AS 0x280040
5963 /* [RW 3] The arbitration scheme of time_slot 3 */
5964 #define XSEM_REG_TS_3_AS 0x280044
5965 /* [RW 3] The arbitration scheme of time_slot 4 */
5966 #define XSEM_REG_TS_4_AS 0x280048
5967 /* [RW 3] The arbitration scheme of time_slot 5 */
5968 #define XSEM_REG_TS_5_AS 0x28004c
5969 /* [RW 3] The arbitration scheme of time_slot 6 */
5970 #define XSEM_REG_TS_6_AS 0x280050
5971 /* [RW 3] The arbitration scheme of time_slot 7 */
5972 #define XSEM_REG_TS_7_AS 0x280054
5973 /* [RW 3] The arbitration scheme of time_slot 8 */
5974 #define XSEM_REG_TS_8_AS 0x280058
5975 /* [RW 3] The arbitration scheme of time_slot 9 */
5976 #define XSEM_REG_TS_9_AS 0x28005c
5977 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5978 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5979 #define XSEM_REG_VFPF_ERR_NUM 0x280380
5980 /* [RW 32] Interrupt mask register #0 read/write */
5981 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
5982 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
5983 /* [R 32] Interrupt register #0 read */
5984 #define XSEM_REG_XSEM_INT_STS_0 0x280104
5985 #define XSEM_REG_XSEM_INT_STS_1 0x280114
5986 /* [RW 32] Parity mask register #0 read/write */
5987 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
5988 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
5989 /* [R 32] Parity register #0 read */
5990 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5991 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
5992 /* [RC 32] Parity register #0 read clear */
5993 #define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
5994 #define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
5995 #define MCPR_ACCESS_LOCK_LOCK (1L<<31)
5996 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5997 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5998 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5999 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
6000 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
6001 #define MCPR_NVM_COMMAND_DONE (1L<<3)
6002 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
6003 #define MCPR_NVM_COMMAND_LAST (1L<<8)
6004 #define MCPR_NVM_COMMAND_WR (1L<<5)
6005 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
6006 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
6007 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
6008 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
6009 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
6010 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
6011 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
6012 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
6013 #define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
6014 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
6015 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
6016 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
6017 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
6018 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
6019 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
6020 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
6021 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
6022 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
6023 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
6024 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
6025 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
6026 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
6027 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
6028 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
6029 #define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
6030 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
6031 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
6032 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
6033 #define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3)
6034 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
6035 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
6036 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
6037 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
6038 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
6039 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
6040 #define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3)
6041 #define EMAC_LED_1000MB_OVERRIDE (1L<<1)
6042 #define EMAC_LED_100MB_OVERRIDE (1L<<2)
6043 #define EMAC_LED_10MB_OVERRIDE (1L<<3)
6044 #define EMAC_LED_2500MB_OVERRIDE (1L<<12)
6045 #define EMAC_LED_OVERRIDE (1L<<0)
6046 #define EMAC_LED_TRAFFIC (1L<<6)
6047 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
6048 #define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
6049 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
6050 #define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
6051 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
6052 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
6053 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
6054 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
6055 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
6056 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
6057 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
6058 #define EMAC_MDIO_STATUS_10MB (1L<<1)
6059 #define EMAC_MODE_25G_MODE (1L<<5)
6060 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
6061 #define EMAC_MODE_PORT_GMII (2L<<2)
6062 #define EMAC_MODE_PORT_MII (1L<<2)
6063 #define EMAC_MODE_PORT_MII_10M (3L<<2)
6064 #define EMAC_MODE_RESET (1L<<0)
6065 #define EMAC_REG_EMAC_LED 0xc
6066 #define EMAC_REG_EMAC_MAC_MATCH 0x10
6067 #define EMAC_REG_EMAC_MDIO_COMM 0xac
6068 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
6069 #define EMAC_REG_EMAC_MDIO_STATUS 0xb0
6070 #define EMAC_REG_EMAC_MODE 0x0
6071 #define EMAC_REG_EMAC_RX_MODE 0xc8
6072 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
6073 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
6074 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
6075 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
6076 #define EMAC_REG_EMAC_TX_MODE 0xbc
6077 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
6078 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
6079 #define EMAC_REG_RX_PFC_MODE 0x320
6080 #define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
6081 #define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
6082 #define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
6083 #define EMAC_REG_RX_PFC_PARAM 0x324
6084 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
6085 #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
6086 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
6087 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
6088 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
6089 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
6090 #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
6091 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
6092 #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
6093 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
6094 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
6095 #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
6096 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
6097 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
6098 #define EMAC_RX_MODE_RESET (1L<<0)
6099 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
6100 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
6101 #define EMAC_TX_MODE_FLOW_EN (1L<<4)
6102 #define EMAC_TX_MODE_RESET (1L<<0)
6103 #define MISC_REGISTERS_GPIO_0 0
6104 #define MISC_REGISTERS_GPIO_1 1
6105 #define MISC_REGISTERS_GPIO_2 2
6106 #define MISC_REGISTERS_GPIO_3 3
6107 #define MISC_REGISTERS_GPIO_CLR_POS 16
6108 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
6109 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
6110 #define MISC_REGISTERS_GPIO_HIGH 1
6111 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
6112 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24
6113 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
6114 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
6115 #define MISC_REGISTERS_GPIO_INT_SET_POS 16
6116 #define MISC_REGISTERS_GPIO_LOW 0
6117 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
6118 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
6119 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
6120 #define MISC_REGISTERS_GPIO_SET_POS 8
6121 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
6122 #define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
6123 #define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19)
6124 #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
6125 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
6126 #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
6127 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
6128 #define MISC_REGISTERS_RESET_REG_1_RST_XSEM (0x1<<22)
6129 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
6130 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
6131 #define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24)
6132 #define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25)
6133 #define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19)
6134 #define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17)
6135 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
6136 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
6137 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
6138 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
6139 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
6140 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
6141 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
6142 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
6143 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
6144 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
6145 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
6146 #define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
6147 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
6148 #define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)
6149 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
6150 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
6151 #define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20)
6152 #define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21)
6153 #define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22)
6154 #define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23)
6155 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
6156 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
6157 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
6158 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
6159 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
6160 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
6161 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
6162 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
6163 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
6164 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
6165 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
6166 #define MISC_REGISTERS_SPIO_4 4
6167 #define MISC_REGISTERS_SPIO_5 5
6168 #define MISC_REGISTERS_SPIO_7 7
6169 #define MISC_REGISTERS_SPIO_CLR_POS 16
6170 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
6171 #define MISC_REGISTERS_SPIO_FLOAT_POS 24
6172 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
6173 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
6174 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
6175 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
6176 #define MISC_REGISTERS_SPIO_SET_POS 8
6177 #define MISC_SPIO_CLR_POS 16
6178 #define MISC_SPIO_FLOAT (0xffL<<24)
6179 #define MISC_SPIO_FLOAT_POS 24
6180 #define MISC_SPIO_INPUT_HI_Z 2
6181 #define MISC_SPIO_INT_OLD_SET_POS 16
6182 #define MISC_SPIO_OUTPUT_HIGH 1
6183 #define MISC_SPIO_OUTPUT_LOW 0
6184 #define MISC_SPIO_SET_POS 8
6185 #define MISC_SPIO_SPIO4 0x10
6186 #define MISC_SPIO_SPIO5 0x20
6187 #define HW_LOCK_MAX_RESOURCE_VALUE 31
6188 #define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB 13
6189 #define HW_LOCK_RESOURCE_DRV_FLAGS 10
6190 #define HW_LOCK_RESOURCE_GPIO 1
6191 #define HW_LOCK_RESOURCE_MDIO 0
6192 #define HW_LOCK_RESOURCE_NVRAM 12
6193 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
6194 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
6195 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
6196 #define HW_LOCK_RESOURCE_RECOVERY_REG 11
6197 #define HW_LOCK_RESOURCE_RESET 5
6198 #define HW_LOCK_RESOURCE_SPIO 2
6199 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
6200 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
6201 #define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19)
6202 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
6203 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
6204 #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
6205 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
6206 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
6207 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
6208 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
6209 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
6210 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
6211 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
6212 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
6213 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
6214 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
6215 #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
6216 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
6217 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
6218 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
6219 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
6220 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
6221 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31)
6222 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
6223 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
6224 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
6225 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
6226 #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
6227 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
6228 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31)
6229 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
6230 #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
6231 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
6232 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
6233 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
6234 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
6235 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
6236 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
6237 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
6238 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
6239 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
6240 #define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
6241 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
6242 #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
6243 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
6244 #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
6245 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
6246 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
6247 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
6248 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
6249 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
6250 #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
6251 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
6252 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
6253 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
6254 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
6255 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
6256 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
6257 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
6258 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
6259 #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
6260 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
6261 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
6262 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
6263 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
6264
6265 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)
6266 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9)
6267
6268 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
6269
6270 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
6271 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
6272
6273 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
6274 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
6275 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
6276 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
6277 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
6278 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
6279 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
6280 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
6281 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
6282 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
6283 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
6284 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
6285 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
6286 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
6287 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
6288 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
6289
6290 /* storm asserts attention bits */
6291 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
6292 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
6293 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
6294 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
6295
6296 /* mcp error attention bit */
6297 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
6298
6299 /*E1H NIG status sync attention mapped to group 4-7*/
6300 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
6301 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
6302 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
6303 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
6304 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
6305 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
6306 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
6307 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
6308
6309
6310 #define LATCHED_ATTN_RBCR 23
6311 #define LATCHED_ATTN_RBCT 24
6312 #define LATCHED_ATTN_RBCN 25
6313 #define LATCHED_ATTN_RBCU 26
6314 #define LATCHED_ATTN_RBCP 27
6315 #define LATCHED_ATTN_TIMEOUT_GRC 28
6316 #define LATCHED_ATTN_RSVD_GRC 29
6317 #define LATCHED_ATTN_ROM_PARITY_MCP 30
6318 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
6319 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
6320 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
6321
6322 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
6323 #define GENERAL_ATTEN_OFFSET(atten_name)\
6324 (1UL << ((94 + atten_name) % 32))
6325 /*
6326 * This file defines GRC base address for every block.
6327 * This file is included by chipsim, asm microcode and cpp microcode.
6328 * These values are used in Design.xml on regBase attribute
6329 * Use the base with the generated offsets of specific registers.
6330 */
6331
6332 #define GRCBASE_PXPCS 0x000000
6333 #define GRCBASE_PCICONFIG 0x002000
6334 #define GRCBASE_PCIREG 0x002400
6335 #define GRCBASE_EMAC0 0x008000
6336 #define GRCBASE_EMAC1 0x008400
6337 #define GRCBASE_DBU 0x008800
6338 #define GRCBASE_MISC 0x00A000
6339 #define GRCBASE_DBG 0x00C000
6340 #define GRCBASE_NIG 0x010000
6341 #define GRCBASE_XCM 0x020000
6342 #define GRCBASE_PRS 0x040000
6343 #define GRCBASE_SRCH 0x040400
6344 #define GRCBASE_TSDM 0x042000
6345 #define GRCBASE_TCM 0x050000
6346 #define GRCBASE_BRB1 0x060000
6347 #define GRCBASE_MCP 0x080000
6348 #define GRCBASE_UPB 0x0C1000
6349 #define GRCBASE_CSDM 0x0C2000
6350 #define GRCBASE_USDM 0x0C4000
6351 #define GRCBASE_CCM 0x0D0000
6352 #define GRCBASE_UCM 0x0E0000
6353 #define GRCBASE_CDU 0x101000
6354 #define GRCBASE_DMAE 0x102000
6355 #define GRCBASE_PXP 0x103000
6356 #define GRCBASE_CFC 0x104000
6357 #define GRCBASE_HC 0x108000
6358 #define GRCBASE_PXP2 0x120000
6359 #define GRCBASE_PBF 0x140000
6360 #define GRCBASE_UMAC0 0x160000
6361 #define GRCBASE_UMAC1 0x160400
6362 #define GRCBASE_XPB 0x161000
6363 #define GRCBASE_MSTAT0 0x162000
6364 #define GRCBASE_MSTAT1 0x162800
6365 #define GRCBASE_XMAC0 0x163000
6366 #define GRCBASE_XMAC1 0x163800
6367 #define GRCBASE_TIMERS 0x164000
6368 #define GRCBASE_XSDM 0x166000
6369 #define GRCBASE_QM 0x168000
6370 #define GRCBASE_DQ 0x170000
6371 #define GRCBASE_TSEM 0x180000
6372 #define GRCBASE_CSEM 0x200000
6373 #define GRCBASE_XSEM 0x280000
6374 #define GRCBASE_USEM 0x300000
6375 #define GRCBASE_MISC_AEU GRCBASE_MISC
6376
6377
6378 /* offset of configuration space in the pci core register */
6379 #define PCICFG_OFFSET 0x2000
6380 #define PCICFG_VENDOR_ID_OFFSET 0x00
6381 #define PCICFG_DEVICE_ID_OFFSET 0x02
6382 #define PCICFG_COMMAND_OFFSET 0x04
6383 #define PCICFG_COMMAND_IO_SPACE (1<<0)
6384 #define PCICFG_COMMAND_MEM_SPACE (1<<1)
6385 #define PCICFG_COMMAND_BUS_MASTER (1<<2)
6386 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
6387 #define PCICFG_COMMAND_MWI_CYCLES (1<<4)
6388 #define PCICFG_COMMAND_VGA_SNOOP (1<<5)
6389 #define PCICFG_COMMAND_PERR_ENA (1<<6)
6390 #define PCICFG_COMMAND_STEPPING (1<<7)
6391 #define PCICFG_COMMAND_SERR_ENA (1<<8)
6392 #define PCICFG_COMMAND_FAST_B2B (1<<9)
6393 #define PCICFG_COMMAND_INT_DISABLE (1<<10)
6394 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
6395 #define PCICFG_STATUS_OFFSET 0x06
6396 #define PCICFG_REVISION_ID_OFFSET 0x08
6397 #define PCICFG_REVESION_ID_MASK 0xff
6398 #define PCICFG_REVESION_ID_ERROR_VAL 0xff
6399 #define PCICFG_CACHE_LINE_SIZE 0x0c
6400 #define PCICFG_LATENCY_TIMER 0x0d
6401 #define PCICFG_BAR_1_LOW 0x10
6402 #define PCICFG_BAR_1_HIGH 0x14
6403 #define PCICFG_BAR_2_LOW 0x18
6404 #define PCICFG_BAR_2_HIGH 0x1c
6405 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
6406 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
6407 #define PCICFG_INT_LINE 0x3c
6408 #define PCICFG_INT_PIN 0x3d
6409 #define PCICFG_PM_CAPABILITY 0x48
6410 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
6411 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
6412 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
6413 #define PCICFG_PM_CAPABILITY_DSI (1<<21)
6414 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
6415 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
6416 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
6417 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
6418 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
6419 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
6420 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
6421 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
6422 #define PCICFG_PM_CSR_OFFSET 0x4c
6423 #define PCICFG_PM_CSR_STATE (0x3<<0)
6424 #define PCICFG_PM_CSR_PME_ENABLE (1<<8)
6425 #define PCICFG_PM_CSR_PME_STATUS (1<<15)
6426 #define PCICFG_MSI_CAP_ID_OFFSET 0x58
6427 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
6428 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
6429 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
6430 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
6431 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
6432 #define PCICFG_GRC_ADDRESS 0x78
6433 #define PCICFG_GRC_DATA 0x80
6434 #define PCICFG_ME_REGISTER 0x98
6435 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
6436 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
6437 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
6438 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
6439 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
6440
6441 #define PCICFG_DEVICE_CONTROL 0xb4
6442 #define PCICFG_DEVICE_STATUS 0xb6
6443 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
6444 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
6445 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
6446 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
6447 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
6448 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
6449 #define PCICFG_LINK_CONTROL 0xbc
6450
6451
6452 #define BAR_USTRORM_INTMEM 0x400000
6453 #define BAR_CSTRORM_INTMEM 0x410000
6454 #define BAR_XSTRORM_INTMEM 0x420000
6455 #define BAR_TSTRORM_INTMEM 0x430000
6456
6457 /* for accessing the IGU in case of status block ACK */
6458 #define BAR_IGU_INTMEM 0x440000
6459
6460 #define BAR_DOORBELL_OFFSET 0x800000
6461
6462 #define BAR_ME_REGISTER 0x450000
6463
6464 /* config_2 offset */
6465 #define GRC_CONFIG_2_SIZE_REG 0x408
6466 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
6467 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
6468 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
6469 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
6470 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
6471 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
6472 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
6473 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
6474 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
6475 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
6476 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
6477 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
6478 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
6479 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
6480 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
6481 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
6482 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
6483 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
6484 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
6485 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
6486 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
6487 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
6488 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
6489 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
6490 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
6491 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
6492 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
6493 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
6494 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
6495 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
6496 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
6497 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
6498 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
6499 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
6500 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
6501 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
6502 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
6503 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
6504 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
6505 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
6506
6507 /* config_3 offset */
6508 #define GRC_CONFIG_3_SIZE_REG 0x40c
6509 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
6510 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
6511 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
6512 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
6513 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
6514 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
6515 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
6516
6517 #define GRC_BAR2_CONFIG 0x4e0
6518 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
6519 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
6520 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
6521 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
6522 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
6523 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
6524 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
6525 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
6526 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
6527 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
6528 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
6529 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
6530 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
6531 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
6532 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
6533 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
6534 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
6535 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
6536
6537 #define PCI_PM_DATA_A 0x410
6538 #define PCI_PM_DATA_B 0x414
6539 #define PCI_ID_VAL1 0x434
6540 #define PCI_ID_VAL2 0x438
6541 #define PCI_ID_VAL3 0x43c
6542
6543 #define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C
6544 #define GRC_CONFIG_REG_PF_INIT_VF 0x624
6545 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xf
6546 /* First VF_NUM for PF is encoded in this register.
6547 * The number of VFs assigned to a PF is assumed to be a multiple of 8.
6548 * Software should program these bits based on Total Number of VFs \
6549 * programmed for each PF.
6550 * Since registers from 0x000-0x7ff are split across functions, each PF will
6551 * have the same location for the same 4 bits
6552 */
6553
6554 #define PXPCS_TL_CONTROL_5 0x814
6555 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/
6556 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/
6557 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/
6558 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/
6559 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/
6560 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/
6561 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/
6562 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/
6563 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/
6564 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/
6565 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/
6566 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/
6567 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/
6568 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/
6569 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/
6570 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/
6571 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/
6572 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/
6573 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/
6574 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/
6575 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/
6576 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/
6577 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/
6578 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/
6579 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/
6580 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/
6581 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/
6582 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/
6583 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/
6584 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
6585
6586
6587 #define PXPCS_TL_FUNC345_STAT 0x854
6588 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */
6589 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\
6590 (1 << 28) /* Unsupported Request Error Status in function4, if \
6591 set, generate pcie_err_attn output when this error is seen. WC */
6592 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\
6593 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
6594 generate pcie_err_attn output when this error is seen.. WC */
6595 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\
6596 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \
6597 generate pcie_err_attn output when this error is seen.. WC */
6598 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\
6599 (1 << 25) /* Receiver Overflow Status Status in function 4, if \
6600 set, generate pcie_err_attn output when this error is seen.. WC \
6601 */
6602 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\
6603 (1 << 24) /* Unexpected Completion Status Status in function 4, \
6604 if set, generate pcie_err_attn output when this error is seen. WC \
6605 */
6606 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\
6607 (1 << 23) /* Receive UR Statusin function 4. If set, generate \
6608 pcie_err_attn output when this error is seen. WC */
6609 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\
6610 (1 << 22) /* Completer Timeout Status Status in function 4, if \
6611 set, generate pcie_err_attn output when this error is seen. WC */
6612 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\
6613 (1 << 21) /* Flow Control Protocol Error Status Status in \
6614 function 4, if set, generate pcie_err_attn output when this error \
6615 is seen. WC */
6616 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\
6617 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \
6618 generate pcie_err_attn output when this error is seen.. WC */
6619 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */
6620 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\
6621 (1 << 18) /* Unsupported Request Error Status in function3, if \
6622 set, generate pcie_err_attn output when this error is seen. WC */
6623 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\
6624 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
6625 generate pcie_err_attn output when this error is seen.. WC */
6626 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\
6627 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
6628 generate pcie_err_attn output when this error is seen.. WC */
6629 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\
6630 (1 << 15) /* Receiver Overflow Status Status in function 3, if \
6631 set, generate pcie_err_attn output when this error is seen.. WC \
6632 */
6633 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\
6634 (1 << 14) /* Unexpected Completion Status Status in function 3, \
6635 if set, generate pcie_err_attn output when this error is seen. WC \
6636 */
6637 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\
6638 (1 << 13) /* Receive UR Statusin function 3. If set, generate \
6639 pcie_err_attn output when this error is seen. WC */
6640 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\
6641 (1 << 12) /* Completer Timeout Status Status in function 3, if \
6642 set, generate pcie_err_attn output when this error is seen. WC */
6643 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\
6644 (1 << 11) /* Flow Control Protocol Error Status Status in \
6645 function 3, if set, generate pcie_err_attn output when this error \
6646 is seen. WC */
6647 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\
6648 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
6649 generate pcie_err_attn output when this error is seen.. WC */
6650 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */
6651 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\
6652 (1 << 8) /* Unsupported Request Error Status for Function 2, if \
6653 set, generate pcie_err_attn output when this error is seen. WC */
6654 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\
6655 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
6656 generate pcie_err_attn output when this error is seen.. WC */
6657 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\
6658 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
6659 generate pcie_err_attn output when this error is seen.. WC */
6660 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\
6661 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \
6662 set, generate pcie_err_attn output when this error is seen.. WC \
6663 */
6664 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\
6665 (1 << 4) /* Unexpected Completion Status Status for Function 2, \
6666 if set, generate pcie_err_attn output when this error is seen. WC \
6667 */
6668 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\
6669 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
6670 pcie_err_attn output when this error is seen. WC */
6671 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\
6672 (1 << 2) /* Completer Timeout Status Status for Function 2, if \
6673 set, generate pcie_err_attn output when this error is seen. WC */
6674 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\
6675 (1 << 1) /* Flow Control Protocol Error Status Status for \
6676 Function 2, if set, generate pcie_err_attn output when this error \
6677 is seen. WC */
6678 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\
6679 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
6680 generate pcie_err_attn output when this error is seen.. WC */
6681
6682
6683 #define PXPCS_TL_FUNC678_STAT 0x85C
6684 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */
6685 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\
6686 (1 << 28) /* Unsupported Request Error Status in function7, if \
6687 set, generate pcie_err_attn output when this error is seen. WC */
6688 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\
6689 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
6690 generate pcie_err_attn output when this error is seen.. WC */
6691 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\
6692 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \
6693 generate pcie_err_attn output when this error is seen.. WC */
6694 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\
6695 (1 << 25) /* Receiver Overflow Status Status in function 7, if \
6696 set, generate pcie_err_attn output when this error is seen.. WC \
6697 */
6698 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\
6699 (1 << 24) /* Unexpected Completion Status Status in function 7, \
6700 if set, generate pcie_err_attn output when this error is seen. WC \
6701 */
6702 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\
6703 (1 << 23) /* Receive UR Statusin function 7. If set, generate \
6704 pcie_err_attn output when this error is seen. WC */
6705 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\
6706 (1 << 22) /* Completer Timeout Status Status in function 7, if \
6707 set, generate pcie_err_attn output when this error is seen. WC */
6708 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\
6709 (1 << 21) /* Flow Control Protocol Error Status Status in \
6710 function 7, if set, generate pcie_err_attn output when this error \
6711 is seen. WC */
6712 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\
6713 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \
6714 generate pcie_err_attn output when this error is seen.. WC */
6715 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */
6716 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\
6717 (1 << 18) /* Unsupported Request Error Status in function6, if \
6718 set, generate pcie_err_attn output when this error is seen. WC */
6719 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\
6720 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
6721 generate pcie_err_attn output when this error is seen.. WC */
6722 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\
6723 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \
6724 generate pcie_err_attn output when this error is seen.. WC */
6725 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\
6726 (1 << 15) /* Receiver Overflow Status Status in function 6, if \
6727 set, generate pcie_err_attn output when this error is seen.. WC \
6728 */
6729 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\
6730 (1 << 14) /* Unexpected Completion Status Status in function 6, \
6731 if set, generate pcie_err_attn output when this error is seen. WC \
6732 */
6733 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\
6734 (1 << 13) /* Receive UR Statusin function 6. If set, generate \
6735 pcie_err_attn output when this error is seen. WC */
6736 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\
6737 (1 << 12) /* Completer Timeout Status Status in function 6, if \
6738 set, generate pcie_err_attn output when this error is seen. WC */
6739 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\
6740 (1 << 11) /* Flow Control Protocol Error Status Status in \
6741 function 6, if set, generate pcie_err_attn output when this error \
6742 is seen. WC */
6743 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\
6744 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \
6745 generate pcie_err_attn output when this error is seen.. WC */
6746 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */
6747 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\
6748 (1 << 8) /* Unsupported Request Error Status for Function 5, if \
6749 set, generate pcie_err_attn output when this error is seen. WC */
6750 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\
6751 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
6752 generate pcie_err_attn output when this error is seen.. WC */
6753 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\
6754 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
6755 generate pcie_err_attn output when this error is seen.. WC */
6756 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\
6757 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \
6758 set, generate pcie_err_attn output when this error is seen.. WC \
6759 */
6760 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\
6761 (1 << 4) /* Unexpected Completion Status Status for Function 5, \
6762 if set, generate pcie_err_attn output when this error is seen. WC \
6763 */
6764 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\
6765 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
6766 pcie_err_attn output when this error is seen. WC */
6767 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\
6768 (1 << 2) /* Completer Timeout Status Status for Function 5, if \
6769 set, generate pcie_err_attn output when this error is seen. WC */
6770 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\
6771 (1 << 1) /* Flow Control Protocol Error Status Status for \
6772 Function 5, if set, generate pcie_err_attn output when this error \
6773 is seen. WC */
6774 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\
6775 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
6776 generate pcie_err_attn output when this error is seen.. WC */
6777
6778
6779 #define BAR_USTRORM_INTMEM 0x400000
6780 #define BAR_CSTRORM_INTMEM 0x410000
6781 #define BAR_XSTRORM_INTMEM 0x420000
6782 #define BAR_TSTRORM_INTMEM 0x430000
6783
6784 /* for accessing the IGU in case of status block ACK */
6785 #define BAR_IGU_INTMEM 0x440000
6786
6787 #define BAR_DOORBELL_OFFSET 0x800000
6788
6789 #define BAR_ME_REGISTER 0x450000
6790 #define ME_REG_PF_NUM_SHIFT 0
6791 #define ME_REG_PF_NUM\
6792 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
6793 #define ME_REG_VF_VALID (1<<8)
6794 #define ME_REG_VF_NUM_SHIFT 9
6795 #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
6796 #define ME_REG_VF_ERR (0x1<<3)
6797 #define ME_REG_ABS_PF_NUM_SHIFT 16
6798 #define ME_REG_ABS_PF_NUM\
6799 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
6800
6801
6802 #define PXP_VF_ADDR_IGU_START 0
6803 #define PXP_VF_ADDR_IGU_SIZE 0x3000
6804 #define PXP_VF_ADDR_IGU_END\
6805 ((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1)
6806
6807 #define PXP_VF_ADDR_USDM_QUEUES_START 0x3000
6808 #define PXP_VF_ADDR_USDM_QUEUES_SIZE\
6809 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE)
6810 #define PXP_VF_ADDR_USDM_QUEUES_END\
6811 ((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1)
6812
6813 #define PXP_VF_ADDR_CSDM_GLOBAL_START 0x7600
6814 #define PXP_VF_ADDR_CSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE)
6815 #define PXP_VF_ADDR_CSDM_GLOBAL_END\
6816 ((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1)
6817
6818 #define PXP_VF_ADDR_DB_START 0x7c00
6819 #define PXP_VF_ADDR_DB_SIZE 0x200
6820 #define PXP_VF_ADDR_DB_END\
6821 ((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1)
6822
6823 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
6824 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
6825 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
6826 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
6827 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
6828
6829 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
6830 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
6831 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
6832 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
6833 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
6834 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
6835 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
6836 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
6837 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
6838 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
6839 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
6840 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
6841 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
6842 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
6843 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
6844 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
6845 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
6846
6847 #define MDIO_REG_BANK_RX0 0x80b0
6848 #define MDIO_RX0_RX_STATUS 0x10
6849 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
6850 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
6851 #define MDIO_RX0_RX_EQ_BOOST 0x1c
6852 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6853 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
6854
6855 #define MDIO_REG_BANK_RX1 0x80c0
6856 #define MDIO_RX1_RX_EQ_BOOST 0x1c
6857 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6858 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
6859
6860 #define MDIO_REG_BANK_RX2 0x80d0
6861 #define MDIO_RX2_RX_EQ_BOOST 0x1c
6862 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6863 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
6864
6865 #define MDIO_REG_BANK_RX3 0x80e0
6866 #define MDIO_RX3_RX_EQ_BOOST 0x1c
6867 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6868 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
6869
6870 #define MDIO_REG_BANK_RX_ALL 0x80f0
6871 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
6872 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6873 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
6874
6875 #define MDIO_REG_BANK_TX0 0x8060
6876 #define MDIO_TX0_TX_DRIVER 0x17
6877 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6878 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6879 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6880 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6881 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6882 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6883 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6884 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6885 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6886
6887 #define MDIO_REG_BANK_TX1 0x8070
6888 #define MDIO_TX1_TX_DRIVER 0x17
6889 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6890 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6891 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6892 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6893 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6894 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6895 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6896 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6897 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6898
6899 #define MDIO_REG_BANK_TX2 0x8080
6900 #define MDIO_TX2_TX_DRIVER 0x17
6901 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6902 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6903 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6904 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6905 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6906 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6907 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6908 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6909 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6910
6911 #define MDIO_REG_BANK_TX3 0x8090
6912 #define MDIO_TX3_TX_DRIVER 0x17
6913 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6914 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
6915 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6916 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
6917 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6918 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
6919 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6920 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
6921 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
6922
6923 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
6924 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
6925
6926 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
6927 #define MDIO_BLOCK1_LANE_CTRL0 0x15
6928 #define MDIO_BLOCK1_LANE_CTRL1 0x16
6929 #define MDIO_BLOCK1_LANE_CTRL2 0x17
6930 #define MDIO_BLOCK1_LANE_PRBS 0x19
6931
6932 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
6933 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
6934 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
6935 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
6936 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
6937 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
6938 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
6939 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
6940 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
6941 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
6942
6943 #define MDIO_REG_BANK_GP_STATUS 0x8120
6944 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
6945 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
6946 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
6947 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
6948 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
6949 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
6950 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
6951 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
6952 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
6953 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
6954 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
6955 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
6956 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
6957 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
6958 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
6959 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
6960 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
6961 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
6962 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
6963 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
6964 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
6965 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
6966 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
6967 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
6968 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
6969 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
6970 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
6971 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
6972 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
6973 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
6974
6975
6976 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
6977 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
6978 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
6979 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
6980 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
6981 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
6982 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
6983
6984 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
6985 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
6986 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
6987 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
6988 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
6989 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
6990 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
6991 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
6992 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
6993 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
6994 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
6995 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
6996 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
6997 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
6998 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
6999 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
7000 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
7001 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
7002 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
7003 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
7004 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
7005 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
7006 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
7007 #define MDIO_SERDES_DIGITAL_MISC1 0x18
7008 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
7009 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
7010 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
7011 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
7012 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
7013 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
7014 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
7015 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
7016 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
7017 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
7018 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
7019 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
7020 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
7021 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
7022 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
7023 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
7024 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
7025 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
7026
7027 #define MDIO_REG_BANK_OVER_1G 0x8320
7028 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
7029 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
7030 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
7031 #define MDIO_OVER_1G_UP1 0x19
7032 #define MDIO_OVER_1G_UP1_2_5G 0x0001
7033 #define MDIO_OVER_1G_UP1_5G 0x0002
7034 #define MDIO_OVER_1G_UP1_6G 0x0004
7035 #define MDIO_OVER_1G_UP1_10G 0x0010
7036 #define MDIO_OVER_1G_UP1_10GH 0x0008
7037 #define MDIO_OVER_1G_UP1_12G 0x0020
7038 #define MDIO_OVER_1G_UP1_12_5G 0x0040
7039 #define MDIO_OVER_1G_UP1_13G 0x0080
7040 #define MDIO_OVER_1G_UP1_15G 0x0100
7041 #define MDIO_OVER_1G_UP1_16G 0x0200
7042 #define MDIO_OVER_1G_UP2 0x1A
7043 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
7044 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
7045 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
7046 #define MDIO_OVER_1G_UP3 0x1B
7047 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
7048 #define MDIO_OVER_1G_LP_UP1 0x1C
7049 #define MDIO_OVER_1G_LP_UP2 0x1D
7050 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
7051 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
7052 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
7053 #define MDIO_OVER_1G_LP_UP3 0x1E
7054
7055 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
7056 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
7057 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
7058 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
7059
7060 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
7061 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
7062 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
7063 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
7064
7065 #define MDIO_REG_BANK_CL73_USERB0 0x8370
7066 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
7067 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
7068 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
7069 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
7070 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
7071 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
7072 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
7073 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
7074 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
7075 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
7076 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
7077
7078 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
7079 #define MDIO_AER_BLOCK_AER_REG 0x1E
7080
7081 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
7082 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
7083 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
7084 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
7085 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
7086 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
7087 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
7088 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
7089 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
7090 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
7091 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
7092 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
7093 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
7094 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
7095 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
7096 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
7097 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
7098 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
7099 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
7100 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
7101 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
7102 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
7103 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
7104 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
7105 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
7106 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
7107 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
7108 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
7109 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
7110 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
7111 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
7112 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
7113 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
7114 Theotherbitsarereservedandshouldbezero*/
7115 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
7116
7117
7118 #define MDIO_PMA_DEVAD 0x1
7119 /*ieee*/
7120 #define MDIO_PMA_REG_CTRL 0x0
7121 #define MDIO_PMA_REG_STATUS 0x1
7122 #define MDIO_PMA_REG_10G_CTRL2 0x7
7123 #define MDIO_PMA_REG_TX_DISABLE 0x0009
7124 #define MDIO_PMA_REG_RX_SD 0xa
7125 /*bcm*/
7126 #define MDIO_PMA_REG_BCM_CTRL 0x0096
7127 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
7128 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
7129 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
7130 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
7131 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
7132 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
7133 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
7134 #define MDIO_PMA_REG_GEN_CTRL 0xca10
7135 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
7136 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
7137 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
7138 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
7139 #define MDIO_PMA_REG_ROM_VER1 0xca19
7140 #define MDIO_PMA_REG_ROM_VER2 0xca1a
7141 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
7142 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
7143 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
7144 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
7145 #define MDIO_PMA_REG_LRM_MODE 0xca3f
7146 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
7147 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
7148
7149 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
7150 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
7151 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
7152 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
7153 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
7154 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
7155 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
7156 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
7157 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
7158 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
7159 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
7160 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
7161
7162 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
7163 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
7164 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
7165 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
7166 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
7167 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
7168 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
7169 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
7170 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
7171
7172 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
7173
7174 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
7175 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
7176 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
7177 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
7178
7179 #define MDIO_PMA_REG_7101_RESET 0xc000
7180 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
7181 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
7182 #define MDIO_PMA_REG_7101_VER1 0xc026
7183 #define MDIO_PMA_REG_7101_VER2 0xc027
7184
7185 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
7186 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
7187 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
7188 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
7189 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
7190 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
7191 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
7192 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
7193 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
7194 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
7195
7196
7197 #define MDIO_WIS_DEVAD 0x2
7198 /*bcm*/
7199 #define MDIO_WIS_REG_LASI_CNTL 0x9002
7200 #define MDIO_WIS_REG_LASI_STATUS 0x9005
7201
7202 #define MDIO_PCS_DEVAD 0x3
7203 #define MDIO_PCS_REG_STATUS 0x0020
7204 #define MDIO_PCS_REG_LASI_STATUS 0x9005
7205 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
7206 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
7207 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
7208 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
7209 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
7210 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
7211 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
7212 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
7213 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
7214
7215
7216 #define MDIO_XS_DEVAD 0x4
7217 #define MDIO_XS_PLL_SEQUENCER 0x8000
7218 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
7219
7220 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
7221 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
7222 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
7223 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
7224 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
7225
7226 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
7227
7228 #define MDIO_AN_DEVAD 0x7
7229 /*ieee*/
7230 #define MDIO_AN_REG_CTRL 0x0000
7231 #define MDIO_AN_REG_STATUS 0x0001
7232 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
7233 #define MDIO_AN_REG_ADV_PAUSE 0x0010
7234 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
7235 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
7236 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
7237 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
7238 #define MDIO_AN_REG_ADV 0x0011
7239 #define MDIO_AN_REG_ADV2 0x0012
7240 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
7241 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
7242 #define MDIO_AN_REG_MASTER_STATUS 0x0021
7243 #define MDIO_AN_REG_EEE_ADV 0x003c
7244 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
7245 /*bcm*/
7246 #define MDIO_AN_REG_LINK_STATUS 0x8304
7247 #define MDIO_AN_REG_CL37_CL73 0x8370
7248 #define MDIO_AN_REG_CL37_AN 0xffe0
7249 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
7250 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
7251 #define MDIO_AN_REG_1000T_STATUS 0xffea
7252
7253 #define MDIO_AN_REG_8073_2_5G 0x8329
7254 #define MDIO_AN_REG_8073_BAM 0x8350
7255
7256 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
7257 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
7258 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
7259 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
7260 #define MDIO_AN_REG_848xx_ID_MSB 0xffe2
7261 #define BCM84858_PHY_ID 0x600d
7262 #define MDIO_AN_REG_848xx_ID_LSB 0xffe3
7263 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
7264 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
7265 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
7266 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
7267 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
7268 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
7269 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
7270 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
7271 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
7272
7273 /* BCM84823 only */
7274 #define MDIO_CTL_DEVAD 0x1e
7275 #define MDIO_CTL_REG_84823_MEDIA 0x401a
7276 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
7277 /* These pins configure the BCM84823 interface to MAC after reset. */
7278 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
7279 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
7280 /* These pins configure the BCM84823 interface to Line after reset. */
7281 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
7282 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
7283 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
7284 /* When this pin is active high during reset, 10GBASE-T core is power
7285 * down, When it is active low the 10GBASE-T is power up
7286 */
7287 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
7288 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
7289 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
7290 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
7291 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
7292 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
7293 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
7294 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
7295 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
7296 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
7297 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
7298 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
7299 /* BCM84858 only */
7300 #define MDIO_PMA_REG_84858_ALLOW_GPHY_ACT 0x8000
7301
7302 /* BCM84833 only */
7303 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
7304 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
7305 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
7306 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
7307 #define MDIO_84833_SUPER_ISOLATE 0x8000
7308 /* These are mailbox register set used by 84833/84858. */
7309 #define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005
7310 #define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006
7311 #define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007
7312 #define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008
7313 #define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009
7314 #define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037
7315 #define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038
7316 #define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039
7317 #define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a
7318 #define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b
7319 #define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c
7320 #define MDIO_848xx_CMD_HDLR_COMMAND (MDIO_848xx_TOP_CFG_SCRATCH_REG0)
7321 #define MDIO_848xx_CMD_HDLR_STATUS (MDIO_848xx_TOP_CFG_SCRATCH_REG26)
7322 #define MDIO_848xx_CMD_HDLR_DATA1 (MDIO_848xx_TOP_CFG_SCRATCH_REG27)
7323 #define MDIO_848xx_CMD_HDLR_DATA2 (MDIO_848xx_TOP_CFG_SCRATCH_REG28)
7324 #define MDIO_848xx_CMD_HDLR_DATA3 (MDIO_848xx_TOP_CFG_SCRATCH_REG29)
7325 #define MDIO_848xx_CMD_HDLR_DATA4 (MDIO_848xx_TOP_CFG_SCRATCH_REG30)
7326 #define MDIO_848xx_CMD_HDLR_DATA5 (MDIO_848xx_TOP_CFG_SCRATCH_REG31)
7327
7328 /* Mailbox command set used by 84833/84858 */
7329 #define PHY848xx_CMD_SET_PAIR_SWAP 0x8001
7330 #define PHY848xx_CMD_GET_EEE_MODE 0x8008
7331 #define PHY848xx_CMD_SET_EEE_MODE 0x8009
7332 /* Mailbox status set used by 84833 only */
7333 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
7334 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
7335 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
7336 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
7337 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
7338 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
7339 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
7340 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
7341 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
7342 /* Mailbox Process */
7343 #define PHY84833_MB_PROCESS1 1
7344 #define PHY84833_MB_PROCESS2 2
7345 #define PHY84833_MB_PROCESS3 3
7346
7347 /* Mailbox status set used by 84858 only */
7348 #define PHY84858_STATUS_CMD_RECEIVED 0x0001
7349 #define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002
7350 #define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004
7351 #define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008
7352 #define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb
7353
7354
7355 /* Warpcore clause 45 addressing */
7356 #define MDIO_WC_DEVAD 0x3
7357 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
7358 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
7359 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
7360 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
7361 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
7362 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
7363 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
7364 #define MDIO_WC_REG_PCS_STATUS2 0x0021
7365 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
7366 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
7367 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
7368 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
7369 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
7370 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
7371 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
7372 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
7373 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
7374 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
7375 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
7376 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
7377 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01
7378 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e
7379 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
7380 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
7381 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
7382 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
7383 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
7384 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
7385 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
7386 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
7387 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
7388 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
7389 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
7390 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
7391 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
7392 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
7393 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
7394 #define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
7395 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
7396 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
7397 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
7398 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
7399 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
7400 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
7401 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
7402 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
7403 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
7404 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
7405 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
7406 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
7407 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
7408 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
7409 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
7410 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
7411 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
7412 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
7413 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
7414 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
7415 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
7416 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
7417 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
7418 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
7419 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
7420 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
7421 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
7422 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
7423 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
7424 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
7425 #define MDIO_WC_REG_DSC_SMC 0x8213
7426 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
7427 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
7428 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
7429 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
7430 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
7431 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
7432 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
7433 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
7434 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
7435 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
7436 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
7437 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
7438 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
7439 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
7440 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
7441 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
7442 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
7443 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
7444 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
7445 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
7446 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
7447 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
7448 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
7449 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
7450 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
7451 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
7452 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
7453 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
7454 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
7455 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
7456 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
7457 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
7458 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
7459 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
7460 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
7461 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
7462 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
7463 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
7464 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
7465 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
7466 #define MDIO_WC_REG_RX66_SCW0 0x83c2
7467 #define MDIO_WC_REG_RX66_SCW1 0x83c3
7468 #define MDIO_WC_REG_RX66_SCW2 0x83c4
7469 #define MDIO_WC_REG_RX66_SCW3 0x83c5
7470 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
7471 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
7472 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
7473 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
7474 #define MDIO_WC_REG_FX100_CTRL1 0x8400
7475 #define MDIO_WC_REG_FX100_CTRL3 0x8402
7476 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
7477 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
7478 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
7479 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
7480 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
7481 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
7482 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
7483 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
7484 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
7485 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
7486 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
7487 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
7488 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
7489 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
7490
7491 #define MDIO_WC_REG_AERBLK_AER 0xffde
7492 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
7493 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
7494
7495 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
7496 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
7497 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
7498
7499 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
7500
7501 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
7502
7503 /* 54618se */
7504 #define MDIO_REG_GPHY_PHYID_LSB 0x3
7505 #define MDIO_REG_GPHY_ID_54618SE 0x5cd5
7506 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
7507 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
7508 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
7509 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
7510 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
7511 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
7512 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
7513 #define MDIO_REG_GPHY_AUX_STATUS 0x19
7514 #define MDIO_REG_INTR_STATUS 0x1a
7515 #define MDIO_REG_INTR_MASK 0x1b
7516 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
7517 #define MDIO_REG_GPHY_SHADOW 0x1c
7518 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
7519 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
7520 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
7521 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
7522 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
7523
7524 #define IGU_FUNC_BASE 0x0400
7525
7526 #define IGU_ADDR_MSIX 0x0000
7527 #define IGU_ADDR_INT_ACK 0x0200
7528 #define IGU_ADDR_PROD_UPD 0x0201
7529 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
7530 #define IGU_ADDR_ATTN_BITS_SET 0x0203
7531 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
7532 #define IGU_ADDR_COALESCE_NOW 0x0205
7533 #define IGU_ADDR_SIMD_MASK 0x0206
7534 #define IGU_ADDR_SIMD_NOMASK 0x0207
7535 #define IGU_ADDR_MSI_CTL 0x0210
7536 #define IGU_ADDR_MSI_ADDR_LO 0x0211
7537 #define IGU_ADDR_MSI_ADDR_HI 0x0212
7538 #define IGU_ADDR_MSI_DATA 0x0213
7539
7540 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
7541 #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
7542 #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
7543 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
7544
7545 #define COMMAND_REG_INT_ACK 0x0
7546 #define COMMAND_REG_PROD_UPD 0x4
7547 #define COMMAND_REG_ATTN_BITS_UPD 0x8
7548 #define COMMAND_REG_ATTN_BITS_SET 0xc
7549 #define COMMAND_REG_ATTN_BITS_CLR 0x10
7550 #define COMMAND_REG_COALESCE_NOW 0x14
7551 #define COMMAND_REG_SIMD_MASK 0x18
7552 #define COMMAND_REG_SIMD_NOMASK 0x1c
7553
7554
7555 #define IGU_MEM_BASE 0x0000
7556
7557 #define IGU_MEM_MSIX_BASE 0x0000
7558 #define IGU_MEM_MSIX_UPPER 0x007f
7559 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
7560
7561 #define IGU_MEM_PBA_MSIX_BASE 0x0200
7562 #define IGU_MEM_PBA_MSIX_UPPER 0x0200
7563
7564 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
7565 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
7566
7567 #define IGU_CMD_INT_ACK_BASE 0x0400
7568 #define IGU_CMD_INT_ACK_UPPER\
7569 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7570 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
7571
7572 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500
7573 #define IGU_CMD_E2_PROD_UPD_UPPER\
7574 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7575 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
7576
7577 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
7578 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
7579 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
7580
7581 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
7582 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
7583 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
7584 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
7585
7586 #define IGU_REG_RESERVED_UPPER 0x05ff
7587 /* Fields of IGU PF CONFIGURATION REGISTER */
7588 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
7589 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
7590 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
7591 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
7592 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
7593 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
7594
7595 /* Fields of IGU VF CONFIGURATION REGISTER */
7596 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
7597 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
7598 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
7599 #define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */
7600 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
7601
7602
7603 #define IGU_BC_DSB_NUM_SEGS 5
7604 #define IGU_BC_NDSB_NUM_SEGS 2
7605 #define IGU_NORM_DSB_NUM_SEGS 2
7606 #define IGU_NORM_NDSB_NUM_SEGS 1
7607 #define IGU_BC_BASE_DSB_PROD 128
7608 #define IGU_NORM_BASE_DSB_PROD 136
7609
7610 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
7611 [5:2] = 0; [1:0] = PF number) */
7612 #define IGU_FID_ENCODE_IS_PF (0x1<<6)
7613 #define IGU_FID_ENCODE_IS_PF_SHIFT 6
7614 #define IGU_FID_VF_NUM_MASK (0x3f)
7615 #define IGU_FID_PF_NUM_MASK (0x7)
7616
7617 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
7618 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
7619 #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1
7620 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
7621 #define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7
7622
7623
7624 #define CDU_REGION_NUMBER_XCM_AG 2
7625 #define CDU_REGION_NUMBER_UCM_AG 4
7626
7627
7628 /* String-to-compress [31:8] = CID (all 24 bits)
7629 * String-to-compress [7:4] = Region
7630 * String-to-compress [3:0] = Type
7631 */
7632 #define CDU_VALID_DATA(_cid, _region, _type)\
7633 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
7634 #define CDU_CRC8(_cid, _region, _type)\
7635 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
7636 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
7637 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
7638 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
7639 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
7640 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
7641
7642 /******************************************************************************
7643 * Description:
7644 * Calculates crc 8 on a word value: polynomial 0-1-2-8
7645 * Code was translated from Verilog.
7646 * Return:
7647 *****************************************************************************/
7648 static inline u8 calc_crc8(u32 data, u8 crc)
7649 {
7650 u8 D[32];
7651 u8 NewCRC[8];
7652 u8 C[8];
7653 u8 crc_res;
7654 u8 i;
7655
7656 /* split the data into 31 bits */
7657 for (i = 0; i < 32; i++) {
7658 D[i] = (u8)(data & 1);
7659 data = data >> 1;
7660 }
7661
7662 /* split the crc into 8 bits */
7663 for (i = 0; i < 8; i++) {
7664 C[i] = crc & 1;
7665 crc = crc >> 1;
7666 }
7667
7668 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
7669 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
7670 C[6] ^ C[7];
7671 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
7672 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
7673 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^
7674 C[6];
7675 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
7676 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
7677 C[0] ^ C[1] ^ C[4] ^ C[5];
7678 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
7679 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
7680 C[1] ^ C[2] ^ C[5] ^ C[6];
7681 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
7682 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
7683 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
7684 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
7685 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
7686 C[3] ^ C[4] ^ C[7];
7687 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
7688 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
7689 C[5];
7690 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
7691 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
7692 C[6];
7693
7694 crc_res = 0;
7695 for (i = 0; i < 8; i++)
7696 crc_res |= (NewCRC[i] << i);
7697
7698 return crc_res;
7699 }
7700
7701
7702 #endif /* BNX2X_REG_H */