This source file includes following definitions.
- reg_poll
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16 #ifndef BNX2X_H
17 #define BNX2X_H
18
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/types.h>
23 #include <linux/pci_regs.h>
24
25 #include <linux/ptp_clock_kernel.h>
26 #include <linux/net_tstamp.h>
27 #include <linux/timecounter.h>
28
29
30
31
32
33
34
35 #define DRV_MODULE_VERSION "1.713.36-0"
36 #define DRV_MODULE_RELDATE "2014/02/10"
37 #define BNX2X_BC_VER 0x040200
38
39 #if defined(CONFIG_DCB)
40 #define BCM_DCBNL
41 #endif
42
43 #include "bnx2x_hsi.h"
44
45 #include "../cnic_if.h"
46
47 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
48
49 #include <linux/mdio.h>
50
51 #include "bnx2x_reg.h"
52 #include "bnx2x_fw_defs.h"
53 #include "bnx2x_mfw_req.h"
54 #include "bnx2x_link.h"
55 #include "bnx2x_sp.h"
56 #include "bnx2x_dcb.h"
57 #include "bnx2x_stats.h"
58 #include "bnx2x_vfpf.h"
59
60 enum bnx2x_int_mode {
61 BNX2X_INT_MODE_MSIX,
62 BNX2X_INT_MODE_INTX,
63 BNX2X_INT_MODE_MSI
64 };
65
66
67
68 #define DRV_MODULE_NAME "bnx2x"
69
70
71 #define BNX2X_MSG_OFF 0x0
72 #define BNX2X_MSG_MCP 0x0010000
73 #define BNX2X_MSG_STATS 0x0020000
74 #define BNX2X_MSG_NVM 0x0040000
75 #define BNX2X_MSG_DMAE 0x0080000
76 #define BNX2X_MSG_SP 0x0100000
77 #define BNX2X_MSG_FP 0x0200000
78 #define BNX2X_MSG_IOV 0x0800000
79 #define BNX2X_MSG_PTP 0x1000000
80 #define BNX2X_MSG_IDLE 0x2000000
81 #define BNX2X_MSG_ETHTOOL 0x4000000
82 #define BNX2X_MSG_DCB 0x8000000
83
84
85 #define DP_INNER(fmt, ...) \
86 pr_notice("[%s:%d(%s)]" fmt, \
87 __func__, __LINE__, \
88 bp->dev ? (bp->dev->name) : "?", \
89 ##__VA_ARGS__);
90
91 #define DP(__mask, fmt, ...) \
92 do { \
93 if (unlikely(bp->msg_enable & (__mask))) \
94 DP_INNER(fmt, ##__VA_ARGS__); \
95 } while (0)
96
97 #define DP_AND(__mask, fmt, ...) \
98 do { \
99 if (unlikely((bp->msg_enable & (__mask)) == __mask)) \
100 DP_INNER(fmt, ##__VA_ARGS__); \
101 } while (0)
102
103 #define DP_CONT(__mask, fmt, ...) \
104 do { \
105 if (unlikely(bp->msg_enable & (__mask))) \
106 pr_cont(fmt, ##__VA_ARGS__); \
107 } while (0)
108
109
110 #define BNX2X_DBG_ERR(fmt, ...) \
111 do { \
112 if (unlikely(netif_msg_probe(bp))) \
113 pr_err("[%s:%d(%s)]" fmt, \
114 __func__, __LINE__, \
115 bp->dev ? (bp->dev->name) : "?", \
116 ##__VA_ARGS__); \
117 } while (0)
118
119
120 #define BNX2X_ERR(fmt, ...) \
121 do { \
122 pr_err("[%s:%d(%s)]" fmt, \
123 __func__, __LINE__, \
124 bp->dev ? (bp->dev->name) : "?", \
125 ##__VA_ARGS__); \
126 } while (0)
127
128 #define BNX2X_ERROR(fmt, ...) \
129 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
130
131
132 #define BNX2X_DEV_INFO(fmt, ...) \
133 do { \
134 if (unlikely(netif_msg_probe(bp))) \
135 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
136 } while (0)
137
138
139 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
140 #ifdef BNX2X_STOP_ON_ERROR
141 #define bnx2x_panic() \
142 do { \
143 bp->panic = 1; \
144 BNX2X_ERR("driver assert\n"); \
145 bnx2x_panic_dump(bp, true); \
146 } while (0)
147 #else
148 #define bnx2x_panic() \
149 do { \
150 bp->panic = 1; \
151 BNX2X_ERR("driver assert\n"); \
152 bnx2x_panic_dump(bp, false); \
153 } while (0)
154 #endif
155
156 #define bnx2x_mc_addr(ha) ((ha)->addr)
157 #define bnx2x_uc_addr(ha) ((ha)->addr)
158
159 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff))
160 #define U64_HI(x) ((u32)(((u64)(x)) >> 32))
161 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
162
163 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
164
165 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
166 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
167 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
168
169 #define REG_WR_RELAXED(bp, offset, val) \
170 writel_relaxed((u32)val, REG_ADDR(bp, offset))
171
172 #define REG_WR16_RELAXED(bp, offset, val) \
173 writew_relaxed((u16)val, REG_ADDR(bp, offset))
174
175 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
176 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
177 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
178
179 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
180 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
181
182 #define REG_RD_DMAE(bp, offset, valp, len32) \
183 do { \
184 bnx2x_read_dmae(bp, offset, len32);\
185 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
186 } while (0)
187
188 #define REG_WR_DMAE(bp, offset, valp, len32) \
189 do { \
190 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
191 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
192 offset, len32); \
193 } while (0)
194
195 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
196 REG_WR_DMAE(bp, offset, valp, len32)
197
198 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
199 do { \
200 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
201 bnx2x_write_big_buf_wb(bp, addr, len32); \
202 } while (0)
203
204 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
205 offsetof(struct shmem_region, field))
206 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
207 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
208
209 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
210 offsetof(struct shmem2_region, field))
211 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
212 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
213 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
214 offsetof(struct mf_cfg, field))
215 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
216 offsetof(struct mf2_cfg, field))
217
218 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
219 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
220 MF_CFG_ADDR(bp, field), (val))
221 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
222
223 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
224 (SHMEM2_RD((bp), size) > \
225 offsetof(struct shmem2_region, field)))
226
227 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
228 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
229
230
231
232
233 #define HC_SP_INDEX_ETH_DEF_CONS 3
234
235
236 #define HC_SP_INDEX_EQ_CONS 7
237
238
239 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
240 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
241
242 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
243 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
244
245
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247
248
249 #define BNX2X_FCOE_L2_RX_INDEX \
250 (&bp->def_status_blk->sp_sb.\
251 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
252
253 #define BNX2X_FCOE_L2_TX_INDEX \
254 (&bp->def_status_blk->sp_sb.\
255 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
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264
265 enum {
266 BNX2X_ISCSI_ETH_CL_ID_IDX,
267 BNX2X_FCOE_ETH_CL_ID_IDX,
268 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
269 };
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279
280
281 #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \
282 (bp)->max_cos)
283
284 #define UIO_DPM 8
285
286 #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \
287 UIO_DPM))
288
289 #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \
290 (UIO_DPM * 2))
291
292 #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp))
293
294 #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \
295 (UIO_DPM_ALIGN(bp) == UIO_DPM))
296
297 #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \
298 (UIO_DPM_CID0_OFFSET(bp)))
299
300 #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \
301 BNX2X_1st_NON_L2_ETH_CID(bp))
302
303 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
304
305 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
306
307 #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
308 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
309 #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
310 #define FCOE_INIT(bp) ((bp)->fcoe_init)
311
312 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
313 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
314
315 #define SM_RX_ID 0
316 #define SM_TX_ID 1
317
318
319 #define FIRST_TX_ONLY_COS_INDEX 1
320 #define FIRST_TX_COS_INDEX 0
321
322
323 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
324 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
325 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
326
327
328 #define FP_COS_TO_TXQ(fp, cos, bp) \
329 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
330
331
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334
335
336
337 enum {
338 FCOE_TXQ_IDX_OFFSET,
339 FWD_TXQ_IDX_OFFSET,
340 OOO_TXQ_IDX_OFFSET,
341 };
342 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
343 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
344
345
346
347
348
349
350
351 struct sw_rx_bd {
352 u8 *data;
353 DEFINE_DMA_UNMAP_ADDR(mapping);
354 };
355
356 struct sw_tx_bd {
357 struct sk_buff *skb;
358 u16 first_bd;
359 u8 flags;
360
361 #define BNX2X_TSO_SPLIT_BD (1<<0)
362 #define BNX2X_HAS_SECOND_PBD (1<<1)
363 };
364
365 struct sw_rx_page {
366 struct page *page;
367 DEFINE_DMA_UNMAP_ADDR(mapping);
368 unsigned int offset;
369 };
370
371 union db_prod {
372 struct doorbell_set_prod data;
373 u32 raw;
374 };
375
376
377 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
378 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
379 ETH_MAX_AGGREGATION_QUEUES_E1 :\
380 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
381 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
382 #define FW_PREFETCH_CNT 16
383 #define DROPLESS_FC_HEADROOM 100
384
385
386 #define BCM_PAGE_SHIFT 12
387 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
388 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
389 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
390
391 #define PAGES_PER_SGE_SHIFT 0
392 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
393 #define SGE_PAGE_SHIFT 12
394 #define SGE_PAGE_SIZE (1 << SGE_PAGE_SHIFT)
395 #define SGE_PAGE_MASK (~(SGE_PAGE_SIZE - 1))
396 #define SGE_PAGE_ALIGN(addr) (((addr) + SGE_PAGE_SIZE - 1) & SGE_PAGE_MASK)
397 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
398 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
399 SGE_PAGES), 0xffff)
400
401
402 #define NUM_RX_SGE_PAGES 2
403 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
404 #define NEXT_PAGE_SGE_DESC_CNT 2
405 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
406
407 #define RX_SGE_MASK (RX_SGE_CNT - 1)
408 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
409 #define MAX_RX_SGE (NUM_RX_SGE - 1)
410 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
411 (MAX_RX_SGE_CNT - 1)) ? \
412 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
413 (x) + 1)
414 #define RX_SGE(x) ((x) & MAX_RX_SGE)
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421
422
423
424
425 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
426 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
427 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
428 MAX_RX_SGE_CNT)
429 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
430 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
431 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
432
433
434
435
436 #define BIT_VEC64_ELEM_SZ 64
437 #define BIT_VEC64_ELEM_SHIFT 6
438 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
439
440 #define __BIT_VEC64_SET_BIT(el, bit) \
441 do { \
442 el = ((el) | ((u64)0x1 << (bit))); \
443 } while (0)
444
445 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
446 do { \
447 el = ((el) & (~((u64)0x1 << (bit)))); \
448 } while (0)
449
450 #define BIT_VEC64_SET_BIT(vec64, idx) \
451 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
452 (idx) & BIT_VEC64_ELEM_MASK)
453
454 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
455 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
456 (idx) & BIT_VEC64_ELEM_MASK)
457
458 #define BIT_VEC64_TEST_BIT(vec64, idx) \
459 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
460 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
461
462
463
464 #define BIT_VEC64_ONES_MASK(idx) \
465 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
466 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
467
468
469
470
471 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
472 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
473 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
474
475 union host_hc_status_block {
476
477 struct host_hc_status_block_e1x *e1x_sb;
478
479 struct host_hc_status_block_e2 *e2_sb;
480 };
481
482 struct bnx2x_agg_info {
483
484
485
486
487
488
489
490 struct sw_rx_bd first_buf;
491 u8 tpa_state;
492 #define BNX2X_TPA_START 1
493 #define BNX2X_TPA_STOP 2
494 #define BNX2X_TPA_ERROR 3
495 u8 placement_offset;
496 u16 parsing_flags;
497 u16 vlan_tag;
498 u16 len_on_bd;
499 u32 rxhash;
500 enum pkt_hash_types rxhash_type;
501 u16 gro_size;
502 u16 full_page;
503 };
504
505 #define Q_STATS_OFFSET32(stat_name) \
506 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
507
508 struct bnx2x_fp_txdata {
509
510 struct sw_tx_bd *tx_buf_ring;
511
512 union eth_tx_bd_types *tx_desc_ring;
513 dma_addr_t tx_desc_mapping;
514
515 u32 cid;
516
517 union db_prod tx_db;
518
519 u16 tx_pkt_prod;
520 u16 tx_pkt_cons;
521 u16 tx_bd_prod;
522 u16 tx_bd_cons;
523
524 unsigned long tx_pkt;
525
526 __le16 *tx_cons_sb;
527
528 int txq_index;
529 struct bnx2x_fastpath *parent_fp;
530 int tx_ring_size;
531 };
532
533 enum bnx2x_tpa_mode_t {
534 TPA_MODE_DISABLED,
535 TPA_MODE_LRO,
536 TPA_MODE_GRO
537 };
538
539 struct bnx2x_alloc_pool {
540 struct page *page;
541 unsigned int offset;
542 };
543
544 struct bnx2x_fastpath {
545 struct bnx2x *bp;
546
547 struct napi_struct napi;
548
549 union host_hc_status_block status_blk;
550
551 __le16 *sb_index_values;
552 __le16 *sb_running_index;
553
554 u32 ustorm_rx_prods_offset;
555
556 u32 rx_buf_size;
557 u32 rx_frag_size;
558 dma_addr_t status_blk_mapping;
559
560 enum bnx2x_tpa_mode_t mode;
561
562 u8 max_cos;
563 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
564
565 struct sw_rx_bd *rx_buf_ring;
566 struct sw_rx_page *rx_page_ring;
567
568 struct eth_rx_bd *rx_desc_ring;
569 dma_addr_t rx_desc_mapping;
570
571 union eth_rx_cqe *rx_comp_ring;
572 dma_addr_t rx_comp_mapping;
573
574
575 struct eth_rx_sge *rx_sge_ring;
576 dma_addr_t rx_sge_mapping;
577
578 u64 sge_mask[RX_SGE_MASK_LEN];
579
580 u32 cid;
581
582 __le16 fp_hc_idx;
583
584 u8 index;
585 u8 rx_queue;
586 u8 cl_id;
587 u8 cl_qzone_id;
588 u8 fw_sb_id;
589 u8 igu_sb_id;
590
591 u16 rx_bd_prod;
592 u16 rx_bd_cons;
593 u16 rx_comp_prod;
594 u16 rx_comp_cons;
595 u16 rx_sge_prod;
596
597 u16 last_max_sge;
598 __le16 *rx_cons_sb;
599
600
601 struct bnx2x_agg_info *tpa_info;
602 #ifdef BNX2X_STOP_ON_ERROR
603 u64 tpa_queue_used;
604 #endif
605
606
607
608
609 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
610 char name[FP_NAME_SIZE];
611
612 struct bnx2x_alloc_pool page_pool;
613 };
614
615 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
616 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
617 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
618 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
619
620
621 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
622
623 #define FCOE_IDX_OFFSET 0
624
625 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
626 FCOE_IDX_OFFSET)
627 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
628 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
629 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
630 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
631 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
632 txdata_ptr[FIRST_TX_COS_INDEX] \
633 ->var)
634
635 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
636 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
637 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
638
639
640 #define MAX_FETCH_BD 13
641 #define RX_COPY_THRESH 92
642
643 #define NUM_TX_RINGS 16
644 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
645 #define NEXT_PAGE_TX_DESC_CNT 1
646 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
647 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
648 #define MAX_TX_BD (NUM_TX_BD - 1)
649 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
650 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
651 (MAX_TX_DESC_CNT - 1)) ? \
652 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
653 (x) + 1)
654 #define TX_BD(x) ((x) & MAX_TX_BD)
655 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
656
657
658 #define NEXT_CNT_PER_TX_PKT(bds) \
659 (((bds) + MAX_TX_DESC_CNT - 1) / \
660 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
661
662
663
664
665
666
667
668 #define BDS_PER_TX_PKT 4
669 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
670
671 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
672 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
673
674
675 #define NUM_RX_RINGS 8
676 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
677 #define NEXT_PAGE_RX_DESC_CNT 2
678 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
679 #define RX_DESC_MASK (RX_DESC_CNT - 1)
680 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
681 #define MAX_RX_BD (NUM_RX_BD - 1)
682 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
683
684
685
686
687
688
689
690 #define NUM_BD_REQ BRB_SIZE(bp)
691 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
692 MAX_RX_DESC_CNT)
693 #define BD_TH_LO(bp) (NUM_BD_REQ + \
694 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
695 FW_DROP_LEVEL(bp))
696 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
697
698 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
699
700 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
701 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
702 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
703 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
704 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
705 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
706 MIN_RX_AVAIL))
707
708 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
709 (MAX_RX_DESC_CNT - 1)) ? \
710 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
711 (x) + 1)
712 #define RX_BD(x) ((x) & MAX_RX_BD)
713
714
715
716
717
718 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
719 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
720 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
721 #define NEXT_PAGE_RCQ_DESC_CNT 1
722 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
723 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
724 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
725 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
726 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
727 (MAX_RCQ_DESC_CNT - 1)) ? \
728 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
729 (x) + 1)
730 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
731
732
733
734
735
736
737
738 #define NUM_RCQ_REQ BRB_SIZE(bp)
739 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
740 MAX_RCQ_DESC_CNT)
741 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
742 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
743 FW_DROP_LEVEL(bp))
744 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
745
746
747 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
748 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
749
750 #define BNX2X_SWCID_SHIFT 17
751 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
752
753
754 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
755 #define CQE_CMD(x) (le32_to_cpu(x) >> \
756 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
757
758 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
759 le32_to_cpu((bd)->addr_lo))
760 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
761
762 #define BNX2X_DB_MIN_SHIFT 3
763 #define BNX2X_DB_SHIFT 3
764 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
765 #error "Min DB doorbell stride is 8"
766 #endif
767 #define DOORBELL_RELAXED(bp, cid, val) \
768 writel_relaxed((u32)(val), (bp)->doorbells + ((bp)->db_size * (cid)))
769
770
771 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
772 skb->csum_offset)
773 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
774 skb->csum_offset))
775
776 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
777
778 #define XMIT_PLAIN 0
779 #define XMIT_CSUM_V4 (1 << 0)
780 #define XMIT_CSUM_V6 (1 << 1)
781 #define XMIT_CSUM_TCP (1 << 2)
782 #define XMIT_GSO_V4 (1 << 3)
783 #define XMIT_GSO_V6 (1 << 4)
784 #define XMIT_CSUM_ENC_V4 (1 << 5)
785 #define XMIT_CSUM_ENC_V6 (1 << 6)
786 #define XMIT_GSO_ENC_V4 (1 << 7)
787 #define XMIT_GSO_ENC_V6 (1 << 8)
788
789 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
790 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
791
792 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
793 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
794
795
796 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
797 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
798 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
799 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
800 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
801
802 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
803
804 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
805 (((le16_to_cpu(flags) & \
806 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
807 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
808 == PRS_FLAG_OVERETH_IPV4)
809 #define BNX2X_RX_SUM_FIX(cqe) \
810 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
811
812 #define FP_USB_FUNC_OFF \
813 offsetof(struct cstorm_status_block_u, func)
814 #define FP_CSB_FUNC_OFF \
815 offsetof(struct cstorm_status_block_c, func)
816
817 #define HC_INDEX_ETH_RX_CQ_CONS 1
818
819 #define HC_INDEX_OOO_TX_CQ_CONS 4
820
821 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
822
823 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
824
825 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
826
827 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
828
829 #define BNX2X_RX_SB_INDEX \
830 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
831
832 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
833
834 #define BNX2X_TX_SB_INDEX_COS0 \
835 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
836
837
838
839
840
841 struct bnx2x_common {
842
843 u32 chip_id;
844
845 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
846
847 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
848 #define CHIP_NUM_57710 0x164e
849 #define CHIP_NUM_57711 0x164f
850 #define CHIP_NUM_57711E 0x1650
851 #define CHIP_NUM_57712 0x1662
852 #define CHIP_NUM_57712_MF 0x1663
853 #define CHIP_NUM_57712_VF 0x166f
854 #define CHIP_NUM_57713 0x1651
855 #define CHIP_NUM_57713E 0x1652
856 #define CHIP_NUM_57800 0x168a
857 #define CHIP_NUM_57800_MF 0x16a5
858 #define CHIP_NUM_57800_VF 0x16a9
859 #define CHIP_NUM_57810 0x168e
860 #define CHIP_NUM_57810_MF 0x16ae
861 #define CHIP_NUM_57810_VF 0x16af
862 #define CHIP_NUM_57811 0x163d
863 #define CHIP_NUM_57811_MF 0x163e
864 #define CHIP_NUM_57811_VF 0x163f
865 #define CHIP_NUM_57840_OBSOLETE 0x168d
866 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
867 #define CHIP_NUM_57840_4_10 0x16a1
868 #define CHIP_NUM_57840_2_20 0x16a2
869 #define CHIP_NUM_57840_MF 0x16a4
870 #define CHIP_NUM_57840_VF 0x16ad
871 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
872 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
873 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
874 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
875 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
876 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
877 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
878 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
879 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
880 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
881 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
882 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
883 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
884 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
885 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
886 #define CHIP_IS_57840(bp) \
887 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
888 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
889 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
890 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
891 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
892 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
893 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
894 CHIP_IS_57711E(bp))
895 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \
896 CHIP_IS_57811_MF(bp) || \
897 CHIP_IS_57811_VF(bp))
898 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
899 CHIP_IS_57712_MF(bp) || \
900 CHIP_IS_57712_VF(bp))
901 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
902 CHIP_IS_57800_MF(bp) || \
903 CHIP_IS_57800_VF(bp) || \
904 CHIP_IS_57810(bp) || \
905 CHIP_IS_57810_MF(bp) || \
906 CHIP_IS_57810_VF(bp) || \
907 CHIP_IS_57811xx(bp) || \
908 CHIP_IS_57840(bp) || \
909 CHIP_IS_57840_MF(bp) || \
910 CHIP_IS_57840_VF(bp))
911 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
912 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
913 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
914
915 #define CHIP_REV_SHIFT 12
916 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
917 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
918 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
919 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
920
921 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
922
923 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
924 !(CHIP_REV_VAL(bp) & 0x00001000))
925
926 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
927 (CHIP_REV_VAL(bp) & 0x00001000))
928
929 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
930 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
931
932 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
933 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
934 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
935 (CHIP_REV_SHIFT + 1)) \
936 << CHIP_REV_SHIFT)
937 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
938 CHIP_REV_SIM(bp) :\
939 CHIP_REV_VAL(bp))
940 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
941 (CHIP_REV(bp) == CHIP_REV_Bx))
942 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
943 (CHIP_REV(bp) == CHIP_REV_Ax))
944
945
946
947
948
949
950
951
952
953
954
955 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
956
957 int flash_size;
958 #define BNX2X_NVRAM_1MB_SIZE 0x20000
959 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
960 #define BNX2X_NVRAM_PAGE_SIZE 256
961
962 u32 shmem_base;
963 u32 shmem2_base;
964 u32 mf_cfg_base;
965 u32 mf2_cfg_base;
966
967 u32 hw_config;
968
969 u32 bc_ver;
970
971 u8 int_block;
972 #define INT_BLOCK_HC 0
973 #define INT_BLOCK_IGU 1
974 #define INT_BLOCK_MODE_NORMAL 0
975 #define INT_BLOCK_MODE_BW_COMP 2
976 #define CHIP_INT_MODE_IS_NBC(bp) \
977 (!CHIP_IS_E1x(bp) && \
978 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
979 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
980
981 u8 chip_port_mode;
982 #define CHIP_4_PORT_MODE 0x0
983 #define CHIP_2_PORT_MODE 0x1
984 #define CHIP_PORT_MODE_NONE 0x2
985 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
986 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
987
988 u32 boot_mode;
989 };
990
991
992 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
993 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
994
995 #define MAX_IGU_ATTN_ACK_TO 100
996
997
998
999
1000 struct bnx2x_port {
1001 u32 pmf;
1002
1003 u32 link_config[LINK_CONFIG_SIZE];
1004
1005 u32 supported[LINK_CONFIG_SIZE];
1006
1007 u32 advertising[LINK_CONFIG_SIZE];
1008
1009 u32 phy_addr;
1010
1011
1012 struct mutex phy_mutex;
1013
1014 u32 port_stx;
1015
1016 struct nig_stats old_nig_stats;
1017 };
1018
1019
1020
1021 #define STATS_OFFSET32(stat_name) \
1022 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
1023
1024
1025 #define BNX2X_MAX_NUM_OF_VFS 64
1026 #define BNX2X_VF_CID_WND 4
1027 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
1028
1029
1030 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
1031
1032
1033
1034
1035 #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS
1036 #define BNX2X_MAX_NUM_VF_QUEUES 64
1037 #define BNX2X_VF_ID_INVALID 0xFF
1038
1039
1040
1041
1042 #define BNX2X_VF_BAR_SIZE 512
1043 #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT))
1044 #error "VF doorbell bar size is 512"
1045 #endif
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070 #define FP_SB_MAX_E1x 16
1071
1072 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
1073
1074 union cdu_context {
1075 struct eth_context eth;
1076 char pad[1024];
1077 };
1078
1079
1080 #define CDU_ILT_PAGE_SZ_HW 2
1081 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW)
1082 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1083
1084 #define CNIC_ISCSI_CID_MAX 256
1085 #define CNIC_FCOE_CID_MAX 2048
1086 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1087 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1088
1089 #define QM_ILT_PAGE_SZ_HW 0
1090 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW)
1091 #define QM_CID_ROUND 1024
1092
1093
1094 #define TM_ILT_PAGE_SZ_HW 0
1095 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW)
1096 #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \
1097 BNX2X_VF_CIDS + \
1098 CNIC_ISCSI_CID_MAX)
1099 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1100 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1101
1102
1103 #define SRC_ILT_PAGE_SZ_HW 0
1104 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW)
1105 #define SRC_HASH_BITS 10
1106 #define SRC_CONN_NUM (1 << SRC_HASH_BITS)
1107 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1108 #define SRC_T2_SZ SRC_ILT_SZ
1109 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1110
1111 #define MAX_DMAE_C 8
1112
1113
1114 struct bnx2x_slowpath {
1115 union {
1116 struct mac_configuration_cmd e1x;
1117 struct eth_classify_rules_ramrod_data e2;
1118 } mac_rdata;
1119
1120 union {
1121 struct eth_classify_rules_ramrod_data e2;
1122 } vlan_rdata;
1123
1124 union {
1125 struct tstorm_eth_mac_filter_config e1x;
1126 struct eth_filter_rules_ramrod_data e2;
1127 } rx_mode_rdata;
1128
1129 union {
1130 struct mac_configuration_cmd e1;
1131 struct eth_multicast_rules_ramrod_data e2;
1132 } mcast_rdata;
1133
1134 struct eth_rss_update_ramrod_data rss_rdata;
1135
1136
1137 union {
1138 struct client_init_ramrod_data init_data;
1139 struct client_update_ramrod_data update_data;
1140 struct tpa_update_ramrod_data tpa_data;
1141 } q_rdata;
1142
1143 union {
1144 struct function_start_data func_start;
1145
1146 struct flow_control_configuration pfc_config;
1147 } func_rdata;
1148
1149
1150
1151
1152
1153
1154 union {
1155 struct afex_vif_list_ramrod_data viflist_data;
1156 struct function_update_data func_update;
1157 } func_afex_rdata;
1158
1159
1160 struct dmae_command dmae[MAX_DMAE_C];
1161
1162 u32 stats_comp;
1163 union mac_stats mac_stats;
1164 struct nig_stats nig_stats;
1165 struct host_port_stats port_stats;
1166 struct host_func_stats func_stats;
1167
1168 u32 wb_comp;
1169 u32 wb_data[4];
1170
1171 union drv_info_to_mcp drv_info_to_mcp;
1172 };
1173
1174 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1175 #define bnx2x_sp_mapping(bp, var) \
1176 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1177
1178
1179 #define MAX_DYNAMIC_ATTN_GRPS 8
1180
1181 struct attn_route {
1182 u32 sig[5];
1183 };
1184
1185 struct iro {
1186 u32 base;
1187 u16 m1;
1188 u16 m2;
1189 u16 m3;
1190 u16 size;
1191 };
1192
1193 struct hw_context {
1194 union cdu_context *vcxt;
1195 dma_addr_t cxt_mapping;
1196 size_t size;
1197 };
1198
1199
1200 struct bnx2x_ilt;
1201
1202 struct bnx2x_vfdb;
1203
1204 enum bnx2x_recovery_state {
1205 BNX2X_RECOVERY_DONE,
1206 BNX2X_RECOVERY_INIT,
1207 BNX2X_RECOVERY_WAIT,
1208 BNX2X_RECOVERY_FAILED,
1209 BNX2X_RECOVERY_NIC_LOADING
1210 };
1211
1212
1213
1214
1215
1216 #define NUM_EQ_PAGES 1
1217 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1218 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1219 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1220 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1221 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1222
1223
1224 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1225 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1226
1227
1228 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1229
1230 #define BNX2X_EQ_INDEX \
1231 (&bp->def_status_blk->sp_sb.\
1232 index_values[HC_SP_INDEX_EQ_CONS])
1233
1234
1235
1236
1237
1238 struct bnx2x_link_report_data {
1239 u16 line_speed;
1240 unsigned long link_report_flags;
1241 };
1242
1243 enum {
1244 BNX2X_LINK_REPORT_FD,
1245 BNX2X_LINK_REPORT_LINK_DOWN,
1246 BNX2X_LINK_REPORT_RX_FC_ON,
1247 BNX2X_LINK_REPORT_TX_FC_ON,
1248 };
1249
1250 enum {
1251 BNX2X_PORT_QUERY_IDX,
1252 BNX2X_PF_QUERY_IDX,
1253 BNX2X_FCOE_QUERY_IDX,
1254 BNX2X_FIRST_QUEUE_QUERY_IDX,
1255 };
1256
1257 struct bnx2x_fw_stats_req {
1258 struct stats_query_header hdr;
1259 struct stats_query_entry query[FP_SB_MAX_E1x+
1260 BNX2X_FIRST_QUEUE_QUERY_IDX];
1261 };
1262
1263 struct bnx2x_fw_stats_data {
1264 struct stats_counter storm_counters;
1265 struct per_port_stats port;
1266 struct per_pf_stats pf;
1267 struct fcoe_statistics_params fcoe;
1268 struct per_queue_stats queue_stats[1];
1269 };
1270
1271
1272 enum sp_rtnl_flag {
1273 BNX2X_SP_RTNL_SETUP_TC,
1274 BNX2X_SP_RTNL_TX_TIMEOUT,
1275 BNX2X_SP_RTNL_FAN_FAILURE,
1276 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1277 BNX2X_SP_RTNL_ENABLE_SRIOV,
1278 BNX2X_SP_RTNL_VFPF_MCAST,
1279 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
1280 BNX2X_SP_RTNL_RX_MODE,
1281 BNX2X_SP_RTNL_HYPERVISOR_VLAN,
1282 BNX2X_SP_RTNL_TX_STOP,
1283 BNX2X_SP_RTNL_GET_DRV_VERSION,
1284 BNX2X_SP_RTNL_CHANGE_UDP_PORT,
1285 BNX2X_SP_RTNL_UPDATE_SVID,
1286 };
1287
1288 enum bnx2x_iov_flag {
1289 BNX2X_IOV_HANDLE_VF_MSG,
1290 BNX2X_IOV_HANDLE_FLR,
1291 };
1292
1293 struct bnx2x_prev_path_list {
1294 struct list_head list;
1295 u8 bus;
1296 u8 slot;
1297 u8 path;
1298 u8 aer;
1299 u8 undi;
1300 };
1301
1302 struct bnx2x_sp_objs {
1303
1304 struct bnx2x_vlan_mac_obj mac_obj;
1305
1306
1307 struct bnx2x_queue_sp_obj q_obj;
1308
1309
1310 struct bnx2x_vlan_mac_obj vlan_obj;
1311 };
1312
1313 struct bnx2x_fp_stats {
1314 struct tstorm_per_queue_stats old_tclient;
1315 struct ustorm_per_queue_stats old_uclient;
1316 struct xstorm_per_queue_stats old_xclient;
1317 struct bnx2x_eth_q_stats eth_q_stats;
1318 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1319 };
1320
1321 enum {
1322 SUB_MF_MODE_UNKNOWN = 0,
1323 SUB_MF_MODE_UFP,
1324 SUB_MF_MODE_NPAR1_DOT_5,
1325 SUB_MF_MODE_BD,
1326 };
1327
1328 struct bnx2x_vlan_entry {
1329 struct list_head link;
1330 u16 vid;
1331 bool hw;
1332 };
1333
1334 enum bnx2x_udp_port_type {
1335 BNX2X_UDP_PORT_VXLAN,
1336 BNX2X_UDP_PORT_GENEVE,
1337 BNX2X_UDP_PORT_MAX,
1338 };
1339
1340 struct bnx2x_udp_tunnel {
1341 u16 dst_port;
1342 u8 count;
1343 };
1344
1345 struct bnx2x {
1346
1347
1348
1349 struct bnx2x_fastpath *fp;
1350 struct bnx2x_sp_objs *sp_objs;
1351 struct bnx2x_fp_stats *fp_stats;
1352 struct bnx2x_fp_txdata *bnx2x_txq;
1353 void __iomem *regview;
1354 void __iomem *doorbells;
1355 u16 db_size;
1356
1357 u8 pf_num;
1358 u8 pfid;
1359 int base_fw_ndsb;
1360 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1361 #define BP_PORT(bp) (bp->pfid & 1)
1362 #define BP_FUNC(bp) (bp->pfid)
1363 #define BP_ABS_FUNC(bp) (bp->pf_num)
1364 #define BP_VN(bp) ((bp)->pfid >> 1)
1365 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1366 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1367 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1368 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1369 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1370
1371 #ifdef CONFIG_BNX2X_SRIOV
1372
1373 struct mutex vf2pf_mutex;
1374
1375 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1376 dma_addr_t vf2pf_mbox_mapping;
1377
1378
1379 struct pfvf_acquire_resp_tlv acquire_resp;
1380
1381
1382 union pf_vf_bulletin *pf2vf_bulletin;
1383 dma_addr_t pf2vf_bulletin_mapping;
1384
1385 union pf_vf_bulletin shadow_bulletin;
1386 struct pf_vf_bulletin_content old_bulletin;
1387
1388 u16 requested_nr_virtfn;
1389 #endif
1390
1391 struct net_device *dev;
1392 struct pci_dev *pdev;
1393
1394 const struct iro *iro_arr;
1395 #define IRO (bp->iro_arr)
1396
1397 enum bnx2x_recovery_state recovery_state;
1398 int is_leader;
1399 struct msix_entry *msix_table;
1400
1401 int tx_ring_size;
1402
1403
1404 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
1405 #define ETH_MIN_PACKET_SIZE (ETH_ZLEN - ETH_HLEN)
1406 #define ETH_MAX_PACKET_SIZE ETH_DATA_LEN
1407 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1408
1409 #define ETH_MAX_TPA_HEADER_SIZE 72
1410
1411
1412
1413
1414 #define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
1415
1416
1417
1418
1419
1420
1421
1422 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1423
1424 #define BNX2X_FW_RX_ALIGN_END \
1425 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1426 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1427
1428 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1429
1430 struct host_sp_status_block *def_status_blk;
1431 #define DEF_SB_IGU_ID 16
1432 #define DEF_SB_ID HC_SP_SB_ID
1433 __le16 def_idx;
1434 __le16 def_att_idx;
1435 u32 attn_state;
1436 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1437
1438
1439 struct eth_spe *spq;
1440 dma_addr_t spq_mapping;
1441 u16 spq_prod_idx;
1442 struct eth_spe *spq_prod_bd;
1443 struct eth_spe *spq_last_bd;
1444 __le16 *dsb_sp_prod;
1445 atomic_t cq_spq_left;
1446
1447 spinlock_t spq_lock;
1448
1449
1450 union event_ring_elem *eq_ring;
1451 dma_addr_t eq_mapping;
1452 u16 eq_prod;
1453 u16 eq_cons;
1454 __le16 *eq_cons_sb;
1455 atomic_t eq_spq_left;
1456
1457
1458 u16 stats_pending;
1459
1460 u16 stats_comp;
1461
1462
1463
1464 int panic;
1465 int msg_enable;
1466
1467 u32 flags;
1468 #define PCIX_FLAG (1 << 0)
1469 #define PCI_32BIT_FLAG (1 << 1)
1470 #define ONE_PORT_FLAG (1 << 2)
1471 #define NO_WOL_FLAG (1 << 3)
1472 #define USING_MSIX_FLAG (1 << 5)
1473 #define USING_MSI_FLAG (1 << 6)
1474 #define DISABLE_MSI_FLAG (1 << 7)
1475 #define NO_MCP_FLAG (1 << 9)
1476 #define MF_FUNC_DIS (1 << 11)
1477 #define OWN_CNIC_IRQ (1 << 12)
1478 #define NO_ISCSI_OOO_FLAG (1 << 13)
1479 #define NO_ISCSI_FLAG (1 << 14)
1480 #define NO_FCOE_FLAG (1 << 15)
1481 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1482 #define TX_SWITCHING (1 << 18)
1483 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1484 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1485 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1486 #define IS_VF_FLAG (1 << 22)
1487 #define BC_SUPPORTS_RMMOD_CMD (1 << 23)
1488 #define HAS_PHYS_PORT_ID (1 << 24)
1489 #define AER_ENABLED (1 << 25)
1490 #define PTP_SUPPORTED (1 << 26)
1491 #define TX_TIMESTAMPING_EN (1 << 27)
1492
1493 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
1494
1495 #ifdef CONFIG_BNX2X_SRIOV
1496 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1497 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
1498 #else
1499 #define IS_VF(bp) false
1500 #define IS_PF(bp) true
1501 #endif
1502
1503 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1504 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1505 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1506
1507 u8 cnic_support;
1508 bool cnic_enabled;
1509 bool cnic_loaded;
1510 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1511
1512
1513
1514
1515 bool fcoe_init;
1516
1517 int mrrs;
1518
1519 struct delayed_work sp_task;
1520 struct delayed_work iov_task;
1521
1522 atomic_t interrupt_occurred;
1523 struct delayed_work sp_rtnl_task;
1524
1525 struct delayed_work period_task;
1526 struct timer_list timer;
1527 int current_interval;
1528
1529 u16 fw_seq;
1530 u16 fw_drv_pulse_wr_seq;
1531 u32 func_stx;
1532
1533 struct link_params link_params;
1534 struct link_vars link_vars;
1535 u32 link_cnt;
1536 struct bnx2x_link_report_data last_reported_link;
1537 bool force_link_down;
1538
1539 struct mdio_if_info mdio;
1540
1541 struct bnx2x_common common;
1542 struct bnx2x_port port;
1543
1544 struct cmng_init cmng;
1545
1546 u32 mf_config[E1HVN_MAX];
1547 u32 mf_ext_config;
1548 u32 path_has_ovlan;
1549 u16 mf_ov;
1550 u8 mf_mode;
1551 #define IS_MF(bp) (bp->mf_mode != 0)
1552 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1553 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1554 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1555 u8 mf_sub_mode;
1556 #define IS_MF_UFP(bp) (IS_MF_SD(bp) && \
1557 bp->mf_sub_mode == SUB_MF_MODE_UFP)
1558 #define IS_MF_BD(bp) (IS_MF_SD(bp) && \
1559 bp->mf_sub_mode == SUB_MF_MODE_BD)
1560
1561 u8 wol;
1562
1563 int rx_ring_size;
1564
1565 u16 tx_quick_cons_trip_int;
1566 u16 tx_quick_cons_trip;
1567 u16 tx_ticks_int;
1568 u16 tx_ticks;
1569
1570 u16 rx_quick_cons_trip_int;
1571 u16 rx_quick_cons_trip;
1572 u16 rx_ticks_int;
1573 u16 rx_ticks;
1574
1575 #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR)
1576
1577 u32 lin_cnt;
1578
1579 u16 state;
1580 #define BNX2X_STATE_CLOSED 0
1581 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1582 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1583 #define BNX2X_STATE_OPEN 0x3000
1584 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1585 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1586
1587 #define BNX2X_STATE_DIAG 0xe000
1588 #define BNX2X_STATE_ERROR 0xf000
1589
1590 #define BNX2X_MAX_PRIORITY 8
1591 int num_queues;
1592 uint num_ethernet_queues;
1593 uint num_cnic_queues;
1594 int disable_tpa;
1595
1596 u32 rx_mode;
1597 #define BNX2X_RX_MODE_NONE 0
1598 #define BNX2X_RX_MODE_NORMAL 1
1599 #define BNX2X_RX_MODE_ALLMULTI 2
1600 #define BNX2X_RX_MODE_PROMISC 3
1601 #define BNX2X_MAX_MULTICAST 64
1602
1603 u8 igu_dsb_id;
1604 u8 igu_base_sb;
1605 u8 igu_sb_cnt;
1606 u8 min_msix_vec_cnt;
1607
1608 u32 igu_base_addr;
1609 dma_addr_t def_status_blk_mapping;
1610
1611 struct bnx2x_slowpath *slowpath;
1612 dma_addr_t slowpath_mapping;
1613
1614
1615 struct mutex drv_info_mutex;
1616 bool drv_info_mng_owner;
1617
1618
1619 u8 fw_stats_num;
1620
1621
1622
1623
1624
1625 void *fw_stats;
1626 dma_addr_t fw_stats_mapping;
1627
1628
1629
1630
1631
1632 struct bnx2x_fw_stats_req *fw_stats_req;
1633 dma_addr_t fw_stats_req_mapping;
1634 int fw_stats_req_sz;
1635
1636
1637
1638
1639
1640 struct bnx2x_fw_stats_data *fw_stats_data;
1641 dma_addr_t fw_stats_data_mapping;
1642 int fw_stats_data_sz;
1643
1644
1645
1646
1647 #define ILT_MAX_L2_LINES 32
1648 struct hw_context context[ILT_MAX_L2_LINES];
1649
1650 struct bnx2x_ilt *ilt;
1651 #define BP_ILT(bp) ((bp)->ilt)
1652 #define ILT_MAX_LINES 256
1653
1654
1655
1656
1657 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1658
1659
1660
1661
1662
1663
1664 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1665 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1666 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1667 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1668 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1669 ILT_PAGE_CIDS))
1670
1671 int qm_cid_count;
1672
1673 bool dropless_fc;
1674
1675 void *t2;
1676 dma_addr_t t2_mapping;
1677 struct cnic_ops __rcu *cnic_ops;
1678 void *cnic_data;
1679 u32 cnic_tag;
1680 struct cnic_eth_dev cnic_eth_dev;
1681 union host_hc_status_block cnic_sb;
1682 dma_addr_t cnic_sb_mapping;
1683 struct eth_spe *cnic_kwq;
1684 struct eth_spe *cnic_kwq_prod;
1685 struct eth_spe *cnic_kwq_cons;
1686 struct eth_spe *cnic_kwq_last;
1687 u16 cnic_kwq_pending;
1688 u16 cnic_spq_pending;
1689 u8 fip_mac[ETH_ALEN];
1690 struct mutex cnic_mutex;
1691 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1692
1693
1694 u8 cnic_base_cl_id;
1695
1696 int dmae_ready;
1697
1698 spinlock_t dmae_lock;
1699
1700
1701 struct mutex fw_mb_mutex;
1702
1703
1704 int stats_state;
1705
1706
1707 struct semaphore stats_lock;
1708
1709
1710 struct dmae_command stats_dmae;
1711 int executer_idx;
1712
1713 u16 stats_counter;
1714 struct bnx2x_eth_stats eth_stats;
1715 struct host_func_stats func_stats;
1716 struct bnx2x_eth_stats_old eth_stats_old;
1717 struct bnx2x_net_stats_old net_stats_old;
1718 struct bnx2x_fw_port_stats_old fw_stats_old;
1719 bool stats_init;
1720
1721 struct z_stream_s *strm;
1722 void *gunzip_buf;
1723 dma_addr_t gunzip_mapping;
1724 int gunzip_outlen;
1725 #define FW_BUF_SIZE 0x8000
1726 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1727 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1728 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1729
1730 struct raw_op *init_ops;
1731
1732 u16 *init_ops_offsets;
1733
1734 u32 *init_data;
1735 u32 init_mode_flags;
1736 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1737
1738 const u8 *tsem_int_table_data;
1739 const u8 *tsem_pram_data;
1740 const u8 *usem_int_table_data;
1741 const u8 *usem_pram_data;
1742 const u8 *xsem_int_table_data;
1743 const u8 *xsem_pram_data;
1744 const u8 *csem_int_table_data;
1745 const u8 *csem_pram_data;
1746 #define INIT_OPS(bp) (bp->init_ops)
1747 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1748 #define INIT_DATA(bp) (bp->init_data)
1749 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1750 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1751 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1752 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1753 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1754 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1755 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1756 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1757
1758 #define PHY_FW_VER_LEN 20
1759 char fw_ver[32];
1760 const struct firmware *firmware;
1761
1762 struct bnx2x_vfdb *vfdb;
1763 #define IS_SRIOV(bp) ((bp)->vfdb)
1764
1765
1766 u16 dcb_state;
1767 #define BNX2X_DCB_STATE_OFF 0
1768 #define BNX2X_DCB_STATE_ON 1
1769
1770
1771 int dcbx_enabled;
1772 #define BNX2X_DCBX_ENABLED_OFF 0
1773 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1774 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1775 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1776
1777 bool dcbx_mode_uset;
1778
1779 struct bnx2x_config_dcbx_params dcbx_config_params;
1780 struct bnx2x_dcbx_port_params dcbx_port_params;
1781 int dcb_version;
1782
1783
1784 struct bnx2x_credit_pool_obj vlans_pool;
1785
1786 struct bnx2x_credit_pool_obj macs_pool;
1787
1788
1789 struct bnx2x_rx_mode_obj rx_mode_obj;
1790
1791
1792 struct bnx2x_mcast_obj mcast_obj;
1793
1794
1795 struct bnx2x_rss_config_obj rss_conf_obj;
1796
1797
1798 struct bnx2x_func_sp_obj func_obj;
1799
1800 unsigned long sp_state;
1801
1802
1803 unsigned long sp_rtnl_state;
1804
1805
1806 unsigned long iov_task_state;
1807
1808
1809 struct dcbx_features dcbx_local_feat;
1810 u32 dcbx_error;
1811
1812 #ifdef BCM_DCBNL
1813 struct dcbx_features dcbx_remote_feat;
1814 u32 dcbx_remote_flags;
1815 #endif
1816
1817 int afex_def_vlan_tag;
1818 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1819 u32 pending_max;
1820
1821
1822 u8 max_cos;
1823
1824
1825 u8 prio_to_cos[8];
1826
1827 int fp_array_size;
1828 u32 dump_preset_idx;
1829
1830 u8 phys_port_id[ETH_ALEN];
1831
1832
1833 struct ptp_clock *ptp_clock;
1834 struct ptp_clock_info ptp_clock_info;
1835 struct work_struct ptp_task;
1836 struct cyclecounter cyclecounter;
1837 struct timecounter timecounter;
1838 bool timecounter_init_done;
1839 struct sk_buff *ptp_tx_skb;
1840 unsigned long ptp_tx_start;
1841 bool hwtstamp_ioctl_called;
1842 u16 tx_type;
1843 u16 rx_filter;
1844
1845 struct bnx2x_link_report_data vf_link_vars;
1846 struct list_head vlan_reg;
1847 u16 vlan_cnt;
1848 u16 vlan_credit;
1849 bool accept_any_vlan;
1850
1851
1852 struct bnx2x_udp_tunnel udp_tunnel_ports[BNX2X_UDP_PORT_MAX];
1853 };
1854
1855
1856 extern int num_queues;
1857 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1858 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1859 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1860 (bp)->num_cnic_queues)
1861 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1862
1863 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1864
1865 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1866
1867
1868 #define RSS_IPV4_CAP_MASK \
1869 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1870
1871 #define RSS_IPV4_TCP_CAP_MASK \
1872 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1873
1874 #define RSS_IPV6_CAP_MASK \
1875 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1876
1877 #define RSS_IPV6_TCP_CAP_MASK \
1878 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1879
1880 struct bnx2x_func_init_params {
1881
1882 bool spq_active;
1883 dma_addr_t spq_map;
1884 u16 spq_prod;
1885
1886 u16 func_id;
1887 u16 pf_id;
1888 };
1889
1890 #define for_each_cnic_queue(bp, var) \
1891 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1892 (var)++) \
1893 if (skip_queue(bp, var)) \
1894 continue; \
1895 else
1896
1897 #define for_each_eth_queue(bp, var) \
1898 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1899
1900 #define for_each_nondefault_eth_queue(bp, var) \
1901 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1902
1903 #define for_each_queue(bp, var) \
1904 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1905 if (skip_queue(bp, var)) \
1906 continue; \
1907 else
1908
1909
1910 #define for_each_valid_rx_queue(bp, var) \
1911 for ((var) = 0; \
1912 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1913 BNX2X_NUM_ETH_QUEUES(bp)); \
1914 (var)++) \
1915 if (skip_rx_queue(bp, var)) \
1916 continue; \
1917 else
1918
1919 #define for_each_rx_queue_cnic(bp, var) \
1920 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1921 (var)++) \
1922 if (skip_rx_queue(bp, var)) \
1923 continue; \
1924 else
1925
1926 #define for_each_rx_queue(bp, var) \
1927 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1928 if (skip_rx_queue(bp, var)) \
1929 continue; \
1930 else
1931
1932
1933 #define for_each_valid_tx_queue(bp, var) \
1934 for ((var) = 0; \
1935 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1936 BNX2X_NUM_ETH_QUEUES(bp)); \
1937 (var)++) \
1938 if (skip_tx_queue(bp, var)) \
1939 continue; \
1940 else
1941
1942 #define for_each_tx_queue_cnic(bp, var) \
1943 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1944 (var)++) \
1945 if (skip_tx_queue(bp, var)) \
1946 continue; \
1947 else
1948
1949 #define for_each_tx_queue(bp, var) \
1950 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1951 if (skip_tx_queue(bp, var)) \
1952 continue; \
1953 else
1954
1955 #define for_each_nondefault_queue(bp, var) \
1956 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1957 if (skip_queue(bp, var)) \
1958 continue; \
1959 else
1960
1961 #define for_each_cos_in_tx_queue(fp, var) \
1962 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1963
1964
1965
1966
1967 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1968
1969
1970
1971
1972 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1973
1974 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1995 struct bnx2x_vlan_mac_obj *obj, bool set,
1996 int mac_type, unsigned long *ramrod_flags);
1997
1998 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
1999 struct bnx2x_vlan_mac_obj *obj, bool set,
2000 unsigned long *ramrod_flags);
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016 int bnx2x_del_all_macs(struct bnx2x *bp,
2017 struct bnx2x_vlan_mac_obj *mac_obj,
2018 int mac_type, bool wait_for_comp);
2019
2020
2021 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
2022 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2023 u8 vf_valid, int fw_sb_id, int igu_sb_id);
2024 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
2025 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2026 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
2027 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2028 void bnx2x_read_mf_cfg(struct bnx2x *bp);
2029
2030 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
2031
2032
2033 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
2034 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
2035 u32 len32);
2036 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2037 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
2038 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
2039 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
2040 bool with_comp, u8 comp_type);
2041
2042 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2043 u8 src_type, u8 dst_type);
2044 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2045 u32 *comp);
2046
2047
2048 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2049 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
2050 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
2051 u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
2052 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
2053 char *msg, u32 poll_cnt);
2054
2055 void bnx2x_calc_fc_adv(struct bnx2x *bp);
2056 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2057 u32 data_hi, u32 data_lo, int cmd_type);
2058 void bnx2x_update_coalesce(struct bnx2x *bp);
2059 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
2060
2061 bool bnx2x_port_after_undi(struct bnx2x *bp);
2062
2063 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
2064 int wait)
2065 {
2066 u32 val;
2067
2068 do {
2069 val = REG_RD(bp, reg);
2070 if (val == expected)
2071 break;
2072 ms -= wait;
2073 msleep(wait);
2074
2075 } while (ms > 0);
2076
2077 return val;
2078 }
2079
2080 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
2081 bool is_pf);
2082
2083 #define BNX2X_ILT_ZALLOC(x, y, size) \
2084 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL)
2085
2086 #define BNX2X_ILT_FREE(x, y, size) \
2087 do { \
2088 if (x) { \
2089 dma_free_coherent(&bp->pdev->dev, size, x, y); \
2090 x = NULL; \
2091 y = 0; \
2092 } \
2093 } while (0)
2094
2095 #define ILOG2(x) (ilog2((x)))
2096
2097 #define ILT_NUM_PAGE_ENTRIES (3072)
2098
2099
2100
2101
2102 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
2103
2104 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
2105
2106
2107
2108
2109
2110
2111 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
2112 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
2113
2114
2115 #define LOAD_NORMAL 0
2116 #define LOAD_OPEN 1
2117 #define LOAD_DIAG 2
2118 #define LOAD_LOOPBACK_EXT 3
2119 #define UNLOAD_NORMAL 0
2120 #define UNLOAD_CLOSE 1
2121 #define UNLOAD_RECOVERY 2
2122
2123
2124 #define DMAE_TIMEOUT -1
2125 #define DMAE_PCI_ERROR -2
2126 #define DMAE_NOT_RDY -3
2127 #define DMAE_PCI_ERR_FLAG 0x80000000
2128
2129 #define DMAE_SRC_PCI 0
2130 #define DMAE_SRC_GRC 1
2131
2132 #define DMAE_DST_NONE 0
2133 #define DMAE_DST_PCI 1
2134 #define DMAE_DST_GRC 2
2135
2136 #define DMAE_COMP_PCI 0
2137 #define DMAE_COMP_GRC 1
2138
2139
2140
2141 #define DMAE_COMP_REGULAR 0
2142 #define DMAE_COM_SET_ERR 1
2143
2144 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
2145 DMAE_COMMAND_SRC_SHIFT)
2146 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
2147 DMAE_COMMAND_SRC_SHIFT)
2148
2149 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
2150 DMAE_COMMAND_DST_SHIFT)
2151 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
2152 DMAE_COMMAND_DST_SHIFT)
2153
2154 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
2155 DMAE_COMMAND_C_DST_SHIFT)
2156 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
2157 DMAE_COMMAND_C_DST_SHIFT)
2158
2159 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
2160
2161 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2162 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2163 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2164 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2165
2166 #define DMAE_CMD_PORT_0 0
2167 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2168
2169 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
2170 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
2171 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
2172
2173 #define DMAE_SRC_PF 0
2174 #define DMAE_SRC_VF 1
2175
2176 #define DMAE_DST_PF 0
2177 #define DMAE_DST_VF 1
2178
2179 #define DMAE_C_SRC 0
2180 #define DMAE_C_DST 1
2181
2182 #define DMAE_LEN32_RD_MAX 0x80
2183 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2184
2185 #define DMAE_COMP_VAL 0x60d0d0ae
2186
2187
2188
2189 #define MAX_DMAE_C_PER_PORT 8
2190 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2191 BP_VN(bp))
2192 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2193 E1HVN_MAX)
2194
2195
2196
2197
2198
2199
2200 #define BNX2X_FW_DMAE_C 13
2201
2202
2203 #define PCICFG_LINK_WIDTH 0x1f00000
2204 #define PCICFG_LINK_WIDTH_SHIFT 20
2205 #define PCICFG_LINK_SPEED 0xf0000
2206 #define PCICFG_LINK_SPEED_SHIFT 16
2207
2208 #define BNX2X_NUM_TESTS_SF 7
2209 #define BNX2X_NUM_TESTS_MF 3
2210 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2211 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
2212
2213 #define BNX2X_PHY_LOOPBACK 0
2214 #define BNX2X_MAC_LOOPBACK 1
2215 #define BNX2X_EXT_LOOPBACK 2
2216 #define BNX2X_PHY_LOOPBACK_FAILED 1
2217 #define BNX2X_MAC_LOOPBACK_FAILED 2
2218 #define BNX2X_EXT_LOOPBACK_FAILED 3
2219 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2220 BNX2X_PHY_LOOPBACK_FAILED)
2221
2222 #define STROM_ASSERT_ARRAY_SIZE 50
2223
2224
2225 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
2226 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2227 (x))
2228
2229 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2230 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2231
2232 #define BNX2X_BTR 4
2233 #define MAX_SPQ_PENDING 8
2234
2235
2236
2237 #define DEF_MIN_RATE 100
2238
2239 #define RS_PERIODIC_TIMEOUT_USEC 400
2240
2241
2242 #define QM_ARB_BYTES 160000
2243
2244 #define MIN_RES 100
2245
2246 #define MIN_ABOVE_THRESH 32768
2247
2248
2249 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2250
2251 #define FAIR_MEM 2
2252
2253 #define ATTN_NIG_FOR_FUNC (1L << 8)
2254 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2255 #define GPIO_2_FUNC (1L << 10)
2256 #define GPIO_3_FUNC (1L << 11)
2257 #define GPIO_4_FUNC (1L << 12)
2258 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2259 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2260 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2261 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2262 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2263 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2264
2265 #define ATTN_HARD_WIRED_MASK 0xff00
2266 #define ATTENTION_ID 4
2267
2268 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \
2269 IS_MF_FCOE_AFEX(bp))
2270
2271
2272
2273 #define BNX2X_PMF_LINK_ASSERT \
2274 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2275
2276 #define BNX2X_MC_ASSERT_BITS \
2277 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2278 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2279 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2280 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2281
2282 #define BNX2X_MCP_ASSERT \
2283 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2284
2285 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2286 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2287 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2288 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2289 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2290 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2291 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2292
2293 #define HW_INTERRUPT_ASSERT_SET_0 \
2294 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2295 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2296 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2297 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2298 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2299 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2300 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2301 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2302 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2303 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2304 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2305 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2306 #define HW_INTERRUPT_ASSERT_SET_1 \
2307 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2308 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2309 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2310 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2311 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2312 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2313 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2314 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2315 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2316 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2317 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2318 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2319 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2320 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2321 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2322 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2323 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2324 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2325 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2326 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2327 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2328 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2329 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2330 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2331 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2332 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2333 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2334 #define HW_INTERRUPT_ASSERT_SET_2 \
2335 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2336 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2337 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2338 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2339 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2340 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2341 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2342 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2343 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2344 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2345 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2346 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2347 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2348
2349 #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \
2350 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2351 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2352 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
2353
2354 #define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \
2355 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2356
2357 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2358 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2359
2360 #define MULTI_MASK 0x7f
2361
2362 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2363 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2364 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2365 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2366
2367 #define DEF_USB_IGU_INDEX_OFF \
2368 offsetof(struct cstorm_def_status_block_u, igu_index)
2369 #define DEF_CSB_IGU_INDEX_OFF \
2370 offsetof(struct cstorm_def_status_block_c, igu_index)
2371 #define DEF_XSB_IGU_INDEX_OFF \
2372 offsetof(struct xstorm_def_status_block, igu_index)
2373 #define DEF_TSB_IGU_INDEX_OFF \
2374 offsetof(struct tstorm_def_status_block, igu_index)
2375
2376 #define DEF_USB_SEGMENT_OFF \
2377 offsetof(struct cstorm_def_status_block_u, segment)
2378 #define DEF_CSB_SEGMENT_OFF \
2379 offsetof(struct cstorm_def_status_block_c, segment)
2380 #define DEF_XSB_SEGMENT_OFF \
2381 offsetof(struct xstorm_def_status_block, segment)
2382 #define DEF_TSB_SEGMENT_OFF \
2383 offsetof(struct tstorm_def_status_block, segment)
2384
2385 #define BNX2X_SP_DSB_INDEX \
2386 (&bp->def_status_blk->sp_sb.\
2387 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2388
2389 #define CAM_IS_INVALID(x) \
2390 (GET_FLAG(x.flags, \
2391 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2392 (T_ETH_MAC_COMMAND_INVALIDATE))
2393
2394
2395 #define MC_HASH_SIZE 8
2396 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2397 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2398
2399 #ifndef PXP2_REG_PXP2_INT_STS
2400 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2401 #endif
2402
2403 #ifndef ETH_MAX_RX_CLIENTS_E2
2404 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2405 #endif
2406
2407 #define BNX2X_VPD_LEN 128
2408 #define VENDOR_ID_LEN 4
2409
2410 #define VF_ACQUIRE_THRESH 3
2411 #define VF_ACQUIRE_MAC_FILTERS 1
2412 #define VF_ACQUIRE_MC_FILTERS 10
2413 #define VF_ACQUIRE_VLAN_FILTERS 2
2414
2415 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2416 (!((me_reg) & ME_REG_VF_ERR)))
2417 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err);
2418
2419
2420 #define CMNG_FNS_NONE 0
2421 #define CMNG_FNS_MINMAX 1
2422
2423 #define HC_SEG_ACCESS_DEF 0
2424 #define HC_SEG_ACCESS_ATTN 4
2425 #define HC_SEG_ACCESS_NORM 0
2426
2427 static const u32 dmae_reg_go_c[] = {
2428 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2429 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2430 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2431 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2432 };
2433
2434 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2435 void bnx2x_notify_link_changed(struct bnx2x *bp);
2436
2437 #define BNX2X_MF_SD_PROTOCOL(bp) \
2438 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2439
2440 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2441 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2442
2443 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2444 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2445
2446 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2447 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2448 #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp))
2449
2450 #define IS_MF_ISCSI_ONLY(bp) (IS_MF_ISCSI_SD(bp) || IS_MF_ISCSI_SI(bp))
2451
2452 #define BNX2X_MF_EXT_PROTOCOL_MASK \
2453 (MACP_FUNC_CFG_FLAGS_ETHERNET | \
2454 MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD | \
2455 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2456
2457 #define BNX2X_MF_EXT_PROT(bp) ((bp)->mf_ext_config & \
2458 BNX2X_MF_EXT_PROTOCOL_MASK)
2459
2460 #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) \
2461 (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2462
2463 #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) \
2464 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2465
2466 #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) \
2467 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD)
2468
2469 #define IS_MF_FCOE_AFEX(bp) \
2470 (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))
2471
2472 #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) \
2473 (IS_MF_SD(bp) && \
2474 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2475 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2476
2477 #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) \
2478 (IS_MF_SI(bp) && \
2479 (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \
2480 BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)))
2481
2482 #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) \
2483 (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) || \
2484 IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp))
2485
2486
2487
2488
2489 #define IS_MF_PERCENT_BW(bp) (IS_MF_SI(bp) || IS_MF_UFP(bp) || IS_MF_BD(bp))
2490
2491 #define SET_FLAG(value, mask, flag) \
2492 do {\
2493 (value) &= ~(mask);\
2494 (value) |= ((flag) << (mask##_SHIFT));\
2495 } while (0)
2496
2497 #define GET_FLAG(value, mask) \
2498 (((value) & (mask)) >> (mask##_SHIFT))
2499
2500 #define GET_FIELD(value, fname) \
2501 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2502
2503 enum {
2504 SWITCH_UPDATE,
2505 AFEX_UPDATE,
2506 };
2507
2508 #define NUM_MACS 8
2509
2510 void bnx2x_set_local_cmng(struct bnx2x *bp);
2511
2512 void bnx2x_update_mng_version(struct bnx2x *bp);
2513
2514 void bnx2x_update_mfw_dump(struct bnx2x *bp);
2515
2516 #define MCPR_SCRATCH_BASE(bp) \
2517 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
2518
2519 #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX))
2520
2521 void bnx2x_init_ptp(struct bnx2x *bp);
2522 int bnx2x_configure_ptp_filters(struct bnx2x *bp);
2523 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb);
2524 void bnx2x_register_phc(struct bnx2x *bp);
2525
2526 #define BNX2X_MAX_PHC_DRIFT 31000000
2527 #define BNX2X_PTP_TX_TIMEOUT
2528
2529
2530
2531
2532 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp);
2533
2534 #endif