This source file includes following definitions.
- bnx2x_exe_queue_init
- bnx2x_exe_queue_free_elem
- bnx2x_exe_queue_length
- bnx2x_exe_queue_add
- __bnx2x_exe_queue_reset_pending
- bnx2x_exe_queue_step
- bnx2x_exe_queue_empty
- bnx2x_exe_queue_alloc_elem
- bnx2x_raw_check_pending
- bnx2x_raw_clear_pending
- bnx2x_raw_set_pending
- bnx2x_state_wait
- bnx2x_raw_wait
- bnx2x_get_cam_offset_mac
- bnx2x_get_credit_mac
- bnx2x_get_cam_offset_vlan
- bnx2x_get_credit_vlan
- bnx2x_get_credit_vlan_mac
- bnx2x_put_cam_offset_mac
- bnx2x_put_credit_mac
- bnx2x_put_cam_offset_vlan
- bnx2x_put_credit_vlan
- bnx2x_put_credit_vlan_mac
- __bnx2x_vlan_mac_h_write_trylock
- __bnx2x_vlan_mac_h_exec_pending
- __bnx2x_vlan_mac_h_pend
- __bnx2x_vlan_mac_h_write_unlock
- __bnx2x_vlan_mac_h_read_lock
- bnx2x_vlan_mac_h_read_lock
- __bnx2x_vlan_mac_h_read_unlock
- bnx2x_vlan_mac_h_read_unlock
- bnx2x_get_n_elements
- bnx2x_check_mac_add
- bnx2x_check_vlan_add
- bnx2x_check_vlan_mac_add
- bnx2x_check_mac_del
- bnx2x_check_vlan_del
- bnx2x_check_vlan_mac_del
- bnx2x_check_move
- bnx2x_check_move_always_err
- bnx2x_vlan_mac_get_rx_tx_flag
- bnx2x_set_mac_in_nig
- bnx2x_vlan_mac_set_cmd_hdr_e2
- bnx2x_vlan_mac_set_rdata_hdr_e2
- bnx2x_set_one_mac_e2
- bnx2x_vlan_mac_set_rdata_hdr_e1x
- bnx2x_vlan_mac_set_cfg_entry_e1x
- bnx2x_vlan_mac_set_rdata_e1x
- bnx2x_set_one_mac_e1x
- bnx2x_set_one_vlan_e2
- bnx2x_set_one_vlan_mac_e2
- bnx2x_set_one_vlan_mac_e1h
- bnx2x_vlan_mac_restore
- bnx2x_exeq_get_mac
- bnx2x_exeq_get_vlan
- bnx2x_exeq_get_vlan_mac
- bnx2x_validate_vlan_mac_add
- bnx2x_validate_vlan_mac_del
- bnx2x_validate_vlan_mac_move
- bnx2x_validate_vlan_mac
- bnx2x_remove_vlan_mac
- bnx2x_wait_vlan_mac
- __bnx2x_vlan_mac_execute_step
- bnx2x_complete_vlan_mac
- bnx2x_optimize_vlan_mac
- bnx2x_vlan_mac_get_registry_elem
- bnx2x_execute_vlan_mac
- bnx2x_vlan_mac_push_new_cmd
- bnx2x_config_vlan_mac
- bnx2x_vlan_mac_del_all
- bnx2x_init_raw_obj
- bnx2x_init_vlan_mac_common
- bnx2x_init_mac_obj
- bnx2x_init_vlan_obj
- bnx2x_init_vlan_mac_obj
- __storm_memset_mac_filters
- bnx2x_set_rx_mode_e1x
- bnx2x_rx_mode_set_rdata_hdr_e2
- bnx2x_rx_mode_set_cmd_state_e2
- bnx2x_set_rx_mode_e2
- bnx2x_wait_rx_mode_comp_e2
- bnx2x_empty_rx_mode_wait
- bnx2x_config_rx_mode
- bnx2x_init_rx_mode_obj
- bnx2x_mcast_bin_from_mac
- bnx2x_mcast_wait
- bnx2x_free_groups
- bnx2x_mcast_enqueue_cmd
- bnx2x_mcast_get_next_bin
- bnx2x_mcast_clear_first_bin
- bnx2x_mcast_get_rx_tx_flag
- bnx2x_mcast_set_one_rule_e2
- bnx2x_mcast_handle_restore_cmd_e2
- bnx2x_mcast_hdl_pending_add_e2
- bnx2x_mcast_hdl_pending_del_e2
- bnx2x_mcast_hdl_pending_restore_e2
- bnx2x_mcast_hdl_pending_set_e2_convert
- bnx2x_mcast_hdl_pending_set_e2
- bnx2x_mcast_handle_pending_cmds_e2
- bnx2x_mcast_hdl_add
- bnx2x_mcast_hdl_del
- bnx2x_mcast_handle_current_cmd
- bnx2x_mcast_validate_e2
- bnx2x_mcast_revert_e2
- bnx2x_mcast_set_rdata_hdr_e2
- bnx2x_mcast_refresh_registry_e2
- bnx2x_mcast_setup_e2
- bnx2x_mcast_validate_e1h
- bnx2x_mcast_revert_e1h
- bnx2x_mcast_hdl_add_e1h
- bnx2x_mcast_hdl_restore_e1h
- bnx2x_mcast_setup_e1h
- bnx2x_mcast_validate_e1
- bnx2x_mcast_revert_e1
- bnx2x_mcast_set_one_rule_e1
- bnx2x_mcast_set_rdata_hdr_e1
- bnx2x_mcast_handle_restore_cmd_e1
- bnx2x_mcast_handle_pending_cmds_e1
- bnx2x_get_fw_mac_addr
- bnx2x_mcast_refresh_registry_e1
- bnx2x_mcast_setup_e1
- bnx2x_mcast_get_registry_size_exact
- bnx2x_mcast_get_registry_size_aprox
- bnx2x_mcast_set_registry_size_exact
- bnx2x_mcast_set_registry_size_aprox
- bnx2x_config_mcast
- bnx2x_mcast_clear_sched
- bnx2x_mcast_set_sched
- bnx2x_mcast_check_sched
- bnx2x_mcast_check_pending
- bnx2x_init_mcast_obj
- __atomic_add_ifless
- __atomic_dec_ifmoe
- bnx2x_credit_pool_get
- bnx2x_credit_pool_put
- bnx2x_credit_pool_check
- bnx2x_credit_pool_always_true
- bnx2x_credit_pool_get_entry
- bnx2x_credit_pool_put_entry
- bnx2x_credit_pool_put_entry_always_true
- bnx2x_credit_pool_get_entry_always_true
- bnx2x_init_credit_pool
- bnx2x_init_mac_credit_pool
- bnx2x_init_vlan_credit_pool
- bnx2x_debug_print_ind_table
- bnx2x_setup_rss
- bnx2x_get_rss_ind_table
- bnx2x_config_rss
- bnx2x_init_rss_config_obj
- bnx2x_queue_state_change
- bnx2x_queue_set_pending
- bnx2x_queue_wait_comp
- bnx2x_queue_comp_cmd
- bnx2x_q_fill_setup_data_e2
- bnx2x_q_fill_init_general_data
- bnx2x_q_fill_init_tx_data
- bnx2x_q_fill_init_pause_data
- bnx2x_q_fill_init_rx_data
- bnx2x_q_fill_setup_data_cmn
- bnx2x_q_fill_setup_tx_only
- bnx2x_q_init
- bnx2x_q_send_setup_e1x
- bnx2x_q_send_setup_e2
- bnx2x_q_send_setup_tx_only
- bnx2x_q_fill_update_data
- bnx2x_q_send_update
- bnx2x_q_send_deactivate
- bnx2x_q_send_activate
- bnx2x_q_fill_update_tpa_data
- bnx2x_q_send_update_tpa
- bnx2x_q_send_halt
- bnx2x_q_send_cfc_del
- bnx2x_q_send_terminate
- bnx2x_q_send_empty
- bnx2x_queue_send_cmd_cmn
- bnx2x_queue_send_cmd_e1x
- bnx2x_queue_send_cmd_e2
- bnx2x_queue_chk_transition
- bnx2x_init_queue_obj
- bnx2x_get_q_logical_state
- bnx2x_func_get_state
- bnx2x_func_wait_comp
- bnx2x_func_state_change_comp
- bnx2x_func_comp_cmd
- bnx2x_func_chk_transition
- bnx2x_func_init_func
- bnx2x_func_init_port
- bnx2x_func_init_cmn_chip
- bnx2x_func_init_cmn
- bnx2x_func_hw_init
- bnx2x_func_reset_func
- bnx2x_func_reset_port
- bnx2x_func_reset_cmn
- bnx2x_func_hw_reset
- bnx2x_func_send_start
- bnx2x_func_send_switch_update
- bnx2x_func_send_afex_update
- bnx2x_func_send_afex_viflists
- bnx2x_func_send_stop
- bnx2x_func_send_tx_stop
- bnx2x_func_send_tx_start
- bnx2x_func_send_set_timesync
- bnx2x_func_send_cmd
- bnx2x_init_func_obj
- bnx2x_func_state_change
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
24 #include <linux/module.h>
25 #include <linux/crc32.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/crc32c.h>
29 #include "bnx2x.h"
30 #include "bnx2x_cmn.h"
31 #include "bnx2x_sp.h"
32
33 #define BNX2X_MAX_EMUL_MULTI 16
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 static inline void bnx2x_exe_queue_init(struct bnx2x *bp,
49 struct bnx2x_exe_queue_obj *o,
50 int exe_len,
51 union bnx2x_qable_obj *owner,
52 exe_q_validate validate,
53 exe_q_remove remove,
54 exe_q_optimize optimize,
55 exe_q_execute exec,
56 exe_q_get get)
57 {
58 memset(o, 0, sizeof(*o));
59
60 INIT_LIST_HEAD(&o->exe_queue);
61 INIT_LIST_HEAD(&o->pending_comp);
62
63 spin_lock_init(&o->lock);
64
65 o->exe_chunk_len = exe_len;
66 o->owner = owner;
67
68
69 o->validate = validate;
70 o->remove = remove;
71 o->optimize = optimize;
72 o->execute = exec;
73 o->get = get;
74
75 DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n",
76 exe_len);
77 }
78
79 static inline void bnx2x_exe_queue_free_elem(struct bnx2x *bp,
80 struct bnx2x_exeq_elem *elem)
81 {
82 DP(BNX2X_MSG_SP, "Deleting an exe_queue element\n");
83 kfree(elem);
84 }
85
86 static inline int bnx2x_exe_queue_length(struct bnx2x_exe_queue_obj *o)
87 {
88 struct bnx2x_exeq_elem *elem;
89 int cnt = 0;
90
91 spin_lock_bh(&o->lock);
92
93 list_for_each_entry(elem, &o->exe_queue, link)
94 cnt++;
95
96 spin_unlock_bh(&o->lock);
97
98 return cnt;
99 }
100
101
102
103
104
105
106
107
108
109
110
111 static inline int bnx2x_exe_queue_add(struct bnx2x *bp,
112 struct bnx2x_exe_queue_obj *o,
113 struct bnx2x_exeq_elem *elem,
114 bool restore)
115 {
116 int rc;
117
118 spin_lock_bh(&o->lock);
119
120 if (!restore) {
121
122 rc = o->optimize(bp, o->owner, elem);
123 if (rc)
124 goto free_and_exit;
125
126
127 rc = o->validate(bp, o->owner, elem);
128 if (rc) {
129 DP(BNX2X_MSG_SP, "Preamble failed: %d\n", rc);
130 goto free_and_exit;
131 }
132 }
133
134
135 list_add_tail(&elem->link, &o->exe_queue);
136
137 spin_unlock_bh(&o->lock);
138
139 return 0;
140
141 free_and_exit:
142 bnx2x_exe_queue_free_elem(bp, elem);
143
144 spin_unlock_bh(&o->lock);
145
146 return rc;
147 }
148
149 static inline void __bnx2x_exe_queue_reset_pending(
150 struct bnx2x *bp,
151 struct bnx2x_exe_queue_obj *o)
152 {
153 struct bnx2x_exeq_elem *elem;
154
155 while (!list_empty(&o->pending_comp)) {
156 elem = list_first_entry(&o->pending_comp,
157 struct bnx2x_exeq_elem, link);
158
159 list_del(&elem->link);
160 bnx2x_exe_queue_free_elem(bp, elem);
161 }
162 }
163
164
165
166
167
168
169
170
171
172
173 static inline int bnx2x_exe_queue_step(struct bnx2x *bp,
174 struct bnx2x_exe_queue_obj *o,
175 unsigned long *ramrod_flags)
176 {
177 struct bnx2x_exeq_elem *elem, spacer;
178 int cur_len = 0, rc;
179
180 memset(&spacer, 0, sizeof(spacer));
181
182
183
184
185
186
187
188 if (!list_empty(&o->pending_comp)) {
189 if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {
190 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n");
191 __bnx2x_exe_queue_reset_pending(bp, o);
192 } else {
193 return 1;
194 }
195 }
196
197
198
199
200 while (!list_empty(&o->exe_queue)) {
201 elem = list_first_entry(&o->exe_queue, struct bnx2x_exeq_elem,
202 link);
203 WARN_ON(!elem->cmd_len);
204
205 if (cur_len + elem->cmd_len <= o->exe_chunk_len) {
206 cur_len += elem->cmd_len;
207
208
209
210
211 list_add_tail(&spacer.link, &o->pending_comp);
212 mb();
213 list_move_tail(&elem->link, &o->pending_comp);
214 list_del(&spacer.link);
215 } else
216 break;
217 }
218
219
220 if (!cur_len)
221 return 0;
222
223 rc = o->execute(bp, o->owner, &o->pending_comp, ramrod_flags);
224 if (rc < 0)
225
226
227
228 list_splice_init(&o->pending_comp, &o->exe_queue);
229 else if (!rc)
230
231
232
233 __bnx2x_exe_queue_reset_pending(bp, o);
234
235 return rc;
236 }
237
238 static inline bool bnx2x_exe_queue_empty(struct bnx2x_exe_queue_obj *o)
239 {
240 bool empty = list_empty(&o->exe_queue);
241
242
243 mb();
244
245 return empty && list_empty(&o->pending_comp);
246 }
247
248 static inline struct bnx2x_exeq_elem *bnx2x_exe_queue_alloc_elem(
249 struct bnx2x *bp)
250 {
251 DP(BNX2X_MSG_SP, "Allocating a new exe_queue element\n");
252 return kzalloc(sizeof(struct bnx2x_exeq_elem), GFP_ATOMIC);
253 }
254
255
256 static bool bnx2x_raw_check_pending(struct bnx2x_raw_obj *o)
257 {
258 return !!test_bit(o->state, o->pstate);
259 }
260
261 static void bnx2x_raw_clear_pending(struct bnx2x_raw_obj *o)
262 {
263 smp_mb__before_atomic();
264 clear_bit(o->state, o->pstate);
265 smp_mb__after_atomic();
266 }
267
268 static void bnx2x_raw_set_pending(struct bnx2x_raw_obj *o)
269 {
270 smp_mb__before_atomic();
271 set_bit(o->state, o->pstate);
272 smp_mb__after_atomic();
273 }
274
275
276
277
278
279
280
281
282
283 static inline int bnx2x_state_wait(struct bnx2x *bp, int state,
284 unsigned long *pstate)
285 {
286
287 int cnt = 5000;
288
289 if (CHIP_REV_IS_EMUL(bp))
290 cnt *= 20;
291
292 DP(BNX2X_MSG_SP, "waiting for state to become %d\n", state);
293
294 might_sleep();
295 while (cnt--) {
296 if (!test_bit(state, pstate)) {
297 #ifdef BNX2X_STOP_ON_ERROR
298 DP(BNX2X_MSG_SP, "exit (cnt %d)\n", 5000 - cnt);
299 #endif
300 return 0;
301 }
302
303 usleep_range(1000, 2000);
304
305 if (bp->panic)
306 return -EIO;
307 }
308
309
310 BNX2X_ERR("timeout waiting for state %d\n", state);
311 #ifdef BNX2X_STOP_ON_ERROR
312 bnx2x_panic();
313 #endif
314
315 return -EBUSY;
316 }
317
318 static int bnx2x_raw_wait(struct bnx2x *bp, struct bnx2x_raw_obj *raw)
319 {
320 return bnx2x_state_wait(bp, raw->state, raw->pstate);
321 }
322
323
324
325 static bool bnx2x_get_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int *offset)
326 {
327 struct bnx2x_credit_pool_obj *mp = o->macs_pool;
328
329 WARN_ON(!mp);
330
331 return mp->get_entry(mp, offset);
332 }
333
334 static bool bnx2x_get_credit_mac(struct bnx2x_vlan_mac_obj *o)
335 {
336 struct bnx2x_credit_pool_obj *mp = o->macs_pool;
337
338 WARN_ON(!mp);
339
340 return mp->get(mp, 1);
341 }
342
343 static bool bnx2x_get_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int *offset)
344 {
345 struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
346
347 WARN_ON(!vp);
348
349 return vp->get_entry(vp, offset);
350 }
351
352 static bool bnx2x_get_credit_vlan(struct bnx2x_vlan_mac_obj *o)
353 {
354 struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
355
356 WARN_ON(!vp);
357
358 return vp->get(vp, 1);
359 }
360
361 static bool bnx2x_get_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o)
362 {
363 struct bnx2x_credit_pool_obj *mp = o->macs_pool;
364 struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
365
366 if (!mp->get(mp, 1))
367 return false;
368
369 if (!vp->get(vp, 1)) {
370 mp->put(mp, 1);
371 return false;
372 }
373
374 return true;
375 }
376
377 static bool bnx2x_put_cam_offset_mac(struct bnx2x_vlan_mac_obj *o, int offset)
378 {
379 struct bnx2x_credit_pool_obj *mp = o->macs_pool;
380
381 return mp->put_entry(mp, offset);
382 }
383
384 static bool bnx2x_put_credit_mac(struct bnx2x_vlan_mac_obj *o)
385 {
386 struct bnx2x_credit_pool_obj *mp = o->macs_pool;
387
388 return mp->put(mp, 1);
389 }
390
391 static bool bnx2x_put_cam_offset_vlan(struct bnx2x_vlan_mac_obj *o, int offset)
392 {
393 struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
394
395 return vp->put_entry(vp, offset);
396 }
397
398 static bool bnx2x_put_credit_vlan(struct bnx2x_vlan_mac_obj *o)
399 {
400 struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
401
402 return vp->put(vp, 1);
403 }
404
405 static bool bnx2x_put_credit_vlan_mac(struct bnx2x_vlan_mac_obj *o)
406 {
407 struct bnx2x_credit_pool_obj *mp = o->macs_pool;
408 struct bnx2x_credit_pool_obj *vp = o->vlans_pool;
409
410 if (!mp->put(mp, 1))
411 return false;
412
413 if (!vp->put(vp, 1)) {
414 mp->get(mp, 1);
415 return false;
416 }
417
418 return true;
419 }
420
421
422
423
424
425
426
427
428
429
430 static int __bnx2x_vlan_mac_h_write_trylock(struct bnx2x *bp,
431 struct bnx2x_vlan_mac_obj *o)
432 {
433 if (o->head_reader) {
434 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - There are readers; Busy\n");
435 return -EBUSY;
436 }
437
438 DP(BNX2X_MSG_SP, "vlan_mac_lock writer - Taken\n");
439 return 0;
440 }
441
442
443
444
445
446
447
448
449
450
451 static void __bnx2x_vlan_mac_h_exec_pending(struct bnx2x *bp,
452 struct bnx2x_vlan_mac_obj *o)
453 {
454 int rc;
455 unsigned long ramrod_flags = o->saved_ramrod_flags;
456
457 DP(BNX2X_MSG_SP, "vlan_mac_lock execute pending command with ramrod flags %lu\n",
458 ramrod_flags);
459 o->head_exe_request = false;
460 o->saved_ramrod_flags = 0;
461 rc = bnx2x_exe_queue_step(bp, &o->exe_queue, &ramrod_flags);
462 if ((rc != 0) && (rc != 1)) {
463 BNX2X_ERR("execution of pending commands failed with rc %d\n",
464 rc);
465 #ifdef BNX2X_STOP_ON_ERROR
466 bnx2x_panic();
467 #endif
468 }
469 }
470
471
472
473
474
475
476
477
478
479
480 static void __bnx2x_vlan_mac_h_pend(struct bnx2x *bp,
481 struct bnx2x_vlan_mac_obj *o,
482 unsigned long ramrod_flags)
483 {
484 o->head_exe_request = true;
485 o->saved_ramrod_flags = ramrod_flags;
486 DP(BNX2X_MSG_SP, "Placing pending execution with ramrod flags %lu\n",
487 ramrod_flags);
488 }
489
490
491
492
493
494
495
496
497
498
499
500 static void __bnx2x_vlan_mac_h_write_unlock(struct bnx2x *bp,
501 struct bnx2x_vlan_mac_obj *o)
502 {
503
504
505
506 while (o->head_exe_request) {
507 DP(BNX2X_MSG_SP, "vlan_mac_lock - writer release encountered a pending request\n");
508 __bnx2x_vlan_mac_h_exec_pending(bp, o);
509 }
510 }
511
512
513
514
515
516
517
518
519
520
521
522 static int __bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp,
523 struct bnx2x_vlan_mac_obj *o)
524 {
525
526 o->head_reader++;
527 DP(BNX2X_MSG_SP, "vlan_mac_lock - locked reader - number %d\n",
528 o->head_reader);
529
530 return 0;
531 }
532
533
534
535
536
537
538
539
540
541 int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp,
542 struct bnx2x_vlan_mac_obj *o)
543 {
544 int rc;
545
546 spin_lock_bh(&o->exe_queue.lock);
547 rc = __bnx2x_vlan_mac_h_read_lock(bp, o);
548 spin_unlock_bh(&o->exe_queue.lock);
549
550 return rc;
551 }
552
553
554
555
556
557
558
559
560
561
562
563 static void __bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp,
564 struct bnx2x_vlan_mac_obj *o)
565 {
566 if (!o->head_reader) {
567 BNX2X_ERR("Need to release vlan mac reader lock, but lock isn't taken\n");
568 #ifdef BNX2X_STOP_ON_ERROR
569 bnx2x_panic();
570 #endif
571 } else {
572 o->head_reader--;
573 DP(BNX2X_MSG_SP, "vlan_mac_lock - decreased readers to %d\n",
574 o->head_reader);
575 }
576
577
578
579
580 if (!o->head_reader && o->head_exe_request) {
581 DP(BNX2X_MSG_SP, "vlan_mac_lock - reader release encountered a pending request\n");
582
583
584 __bnx2x_vlan_mac_h_write_unlock(bp, o);
585 }
586 }
587
588
589
590
591
592
593
594
595
596
597
598 void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp,
599 struct bnx2x_vlan_mac_obj *o)
600 {
601 spin_lock_bh(&o->exe_queue.lock);
602 __bnx2x_vlan_mac_h_read_unlock(bp, o);
603 spin_unlock_bh(&o->exe_queue.lock);
604 }
605
606 static int bnx2x_get_n_elements(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
607 int n, u8 *base, u8 stride, u8 size)
608 {
609 struct bnx2x_vlan_mac_registry_elem *pos;
610 u8 *next = base;
611 int counter = 0;
612 int read_lock;
613
614 DP(BNX2X_MSG_SP, "get_n_elements - taking vlan_mac_lock (reader)\n");
615 read_lock = bnx2x_vlan_mac_h_read_lock(bp, o);
616 if (read_lock != 0)
617 BNX2X_ERR("get_n_elements failed to get vlan mac reader lock; Access without lock\n");
618
619
620 list_for_each_entry(pos, &o->head, link) {
621 if (counter < n) {
622 memcpy(next, &pos->u, size);
623 counter++;
624 DP(BNX2X_MSG_SP, "copied element number %d to address %p element was:\n",
625 counter, next);
626 next += stride + size;
627 }
628 }
629
630 if (read_lock == 0) {
631 DP(BNX2X_MSG_SP, "get_n_elements - releasing vlan_mac_lock (reader)\n");
632 bnx2x_vlan_mac_h_read_unlock(bp, o);
633 }
634
635 return counter * ETH_ALEN;
636 }
637
638
639 static int bnx2x_check_mac_add(struct bnx2x *bp,
640 struct bnx2x_vlan_mac_obj *o,
641 union bnx2x_classification_ramrod_data *data)
642 {
643 struct bnx2x_vlan_mac_registry_elem *pos;
644
645 DP(BNX2X_MSG_SP, "Checking MAC %pM for ADD command\n", data->mac.mac);
646
647 if (!is_valid_ether_addr(data->mac.mac))
648 return -EINVAL;
649
650
651 list_for_each_entry(pos, &o->head, link)
652 if (ether_addr_equal(data->mac.mac, pos->u.mac.mac) &&
653 (data->mac.is_inner_mac == pos->u.mac.is_inner_mac))
654 return -EEXIST;
655
656 return 0;
657 }
658
659 static int bnx2x_check_vlan_add(struct bnx2x *bp,
660 struct bnx2x_vlan_mac_obj *o,
661 union bnx2x_classification_ramrod_data *data)
662 {
663 struct bnx2x_vlan_mac_registry_elem *pos;
664
665 DP(BNX2X_MSG_SP, "Checking VLAN %d for ADD command\n", data->vlan.vlan);
666
667 list_for_each_entry(pos, &o->head, link)
668 if (data->vlan.vlan == pos->u.vlan.vlan)
669 return -EEXIST;
670
671 return 0;
672 }
673
674 static int bnx2x_check_vlan_mac_add(struct bnx2x *bp,
675 struct bnx2x_vlan_mac_obj *o,
676 union bnx2x_classification_ramrod_data *data)
677 {
678 struct bnx2x_vlan_mac_registry_elem *pos;
679
680 DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for ADD command\n",
681 data->vlan_mac.mac, data->vlan_mac.vlan);
682
683 list_for_each_entry(pos, &o->head, link)
684 if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) &&
685 (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac,
686 ETH_ALEN)) &&
687 (data->vlan_mac.is_inner_mac ==
688 pos->u.vlan_mac.is_inner_mac))
689 return -EEXIST;
690
691 return 0;
692 }
693
694
695 static struct bnx2x_vlan_mac_registry_elem *
696 bnx2x_check_mac_del(struct bnx2x *bp,
697 struct bnx2x_vlan_mac_obj *o,
698 union bnx2x_classification_ramrod_data *data)
699 {
700 struct bnx2x_vlan_mac_registry_elem *pos;
701
702 DP(BNX2X_MSG_SP, "Checking MAC %pM for DEL command\n", data->mac.mac);
703
704 list_for_each_entry(pos, &o->head, link)
705 if (ether_addr_equal(data->mac.mac, pos->u.mac.mac) &&
706 (data->mac.is_inner_mac == pos->u.mac.is_inner_mac))
707 return pos;
708
709 return NULL;
710 }
711
712 static struct bnx2x_vlan_mac_registry_elem *
713 bnx2x_check_vlan_del(struct bnx2x *bp,
714 struct bnx2x_vlan_mac_obj *o,
715 union bnx2x_classification_ramrod_data *data)
716 {
717 struct bnx2x_vlan_mac_registry_elem *pos;
718
719 DP(BNX2X_MSG_SP, "Checking VLAN %d for DEL command\n", data->vlan.vlan);
720
721 list_for_each_entry(pos, &o->head, link)
722 if (data->vlan.vlan == pos->u.vlan.vlan)
723 return pos;
724
725 return NULL;
726 }
727
728 static struct bnx2x_vlan_mac_registry_elem *
729 bnx2x_check_vlan_mac_del(struct bnx2x *bp,
730 struct bnx2x_vlan_mac_obj *o,
731 union bnx2x_classification_ramrod_data *data)
732 {
733 struct bnx2x_vlan_mac_registry_elem *pos;
734
735 DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for DEL command\n",
736 data->vlan_mac.mac, data->vlan_mac.vlan);
737
738 list_for_each_entry(pos, &o->head, link)
739 if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) &&
740 (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac,
741 ETH_ALEN)) &&
742 (data->vlan_mac.is_inner_mac ==
743 pos->u.vlan_mac.is_inner_mac))
744 return pos;
745
746 return NULL;
747 }
748
749
750 static bool bnx2x_check_move(struct bnx2x *bp,
751 struct bnx2x_vlan_mac_obj *src_o,
752 struct bnx2x_vlan_mac_obj *dst_o,
753 union bnx2x_classification_ramrod_data *data)
754 {
755 struct bnx2x_vlan_mac_registry_elem *pos;
756 int rc;
757
758
759
760
761 pos = src_o->check_del(bp, src_o, data);
762
763
764 rc = dst_o->check_add(bp, dst_o, data);
765
766
767
768
769 if (rc || !pos)
770 return false;
771
772 return true;
773 }
774
775 static bool bnx2x_check_move_always_err(
776 struct bnx2x *bp,
777 struct bnx2x_vlan_mac_obj *src_o,
778 struct bnx2x_vlan_mac_obj *dst_o,
779 union bnx2x_classification_ramrod_data *data)
780 {
781 return false;
782 }
783
784 static inline u8 bnx2x_vlan_mac_get_rx_tx_flag(struct bnx2x_vlan_mac_obj *o)
785 {
786 struct bnx2x_raw_obj *raw = &o->raw;
787 u8 rx_tx_flag = 0;
788
789 if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) ||
790 (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
791 rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_TX_CMD;
792
793 if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) ||
794 (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
795 rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_RX_CMD;
796
797 return rx_tx_flag;
798 }
799
800 static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
801 bool add, unsigned char *dev_addr, int index)
802 {
803 u32 wb_data[2];
804 u32 reg_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
805 NIG_REG_LLH0_FUNC_MEM;
806
807 if (!IS_MF_SI(bp) && !IS_MF_AFEX(bp))
808 return;
809
810 if (index > BNX2X_LLH_CAM_MAX_PF_LINE)
811 return;
812
813 DP(BNX2X_MSG_SP, "Going to %s LLH configuration at entry %d\n",
814 (add ? "ADD" : "DELETE"), index);
815
816 if (add) {
817
818 reg_offset += 8*index;
819
820 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
821 (dev_addr[4] << 8) | dev_addr[5]);
822 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
823
824 REG_WR_DMAE(bp, reg_offset, wb_data, 2);
825 }
826
827 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
828 NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4*index, add);
829 }
830
831
832
833
834
835
836
837
838
839
840
841 static inline void bnx2x_vlan_mac_set_cmd_hdr_e2(struct bnx2x *bp,
842 struct bnx2x_vlan_mac_obj *o, bool add, int opcode,
843 struct eth_classify_cmd_header *hdr)
844 {
845 struct bnx2x_raw_obj *raw = &o->raw;
846
847 hdr->client_id = raw->cl_id;
848 hdr->func_id = raw->func_id;
849
850
851 hdr->cmd_general_data |=
852 bnx2x_vlan_mac_get_rx_tx_flag(o);
853
854 if (add)
855 hdr->cmd_general_data |= ETH_CLASSIFY_CMD_HEADER_IS_ADD;
856
857 hdr->cmd_general_data |=
858 (opcode << ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT);
859 }
860
861
862
863
864
865
866
867
868
869
870
871
872 static inline void bnx2x_vlan_mac_set_rdata_hdr_e2(u32 cid, int type,
873 struct eth_classify_header *hdr, int rule_cnt)
874 {
875 hdr->echo = cpu_to_le32((cid & BNX2X_SWCID_MASK) |
876 (type << BNX2X_SWCID_SHIFT));
877 hdr->rule_cnt = (u8)rule_cnt;
878 }
879
880
881 static void bnx2x_set_one_mac_e2(struct bnx2x *bp,
882 struct bnx2x_vlan_mac_obj *o,
883 struct bnx2x_exeq_elem *elem, int rule_idx,
884 int cam_offset)
885 {
886 struct bnx2x_raw_obj *raw = &o->raw;
887 struct eth_classify_rules_ramrod_data *data =
888 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
889 int rule_cnt = rule_idx + 1, cmd = elem->cmd_data.vlan_mac.cmd;
890 union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
891 bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false;
892 unsigned long *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags;
893 u8 *mac = elem->cmd_data.vlan_mac.u.mac.mac;
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912 if (cmd != BNX2X_VLAN_MAC_MOVE) {
913 if (test_bit(BNX2X_ISCSI_ETH_MAC, vlan_mac_flags))
914 bnx2x_set_mac_in_nig(bp, add, mac,
915 BNX2X_LLH_CAM_ISCSI_ETH_LINE);
916 else if (test_bit(BNX2X_ETH_MAC, vlan_mac_flags))
917 bnx2x_set_mac_in_nig(bp, add, mac,
918 BNX2X_LLH_CAM_ETH_LINE);
919 }
920
921
922 if (rule_idx == 0)
923 memset(data, 0, sizeof(*data));
924
925
926 bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_MAC,
927 &rule_entry->mac.header);
928
929 DP(BNX2X_MSG_SP, "About to %s MAC %pM for Queue %d\n",
930 (add ? "add" : "delete"), mac, raw->cl_id);
931
932
933 bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb,
934 &rule_entry->mac.mac_mid,
935 &rule_entry->mac.mac_lsb, mac);
936 rule_entry->mac.inner_mac =
937 cpu_to_le16(elem->cmd_data.vlan_mac.u.mac.is_inner_mac);
938
939
940 if (cmd == BNX2X_VLAN_MAC_MOVE) {
941 rule_entry++;
942 rule_cnt++;
943
944
945 bnx2x_vlan_mac_set_cmd_hdr_e2(bp,
946 elem->cmd_data.vlan_mac.target_obj,
947 true, CLASSIFY_RULE_OPCODE_MAC,
948 &rule_entry->mac.header);
949
950
951 bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb,
952 &rule_entry->mac.mac_mid,
953 &rule_entry->mac.mac_lsb, mac);
954 rule_entry->mac.inner_mac =
955 cpu_to_le16(elem->cmd_data.vlan_mac.
956 u.mac.is_inner_mac);
957 }
958
959
960
961
962 bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
963 rule_cnt);
964 }
965
966
967
968
969
970
971
972
973
974
975
976
977 static inline void bnx2x_vlan_mac_set_rdata_hdr_e1x(struct bnx2x *bp,
978 struct bnx2x_vlan_mac_obj *o, int type, int cam_offset,
979 struct mac_configuration_hdr *hdr)
980 {
981 struct bnx2x_raw_obj *r = &o->raw;
982
983 hdr->length = 1;
984 hdr->offset = (u8)cam_offset;
985 hdr->client_id = cpu_to_le16(0xff);
986 hdr->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
987 (type << BNX2X_SWCID_SHIFT));
988 }
989
990 static inline void bnx2x_vlan_mac_set_cfg_entry_e1x(struct bnx2x *bp,
991 struct bnx2x_vlan_mac_obj *o, bool add, int opcode, u8 *mac,
992 u16 vlan_id, struct mac_configuration_entry *cfg_entry)
993 {
994 struct bnx2x_raw_obj *r = &o->raw;
995 u32 cl_bit_vec = (1 << r->cl_id);
996
997 cfg_entry->clients_bit_vector = cpu_to_le32(cl_bit_vec);
998 cfg_entry->pf_id = r->func_id;
999 cfg_entry->vlan_id = cpu_to_le16(vlan_id);
1000
1001 if (add) {
1002 SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
1003 T_ETH_MAC_COMMAND_SET);
1004 SET_FLAG(cfg_entry->flags,
1005 MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE, opcode);
1006
1007
1008 bnx2x_set_fw_mac_addr(&cfg_entry->msb_mac_addr,
1009 &cfg_entry->middle_mac_addr,
1010 &cfg_entry->lsb_mac_addr, mac);
1011 } else
1012 SET_FLAG(cfg_entry->flags, MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
1013 T_ETH_MAC_COMMAND_INVALIDATE);
1014 }
1015
1016 static inline void bnx2x_vlan_mac_set_rdata_e1x(struct bnx2x *bp,
1017 struct bnx2x_vlan_mac_obj *o, int type, int cam_offset, bool add,
1018 u8 *mac, u16 vlan_id, int opcode, struct mac_configuration_cmd *config)
1019 {
1020 struct mac_configuration_entry *cfg_entry = &config->config_table[0];
1021 struct bnx2x_raw_obj *raw = &o->raw;
1022
1023 bnx2x_vlan_mac_set_rdata_hdr_e1x(bp, o, type, cam_offset,
1024 &config->hdr);
1025 bnx2x_vlan_mac_set_cfg_entry_e1x(bp, o, add, opcode, mac, vlan_id,
1026 cfg_entry);
1027
1028 DP(BNX2X_MSG_SP, "%s MAC %pM CLID %d CAM offset %d\n",
1029 (add ? "setting" : "clearing"),
1030 mac, raw->cl_id, cam_offset);
1031 }
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042 static void bnx2x_set_one_mac_e1x(struct bnx2x *bp,
1043 struct bnx2x_vlan_mac_obj *o,
1044 struct bnx2x_exeq_elem *elem, int rule_idx,
1045 int cam_offset)
1046 {
1047 struct bnx2x_raw_obj *raw = &o->raw;
1048 struct mac_configuration_cmd *config =
1049 (struct mac_configuration_cmd *)(raw->rdata);
1050
1051
1052
1053 bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ?
1054 true : false;
1055
1056
1057 memset(config, 0, sizeof(*config));
1058
1059 bnx2x_vlan_mac_set_rdata_e1x(bp, o, raw->state,
1060 cam_offset, add,
1061 elem->cmd_data.vlan_mac.u.mac.mac, 0,
1062 ETH_VLAN_FILTER_ANY_VLAN, config);
1063 }
1064
1065 static void bnx2x_set_one_vlan_e2(struct bnx2x *bp,
1066 struct bnx2x_vlan_mac_obj *o,
1067 struct bnx2x_exeq_elem *elem, int rule_idx,
1068 int cam_offset)
1069 {
1070 struct bnx2x_raw_obj *raw = &o->raw;
1071 struct eth_classify_rules_ramrod_data *data =
1072 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
1073 int rule_cnt = rule_idx + 1;
1074 union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
1075 enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
1076 bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false;
1077 u16 vlan = elem->cmd_data.vlan_mac.u.vlan.vlan;
1078
1079
1080 if (rule_idx == 0)
1081 memset(data, 0, sizeof(*data));
1082
1083
1084 bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_VLAN,
1085 &rule_entry->vlan.header);
1086
1087 DP(BNX2X_MSG_SP, "About to %s VLAN %d\n", (add ? "add" : "delete"),
1088 vlan);
1089
1090
1091 rule_entry->vlan.vlan = cpu_to_le16(vlan);
1092
1093
1094 if (cmd == BNX2X_VLAN_MAC_MOVE) {
1095 rule_entry++;
1096 rule_cnt++;
1097
1098
1099 bnx2x_vlan_mac_set_cmd_hdr_e2(bp,
1100 elem->cmd_data.vlan_mac.target_obj,
1101 true, CLASSIFY_RULE_OPCODE_VLAN,
1102 &rule_entry->vlan.header);
1103
1104
1105 rule_entry->vlan.vlan = cpu_to_le16(vlan);
1106 }
1107
1108
1109
1110
1111 bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
1112 rule_cnt);
1113 }
1114
1115 static void bnx2x_set_one_vlan_mac_e2(struct bnx2x *bp,
1116 struct bnx2x_vlan_mac_obj *o,
1117 struct bnx2x_exeq_elem *elem,
1118 int rule_idx, int cam_offset)
1119 {
1120 struct bnx2x_raw_obj *raw = &o->raw;
1121 struct eth_classify_rules_ramrod_data *data =
1122 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
1123 int rule_cnt = rule_idx + 1;
1124 union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
1125 enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
1126 bool add = (cmd == BNX2X_VLAN_MAC_ADD) ? true : false;
1127 u16 vlan = elem->cmd_data.vlan_mac.u.vlan_mac.vlan;
1128 u8 *mac = elem->cmd_data.vlan_mac.u.vlan_mac.mac;
1129 u16 inner_mac;
1130
1131
1132 if (rule_idx == 0)
1133 memset(data, 0, sizeof(*data));
1134
1135
1136 bnx2x_vlan_mac_set_cmd_hdr_e2(bp, o, add, CLASSIFY_RULE_OPCODE_PAIR,
1137 &rule_entry->pair.header);
1138
1139
1140 rule_entry->pair.vlan = cpu_to_le16(vlan);
1141 bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb,
1142 &rule_entry->pair.mac_mid,
1143 &rule_entry->pair.mac_lsb, mac);
1144 inner_mac = elem->cmd_data.vlan_mac.u.vlan_mac.is_inner_mac;
1145 rule_entry->pair.inner_mac = cpu_to_le16(inner_mac);
1146
1147 if (cmd == BNX2X_VLAN_MAC_MOVE) {
1148 struct bnx2x_vlan_mac_obj *target_obj;
1149
1150 rule_entry++;
1151 rule_cnt++;
1152
1153
1154 target_obj = elem->cmd_data.vlan_mac.target_obj;
1155 bnx2x_vlan_mac_set_cmd_hdr_e2(bp, target_obj,
1156 true, CLASSIFY_RULE_OPCODE_PAIR,
1157 &rule_entry->pair.header);
1158
1159
1160 rule_entry->pair.vlan = cpu_to_le16(vlan);
1161 bnx2x_set_fw_mac_addr(&rule_entry->pair.mac_msb,
1162 &rule_entry->pair.mac_mid,
1163 &rule_entry->pair.mac_lsb, mac);
1164 rule_entry->pair.inner_mac = cpu_to_le16(inner_mac);
1165 }
1166
1167
1168 bnx2x_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
1169 rule_cnt);
1170 }
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181 static void bnx2x_set_one_vlan_mac_e1h(struct bnx2x *bp,
1182 struct bnx2x_vlan_mac_obj *o,
1183 struct bnx2x_exeq_elem *elem,
1184 int rule_idx, int cam_offset)
1185 {
1186 struct bnx2x_raw_obj *raw = &o->raw;
1187 struct mac_configuration_cmd *config =
1188 (struct mac_configuration_cmd *)(raw->rdata);
1189
1190
1191
1192 bool add = (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ?
1193 true : false;
1194
1195
1196 memset(config, 0, sizeof(*config));
1197
1198 bnx2x_vlan_mac_set_rdata_e1x(bp, o, BNX2X_FILTER_VLAN_MAC_PENDING,
1199 cam_offset, add,
1200 elem->cmd_data.vlan_mac.u.vlan_mac.mac,
1201 elem->cmd_data.vlan_mac.u.vlan_mac.vlan,
1202 ETH_VLAN_FILTER_CLASSIFY, config);
1203 }
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224 static int bnx2x_vlan_mac_restore(struct bnx2x *bp,
1225 struct bnx2x_vlan_mac_ramrod_params *p,
1226 struct bnx2x_vlan_mac_registry_elem **ppos)
1227 {
1228 struct bnx2x_vlan_mac_registry_elem *pos;
1229 struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj;
1230
1231
1232 if (list_empty(&o->head)) {
1233 *ppos = NULL;
1234 return 0;
1235 }
1236
1237
1238 if (*ppos == NULL)
1239 *ppos = list_first_entry(&o->head,
1240 struct bnx2x_vlan_mac_registry_elem,
1241 link);
1242 else
1243 *ppos = list_next_entry(*ppos, link);
1244
1245 pos = *ppos;
1246
1247
1248 if (list_is_last(&pos->link, &o->head))
1249 *ppos = NULL;
1250
1251
1252 memcpy(&p->user_req.u, &pos->u, sizeof(pos->u));
1253
1254
1255 p->user_req.cmd = BNX2X_VLAN_MAC_ADD;
1256
1257
1258 p->user_req.vlan_mac_flags = pos->vlan_mac_flags;
1259
1260
1261 __set_bit(RAMROD_RESTORE, &p->ramrod_flags);
1262
1263 return bnx2x_config_vlan_mac(bp, p);
1264 }
1265
1266
1267
1268
1269
1270 static struct bnx2x_exeq_elem *bnx2x_exeq_get_mac(
1271 struct bnx2x_exe_queue_obj *o,
1272 struct bnx2x_exeq_elem *elem)
1273 {
1274 struct bnx2x_exeq_elem *pos;
1275 struct bnx2x_mac_ramrod_data *data = &elem->cmd_data.vlan_mac.u.mac;
1276
1277
1278 list_for_each_entry(pos, &o->exe_queue, link)
1279 if (!memcmp(&pos->cmd_data.vlan_mac.u.mac, data,
1280 sizeof(*data)) &&
1281 (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))
1282 return pos;
1283
1284 return NULL;
1285 }
1286
1287 static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan(
1288 struct bnx2x_exe_queue_obj *o,
1289 struct bnx2x_exeq_elem *elem)
1290 {
1291 struct bnx2x_exeq_elem *pos;
1292 struct bnx2x_vlan_ramrod_data *data = &elem->cmd_data.vlan_mac.u.vlan;
1293
1294
1295 list_for_each_entry(pos, &o->exe_queue, link)
1296 if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan, data,
1297 sizeof(*data)) &&
1298 (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))
1299 return pos;
1300
1301 return NULL;
1302 }
1303
1304 static struct bnx2x_exeq_elem *bnx2x_exeq_get_vlan_mac(
1305 struct bnx2x_exe_queue_obj *o,
1306 struct bnx2x_exeq_elem *elem)
1307 {
1308 struct bnx2x_exeq_elem *pos;
1309 struct bnx2x_vlan_mac_ramrod_data *data =
1310 &elem->cmd_data.vlan_mac.u.vlan_mac;
1311
1312
1313 list_for_each_entry(pos, &o->exe_queue, link)
1314 if (!memcmp(&pos->cmd_data.vlan_mac.u.vlan_mac, data,
1315 sizeof(*data)) &&
1316 (pos->cmd_data.vlan_mac.cmd ==
1317 elem->cmd_data.vlan_mac.cmd))
1318 return pos;
1319
1320 return NULL;
1321 }
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336 static inline int bnx2x_validate_vlan_mac_add(struct bnx2x *bp,
1337 union bnx2x_qable_obj *qo,
1338 struct bnx2x_exeq_elem *elem)
1339 {
1340 struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac;
1341 struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1342 int rc;
1343
1344
1345 rc = o->check_add(bp, o, &elem->cmd_data.vlan_mac.u);
1346 if (rc) {
1347 DP(BNX2X_MSG_SP, "ADD command is not allowed considering current registry state.\n");
1348 return rc;
1349 }
1350
1351
1352
1353
1354 if (exeq->get(exeq, elem)) {
1355 DP(BNX2X_MSG_SP, "There is a pending ADD command already\n");
1356 return -EEXIST;
1357 }
1358
1359
1360
1361
1362
1363
1364 if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1365 &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1366 o->get_credit(o)))
1367 return -EINVAL;
1368
1369 return 0;
1370 }
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384 static inline int bnx2x_validate_vlan_mac_del(struct bnx2x *bp,
1385 union bnx2x_qable_obj *qo,
1386 struct bnx2x_exeq_elem *elem)
1387 {
1388 struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac;
1389 struct bnx2x_vlan_mac_registry_elem *pos;
1390 struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1391 struct bnx2x_exeq_elem query_elem;
1392
1393
1394
1395
1396 pos = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u);
1397 if (!pos) {
1398 DP(BNX2X_MSG_SP, "DEL command is not allowed considering current registry state\n");
1399 return -EEXIST;
1400 }
1401
1402
1403
1404
1405 memcpy(&query_elem, elem, sizeof(query_elem));
1406
1407
1408 query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_MOVE;
1409 if (exeq->get(exeq, &query_elem)) {
1410 BNX2X_ERR("There is a pending MOVE command already\n");
1411 return -EINVAL;
1412 }
1413
1414
1415 if (exeq->get(exeq, elem)) {
1416 DP(BNX2X_MSG_SP, "There is a pending DEL command already\n");
1417 return -EEXIST;
1418 }
1419
1420
1421 if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1422 &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1423 o->put_credit(o))) {
1424 BNX2X_ERR("Failed to return a credit\n");
1425 return -EINVAL;
1426 }
1427
1428 return 0;
1429 }
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443 static inline int bnx2x_validate_vlan_mac_move(struct bnx2x *bp,
1444 union bnx2x_qable_obj *qo,
1445 struct bnx2x_exeq_elem *elem)
1446 {
1447 struct bnx2x_vlan_mac_obj *src_o = &qo->vlan_mac;
1448 struct bnx2x_vlan_mac_obj *dest_o = elem->cmd_data.vlan_mac.target_obj;
1449 struct bnx2x_exeq_elem query_elem;
1450 struct bnx2x_exe_queue_obj *src_exeq = &src_o->exe_queue;
1451 struct bnx2x_exe_queue_obj *dest_exeq = &dest_o->exe_queue;
1452
1453
1454
1455
1456 if (!src_o->check_move(bp, src_o, dest_o,
1457 &elem->cmd_data.vlan_mac.u)) {
1458 DP(BNX2X_MSG_SP, "MOVE command is not allowed considering current registry state\n");
1459 return -EINVAL;
1460 }
1461
1462
1463
1464
1465
1466 memcpy(&query_elem, elem, sizeof(query_elem));
1467
1468
1469 query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL;
1470 if (src_exeq->get(src_exeq, &query_elem)) {
1471 BNX2X_ERR("There is a pending DEL command on the source queue already\n");
1472 return -EINVAL;
1473 }
1474
1475
1476 if (src_exeq->get(src_exeq, elem)) {
1477 DP(BNX2X_MSG_SP, "There is a pending MOVE command already\n");
1478 return -EEXIST;
1479 }
1480
1481
1482 query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD;
1483 if (dest_exeq->get(dest_exeq, &query_elem)) {
1484 BNX2X_ERR("There is a pending ADD command on the destination queue already\n");
1485 return -EINVAL;
1486 }
1487
1488
1489 if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
1490 &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1491 dest_o->get_credit(dest_o)))
1492 return -EINVAL;
1493
1494 if (!(test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1495 &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1496 src_o->put_credit(src_o))) {
1497
1498 dest_o->put_credit(dest_o);
1499 return -EINVAL;
1500 }
1501
1502 return 0;
1503 }
1504
1505 static int bnx2x_validate_vlan_mac(struct bnx2x *bp,
1506 union bnx2x_qable_obj *qo,
1507 struct bnx2x_exeq_elem *elem)
1508 {
1509 switch (elem->cmd_data.vlan_mac.cmd) {
1510 case BNX2X_VLAN_MAC_ADD:
1511 return bnx2x_validate_vlan_mac_add(bp, qo, elem);
1512 case BNX2X_VLAN_MAC_DEL:
1513 return bnx2x_validate_vlan_mac_del(bp, qo, elem);
1514 case BNX2X_VLAN_MAC_MOVE:
1515 return bnx2x_validate_vlan_mac_move(bp, qo, elem);
1516 default:
1517 return -EINVAL;
1518 }
1519 }
1520
1521 static int bnx2x_remove_vlan_mac(struct bnx2x *bp,
1522 union bnx2x_qable_obj *qo,
1523 struct bnx2x_exeq_elem *elem)
1524 {
1525 int rc = 0;
1526
1527
1528 if (test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1529 &elem->cmd_data.vlan_mac.vlan_mac_flags))
1530 return 0;
1531
1532 switch (elem->cmd_data.vlan_mac.cmd) {
1533 case BNX2X_VLAN_MAC_ADD:
1534 case BNX2X_VLAN_MAC_MOVE:
1535 rc = qo->vlan_mac.put_credit(&qo->vlan_mac);
1536 break;
1537 case BNX2X_VLAN_MAC_DEL:
1538 rc = qo->vlan_mac.get_credit(&qo->vlan_mac);
1539 break;
1540 default:
1541 return -EINVAL;
1542 }
1543
1544 if (rc != true)
1545 return -EINVAL;
1546
1547 return 0;
1548 }
1549
1550
1551
1552
1553
1554
1555
1556
1557 static int bnx2x_wait_vlan_mac(struct bnx2x *bp,
1558 struct bnx2x_vlan_mac_obj *o)
1559 {
1560 int cnt = 5000, rc;
1561 struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1562 struct bnx2x_raw_obj *raw = &o->raw;
1563
1564 while (cnt--) {
1565
1566 rc = raw->wait_comp(bp, raw);
1567 if (rc)
1568 return rc;
1569
1570
1571 if (!bnx2x_exe_queue_empty(exeq))
1572 usleep_range(1000, 2000);
1573 else
1574 return 0;
1575 }
1576
1577 return -EBUSY;
1578 }
1579
1580 static int __bnx2x_vlan_mac_execute_step(struct bnx2x *bp,
1581 struct bnx2x_vlan_mac_obj *o,
1582 unsigned long *ramrod_flags)
1583 {
1584 int rc = 0;
1585
1586 spin_lock_bh(&o->exe_queue.lock);
1587
1588 DP(BNX2X_MSG_SP, "vlan_mac_execute_step - trying to take writer lock\n");
1589 rc = __bnx2x_vlan_mac_h_write_trylock(bp, o);
1590
1591 if (rc != 0) {
1592 __bnx2x_vlan_mac_h_pend(bp, o, *ramrod_flags);
1593
1594
1595
1596
1597 rc = 1;
1598 } else {
1599 rc = bnx2x_exe_queue_step(bp, &o->exe_queue, ramrod_flags);
1600 }
1601 spin_unlock_bh(&o->exe_queue.lock);
1602
1603 return rc;
1604 }
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615 static int bnx2x_complete_vlan_mac(struct bnx2x *bp,
1616 struct bnx2x_vlan_mac_obj *o,
1617 union event_ring_elem *cqe,
1618 unsigned long *ramrod_flags)
1619 {
1620 struct bnx2x_raw_obj *r = &o->raw;
1621 int rc;
1622
1623
1624
1625
1626 spin_lock_bh(&o->exe_queue.lock);
1627
1628
1629 __bnx2x_exe_queue_reset_pending(bp, &o->exe_queue);
1630
1631
1632 r->clear_pending(r);
1633
1634 spin_unlock_bh(&o->exe_queue.lock);
1635
1636
1637 if (cqe->message.error)
1638 return -EINVAL;
1639
1640
1641 if (test_bit(RAMROD_CONT, ramrod_flags)) {
1642 rc = __bnx2x_vlan_mac_execute_step(bp, o, ramrod_flags);
1643
1644 if (rc < 0)
1645 return rc;
1646 }
1647
1648
1649 if (!bnx2x_exe_queue_empty(&o->exe_queue))
1650 return 1;
1651
1652 return 0;
1653 }
1654
1655
1656
1657
1658
1659
1660
1661
1662 static int bnx2x_optimize_vlan_mac(struct bnx2x *bp,
1663 union bnx2x_qable_obj *qo,
1664 struct bnx2x_exeq_elem *elem)
1665 {
1666 struct bnx2x_exeq_elem query, *pos;
1667 struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac;
1668 struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
1669
1670 memcpy(&query, elem, sizeof(query));
1671
1672 switch (elem->cmd_data.vlan_mac.cmd) {
1673 case BNX2X_VLAN_MAC_ADD:
1674 query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL;
1675 break;
1676 case BNX2X_VLAN_MAC_DEL:
1677 query.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD;
1678 break;
1679 default:
1680
1681 return 0;
1682 }
1683
1684
1685 pos = exeq->get(exeq, &query);
1686 if (pos) {
1687
1688
1689 if (!test_bit(BNX2X_DONT_CONSUME_CAM_CREDIT,
1690 &pos->cmd_data.vlan_mac.vlan_mac_flags)) {
1691 if ((query.cmd_data.vlan_mac.cmd ==
1692 BNX2X_VLAN_MAC_ADD) && !o->put_credit(o)) {
1693 BNX2X_ERR("Failed to return the credit for the optimized ADD command\n");
1694 return -EINVAL;
1695 } else if (!o->get_credit(o)) {
1696 BNX2X_ERR("Failed to recover the credit from the optimized DEL command\n");
1697 return -EINVAL;
1698 }
1699 }
1700
1701 DP(BNX2X_MSG_SP, "Optimizing %s command\n",
1702 (elem->cmd_data.vlan_mac.cmd == BNX2X_VLAN_MAC_ADD) ?
1703 "ADD" : "DEL");
1704
1705 list_del(&pos->link);
1706 bnx2x_exe_queue_free_elem(bp, pos);
1707 return 1;
1708 }
1709
1710 return 0;
1711 }
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724 static inline int bnx2x_vlan_mac_get_registry_elem(
1725 struct bnx2x *bp,
1726 struct bnx2x_vlan_mac_obj *o,
1727 struct bnx2x_exeq_elem *elem,
1728 bool restore,
1729 struct bnx2x_vlan_mac_registry_elem **re)
1730 {
1731 enum bnx2x_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
1732 struct bnx2x_vlan_mac_registry_elem *reg_elem;
1733
1734
1735 if (!restore &&
1736 ((cmd == BNX2X_VLAN_MAC_ADD) || (cmd == BNX2X_VLAN_MAC_MOVE))) {
1737 reg_elem = kzalloc(sizeof(*reg_elem), GFP_ATOMIC);
1738 if (!reg_elem)
1739 return -ENOMEM;
1740
1741
1742 if (!o->get_cam_offset(o, ®_elem->cam_offset)) {
1743
1744
1745
1746 WARN_ON(1);
1747 kfree(reg_elem);
1748 return -EINVAL;
1749 }
1750
1751 DP(BNX2X_MSG_SP, "Got cam offset %d\n", reg_elem->cam_offset);
1752
1753
1754 memcpy(®_elem->u, &elem->cmd_data.vlan_mac.u,
1755 sizeof(reg_elem->u));
1756
1757
1758 reg_elem->vlan_mac_flags =
1759 elem->cmd_data.vlan_mac.vlan_mac_flags;
1760 } else
1761 reg_elem = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u);
1762
1763 *re = reg_elem;
1764 return 0;
1765 }
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777 static int bnx2x_execute_vlan_mac(struct bnx2x *bp,
1778 union bnx2x_qable_obj *qo,
1779 struct list_head *exe_chunk,
1780 unsigned long *ramrod_flags)
1781 {
1782 struct bnx2x_exeq_elem *elem;
1783 struct bnx2x_vlan_mac_obj *o = &qo->vlan_mac, *cam_obj;
1784 struct bnx2x_raw_obj *r = &o->raw;
1785 int rc, idx = 0;
1786 bool restore = test_bit(RAMROD_RESTORE, ramrod_flags);
1787 bool drv_only = test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags);
1788 struct bnx2x_vlan_mac_registry_elem *reg_elem;
1789 enum bnx2x_vlan_mac_cmd cmd;
1790
1791
1792
1793
1794 if (!drv_only) {
1795 WARN_ON(r->check_pending(r));
1796
1797
1798 r->set_pending(r);
1799
1800
1801 list_for_each_entry(elem, exe_chunk, link) {
1802 cmd = elem->cmd_data.vlan_mac.cmd;
1803
1804
1805
1806 if (cmd == BNX2X_VLAN_MAC_MOVE)
1807 cam_obj = elem->cmd_data.vlan_mac.target_obj;
1808 else
1809 cam_obj = o;
1810
1811 rc = bnx2x_vlan_mac_get_registry_elem(bp, cam_obj,
1812 elem, restore,
1813 ®_elem);
1814 if (rc)
1815 goto error_exit;
1816
1817 WARN_ON(!reg_elem);
1818
1819
1820 if (!restore &&
1821 ((cmd == BNX2X_VLAN_MAC_ADD) ||
1822 (cmd == BNX2X_VLAN_MAC_MOVE)))
1823 list_add(®_elem->link, &cam_obj->head);
1824
1825
1826 o->set_one_rule(bp, o, elem, idx,
1827 reg_elem->cam_offset);
1828
1829
1830 if (cmd == BNX2X_VLAN_MAC_MOVE)
1831 idx += 2;
1832 else
1833 idx++;
1834 }
1835
1836
1837
1838
1839
1840
1841
1842
1843 rc = bnx2x_sp_post(bp, o->ramrod_cmd, r->cid,
1844 U64_HI(r->rdata_mapping),
1845 U64_LO(r->rdata_mapping),
1846 ETH_CONNECTION_TYPE);
1847 if (rc)
1848 goto error_exit;
1849 }
1850
1851
1852 list_for_each_entry(elem, exe_chunk, link) {
1853 cmd = elem->cmd_data.vlan_mac.cmd;
1854 if ((cmd == BNX2X_VLAN_MAC_DEL) ||
1855 (cmd == BNX2X_VLAN_MAC_MOVE)) {
1856 reg_elem = o->check_del(bp, o,
1857 &elem->cmd_data.vlan_mac.u);
1858
1859 WARN_ON(!reg_elem);
1860
1861 o->put_cam_offset(o, reg_elem->cam_offset);
1862 list_del(®_elem->link);
1863 kfree(reg_elem);
1864 }
1865 }
1866
1867 if (!drv_only)
1868 return 1;
1869 else
1870 return 0;
1871
1872 error_exit:
1873 r->clear_pending(r);
1874
1875
1876 list_for_each_entry(elem, exe_chunk, link) {
1877 cmd = elem->cmd_data.vlan_mac.cmd;
1878
1879 if (cmd == BNX2X_VLAN_MAC_MOVE)
1880 cam_obj = elem->cmd_data.vlan_mac.target_obj;
1881 else
1882 cam_obj = o;
1883
1884
1885 if (!restore &&
1886 ((cmd == BNX2X_VLAN_MAC_ADD) ||
1887 (cmd == BNX2X_VLAN_MAC_MOVE))) {
1888 reg_elem = o->check_del(bp, cam_obj,
1889 &elem->cmd_data.vlan_mac.u);
1890 if (reg_elem) {
1891 list_del(®_elem->link);
1892 kfree(reg_elem);
1893 }
1894 }
1895 }
1896
1897 return rc;
1898 }
1899
1900 static inline int bnx2x_vlan_mac_push_new_cmd(
1901 struct bnx2x *bp,
1902 struct bnx2x_vlan_mac_ramrod_params *p)
1903 {
1904 struct bnx2x_exeq_elem *elem;
1905 struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj;
1906 bool restore = test_bit(RAMROD_RESTORE, &p->ramrod_flags);
1907
1908
1909 elem = bnx2x_exe_queue_alloc_elem(bp);
1910 if (!elem)
1911 return -ENOMEM;
1912
1913
1914 switch (p->user_req.cmd) {
1915 case BNX2X_VLAN_MAC_MOVE:
1916 elem->cmd_len = 2;
1917 break;
1918 default:
1919 elem->cmd_len = 1;
1920 }
1921
1922
1923 memcpy(&elem->cmd_data.vlan_mac, &p->user_req, sizeof(p->user_req));
1924
1925
1926 return bnx2x_exe_queue_add(bp, &o->exe_queue, elem, restore);
1927 }
1928
1929
1930
1931
1932
1933
1934
1935
1936 int bnx2x_config_vlan_mac(struct bnx2x *bp,
1937 struct bnx2x_vlan_mac_ramrod_params *p)
1938 {
1939 int rc = 0;
1940 struct bnx2x_vlan_mac_obj *o = p->vlan_mac_obj;
1941 unsigned long *ramrod_flags = &p->ramrod_flags;
1942 bool cont = test_bit(RAMROD_CONT, ramrod_flags);
1943 struct bnx2x_raw_obj *raw = &o->raw;
1944
1945
1946
1947
1948 if (!cont) {
1949 rc = bnx2x_vlan_mac_push_new_cmd(bp, p);
1950 if (rc)
1951 return rc;
1952 }
1953
1954
1955
1956
1957 if (!bnx2x_exe_queue_empty(&o->exe_queue))
1958 rc = 1;
1959
1960 if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {
1961 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\n");
1962 raw->clear_pending(raw);
1963 }
1964
1965
1966 if (cont || test_bit(RAMROD_EXEC, ramrod_flags) ||
1967 test_bit(RAMROD_COMP_WAIT, ramrod_flags)) {
1968 rc = __bnx2x_vlan_mac_execute_step(bp, p->vlan_mac_obj,
1969 &p->ramrod_flags);
1970 if (rc < 0)
1971 return rc;
1972 }
1973
1974
1975
1976
1977 if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) {
1978
1979
1980
1981 int max_iterations = bnx2x_exe_queue_length(&o->exe_queue) + 1;
1982
1983 while (!bnx2x_exe_queue_empty(&o->exe_queue) &&
1984 max_iterations--) {
1985
1986
1987 rc = raw->wait_comp(bp, raw);
1988 if (rc)
1989 return rc;
1990
1991
1992 rc = __bnx2x_vlan_mac_execute_step(bp,
1993 p->vlan_mac_obj,
1994 &p->ramrod_flags);
1995 if (rc < 0)
1996 return rc;
1997 }
1998
1999 return 0;
2000 }
2001
2002 return rc;
2003 }
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018 static int bnx2x_vlan_mac_del_all(struct bnx2x *bp,
2019 struct bnx2x_vlan_mac_obj *o,
2020 unsigned long *vlan_mac_flags,
2021 unsigned long *ramrod_flags)
2022 {
2023 struct bnx2x_vlan_mac_registry_elem *pos = NULL;
2024 struct bnx2x_vlan_mac_ramrod_params p;
2025 struct bnx2x_exe_queue_obj *exeq = &o->exe_queue;
2026 struct bnx2x_exeq_elem *exeq_pos, *exeq_pos_n;
2027 unsigned long flags;
2028 int read_lock;
2029 int rc = 0;
2030
2031
2032
2033 spin_lock_bh(&exeq->lock);
2034
2035 list_for_each_entry_safe(exeq_pos, exeq_pos_n, &exeq->exe_queue, link) {
2036 flags = exeq_pos->cmd_data.vlan_mac.vlan_mac_flags;
2037 if (BNX2X_VLAN_MAC_CMP_FLAGS(flags) ==
2038 BNX2X_VLAN_MAC_CMP_FLAGS(*vlan_mac_flags)) {
2039 rc = exeq->remove(bp, exeq->owner, exeq_pos);
2040 if (rc) {
2041 BNX2X_ERR("Failed to remove command\n");
2042 spin_unlock_bh(&exeq->lock);
2043 return rc;
2044 }
2045 list_del(&exeq_pos->link);
2046 bnx2x_exe_queue_free_elem(bp, exeq_pos);
2047 }
2048 }
2049
2050 spin_unlock_bh(&exeq->lock);
2051
2052
2053 memset(&p, 0, sizeof(p));
2054 p.vlan_mac_obj = o;
2055 p.ramrod_flags = *ramrod_flags;
2056 p.user_req.cmd = BNX2X_VLAN_MAC_DEL;
2057
2058
2059
2060
2061 __clear_bit(RAMROD_COMP_WAIT, &p.ramrod_flags);
2062 __clear_bit(RAMROD_EXEC, &p.ramrod_flags);
2063 __clear_bit(RAMROD_CONT, &p.ramrod_flags);
2064
2065 DP(BNX2X_MSG_SP, "vlan_mac_del_all -- taking vlan_mac_lock (reader)\n");
2066 read_lock = bnx2x_vlan_mac_h_read_lock(bp, o);
2067 if (read_lock != 0)
2068 return read_lock;
2069
2070 list_for_each_entry(pos, &o->head, link) {
2071 flags = pos->vlan_mac_flags;
2072 if (BNX2X_VLAN_MAC_CMP_FLAGS(flags) ==
2073 BNX2X_VLAN_MAC_CMP_FLAGS(*vlan_mac_flags)) {
2074 p.user_req.vlan_mac_flags = pos->vlan_mac_flags;
2075 memcpy(&p.user_req.u, &pos->u, sizeof(pos->u));
2076 rc = bnx2x_config_vlan_mac(bp, &p);
2077 if (rc < 0) {
2078 BNX2X_ERR("Failed to add a new DEL command\n");
2079 bnx2x_vlan_mac_h_read_unlock(bp, o);
2080 return rc;
2081 }
2082 }
2083 }
2084
2085 DP(BNX2X_MSG_SP, "vlan_mac_del_all -- releasing vlan_mac_lock (reader)\n");
2086 bnx2x_vlan_mac_h_read_unlock(bp, o);
2087
2088 p.ramrod_flags = *ramrod_flags;
2089 __set_bit(RAMROD_CONT, &p.ramrod_flags);
2090
2091 return bnx2x_config_vlan_mac(bp, &p);
2092 }
2093
2094 static inline void bnx2x_init_raw_obj(struct bnx2x_raw_obj *raw, u8 cl_id,
2095 u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping, int state,
2096 unsigned long *pstate, bnx2x_obj_type type)
2097 {
2098 raw->func_id = func_id;
2099 raw->cid = cid;
2100 raw->cl_id = cl_id;
2101 raw->rdata = rdata;
2102 raw->rdata_mapping = rdata_mapping;
2103 raw->state = state;
2104 raw->pstate = pstate;
2105 raw->obj_type = type;
2106 raw->check_pending = bnx2x_raw_check_pending;
2107 raw->clear_pending = bnx2x_raw_clear_pending;
2108 raw->set_pending = bnx2x_raw_set_pending;
2109 raw->wait_comp = bnx2x_raw_wait;
2110 }
2111
2112 static inline void bnx2x_init_vlan_mac_common(struct bnx2x_vlan_mac_obj *o,
2113 u8 cl_id, u32 cid, u8 func_id, void *rdata, dma_addr_t rdata_mapping,
2114 int state, unsigned long *pstate, bnx2x_obj_type type,
2115 struct bnx2x_credit_pool_obj *macs_pool,
2116 struct bnx2x_credit_pool_obj *vlans_pool)
2117 {
2118 INIT_LIST_HEAD(&o->head);
2119 o->head_reader = 0;
2120 o->head_exe_request = false;
2121 o->saved_ramrod_flags = 0;
2122
2123 o->macs_pool = macs_pool;
2124 o->vlans_pool = vlans_pool;
2125
2126 o->delete_all = bnx2x_vlan_mac_del_all;
2127 o->restore = bnx2x_vlan_mac_restore;
2128 o->complete = bnx2x_complete_vlan_mac;
2129 o->wait = bnx2x_wait_vlan_mac;
2130
2131 bnx2x_init_raw_obj(&o->raw, cl_id, cid, func_id, rdata, rdata_mapping,
2132 state, pstate, type);
2133 }
2134
2135 void bnx2x_init_mac_obj(struct bnx2x *bp,
2136 struct bnx2x_vlan_mac_obj *mac_obj,
2137 u8 cl_id, u32 cid, u8 func_id, void *rdata,
2138 dma_addr_t rdata_mapping, int state,
2139 unsigned long *pstate, bnx2x_obj_type type,
2140 struct bnx2x_credit_pool_obj *macs_pool)
2141 {
2142 union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)mac_obj;
2143
2144 bnx2x_init_vlan_mac_common(mac_obj, cl_id, cid, func_id, rdata,
2145 rdata_mapping, state, pstate, type,
2146 macs_pool, NULL);
2147
2148
2149 mac_obj->get_credit = bnx2x_get_credit_mac;
2150 mac_obj->put_credit = bnx2x_put_credit_mac;
2151 mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac;
2152 mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac;
2153
2154 if (CHIP_IS_E1x(bp)) {
2155 mac_obj->set_one_rule = bnx2x_set_one_mac_e1x;
2156 mac_obj->check_del = bnx2x_check_mac_del;
2157 mac_obj->check_add = bnx2x_check_mac_add;
2158 mac_obj->check_move = bnx2x_check_move_always_err;
2159 mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC;
2160
2161
2162 bnx2x_exe_queue_init(bp,
2163 &mac_obj->exe_queue, 1, qable_obj,
2164 bnx2x_validate_vlan_mac,
2165 bnx2x_remove_vlan_mac,
2166 bnx2x_optimize_vlan_mac,
2167 bnx2x_execute_vlan_mac,
2168 bnx2x_exeq_get_mac);
2169 } else {
2170 mac_obj->set_one_rule = bnx2x_set_one_mac_e2;
2171 mac_obj->check_del = bnx2x_check_mac_del;
2172 mac_obj->check_add = bnx2x_check_mac_add;
2173 mac_obj->check_move = bnx2x_check_move;
2174 mac_obj->ramrod_cmd =
2175 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
2176 mac_obj->get_n_elements = bnx2x_get_n_elements;
2177
2178
2179 bnx2x_exe_queue_init(bp,
2180 &mac_obj->exe_queue, CLASSIFY_RULES_COUNT,
2181 qable_obj, bnx2x_validate_vlan_mac,
2182 bnx2x_remove_vlan_mac,
2183 bnx2x_optimize_vlan_mac,
2184 bnx2x_execute_vlan_mac,
2185 bnx2x_exeq_get_mac);
2186 }
2187 }
2188
2189 void bnx2x_init_vlan_obj(struct bnx2x *bp,
2190 struct bnx2x_vlan_mac_obj *vlan_obj,
2191 u8 cl_id, u32 cid, u8 func_id, void *rdata,
2192 dma_addr_t rdata_mapping, int state,
2193 unsigned long *pstate, bnx2x_obj_type type,
2194 struct bnx2x_credit_pool_obj *vlans_pool)
2195 {
2196 union bnx2x_qable_obj *qable_obj = (union bnx2x_qable_obj *)vlan_obj;
2197
2198 bnx2x_init_vlan_mac_common(vlan_obj, cl_id, cid, func_id, rdata,
2199 rdata_mapping, state, pstate, type, NULL,
2200 vlans_pool);
2201
2202 vlan_obj->get_credit = bnx2x_get_credit_vlan;
2203 vlan_obj->put_credit = bnx2x_put_credit_vlan;
2204 vlan_obj->get_cam_offset = bnx2x_get_cam_offset_vlan;
2205 vlan_obj->put_cam_offset = bnx2x_put_cam_offset_vlan;
2206
2207 if (CHIP_IS_E1x(bp)) {
2208 BNX2X_ERR("Do not support chips others than E2 and newer\n");
2209 BUG();
2210 } else {
2211 vlan_obj->set_one_rule = bnx2x_set_one_vlan_e2;
2212 vlan_obj->check_del = bnx2x_check_vlan_del;
2213 vlan_obj->check_add = bnx2x_check_vlan_add;
2214 vlan_obj->check_move = bnx2x_check_move;
2215 vlan_obj->ramrod_cmd =
2216 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
2217 vlan_obj->get_n_elements = bnx2x_get_n_elements;
2218
2219
2220 bnx2x_exe_queue_init(bp,
2221 &vlan_obj->exe_queue, CLASSIFY_RULES_COUNT,
2222 qable_obj, bnx2x_validate_vlan_mac,
2223 bnx2x_remove_vlan_mac,
2224 bnx2x_optimize_vlan_mac,
2225 bnx2x_execute_vlan_mac,
2226 bnx2x_exeq_get_vlan);
2227 }
2228 }
2229
2230 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp,
2231 struct bnx2x_vlan_mac_obj *vlan_mac_obj,
2232 u8 cl_id, u32 cid, u8 func_id, void *rdata,
2233 dma_addr_t rdata_mapping, int state,
2234 unsigned long *pstate, bnx2x_obj_type type,
2235 struct bnx2x_credit_pool_obj *macs_pool,
2236 struct bnx2x_credit_pool_obj *vlans_pool)
2237 {
2238 union bnx2x_qable_obj *qable_obj =
2239 (union bnx2x_qable_obj *)vlan_mac_obj;
2240
2241 bnx2x_init_vlan_mac_common(vlan_mac_obj, cl_id, cid, func_id, rdata,
2242 rdata_mapping, state, pstate, type,
2243 macs_pool, vlans_pool);
2244
2245
2246 vlan_mac_obj->get_credit = bnx2x_get_credit_vlan_mac;
2247 vlan_mac_obj->put_credit = bnx2x_put_credit_vlan_mac;
2248
2249
2250
2251
2252 vlan_mac_obj->get_cam_offset = bnx2x_get_cam_offset_mac;
2253 vlan_mac_obj->put_cam_offset = bnx2x_put_cam_offset_mac;
2254
2255 if (CHIP_IS_E1(bp)) {
2256 BNX2X_ERR("Do not support chips others than E2\n");
2257 BUG();
2258 } else if (CHIP_IS_E1H(bp)) {
2259 vlan_mac_obj->set_one_rule = bnx2x_set_one_vlan_mac_e1h;
2260 vlan_mac_obj->check_del = bnx2x_check_vlan_mac_del;
2261 vlan_mac_obj->check_add = bnx2x_check_vlan_mac_add;
2262 vlan_mac_obj->check_move = bnx2x_check_move_always_err;
2263 vlan_mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC;
2264
2265
2266 bnx2x_exe_queue_init(bp,
2267 &vlan_mac_obj->exe_queue, 1, qable_obj,
2268 bnx2x_validate_vlan_mac,
2269 bnx2x_remove_vlan_mac,
2270 bnx2x_optimize_vlan_mac,
2271 bnx2x_execute_vlan_mac,
2272 bnx2x_exeq_get_vlan_mac);
2273 } else {
2274 vlan_mac_obj->set_one_rule = bnx2x_set_one_vlan_mac_e2;
2275 vlan_mac_obj->check_del = bnx2x_check_vlan_mac_del;
2276 vlan_mac_obj->check_add = bnx2x_check_vlan_mac_add;
2277 vlan_mac_obj->check_move = bnx2x_check_move;
2278 vlan_mac_obj->ramrod_cmd =
2279 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
2280
2281
2282 bnx2x_exe_queue_init(bp,
2283 &vlan_mac_obj->exe_queue,
2284 CLASSIFY_RULES_COUNT,
2285 qable_obj, bnx2x_validate_vlan_mac,
2286 bnx2x_remove_vlan_mac,
2287 bnx2x_optimize_vlan_mac,
2288 bnx2x_execute_vlan_mac,
2289 bnx2x_exeq_get_vlan_mac);
2290 }
2291 }
2292
2293 static inline void __storm_memset_mac_filters(struct bnx2x *bp,
2294 struct tstorm_eth_mac_filter_config *mac_filters,
2295 u16 pf_id)
2296 {
2297 size_t size = sizeof(struct tstorm_eth_mac_filter_config);
2298
2299 u32 addr = BAR_TSTRORM_INTMEM +
2300 TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id);
2301
2302 __storm_memset_struct(bp, addr, size, (u32 *)mac_filters);
2303 }
2304
2305 static int bnx2x_set_rx_mode_e1x(struct bnx2x *bp,
2306 struct bnx2x_rx_mode_ramrod_params *p)
2307 {
2308
2309 u32 mask = (1 << p->cl_id);
2310
2311 struct tstorm_eth_mac_filter_config *mac_filters =
2312 (struct tstorm_eth_mac_filter_config *)p->rdata;
2313
2314
2315 u8 drop_all_ucast = 1, drop_all_mcast = 1;
2316 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2317 u8 unmatched_unicast = 0;
2318
2319
2320
2321 if (test_bit(BNX2X_ACCEPT_UNICAST, &p->rx_accept_flags))
2322
2323 drop_all_ucast = 0;
2324
2325 if (test_bit(BNX2X_ACCEPT_MULTICAST, &p->rx_accept_flags))
2326
2327 drop_all_mcast = 0;
2328
2329 if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, &p->rx_accept_flags)) {
2330
2331 drop_all_ucast = 0;
2332 accp_all_ucast = 1;
2333 }
2334 if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, &p->rx_accept_flags)) {
2335
2336 drop_all_mcast = 0;
2337 accp_all_mcast = 1;
2338 }
2339 if (test_bit(BNX2X_ACCEPT_BROADCAST, &p->rx_accept_flags))
2340
2341 accp_all_bcast = 1;
2342 if (test_bit(BNX2X_ACCEPT_UNMATCHED, &p->rx_accept_flags))
2343
2344 unmatched_unicast = 1;
2345
2346 mac_filters->ucast_drop_all = drop_all_ucast ?
2347 mac_filters->ucast_drop_all | mask :
2348 mac_filters->ucast_drop_all & ~mask;
2349
2350 mac_filters->mcast_drop_all = drop_all_mcast ?
2351 mac_filters->mcast_drop_all | mask :
2352 mac_filters->mcast_drop_all & ~mask;
2353
2354 mac_filters->ucast_accept_all = accp_all_ucast ?
2355 mac_filters->ucast_accept_all | mask :
2356 mac_filters->ucast_accept_all & ~mask;
2357
2358 mac_filters->mcast_accept_all = accp_all_mcast ?
2359 mac_filters->mcast_accept_all | mask :
2360 mac_filters->mcast_accept_all & ~mask;
2361
2362 mac_filters->bcast_accept_all = accp_all_bcast ?
2363 mac_filters->bcast_accept_all | mask :
2364 mac_filters->bcast_accept_all & ~mask;
2365
2366 mac_filters->unmatched_unicast = unmatched_unicast ?
2367 mac_filters->unmatched_unicast | mask :
2368 mac_filters->unmatched_unicast & ~mask;
2369
2370 DP(BNX2X_MSG_SP, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n"
2371 "accp_mcast 0x%x\naccp_bcast 0x%x\n",
2372 mac_filters->ucast_drop_all, mac_filters->mcast_drop_all,
2373 mac_filters->ucast_accept_all, mac_filters->mcast_accept_all,
2374 mac_filters->bcast_accept_all);
2375
2376
2377 __storm_memset_mac_filters(bp, mac_filters, p->func_id);
2378
2379
2380 clear_bit(p->state, p->pstate);
2381 smp_mb__after_atomic();
2382
2383 return 0;
2384 }
2385
2386
2387 static inline void bnx2x_rx_mode_set_rdata_hdr_e2(u32 cid,
2388 struct eth_classify_header *hdr,
2389 u8 rule_cnt)
2390 {
2391 hdr->echo = cpu_to_le32(cid);
2392 hdr->rule_cnt = rule_cnt;
2393 }
2394
2395 static inline void bnx2x_rx_mode_set_cmd_state_e2(struct bnx2x *bp,
2396 unsigned long *accept_flags,
2397 struct eth_filter_rules_cmd *cmd,
2398 bool clear_accept_all)
2399 {
2400 u16 state;
2401
2402
2403 state = ETH_FILTER_RULES_CMD_UCAST_DROP_ALL |
2404 ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2405
2406 if (test_bit(BNX2X_ACCEPT_UNICAST, accept_flags))
2407 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2408
2409 if (test_bit(BNX2X_ACCEPT_MULTICAST, accept_flags))
2410 state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2411
2412 if (test_bit(BNX2X_ACCEPT_ALL_UNICAST, accept_flags)) {
2413 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2414 state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL;
2415 }
2416
2417 if (test_bit(BNX2X_ACCEPT_ALL_MULTICAST, accept_flags)) {
2418 state |= ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL;
2419 state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2420 }
2421
2422 if (test_bit(BNX2X_ACCEPT_BROADCAST, accept_flags))
2423 state |= ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL;
2424
2425 if (test_bit(BNX2X_ACCEPT_UNMATCHED, accept_flags)) {
2426 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2427 state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED;
2428 }
2429
2430 if (test_bit(BNX2X_ACCEPT_ANY_VLAN, accept_flags))
2431 state |= ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN;
2432
2433
2434 if (clear_accept_all) {
2435 state &= ~ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL;
2436 state &= ~ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL;
2437 state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL;
2438 state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED;
2439 }
2440
2441 cmd->state = cpu_to_le16(state);
2442 }
2443
2444 static int bnx2x_set_rx_mode_e2(struct bnx2x *bp,
2445 struct bnx2x_rx_mode_ramrod_params *p)
2446 {
2447 struct eth_filter_rules_ramrod_data *data = p->rdata;
2448 int rc;
2449 u8 rule_idx = 0;
2450
2451
2452 memset(data, 0, sizeof(*data));
2453
2454
2455
2456
2457 if (test_bit(RAMROD_TX, &p->ramrod_flags)) {
2458 data->rules[rule_idx].client_id = p->cl_id;
2459 data->rules[rule_idx].func_id = p->func_id;
2460
2461 data->rules[rule_idx].cmd_general_data =
2462 ETH_FILTER_RULES_CMD_TX_CMD;
2463
2464 bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags,
2465 &(data->rules[rule_idx++]),
2466 false);
2467 }
2468
2469
2470 if (test_bit(RAMROD_RX, &p->ramrod_flags)) {
2471 data->rules[rule_idx].client_id = p->cl_id;
2472 data->rules[rule_idx].func_id = p->func_id;
2473
2474 data->rules[rule_idx].cmd_general_data =
2475 ETH_FILTER_RULES_CMD_RX_CMD;
2476
2477 bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags,
2478 &(data->rules[rule_idx++]),
2479 false);
2480 }
2481
2482
2483
2484
2485
2486
2487
2488 if (test_bit(BNX2X_RX_MODE_FCOE_ETH, &p->rx_mode_flags)) {
2489
2490 if (test_bit(RAMROD_TX, &p->ramrod_flags)) {
2491 data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id);
2492 data->rules[rule_idx].func_id = p->func_id;
2493
2494 data->rules[rule_idx].cmd_general_data =
2495 ETH_FILTER_RULES_CMD_TX_CMD;
2496
2497 bnx2x_rx_mode_set_cmd_state_e2(bp, &p->tx_accept_flags,
2498 &(data->rules[rule_idx]),
2499 true);
2500 rule_idx++;
2501 }
2502
2503
2504 if (test_bit(RAMROD_RX, &p->ramrod_flags)) {
2505 data->rules[rule_idx].client_id = bnx2x_fcoe(bp, cl_id);
2506 data->rules[rule_idx].func_id = p->func_id;
2507
2508 data->rules[rule_idx].cmd_general_data =
2509 ETH_FILTER_RULES_CMD_RX_CMD;
2510
2511 bnx2x_rx_mode_set_cmd_state_e2(bp, &p->rx_accept_flags,
2512 &(data->rules[rule_idx]),
2513 true);
2514 rule_idx++;
2515 }
2516 }
2517
2518
2519
2520
2521 bnx2x_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx);
2522
2523 DP(BNX2X_MSG_SP, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\n",
2524 data->header.rule_cnt, p->rx_accept_flags,
2525 p->tx_accept_flags);
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_FILTER_RULES, p->cid,
2536 U64_HI(p->rdata_mapping),
2537 U64_LO(p->rdata_mapping),
2538 ETH_CONNECTION_TYPE);
2539 if (rc)
2540 return rc;
2541
2542
2543 return 1;
2544 }
2545
2546 static int bnx2x_wait_rx_mode_comp_e2(struct bnx2x *bp,
2547 struct bnx2x_rx_mode_ramrod_params *p)
2548 {
2549 return bnx2x_state_wait(bp, p->state, p->pstate);
2550 }
2551
2552 static int bnx2x_empty_rx_mode_wait(struct bnx2x *bp,
2553 struct bnx2x_rx_mode_ramrod_params *p)
2554 {
2555
2556 return 0;
2557 }
2558
2559 int bnx2x_config_rx_mode(struct bnx2x *bp,
2560 struct bnx2x_rx_mode_ramrod_params *p)
2561 {
2562 int rc;
2563
2564
2565 rc = p->rx_mode_obj->config_rx_mode(bp, p);
2566 if (rc < 0)
2567 return rc;
2568
2569
2570 if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags)) {
2571 rc = p->rx_mode_obj->wait_comp(bp, p);
2572 if (rc)
2573 return rc;
2574 }
2575
2576 return rc;
2577 }
2578
2579 void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
2580 struct bnx2x_rx_mode_obj *o)
2581 {
2582 if (CHIP_IS_E1x(bp)) {
2583 o->wait_comp = bnx2x_empty_rx_mode_wait;
2584 o->config_rx_mode = bnx2x_set_rx_mode_e1x;
2585 } else {
2586 o->wait_comp = bnx2x_wait_rx_mode_comp_e2;
2587 o->config_rx_mode = bnx2x_set_rx_mode_e2;
2588 }
2589 }
2590
2591
2592 static inline u8 bnx2x_mcast_bin_from_mac(u8 *mac)
2593 {
2594 return (crc32c_le(0, mac, ETH_ALEN) >> 24) & 0xff;
2595 }
2596
2597 struct bnx2x_mcast_mac_elem {
2598 struct list_head link;
2599 u8 mac[ETH_ALEN];
2600 u8 pad[2];
2601 };
2602
2603 struct bnx2x_mcast_bin_elem {
2604 struct list_head link;
2605 int bin;
2606 int type;
2607 };
2608
2609 union bnx2x_mcast_elem {
2610 struct bnx2x_mcast_bin_elem bin_elem;
2611 struct bnx2x_mcast_mac_elem mac_elem;
2612 };
2613
2614 struct bnx2x_mcast_elem_group {
2615 struct list_head mcast_group_link;
2616 union bnx2x_mcast_elem mcast_elems[];
2617 };
2618
2619 #define MCAST_MAC_ELEMS_PER_PG \
2620 ((PAGE_SIZE - sizeof(struct bnx2x_mcast_elem_group)) / \
2621 sizeof(union bnx2x_mcast_elem))
2622
2623 struct bnx2x_pending_mcast_cmd {
2624 struct list_head link;
2625 struct list_head group_head;
2626 int type;
2627 union {
2628 struct list_head macs_head;
2629 u32 macs_num;
2630 int next_bin;
2631 } data;
2632
2633 bool set_convert;
2634
2635
2636
2637
2638 bool done;
2639
2640
2641
2642
2643
2644 };
2645
2646 static int bnx2x_mcast_wait(struct bnx2x *bp,
2647 struct bnx2x_mcast_obj *o)
2648 {
2649 if (bnx2x_state_wait(bp, o->sched_state, o->raw.pstate) ||
2650 o->raw.wait_comp(bp, &o->raw))
2651 return -EBUSY;
2652
2653 return 0;
2654 }
2655
2656 static void bnx2x_free_groups(struct list_head *mcast_group_list)
2657 {
2658 struct bnx2x_mcast_elem_group *current_mcast_group;
2659
2660 while (!list_empty(mcast_group_list)) {
2661 current_mcast_group = list_first_entry(mcast_group_list,
2662 struct bnx2x_mcast_elem_group,
2663 mcast_group_link);
2664 list_del(¤t_mcast_group->mcast_group_link);
2665 free_page((unsigned long)current_mcast_group);
2666 }
2667 }
2668
2669 static int bnx2x_mcast_enqueue_cmd(struct bnx2x *bp,
2670 struct bnx2x_mcast_obj *o,
2671 struct bnx2x_mcast_ramrod_params *p,
2672 enum bnx2x_mcast_cmd cmd)
2673 {
2674 struct bnx2x_pending_mcast_cmd *new_cmd;
2675 struct bnx2x_mcast_list_elem *pos;
2676 struct bnx2x_mcast_elem_group *elem_group;
2677 struct bnx2x_mcast_mac_elem *mac_elem;
2678 int total_elems = 0, macs_list_len = 0, offset = 0;
2679
2680
2681 if (cmd == BNX2X_MCAST_CMD_ADD || cmd == BNX2X_MCAST_CMD_SET)
2682 macs_list_len = p->mcast_list_len;
2683
2684
2685 if (!p->mcast_list_len)
2686 return 0;
2687
2688
2689 new_cmd = kzalloc(sizeof(*new_cmd), GFP_ATOMIC);
2690 if (!new_cmd)
2691 return -ENOMEM;
2692
2693 INIT_LIST_HEAD(&new_cmd->data.macs_head);
2694 INIT_LIST_HEAD(&new_cmd->group_head);
2695 new_cmd->type = cmd;
2696 new_cmd->done = false;
2697
2698 DP(BNX2X_MSG_SP, "About to enqueue a new %d command. macs_list_len=%d\n",
2699 cmd, macs_list_len);
2700
2701 switch (cmd) {
2702 case BNX2X_MCAST_CMD_ADD:
2703 case BNX2X_MCAST_CMD_SET:
2704
2705
2706
2707
2708 total_elems = macs_list_len;
2709 if (cmd == BNX2X_MCAST_CMD_SET) {
2710 if (total_elems < BNX2X_MCAST_BINS_NUM)
2711 total_elems = BNX2X_MCAST_BINS_NUM;
2712 }
2713 while (total_elems > 0) {
2714 elem_group = (struct bnx2x_mcast_elem_group *)
2715 __get_free_page(GFP_ATOMIC | __GFP_ZERO);
2716 if (!elem_group) {
2717 bnx2x_free_groups(&new_cmd->group_head);
2718 kfree(new_cmd);
2719 return -ENOMEM;
2720 }
2721 total_elems -= MCAST_MAC_ELEMS_PER_PG;
2722 list_add_tail(&elem_group->mcast_group_link,
2723 &new_cmd->group_head);
2724 }
2725 elem_group = list_first_entry(&new_cmd->group_head,
2726 struct bnx2x_mcast_elem_group,
2727 mcast_group_link);
2728 list_for_each_entry(pos, &p->mcast_list, link) {
2729 mac_elem = &elem_group->mcast_elems[offset].mac_elem;
2730 memcpy(mac_elem->mac, pos->mac, ETH_ALEN);
2731
2732
2733
2734 list_add_tail(&mac_elem->link,
2735 &new_cmd->data.macs_head);
2736 offset++;
2737 if (offset == MCAST_MAC_ELEMS_PER_PG) {
2738 offset = 0;
2739 elem_group = list_next_entry(elem_group,
2740 mcast_group_link);
2741 }
2742 }
2743 break;
2744
2745 case BNX2X_MCAST_CMD_DEL:
2746 new_cmd->data.macs_num = p->mcast_list_len;
2747 break;
2748
2749 case BNX2X_MCAST_CMD_RESTORE:
2750 new_cmd->data.next_bin = 0;
2751 break;
2752
2753 default:
2754 kfree(new_cmd);
2755 BNX2X_ERR("Unknown command: %d\n", cmd);
2756 return -EINVAL;
2757 }
2758
2759
2760 list_add_tail(&new_cmd->link, &o->pending_cmds_head);
2761
2762 o->set_sched(o);
2763
2764 return 1;
2765 }
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775 static inline int bnx2x_mcast_get_next_bin(struct bnx2x_mcast_obj *o, int last)
2776 {
2777 int i, j, inner_start = last % BIT_VEC64_ELEM_SZ;
2778
2779 for (i = last / BIT_VEC64_ELEM_SZ; i < BNX2X_MCAST_VEC_SZ; i++) {
2780 if (o->registry.aprox_match.vec[i])
2781 for (j = inner_start; j < BIT_VEC64_ELEM_SZ; j++) {
2782 int cur_bit = j + BIT_VEC64_ELEM_SZ * i;
2783 if (BIT_VEC64_TEST_BIT(o->registry.aprox_match.
2784 vec, cur_bit)) {
2785 return cur_bit;
2786 }
2787 }
2788 inner_start = 0;
2789 }
2790
2791
2792 return -1;
2793 }
2794
2795
2796
2797
2798
2799
2800
2801
2802 static inline int bnx2x_mcast_clear_first_bin(struct bnx2x_mcast_obj *o)
2803 {
2804 int cur_bit = bnx2x_mcast_get_next_bin(o, 0);
2805
2806 if (cur_bit >= 0)
2807 BIT_VEC64_CLEAR_BIT(o->registry.aprox_match.vec, cur_bit);
2808
2809 return cur_bit;
2810 }
2811
2812 static inline u8 bnx2x_mcast_get_rx_tx_flag(struct bnx2x_mcast_obj *o)
2813 {
2814 struct bnx2x_raw_obj *raw = &o->raw;
2815 u8 rx_tx_flag = 0;
2816
2817 if ((raw->obj_type == BNX2X_OBJ_TYPE_TX) ||
2818 (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
2819 rx_tx_flag |= ETH_MULTICAST_RULES_CMD_TX_CMD;
2820
2821 if ((raw->obj_type == BNX2X_OBJ_TYPE_RX) ||
2822 (raw->obj_type == BNX2X_OBJ_TYPE_RX_TX))
2823 rx_tx_flag |= ETH_MULTICAST_RULES_CMD_RX_CMD;
2824
2825 return rx_tx_flag;
2826 }
2827
2828 static void bnx2x_mcast_set_one_rule_e2(struct bnx2x *bp,
2829 struct bnx2x_mcast_obj *o, int idx,
2830 union bnx2x_mcast_config_data *cfg_data,
2831 enum bnx2x_mcast_cmd cmd)
2832 {
2833 struct bnx2x_raw_obj *r = &o->raw;
2834 struct eth_multicast_rules_ramrod_data *data =
2835 (struct eth_multicast_rules_ramrod_data *)(r->rdata);
2836 u8 func_id = r->func_id;
2837 u8 rx_tx_add_flag = bnx2x_mcast_get_rx_tx_flag(o);
2838 int bin;
2839
2840 if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE) ||
2841 (cmd == BNX2X_MCAST_CMD_SET_ADD))
2842 rx_tx_add_flag |= ETH_MULTICAST_RULES_CMD_IS_ADD;
2843
2844 data->rules[idx].cmd_general_data |= rx_tx_add_flag;
2845
2846
2847 switch (cmd) {
2848 case BNX2X_MCAST_CMD_ADD:
2849 bin = bnx2x_mcast_bin_from_mac(cfg_data->mac);
2850 BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bin);
2851 break;
2852
2853 case BNX2X_MCAST_CMD_DEL:
2854
2855
2856
2857
2858
2859
2860 bin = bnx2x_mcast_clear_first_bin(o);
2861 break;
2862
2863 case BNX2X_MCAST_CMD_RESTORE:
2864 bin = cfg_data->bin;
2865 break;
2866
2867 case BNX2X_MCAST_CMD_SET_ADD:
2868 bin = cfg_data->bin;
2869 BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bin);
2870 break;
2871
2872 case BNX2X_MCAST_CMD_SET_DEL:
2873 bin = cfg_data->bin;
2874 BIT_VEC64_CLEAR_BIT(o->registry.aprox_match.vec, bin);
2875 break;
2876
2877 default:
2878 BNX2X_ERR("Unknown command: %d\n", cmd);
2879 return;
2880 }
2881
2882 DP(BNX2X_MSG_SP, "%s bin %d\n",
2883 ((rx_tx_add_flag & ETH_MULTICAST_RULES_CMD_IS_ADD) ?
2884 "Setting" : "Clearing"), bin);
2885
2886 data->rules[idx].bin_id = (u8)bin;
2887 data->rules[idx].func_id = func_id;
2888 data->rules[idx].engine_id = o->engine_id;
2889 }
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901 static inline int bnx2x_mcast_handle_restore_cmd_e2(
2902 struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_bin,
2903 int *rdata_idx)
2904 {
2905 int cur_bin, cnt = *rdata_idx;
2906 union bnx2x_mcast_config_data cfg_data = {NULL};
2907
2908
2909 for (cur_bin = bnx2x_mcast_get_next_bin(o, start_bin); cur_bin >= 0;
2910 cur_bin = bnx2x_mcast_get_next_bin(o, cur_bin + 1)) {
2911
2912 cfg_data.bin = (u8)cur_bin;
2913 o->set_one_rule(bp, o, cnt, &cfg_data,
2914 BNX2X_MCAST_CMD_RESTORE);
2915
2916 cnt++;
2917
2918 DP(BNX2X_MSG_SP, "About to configure a bin %d\n", cur_bin);
2919
2920
2921
2922
2923 if (cnt >= o->max_cmd_len)
2924 break;
2925 }
2926
2927 *rdata_idx = cnt;
2928
2929 return cur_bin;
2930 }
2931
2932 static inline void bnx2x_mcast_hdl_pending_add_e2(struct bnx2x *bp,
2933 struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos,
2934 int *line_idx)
2935 {
2936 struct bnx2x_mcast_mac_elem *pmac_pos, *pmac_pos_n;
2937 int cnt = *line_idx;
2938 union bnx2x_mcast_config_data cfg_data = {NULL};
2939
2940 list_for_each_entry_safe(pmac_pos, pmac_pos_n, &cmd_pos->data.macs_head,
2941 link) {
2942
2943 cfg_data.mac = &pmac_pos->mac[0];
2944 o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type);
2945
2946 cnt++;
2947
2948 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
2949 pmac_pos->mac);
2950
2951 list_del(&pmac_pos->link);
2952
2953
2954
2955
2956 if (cnt >= o->max_cmd_len)
2957 break;
2958 }
2959
2960 *line_idx = cnt;
2961
2962
2963 if (list_empty(&cmd_pos->data.macs_head))
2964 cmd_pos->done = true;
2965 }
2966
2967 static inline void bnx2x_mcast_hdl_pending_del_e2(struct bnx2x *bp,
2968 struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos,
2969 int *line_idx)
2970 {
2971 int cnt = *line_idx;
2972
2973 while (cmd_pos->data.macs_num) {
2974 o->set_one_rule(bp, o, cnt, NULL, cmd_pos->type);
2975
2976 cnt++;
2977
2978 cmd_pos->data.macs_num--;
2979
2980 DP(BNX2X_MSG_SP, "Deleting MAC. %d left,cnt is %d\n",
2981 cmd_pos->data.macs_num, cnt);
2982
2983
2984
2985
2986 if (cnt >= o->max_cmd_len)
2987 break;
2988 }
2989
2990 *line_idx = cnt;
2991
2992
2993 if (!cmd_pos->data.macs_num)
2994 cmd_pos->done = true;
2995 }
2996
2997 static inline void bnx2x_mcast_hdl_pending_restore_e2(struct bnx2x *bp,
2998 struct bnx2x_mcast_obj *o, struct bnx2x_pending_mcast_cmd *cmd_pos,
2999 int *line_idx)
3000 {
3001 cmd_pos->data.next_bin = o->hdl_restore(bp, o, cmd_pos->data.next_bin,
3002 line_idx);
3003
3004 if (cmd_pos->data.next_bin < 0)
3005
3006 cmd_pos->done = true;
3007 else
3008
3009 cmd_pos->data.next_bin++;
3010 }
3011
3012 static void
3013 bnx2x_mcast_hdl_pending_set_e2_convert(struct bnx2x *bp,
3014 struct bnx2x_mcast_obj *o,
3015 struct bnx2x_pending_mcast_cmd *cmd_pos)
3016 {
3017 u64 cur[BNX2X_MCAST_VEC_SZ], req[BNX2X_MCAST_VEC_SZ];
3018 struct bnx2x_mcast_mac_elem *pmac_pos, *pmac_pos_n;
3019 struct bnx2x_mcast_bin_elem *p_item;
3020 struct bnx2x_mcast_elem_group *elem_group;
3021 int cnt = 0, mac_cnt = 0, offset = 0, i;
3022
3023 memset(req, 0, sizeof(u64) * BNX2X_MCAST_VEC_SZ);
3024 memcpy(cur, o->registry.aprox_match.vec,
3025 sizeof(u64) * BNX2X_MCAST_VEC_SZ);
3026
3027
3028 list_for_each_entry_safe(pmac_pos, pmac_pos_n, &cmd_pos->data.macs_head,
3029 link) {
3030 int bin = bnx2x_mcast_bin_from_mac(pmac_pos->mac);
3031
3032 DP(BNX2X_MSG_SP, "Set contains %pM mcast MAC\n",
3033 pmac_pos->mac);
3034
3035 BIT_VEC64_SET_BIT(req, bin);
3036 list_del(&pmac_pos->link);
3037 mac_cnt++;
3038 }
3039
3040
3041
3042
3043 cmd_pos->set_convert = true;
3044 INIT_LIST_HEAD(&cmd_pos->data.macs_head);
3045 elem_group = list_first_entry(&cmd_pos->group_head,
3046 struct bnx2x_mcast_elem_group,
3047 mcast_group_link);
3048 for (i = 0; i < BNX2X_MCAST_BINS_NUM; i++) {
3049 bool b_current = !!BIT_VEC64_TEST_BIT(cur, i);
3050 bool b_required = !!BIT_VEC64_TEST_BIT(req, i);
3051
3052 if (b_current == b_required)
3053 continue;
3054
3055 p_item = &elem_group->mcast_elems[offset].bin_elem;
3056 p_item->bin = i;
3057 p_item->type = b_required ? BNX2X_MCAST_CMD_SET_ADD
3058 : BNX2X_MCAST_CMD_SET_DEL;
3059 list_add_tail(&p_item->link , &cmd_pos->data.macs_head);
3060 cnt++;
3061 offset++;
3062 if (offset == MCAST_MAC_ELEMS_PER_PG) {
3063 offset = 0;
3064 elem_group = list_next_entry(elem_group,
3065 mcast_group_link);
3066 }
3067 }
3068
3069
3070
3071
3072
3073 o->total_pending_num -= (o->max_cmd_len + mac_cnt);
3074 o->total_pending_num += cnt;
3075
3076 DP(BNX2X_MSG_SP, "o->total_pending_num=%d\n", o->total_pending_num);
3077 }
3078
3079 static void
3080 bnx2x_mcast_hdl_pending_set_e2(struct bnx2x *bp,
3081 struct bnx2x_mcast_obj *o,
3082 struct bnx2x_pending_mcast_cmd *cmd_pos,
3083 int *cnt)
3084 {
3085 union bnx2x_mcast_config_data cfg_data = {NULL};
3086 struct bnx2x_mcast_bin_elem *p_item, *p_item_n;
3087
3088
3089
3090
3091
3092
3093
3094
3095 if (!cmd_pos->set_convert)
3096 bnx2x_mcast_hdl_pending_set_e2_convert(bp, o, cmd_pos);
3097
3098 list_for_each_entry_safe(p_item, p_item_n, &cmd_pos->data.macs_head,
3099 link) {
3100 cfg_data.bin = (u8)p_item->bin;
3101 o->set_one_rule(bp, o, *cnt, &cfg_data, p_item->type);
3102 (*cnt)++;
3103
3104 list_del(&p_item->link);
3105
3106
3107 if (*cnt >= o->max_cmd_len)
3108 break;
3109 }
3110
3111
3112 if (list_empty(&cmd_pos->data.macs_head))
3113 cmd_pos->done = true;
3114 }
3115
3116 static inline int bnx2x_mcast_handle_pending_cmds_e2(struct bnx2x *bp,
3117 struct bnx2x_mcast_ramrod_params *p)
3118 {
3119 struct bnx2x_pending_mcast_cmd *cmd_pos, *cmd_pos_n;
3120 int cnt = 0;
3121 struct bnx2x_mcast_obj *o = p->mcast_obj;
3122
3123 list_for_each_entry_safe(cmd_pos, cmd_pos_n, &o->pending_cmds_head,
3124 link) {
3125 switch (cmd_pos->type) {
3126 case BNX2X_MCAST_CMD_ADD:
3127 bnx2x_mcast_hdl_pending_add_e2(bp, o, cmd_pos, &cnt);
3128 break;
3129
3130 case BNX2X_MCAST_CMD_DEL:
3131 bnx2x_mcast_hdl_pending_del_e2(bp, o, cmd_pos, &cnt);
3132 break;
3133
3134 case BNX2X_MCAST_CMD_RESTORE:
3135 bnx2x_mcast_hdl_pending_restore_e2(bp, o, cmd_pos,
3136 &cnt);
3137 break;
3138
3139 case BNX2X_MCAST_CMD_SET:
3140 bnx2x_mcast_hdl_pending_set_e2(bp, o, cmd_pos, &cnt);
3141 break;
3142
3143 default:
3144 BNX2X_ERR("Unknown command: %d\n", cmd_pos->type);
3145 return -EINVAL;
3146 }
3147
3148
3149
3150
3151 if (cmd_pos->done) {
3152 list_del(&cmd_pos->link);
3153 bnx2x_free_groups(&cmd_pos->group_head);
3154 kfree(cmd_pos);
3155 }
3156
3157
3158 if (cnt >= o->max_cmd_len)
3159 break;
3160 }
3161
3162 return cnt;
3163 }
3164
3165 static inline void bnx2x_mcast_hdl_add(struct bnx2x *bp,
3166 struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p,
3167 int *line_idx)
3168 {
3169 struct bnx2x_mcast_list_elem *mlist_pos;
3170 union bnx2x_mcast_config_data cfg_data = {NULL};
3171 int cnt = *line_idx;
3172
3173 list_for_each_entry(mlist_pos, &p->mcast_list, link) {
3174 cfg_data.mac = mlist_pos->mac;
3175 o->set_one_rule(bp, o, cnt, &cfg_data, BNX2X_MCAST_CMD_ADD);
3176
3177 cnt++;
3178
3179 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
3180 mlist_pos->mac);
3181 }
3182
3183 *line_idx = cnt;
3184 }
3185
3186 static inline void bnx2x_mcast_hdl_del(struct bnx2x *bp,
3187 struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p,
3188 int *line_idx)
3189 {
3190 int cnt = *line_idx, i;
3191
3192 for (i = 0; i < p->mcast_list_len; i++) {
3193 o->set_one_rule(bp, o, cnt, NULL, BNX2X_MCAST_CMD_DEL);
3194
3195 cnt++;
3196
3197 DP(BNX2X_MSG_SP, "Deleting MAC. %d left\n",
3198 p->mcast_list_len - i - 1);
3199 }
3200
3201 *line_idx = cnt;
3202 }
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216 static inline int bnx2x_mcast_handle_current_cmd(struct bnx2x *bp,
3217 struct bnx2x_mcast_ramrod_params *p,
3218 enum bnx2x_mcast_cmd cmd,
3219 int start_cnt)
3220 {
3221 struct bnx2x_mcast_obj *o = p->mcast_obj;
3222 int cnt = start_cnt;
3223
3224 DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len);
3225
3226 switch (cmd) {
3227 case BNX2X_MCAST_CMD_ADD:
3228 bnx2x_mcast_hdl_add(bp, o, p, &cnt);
3229 break;
3230
3231 case BNX2X_MCAST_CMD_DEL:
3232 bnx2x_mcast_hdl_del(bp, o, p, &cnt);
3233 break;
3234
3235 case BNX2X_MCAST_CMD_RESTORE:
3236 o->hdl_restore(bp, o, 0, &cnt);
3237 break;
3238
3239 default:
3240 BNX2X_ERR("Unknown command: %d\n", cmd);
3241 return -EINVAL;
3242 }
3243
3244
3245 p->mcast_list_len = 0;
3246
3247 return cnt;
3248 }
3249
3250 static int bnx2x_mcast_validate_e2(struct bnx2x *bp,
3251 struct bnx2x_mcast_ramrod_params *p,
3252 enum bnx2x_mcast_cmd cmd)
3253 {
3254 struct bnx2x_mcast_obj *o = p->mcast_obj;
3255 int reg_sz = o->get_registry_size(o);
3256
3257 switch (cmd) {
3258
3259 case BNX2X_MCAST_CMD_DEL:
3260 o->set_registry_size(o, 0);
3261
3262
3263
3264 case BNX2X_MCAST_CMD_RESTORE:
3265
3266
3267
3268
3269
3270
3271
3272 p->mcast_list_len = reg_sz;
3273 break;
3274
3275 case BNX2X_MCAST_CMD_ADD:
3276 case BNX2X_MCAST_CMD_CONT:
3277
3278
3279
3280
3281 o->set_registry_size(o, reg_sz + p->mcast_list_len);
3282 break;
3283
3284 case BNX2X_MCAST_CMD_SET:
3285
3286
3287
3288
3289
3290
3291
3292
3293 o->set_registry_size(o, reg_sz + p->mcast_list_len);
3294 o->total_pending_num += o->max_cmd_len;
3295 break;
3296
3297 default:
3298 BNX2X_ERR("Unknown command: %d\n", cmd);
3299 return -EINVAL;
3300 }
3301
3302
3303 o->total_pending_num += p->mcast_list_len;
3304
3305 return 0;
3306 }
3307
3308 static void bnx2x_mcast_revert_e2(struct bnx2x *bp,
3309 struct bnx2x_mcast_ramrod_params *p,
3310 int old_num_bins,
3311 enum bnx2x_mcast_cmd cmd)
3312 {
3313 struct bnx2x_mcast_obj *o = p->mcast_obj;
3314
3315 o->set_registry_size(o, old_num_bins);
3316 o->total_pending_num -= p->mcast_list_len;
3317
3318 if (cmd == BNX2X_MCAST_CMD_SET)
3319 o->total_pending_num -= o->max_cmd_len;
3320 }
3321
3322
3323
3324
3325
3326
3327
3328
3329 static inline void bnx2x_mcast_set_rdata_hdr_e2(struct bnx2x *bp,
3330 struct bnx2x_mcast_ramrod_params *p,
3331 u8 len)
3332 {
3333 struct bnx2x_raw_obj *r = &p->mcast_obj->raw;
3334 struct eth_multicast_rules_ramrod_data *data =
3335 (struct eth_multicast_rules_ramrod_data *)(r->rdata);
3336
3337 data->header.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
3338 (BNX2X_FILTER_MCAST_PENDING <<
3339 BNX2X_SWCID_SHIFT));
3340 data->header.rule_cnt = len;
3341 }
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354 static inline int bnx2x_mcast_refresh_registry_e2(struct bnx2x *bp,
3355 struct bnx2x_mcast_obj *o)
3356 {
3357 int i, cnt = 0;
3358 u64 elem;
3359
3360 for (i = 0; i < BNX2X_MCAST_VEC_SZ; i++) {
3361 elem = o->registry.aprox_match.vec[i];
3362 for (; elem; cnt++)
3363 elem &= elem - 1;
3364 }
3365
3366 o->set_registry_size(o, cnt);
3367
3368 return 0;
3369 }
3370
3371 static int bnx2x_mcast_setup_e2(struct bnx2x *bp,
3372 struct bnx2x_mcast_ramrod_params *p,
3373 enum bnx2x_mcast_cmd cmd)
3374 {
3375 struct bnx2x_raw_obj *raw = &p->mcast_obj->raw;
3376 struct bnx2x_mcast_obj *o = p->mcast_obj;
3377 struct eth_multicast_rules_ramrod_data *data =
3378 (struct eth_multicast_rules_ramrod_data *)(raw->rdata);
3379 int cnt = 0, rc;
3380
3381
3382 memset(data, 0, sizeof(*data));
3383
3384 cnt = bnx2x_mcast_handle_pending_cmds_e2(bp, p);
3385
3386
3387 if (list_empty(&o->pending_cmds_head))
3388 o->clear_sched(o);
3389
3390
3391
3392
3393
3394
3395
3396 if (p->mcast_list_len > 0)
3397 cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, cnt);
3398
3399
3400
3401
3402 o->total_pending_num -= cnt;
3403
3404
3405 WARN_ON(o->total_pending_num < 0);
3406 WARN_ON(cnt > o->max_cmd_len);
3407
3408 bnx2x_mcast_set_rdata_hdr_e2(bp, p, (u8)cnt);
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425 if (!o->total_pending_num)
3426 bnx2x_mcast_refresh_registry_e2(bp, o);
3427
3428
3429
3430
3431
3432
3433 if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags) || !cnt) {
3434 raw->clear_pending(raw);
3435 return 0;
3436 } else {
3437
3438
3439
3440
3441
3442
3443
3444
3445 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_MULTICAST_RULES,
3446 raw->cid, U64_HI(raw->rdata_mapping),
3447 U64_LO(raw->rdata_mapping),
3448 ETH_CONNECTION_TYPE);
3449 if (rc)
3450 return rc;
3451
3452
3453 return 1;
3454 }
3455 }
3456
3457 static int bnx2x_mcast_validate_e1h(struct bnx2x *bp,
3458 struct bnx2x_mcast_ramrod_params *p,
3459 enum bnx2x_mcast_cmd cmd)
3460 {
3461 if (cmd == BNX2X_MCAST_CMD_SET) {
3462 BNX2X_ERR("Can't use `set' command on e1h!\n");
3463 return -EINVAL;
3464 }
3465
3466
3467 if ((cmd == BNX2X_MCAST_CMD_DEL) || (cmd == BNX2X_MCAST_CMD_RESTORE))
3468 p->mcast_list_len = 1;
3469
3470 return 0;
3471 }
3472
3473 static void bnx2x_mcast_revert_e1h(struct bnx2x *bp,
3474 struct bnx2x_mcast_ramrod_params *p,
3475 int old_num_bins,
3476 enum bnx2x_mcast_cmd cmd)
3477 {
3478
3479 }
3480
3481 #define BNX2X_57711_SET_MC_FILTER(filter, bit) \
3482 do { \
3483 (filter)[(bit) >> 5] |= (1 << ((bit) & 0x1f)); \
3484 } while (0)
3485
3486 static inline void bnx2x_mcast_hdl_add_e1h(struct bnx2x *bp,
3487 struct bnx2x_mcast_obj *o,
3488 struct bnx2x_mcast_ramrod_params *p,
3489 u32 *mc_filter)
3490 {
3491 struct bnx2x_mcast_list_elem *mlist_pos;
3492 int bit;
3493
3494 list_for_each_entry(mlist_pos, &p->mcast_list, link) {
3495 bit = bnx2x_mcast_bin_from_mac(mlist_pos->mac);
3496 BNX2X_57711_SET_MC_FILTER(mc_filter, bit);
3497
3498 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC, bin %d\n",
3499 mlist_pos->mac, bit);
3500
3501
3502 BIT_VEC64_SET_BIT(o->registry.aprox_match.vec,
3503 bit);
3504 }
3505 }
3506
3507 static inline void bnx2x_mcast_hdl_restore_e1h(struct bnx2x *bp,
3508 struct bnx2x_mcast_obj *o, struct bnx2x_mcast_ramrod_params *p,
3509 u32 *mc_filter)
3510 {
3511 int bit;
3512
3513 for (bit = bnx2x_mcast_get_next_bin(o, 0);
3514 bit >= 0;
3515 bit = bnx2x_mcast_get_next_bin(o, bit + 1)) {
3516 BNX2X_57711_SET_MC_FILTER(mc_filter, bit);
3517 DP(BNX2X_MSG_SP, "About to set bin %d\n", bit);
3518 }
3519 }
3520
3521
3522
3523
3524
3525 static int bnx2x_mcast_setup_e1h(struct bnx2x *bp,
3526 struct bnx2x_mcast_ramrod_params *p,
3527 enum bnx2x_mcast_cmd cmd)
3528 {
3529 int i;
3530 struct bnx2x_mcast_obj *o = p->mcast_obj;
3531 struct bnx2x_raw_obj *r = &o->raw;
3532
3533
3534
3535
3536 if (!test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3537 u32 mc_filter[MC_HASH_SIZE] = {0};
3538
3539
3540
3541
3542 switch (cmd) {
3543 case BNX2X_MCAST_CMD_ADD:
3544 bnx2x_mcast_hdl_add_e1h(bp, o, p, mc_filter);
3545 break;
3546
3547 case BNX2X_MCAST_CMD_DEL:
3548 DP(BNX2X_MSG_SP,
3549 "Invalidating multicast MACs configuration\n");
3550
3551
3552 memset(o->registry.aprox_match.vec, 0,
3553 sizeof(o->registry.aprox_match.vec));
3554 break;
3555
3556 case BNX2X_MCAST_CMD_RESTORE:
3557 bnx2x_mcast_hdl_restore_e1h(bp, o, p, mc_filter);
3558 break;
3559
3560 default:
3561 BNX2X_ERR("Unknown command: %d\n", cmd);
3562 return -EINVAL;
3563 }
3564
3565
3566 for (i = 0; i < MC_HASH_SIZE; i++)
3567 REG_WR(bp, MC_HASH_OFFSET(bp, i), mc_filter[i]);
3568 } else
3569
3570 memset(o->registry.aprox_match.vec, 0,
3571 sizeof(o->registry.aprox_match.vec));
3572
3573
3574 r->clear_pending(r);
3575
3576 return 0;
3577 }
3578
3579 static int bnx2x_mcast_validate_e1(struct bnx2x *bp,
3580 struct bnx2x_mcast_ramrod_params *p,
3581 enum bnx2x_mcast_cmd cmd)
3582 {
3583 struct bnx2x_mcast_obj *o = p->mcast_obj;
3584 int reg_sz = o->get_registry_size(o);
3585
3586 if (cmd == BNX2X_MCAST_CMD_SET) {
3587 BNX2X_ERR("Can't use `set' command on e1!\n");
3588 return -EINVAL;
3589 }
3590
3591 switch (cmd) {
3592
3593 case BNX2X_MCAST_CMD_DEL:
3594 o->set_registry_size(o, 0);
3595
3596
3597
3598 case BNX2X_MCAST_CMD_RESTORE:
3599 p->mcast_list_len = reg_sz;
3600 DP(BNX2X_MSG_SP, "Command %d, p->mcast_list_len=%d\n",
3601 cmd, p->mcast_list_len);
3602 break;
3603
3604 case BNX2X_MCAST_CMD_ADD:
3605 case BNX2X_MCAST_CMD_CONT:
3606
3607
3608
3609
3610 if (p->mcast_list_len > o->max_cmd_len) {
3611 BNX2X_ERR("Can't configure more than %d multicast MACs on 57710\n",
3612 o->max_cmd_len);
3613 return -EINVAL;
3614 }
3615
3616
3617
3618
3619 DP(BNX2X_MSG_SP, "p->mcast_list_len=%d\n", p->mcast_list_len);
3620 if (p->mcast_list_len > 0)
3621 o->set_registry_size(o, p->mcast_list_len);
3622
3623 break;
3624
3625 default:
3626 BNX2X_ERR("Unknown command: %d\n", cmd);
3627 return -EINVAL;
3628 }
3629
3630
3631
3632
3633 if (p->mcast_list_len)
3634 o->total_pending_num += o->max_cmd_len;
3635
3636 return 0;
3637 }
3638
3639 static void bnx2x_mcast_revert_e1(struct bnx2x *bp,
3640 struct bnx2x_mcast_ramrod_params *p,
3641 int old_num_macs,
3642 enum bnx2x_mcast_cmd cmd)
3643 {
3644 struct bnx2x_mcast_obj *o = p->mcast_obj;
3645
3646 o->set_registry_size(o, old_num_macs);
3647
3648
3649
3650
3651
3652 if (p->mcast_list_len)
3653 o->total_pending_num -= o->max_cmd_len;
3654 }
3655
3656 static void bnx2x_mcast_set_one_rule_e1(struct bnx2x *bp,
3657 struct bnx2x_mcast_obj *o, int idx,
3658 union bnx2x_mcast_config_data *cfg_data,
3659 enum bnx2x_mcast_cmd cmd)
3660 {
3661 struct bnx2x_raw_obj *r = &o->raw;
3662 struct mac_configuration_cmd *data =
3663 (struct mac_configuration_cmd *)(r->rdata);
3664
3665
3666 if ((cmd == BNX2X_MCAST_CMD_ADD) || (cmd == BNX2X_MCAST_CMD_RESTORE)) {
3667 bnx2x_set_fw_mac_addr(&data->config_table[idx].msb_mac_addr,
3668 &data->config_table[idx].middle_mac_addr,
3669 &data->config_table[idx].lsb_mac_addr,
3670 cfg_data->mac);
3671
3672 data->config_table[idx].vlan_id = 0;
3673 data->config_table[idx].pf_id = r->func_id;
3674 data->config_table[idx].clients_bit_vector =
3675 cpu_to_le32(1 << r->cl_id);
3676
3677 SET_FLAG(data->config_table[idx].flags,
3678 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
3679 T_ETH_MAC_COMMAND_SET);
3680 }
3681 }
3682
3683
3684
3685
3686
3687
3688
3689
3690 static inline void bnx2x_mcast_set_rdata_hdr_e1(struct bnx2x *bp,
3691 struct bnx2x_mcast_ramrod_params *p,
3692 u8 len)
3693 {
3694 struct bnx2x_raw_obj *r = &p->mcast_obj->raw;
3695 struct mac_configuration_cmd *data =
3696 (struct mac_configuration_cmd *)(r->rdata);
3697
3698 u8 offset = (CHIP_REV_IS_SLOW(bp) ?
3699 BNX2X_MAX_EMUL_MULTI*(1 + r->func_id) :
3700 BNX2X_MAX_MULTICAST*(1 + r->func_id));
3701
3702 data->hdr.offset = offset;
3703 data->hdr.client_id = cpu_to_le16(0xff);
3704 data->hdr.echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
3705 (BNX2X_FILTER_MCAST_PENDING <<
3706 BNX2X_SWCID_SHIFT));
3707 data->hdr.length = len;
3708 }
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723 static inline int bnx2x_mcast_handle_restore_cmd_e1(
3724 struct bnx2x *bp, struct bnx2x_mcast_obj *o , int start_idx,
3725 int *rdata_idx)
3726 {
3727 struct bnx2x_mcast_mac_elem *elem;
3728 int i = 0;
3729 union bnx2x_mcast_config_data cfg_data = {NULL};
3730
3731
3732 list_for_each_entry(elem, &o->registry.exact_match.macs, link) {
3733 cfg_data.mac = &elem->mac[0];
3734 o->set_one_rule(bp, o, i, &cfg_data, BNX2X_MCAST_CMD_RESTORE);
3735
3736 i++;
3737
3738 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
3739 cfg_data.mac);
3740 }
3741
3742 *rdata_idx = i;
3743
3744 return -1;
3745 }
3746
3747 static inline int bnx2x_mcast_handle_pending_cmds_e1(
3748 struct bnx2x *bp, struct bnx2x_mcast_ramrod_params *p)
3749 {
3750 struct bnx2x_pending_mcast_cmd *cmd_pos;
3751 struct bnx2x_mcast_mac_elem *pmac_pos;
3752 struct bnx2x_mcast_obj *o = p->mcast_obj;
3753 union bnx2x_mcast_config_data cfg_data = {NULL};
3754 int cnt = 0;
3755
3756
3757 if (list_empty(&o->pending_cmds_head))
3758 return 0;
3759
3760
3761 cmd_pos = list_first_entry(&o->pending_cmds_head,
3762 struct bnx2x_pending_mcast_cmd, link);
3763
3764 switch (cmd_pos->type) {
3765 case BNX2X_MCAST_CMD_ADD:
3766 list_for_each_entry(pmac_pos, &cmd_pos->data.macs_head, link) {
3767 cfg_data.mac = &pmac_pos->mac[0];
3768 o->set_one_rule(bp, o, cnt, &cfg_data, cmd_pos->type);
3769
3770 cnt++;
3771
3772 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
3773 pmac_pos->mac);
3774 }
3775 break;
3776
3777 case BNX2X_MCAST_CMD_DEL:
3778 cnt = cmd_pos->data.macs_num;
3779 DP(BNX2X_MSG_SP, "About to delete %d multicast MACs\n", cnt);
3780 break;
3781
3782 case BNX2X_MCAST_CMD_RESTORE:
3783 o->hdl_restore(bp, o, 0, &cnt);
3784 break;
3785
3786 default:
3787 BNX2X_ERR("Unknown command: %d\n", cmd_pos->type);
3788 return -EINVAL;
3789 }
3790
3791 list_del(&cmd_pos->link);
3792 bnx2x_free_groups(&cmd_pos->group_head);
3793 kfree(cmd_pos);
3794
3795 return cnt;
3796 }
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806 static inline void bnx2x_get_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
3807 __le16 *fw_lo, u8 *mac)
3808 {
3809 mac[1] = ((u8 *)fw_hi)[0];
3810 mac[0] = ((u8 *)fw_hi)[1];
3811 mac[3] = ((u8 *)fw_mid)[0];
3812 mac[2] = ((u8 *)fw_mid)[1];
3813 mac[5] = ((u8 *)fw_lo)[0];
3814 mac[4] = ((u8 *)fw_lo)[1];
3815 }
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828 static inline int bnx2x_mcast_refresh_registry_e1(struct bnx2x *bp,
3829 struct bnx2x_mcast_obj *o)
3830 {
3831 struct bnx2x_raw_obj *raw = &o->raw;
3832 struct bnx2x_mcast_mac_elem *elem;
3833 struct mac_configuration_cmd *data =
3834 (struct mac_configuration_cmd *)(raw->rdata);
3835
3836
3837
3838
3839 if (GET_FLAG(data->config_table[0].flags,
3840 MAC_CONFIGURATION_ENTRY_ACTION_TYPE)) {
3841 int i, len = data->hdr.length;
3842
3843
3844 if (!list_empty(&o->registry.exact_match.macs))
3845 return 0;
3846
3847 elem = kcalloc(len, sizeof(*elem), GFP_ATOMIC);
3848 if (!elem) {
3849 BNX2X_ERR("Failed to allocate registry memory\n");
3850 return -ENOMEM;
3851 }
3852
3853 for (i = 0; i < len; i++, elem++) {
3854 bnx2x_get_fw_mac_addr(
3855 &data->config_table[i].msb_mac_addr,
3856 &data->config_table[i].middle_mac_addr,
3857 &data->config_table[i].lsb_mac_addr,
3858 elem->mac);
3859 DP(BNX2X_MSG_SP, "Adding registry entry for [%pM]\n",
3860 elem->mac);
3861 list_add_tail(&elem->link,
3862 &o->registry.exact_match.macs);
3863 }
3864 } else {
3865 elem = list_first_entry(&o->registry.exact_match.macs,
3866 struct bnx2x_mcast_mac_elem, link);
3867 DP(BNX2X_MSG_SP, "Deleting a registry\n");
3868 kfree(elem);
3869 INIT_LIST_HEAD(&o->registry.exact_match.macs);
3870 }
3871
3872 return 0;
3873 }
3874
3875 static int bnx2x_mcast_setup_e1(struct bnx2x *bp,
3876 struct bnx2x_mcast_ramrod_params *p,
3877 enum bnx2x_mcast_cmd cmd)
3878 {
3879 struct bnx2x_mcast_obj *o = p->mcast_obj;
3880 struct bnx2x_raw_obj *raw = &o->raw;
3881 struct mac_configuration_cmd *data =
3882 (struct mac_configuration_cmd *)(raw->rdata);
3883 int cnt = 0, i, rc;
3884
3885
3886 memset(data, 0, sizeof(*data));
3887
3888
3889 for (i = 0; i < o->max_cmd_len ; i++)
3890 SET_FLAG(data->config_table[i].flags,
3891 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
3892 T_ETH_MAC_COMMAND_INVALIDATE);
3893
3894
3895 cnt = bnx2x_mcast_handle_pending_cmds_e1(bp, p);
3896
3897
3898 if (list_empty(&o->pending_cmds_head))
3899 o->clear_sched(o);
3900
3901
3902 if (!cnt)
3903 cnt = bnx2x_mcast_handle_current_cmd(bp, p, cmd, 0);
3904
3905
3906
3907
3908 o->total_pending_num -= o->max_cmd_len;
3909
3910
3911
3912 WARN_ON(cnt > o->max_cmd_len);
3913
3914
3915 bnx2x_mcast_set_rdata_hdr_e1(bp, p, (u8)cnt);
3916
3917
3918
3919
3920
3921
3922
3923 rc = bnx2x_mcast_refresh_registry_e1(bp, o);
3924 if (rc)
3925 return rc;
3926
3927
3928
3929
3930 if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3931 raw->clear_pending(raw);
3932 return 0;
3933 } else {
3934
3935
3936
3937
3938
3939
3940
3941
3942 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, raw->cid,
3943 U64_HI(raw->rdata_mapping),
3944 U64_LO(raw->rdata_mapping),
3945 ETH_CONNECTION_TYPE);
3946 if (rc)
3947 return rc;
3948
3949
3950 return 1;
3951 }
3952 }
3953
3954 static int bnx2x_mcast_get_registry_size_exact(struct bnx2x_mcast_obj *o)
3955 {
3956 return o->registry.exact_match.num_macs_set;
3957 }
3958
3959 static int bnx2x_mcast_get_registry_size_aprox(struct bnx2x_mcast_obj *o)
3960 {
3961 return o->registry.aprox_match.num_bins_set;
3962 }
3963
3964 static void bnx2x_mcast_set_registry_size_exact(struct bnx2x_mcast_obj *o,
3965 int n)
3966 {
3967 o->registry.exact_match.num_macs_set = n;
3968 }
3969
3970 static void bnx2x_mcast_set_registry_size_aprox(struct bnx2x_mcast_obj *o,
3971 int n)
3972 {
3973 o->registry.aprox_match.num_bins_set = n;
3974 }
3975
3976 int bnx2x_config_mcast(struct bnx2x *bp,
3977 struct bnx2x_mcast_ramrod_params *p,
3978 enum bnx2x_mcast_cmd cmd)
3979 {
3980 struct bnx2x_mcast_obj *o = p->mcast_obj;
3981 struct bnx2x_raw_obj *r = &o->raw;
3982 int rc = 0, old_reg_size;
3983
3984
3985
3986
3987 old_reg_size = o->get_registry_size(o);
3988
3989
3990 rc = o->validate(bp, p, cmd);
3991 if (rc)
3992 return rc;
3993
3994
3995 if ((!p->mcast_list_len) && (!o->check_sched(o)))
3996 return 0;
3997
3998 DP(BNX2X_MSG_SP, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\n",
3999 o->total_pending_num, p->mcast_list_len, o->max_cmd_len);
4000
4001
4002
4003
4004 if (r->check_pending(r) ||
4005 ((o->max_cmd_len > 0) && (o->total_pending_num > o->max_cmd_len))) {
4006 rc = o->enqueue_cmd(bp, p->mcast_obj, p, cmd);
4007 if (rc < 0)
4008 goto error_exit1;
4009
4010
4011
4012
4013 p->mcast_list_len = 0;
4014 }
4015
4016 if (!r->check_pending(r)) {
4017
4018
4019 r->set_pending(r);
4020
4021
4022 rc = o->config_mcast(bp, p, cmd);
4023 if (rc < 0)
4024 goto error_exit2;
4025
4026
4027 if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags))
4028 rc = o->wait_comp(bp, o);
4029 }
4030
4031 return rc;
4032
4033 error_exit2:
4034 r->clear_pending(r);
4035
4036 error_exit1:
4037 o->revert(bp, p, old_reg_size, cmd);
4038
4039 return rc;
4040 }
4041
4042 static void bnx2x_mcast_clear_sched(struct bnx2x_mcast_obj *o)
4043 {
4044 smp_mb__before_atomic();
4045 clear_bit(o->sched_state, o->raw.pstate);
4046 smp_mb__after_atomic();
4047 }
4048
4049 static void bnx2x_mcast_set_sched(struct bnx2x_mcast_obj *o)
4050 {
4051 smp_mb__before_atomic();
4052 set_bit(o->sched_state, o->raw.pstate);
4053 smp_mb__after_atomic();
4054 }
4055
4056 static bool bnx2x_mcast_check_sched(struct bnx2x_mcast_obj *o)
4057 {
4058 return !!test_bit(o->sched_state, o->raw.pstate);
4059 }
4060
4061 static bool bnx2x_mcast_check_pending(struct bnx2x_mcast_obj *o)
4062 {
4063 return o->raw.check_pending(&o->raw) || o->check_sched(o);
4064 }
4065
4066 void bnx2x_init_mcast_obj(struct bnx2x *bp,
4067 struct bnx2x_mcast_obj *mcast_obj,
4068 u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
4069 u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
4070 int state, unsigned long *pstate, bnx2x_obj_type type)
4071 {
4072 memset(mcast_obj, 0, sizeof(*mcast_obj));
4073
4074 bnx2x_init_raw_obj(&mcast_obj->raw, mcast_cl_id, mcast_cid, func_id,
4075 rdata, rdata_mapping, state, pstate, type);
4076
4077 mcast_obj->engine_id = engine_id;
4078
4079 INIT_LIST_HEAD(&mcast_obj->pending_cmds_head);
4080
4081 mcast_obj->sched_state = BNX2X_FILTER_MCAST_SCHED;
4082 mcast_obj->check_sched = bnx2x_mcast_check_sched;
4083 mcast_obj->set_sched = bnx2x_mcast_set_sched;
4084 mcast_obj->clear_sched = bnx2x_mcast_clear_sched;
4085
4086 if (CHIP_IS_E1(bp)) {
4087 mcast_obj->config_mcast = bnx2x_mcast_setup_e1;
4088 mcast_obj->enqueue_cmd = bnx2x_mcast_enqueue_cmd;
4089 mcast_obj->hdl_restore =
4090 bnx2x_mcast_handle_restore_cmd_e1;
4091 mcast_obj->check_pending = bnx2x_mcast_check_pending;
4092
4093 if (CHIP_REV_IS_SLOW(bp))
4094 mcast_obj->max_cmd_len = BNX2X_MAX_EMUL_MULTI;
4095 else
4096 mcast_obj->max_cmd_len = BNX2X_MAX_MULTICAST;
4097
4098 mcast_obj->wait_comp = bnx2x_mcast_wait;
4099 mcast_obj->set_one_rule = bnx2x_mcast_set_one_rule_e1;
4100 mcast_obj->validate = bnx2x_mcast_validate_e1;
4101 mcast_obj->revert = bnx2x_mcast_revert_e1;
4102 mcast_obj->get_registry_size =
4103 bnx2x_mcast_get_registry_size_exact;
4104 mcast_obj->set_registry_size =
4105 bnx2x_mcast_set_registry_size_exact;
4106
4107
4108
4109
4110 INIT_LIST_HEAD(&mcast_obj->registry.exact_match.macs);
4111
4112 } else if (CHIP_IS_E1H(bp)) {
4113 mcast_obj->config_mcast = bnx2x_mcast_setup_e1h;
4114 mcast_obj->enqueue_cmd = NULL;
4115 mcast_obj->hdl_restore = NULL;
4116 mcast_obj->check_pending = bnx2x_mcast_check_pending;
4117
4118
4119
4120
4121 mcast_obj->max_cmd_len = -1;
4122 mcast_obj->wait_comp = bnx2x_mcast_wait;
4123 mcast_obj->set_one_rule = NULL;
4124 mcast_obj->validate = bnx2x_mcast_validate_e1h;
4125 mcast_obj->revert = bnx2x_mcast_revert_e1h;
4126 mcast_obj->get_registry_size =
4127 bnx2x_mcast_get_registry_size_aprox;
4128 mcast_obj->set_registry_size =
4129 bnx2x_mcast_set_registry_size_aprox;
4130 } else {
4131 mcast_obj->config_mcast = bnx2x_mcast_setup_e2;
4132 mcast_obj->enqueue_cmd = bnx2x_mcast_enqueue_cmd;
4133 mcast_obj->hdl_restore =
4134 bnx2x_mcast_handle_restore_cmd_e2;
4135 mcast_obj->check_pending = bnx2x_mcast_check_pending;
4136
4137
4138 mcast_obj->max_cmd_len = 16;
4139 mcast_obj->wait_comp = bnx2x_mcast_wait;
4140 mcast_obj->set_one_rule = bnx2x_mcast_set_one_rule_e2;
4141 mcast_obj->validate = bnx2x_mcast_validate_e2;
4142 mcast_obj->revert = bnx2x_mcast_revert_e2;
4143 mcast_obj->get_registry_size =
4144 bnx2x_mcast_get_registry_size_aprox;
4145 mcast_obj->set_registry_size =
4146 bnx2x_mcast_set_registry_size_aprox;
4147 }
4148 }
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162 static inline bool __atomic_add_ifless(atomic_t *v, int a, int u)
4163 {
4164 int c, old;
4165
4166 c = atomic_read(v);
4167 for (;;) {
4168 if (unlikely(c + a >= u))
4169 return false;
4170
4171 old = atomic_cmpxchg((v), c, c + a);
4172 if (likely(old == c))
4173 break;
4174 c = old;
4175 }
4176
4177 return true;
4178 }
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190 static inline bool __atomic_dec_ifmoe(atomic_t *v, int a, int u)
4191 {
4192 int c, old;
4193
4194 c = atomic_read(v);
4195 for (;;) {
4196 if (unlikely(c - a < u))
4197 return false;
4198
4199 old = atomic_cmpxchg((v), c, c - a);
4200 if (likely(old == c))
4201 break;
4202 c = old;
4203 }
4204
4205 return true;
4206 }
4207
4208 static bool bnx2x_credit_pool_get(struct bnx2x_credit_pool_obj *o, int cnt)
4209 {
4210 bool rc;
4211
4212 smp_mb();
4213 rc = __atomic_dec_ifmoe(&o->credit, cnt, 0);
4214 smp_mb();
4215
4216 return rc;
4217 }
4218
4219 static bool bnx2x_credit_pool_put(struct bnx2x_credit_pool_obj *o, int cnt)
4220 {
4221 bool rc;
4222
4223 smp_mb();
4224
4225
4226 rc = __atomic_add_ifless(&o->credit, cnt, o->pool_sz + 1);
4227
4228 smp_mb();
4229
4230 return rc;
4231 }
4232
4233 static int bnx2x_credit_pool_check(struct bnx2x_credit_pool_obj *o)
4234 {
4235 int cur_credit;
4236
4237 smp_mb();
4238 cur_credit = atomic_read(&o->credit);
4239
4240 return cur_credit;
4241 }
4242
4243 static bool bnx2x_credit_pool_always_true(struct bnx2x_credit_pool_obj *o,
4244 int cnt)
4245 {
4246 return true;
4247 }
4248
4249 static bool bnx2x_credit_pool_get_entry(
4250 struct bnx2x_credit_pool_obj *o,
4251 int *offset)
4252 {
4253 int idx, vec, i;
4254
4255 *offset = -1;
4256
4257
4258 for (vec = 0; vec < BNX2X_POOL_VEC_SIZE; vec++) {
4259
4260
4261 if (!o->pool_mirror[vec])
4262 continue;
4263
4264
4265 for (idx = vec * BIT_VEC64_ELEM_SZ, i = 0;
4266 i < BIT_VEC64_ELEM_SZ; idx++, i++)
4267
4268 if (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) {
4269
4270 BIT_VEC64_CLEAR_BIT(o->pool_mirror, idx);
4271 *offset = o->base_pool_offset + idx;
4272 return true;
4273 }
4274 }
4275
4276 return false;
4277 }
4278
4279 static bool bnx2x_credit_pool_put_entry(
4280 struct bnx2x_credit_pool_obj *o,
4281 int offset)
4282 {
4283 if (offset < o->base_pool_offset)
4284 return false;
4285
4286 offset -= o->base_pool_offset;
4287
4288 if (offset >= o->pool_sz)
4289 return false;
4290
4291
4292 BIT_VEC64_SET_BIT(o->pool_mirror, offset);
4293
4294 return true;
4295 }
4296
4297 static bool bnx2x_credit_pool_put_entry_always_true(
4298 struct bnx2x_credit_pool_obj *o,
4299 int offset)
4300 {
4301 return true;
4302 }
4303
4304 static bool bnx2x_credit_pool_get_entry_always_true(
4305 struct bnx2x_credit_pool_obj *o,
4306 int *offset)
4307 {
4308 *offset = -1;
4309 return true;
4310 }
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322 void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p,
4323 int base, int credit)
4324 {
4325
4326 memset(p, 0, sizeof(*p));
4327
4328
4329 memset(&p->pool_mirror, 0xff, sizeof(p->pool_mirror));
4330
4331
4332 atomic_set(&p->credit, credit);
4333
4334
4335 p->pool_sz = credit;
4336
4337 p->base_pool_offset = base;
4338
4339
4340 smp_mb();
4341
4342 p->check = bnx2x_credit_pool_check;
4343
4344
4345 if (credit >= 0) {
4346 p->put = bnx2x_credit_pool_put;
4347 p->get = bnx2x_credit_pool_get;
4348 p->put_entry = bnx2x_credit_pool_put_entry;
4349 p->get_entry = bnx2x_credit_pool_get_entry;
4350 } else {
4351 p->put = bnx2x_credit_pool_always_true;
4352 p->get = bnx2x_credit_pool_always_true;
4353 p->put_entry = bnx2x_credit_pool_put_entry_always_true;
4354 p->get_entry = bnx2x_credit_pool_get_entry_always_true;
4355 }
4356
4357
4358 if (base < 0) {
4359 p->put_entry = bnx2x_credit_pool_put_entry_always_true;
4360 p->get_entry = bnx2x_credit_pool_get_entry_always_true;
4361 }
4362 }
4363
4364 void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
4365 struct bnx2x_credit_pool_obj *p, u8 func_id,
4366 u8 func_num)
4367 {
4368
4369 #define BNX2X_CAM_SIZE_EMUL 5
4370
4371 int cam_sz;
4372
4373 if (CHIP_IS_E1(bp)) {
4374
4375 if (!CHIP_REV_IS_SLOW(bp))
4376 cam_sz = (MAX_MAC_CREDIT_E1 / 2) - BNX2X_MAX_MULTICAST;
4377 else
4378 cam_sz = BNX2X_CAM_SIZE_EMUL - BNX2X_MAX_EMUL_MULTI;
4379
4380 bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz);
4381
4382 } else if (CHIP_IS_E1H(bp)) {
4383
4384
4385
4386 if ((func_num > 0)) {
4387 if (!CHIP_REV_IS_SLOW(bp))
4388 cam_sz = (MAX_MAC_CREDIT_E1H / (2*func_num));
4389 else
4390 cam_sz = BNX2X_CAM_SIZE_EMUL;
4391 bnx2x_init_credit_pool(p, func_id * cam_sz, cam_sz);
4392 } else {
4393
4394 bnx2x_init_credit_pool(p, 0, 0);
4395 }
4396
4397 } else {
4398
4399
4400
4401
4402 if (func_num > 0) {
4403 if (!CHIP_REV_IS_SLOW(bp))
4404 cam_sz = PF_MAC_CREDIT_E2(bp, func_num);
4405 else
4406 cam_sz = BNX2X_CAM_SIZE_EMUL;
4407
4408
4409
4410
4411 bnx2x_init_credit_pool(p, -1, cam_sz);
4412 } else {
4413
4414 bnx2x_init_credit_pool(p, 0, 0);
4415 }
4416 }
4417 }
4418
4419 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
4420 struct bnx2x_credit_pool_obj *p,
4421 u8 func_id,
4422 u8 func_num)
4423 {
4424 if (CHIP_IS_E1x(bp)) {
4425
4426
4427
4428 bnx2x_init_credit_pool(p, 0, -1);
4429 } else {
4430
4431
4432
4433 if (func_num > 0) {
4434 int credit = PF_VLAN_CREDIT_E2(bp, func_num);
4435
4436 bnx2x_init_credit_pool(p, -1, credit);
4437 } else
4438
4439 bnx2x_init_credit_pool(p, 0, 0);
4440 }
4441 }
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452 static inline void bnx2x_debug_print_ind_table(struct bnx2x *bp,
4453 struct bnx2x_config_rss_params *p)
4454 {
4455 int i;
4456
4457 DP(BNX2X_MSG_SP, "Setting indirection table to:\n");
4458 DP(BNX2X_MSG_SP, "0x0000: ");
4459 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
4460 DP_CONT(BNX2X_MSG_SP, "0x%02x ", p->ind_table[i]);
4461
4462
4463 if ((i + 1 < T_ETH_INDIRECTION_TABLE_SIZE) &&
4464 (((i + 1) & 0x3) == 0)) {
4465 DP_CONT(BNX2X_MSG_SP, "\n");
4466 DP(BNX2X_MSG_SP, "0x%04x: ", i + 1);
4467 }
4468 }
4469
4470 DP_CONT(BNX2X_MSG_SP, "\n");
4471 }
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481 static int bnx2x_setup_rss(struct bnx2x *bp,
4482 struct bnx2x_config_rss_params *p)
4483 {
4484 struct bnx2x_rss_config_obj *o = p->rss_obj;
4485 struct bnx2x_raw_obj *r = &o->raw;
4486 struct eth_rss_update_ramrod_data *data =
4487 (struct eth_rss_update_ramrod_data *)(r->rdata);
4488 u16 caps = 0;
4489 u8 rss_mode = 0;
4490 int rc;
4491
4492 memset(data, 0, sizeof(*data));
4493
4494 DP(BNX2X_MSG_SP, "Configuring RSS\n");
4495
4496
4497 data->echo = cpu_to_le32((r->cid & BNX2X_SWCID_MASK) |
4498 (r->state << BNX2X_SWCID_SHIFT));
4499
4500
4501 if (test_bit(BNX2X_RSS_MODE_DISABLED, &p->rss_flags))
4502 rss_mode = ETH_RSS_MODE_DISABLED;
4503 else if (test_bit(BNX2X_RSS_MODE_REGULAR, &p->rss_flags))
4504 rss_mode = ETH_RSS_MODE_REGULAR;
4505
4506 data->rss_mode = rss_mode;
4507
4508 DP(BNX2X_MSG_SP, "rss_mode=%d\n", rss_mode);
4509
4510
4511 if (test_bit(BNX2X_RSS_IPV4, &p->rss_flags))
4512 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY;
4513
4514 if (test_bit(BNX2X_RSS_IPV4_TCP, &p->rss_flags))
4515 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY;
4516
4517 if (test_bit(BNX2X_RSS_IPV4_UDP, &p->rss_flags))
4518 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY;
4519
4520 if (test_bit(BNX2X_RSS_IPV6, &p->rss_flags))
4521 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY;
4522
4523 if (test_bit(BNX2X_RSS_IPV6_TCP, &p->rss_flags))
4524 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY;
4525
4526 if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags))
4527 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
4528
4529 if (test_bit(BNX2X_RSS_IPV4_VXLAN, &p->rss_flags))
4530 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY;
4531
4532 if (test_bit(BNX2X_RSS_IPV6_VXLAN, &p->rss_flags))
4533 caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY;
4534
4535 if (test_bit(BNX2X_RSS_TUNN_INNER_HDRS, &p->rss_flags))
4536 caps |= ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY;
4537
4538
4539 if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) {
4540 u8 *dst = (u8 *)(data->rss_key) + sizeof(data->rss_key);
4541 const u8 *src = (const u8 *)p->rss_key;
4542 int i;
4543
4544
4545
4546
4547 for (i = 0; i < sizeof(data->rss_key); i++)
4548 *--dst = *src++;
4549
4550 caps |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY;
4551 }
4552
4553 data->capabilities = cpu_to_le16(caps);
4554
4555
4556 data->rss_result_mask = p->rss_result_mask;
4557
4558
4559 data->rss_engine_id = o->engine_id;
4560
4561 DP(BNX2X_MSG_SP, "rss_engine_id=%d\n", data->rss_engine_id);
4562
4563
4564 memcpy(data->indirection_table, p->ind_table,
4565 T_ETH_INDIRECTION_TABLE_SIZE);
4566
4567
4568 memcpy(o->ind_table, p->ind_table, T_ETH_INDIRECTION_TABLE_SIZE);
4569
4570
4571 if (netif_msg_ifup(bp))
4572 bnx2x_debug_print_ind_table(bp, p);
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_RSS_UPDATE, r->cid,
4583 U64_HI(r->rdata_mapping),
4584 U64_LO(r->rdata_mapping),
4585 ETH_CONNECTION_TYPE);
4586
4587 if (rc < 0)
4588 return rc;
4589
4590 return 1;
4591 }
4592
4593 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
4594 u8 *ind_table)
4595 {
4596 memcpy(ind_table, rss_obj->ind_table, sizeof(rss_obj->ind_table));
4597 }
4598
4599 int bnx2x_config_rss(struct bnx2x *bp,
4600 struct bnx2x_config_rss_params *p)
4601 {
4602 int rc;
4603 struct bnx2x_rss_config_obj *o = p->rss_obj;
4604 struct bnx2x_raw_obj *r = &o->raw;
4605
4606
4607 if (test_bit(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
4608 DP(BNX2X_MSG_SP, "Not configuring RSS ramrod_flags=%lx\n",
4609 p->ramrod_flags);
4610 return 0;
4611 }
4612
4613 r->set_pending(r);
4614
4615 rc = o->config_rss(bp, p);
4616 if (rc < 0) {
4617 r->clear_pending(r);
4618 return rc;
4619 }
4620
4621 if (test_bit(RAMROD_COMP_WAIT, &p->ramrod_flags))
4622 rc = r->wait_comp(bp, r);
4623
4624 return rc;
4625 }
4626
4627 void bnx2x_init_rss_config_obj(struct bnx2x *bp,
4628 struct bnx2x_rss_config_obj *rss_obj,
4629 u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
4630 void *rdata, dma_addr_t rdata_mapping,
4631 int state, unsigned long *pstate,
4632 bnx2x_obj_type type)
4633 {
4634 bnx2x_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata,
4635 rdata_mapping, state, pstate, type);
4636
4637 rss_obj->engine_id = engine_id;
4638 rss_obj->config_rss = bnx2x_setup_rss;
4639 }
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655 int bnx2x_queue_state_change(struct bnx2x *bp,
4656 struct bnx2x_queue_state_params *params)
4657 {
4658 struct bnx2x_queue_sp_obj *o = params->q_obj;
4659 int rc, pending_bit;
4660 unsigned long *pending = &o->pending;
4661
4662
4663 rc = o->check_transition(bp, o, params);
4664 if (rc) {
4665 BNX2X_ERR("check transition returned an error. rc %d\n", rc);
4666 return -EINVAL;
4667 }
4668
4669
4670 DP(BNX2X_MSG_SP, "pending bit was=%lx\n", o->pending);
4671 pending_bit = o->set_pending(o, params);
4672 DP(BNX2X_MSG_SP, "pending bit now=%lx\n", o->pending);
4673
4674
4675 if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags))
4676 o->complete_cmd(bp, o, pending_bit);
4677 else {
4678
4679 rc = o->send_cmd(bp, params);
4680 if (rc) {
4681 o->next_state = BNX2X_Q_STATE_MAX;
4682 clear_bit(pending_bit, pending);
4683 smp_mb__after_atomic();
4684 return rc;
4685 }
4686
4687 if (test_bit(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) {
4688 rc = o->wait_comp(bp, o, pending_bit);
4689 if (rc)
4690 return rc;
4691
4692 return 0;
4693 }
4694 }
4695
4696 return !!test_bit(pending_bit, pending);
4697 }
4698
4699 static int bnx2x_queue_set_pending(struct bnx2x_queue_sp_obj *obj,
4700 struct bnx2x_queue_state_params *params)
4701 {
4702 enum bnx2x_queue_cmd cmd = params->cmd, bit;
4703
4704
4705
4706
4707 if ((cmd == BNX2X_Q_CMD_ACTIVATE) ||
4708 (cmd == BNX2X_Q_CMD_DEACTIVATE))
4709 bit = BNX2X_Q_CMD_UPDATE;
4710 else
4711 bit = cmd;
4712
4713 set_bit(bit, &obj->pending);
4714 return bit;
4715 }
4716
4717 static int bnx2x_queue_wait_comp(struct bnx2x *bp,
4718 struct bnx2x_queue_sp_obj *o,
4719 enum bnx2x_queue_cmd cmd)
4720 {
4721 return bnx2x_state_wait(bp, cmd, &o->pending);
4722 }
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733 static int bnx2x_queue_comp_cmd(struct bnx2x *bp,
4734 struct bnx2x_queue_sp_obj *o,
4735 enum bnx2x_queue_cmd cmd)
4736 {
4737 unsigned long cur_pending = o->pending;
4738
4739 if (!test_and_clear_bit(cmd, &cur_pending)) {
4740 BNX2X_ERR("Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\n",
4741 cmd, o->cids[BNX2X_PRIMARY_CID_INDEX],
4742 o->state, cur_pending, o->next_state);
4743 return -EINVAL;
4744 }
4745
4746 if (o->next_tx_only >= o->max_cos)
4747
4748
4749
4750 BNX2X_ERR("illegal value for next tx_only: %d. max cos was %d",
4751 o->next_tx_only, o->max_cos);
4752
4753 DP(BNX2X_MSG_SP,
4754 "Completing command %d for queue %d, setting state to %d\n",
4755 cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_state);
4756
4757 if (o->next_tx_only)
4758 DP(BNX2X_MSG_SP, "primary cid %d: num tx-only cons %d\n",
4759 o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_tx_only);
4760
4761 o->state = o->next_state;
4762 o->num_tx_only = o->next_tx_only;
4763 o->next_state = BNX2X_Q_STATE_MAX;
4764
4765
4766
4767
4768 wmb();
4769
4770 clear_bit(cmd, &o->pending);
4771 smp_mb__after_atomic();
4772
4773 return 0;
4774 }
4775
4776 static void bnx2x_q_fill_setup_data_e2(struct bnx2x *bp,
4777 struct bnx2x_queue_state_params *cmd_params,
4778 struct client_init_ramrod_data *data)
4779 {
4780 struct bnx2x_queue_setup_params *params = &cmd_params->params.setup;
4781
4782
4783
4784
4785 data->rx.tpa_en |= test_bit(BNX2X_Q_FLG_TPA_IPV6, ¶ms->flags) *
4786 CLIENT_INIT_RX_DATA_TPA_EN_IPV6;
4787 }
4788
4789 static void bnx2x_q_fill_init_general_data(struct bnx2x *bp,
4790 struct bnx2x_queue_sp_obj *o,
4791 struct bnx2x_general_setup_params *params,
4792 struct client_init_general_data *gen_data,
4793 unsigned long *flags)
4794 {
4795 gen_data->client_id = o->cl_id;
4796
4797 if (test_bit(BNX2X_Q_FLG_STATS, flags)) {
4798 gen_data->statistics_counter_id =
4799 params->stat_id;
4800 gen_data->statistics_en_flg = 1;
4801 gen_data->statistics_zero_flg =
4802 test_bit(BNX2X_Q_FLG_ZERO_STATS, flags);
4803 } else
4804 gen_data->statistics_counter_id =
4805 DISABLE_STATISTIC_COUNTER_ID_VALUE;
4806
4807 gen_data->is_fcoe_flg = test_bit(BNX2X_Q_FLG_FCOE, flags);
4808 gen_data->activate_flg = test_bit(BNX2X_Q_FLG_ACTIVE, flags);
4809 gen_data->sp_client_id = params->spcl_id;
4810 gen_data->mtu = cpu_to_le16(params->mtu);
4811 gen_data->func_id = o->func_id;
4812
4813 gen_data->cos = params->cos;
4814
4815 gen_data->traffic_type =
4816 test_bit(BNX2X_Q_FLG_FCOE, flags) ?
4817 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
4818
4819 gen_data->fp_hsi_ver = params->fp_hsi;
4820
4821 DP(BNX2X_MSG_SP, "flags: active %d, cos %d, stats en %d\n",
4822 gen_data->activate_flg, gen_data->cos, gen_data->statistics_en_flg);
4823 }
4824
4825 static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o,
4826 struct bnx2x_txq_setup_params *params,
4827 struct client_init_tx_data *tx_data,
4828 unsigned long *flags)
4829 {
4830 tx_data->enforce_security_flg =
4831 test_bit(BNX2X_Q_FLG_TX_SEC, flags);
4832 tx_data->default_vlan =
4833 cpu_to_le16(params->default_vlan);
4834 tx_data->default_vlan_flg =
4835 test_bit(BNX2X_Q_FLG_DEF_VLAN, flags);
4836 tx_data->tx_switching_flg =
4837 test_bit(BNX2X_Q_FLG_TX_SWITCH, flags);
4838 tx_data->anti_spoofing_flg =
4839 test_bit(BNX2X_Q_FLG_ANTI_SPOOF, flags);
4840 tx_data->force_default_pri_flg =
4841 test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags);
4842 tx_data->refuse_outband_vlan_flg =
4843 test_bit(BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN, flags);
4844 tx_data->tunnel_lso_inc_ip_id =
4845 test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, flags);
4846 tx_data->tunnel_non_lso_pcsum_location =
4847 test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? CSUM_ON_PKT :
4848 CSUM_ON_BD;
4849
4850 tx_data->tx_status_block_id = params->fw_sb_id;
4851 tx_data->tx_sb_index_number = params->sb_cq_index;
4852 tx_data->tss_leading_client_id = params->tss_leading_cl_id;
4853
4854 tx_data->tx_bd_page_base.lo =
4855 cpu_to_le32(U64_LO(params->dscr_map));
4856 tx_data->tx_bd_page_base.hi =
4857 cpu_to_le32(U64_HI(params->dscr_map));
4858
4859
4860 tx_data->state = 0;
4861 }
4862
4863 static void bnx2x_q_fill_init_pause_data(struct bnx2x_queue_sp_obj *o,
4864 struct rxq_pause_params *params,
4865 struct client_init_rx_data *rx_data)
4866 {
4867
4868 rx_data->cqe_pause_thr_low = cpu_to_le16(params->rcq_th_lo);
4869 rx_data->cqe_pause_thr_high = cpu_to_le16(params->rcq_th_hi);
4870 rx_data->bd_pause_thr_low = cpu_to_le16(params->bd_th_lo);
4871 rx_data->bd_pause_thr_high = cpu_to_le16(params->bd_th_hi);
4872 rx_data->sge_pause_thr_low = cpu_to_le16(params->sge_th_lo);
4873 rx_data->sge_pause_thr_high = cpu_to_le16(params->sge_th_hi);
4874 rx_data->rx_cos_mask = cpu_to_le16(params->pri_map);
4875 }
4876
4877 static void bnx2x_q_fill_init_rx_data(struct bnx2x_queue_sp_obj *o,
4878 struct bnx2x_rxq_setup_params *params,
4879 struct client_init_rx_data *rx_data,
4880 unsigned long *flags)
4881 {
4882 rx_data->tpa_en = test_bit(BNX2X_Q_FLG_TPA, flags) *
4883 CLIENT_INIT_RX_DATA_TPA_EN_IPV4;
4884 rx_data->tpa_en |= test_bit(BNX2X_Q_FLG_TPA_GRO, flags) *
4885 CLIENT_INIT_RX_DATA_TPA_MODE;
4886 rx_data->vmqueue_mode_en_flg = 0;
4887
4888 rx_data->cache_line_alignment_log_size =
4889 params->cache_line_log;
4890 rx_data->enable_dynamic_hc =
4891 test_bit(BNX2X_Q_FLG_DHC, flags);
4892 rx_data->max_sges_for_packet = params->max_sges_pkt;
4893 rx_data->client_qzone_id = params->cl_qzone_id;
4894 rx_data->max_agg_size = cpu_to_le16(params->tpa_agg_sz);
4895
4896
4897 rx_data->state = cpu_to_le16(CLIENT_INIT_RX_DATA_UCAST_DROP_ALL |
4898 CLIENT_INIT_RX_DATA_MCAST_DROP_ALL);
4899
4900
4901 rx_data->drop_ip_cs_err_flg = 0;
4902 rx_data->drop_tcp_cs_err_flg = 0;
4903 rx_data->drop_ttl0_flg = 0;
4904 rx_data->drop_udp_cs_err_flg = 0;
4905 rx_data->inner_vlan_removal_enable_flg =
4906 test_bit(BNX2X_Q_FLG_VLAN, flags);
4907 rx_data->outer_vlan_removal_enable_flg =
4908 test_bit(BNX2X_Q_FLG_OV, flags);
4909 rx_data->status_block_id = params->fw_sb_id;
4910 rx_data->rx_sb_index_number = params->sb_cq_index;
4911 rx_data->max_tpa_queues = params->max_tpa_queues;
4912 rx_data->max_bytes_on_bd = cpu_to_le16(params->buf_sz);
4913 rx_data->sge_buff_size = cpu_to_le16(params->sge_buf_sz);
4914 rx_data->bd_page_base.lo =
4915 cpu_to_le32(U64_LO(params->dscr_map));
4916 rx_data->bd_page_base.hi =
4917 cpu_to_le32(U64_HI(params->dscr_map));
4918 rx_data->sge_page_base.lo =
4919 cpu_to_le32(U64_LO(params->sge_map));
4920 rx_data->sge_page_base.hi =
4921 cpu_to_le32(U64_HI(params->sge_map));
4922 rx_data->cqe_page_base.lo =
4923 cpu_to_le32(U64_LO(params->rcq_map));
4924 rx_data->cqe_page_base.hi =
4925 cpu_to_le32(U64_HI(params->rcq_map));
4926 rx_data->is_leading_rss = test_bit(BNX2X_Q_FLG_LEADING_RSS, flags);
4927
4928 if (test_bit(BNX2X_Q_FLG_MCAST, flags)) {
4929 rx_data->approx_mcast_engine_id = params->mcast_engine_id;
4930 rx_data->is_approx_mcast = 1;
4931 }
4932
4933 rx_data->rss_engine_id = params->rss_engine_id;
4934
4935
4936 rx_data->silent_vlan_removal_flg =
4937 test_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, flags);
4938 rx_data->silent_vlan_value =
4939 cpu_to_le16(params->silent_removal_value);
4940 rx_data->silent_vlan_mask =
4941 cpu_to_le16(params->silent_removal_mask);
4942 }
4943
4944
4945 static void bnx2x_q_fill_setup_data_cmn(struct bnx2x *bp,
4946 struct bnx2x_queue_state_params *cmd_params,
4947 struct client_init_ramrod_data *data)
4948 {
4949 bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj,
4950 &cmd_params->params.setup.gen_params,
4951 &data->general,
4952 &cmd_params->params.setup.flags);
4953
4954 bnx2x_q_fill_init_tx_data(cmd_params->q_obj,
4955 &cmd_params->params.setup.txq_params,
4956 &data->tx,
4957 &cmd_params->params.setup.flags);
4958
4959 bnx2x_q_fill_init_rx_data(cmd_params->q_obj,
4960 &cmd_params->params.setup.rxq_params,
4961 &data->rx,
4962 &cmd_params->params.setup.flags);
4963
4964 bnx2x_q_fill_init_pause_data(cmd_params->q_obj,
4965 &cmd_params->params.setup.pause_params,
4966 &data->rx);
4967 }
4968
4969
4970 static void bnx2x_q_fill_setup_tx_only(struct bnx2x *bp,
4971 struct bnx2x_queue_state_params *cmd_params,
4972 struct tx_queue_init_ramrod_data *data)
4973 {
4974 bnx2x_q_fill_init_general_data(bp, cmd_params->q_obj,
4975 &cmd_params->params.tx_only.gen_params,
4976 &data->general,
4977 &cmd_params->params.tx_only.flags);
4978
4979 bnx2x_q_fill_init_tx_data(cmd_params->q_obj,
4980 &cmd_params->params.tx_only.txq_params,
4981 &data->tx,
4982 &cmd_params->params.tx_only.flags);
4983
4984 DP(BNX2X_MSG_SP, "cid %d, tx bd page lo %x hi %x",
4985 cmd_params->q_obj->cids[0],
4986 data->tx.tx_bd_page_base.lo,
4987 data->tx.tx_bd_page_base.hi);
4988 }
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001 static inline int bnx2x_q_init(struct bnx2x *bp,
5002 struct bnx2x_queue_state_params *params)
5003 {
5004 struct bnx2x_queue_sp_obj *o = params->q_obj;
5005 struct bnx2x_queue_init_params *init = ¶ms->params.init;
5006 u16 hc_usec;
5007 u8 cos;
5008
5009
5010 if (test_bit(BNX2X_Q_TYPE_HAS_TX, &o->type) &&
5011 test_bit(BNX2X_Q_FLG_HC, &init->tx.flags)) {
5012 hc_usec = init->tx.hc_rate ? 1000000 / init->tx.hc_rate : 0;
5013
5014 bnx2x_update_coalesce_sb_index(bp, init->tx.fw_sb_id,
5015 init->tx.sb_cq_index,
5016 !test_bit(BNX2X_Q_FLG_HC_EN, &init->tx.flags),
5017 hc_usec);
5018 }
5019
5020
5021 if (test_bit(BNX2X_Q_TYPE_HAS_RX, &o->type) &&
5022 test_bit(BNX2X_Q_FLG_HC, &init->rx.flags)) {
5023 hc_usec = init->rx.hc_rate ? 1000000 / init->rx.hc_rate : 0;
5024
5025 bnx2x_update_coalesce_sb_index(bp, init->rx.fw_sb_id,
5026 init->rx.sb_cq_index,
5027 !test_bit(BNX2X_Q_FLG_HC_EN, &init->rx.flags),
5028 hc_usec);
5029 }
5030
5031
5032 for (cos = 0; cos < o->max_cos; cos++) {
5033 DP(BNX2X_MSG_SP, "setting context validation. cid %d, cos %d\n",
5034 o->cids[cos], cos);
5035 DP(BNX2X_MSG_SP, "context pointer %p\n", init->cxts[cos]);
5036 bnx2x_set_ctx_validation(bp, init->cxts[cos], o->cids[cos]);
5037 }
5038
5039
5040 o->complete_cmd(bp, o, BNX2X_Q_CMD_INIT);
5041
5042 smp_mb();
5043
5044 return 0;
5045 }
5046
5047 static inline int bnx2x_q_send_setup_e1x(struct bnx2x *bp,
5048 struct bnx2x_queue_state_params *params)
5049 {
5050 struct bnx2x_queue_sp_obj *o = params->q_obj;
5051 struct client_init_ramrod_data *rdata =
5052 (struct client_init_ramrod_data *)o->rdata;
5053 dma_addr_t data_mapping = o->rdata_mapping;
5054 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
5055
5056
5057 memset(rdata, 0, sizeof(*rdata));
5058
5059
5060 bnx2x_q_fill_setup_data_cmn(bp, params, rdata);
5061
5062
5063
5064
5065
5066
5067
5068 return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX],
5069 U64_HI(data_mapping),
5070 U64_LO(data_mapping), ETH_CONNECTION_TYPE);
5071 }
5072
5073 static inline int bnx2x_q_send_setup_e2(struct bnx2x *bp,
5074 struct bnx2x_queue_state_params *params)
5075 {
5076 struct bnx2x_queue_sp_obj *o = params->q_obj;
5077 struct client_init_ramrod_data *rdata =
5078 (struct client_init_ramrod_data *)o->rdata;
5079 dma_addr_t data_mapping = o->rdata_mapping;
5080 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
5081
5082
5083 memset(rdata, 0, sizeof(*rdata));
5084
5085
5086 bnx2x_q_fill_setup_data_cmn(bp, params, rdata);
5087 bnx2x_q_fill_setup_data_e2(bp, params, rdata);
5088
5089
5090
5091
5092
5093
5094
5095 return bnx2x_sp_post(bp, ramrod, o->cids[BNX2X_PRIMARY_CID_INDEX],
5096 U64_HI(data_mapping),
5097 U64_LO(data_mapping), ETH_CONNECTION_TYPE);
5098 }
5099
5100 static inline int bnx2x_q_send_setup_tx_only(struct bnx2x *bp,
5101 struct bnx2x_queue_state_params *params)
5102 {
5103 struct bnx2x_queue_sp_obj *o = params->q_obj;
5104 struct tx_queue_init_ramrod_data *rdata =
5105 (struct tx_queue_init_ramrod_data *)o->rdata;
5106 dma_addr_t data_mapping = o->rdata_mapping;
5107 int ramrod = RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP;
5108 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
5109 ¶ms->params.tx_only;
5110 u8 cid_index = tx_only_params->cid_index;
5111
5112 if (cid_index >= o->max_cos) {
5113 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
5114 o->cl_id, cid_index);
5115 return -EINVAL;
5116 }
5117
5118 DP(BNX2X_MSG_SP, "parameters received: cos: %d sp-id: %d\n",
5119 tx_only_params->gen_params.cos,
5120 tx_only_params->gen_params.spcl_id);
5121
5122
5123 memset(rdata, 0, sizeof(*rdata));
5124
5125
5126 bnx2x_q_fill_setup_tx_only(bp, params, rdata);
5127
5128 DP(BNX2X_MSG_SP, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\n",
5129 o->cids[cid_index], rdata->general.client_id,
5130 rdata->general.sp_client_id, rdata->general.cos);
5131
5132
5133
5134
5135
5136
5137
5138 return bnx2x_sp_post(bp, ramrod, o->cids[cid_index],
5139 U64_HI(data_mapping),
5140 U64_LO(data_mapping), ETH_CONNECTION_TYPE);
5141 }
5142
5143 static void bnx2x_q_fill_update_data(struct bnx2x *bp,
5144 struct bnx2x_queue_sp_obj *obj,
5145 struct bnx2x_queue_update_params *params,
5146 struct client_update_ramrod_data *data)
5147 {
5148
5149 data->client_id = obj->cl_id;
5150
5151
5152 data->func_id = obj->func_id;
5153
5154
5155 data->default_vlan = cpu_to_le16(params->def_vlan);
5156
5157
5158 data->inner_vlan_removal_enable_flg =
5159 test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM, ¶ms->update_flags);
5160 data->inner_vlan_removal_change_flg =
5161 test_bit(BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
5162 ¶ms->update_flags);
5163
5164
5165 data->outer_vlan_removal_enable_flg =
5166 test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM, ¶ms->update_flags);
5167 data->outer_vlan_removal_change_flg =
5168 test_bit(BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
5169 ¶ms->update_flags);
5170
5171
5172
5173
5174 data->anti_spoofing_enable_flg =
5175 test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF, ¶ms->update_flags);
5176 data->anti_spoofing_change_flg =
5177 test_bit(BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, ¶ms->update_flags);
5178
5179
5180 data->activate_flg =
5181 test_bit(BNX2X_Q_UPDATE_ACTIVATE, ¶ms->update_flags);
5182 data->activate_change_flg =
5183 test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, ¶ms->update_flags);
5184
5185
5186 data->default_vlan_enable_flg =
5187 test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN, ¶ms->update_flags);
5188 data->default_vlan_change_flg =
5189 test_bit(BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
5190 ¶ms->update_flags);
5191
5192
5193 data->silent_vlan_change_flg =
5194 test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5195 ¶ms->update_flags);
5196 data->silent_vlan_removal_flg =
5197 test_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, ¶ms->update_flags);
5198 data->silent_vlan_value = cpu_to_le16(params->silent_removal_value);
5199 data->silent_vlan_mask = cpu_to_le16(params->silent_removal_mask);
5200
5201
5202 data->tx_switching_flg =
5203 test_bit(BNX2X_Q_UPDATE_TX_SWITCHING, ¶ms->update_flags);
5204 data->tx_switching_change_flg =
5205 test_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
5206 ¶ms->update_flags);
5207
5208
5209 data->handle_ptp_pkts_flg =
5210 test_bit(BNX2X_Q_UPDATE_PTP_PKTS, ¶ms->update_flags);
5211 data->handle_ptp_pkts_change_flg =
5212 test_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, ¶ms->update_flags);
5213 }
5214
5215 static inline int bnx2x_q_send_update(struct bnx2x *bp,
5216 struct bnx2x_queue_state_params *params)
5217 {
5218 struct bnx2x_queue_sp_obj *o = params->q_obj;
5219 struct client_update_ramrod_data *rdata =
5220 (struct client_update_ramrod_data *)o->rdata;
5221 dma_addr_t data_mapping = o->rdata_mapping;
5222 struct bnx2x_queue_update_params *update_params =
5223 ¶ms->params.update;
5224 u8 cid_index = update_params->cid_index;
5225
5226 if (cid_index >= o->max_cos) {
5227 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
5228 o->cl_id, cid_index);
5229 return -EINVAL;
5230 }
5231
5232
5233 memset(rdata, 0, sizeof(*rdata));
5234
5235
5236 bnx2x_q_fill_update_data(bp, o, update_params, rdata);
5237
5238
5239
5240
5241
5242
5243
5244 return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
5245 o->cids[cid_index], U64_HI(data_mapping),
5246 U64_LO(data_mapping), ETH_CONNECTION_TYPE);
5247 }
5248
5249
5250
5251
5252
5253
5254
5255
5256
5257 static inline int bnx2x_q_send_deactivate(struct bnx2x *bp,
5258 struct bnx2x_queue_state_params *params)
5259 {
5260 struct bnx2x_queue_update_params *update = ¶ms->params.update;
5261
5262 memset(update, 0, sizeof(*update));
5263
5264 __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags);
5265
5266 return bnx2x_q_send_update(bp, params);
5267 }
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277 static inline int bnx2x_q_send_activate(struct bnx2x *bp,
5278 struct bnx2x_queue_state_params *params)
5279 {
5280 struct bnx2x_queue_update_params *update = ¶ms->params.update;
5281
5282 memset(update, 0, sizeof(*update));
5283
5284 __set_bit(BNX2X_Q_UPDATE_ACTIVATE, &update->update_flags);
5285 __set_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags);
5286
5287 return bnx2x_q_send_update(bp, params);
5288 }
5289
5290 static void bnx2x_q_fill_update_tpa_data(struct bnx2x *bp,
5291 struct bnx2x_queue_sp_obj *obj,
5292 struct bnx2x_queue_update_tpa_params *params,
5293 struct tpa_update_ramrod_data *data)
5294 {
5295 data->client_id = obj->cl_id;
5296 data->complete_on_both_clients = params->complete_on_both_clients;
5297 data->dont_verify_rings_pause_thr_flg =
5298 params->dont_verify_thr;
5299 data->max_agg_size = cpu_to_le16(params->max_agg_sz);
5300 data->max_sges_for_packet = params->max_sges_pkt;
5301 data->max_tpa_queues = params->max_tpa_queues;
5302 data->sge_buff_size = cpu_to_le16(params->sge_buff_sz);
5303 data->sge_page_base_hi = cpu_to_le32(U64_HI(params->sge_map));
5304 data->sge_page_base_lo = cpu_to_le32(U64_LO(params->sge_map));
5305 data->sge_pause_thr_high = cpu_to_le16(params->sge_pause_thr_high);
5306 data->sge_pause_thr_low = cpu_to_le16(params->sge_pause_thr_low);
5307 data->tpa_mode = params->tpa_mode;
5308 data->update_ipv4 = params->update_ipv4;
5309 data->update_ipv6 = params->update_ipv6;
5310 }
5311
5312 static inline int bnx2x_q_send_update_tpa(struct bnx2x *bp,
5313 struct bnx2x_queue_state_params *params)
5314 {
5315 struct bnx2x_queue_sp_obj *o = params->q_obj;
5316 struct tpa_update_ramrod_data *rdata =
5317 (struct tpa_update_ramrod_data *)o->rdata;
5318 dma_addr_t data_mapping = o->rdata_mapping;
5319 struct bnx2x_queue_update_tpa_params *update_tpa_params =
5320 ¶ms->params.update_tpa;
5321 u16 type;
5322
5323
5324 memset(rdata, 0, sizeof(*rdata));
5325
5326
5327 bnx2x_q_fill_update_tpa_data(bp, o, update_tpa_params, rdata);
5328
5329
5330
5331
5332
5333 type = ETH_CONNECTION_TYPE |
5334 ((o->func_id) << SPE_HDR_FUNCTION_ID_SHIFT);
5335
5336
5337
5338
5339
5340
5341
5342 return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TPA_UPDATE,
5343 o->cids[BNX2X_PRIMARY_CID_INDEX],
5344 U64_HI(data_mapping),
5345 U64_LO(data_mapping), type);
5346 }
5347
5348 static inline int bnx2x_q_send_halt(struct bnx2x *bp,
5349 struct bnx2x_queue_state_params *params)
5350 {
5351 struct bnx2x_queue_sp_obj *o = params->q_obj;
5352
5353 return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT,
5354 o->cids[BNX2X_PRIMARY_CID_INDEX], 0, o->cl_id,
5355 ETH_CONNECTION_TYPE);
5356 }
5357
5358 static inline int bnx2x_q_send_cfc_del(struct bnx2x *bp,
5359 struct bnx2x_queue_state_params *params)
5360 {
5361 struct bnx2x_queue_sp_obj *o = params->q_obj;
5362 u8 cid_idx = params->params.cfc_del.cid_index;
5363
5364 if (cid_idx >= o->max_cos) {
5365 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
5366 o->cl_id, cid_idx);
5367 return -EINVAL;
5368 }
5369
5370 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL,
5371 o->cids[cid_idx], 0, 0, NONE_CONNECTION_TYPE);
5372 }
5373
5374 static inline int bnx2x_q_send_terminate(struct bnx2x *bp,
5375 struct bnx2x_queue_state_params *params)
5376 {
5377 struct bnx2x_queue_sp_obj *o = params->q_obj;
5378 u8 cid_index = params->params.terminate.cid_index;
5379
5380 if (cid_index >= o->max_cos) {
5381 BNX2X_ERR("queue[%d]: cid_index (%d) is out of range\n",
5382 o->cl_id, cid_index);
5383 return -EINVAL;
5384 }
5385
5386 return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE,
5387 o->cids[cid_index], 0, 0, ETH_CONNECTION_TYPE);
5388 }
5389
5390 static inline int bnx2x_q_send_empty(struct bnx2x *bp,
5391 struct bnx2x_queue_state_params *params)
5392 {
5393 struct bnx2x_queue_sp_obj *o = params->q_obj;
5394
5395 return bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_EMPTY,
5396 o->cids[BNX2X_PRIMARY_CID_INDEX], 0, 0,
5397 ETH_CONNECTION_TYPE);
5398 }
5399
5400 static inline int bnx2x_queue_send_cmd_cmn(struct bnx2x *bp,
5401 struct bnx2x_queue_state_params *params)
5402 {
5403 switch (params->cmd) {
5404 case BNX2X_Q_CMD_INIT:
5405 return bnx2x_q_init(bp, params);
5406 case BNX2X_Q_CMD_SETUP_TX_ONLY:
5407 return bnx2x_q_send_setup_tx_only(bp, params);
5408 case BNX2X_Q_CMD_DEACTIVATE:
5409 return bnx2x_q_send_deactivate(bp, params);
5410 case BNX2X_Q_CMD_ACTIVATE:
5411 return bnx2x_q_send_activate(bp, params);
5412 case BNX2X_Q_CMD_UPDATE:
5413 return bnx2x_q_send_update(bp, params);
5414 case BNX2X_Q_CMD_UPDATE_TPA:
5415 return bnx2x_q_send_update_tpa(bp, params);
5416 case BNX2X_Q_CMD_HALT:
5417 return bnx2x_q_send_halt(bp, params);
5418 case BNX2X_Q_CMD_CFC_DEL:
5419 return bnx2x_q_send_cfc_del(bp, params);
5420 case BNX2X_Q_CMD_TERMINATE:
5421 return bnx2x_q_send_terminate(bp, params);
5422 case BNX2X_Q_CMD_EMPTY:
5423 return bnx2x_q_send_empty(bp, params);
5424 default:
5425 BNX2X_ERR("Unknown command: %d\n", params->cmd);
5426 return -EINVAL;
5427 }
5428 }
5429
5430 static int bnx2x_queue_send_cmd_e1x(struct bnx2x *bp,
5431 struct bnx2x_queue_state_params *params)
5432 {
5433 switch (params->cmd) {
5434 case BNX2X_Q_CMD_SETUP:
5435 return bnx2x_q_send_setup_e1x(bp, params);
5436 case BNX2X_Q_CMD_INIT:
5437 case BNX2X_Q_CMD_SETUP_TX_ONLY:
5438 case BNX2X_Q_CMD_DEACTIVATE:
5439 case BNX2X_Q_CMD_ACTIVATE:
5440 case BNX2X_Q_CMD_UPDATE:
5441 case BNX2X_Q_CMD_UPDATE_TPA:
5442 case BNX2X_Q_CMD_HALT:
5443 case BNX2X_Q_CMD_CFC_DEL:
5444 case BNX2X_Q_CMD_TERMINATE:
5445 case BNX2X_Q_CMD_EMPTY:
5446 return bnx2x_queue_send_cmd_cmn(bp, params);
5447 default:
5448 BNX2X_ERR("Unknown command: %d\n", params->cmd);
5449 return -EINVAL;
5450 }
5451 }
5452
5453 static int bnx2x_queue_send_cmd_e2(struct bnx2x *bp,
5454 struct bnx2x_queue_state_params *params)
5455 {
5456 switch (params->cmd) {
5457 case BNX2X_Q_CMD_SETUP:
5458 return bnx2x_q_send_setup_e2(bp, params);
5459 case BNX2X_Q_CMD_INIT:
5460 case BNX2X_Q_CMD_SETUP_TX_ONLY:
5461 case BNX2X_Q_CMD_DEACTIVATE:
5462 case BNX2X_Q_CMD_ACTIVATE:
5463 case BNX2X_Q_CMD_UPDATE:
5464 case BNX2X_Q_CMD_UPDATE_TPA:
5465 case BNX2X_Q_CMD_HALT:
5466 case BNX2X_Q_CMD_CFC_DEL:
5467 case BNX2X_Q_CMD_TERMINATE:
5468 case BNX2X_Q_CMD_EMPTY:
5469 return bnx2x_queue_send_cmd_cmn(bp, params);
5470 default:
5471 BNX2X_ERR("Unknown command: %d\n", params->cmd);
5472 return -EINVAL;
5473 }
5474 }
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492 static int bnx2x_queue_chk_transition(struct bnx2x *bp,
5493 struct bnx2x_queue_sp_obj *o,
5494 struct bnx2x_queue_state_params *params)
5495 {
5496 enum bnx2x_q_state state = o->state, next_state = BNX2X_Q_STATE_MAX;
5497 enum bnx2x_queue_cmd cmd = params->cmd;
5498 struct bnx2x_queue_update_params *update_params =
5499 ¶ms->params.update;
5500 u8 next_tx_only = o->num_tx_only;
5501
5502
5503
5504
5505 if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) {
5506 o->pending = 0;
5507 o->next_state = BNX2X_Q_STATE_MAX;
5508 }
5509
5510
5511
5512
5513 if (o->pending) {
5514 BNX2X_ERR("Blocking transition since pending was %lx\n",
5515 o->pending);
5516 return -EBUSY;
5517 }
5518
5519 switch (state) {
5520 case BNX2X_Q_STATE_RESET:
5521 if (cmd == BNX2X_Q_CMD_INIT)
5522 next_state = BNX2X_Q_STATE_INITIALIZED;
5523
5524 break;
5525 case BNX2X_Q_STATE_INITIALIZED:
5526 if (cmd == BNX2X_Q_CMD_SETUP) {
5527 if (test_bit(BNX2X_Q_FLG_ACTIVE,
5528 ¶ms->params.setup.flags))
5529 next_state = BNX2X_Q_STATE_ACTIVE;
5530 else
5531 next_state = BNX2X_Q_STATE_INACTIVE;
5532 }
5533
5534 break;
5535 case BNX2X_Q_STATE_ACTIVE:
5536 if (cmd == BNX2X_Q_CMD_DEACTIVATE)
5537 next_state = BNX2X_Q_STATE_INACTIVE;
5538
5539 else if ((cmd == BNX2X_Q_CMD_EMPTY) ||
5540 (cmd == BNX2X_Q_CMD_UPDATE_TPA))
5541 next_state = BNX2X_Q_STATE_ACTIVE;
5542
5543 else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) {
5544 next_state = BNX2X_Q_STATE_MULTI_COS;
5545 next_tx_only = 1;
5546 }
5547
5548 else if (cmd == BNX2X_Q_CMD_HALT)
5549 next_state = BNX2X_Q_STATE_STOPPED;
5550
5551 else if (cmd == BNX2X_Q_CMD_UPDATE) {
5552
5553
5554
5555 if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG,
5556 &update_params->update_flags) &&
5557 !test_bit(BNX2X_Q_UPDATE_ACTIVATE,
5558 &update_params->update_flags))
5559 next_state = BNX2X_Q_STATE_INACTIVE;
5560 else
5561 next_state = BNX2X_Q_STATE_ACTIVE;
5562 }
5563
5564 break;
5565 case BNX2X_Q_STATE_MULTI_COS:
5566 if (cmd == BNX2X_Q_CMD_TERMINATE)
5567 next_state = BNX2X_Q_STATE_MCOS_TERMINATED;
5568
5569 else if (cmd == BNX2X_Q_CMD_SETUP_TX_ONLY) {
5570 next_state = BNX2X_Q_STATE_MULTI_COS;
5571 next_tx_only = o->num_tx_only + 1;
5572 }
5573
5574 else if ((cmd == BNX2X_Q_CMD_EMPTY) ||
5575 (cmd == BNX2X_Q_CMD_UPDATE_TPA))
5576 next_state = BNX2X_Q_STATE_MULTI_COS;
5577
5578 else if (cmd == BNX2X_Q_CMD_UPDATE) {
5579
5580
5581
5582 if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG,
5583 &update_params->update_flags) &&
5584 !test_bit(BNX2X_Q_UPDATE_ACTIVATE,
5585 &update_params->update_flags))
5586 next_state = BNX2X_Q_STATE_INACTIVE;
5587 else
5588 next_state = BNX2X_Q_STATE_MULTI_COS;
5589 }
5590
5591 break;
5592 case BNX2X_Q_STATE_MCOS_TERMINATED:
5593 if (cmd == BNX2X_Q_CMD_CFC_DEL) {
5594 next_tx_only = o->num_tx_only - 1;
5595 if (next_tx_only == 0)
5596 next_state = BNX2X_Q_STATE_ACTIVE;
5597 else
5598 next_state = BNX2X_Q_STATE_MULTI_COS;
5599 }
5600
5601 break;
5602 case BNX2X_Q_STATE_INACTIVE:
5603 if (cmd == BNX2X_Q_CMD_ACTIVATE)
5604 next_state = BNX2X_Q_STATE_ACTIVE;
5605
5606 else if ((cmd == BNX2X_Q_CMD_EMPTY) ||
5607 (cmd == BNX2X_Q_CMD_UPDATE_TPA))
5608 next_state = BNX2X_Q_STATE_INACTIVE;
5609
5610 else if (cmd == BNX2X_Q_CMD_HALT)
5611 next_state = BNX2X_Q_STATE_STOPPED;
5612
5613 else if (cmd == BNX2X_Q_CMD_UPDATE) {
5614
5615
5616
5617 if (test_bit(BNX2X_Q_UPDATE_ACTIVATE_CHNG,
5618 &update_params->update_flags) &&
5619 test_bit(BNX2X_Q_UPDATE_ACTIVATE,
5620 &update_params->update_flags)){
5621 if (o->num_tx_only == 0)
5622 next_state = BNX2X_Q_STATE_ACTIVE;
5623 else
5624 next_state = BNX2X_Q_STATE_MULTI_COS;
5625 } else
5626 next_state = BNX2X_Q_STATE_INACTIVE;
5627 }
5628
5629 break;
5630 case BNX2X_Q_STATE_STOPPED:
5631 if (cmd == BNX2X_Q_CMD_TERMINATE)
5632 next_state = BNX2X_Q_STATE_TERMINATED;
5633
5634 break;
5635 case BNX2X_Q_STATE_TERMINATED:
5636 if (cmd == BNX2X_Q_CMD_CFC_DEL)
5637 next_state = BNX2X_Q_STATE_RESET;
5638
5639 break;
5640 default:
5641 BNX2X_ERR("Illegal state: %d\n", state);
5642 }
5643
5644
5645 if (next_state != BNX2X_Q_STATE_MAX) {
5646 DP(BNX2X_MSG_SP, "Good state transition: %d(%d)->%d\n",
5647 state, cmd, next_state);
5648 o->next_state = next_state;
5649 o->next_tx_only = next_tx_only;
5650 return 0;
5651 }
5652
5653 DP(BNX2X_MSG_SP, "Bad state transition request: %d %d\n", state, cmd);
5654
5655 return -EINVAL;
5656 }
5657
5658 void bnx2x_init_queue_obj(struct bnx2x *bp,
5659 struct bnx2x_queue_sp_obj *obj,
5660 u8 cl_id, u32 *cids, u8 cid_cnt, u8 func_id,
5661 void *rdata,
5662 dma_addr_t rdata_mapping, unsigned long type)
5663 {
5664 memset(obj, 0, sizeof(*obj));
5665
5666
5667 BUG_ON(BNX2X_MULTI_TX_COS < cid_cnt);
5668
5669 memcpy(obj->cids, cids, sizeof(obj->cids[0]) * cid_cnt);
5670 obj->max_cos = cid_cnt;
5671 obj->cl_id = cl_id;
5672 obj->func_id = func_id;
5673 obj->rdata = rdata;
5674 obj->rdata_mapping = rdata_mapping;
5675 obj->type = type;
5676 obj->next_state = BNX2X_Q_STATE_MAX;
5677
5678 if (CHIP_IS_E1x(bp))
5679 obj->send_cmd = bnx2x_queue_send_cmd_e1x;
5680 else
5681 obj->send_cmd = bnx2x_queue_send_cmd_e2;
5682
5683 obj->check_transition = bnx2x_queue_chk_transition;
5684
5685 obj->complete_cmd = bnx2x_queue_comp_cmd;
5686 obj->wait_comp = bnx2x_queue_wait_comp;
5687 obj->set_pending = bnx2x_queue_set_pending;
5688 }
5689
5690
5691 int bnx2x_get_q_logical_state(struct bnx2x *bp,
5692 struct bnx2x_queue_sp_obj *obj)
5693 {
5694 switch (obj->state) {
5695 case BNX2X_Q_STATE_ACTIVE:
5696 case BNX2X_Q_STATE_MULTI_COS:
5697 return BNX2X_Q_LOGICAL_STATE_ACTIVE;
5698 case BNX2X_Q_STATE_RESET:
5699 case BNX2X_Q_STATE_INITIALIZED:
5700 case BNX2X_Q_STATE_MCOS_TERMINATED:
5701 case BNX2X_Q_STATE_INACTIVE:
5702 case BNX2X_Q_STATE_STOPPED:
5703 case BNX2X_Q_STATE_TERMINATED:
5704 case BNX2X_Q_STATE_FLRED:
5705 return BNX2X_Q_LOGICAL_STATE_STOPPED;
5706 default:
5707 return -EINVAL;
5708 }
5709 }
5710
5711
5712 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
5713 struct bnx2x_func_sp_obj *o)
5714 {
5715
5716 if (o->pending)
5717 return BNX2X_F_STATE_MAX;
5718
5719
5720
5721
5722 rmb();
5723
5724 return o->state;
5725 }
5726
5727 static int bnx2x_func_wait_comp(struct bnx2x *bp,
5728 struct bnx2x_func_sp_obj *o,
5729 enum bnx2x_func_cmd cmd)
5730 {
5731 return bnx2x_state_wait(bp, cmd, &o->pending);
5732 }
5733
5734
5735
5736
5737
5738
5739
5740
5741
5742
5743
5744 static inline int bnx2x_func_state_change_comp(struct bnx2x *bp,
5745 struct bnx2x_func_sp_obj *o,
5746 enum bnx2x_func_cmd cmd)
5747 {
5748 unsigned long cur_pending = o->pending;
5749
5750 if (!test_and_clear_bit(cmd, &cur_pending)) {
5751 BNX2X_ERR("Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\n",
5752 cmd, BP_FUNC(bp), o->state,
5753 cur_pending, o->next_state);
5754 return -EINVAL;
5755 }
5756
5757 DP(BNX2X_MSG_SP,
5758 "Completing command %d for func %d, setting state to %d\n",
5759 cmd, BP_FUNC(bp), o->next_state);
5760
5761 o->state = o->next_state;
5762 o->next_state = BNX2X_F_STATE_MAX;
5763
5764
5765
5766
5767 wmb();
5768
5769 clear_bit(cmd, &o->pending);
5770 smp_mb__after_atomic();
5771
5772 return 0;
5773 }
5774
5775
5776
5777
5778
5779
5780
5781
5782
5783
5784 static int bnx2x_func_comp_cmd(struct bnx2x *bp,
5785 struct bnx2x_func_sp_obj *o,
5786 enum bnx2x_func_cmd cmd)
5787 {
5788
5789
5790
5791 int rc = bnx2x_func_state_change_comp(bp, o, cmd);
5792 return rc;
5793 }
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810 static int bnx2x_func_chk_transition(struct bnx2x *bp,
5811 struct bnx2x_func_sp_obj *o,
5812 struct bnx2x_func_state_params *params)
5813 {
5814 enum bnx2x_func_state state = o->state, next_state = BNX2X_F_STATE_MAX;
5815 enum bnx2x_func_cmd cmd = params->cmd;
5816
5817
5818
5819
5820 if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) {
5821 o->pending = 0;
5822 o->next_state = BNX2X_F_STATE_MAX;
5823 }
5824
5825
5826
5827
5828 if (o->pending)
5829 return -EBUSY;
5830
5831 switch (state) {
5832 case BNX2X_F_STATE_RESET:
5833 if (cmd == BNX2X_F_CMD_HW_INIT)
5834 next_state = BNX2X_F_STATE_INITIALIZED;
5835
5836 break;
5837 case BNX2X_F_STATE_INITIALIZED:
5838 if (cmd == BNX2X_F_CMD_START)
5839 next_state = BNX2X_F_STATE_STARTED;
5840
5841 else if (cmd == BNX2X_F_CMD_HW_RESET)
5842 next_state = BNX2X_F_STATE_RESET;
5843
5844 break;
5845 case BNX2X_F_STATE_STARTED:
5846 if (cmd == BNX2X_F_CMD_STOP)
5847 next_state = BNX2X_F_STATE_INITIALIZED;
5848
5849
5850
5851
5852 else if ((cmd == BNX2X_F_CMD_AFEX_UPDATE) &&
5853 (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5854 next_state = BNX2X_F_STATE_STARTED;
5855
5856 else if ((cmd == BNX2X_F_CMD_AFEX_VIFLISTS) &&
5857 (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5858 next_state = BNX2X_F_STATE_STARTED;
5859
5860
5861
5862
5863 else if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) &&
5864 (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5865 next_state = BNX2X_F_STATE_STARTED;
5866
5867 else if ((cmd == BNX2X_F_CMD_SET_TIMESYNC) &&
5868 (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5869 next_state = BNX2X_F_STATE_STARTED;
5870
5871 else if (cmd == BNX2X_F_CMD_TX_STOP)
5872 next_state = BNX2X_F_STATE_TX_STOPPED;
5873
5874 break;
5875 case BNX2X_F_STATE_TX_STOPPED:
5876 if ((cmd == BNX2X_F_CMD_SWITCH_UPDATE) &&
5877 (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5878 next_state = BNX2X_F_STATE_TX_STOPPED;
5879
5880 else if ((cmd == BNX2X_F_CMD_SET_TIMESYNC) &&
5881 (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
5882 next_state = BNX2X_F_STATE_TX_STOPPED;
5883
5884 else if (cmd == BNX2X_F_CMD_TX_START)
5885 next_state = BNX2X_F_STATE_STARTED;
5886
5887 break;
5888 default:
5889 BNX2X_ERR("Unknown state: %d\n", state);
5890 }
5891
5892
5893 if (next_state != BNX2X_F_STATE_MAX) {
5894 DP(BNX2X_MSG_SP, "Good function state transition: %d(%d)->%d\n",
5895 state, cmd, next_state);
5896 o->next_state = next_state;
5897 return 0;
5898 }
5899
5900 DP(BNX2X_MSG_SP, "Bad function state transition request: %d %d\n",
5901 state, cmd);
5902
5903 return -EINVAL;
5904 }
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916 static inline int bnx2x_func_init_func(struct bnx2x *bp,
5917 const struct bnx2x_func_sp_drv_ops *drv)
5918 {
5919 return drv->init_hw_func(bp);
5920 }
5921
5922
5923
5924
5925
5926
5927
5928
5929
5930
5931
5932
5933 static inline int bnx2x_func_init_port(struct bnx2x *bp,
5934 const struct bnx2x_func_sp_drv_ops *drv)
5935 {
5936 int rc = drv->init_hw_port(bp);
5937 if (rc)
5938 return rc;
5939
5940 return bnx2x_func_init_func(bp, drv);
5941 }
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953 static inline int bnx2x_func_init_cmn_chip(struct bnx2x *bp,
5954 const struct bnx2x_func_sp_drv_ops *drv)
5955 {
5956 int rc = drv->init_hw_cmn_chip(bp);
5957 if (rc)
5958 return rc;
5959
5960 return bnx2x_func_init_port(bp, drv);
5961 }
5962
5963
5964
5965
5966
5967
5968
5969
5970
5971
5972
5973 static inline int bnx2x_func_init_cmn(struct bnx2x *bp,
5974 const struct bnx2x_func_sp_drv_ops *drv)
5975 {
5976 int rc = drv->init_hw_cmn(bp);
5977 if (rc)
5978 return rc;
5979
5980 return bnx2x_func_init_port(bp, drv);
5981 }
5982
5983 static int bnx2x_func_hw_init(struct bnx2x *bp,
5984 struct bnx2x_func_state_params *params)
5985 {
5986 u32 load_code = params->params.hw_init.load_phase;
5987 struct bnx2x_func_sp_obj *o = params->f_obj;
5988 const struct bnx2x_func_sp_drv_ops *drv = o->drv;
5989 int rc = 0;
5990
5991 DP(BNX2X_MSG_SP, "function %d load_code %x\n",
5992 BP_ABS_FUNC(bp), load_code);
5993
5994
5995 rc = drv->gunzip_init(bp);
5996 if (rc)
5997 return rc;
5998
5999
6000 rc = drv->init_fw(bp);
6001 if (rc) {
6002 BNX2X_ERR("Error loading firmware\n");
6003 goto init_err;
6004 }
6005
6006
6007 switch (load_code) {
6008 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6009 rc = bnx2x_func_init_cmn_chip(bp, drv);
6010 if (rc)
6011 goto init_err;
6012
6013 break;
6014 case FW_MSG_CODE_DRV_LOAD_COMMON:
6015 rc = bnx2x_func_init_cmn(bp, drv);
6016 if (rc)
6017 goto init_err;
6018
6019 break;
6020 case FW_MSG_CODE_DRV_LOAD_PORT:
6021 rc = bnx2x_func_init_port(bp, drv);
6022 if (rc)
6023 goto init_err;
6024
6025 break;
6026 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6027 rc = bnx2x_func_init_func(bp, drv);
6028 if (rc)
6029 goto init_err;
6030
6031 break;
6032 default:
6033 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6034 rc = -EINVAL;
6035 }
6036
6037 init_err:
6038 drv->gunzip_end(bp);
6039
6040
6041
6042
6043 if (!rc)
6044 o->complete_cmd(bp, o, BNX2X_F_CMD_HW_INIT);
6045
6046 return rc;
6047 }
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058 static inline void bnx2x_func_reset_func(struct bnx2x *bp,
6059 const struct bnx2x_func_sp_drv_ops *drv)
6060 {
6061 drv->reset_hw_func(bp);
6062 }
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079 static inline void bnx2x_func_reset_port(struct bnx2x *bp,
6080 const struct bnx2x_func_sp_drv_ops *drv)
6081 {
6082 drv->reset_hw_port(bp);
6083 bnx2x_func_reset_func(bp, drv);
6084 }
6085
6086
6087
6088
6089
6090
6091
6092
6093
6094
6095
6096 static inline void bnx2x_func_reset_cmn(struct bnx2x *bp,
6097 const struct bnx2x_func_sp_drv_ops *drv)
6098 {
6099 bnx2x_func_reset_port(bp, drv);
6100 drv->reset_hw_cmn(bp);
6101 }
6102
6103 static inline int bnx2x_func_hw_reset(struct bnx2x *bp,
6104 struct bnx2x_func_state_params *params)
6105 {
6106 u32 reset_phase = params->params.hw_reset.reset_phase;
6107 struct bnx2x_func_sp_obj *o = params->f_obj;
6108 const struct bnx2x_func_sp_drv_ops *drv = o->drv;
6109
6110 DP(BNX2X_MSG_SP, "function %d reset_phase %x\n", BP_ABS_FUNC(bp),
6111 reset_phase);
6112
6113 switch (reset_phase) {
6114 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
6115 bnx2x_func_reset_cmn(bp, drv);
6116 break;
6117 case FW_MSG_CODE_DRV_UNLOAD_PORT:
6118 bnx2x_func_reset_port(bp, drv);
6119 break;
6120 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
6121 bnx2x_func_reset_func(bp, drv);
6122 break;
6123 default:
6124 BNX2X_ERR("Unknown reset_phase (0x%x) from MCP\n",
6125 reset_phase);
6126 break;
6127 }
6128
6129
6130 o->complete_cmd(bp, o, BNX2X_F_CMD_HW_RESET);
6131
6132 return 0;
6133 }
6134
6135 static inline int bnx2x_func_send_start(struct bnx2x *bp,
6136 struct bnx2x_func_state_params *params)
6137 {
6138 struct bnx2x_func_sp_obj *o = params->f_obj;
6139 struct function_start_data *rdata =
6140 (struct function_start_data *)o->rdata;
6141 dma_addr_t data_mapping = o->rdata_mapping;
6142 struct bnx2x_func_start_params *start_params = ¶ms->params.start;
6143
6144 memset(rdata, 0, sizeof(*rdata));
6145
6146
6147 rdata->function_mode = (u8)start_params->mf_mode;
6148 rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag);
6149 rdata->path_id = BP_PATH(bp);
6150 rdata->network_cos_mode = start_params->network_cos_mode;
6151 rdata->dmae_cmd_id = BNX2X_FW_DMAE_C;
6152
6153 rdata->vxlan_dst_port = cpu_to_le16(start_params->vxlan_dst_port);
6154 rdata->geneve_dst_port = cpu_to_le16(start_params->geneve_dst_port);
6155 rdata->inner_clss_l2gre = start_params->inner_clss_l2gre;
6156 rdata->inner_clss_l2geneve = start_params->inner_clss_l2geneve;
6157 rdata->inner_clss_vxlan = start_params->inner_clss_vxlan;
6158 rdata->inner_rss = start_params->inner_rss;
6159
6160 rdata->sd_accept_mf_clss_fail = start_params->class_fail;
6161 if (start_params->class_fail_ethtype) {
6162 rdata->sd_accept_mf_clss_fail_match_ethtype = 1;
6163 rdata->sd_accept_mf_clss_fail_ethtype =
6164 cpu_to_le16(start_params->class_fail_ethtype);
6165 }
6166
6167 rdata->sd_vlan_force_pri_flg = start_params->sd_vlan_force_pri;
6168 rdata->sd_vlan_force_pri_val = start_params->sd_vlan_force_pri_val;
6169 if (start_params->sd_vlan_eth_type)
6170 rdata->sd_vlan_eth_type =
6171 cpu_to_le16(start_params->sd_vlan_eth_type);
6172 else
6173 rdata->sd_vlan_eth_type =
6174 cpu_to_le16(0x8100);
6175
6176 rdata->no_added_tags = start_params->no_added_tags;
6177
6178 rdata->c2s_pri_tt_valid = start_params->c2s_pri_valid;
6179 if (rdata->c2s_pri_tt_valid) {
6180 memcpy(rdata->c2s_pri_trans_table.val,
6181 start_params->c2s_pri,
6182 MAX_VLAN_PRIORITIES);
6183 rdata->c2s_pri_default = start_params->c2s_pri_default;
6184 }
6185
6186
6187
6188
6189
6190
6191
6192 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0,
6193 U64_HI(data_mapping),
6194 U64_LO(data_mapping), NONE_CONNECTION_TYPE);
6195 }
6196
6197 static inline int bnx2x_func_send_switch_update(struct bnx2x *bp,
6198 struct bnx2x_func_state_params *params)
6199 {
6200 struct bnx2x_func_sp_obj *o = params->f_obj;
6201 struct function_update_data *rdata =
6202 (struct function_update_data *)o->rdata;
6203 dma_addr_t data_mapping = o->rdata_mapping;
6204 struct bnx2x_func_switch_update_params *switch_update_params =
6205 ¶ms->params.switch_update;
6206
6207 memset(rdata, 0, sizeof(*rdata));
6208
6209
6210 if (test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
6211 &switch_update_params->changes)) {
6212 rdata->tx_switch_suspend_change_flg = 1;
6213 rdata->tx_switch_suspend =
6214 test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
6215 &switch_update_params->changes);
6216 }
6217
6218 if (test_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
6219 &switch_update_params->changes)) {
6220 rdata->sd_vlan_tag_change_flg = 1;
6221 rdata->sd_vlan_tag =
6222 cpu_to_le16(switch_update_params->vlan);
6223 }
6224
6225 if (test_bit(BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,
6226 &switch_update_params->changes)) {
6227 rdata->sd_vlan_eth_type_change_flg = 1;
6228 rdata->sd_vlan_eth_type =
6229 cpu_to_le16(switch_update_params->vlan_eth_type);
6230 }
6231
6232 if (test_bit(BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
6233 &switch_update_params->changes)) {
6234 rdata->sd_vlan_force_pri_change_flg = 1;
6235 if (test_bit(BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
6236 &switch_update_params->changes))
6237 rdata->sd_vlan_force_pri_flg = 1;
6238 rdata->sd_vlan_force_pri_flg =
6239 switch_update_params->vlan_force_prio;
6240 }
6241
6242 if (test_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
6243 &switch_update_params->changes)) {
6244 rdata->update_tunn_cfg_flg = 1;
6245 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
6246 &switch_update_params->changes))
6247 rdata->inner_clss_l2gre = 1;
6248 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
6249 &switch_update_params->changes))
6250 rdata->inner_clss_vxlan = 1;
6251 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
6252 &switch_update_params->changes))
6253 rdata->inner_clss_l2geneve = 1;
6254 if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
6255 &switch_update_params->changes))
6256 rdata->inner_rss = 1;
6257 rdata->vxlan_dst_port =
6258 cpu_to_le16(switch_update_params->vxlan_dst_port);
6259 rdata->geneve_dst_port =
6260 cpu_to_le16(switch_update_params->geneve_dst_port);
6261 }
6262
6263 rdata->echo = SWITCH_UPDATE;
6264
6265
6266
6267
6268
6269
6270
6271 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
6272 U64_HI(data_mapping),
6273 U64_LO(data_mapping), NONE_CONNECTION_TYPE);
6274 }
6275
6276 static inline int bnx2x_func_send_afex_update(struct bnx2x *bp,
6277 struct bnx2x_func_state_params *params)
6278 {
6279 struct bnx2x_func_sp_obj *o = params->f_obj;
6280 struct function_update_data *rdata =
6281 (struct function_update_data *)o->afex_rdata;
6282 dma_addr_t data_mapping = o->afex_rdata_mapping;
6283 struct bnx2x_func_afex_update_params *afex_update_params =
6284 ¶ms->params.afex_update;
6285
6286 memset(rdata, 0, sizeof(*rdata));
6287
6288
6289 rdata->vif_id_change_flg = 1;
6290 rdata->vif_id = cpu_to_le16(afex_update_params->vif_id);
6291 rdata->afex_default_vlan_change_flg = 1;
6292 rdata->afex_default_vlan =
6293 cpu_to_le16(afex_update_params->afex_default_vlan);
6294 rdata->allowed_priorities_change_flg = 1;
6295 rdata->allowed_priorities = afex_update_params->allowed_priorities;
6296 rdata->echo = AFEX_UPDATE;
6297
6298
6299
6300
6301
6302
6303
6304 DP(BNX2X_MSG_SP,
6305 "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x\n",
6306 rdata->vif_id,
6307 rdata->afex_default_vlan, rdata->allowed_priorities);
6308
6309 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
6310 U64_HI(data_mapping),
6311 U64_LO(data_mapping), NONE_CONNECTION_TYPE);
6312 }
6313
6314 static
6315 inline int bnx2x_func_send_afex_viflists(struct bnx2x *bp,
6316 struct bnx2x_func_state_params *params)
6317 {
6318 struct bnx2x_func_sp_obj *o = params->f_obj;
6319 struct afex_vif_list_ramrod_data *rdata =
6320 (struct afex_vif_list_ramrod_data *)o->afex_rdata;
6321 struct bnx2x_func_afex_viflists_params *afex_vif_params =
6322 ¶ms->params.afex_viflists;
6323 u64 *p_rdata = (u64 *)rdata;
6324
6325 memset(rdata, 0, sizeof(*rdata));
6326
6327
6328 rdata->vif_list_index = cpu_to_le16(afex_vif_params->vif_list_index);
6329 rdata->func_bit_map = afex_vif_params->func_bit_map;
6330 rdata->afex_vif_list_command = afex_vif_params->afex_vif_list_command;
6331 rdata->func_to_clear = afex_vif_params->func_to_clear;
6332
6333
6334 rdata->echo = afex_vif_params->afex_vif_list_command;
6335
6336
6337
6338
6339
6340
6341
6342
6343 DP(BNX2X_MSG_SP, "afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x\n",
6344 rdata->afex_vif_list_command, rdata->vif_list_index,
6345 rdata->func_bit_map, rdata->func_to_clear);
6346
6347
6348 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 0,
6349 U64_HI(*p_rdata), U64_LO(*p_rdata),
6350 NONE_CONNECTION_TYPE);
6351 }
6352
6353 static inline int bnx2x_func_send_stop(struct bnx2x *bp,
6354 struct bnx2x_func_state_params *params)
6355 {
6356 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0,
6357 NONE_CONNECTION_TYPE);
6358 }
6359
6360 static inline int bnx2x_func_send_tx_stop(struct bnx2x *bp,
6361 struct bnx2x_func_state_params *params)
6362 {
6363 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 0, 0, 0,
6364 NONE_CONNECTION_TYPE);
6365 }
6366 static inline int bnx2x_func_send_tx_start(struct bnx2x *bp,
6367 struct bnx2x_func_state_params *params)
6368 {
6369 struct bnx2x_func_sp_obj *o = params->f_obj;
6370 struct flow_control_configuration *rdata =
6371 (struct flow_control_configuration *)o->rdata;
6372 dma_addr_t data_mapping = o->rdata_mapping;
6373 struct bnx2x_func_tx_start_params *tx_start_params =
6374 ¶ms->params.tx_start;
6375 int i;
6376
6377 memset(rdata, 0, sizeof(*rdata));
6378
6379 rdata->dcb_enabled = tx_start_params->dcb_enabled;
6380 rdata->dcb_version = tx_start_params->dcb_version;
6381 rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0_en;
6382
6383 for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)
6384 rdata->traffic_type_to_priority_cos[i] =
6385 tx_start_params->traffic_type_to_priority_cos[i];
6386
6387 for (i = 0; i < MAX_TRAFFIC_TYPES; i++)
6388 rdata->dcb_outer_pri[i] = tx_start_params->dcb_outer_pri[i];
6389
6390
6391
6392
6393
6394
6395 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_START_TRAFFIC, 0,
6396 U64_HI(data_mapping),
6397 U64_LO(data_mapping), NONE_CONNECTION_TYPE);
6398 }
6399
6400 static inline
6401 int bnx2x_func_send_set_timesync(struct bnx2x *bp,
6402 struct bnx2x_func_state_params *params)
6403 {
6404 struct bnx2x_func_sp_obj *o = params->f_obj;
6405 struct set_timesync_ramrod_data *rdata =
6406 (struct set_timesync_ramrod_data *)o->rdata;
6407 dma_addr_t data_mapping = o->rdata_mapping;
6408 struct bnx2x_func_set_timesync_params *set_timesync_params =
6409 ¶ms->params.set_timesync;
6410
6411 memset(rdata, 0, sizeof(*rdata));
6412
6413
6414 rdata->drift_adjust_cmd = set_timesync_params->drift_adjust_cmd;
6415 rdata->offset_cmd = set_timesync_params->offset_cmd;
6416 rdata->add_sub_drift_adjust_value =
6417 set_timesync_params->add_sub_drift_adjust_value;
6418 rdata->drift_adjust_value = set_timesync_params->drift_adjust_value;
6419 rdata->drift_adjust_period = set_timesync_params->drift_adjust_period;
6420 rdata->offset_delta.lo =
6421 cpu_to_le32(U64_LO(set_timesync_params->offset_delta));
6422 rdata->offset_delta.hi =
6423 cpu_to_le32(U64_HI(set_timesync_params->offset_delta));
6424
6425 DP(BNX2X_MSG_SP, "Set timesync command params: drift_cmd = %d, offset_cmd = %d, add_sub_drift = %d, drift_val = %d, drift_period = %d, offset_lo = %d, offset_hi = %d\n",
6426 rdata->drift_adjust_cmd, rdata->offset_cmd,
6427 rdata->add_sub_drift_adjust_value, rdata->drift_adjust_value,
6428 rdata->drift_adjust_period, rdata->offset_delta.lo,
6429 rdata->offset_delta.hi);
6430
6431 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_TIMESYNC, 0,
6432 U64_HI(data_mapping),
6433 U64_LO(data_mapping), NONE_CONNECTION_TYPE);
6434 }
6435
6436 static int bnx2x_func_send_cmd(struct bnx2x *bp,
6437 struct bnx2x_func_state_params *params)
6438 {
6439 switch (params->cmd) {
6440 case BNX2X_F_CMD_HW_INIT:
6441 return bnx2x_func_hw_init(bp, params);
6442 case BNX2X_F_CMD_START:
6443 return bnx2x_func_send_start(bp, params);
6444 case BNX2X_F_CMD_STOP:
6445 return bnx2x_func_send_stop(bp, params);
6446 case BNX2X_F_CMD_HW_RESET:
6447 return bnx2x_func_hw_reset(bp, params);
6448 case BNX2X_F_CMD_AFEX_UPDATE:
6449 return bnx2x_func_send_afex_update(bp, params);
6450 case BNX2X_F_CMD_AFEX_VIFLISTS:
6451 return bnx2x_func_send_afex_viflists(bp, params);
6452 case BNX2X_F_CMD_TX_STOP:
6453 return bnx2x_func_send_tx_stop(bp, params);
6454 case BNX2X_F_CMD_TX_START:
6455 return bnx2x_func_send_tx_start(bp, params);
6456 case BNX2X_F_CMD_SWITCH_UPDATE:
6457 return bnx2x_func_send_switch_update(bp, params);
6458 case BNX2X_F_CMD_SET_TIMESYNC:
6459 return bnx2x_func_send_set_timesync(bp, params);
6460 default:
6461 BNX2X_ERR("Unknown command: %d\n", params->cmd);
6462 return -EINVAL;
6463 }
6464 }
6465
6466 void bnx2x_init_func_obj(struct bnx2x *bp,
6467 struct bnx2x_func_sp_obj *obj,
6468 void *rdata, dma_addr_t rdata_mapping,
6469 void *afex_rdata, dma_addr_t afex_rdata_mapping,
6470 struct bnx2x_func_sp_drv_ops *drv_iface)
6471 {
6472 memset(obj, 0, sizeof(*obj));
6473
6474 mutex_init(&obj->one_pending_mutex);
6475
6476 obj->rdata = rdata;
6477 obj->rdata_mapping = rdata_mapping;
6478 obj->afex_rdata = afex_rdata;
6479 obj->afex_rdata_mapping = afex_rdata_mapping;
6480 obj->send_cmd = bnx2x_func_send_cmd;
6481 obj->check_transition = bnx2x_func_chk_transition;
6482 obj->complete_cmd = bnx2x_func_comp_cmd;
6483 obj->wait_comp = bnx2x_func_wait_comp;
6484
6485 obj->drv = drv_iface;
6486 }
6487
6488
6489
6490
6491
6492
6493
6494
6495
6496
6497
6498
6499
6500
6501 int bnx2x_func_state_change(struct bnx2x *bp,
6502 struct bnx2x_func_state_params *params)
6503 {
6504 struct bnx2x_func_sp_obj *o = params->f_obj;
6505 int rc, cnt = 300;
6506 enum bnx2x_func_cmd cmd = params->cmd;
6507 unsigned long *pending = &o->pending;
6508
6509 mutex_lock(&o->one_pending_mutex);
6510
6511
6512 rc = o->check_transition(bp, o, params);
6513 if ((rc == -EBUSY) &&
6514 (test_bit(RAMROD_RETRY, ¶ms->ramrod_flags))) {
6515 while ((rc == -EBUSY) && (--cnt > 0)) {
6516 mutex_unlock(&o->one_pending_mutex);
6517 msleep(10);
6518 mutex_lock(&o->one_pending_mutex);
6519 rc = o->check_transition(bp, o, params);
6520 }
6521 if (rc == -EBUSY) {
6522 mutex_unlock(&o->one_pending_mutex);
6523 BNX2X_ERR("timeout waiting for previous ramrod completion\n");
6524 return rc;
6525 }
6526 } else if (rc) {
6527 mutex_unlock(&o->one_pending_mutex);
6528 return rc;
6529 }
6530
6531
6532 set_bit(cmd, pending);
6533
6534
6535 if (test_bit(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) {
6536 bnx2x_func_state_change_comp(bp, o, cmd);
6537 mutex_unlock(&o->one_pending_mutex);
6538 } else {
6539
6540 rc = o->send_cmd(bp, params);
6541
6542 mutex_unlock(&o->one_pending_mutex);
6543
6544 if (rc) {
6545 o->next_state = BNX2X_F_STATE_MAX;
6546 clear_bit(cmd, pending);
6547 smp_mb__after_atomic();
6548 return rc;
6549 }
6550
6551 if (test_bit(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) {
6552 rc = o->wait_comp(bp, o, cmd);
6553 if (rc)
6554 return rc;
6555
6556 return 0;
6557 }
6558 }
6559
6560 return !!test_bit(cmd, pending);
6561 }