This source file includes following definitions.
- bnx2x_bits_en
- bnx2x_bits_dis
- bnx2x_check_lfa
- bnx2x_get_epio
- bnx2x_set_epio
- bnx2x_set_cfg_pin
- bnx2x_get_cfg_pin
- bnx2x_ets_e2e3a0_disabled
- bnx2x_ets_get_min_w_val_nig
- bnx2x_ets_get_credit_upper_bound
- bnx2x_ets_e3b0_set_credit_upper_bound_nig
- bnx2x_ets_e3b0_nig_disabled
- bnx2x_ets_e3b0_set_credit_upper_bound_pbf
- bnx2x_ets_e3b0_pbf_disabled
- bnx2x_ets_e3b0_disabled
- bnx2x_ets_disabled
- bnx2x_ets_e3b0_cli_map
- bnx2x_ets_e3b0_set_cos_bw
- bnx2x_ets_e3b0_get_total_bw
- bnx2x_ets_e3b0_sp_pri_to_cos_init
- bnx2x_ets_e3b0_sp_pri_to_cos_set
- bnx2x_e3b0_sp_get_pri_cli_reg
- bnx2x_e3b0_sp_get_pri_cli_reg_nig
- bnx2x_e3b0_sp_get_pri_cli_reg_pbf
- bnx2x_ets_e3b0_sp_set_pri_cli_reg
- bnx2x_ets_e3b0_config
- bnx2x_ets_bw_limit_common
- bnx2x_ets_bw_limit
- bnx2x_ets_strict
- bnx2x_update_pfc_xmac
- bnx2x_set_mdio_clk
- bnx2x_set_mdio_emac_per_phy
- bnx2x_is_4_port_mode
- bnx2x_emac_init
- bnx2x_set_xumac_nig
- bnx2x_set_umac_rxtx
- bnx2x_umac_enable
- bnx2x_xmac_init
- bnx2x_set_xmac_rxtx
- bnx2x_xmac_enable
- bnx2x_emac_enable
- bnx2x_update_pfc_bmac1
- bnx2x_update_pfc_bmac2
- bnx2x_pfc_nig_rx_priority_mask
- bnx2x_update_mng
- bnx2x_update_link_attr
- bnx2x_update_pfc_nig
- bnx2x_update_pfc
- bnx2x_bmac1_enable
- bnx2x_bmac2_enable
- bnx2x_bmac_enable
- bnx2x_set_bmac_rx
- bnx2x_pbf_update
- bnx2x_get_emac_base
- bnx2x_cl22_write
- bnx2x_cl22_read
- bnx2x_cl45_read
- bnx2x_cl45_write
- bnx2x_eee_has_cap
- bnx2x_eee_nvram_to_time
- bnx2x_eee_time_to_nvram
- bnx2x_eee_calc_timer
- bnx2x_eee_set_timers
- bnx2x_eee_initial_config
- bnx2x_eee_disable
- bnx2x_eee_advertise
- bnx2x_update_mng_eee
- bnx2x_eee_an_resolve
- bnx2x_bsc_module_sel
- bnx2x_bsc_read
- bnx2x_cl45_read_or_write
- bnx2x_cl45_read_and_write
- bnx2x_phy_read
- bnx2x_phy_write
- bnx2x_get_warpcore_lane
- bnx2x_set_aer_mmd
- bnx2x_set_serdes_access
- bnx2x_serdes_deassert
- bnx2x_xgxs_specific_func
- bnx2x_xgxs_deassert
- bnx2x_calc_ieee_aneg_adv
- set_phy_vars
- bnx2x_ext_phy_set_pause
- bnx2x_pause_resolve
- bnx2x_ext_phy_update_adv_fc
- bnx2x_ext_phy_resolve_fc
- bnx2x_warpcore_enable_AN_KR2
- bnx2x_disable_kr2
- bnx2x_warpcore_set_lpi_passthrough
- bnx2x_warpcore_restart_AN_KR
- bnx2x_warpcore_enable_AN_KR
- bnx2x_warpcore_set_10G_KR
- bnx2x_warpcore_set_10G_XFI
- bnx2x_warpcore_set_20G_force_KR2
- bnx2x_warpcore_set_20G_DXGXS
- bnx2x_warpcore_set_sgmii_speed
- bnx2x_warpcore_reset_lane
- bnx2x_warpcore_clear_regs
- bnx2x_get_mod_abs_int_cfg
- bnx2x_is_sfp_module_plugged
- bnx2x_warpcore_get_sigdet
- bnx2x_warpcore_config_runtime
- bnx2x_warpcore_config_sfi
- bnx2x_sfp_e3_set_transmitter
- bnx2x_warpcore_config_init
- bnx2x_warpcore_link_reset
- bnx2x_set_warpcore_loopback
- bnx2x_sync_link
- bnx2x_link_status_update
- bnx2x_set_master_ln
- bnx2x_reset_unicore
- bnx2x_set_swap_lanes
- bnx2x_set_parallel_detection
- bnx2x_set_autoneg
- bnx2x_program_serdes
- bnx2x_set_brcm_cl37_advertisement
- bnx2x_set_ieee_aneg_advertisement
- bnx2x_restart_autoneg
- bnx2x_initialize_sgmii_process
- bnx2x_direct_parallel_detect_used
- bnx2x_update_adv_fc
- bnx2x_flow_ctrl_resolve
- bnx2x_check_fallback_to_cl37
- bnx2x_xgxs_an_resolve
- bnx2x_get_link_speed_duplex
- bnx2x_link_settings_status
- bnx2x_warpcore_read_status
- bnx2x_set_gmii_tx_driver
- bnx2x_emac_program
- bnx2x_set_preemphasis
- bnx2x_xgxs_config_init
- bnx2x_prepare_xgxs
- bnx2x_wait_reset_complete
- bnx2x_link_int_enable
- bnx2x_rearm_latch_signal
- bnx2x_link_int_ack
- bnx2x_null_format_ver
- bnx2x_format_ver
- bnx2x_3_seq_format_ver
- bnx2x_get_ext_phy_fw_version
- bnx2x_set_xgxs_loopback
- bnx2x_set_led
- bnx2x_test_link
- bnx2x_link_initialize
- bnx2x_int_link_reset
- bnx2x_common_ext_link_reset
- bnx2x_update_link_down
- bnx2x_update_link_up
- bnx2x_chng_link_count
- bnx2x_link_update
- bnx2x_ext_phy_hw_reset
- bnx2x_save_spirom_version
- bnx2x_save_bcm_spirom_ver
- bnx2x_ext_phy_10G_an_resolve
- bnx2x_8073_resolve_fc
- bnx2x_8073_8727_external_rom_boot
- bnx2x_8073_is_snr_needed
- bnx2x_8073_xaui_wa
- bnx2x_807x_force_10G
- bnx2x_8073_set_pause_cl37
- bnx2x_8073_specific_func
- bnx2x_8073_config_init
- bnx2x_8073_read_status
- bnx2x_8073_link_reset
- bnx2x_8705_config_init
- bnx2x_8705_read_status
- bnx2x_set_disable_pmd_transmit
- bnx2x_get_gpio_port
- bnx2x_sfp_e1e2_set_transmitter
- bnx2x_sfp_set_transmitter
- bnx2x_8726_read_sfp_module_eeprom
- bnx2x_warpcore_power_module
- bnx2x_warpcore_read_sfp_module_eeprom
- bnx2x_8727_read_sfp_module_eeprom
- bnx2x_read_sfp_module_eeprom
- bnx2x_get_edc_mode
- bnx2x_verify_sfp_module
- bnx2x_wait_for_sfp_module_initialized
- bnx2x_8727_power_module
- bnx2x_8726_set_limiting_mode
- bnx2x_8727_set_limiting_mode
- bnx2x_8727_specific_func
- bnx2x_set_e1e2_module_fault_led
- bnx2x_set_e3_module_fault_led
- bnx2x_set_sfp_module_fault_led
- bnx2x_warpcore_hw_reset
- bnx2x_power_sfp_module
- bnx2x_warpcore_set_limiting_mode
- bnx2x_set_limiting_mode
- bnx2x_sfp_module_detection
- bnx2x_handle_module_detect_int
- bnx2x_sfp_mask_fault
- bnx2x_8706_8726_read_status
- bnx2x_8706_config_init
- bnx2x_8706_read_status
- bnx2x_8726_config_loopback
- bnx2x_8726_external_rom_boot
- bnx2x_8726_read_status
- bnx2x_8726_config_init
- bnx2x_8726_link_reset
- bnx2x_8727_set_link_led
- bnx2x_8727_hw_reset
- bnx2x_8727_config_speed
- bnx2x_8727_config_init
- bnx2x_8727_handle_mod_abs
- bnx2x_8727_read_status
- bnx2x_8727_link_reset
- bnx2x_is_8483x_8485x
- bnx2x_save_848xx_spirom_version
- bnx2x_848xx_set_led
- bnx2x_848xx_specific_func
- bnx2x_848xx_cmn_config_init
- bnx2x_8481_config_init
- bnx2x_84858_cmd_hdlr
- bnx2x_84833_cmd_hdlr
- bnx2x_848xx_cmd_hdlr
- bnx2x_848xx_pair_swap_cfg
- bnx2x_84833_get_reset_gpios
- bnx2x_84833_hw_reset_phy
- bnx2x_8483x_disable_eee
- bnx2x_8483x_enable_eee
- bnx2x_848x3_config_init
- bnx2x_848xx_read_status
- bnx2x_8485x_format_ver
- bnx2x_848xx_format_ver
- bnx2x_8481_hw_reset
- bnx2x_8481_link_reset
- bnx2x_848x3_link_reset
- bnx2x_848xx_set_link_led
- bnx2x_54618se_specific_func
- bnx2x_54618se_config_init
- bnx2x_5461x_set_link_led
- bnx2x_54618se_link_reset
- bnx2x_54618se_read_status
- bnx2x_54618se_config_loopback
- bnx2x_7101_config_loopback
- bnx2x_7101_config_init
- bnx2x_7101_read_status
- bnx2x_7101_format_ver
- bnx2x_sfx7101_sp_sw_reset
- bnx2x_7101_hw_reset
- bnx2x_7101_set_link_led
- bnx2x_populate_preemphasis
- bnx2x_get_ext_phy_config
- bnx2x_populate_int_phy
- bnx2x_populate_ext_phy
- bnx2x_populate_phy
- bnx2x_phy_def_cfg
- bnx2x_phy_selection
- bnx2x_phy_probe
- bnx2x_init_bmac_loopback
- bnx2x_init_emac_loopback
- bnx2x_init_xmac_loopback
- bnx2x_init_umac_loopback
- bnx2x_init_xgxs_loopback
- bnx2x_set_rx_filter
- bnx2x_avoid_link_flap
- bnx2x_cannot_avoid_link_flap
- bnx2x_phy_init
- bnx2x_link_reset
- bnx2x_lfa_reset
- bnx2x_8073_common_init_phy
- bnx2x_8726_common_init_phy
- bnx2x_get_ext_phy_reset_gpio
- bnx2x_8727_common_init_phy
- bnx2x_84833_common_init_phy
- bnx2x_ext_phy_common_init
- bnx2x_common_init_phy
- bnx2x_check_over_curr
- bnx2x_analyze_link_error
- bnx2x_check_half_open_conn
- bnx2x_sfp_tx_fault_detection
- bnx2x_kr2_recovery
- bnx2x_check_kr2_wa
- bnx2x_period_func
- bnx2x_fan_failure_det_req
- bnx2x_hw_reset_phy
- bnx2x_init_mod_abs_int
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18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/kernel.h>
22 #include <linux/errno.h>
23 #include <linux/pci.h>
24 #include <linux/netdevice.h>
25 #include <linux/delay.h>
26 #include <linux/ethtool.h>
27 #include <linux/mutex.h>
28
29 #include "bnx2x.h"
30 #include "bnx2x_cmn.h"
31
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
33 struct link_params *params,
34 u8 dev_addr, u16 addr, u8 byte_cnt,
35 u8 *o_buf, u8);
36
37 #define MDIO_ACCESS_TIMEOUT 1000
38 #define WC_LANE_MAX 4
39 #define I2C_SWITCH_WIDTH 2
40 #define I2C_BSC0 0
41 #define I2C_BSC1 1
42 #define I2C_WA_RETRY_CNT 3
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
44 #define MCPR_IMC_COMMAND_READ_OP 1
45 #define MCPR_IMC_COMMAND_WRITE_OP 2
46
47
48 #define LED_BLINK_RATE_VAL_E3 354
49 #define LED_BLINK_RATE_VAL_E1X_E2 480
50
51
52
53
54 #define NIG_LATCH_BC_ENABLE_MI_INT 0
55
56 #define NIG_STATUS_EMAC0_MI_INT \
57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
58 #define NIG_STATUS_XGXS0_LINK10G \
59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
60 #define NIG_STATUS_XGXS0_LINK_STATUS \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
64 #define NIG_STATUS_SERDES0_LINK_STATUS \
65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
66 #define NIG_MASK_MI_INT \
67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
68 #define NIG_MASK_XGXS0_LINK10G \
69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
70 #define NIG_MASK_XGXS0_LINK_STATUS \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
72 #define NIG_MASK_SERDES0_LINK_STATUS \
73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
74
75 #define MDIO_AN_CL73_OR_37_COMPLETE \
76 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
77 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
78
79 #define XGXS_RESET_BITS \
80 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
84 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
85
86 #define SERDES_RESET_BITS \
87 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
91
92 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
93 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
94 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
95 #define AUTONEG_PARALLEL \
96 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
97 #define AUTONEG_SGMII_FIBER_AUTODET \
98 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
99 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
100
101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
105 #define GP_STATUS_SPEED_MASK \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
107 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
108 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
109 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
110 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
111 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
112 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
113 #define GP_STATUS_10G_HIG \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
115 #define GP_STATUS_10G_CX4 \
116 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
118 #define GP_STATUS_10G_KX4 \
119 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
121 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
123 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
124 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
125 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
126 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
127 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
128 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
129 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
130 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
131 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
132 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
133 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
134 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
135 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
136 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
137 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
138 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
139 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
140
141 #define LINK_UPDATE_MASK \
142 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
143 LINK_STATUS_LINK_UP | \
144 LINK_STATUS_PHYSICAL_LINK_FLAG | \
145 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
146 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
147 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
148 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
149 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
150 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
151
152 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
153 #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
154 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
155 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
156 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
157
158
159 #define SFP_EEPROM_10G_COMP_CODE_ADDR 0x3
160 #define SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4)
161 #define SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5)
162 #define SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6)
163
164 #define SFP_EEPROM_1G_COMP_CODE_ADDR 0x6
165 #define SFP_EEPROM_1G_COMP_CODE_SX (1<<0)
166 #define SFP_EEPROM_1G_COMP_CODE_LX (1<<1)
167 #define SFP_EEPROM_1G_COMP_CODE_CX (1<<2)
168 #define SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3)
169
170 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
171 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
172 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
173
174 #define SFP_EEPROM_OPTIONS_ADDR 0x40
175 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
176 #define SFP_EEPROM_OPTIONS_SIZE 2
177
178 #define EDC_MODE_LINEAR 0x0022
179 #define EDC_MODE_LIMITING 0x0044
180 #define EDC_MODE_PASSIVE_DAC 0x0055
181 #define EDC_MODE_ACTIVE_DAC 0x0066
182
183
184 #define DCBX_INVALID_COS (0xFF)
185
186 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
187 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
188 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
189 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
190 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
191
192 #define MAX_PACKET_SIZE (9700)
193 #define MAX_KR_LINK_RETRY 4
194 #define DEFAULT_TX_DRV_BRDCT 2
195 #define DEFAULT_TX_DRV_IFIR 0
196 #define DEFAULT_TX_DRV_POST2 3
197 #define DEFAULT_TX_DRV_IPRE_DRIVER 6
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202
203 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
204 bnx2x_cl45_write(_bp, _phy, \
205 (_phy)->def_md_devad, \
206 (_bank + (_addr & 0xf)), \
207 _val)
208
209 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
210 bnx2x_cl45_read(_bp, _phy, \
211 (_phy)->def_md_devad, \
212 (_bank + (_addr & 0xf)), \
213 _val)
214
215 static int bnx2x_check_half_open_conn(struct link_params *params,
216 struct link_vars *vars, u8 notify);
217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
218 struct link_params *params);
219
220 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
221 {
222 u32 val = REG_RD(bp, reg);
223
224 val |= bits;
225 REG_WR(bp, reg, val);
226 return val;
227 }
228
229 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
230 {
231 u32 val = REG_RD(bp, reg);
232
233 val &= ~bits;
234 REG_WR(bp, reg, val);
235 return val;
236 }
237
238
239
240
241
242
243
244
245
246 static int bnx2x_check_lfa(struct link_params *params)
247 {
248 u32 link_status, cfg_idx, lfa_mask, cfg_size;
249 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
250 u32 saved_val, req_val, eee_status;
251 struct bnx2x *bp = params->bp;
252
253 additional_config =
254 REG_RD(bp, params->lfa_base +
255 offsetof(struct shmem_lfa, additional_config));
256
257
258
259
260 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
261 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
262 REG_WR(bp, params->lfa_base +
263 offsetof(struct shmem_lfa, additional_config),
264 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
265 return LFA_DCC_LFA_DISABLED;
266 }
267
268
269 link_status = REG_RD(bp, params->shmem_base +
270 offsetof(struct shmem_region,
271 port_mb[params->port].link_status));
272 if (!(link_status & LINK_STATUS_LINK_UP))
273 return LFA_LINK_DOWN;
274
275
276
277
278 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
279 return 0;
280
281
282 if (params->loopback_mode)
283 return LFA_LOOPBACK_ENABLED;
284
285
286 if (!params->lfa_base)
287 return LFA_MFW_IS_TOO_OLD;
288
289 if (params->num_phys == 3) {
290 cfg_size = 2;
291 lfa_mask = 0xffffffff;
292 } else {
293 cfg_size = 1;
294 lfa_mask = 0xffff;
295 }
296
297
298 saved_val = REG_RD(bp, params->lfa_base +
299 offsetof(struct shmem_lfa, req_duplex));
300 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
301 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
302 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
303 (saved_val & lfa_mask), (req_val & lfa_mask));
304 return LFA_DUPLEX_MISMATCH;
305 }
306
307 saved_val = REG_RD(bp, params->lfa_base +
308 offsetof(struct shmem_lfa, req_flow_ctrl));
309 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
310 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
311 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
312 (saved_val & lfa_mask), (req_val & lfa_mask));
313 return LFA_FLOW_CTRL_MISMATCH;
314 }
315
316 saved_val = REG_RD(bp, params->lfa_base +
317 offsetof(struct shmem_lfa, req_line_speed));
318 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
319 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
320 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
321 (saved_val & lfa_mask), (req_val & lfa_mask));
322 return LFA_LINK_SPEED_MISMATCH;
323 }
324
325 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
326 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
327 offsetof(struct shmem_lfa,
328 speed_cap_mask[cfg_idx]));
329
330 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
331 DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
332 cur_speed_cap_mask,
333 params->speed_cap_mask[cfg_idx]);
334 return LFA_SPEED_CAP_MISMATCH;
335 }
336 }
337
338 cur_req_fc_auto_adv =
339 REG_RD(bp, params->lfa_base +
340 offsetof(struct shmem_lfa, additional_config)) &
341 REQ_FC_AUTO_ADV_MASK;
342
343 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
344 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
345 cur_req_fc_auto_adv, params->req_fc_auto_adv);
346 return LFA_FLOW_CTRL_MISMATCH;
347 }
348
349 eee_status = REG_RD(bp, params->shmem2_base +
350 offsetof(struct shmem2_region,
351 eee_status[params->port]));
352
353 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
354 (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
355 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
356 (params->eee_mode & EEE_MODE_ADV_LPI))) {
357 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
358 eee_status);
359 return LFA_EEE_MISMATCH;
360 }
361
362
363 return 0;
364 }
365
366
367
368 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
369 {
370 u32 epio_mask, gp_oenable;
371 *en = 0;
372
373 if (epio_pin > 31) {
374 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
375 return;
376 }
377
378 epio_mask = 1 << epio_pin;
379
380 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
381 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
382
383 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
384 }
385 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
386 {
387 u32 epio_mask, gp_output, gp_oenable;
388
389
390 if (epio_pin > 31) {
391 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
392 return;
393 }
394 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
395 epio_mask = 1 << epio_pin;
396
397 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
398 if (en)
399 gp_output |= epio_mask;
400 else
401 gp_output &= ~epio_mask;
402
403 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
404
405
406 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
407 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
408 }
409
410 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
411 {
412 if (pin_cfg == PIN_CFG_NA)
413 return;
414 if (pin_cfg >= PIN_CFG_EPIO0) {
415 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
416 } else {
417 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
418 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
419 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
420 }
421 }
422
423 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
424 {
425 if (pin_cfg == PIN_CFG_NA)
426 return -EINVAL;
427 if (pin_cfg >= PIN_CFG_EPIO0) {
428 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
429 } else {
430 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
431 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
432 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
433 }
434 return 0;
435
436 }
437
438
439
440 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
441 {
442
443 struct bnx2x *bp = params->bp;
444
445 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
446
447
448
449
450
451
452
453
454 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
455
456
457
458
459
460
461
462
463 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
464
465 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
466
467
468
469 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
470
471
472
473 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
474 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
475 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
476
477 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
478 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
479 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
480
481 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
482
483
484
485 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
486 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
487
488 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
489 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
490
491 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
492 }
493
494
495
496
497
498 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
499 {
500 u32 min_w_val = 0;
501
502 if (vars->link_up) {
503 if (vars->line_speed == SPEED_20000)
504 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
505 else
506 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
507 } else
508 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
509
510
511
512 return min_w_val;
513 }
514
515
516
517
518
519 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
520 {
521 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
522 MAX_PACKET_SIZE);
523 return credit_upper_bound;
524 }
525
526
527
528
529
530 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
531 const struct link_params *params,
532 const u32 min_w_val)
533 {
534 struct bnx2x *bp = params->bp;
535 const u8 port = params->port;
536 const u32 credit_upper_bound =
537 bnx2x_ets_get_credit_upper_bound(min_w_val);
538
539 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
540 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
541 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
542 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
543 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
544 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
546 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
548 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
550 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
551
552 if (!port) {
553 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
554 credit_upper_bound);
555 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
556 credit_upper_bound);
557 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
558 credit_upper_bound);
559 }
560 }
561
562
563
564
565
566
567
568
569 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
570 const struct link_vars *vars)
571 {
572 struct bnx2x *bp = params->bp;
573 const u8 port = params->port;
574 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
575
576
577
578
579
580 if (port) {
581 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
582 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
583 } else {
584 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
585 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
586 }
587
588
589
590 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
591 NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
592
593
594
595 if (port) {
596
597 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
598 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
599 } else {
600
601 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
602 0x43210876);
603 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
604 }
605
606
607
608
609
610
611
612
613 if (port)
614 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
615 else
616 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
617
618 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
619 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
620
621
622
623
624
625
626
627 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
628 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
629 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
630 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
631 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
632 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
634 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
636 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
638 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
639 if (!port) {
640 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
641 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
642 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
643 }
644
645 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
646 }
647
648
649
650
651
652 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
653 const struct link_params *params,
654 const u32 min_w_val)
655 {
656 struct bnx2x *bp = params->bp;
657 const u32 credit_upper_bound =
658 bnx2x_ets_get_credit_upper_bound(min_w_val);
659 const u8 port = params->port;
660 u32 base_upper_bound = 0;
661 u8 max_cos = 0;
662 u8 i = 0;
663
664
665
666 if (!port) {
667 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
668 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
669 } else {
670 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
671 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
672 }
673
674 for (i = 0; i < max_cos; i++)
675 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
676 }
677
678
679
680
681
682
683
684
685
686 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
687 {
688 struct bnx2x *bp = params->bp;
689 const u8 port = params->port;
690 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
691 u8 i = 0;
692 u32 base_weight = 0;
693 u8 max_cos = 0;
694
695
696
697
698
699 if (port)
700
701 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
702 else
703
704 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
705
706
707 if (port)
708
709 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
710 else
711
712 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
713
714 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
715 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
716
717
718 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
719 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
720
721 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
722 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
723
724
725
726 if (!port) {
727 base_weight = PBF_REG_COS0_WEIGHT_P0;
728 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
729 } else {
730 base_weight = PBF_REG_COS0_WEIGHT_P1;
731 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
732 }
733
734 for (i = 0; i < max_cos; i++)
735 REG_WR(bp, base_weight + (0x4 * i), 0);
736
737 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
738 }
739
740
741
742
743
744 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
745 const struct link_vars *vars)
746 {
747 struct bnx2x *bp = params->bp;
748
749 if (!CHIP_IS_E3B0(bp)) {
750 DP(NETIF_MSG_LINK,
751 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
752 return -EINVAL;
753 }
754
755 bnx2x_ets_e3b0_nig_disabled(params, vars);
756
757 bnx2x_ets_e3b0_pbf_disabled(params);
758
759 return 0;
760 }
761
762
763
764
765
766
767 int bnx2x_ets_disabled(struct link_params *params,
768 struct link_vars *vars)
769 {
770 struct bnx2x *bp = params->bp;
771 int bnx2x_status = 0;
772
773 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
774 bnx2x_ets_e2e3a0_disabled(params);
775 else if (CHIP_IS_E3B0(bp))
776 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
777 else {
778 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
779 return -EINVAL;
780 }
781
782 return bnx2x_status;
783 }
784
785
786
787
788
789
790 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
791 const struct bnx2x_ets_params *ets_params,
792 const u8 cos_sp_bitmap,
793 const u8 cos_bw_bitmap)
794 {
795 struct bnx2x *bp = params->bp;
796 const u8 port = params->port;
797 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
798 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
799 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
800 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
801
802 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
803 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
804
805 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
806 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
807
808 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
809 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
810 nig_cli_subject2wfq_bitmap);
811
812 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
813 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
814 pbf_cli_subject2wfq_bitmap);
815
816 return 0;
817 }
818
819
820
821
822
823
824 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
825 const u8 cos_entry,
826 const u32 min_w_val_nig,
827 const u32 min_w_val_pbf,
828 const u16 total_bw,
829 const u8 bw,
830 const u8 port)
831 {
832 u32 nig_reg_adress_crd_weight = 0;
833 u32 pbf_reg_adress_crd_weight = 0;
834
835 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
836 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
837
838 switch (cos_entry) {
839 case 0:
840 nig_reg_adress_crd_weight =
841 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
842 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
843 pbf_reg_adress_crd_weight = (port) ?
844 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
845 break;
846 case 1:
847 nig_reg_adress_crd_weight = (port) ?
848 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
849 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
850 pbf_reg_adress_crd_weight = (port) ?
851 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
852 break;
853 case 2:
854 nig_reg_adress_crd_weight = (port) ?
855 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
856 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
857
858 pbf_reg_adress_crd_weight = (port) ?
859 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
860 break;
861 case 3:
862 if (port)
863 return -EINVAL;
864 nig_reg_adress_crd_weight = NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
865 pbf_reg_adress_crd_weight = PBF_REG_COS3_WEIGHT_P0;
866 break;
867 case 4:
868 if (port)
869 return -EINVAL;
870 nig_reg_adress_crd_weight = NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
871 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
872 break;
873 case 5:
874 if (port)
875 return -EINVAL;
876 nig_reg_adress_crd_weight = NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
877 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
878 break;
879 }
880
881 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
882
883 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
884
885 return 0;
886 }
887
888
889
890
891
892 static int bnx2x_ets_e3b0_get_total_bw(
893 const struct link_params *params,
894 struct bnx2x_ets_params *ets_params,
895 u16 *total_bw)
896 {
897 struct bnx2x *bp = params->bp;
898 u8 cos_idx = 0;
899 u8 is_bw_cos_exist = 0;
900
901 *total_bw = 0 ;
902
903 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
904 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
905 is_bw_cos_exist = 1;
906 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
907 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
908 "was set to 0\n");
909
910
911
912 ets_params->cos[cos_idx].params.bw_params.bw
913 = 1;
914 }
915 *total_bw +=
916 ets_params->cos[cos_idx].params.bw_params.bw;
917 }
918 }
919
920
921 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
922 if (*total_bw == 0) {
923 DP(NETIF_MSG_LINK,
924 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
925 return -EINVAL;
926 }
927 DP(NETIF_MSG_LINK,
928 "bnx2x_ets_E3B0_config total BW should be 100\n");
929
930
931
932 }
933 return 0;
934 }
935
936
937
938
939
940
941 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
942 {
943 u8 pri = 0;
944 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
945 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
946 }
947
948
949
950
951
952
953 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
954 u8 *sp_pri_to_cos, const u8 pri,
955 const u8 cos_entry)
956 {
957 struct bnx2x *bp = params->bp;
958 const u8 port = params->port;
959 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
960 DCBX_E3B0_MAX_NUM_COS_PORT0;
961
962 if (pri >= max_num_of_cos) {
963 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
964 "parameter Illegal strict priority\n");
965 return -EINVAL;
966 }
967
968 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
969 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
970 "parameter There can't be two COS's with "
971 "the same strict pri\n");
972 return -EINVAL;
973 }
974
975 sp_pri_to_cos[pri] = cos_entry;
976 return 0;
977
978 }
979
980
981
982
983
984
985
986 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
987 const u8 pri_set,
988 const u8 pri_offset,
989 const u8 entry_size)
990 {
991 u64 pri_cli_nig = 0;
992 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
993 (pri_set + pri_offset));
994
995 return pri_cli_nig;
996 }
997
998
999
1000
1001
1002
1003 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
1004 {
1005
1006 const u8 nig_cos_offset = 3;
1007 const u8 nig_pri_offset = 3;
1008
1009 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1010 nig_pri_offset, 4);
1011
1012 }
1013
1014
1015
1016
1017
1018
1019 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1020 {
1021 const u8 pbf_cos_offset = 0;
1022 const u8 pbf_pri_offset = 0;
1023
1024 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1025 pbf_pri_offset, 3);
1026
1027 }
1028
1029
1030
1031
1032
1033
1034
1035 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1036 u8 *sp_pri_to_cos)
1037 {
1038 struct bnx2x *bp = params->bp;
1039 u8 i = 0;
1040 const u8 port = params->port;
1041
1042 u64 pri_cli_nig = 0x210;
1043 u32 pri_cli_pbf = 0x0;
1044 u8 pri_set = 0;
1045 u8 pri_bitmask = 0;
1046 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1047 DCBX_E3B0_MAX_NUM_COS_PORT0;
1048
1049 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1050
1051
1052 for (i = 0; i < max_num_of_cos; i++) {
1053 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1054 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1055 DP(NETIF_MSG_LINK,
1056 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1057 "invalid cos entry\n");
1058 return -EINVAL;
1059 }
1060
1061 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1062 sp_pri_to_cos[i], pri_set);
1063
1064 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1065 sp_pri_to_cos[i], pri_set);
1066 pri_bitmask = 1 << sp_pri_to_cos[i];
1067
1068 if (!(pri_bitmask & cos_bit_to_set)) {
1069 DP(NETIF_MSG_LINK,
1070 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1071 "invalid There can't be two COS's with"
1072 " the same strict pri\n");
1073 return -EINVAL;
1074 }
1075 cos_bit_to_set &= ~pri_bitmask;
1076 pri_set++;
1077 }
1078 }
1079
1080
1081 for (i = 0; i < max_num_of_cos; i++) {
1082 pri_bitmask = 1 << i;
1083
1084 if (pri_bitmask & cos_bit_to_set) {
1085
1086 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1087 i, pri_set);
1088
1089 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1090 i, pri_set);
1091
1092 cos_bit_to_set &= ~pri_bitmask;
1093 pri_set++;
1094 }
1095 }
1096
1097 if (pri_set != max_num_of_cos) {
1098 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1099 "entries were set\n");
1100 return -EINVAL;
1101 }
1102
1103 if (port) {
1104
1105 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1106 (u32)pri_cli_nig);
1107
1108 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1109 } else {
1110
1111 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1112 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1113
1114 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1115 pri_cli_nig_lsb);
1116 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1117 pri_cli_nig_msb);
1118
1119 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1120 }
1121 return 0;
1122 }
1123
1124
1125
1126
1127
1128 int bnx2x_ets_e3b0_config(const struct link_params *params,
1129 const struct link_vars *vars,
1130 struct bnx2x_ets_params *ets_params)
1131 {
1132 struct bnx2x *bp = params->bp;
1133 int bnx2x_status = 0;
1134 const u8 port = params->port;
1135 u16 total_bw = 0;
1136 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1137 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1138 u8 cos_bw_bitmap = 0;
1139 u8 cos_sp_bitmap = 0;
1140 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1141 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1142 DCBX_E3B0_MAX_NUM_COS_PORT0;
1143 u8 cos_entry = 0;
1144
1145 if (!CHIP_IS_E3B0(bp)) {
1146 DP(NETIF_MSG_LINK,
1147 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1148 return -EINVAL;
1149 }
1150
1151 if ((ets_params->num_of_cos > max_num_of_cos)) {
1152 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1153 "isn't supported\n");
1154 return -EINVAL;
1155 }
1156
1157
1158 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1159
1160
1161 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1162 &total_bw);
1163 if (bnx2x_status) {
1164 DP(NETIF_MSG_LINK,
1165 "bnx2x_ets_E3B0_config get_total_bw failed\n");
1166 return -EINVAL;
1167 }
1168
1169
1170
1171
1172 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1173 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1174
1175
1176 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1177 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1178 cos_bw_bitmap |= (1 << cos_entry);
1179
1180
1181
1182 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1183 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1184 total_bw,
1185 ets_params->cos[cos_entry].params.bw_params.bw,
1186 port);
1187 } else if (bnx2x_cos_state_strict ==
1188 ets_params->cos[cos_entry].state){
1189 cos_sp_bitmap |= (1 << cos_entry);
1190
1191 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1192 params,
1193 sp_pri_to_cos,
1194 ets_params->cos[cos_entry].params.sp_params.pri,
1195 cos_entry);
1196
1197 } else {
1198 DP(NETIF_MSG_LINK,
1199 "bnx2x_ets_e3b0_config cos state not valid\n");
1200 return -EINVAL;
1201 }
1202 if (bnx2x_status) {
1203 DP(NETIF_MSG_LINK,
1204 "bnx2x_ets_e3b0_config set cos bw failed\n");
1205 return bnx2x_status;
1206 }
1207 }
1208
1209
1210 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1211 sp_pri_to_cos);
1212
1213 if (bnx2x_status) {
1214 DP(NETIF_MSG_LINK,
1215 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1216 return bnx2x_status;
1217 }
1218
1219
1220 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1221 cos_sp_bitmap,
1222 cos_bw_bitmap);
1223
1224 if (bnx2x_status) {
1225 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1226 return bnx2x_status;
1227 }
1228 return 0;
1229 }
1230 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1231 {
1232
1233 struct bnx2x *bp = params->bp;
1234 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1235
1236
1237
1238
1239 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1240
1241
1242
1243
1244
1245
1246 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1247
1248 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1249 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1250 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1251 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1252
1253
1254 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1255
1256
1257 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1258
1259
1260
1261
1262
1263
1264
1265 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1266
1267
1268 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1269 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1270 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1271 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1272 }
1273
1274 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1275 const u32 cos1_bw)
1276 {
1277
1278 struct bnx2x *bp = params->bp;
1279 const u32 total_bw = cos0_bw + cos1_bw;
1280 u32 cos0_credit_weight = 0;
1281 u32 cos1_credit_weight = 0;
1282
1283 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1284
1285 if ((!total_bw) ||
1286 (!cos0_bw) ||
1287 (!cos1_bw)) {
1288 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1289 return;
1290 }
1291
1292 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1293 total_bw;
1294 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1295 total_bw;
1296
1297 bnx2x_ets_bw_limit_common(params);
1298
1299 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1300 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1301
1302 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1303 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1304 }
1305
1306 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1307 {
1308
1309 struct bnx2x *bp = params->bp;
1310 u32 val = 0;
1311
1312 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1313
1314
1315
1316
1317
1318
1319
1320 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1321
1322
1323
1324 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1325
1326 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1327
1328 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1329
1330
1331 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1332
1333
1334
1335
1336
1337
1338
1339
1340 val = (!strict_cos) ? 0x2318 : 0x22E0;
1341 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1342
1343 return 0;
1344 }
1345
1346
1347
1348
1349 static void bnx2x_update_pfc_xmac(struct link_params *params,
1350 struct link_vars *vars,
1351 u8 is_lb)
1352 {
1353 struct bnx2x *bp = params->bp;
1354 u32 xmac_base;
1355 u32 pause_val, pfc0_val, pfc1_val;
1356
1357
1358 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1359
1360
1361 pause_val = 0x18000;
1362 pfc0_val = 0xFFFF8000;
1363 pfc1_val = 0x2;
1364
1365
1366 if (!(params->feature_config_flags &
1367 FEATURE_CONFIG_PFC_ENABLED)) {
1368
1369
1370
1371 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1372 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1373
1374
1375 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1376 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1377 } else {
1378 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1379 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1380 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1381 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1382 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1383
1384 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1385 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1386 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1387 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1388
1389 }
1390
1391
1392 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1393 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1394 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1395
1396
1397
1398 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1399 ((params->mac_addr[2] << 24) |
1400 (params->mac_addr[3] << 16) |
1401 (params->mac_addr[4] << 8) |
1402 (params->mac_addr[5])));
1403 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1404 ((params->mac_addr[0] << 8) |
1405 (params->mac_addr[1])));
1406
1407 udelay(30);
1408 }
1409
1410
1411
1412
1413 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1414 u32 emac_base)
1415 {
1416 u32 new_mode, cur_mode;
1417 u32 clc_cnt;
1418
1419
1420
1421 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1422
1423 if (USES_WARPCORE(bp))
1424 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1425 else
1426 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1427
1428 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1429 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1430 return;
1431
1432 new_mode = cur_mode &
1433 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1434 new_mode |= clc_cnt;
1435 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1436
1437 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1438 cur_mode, new_mode);
1439 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1440 udelay(40);
1441 }
1442
1443 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1444 struct link_params *params)
1445 {
1446 u8 phy_index;
1447
1448 for (phy_index = INT_PHY; phy_index < params->num_phys;
1449 phy_index++)
1450 bnx2x_set_mdio_clk(bp, params->chip_id,
1451 params->phy[phy_index].mdio_ctrl);
1452 }
1453
1454 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1455 {
1456 u32 port4mode_ovwr_val;
1457
1458 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1459 if (port4mode_ovwr_val & (1<<0)) {
1460
1461 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1462 }
1463
1464 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1465 }
1466
1467 static void bnx2x_emac_init(struct link_params *params,
1468 struct link_vars *vars)
1469 {
1470
1471 struct bnx2x *bp = params->bp;
1472 u8 port = params->port;
1473 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1474 u32 val;
1475 u16 timeout;
1476
1477 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1478 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1479 udelay(5);
1480 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1481 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1482
1483
1484
1485 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1486 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1487
1488 timeout = 200;
1489 do {
1490 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1491 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1492 if (!timeout) {
1493 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1494 return;
1495 }
1496 timeout--;
1497 } while (val & EMAC_MODE_RESET);
1498
1499 bnx2x_set_mdio_emac_per_phy(bp, params);
1500
1501 val = ((params->mac_addr[0] << 8) |
1502 params->mac_addr[1]);
1503 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1504
1505 val = ((params->mac_addr[2] << 24) |
1506 (params->mac_addr[3] << 16) |
1507 (params->mac_addr[4] << 8) |
1508 params->mac_addr[5]);
1509 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1510 }
1511
1512 static void bnx2x_set_xumac_nig(struct link_params *params,
1513 u16 tx_pause_en,
1514 u8 enable)
1515 {
1516 struct bnx2x *bp = params->bp;
1517
1518 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1519 enable);
1520 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1521 enable);
1522 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1523 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1524 }
1525
1526 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1527 {
1528 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1529 u32 val;
1530 struct bnx2x *bp = params->bp;
1531 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1532 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1533 return;
1534 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1535 if (en)
1536 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1537 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1538 else
1539 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1540 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1541
1542 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1543 }
1544
1545 static void bnx2x_umac_enable(struct link_params *params,
1546 struct link_vars *vars, u8 lb)
1547 {
1548 u32 val;
1549 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1550 struct bnx2x *bp = params->bp;
1551
1552 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1553 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1554 usleep_range(1000, 2000);
1555
1556 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1557 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1558
1559 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1560
1561
1562 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1563
1564 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1565 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1566 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1567 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1568 switch (vars->line_speed) {
1569 case SPEED_10:
1570 val |= (0<<2);
1571 break;
1572 case SPEED_100:
1573 val |= (1<<2);
1574 break;
1575 case SPEED_1000:
1576 val |= (2<<2);
1577 break;
1578 case SPEED_2500:
1579 val |= (3<<2);
1580 break;
1581 default:
1582 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1583 vars->line_speed);
1584 break;
1585 }
1586 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1587 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1588
1589 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1590 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1591
1592 if (vars->duplex == DUPLEX_HALF)
1593 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1594
1595 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1596 udelay(50);
1597
1598
1599 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1600 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1601 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1602 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1603 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1604 } else {
1605 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1606 }
1607
1608
1609 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1610 ((params->mac_addr[2] << 24) |
1611 (params->mac_addr[3] << 16) |
1612 (params->mac_addr[4] << 8) |
1613 (params->mac_addr[5])));
1614 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1615 ((params->mac_addr[0] << 8) |
1616 (params->mac_addr[1])));
1617
1618
1619 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1620 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1621 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1622 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1623 udelay(50);
1624
1625
1626 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1627
1628
1629 if (lb)
1630 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1631 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1632
1633
1634
1635
1636 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1637 bnx2x_set_xumac_nig(params,
1638 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1639 vars->mac_type = MAC_TYPE_UMAC;
1640
1641 }
1642
1643
1644 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1645 {
1646 struct bnx2x *bp = params->bp;
1647 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1648
1649
1650
1651
1652
1653
1654
1655 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1656 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1657 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1658 is_port4mode &&
1659 (REG_RD(bp, MISC_REG_RESET_REG_2) &
1660 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1661 DP(NETIF_MSG_LINK,
1662 "XMAC already out of reset in 4-port mode\n");
1663 return;
1664 }
1665
1666
1667 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1668 MISC_REGISTERS_RESET_REG_2_XMAC);
1669 usleep_range(1000, 2000);
1670
1671 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1672 MISC_REGISTERS_RESET_REG_2_XMAC);
1673 if (is_port4mode) {
1674 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1675
1676
1677 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1678
1679
1680 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1681 } else {
1682
1683 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1684 if (max_speed == SPEED_10000) {
1685 DP(NETIF_MSG_LINK,
1686 "Init XMAC to 10G x 1 port per path\n");
1687
1688 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1689 } else {
1690 DP(NETIF_MSG_LINK,
1691 "Init XMAC to 20G x 2 ports per path\n");
1692
1693 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1694 }
1695 }
1696
1697 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1698 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1699 usleep_range(1000, 2000);
1700
1701 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1702 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1703
1704 }
1705
1706 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1707 {
1708 u8 port = params->port;
1709 struct bnx2x *bp = params->bp;
1710 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1711 u32 val;
1712
1713 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1714 MISC_REGISTERS_RESET_REG_2_XMAC) {
1715
1716
1717
1718
1719 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1720 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1721 (pfc_ctrl & ~(1<<1)));
1722 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1723 (pfc_ctrl | (1<<1)));
1724 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1725 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1726 if (en)
1727 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1728 else
1729 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1730 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1731 }
1732 }
1733
1734 static int bnx2x_xmac_enable(struct link_params *params,
1735 struct link_vars *vars, u8 lb)
1736 {
1737 u32 val, xmac_base;
1738 struct bnx2x *bp = params->bp;
1739 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1740
1741 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1742
1743 bnx2x_xmac_init(params, vars->line_speed);
1744
1745
1746
1747
1748
1749
1750
1751
1752 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1753
1754
1755
1756
1757 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1758 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1759 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1760 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1761 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1762 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1763 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1764 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1765 }
1766
1767 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1768
1769
1770 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1771
1772
1773 bnx2x_update_pfc_xmac(params, vars, 0);
1774
1775 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1776 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1777 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1778 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1779 } else {
1780 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1781 }
1782
1783
1784 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1785
1786
1787 if ((vars->line_speed == SPEED_20000) &&
1788 (params->phy[INT_PHY].supported &
1789 SUPPORTED_20000baseKR2_Full))
1790 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1791
1792
1793 if (lb)
1794 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1795 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1796 bnx2x_set_xumac_nig(params,
1797 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1798
1799 vars->mac_type = MAC_TYPE_XMAC;
1800
1801 return 0;
1802 }
1803
1804 static int bnx2x_emac_enable(struct link_params *params,
1805 struct link_vars *vars, u8 lb)
1806 {
1807 struct bnx2x *bp = params->bp;
1808 u8 port = params->port;
1809 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1810 u32 val;
1811
1812 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1813
1814
1815 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1816 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1817
1818
1819 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1820
1821
1822 if (vars->phy_flags & PHY_XGXS_FLAG) {
1823 u32 ser_lane = ((params->lane_config &
1824 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1825 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1826
1827 DP(NETIF_MSG_LINK, "XGXS\n");
1828
1829 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1830
1831 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1832
1833 } else {
1834 DP(NETIF_MSG_LINK, "SerDes\n");
1835
1836 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1837 }
1838
1839 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1840 EMAC_RX_MODE_RESET);
1841 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1842 EMAC_TX_MODE_RESET);
1843
1844
1845 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1846 EMAC_RX_MODE_FLOW_EN);
1847
1848 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1849 (EMAC_TX_MODE_EXT_PAUSE_EN |
1850 EMAC_TX_MODE_FLOW_EN));
1851 if (!(params->feature_config_flags &
1852 FEATURE_CONFIG_PFC_ENABLED)) {
1853 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1854 bnx2x_bits_en(bp, emac_base +
1855 EMAC_REG_EMAC_RX_MODE,
1856 EMAC_RX_MODE_FLOW_EN);
1857
1858 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1859 bnx2x_bits_en(bp, emac_base +
1860 EMAC_REG_EMAC_TX_MODE,
1861 (EMAC_TX_MODE_EXT_PAUSE_EN |
1862 EMAC_TX_MODE_FLOW_EN));
1863 } else
1864 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1865 EMAC_TX_MODE_FLOW_EN);
1866
1867
1868 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1869 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1870
1871
1872
1873
1874
1875
1876
1877
1878 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1879 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1880 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1881
1882 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1883 EMAC_REG_RX_PFC_MODE_RX_EN |
1884 EMAC_REG_RX_PFC_MODE_TX_EN |
1885 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1886
1887 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1888 ((0x0101 <<
1889 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1890 (0x00ff <<
1891 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1892 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1893 }
1894 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1895
1896
1897 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1898 if (lb)
1899 val |= 0x810;
1900 else
1901 val &= ~0x810;
1902 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1903
1904
1905 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1906
1907
1908 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1909 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1910 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD)));
1911
1912
1913 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1914
1915
1916 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1917 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1918 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1919
1920
1921 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1922 val = 0;
1923 if ((params->feature_config_flags &
1924 FEATURE_CONFIG_PFC_ENABLED) ||
1925 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1926 val = 1;
1927
1928 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1929 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1930
1931 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1932
1933 vars->mac_type = MAC_TYPE_EMAC;
1934 return 0;
1935 }
1936
1937 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1938 struct link_vars *vars)
1939 {
1940 u32 wb_data[2];
1941 struct bnx2x *bp = params->bp;
1942 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1943 NIG_REG_INGRESS_BMAC0_MEM;
1944
1945 u32 val = 0x14;
1946 if ((!(params->feature_config_flags &
1947 FEATURE_CONFIG_PFC_ENABLED)) &&
1948 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1949
1950 val |= (1<<5);
1951 wb_data[0] = val;
1952 wb_data[1] = 0;
1953 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1954
1955
1956 val = 0xc0;
1957 if (!(params->feature_config_flags &
1958 FEATURE_CONFIG_PFC_ENABLED) &&
1959 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1960 val |= 0x800000;
1961 wb_data[0] = val;
1962 wb_data[1] = 0;
1963 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1964 }
1965
1966 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1967 struct link_vars *vars,
1968 u8 is_lb)
1969 {
1970
1971
1972
1973 u32 wb_data[2];
1974 struct bnx2x *bp = params->bp;
1975 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1976 NIG_REG_INGRESS_BMAC0_MEM;
1977 u32 val = 0x14;
1978
1979 if ((!(params->feature_config_flags &
1980 FEATURE_CONFIG_PFC_ENABLED)) &&
1981 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1982
1983 val |= (1<<5);
1984 wb_data[0] = val;
1985 wb_data[1] = 0;
1986 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1987 udelay(30);
1988
1989
1990 val = 0xc0;
1991 if (!(params->feature_config_flags &
1992 FEATURE_CONFIG_PFC_ENABLED) &&
1993 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1994 val |= 0x800000;
1995 wb_data[0] = val;
1996 wb_data[1] = 0;
1997 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1998
1999 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2000 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2001
2002 wb_data[0] = 0x0;
2003 wb_data[0] |= (1<<0);
2004 wb_data[0] |= (1<<1);
2005 wb_data[0] |= (1<<2);
2006 wb_data[0] |= (1<<3);
2007 wb_data[0] |= (1<<5);
2008 wb_data[1] = 0;
2009 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2010 wb_data, 2);
2011
2012 wb_data[0] &= ~(1<<2);
2013 } else {
2014 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2015
2016 wb_data[0] = 0x8;
2017 wb_data[1] = 0;
2018 }
2019
2020 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2021
2022
2023
2024
2025
2026
2027 val = 0x8000;
2028 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2029 val |= (1<<16);
2030
2031 wb_data[0] = val;
2032 wb_data[1] = 0;
2033 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2034 wb_data, 2);
2035
2036
2037 val = 0x3;
2038 if (is_lb) {
2039 val |= 0x4;
2040 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2041 }
2042
2043 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2044 val |= ((1<<6)|(1<<5));
2045
2046 wb_data[0] = val;
2047 wb_data[1] = 0;
2048 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2049 }
2050
2051
2052
2053
2054
2055
2056 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2057 u8 cos_entry,
2058 u32 priority_mask, u8 port)
2059 {
2060 u32 nig_reg_rx_priority_mask_add = 0;
2061
2062 switch (cos_entry) {
2063 case 0:
2064 nig_reg_rx_priority_mask_add = (port) ?
2065 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2066 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2067 break;
2068 case 1:
2069 nig_reg_rx_priority_mask_add = (port) ?
2070 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2071 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2072 break;
2073 case 2:
2074 nig_reg_rx_priority_mask_add = (port) ?
2075 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2076 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2077 break;
2078 case 3:
2079 if (port)
2080 return -EINVAL;
2081 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2082 break;
2083 case 4:
2084 if (port)
2085 return -EINVAL;
2086 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2087 break;
2088 case 5:
2089 if (port)
2090 return -EINVAL;
2091 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2092 break;
2093 }
2094
2095 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2096
2097 return 0;
2098 }
2099 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2100 {
2101 struct bnx2x *bp = params->bp;
2102
2103 REG_WR(bp, params->shmem_base +
2104 offsetof(struct shmem_region,
2105 port_mb[params->port].link_status), link_status);
2106 }
2107
2108 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2109 {
2110 struct bnx2x *bp = params->bp;
2111
2112 if (SHMEM2_HAS(bp, link_attr_sync))
2113 REG_WR(bp, params->shmem2_base +
2114 offsetof(struct shmem2_region,
2115 link_attr_sync[params->port]), link_attr);
2116 }
2117
2118 static void bnx2x_update_pfc_nig(struct link_params *params,
2119 struct link_vars *vars,
2120 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2121 {
2122 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2123 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2124 u32 pkt_priority_to_cos = 0;
2125 struct bnx2x *bp = params->bp;
2126 u8 port = params->port;
2127
2128 int set_pfc = params->feature_config_flags &
2129 FEATURE_CONFIG_PFC_ENABLED;
2130 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2131
2132
2133
2134
2135
2136 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2137 NIG_REG_LLH0_XCM_MASK);
2138
2139
2140
2141 if (set_pfc) {
2142 pause_enable = 0;
2143 llfc_out_en = 0;
2144 llfc_enable = 0;
2145 if (CHIP_IS_E3(bp))
2146 ppp_enable = 0;
2147 else
2148 ppp_enable = 1;
2149 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2150 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2151 xcm_out_en = 0;
2152 hwpfc_enable = 1;
2153 } else {
2154 if (nig_params) {
2155 llfc_out_en = nig_params->llfc_out_en;
2156 llfc_enable = nig_params->llfc_enable;
2157 pause_enable = nig_params->pause_enable;
2158 } else
2159 pause_enable = 1;
2160
2161 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2162 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2163 xcm_out_en = 1;
2164 }
2165
2166 if (CHIP_IS_E3(bp))
2167 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2168 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2169 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2170 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2171 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2172 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2173 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2174 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2175
2176 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2177 NIG_REG_PPP_ENABLE_0, ppp_enable);
2178
2179 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2180 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2181
2182 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2183 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2184
2185
2186 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2187 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2188
2189
2190 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2191 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2192
2193 if (nig_params) {
2194 u8 i = 0;
2195 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2196
2197 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2198 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2199 nig_params->rx_cos_priority_mask[i], port);
2200
2201 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2202 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2203 nig_params->llfc_high_priority_classes);
2204
2205 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2206 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2207 nig_params->llfc_low_priority_classes);
2208 }
2209 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2210 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2211 pkt_priority_to_cos);
2212 }
2213
2214 int bnx2x_update_pfc(struct link_params *params,
2215 struct link_vars *vars,
2216 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2217 {
2218
2219
2220
2221
2222 u32 val;
2223 struct bnx2x *bp = params->bp;
2224 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2225
2226 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2227 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2228 else
2229 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2230
2231 bnx2x_update_mng(params, vars->link_status);
2232
2233
2234 bnx2x_update_pfc_nig(params, vars, pfc_params);
2235
2236 if (!vars->link_up)
2237 return 0;
2238
2239 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2240
2241 if (CHIP_IS_E3(bp)) {
2242 if (vars->mac_type == MAC_TYPE_XMAC)
2243 bnx2x_update_pfc_xmac(params, vars, 0);
2244 } else {
2245 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2246 if ((val &
2247 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2248 == 0) {
2249 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2250 bnx2x_emac_enable(params, vars, 0);
2251 return 0;
2252 }
2253 if (CHIP_IS_E2(bp))
2254 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2255 else
2256 bnx2x_update_pfc_bmac1(params, vars);
2257
2258 val = 0;
2259 if ((params->feature_config_flags &
2260 FEATURE_CONFIG_PFC_ENABLED) ||
2261 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2262 val = 1;
2263 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2264 }
2265 return 0;
2266 }
2267
2268 static int bnx2x_bmac1_enable(struct link_params *params,
2269 struct link_vars *vars,
2270 u8 is_lb)
2271 {
2272 struct bnx2x *bp = params->bp;
2273 u8 port = params->port;
2274 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2275 NIG_REG_INGRESS_BMAC0_MEM;
2276 u32 wb_data[2];
2277 u32 val;
2278
2279 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2280
2281
2282 wb_data[0] = 0x3c;
2283 wb_data[1] = 0;
2284 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2285 wb_data, 2);
2286
2287
2288 wb_data[0] = ((params->mac_addr[2] << 24) |
2289 (params->mac_addr[3] << 16) |
2290 (params->mac_addr[4] << 8) |
2291 params->mac_addr[5]);
2292 wb_data[1] = ((params->mac_addr[0] << 8) |
2293 params->mac_addr[1]);
2294 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2295
2296
2297 val = 0x3;
2298 if (is_lb) {
2299 val |= 0x4;
2300 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2301 }
2302 wb_data[0] = val;
2303 wb_data[1] = 0;
2304 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2305
2306
2307 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2308 wb_data[1] = 0;
2309 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2310
2311 bnx2x_update_pfc_bmac1(params, vars);
2312
2313
2314 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2315 wb_data[1] = 0;
2316 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2317
2318
2319 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2320 wb_data[1] = 0;
2321 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2322
2323
2324 wb_data[0] = 0x1000200;
2325 wb_data[1] = 0;
2326 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2327 wb_data, 2);
2328
2329 return 0;
2330 }
2331
2332 static int bnx2x_bmac2_enable(struct link_params *params,
2333 struct link_vars *vars,
2334 u8 is_lb)
2335 {
2336 struct bnx2x *bp = params->bp;
2337 u8 port = params->port;
2338 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2339 NIG_REG_INGRESS_BMAC0_MEM;
2340 u32 wb_data[2];
2341
2342 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2343
2344 wb_data[0] = 0;
2345 wb_data[1] = 0;
2346 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2347 udelay(30);
2348
2349
2350 wb_data[0] = 0x3c;
2351 wb_data[1] = 0;
2352 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2353 wb_data, 2);
2354
2355 udelay(30);
2356
2357
2358 wb_data[0] = ((params->mac_addr[2] << 24) |
2359 (params->mac_addr[3] << 16) |
2360 (params->mac_addr[4] << 8) |
2361 params->mac_addr[5]);
2362 wb_data[1] = ((params->mac_addr[0] << 8) |
2363 params->mac_addr[1]);
2364 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2365 wb_data, 2);
2366
2367 udelay(30);
2368
2369
2370 wb_data[0] = 0x1000200;
2371 wb_data[1] = 0;
2372 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2373 wb_data, 2);
2374 udelay(30);
2375
2376
2377 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2378 wb_data[1] = 0;
2379 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2380 udelay(30);
2381
2382
2383 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;
2384 wb_data[1] = 0;
2385 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2386 udelay(30);
2387
2388 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD - 2;
2389 wb_data[1] = 0;
2390 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2391 udelay(30);
2392 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2393
2394 return 0;
2395 }
2396
2397 static int bnx2x_bmac_enable(struct link_params *params,
2398 struct link_vars *vars,
2399 u8 is_lb, u8 reset_bmac)
2400 {
2401 int rc = 0;
2402 u8 port = params->port;
2403 struct bnx2x *bp = params->bp;
2404 u32 val;
2405
2406 if (reset_bmac) {
2407 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2408 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2409 usleep_range(1000, 2000);
2410 }
2411
2412 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2413 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2414
2415
2416 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2417
2418
2419 if (CHIP_IS_E2(bp))
2420 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2421 else
2422 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2423 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2424 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2425 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2426 val = 0;
2427 if ((params->feature_config_flags &
2428 FEATURE_CONFIG_PFC_ENABLED) ||
2429 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2430 val = 1;
2431 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2432 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2433 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2434 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2435 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2436 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2437
2438 vars->mac_type = MAC_TYPE_BMAC;
2439 return rc;
2440 }
2441
2442 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2443 {
2444 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2445 NIG_REG_INGRESS_BMAC0_MEM;
2446 u32 wb_data[2];
2447 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2448
2449 if (CHIP_IS_E2(bp))
2450 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2451 else
2452 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2453
2454 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2455 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2456 nig_bmac_enable) {
2457
2458 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2459 if (en)
2460 wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2461 else
2462 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2463 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2464 usleep_range(1000, 2000);
2465 }
2466 }
2467
2468 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2469 u32 line_speed)
2470 {
2471 struct bnx2x *bp = params->bp;
2472 u8 port = params->port;
2473 u32 init_crd, crd;
2474 u32 count = 1000;
2475
2476
2477 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2478
2479
2480 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2481 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2482 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2483
2484 while ((init_crd != crd) && count) {
2485 usleep_range(5000, 10000);
2486 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2487 count--;
2488 }
2489 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2490 if (init_crd != crd) {
2491 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2492 init_crd, crd);
2493 return -EINVAL;
2494 }
2495
2496 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2497 line_speed == SPEED_10 ||
2498 line_speed == SPEED_100 ||
2499 line_speed == SPEED_1000 ||
2500 line_speed == SPEED_2500) {
2501 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2502
2503 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2504
2505 init_crd = 778;
2506
2507 } else {
2508 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2509 ETH_OVERHEAD)/16;
2510 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2511
2512 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2513
2514 switch (line_speed) {
2515 case SPEED_10000:
2516 init_crd = thresh + 553 - 22;
2517 break;
2518 default:
2519 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2520 line_speed);
2521 return -EINVAL;
2522 }
2523 }
2524 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2525 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2526 line_speed, init_crd);
2527
2528
2529 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2530 usleep_range(5000, 10000);
2531 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2532
2533
2534 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2535 return 0;
2536 }
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2554 u32 mdc_mdio_access, u8 port)
2555 {
2556 u32 emac_base = 0;
2557 switch (mdc_mdio_access) {
2558 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2559 break;
2560 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2561 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2562 emac_base = GRCBASE_EMAC1;
2563 else
2564 emac_base = GRCBASE_EMAC0;
2565 break;
2566 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2567 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2568 emac_base = GRCBASE_EMAC0;
2569 else
2570 emac_base = GRCBASE_EMAC1;
2571 break;
2572 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2573 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2574 break;
2575 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2576 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2577 break;
2578 default:
2579 break;
2580 }
2581 return emac_base;
2582
2583 }
2584
2585
2586
2587
2588 static int bnx2x_cl22_write(struct bnx2x *bp,
2589 struct bnx2x_phy *phy,
2590 u16 reg, u16 val)
2591 {
2592 u32 tmp, mode;
2593 u8 i;
2594 int rc = 0;
2595
2596 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2597 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2598 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2599
2600
2601 tmp = ((phy->addr << 21) | (reg << 16) | val |
2602 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2603 EMAC_MDIO_COMM_START_BUSY);
2604 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2605
2606 for (i = 0; i < 50; i++) {
2607 udelay(10);
2608
2609 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2610 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2611 udelay(5);
2612 break;
2613 }
2614 }
2615 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2616 DP(NETIF_MSG_LINK, "write phy register failed\n");
2617 rc = -EFAULT;
2618 }
2619 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2620 return rc;
2621 }
2622
2623 static int bnx2x_cl22_read(struct bnx2x *bp,
2624 struct bnx2x_phy *phy,
2625 u16 reg, u16 *ret_val)
2626 {
2627 u32 val, mode;
2628 u16 i;
2629 int rc = 0;
2630
2631
2632 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2633 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2634 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2635
2636
2637 val = ((phy->addr << 21) | (reg << 16) |
2638 EMAC_MDIO_COMM_COMMAND_READ_22 |
2639 EMAC_MDIO_COMM_START_BUSY);
2640 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2641
2642 for (i = 0; i < 50; i++) {
2643 udelay(10);
2644
2645 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2646 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2647 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2648 udelay(5);
2649 break;
2650 }
2651 }
2652 if (val & EMAC_MDIO_COMM_START_BUSY) {
2653 DP(NETIF_MSG_LINK, "read phy register failed\n");
2654
2655 *ret_val = 0;
2656 rc = -EFAULT;
2657 }
2658 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2659 return rc;
2660 }
2661
2662
2663
2664
2665 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2666 u8 devad, u16 reg, u16 *ret_val)
2667 {
2668 u32 val;
2669 u16 i;
2670 int rc = 0;
2671 u32 chip_id;
2672 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2673 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2674 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2675 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2676 }
2677
2678 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2679 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2680 EMAC_MDIO_STATUS_10MB);
2681
2682 val = ((phy->addr << 21) | (devad << 16) | reg |
2683 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2684 EMAC_MDIO_COMM_START_BUSY);
2685 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2686
2687 for (i = 0; i < 50; i++) {
2688 udelay(10);
2689
2690 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2691 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2692 udelay(5);
2693 break;
2694 }
2695 }
2696 if (val & EMAC_MDIO_COMM_START_BUSY) {
2697 DP(NETIF_MSG_LINK, "read phy register failed\n");
2698 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2699 *ret_val = 0;
2700 rc = -EFAULT;
2701 } else {
2702
2703 val = ((phy->addr << 21) | (devad << 16) |
2704 EMAC_MDIO_COMM_COMMAND_READ_45 |
2705 EMAC_MDIO_COMM_START_BUSY);
2706 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2707
2708 for (i = 0; i < 50; i++) {
2709 udelay(10);
2710
2711 val = REG_RD(bp, phy->mdio_ctrl +
2712 EMAC_REG_EMAC_MDIO_COMM);
2713 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2714 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2715 break;
2716 }
2717 }
2718 if (val & EMAC_MDIO_COMM_START_BUSY) {
2719 DP(NETIF_MSG_LINK, "read phy register failed\n");
2720 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2721 *ret_val = 0;
2722 rc = -EFAULT;
2723 }
2724 }
2725
2726 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2727 phy->flags ^= FLAGS_DUMMY_READ;
2728 if (phy->flags & FLAGS_DUMMY_READ) {
2729 u16 temp_val;
2730 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2731 }
2732 }
2733
2734 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2735 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2736 EMAC_MDIO_STATUS_10MB);
2737 return rc;
2738 }
2739
2740 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2741 u8 devad, u16 reg, u16 val)
2742 {
2743 u32 tmp;
2744 u8 i;
2745 int rc = 0;
2746 u32 chip_id;
2747 if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2748 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2749 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2750 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2751 }
2752
2753 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2754 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2755 EMAC_MDIO_STATUS_10MB);
2756
2757
2758 tmp = ((phy->addr << 21) | (devad << 16) | reg |
2759 EMAC_MDIO_COMM_COMMAND_ADDRESS |
2760 EMAC_MDIO_COMM_START_BUSY);
2761 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2762
2763 for (i = 0; i < 50; i++) {
2764 udelay(10);
2765
2766 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2767 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2768 udelay(5);
2769 break;
2770 }
2771 }
2772 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2773 DP(NETIF_MSG_LINK, "write phy register failed\n");
2774 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2775 rc = -EFAULT;
2776 } else {
2777
2778 tmp = ((phy->addr << 21) | (devad << 16) | val |
2779 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2780 EMAC_MDIO_COMM_START_BUSY);
2781 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2782
2783 for (i = 0; i < 50; i++) {
2784 udelay(10);
2785
2786 tmp = REG_RD(bp, phy->mdio_ctrl +
2787 EMAC_REG_EMAC_MDIO_COMM);
2788 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2789 udelay(5);
2790 break;
2791 }
2792 }
2793 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2794 DP(NETIF_MSG_LINK, "write phy register failed\n");
2795 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
2796 rc = -EFAULT;
2797 }
2798 }
2799
2800 if (phy->flags & FLAGS_MDC_MDIO_WA) {
2801 phy->flags ^= FLAGS_DUMMY_READ;
2802 if (phy->flags & FLAGS_DUMMY_READ) {
2803 u16 temp_val;
2804 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2805 }
2806 }
2807 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2808 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2809 EMAC_MDIO_STATUS_10MB);
2810 return rc;
2811 }
2812
2813
2814
2815
2816 static u8 bnx2x_eee_has_cap(struct link_params *params)
2817 {
2818 struct bnx2x *bp = params->bp;
2819
2820 if (REG_RD(bp, params->shmem2_base) <=
2821 offsetof(struct shmem2_region, eee_status[params->port]))
2822 return 0;
2823
2824 return 1;
2825 }
2826
2827 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2828 {
2829 switch (nvram_mode) {
2830 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2831 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2832 break;
2833 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2834 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2835 break;
2836 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2837 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2838 break;
2839 default:
2840 *idle_timer = 0;
2841 break;
2842 }
2843
2844 return 0;
2845 }
2846
2847 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2848 {
2849 switch (idle_timer) {
2850 case EEE_MODE_NVRAM_BALANCED_TIME:
2851 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2852 break;
2853 case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2854 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2855 break;
2856 case EEE_MODE_NVRAM_LATENCY_TIME:
2857 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2858 break;
2859 default:
2860 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2861 break;
2862 }
2863
2864 return 0;
2865 }
2866
2867 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2868 {
2869 u32 eee_mode, eee_idle;
2870 struct bnx2x *bp = params->bp;
2871
2872 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2873 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2874
2875 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2876 } else {
2877
2878 if (bnx2x_eee_nvram_to_time(params->eee_mode &
2879 EEE_MODE_NVRAM_MASK,
2880 &eee_idle))
2881 return 0;
2882 }
2883 } else {
2884
2885 eee_mode = ((REG_RD(bp, params->shmem_base +
2886 offsetof(struct shmem_region, dev_info.
2887 port_feature_config[params->port].
2888 eee_power_mode)) &
2889 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2890 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2891
2892 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2893 return 0;
2894 }
2895
2896 return eee_idle;
2897 }
2898
2899 static int bnx2x_eee_set_timers(struct link_params *params,
2900 struct link_vars *vars)
2901 {
2902 u32 eee_idle = 0, eee_mode;
2903 struct bnx2x *bp = params->bp;
2904
2905 eee_idle = bnx2x_eee_calc_timer(params);
2906
2907 if (eee_idle) {
2908 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2909 eee_idle);
2910 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2911 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2912 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2913 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2914 return -EINVAL;
2915 }
2916
2917 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2918 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2919
2920 eee_idle >>= 4;
2921 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2922 SHMEM_EEE_TIME_OUTPUT_BIT;
2923 } else {
2924 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2925 return -EINVAL;
2926 vars->eee_status |= eee_mode;
2927 }
2928
2929 return 0;
2930 }
2931
2932 static int bnx2x_eee_initial_config(struct link_params *params,
2933 struct link_vars *vars, u8 mode)
2934 {
2935 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2936
2937
2938 if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2939 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2940 else
2941 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2942
2943 if (params->eee_mode & EEE_MODE_ADV_LPI)
2944 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2945 else
2946 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2947
2948 return bnx2x_eee_set_timers(params, vars);
2949 }
2950
2951 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2952 struct link_params *params,
2953 struct link_vars *vars)
2954 {
2955 struct bnx2x *bp = params->bp;
2956
2957
2958 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2959
2960 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2961
2962 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2963
2964 return 0;
2965 }
2966
2967 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
2968 struct link_params *params,
2969 struct link_vars *vars, u8 modes)
2970 {
2971 struct bnx2x *bp = params->bp;
2972 u16 val = 0;
2973
2974
2975 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2976
2977 if (modes & SHMEM_EEE_10G_ADV) {
2978 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
2979 val |= 0x8;
2980 }
2981 if (modes & SHMEM_EEE_1G_ADV) {
2982 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
2983 val |= 0x4;
2984 }
2985
2986 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2987
2988 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2989 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
2990
2991 return 0;
2992 }
2993
2994 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
2995 {
2996 struct bnx2x *bp = params->bp;
2997
2998 if (bnx2x_eee_has_cap(params))
2999 REG_WR(bp, params->shmem2_base +
3000 offsetof(struct shmem2_region,
3001 eee_status[params->port]), eee_status);
3002 }
3003
3004 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3005 struct link_params *params,
3006 struct link_vars *vars)
3007 {
3008 struct bnx2x *bp = params->bp;
3009 u16 adv = 0, lp = 0;
3010 u32 lp_adv = 0;
3011 u8 neg = 0;
3012
3013 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3014 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3015
3016 if (lp & 0x2) {
3017 lp_adv |= SHMEM_EEE_100M_ADV;
3018 if (adv & 0x2) {
3019 if (vars->line_speed == SPEED_100)
3020 neg = 1;
3021 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3022 }
3023 }
3024 if (lp & 0x14) {
3025 lp_adv |= SHMEM_EEE_1G_ADV;
3026 if (adv & 0x14) {
3027 if (vars->line_speed == SPEED_1000)
3028 neg = 1;
3029 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3030 }
3031 }
3032 if (lp & 0x68) {
3033 lp_adv |= SHMEM_EEE_10G_ADV;
3034 if (adv & 0x68) {
3035 if (vars->line_speed == SPEED_10000)
3036 neg = 1;
3037 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3038 }
3039 }
3040
3041 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3042 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3043
3044 if (neg) {
3045 DP(NETIF_MSG_LINK, "EEE is active\n");
3046 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3047 }
3048
3049 }
3050
3051
3052
3053
3054 static void bnx2x_bsc_module_sel(struct link_params *params)
3055 {
3056 int idx;
3057 u32 board_cfg, sfp_ctrl;
3058 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3059 struct bnx2x *bp = params->bp;
3060 u8 port = params->port;
3061
3062 board_cfg = REG_RD(bp, params->shmem_base +
3063 offsetof(struct shmem_region,
3064 dev_info.shared_hw_config.board));
3065 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3066 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3067 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3068
3069
3070 sfp_ctrl = REG_RD(bp, params->shmem_base +
3071 offsetof(struct shmem_region,
3072 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3073 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3074 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3075 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3076 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3077 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3078 }
3079
3080 static int bnx2x_bsc_read(struct link_params *params,
3081 struct bnx2x *bp,
3082 u8 sl_devid,
3083 u16 sl_addr,
3084 u8 lc_addr,
3085 u8 xfer_cnt,
3086 u32 *data_array)
3087 {
3088 u32 val, i;
3089 int rc = 0;
3090
3091 if (xfer_cnt > 16) {
3092 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3093 xfer_cnt);
3094 return -EINVAL;
3095 }
3096 bnx2x_bsc_module_sel(params);
3097
3098 xfer_cnt = 16 - lc_addr;
3099
3100
3101 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3102 val |= MCPR_IMC_COMMAND_ENABLE;
3103 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3104
3105
3106 val = (sl_devid << 16) | sl_addr;
3107 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3108
3109
3110 val = (MCPR_IMC_COMMAND_ENABLE) |
3111 (MCPR_IMC_COMMAND_WRITE_OP <<
3112 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3113 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3114 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3115
3116
3117 i = 0;
3118 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3119 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3120 udelay(10);
3121 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3122 if (i++ > 1000) {
3123 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3124 i);
3125 rc = -EFAULT;
3126 break;
3127 }
3128 }
3129 if (rc == -EFAULT)
3130 return rc;
3131
3132
3133 val = (MCPR_IMC_COMMAND_ENABLE) |
3134 (MCPR_IMC_COMMAND_READ_OP <<
3135 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3136 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3137 (xfer_cnt);
3138 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3139
3140
3141 i = 0;
3142 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3143 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3144 udelay(10);
3145 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3146 if (i++ > 1000) {
3147 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3148 rc = -EFAULT;
3149 break;
3150 }
3151 }
3152 if (rc == -EFAULT)
3153 return rc;
3154
3155 for (i = (lc_addr >> 2); i < 4; i++) {
3156 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3157 #ifdef __BIG_ENDIAN
3158 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3159 ((data_array[i] & 0x0000ff00) << 8) |
3160 ((data_array[i] & 0x00ff0000) >> 8) |
3161 ((data_array[i] & 0xff000000) >> 24);
3162 #endif
3163 }
3164 return rc;
3165 }
3166
3167 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3168 u8 devad, u16 reg, u16 or_val)
3169 {
3170 u16 val;
3171 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3172 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3173 }
3174
3175 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3176 struct bnx2x_phy *phy,
3177 u8 devad, u16 reg, u16 and_val)
3178 {
3179 u16 val;
3180 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3181 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3182 }
3183
3184 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3185 u8 devad, u16 reg, u16 *ret_val)
3186 {
3187 u8 phy_index;
3188
3189
3190
3191 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3192 if (params->phy[phy_index].addr == phy_addr) {
3193 return bnx2x_cl45_read(params->bp,
3194 ¶ms->phy[phy_index], devad,
3195 reg, ret_val);
3196 }
3197 }
3198 return -EINVAL;
3199 }
3200
3201 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3202 u8 devad, u16 reg, u16 val)
3203 {
3204 u8 phy_index;
3205
3206
3207
3208 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3209 if (params->phy[phy_index].addr == phy_addr) {
3210 return bnx2x_cl45_write(params->bp,
3211 ¶ms->phy[phy_index], devad,
3212 reg, val);
3213 }
3214 }
3215 return -EINVAL;
3216 }
3217 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3218 struct link_params *params)
3219 {
3220 u8 lane = 0;
3221 struct bnx2x *bp = params->bp;
3222 u32 path_swap, path_swap_ovr;
3223 u8 path, port;
3224
3225 path = BP_PATH(bp);
3226 port = params->port;
3227
3228 if (bnx2x_is_4_port_mode(bp)) {
3229 u32 port_swap, port_swap_ovr;
3230
3231
3232 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3233 if (path_swap_ovr & 0x1)
3234 path_swap = (path_swap_ovr & 0x2);
3235 else
3236 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3237
3238 if (path_swap)
3239 path = path ^ 1;
3240
3241
3242 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3243 if (port_swap_ovr & 0x1)
3244 port_swap = (port_swap_ovr & 0x2);
3245 else
3246 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3247
3248 if (port_swap)
3249 port = port ^ 1;
3250
3251 lane = (port<<1) + path;
3252 } else {
3253
3254
3255 path_swap_ovr =
3256 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3257 if (path_swap_ovr & 0x1) {
3258 path_swap = (path_swap_ovr & 0x2);
3259 } else {
3260 path_swap =
3261 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3262 }
3263 if (path_swap)
3264 path = path ^ 1;
3265
3266 lane = path << 1 ;
3267 }
3268 return lane;
3269 }
3270
3271 static void bnx2x_set_aer_mmd(struct link_params *params,
3272 struct bnx2x_phy *phy)
3273 {
3274 u32 ser_lane;
3275 u16 offset, aer_val;
3276 struct bnx2x *bp = params->bp;
3277 ser_lane = ((params->lane_config &
3278 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3279 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3280
3281 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3282 (phy->addr + ser_lane) : 0;
3283
3284 if (USES_WARPCORE(bp)) {
3285 aer_val = bnx2x_get_warpcore_lane(phy, params);
3286
3287
3288
3289
3290
3291
3292 if (phy->flags & FLAGS_WC_DUAL_MODE)
3293 aer_val = (aer_val >> 1) | 0x200;
3294 } else if (CHIP_IS_E2(bp))
3295 aer_val = 0x3800 + offset - 1;
3296 else
3297 aer_val = 0x3800 + offset;
3298
3299 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3300 MDIO_AER_BLOCK_AER_REG, aer_val);
3301
3302 }
3303
3304
3305
3306
3307
3308 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3309 {
3310 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3311
3312
3313 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3314 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3315 udelay(500);
3316 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3317 udelay(500);
3318
3319 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3320 }
3321
3322 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3323 {
3324 u32 val;
3325
3326 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3327
3328 val = SERDES_RESET_BITS << (port*16);
3329
3330
3331 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3332 udelay(500);
3333 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3334
3335 bnx2x_set_serdes_access(bp, port);
3336
3337 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3338 DEFAULT_PHY_DEV_ADDR);
3339 }
3340
3341 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3342 struct link_params *params,
3343 u32 action)
3344 {
3345 struct bnx2x *bp = params->bp;
3346 switch (action) {
3347 case PHY_INIT:
3348
3349 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3350 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3351 phy->def_md_devad);
3352 break;
3353 }
3354 }
3355
3356 static void bnx2x_xgxs_deassert(struct link_params *params)
3357 {
3358 struct bnx2x *bp = params->bp;
3359 u8 port;
3360 u32 val;
3361 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3362 port = params->port;
3363
3364 val = XGXS_RESET_BITS << (port*16);
3365
3366
3367 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3368 udelay(500);
3369 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3370 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params,
3371 PHY_INIT);
3372 }
3373
3374 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3375 struct link_params *params, u16 *ieee_fc)
3376 {
3377 struct bnx2x *bp = params->bp;
3378 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3379
3380
3381
3382
3383 switch (phy->req_flow_ctrl) {
3384 case BNX2X_FLOW_CTRL_AUTO:
3385 switch (params->req_fc_auto_adv) {
3386 case BNX2X_FLOW_CTRL_BOTH:
3387 case BNX2X_FLOW_CTRL_RX:
3388 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3389 break;
3390 case BNX2X_FLOW_CTRL_TX:
3391 *ieee_fc |=
3392 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3393 break;
3394 default:
3395 break;
3396 }
3397 break;
3398 case BNX2X_FLOW_CTRL_TX:
3399 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3400 break;
3401
3402 case BNX2X_FLOW_CTRL_RX:
3403 case BNX2X_FLOW_CTRL_BOTH:
3404 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3405 break;
3406
3407 case BNX2X_FLOW_CTRL_NONE:
3408 default:
3409 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3410 break;
3411 }
3412 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3413 }
3414
3415 static void set_phy_vars(struct link_params *params,
3416 struct link_vars *vars)
3417 {
3418 struct bnx2x *bp = params->bp;
3419 u8 actual_phy_idx, phy_index, link_cfg_idx;
3420 u8 phy_config_swapped = params->multi_phy_config &
3421 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3422 for (phy_index = INT_PHY; phy_index < params->num_phys;
3423 phy_index++) {
3424 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3425 actual_phy_idx = phy_index;
3426 if (phy_config_swapped) {
3427 if (phy_index == EXT_PHY1)
3428 actual_phy_idx = EXT_PHY2;
3429 else if (phy_index == EXT_PHY2)
3430 actual_phy_idx = EXT_PHY1;
3431 }
3432 params->phy[actual_phy_idx].req_flow_ctrl =
3433 params->req_flow_ctrl[link_cfg_idx];
3434
3435 params->phy[actual_phy_idx].req_line_speed =
3436 params->req_line_speed[link_cfg_idx];
3437
3438 params->phy[actual_phy_idx].speed_cap_mask =
3439 params->speed_cap_mask[link_cfg_idx];
3440
3441 params->phy[actual_phy_idx].req_duplex =
3442 params->req_duplex[link_cfg_idx];
3443
3444 if (params->req_line_speed[link_cfg_idx] ==
3445 SPEED_AUTO_NEG)
3446 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3447
3448 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3449 " speed_cap_mask %x\n",
3450 params->phy[actual_phy_idx].req_flow_ctrl,
3451 params->phy[actual_phy_idx].req_line_speed,
3452 params->phy[actual_phy_idx].speed_cap_mask);
3453 }
3454 }
3455
3456 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3457 struct bnx2x_phy *phy,
3458 struct link_vars *vars)
3459 {
3460 u16 val;
3461 struct bnx2x *bp = params->bp;
3462
3463 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3464
3465 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3466
3467
3468 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3469 if ((vars->ieee_fc &
3470 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3471 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3472 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3473 }
3474 if ((vars->ieee_fc &
3475 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3476 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3477 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3478 }
3479 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3480 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3481 }
3482
3483 static void bnx2x_pause_resolve(struct bnx2x_phy *phy,
3484 struct link_params *params,
3485 struct link_vars *vars,
3486 u32 pause_result)
3487 {
3488 struct bnx2x *bp = params->bp;
3489
3490 switch (pause_result) {
3491 case 0xb:
3492 DP(NETIF_MSG_LINK, "Flow Control: TX only\n");
3493 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3494 break;
3495
3496 case 0xe:
3497 DP(NETIF_MSG_LINK, "Flow Control: RX only\n");
3498 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3499 break;
3500
3501 case 0x5:
3502 case 0x7:
3503 case 0xd:
3504 case 0xf:
3505
3506
3507
3508
3509 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
3510 DP(NETIF_MSG_LINK, "Flow Control: RX & TX\n");
3511 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3512 } else {
3513 DP(NETIF_MSG_LINK, "Flow Control: RX only\n");
3514 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3515 }
3516 break;
3517
3518 default:
3519 DP(NETIF_MSG_LINK, "Flow Control: None\n");
3520 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3521 break;
3522 }
3523 if (pause_result & (1<<0))
3524 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3525 if (pause_result & (1<<1))
3526 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3527
3528 }
3529
3530 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3531 struct link_params *params,
3532 struct link_vars *vars)
3533 {
3534 u16 ld_pause;
3535 u16 lp_pause;
3536 u16 pause_result;
3537 struct bnx2x *bp = params->bp;
3538 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3539 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3540 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3541 } else if (CHIP_IS_E3(bp) &&
3542 SINGLE_MEDIA_DIRECT(params)) {
3543 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3544 u16 gp_status, gp_mask;
3545 bnx2x_cl45_read(bp, phy,
3546 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3547 &gp_status);
3548 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3549 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3550 lane;
3551 if ((gp_status & gp_mask) == gp_mask) {
3552 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3553 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3554 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3555 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3556 } else {
3557 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3558 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3559 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3560 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3561 ld_pause = ((ld_pause &
3562 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3563 << 3);
3564 lp_pause = ((lp_pause &
3565 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3566 << 3);
3567 }
3568 } else {
3569 bnx2x_cl45_read(bp, phy,
3570 MDIO_AN_DEVAD,
3571 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3572 bnx2x_cl45_read(bp, phy,
3573 MDIO_AN_DEVAD,
3574 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3575 }
3576 pause_result = (ld_pause &
3577 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3578 pause_result |= (lp_pause &
3579 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3580 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3581 bnx2x_pause_resolve(phy, params, vars, pause_result);
3582
3583 }
3584
3585 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3586 struct link_params *params,
3587 struct link_vars *vars)
3588 {
3589 u8 ret = 0;
3590 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3591 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3592
3593 if (phy->req_line_speed == SPEED_AUTO_NEG)
3594 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3595
3596 vars->flow_ctrl = phy->req_flow_ctrl;
3597 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3598 vars->flow_ctrl = params->req_fc_auto_adv;
3599 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3600 ret = 1;
3601 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3602 }
3603 return ret;
3604 }
3605
3606
3607
3608
3609
3610
3611
3612
3613 #define WC_TX_DRIVER(post2, idriver, ipre, ifir) \
3614 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3615 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3616 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \
3617 (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET))
3618
3619 #define WC_TX_FIR(post, main, pre) \
3620 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3621 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3622 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3623
3624 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3625 struct link_params *params,
3626 struct link_vars *vars)
3627 {
3628 struct bnx2x *bp = params->bp;
3629 u16 i;
3630 static struct bnx2x_reg_set reg_set[] = {
3631
3632 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3633 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3634 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3635 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3636 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3637 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3638
3639 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3640 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3641 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3642 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3643 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3644 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3645 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3646 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3647 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3648 };
3649 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3650
3651 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3652 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3653
3654 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3655 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3656 reg_set[i].val);
3657
3658
3659 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3660 bnx2x_update_link_attr(params, params->link_attr_sync);
3661 }
3662
3663 static void bnx2x_disable_kr2(struct link_params *params,
3664 struct link_vars *vars,
3665 struct bnx2x_phy *phy)
3666 {
3667 struct bnx2x *bp = params->bp;
3668 int i;
3669 static struct bnx2x_reg_set reg_set[] = {
3670
3671 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3672 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3673 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3674 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3675 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3676 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3677 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3678 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3679 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3680 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3681 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3682 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3683 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3684 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3685 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3686 };
3687 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
3688
3689 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3690 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3691 reg_set[i].val);
3692 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3693 bnx2x_update_link_attr(params, params->link_attr_sync);
3694
3695 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
3696 }
3697
3698 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3699 struct link_params *params)
3700 {
3701 struct bnx2x *bp = params->bp;
3702
3703 DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3704 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3705 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3706 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3707 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3708 }
3709
3710 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3711 struct link_params *params)
3712 {
3713
3714 struct bnx2x *bp = params->bp;
3715 u16 lane = bnx2x_get_warpcore_lane(phy, params);
3716 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3717 MDIO_AER_BLOCK_AER_REG, lane);
3718 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3719 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3720
3721
3722 bnx2x_set_aer_mmd(params, phy);
3723 }
3724
3725 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3726 struct link_params *params,
3727 struct link_vars *vars) {
3728 u16 lane, i, cl72_ctrl, an_adv = 0, val;
3729 u32 wc_lane_config;
3730 struct bnx2x *bp = params->bp;
3731 static struct bnx2x_reg_set reg_set[] = {
3732 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3733 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3734 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3735 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3736
3737 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3738 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3739 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3740 };
3741 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3742
3743 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3744 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3745 reg_set[i].val);
3746
3747 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3748 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3749 cl72_ctrl &= 0x08ff;
3750 cl72_ctrl |= 0x3800;
3751 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3752 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3753
3754
3755 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3756 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3757 (vars->line_speed == SPEED_1000)) {
3758 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3759 an_adv |= (1<<5);
3760
3761
3762 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3763 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3764 }
3765 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3766 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3767 (vars->line_speed == SPEED_10000)) {
3768
3769 an_adv |= (1<<7);
3770
3771 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3772 MDIO_AER_BLOCK_AER_REG, 0);
3773
3774 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3775 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3776 bnx2x_set_aer_mmd(params, phy);
3777 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3778 }
3779
3780
3781 lane = bnx2x_get_warpcore_lane(phy, params);
3782 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3783 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3784 WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
3785
3786 if (phy->flags & FLAGS_WC_DUAL_MODE)
3787 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3788 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3789 WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
3790 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3791 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3792 0x03f0);
3793 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3794 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3795 0x03f0);
3796
3797
3798 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3799 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3800
3801
3802 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3803 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3804 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3805 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3806
3807
3808 if (REG_RD(bp, params->shmem_base +
3809 offsetof(struct shmem_region, dev_info.
3810 port_hw_config[params->port].default_cfg)) &
3811 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3812 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3813 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3814 1);
3815 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3816 }
3817
3818
3819 bnx2x_ext_phy_set_pause(params, phy, vars);
3820 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3821 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3822 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3823
3824
3825 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3826 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3827
3828 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3829 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3830 (phy->req_line_speed == SPEED_20000)) {
3831
3832 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3833 MDIO_AER_BLOCK_AER_REG, lane);
3834
3835 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3836 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3837 (1<<11));
3838
3839 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3840 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3841 bnx2x_set_aer_mmd(params, phy);
3842
3843 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3844 } else {
3845
3846 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3847 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
3848 wc_lane_config = REG_RD(bp, params->shmem_base +
3849 offsetof(struct shmem_region, dev_info.
3850 shared_hw_config.wc_lane_config));
3851 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3852 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
3853
3854
3855
3856 val |= 1 << 11;
3857
3858
3859
3860
3861 if (wc_lane_config &
3862 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
3863 val |= 3 << 2;
3864 else
3865 val &= ~(3 << 2);
3866 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3867 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
3868 val);
3869
3870 bnx2x_disable_kr2(params, vars, phy);
3871 }
3872
3873
3874 bnx2x_warpcore_restart_AN_KR(phy, params);
3875 }
3876
3877 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3878 struct link_params *params,
3879 struct link_vars *vars)
3880 {
3881 struct bnx2x *bp = params->bp;
3882 u16 val16, i, lane;
3883 static struct bnx2x_reg_set reg_set[] = {
3884
3885 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3886 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3887 0x3f00},
3888 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3889 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3890 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3891 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3892
3893 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3894 };
3895
3896 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3897 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3898 reg_set[i].val);
3899
3900 lane = bnx2x_get_warpcore_lane(phy, params);
3901
3902 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3903 MDIO_AER_BLOCK_AER_REG, 0);
3904
3905 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3906 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3907 val16 &= ~(0x0011 << lane);
3908 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3909 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3910
3911 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3912 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3913 val16 |= (0x0303 << (lane << 1));
3914 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3915 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3916
3917 bnx2x_set_aer_mmd(params, phy);
3918
3919 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3920 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3921
3922 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3923 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3924
3925
3926 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3927 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3928
3929
3930 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3931 MDIO_WC_REG_TX66_CONTROL, 0x9);
3932
3933
3934 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3935 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3936
3937
3938 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3939 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3940 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3941 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3942
3943 }
3944
3945 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3946 struct link_params *params,
3947 u8 is_xfi)
3948 {
3949 struct bnx2x *bp = params->bp;
3950 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3951 u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3952 u32 ifir_val, ipost2_val, ipre_driver_val;
3953
3954
3955 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3956 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3957
3958
3959 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3960 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3961
3962
3963 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3964
3965
3966 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3967 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3968
3969
3970 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3971 MDIO_WC_REG_FX100_CTRL3, 0x0080);
3972
3973
3974 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3975 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3976
3977
3978 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3979 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3980 0xFFEE);
3981
3982
3983 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3984 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3985 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3986 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3987 ((val | 0x0006) & 0xFFFE));
3988
3989
3990 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3991 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3992
3993 misc1_val &= ~(0x1f);
3994
3995 if (is_xfi) {
3996 misc1_val |= 0x5;
3997 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3998 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0);
3999 } else {
4000 cfg_tap_val = REG_RD(bp, params->shmem_base +
4001 offsetof(struct shmem_region, dev_info.
4002 port_hw_config[params->port].
4003 sfi_tap_values));
4004
4005 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4006
4007 misc1_val |= 0x9;
4008
4009
4010 if (tx_equal)
4011 tap_val = (u16)tx_equal;
4012 else
4013 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4014
4015 ifir_val = DEFAULT_TX_DRV_IFIR;
4016 ipost2_val = DEFAULT_TX_DRV_POST2;
4017 ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER;
4018 tx_drv_brdct = DEFAULT_TX_DRV_BRDCT;
4019
4020
4021
4022
4023 if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK |
4024 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK |
4025 PORT_HW_CFG_TX_DRV_POST2_MASK)) {
4026 ifir_val = (cfg_tap_val &
4027 PORT_HW_CFG_TX_DRV_IFIR_MASK) >>
4028 PORT_HW_CFG_TX_DRV_IFIR_SHIFT;
4029 ipre_driver_val = (cfg_tap_val &
4030 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK)
4031 >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT;
4032 ipost2_val = (cfg_tap_val &
4033 PORT_HW_CFG_TX_DRV_POST2_MASK) >>
4034 PORT_HW_CFG_TX_DRV_POST2_SHIFT;
4035 }
4036
4037 if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) {
4038 tx_drv_brdct = (cfg_tap_val &
4039 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4040 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4041 }
4042
4043 tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct,
4044 ipre_driver_val, ifir_val);
4045 }
4046 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4047 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4048
4049
4050 lane = bnx2x_get_warpcore_lane(phy, params);
4051 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4052 MDIO_WC_REG_TX_FIR_TAP,
4053 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4054 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4055 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4056 tx_driver_val);
4057
4058
4059 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4060 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4061
4062
4063 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4064 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4065
4066 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4067
4068
4069 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4070 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4071
4072
4073 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4074 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4075 0xFFFE);
4076
4077 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4078 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4079 }
4080
4081 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4082 struct link_params *params)
4083 {
4084 u16 val;
4085 struct bnx2x *bp = params->bp;
4086
4087 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4088 MDIO_AER_BLOCK_AER_REG, 0);
4089
4090
4091 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4092 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4093
4094 bnx2x_set_aer_mmd(params, phy);
4095
4096 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4097 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4098 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4099 MDIO_AN_REG_CTRL, 0);
4100
4101 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4102 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4103 val &= ~(1<<5);
4104 val |= (1<<6);
4105 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4106 MDIO_WC_REG_CL73_USERB0_CTRL, val);
4107
4108
4109 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4110 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4111
4112 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4113 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4114
4115 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4116 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4117 val &= ~(3<<14);
4118 val |= (1<<15);
4119 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4120 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4121 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4122 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4123
4124
4125 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4126 MDIO_AER_BLOCK_AER_REG, 0);
4127
4128 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4129 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4130
4131 bnx2x_set_aer_mmd(params, phy);
4132 }
4133
4134 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4135 struct bnx2x_phy *phy,
4136 u16 lane)
4137 {
4138
4139 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4140 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4141
4142
4143 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4144 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4145
4146 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4147 MDIO_WC_REG_RX66_SCW0, 0xE070);
4148
4149 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4150 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4151
4152 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4153 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4154
4155 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4156 MDIO_WC_REG_RX66_SCW3, 0x8090);
4157
4158 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4159 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4160
4161 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4162 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4163
4164 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4165 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4166
4167 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4168 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4169
4170
4171 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4172 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4173
4174
4175 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4176 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4177
4178
4179 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4180 MDIO_WC_REG_TX_FIR_TAP,
4181 (WC_TX_FIR(0x12, 0x2d, 0x00) |
4182 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4183 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4184 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4185 WC_TX_DRIVER(0x02, 0x02, 0x02, 0));
4186 }
4187
4188 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4189 struct link_params *params,
4190 u8 fiber_mode,
4191 u8 always_autoneg)
4192 {
4193 struct bnx2x *bp = params->bp;
4194 u16 val16, digctrl_kx1, digctrl_kx2;
4195
4196
4197 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4198 MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4199
4200 bnx2x_warpcore_set_lpi_passthrough(phy, params);
4201
4202 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4203
4204 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4205 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4206 0x1000);
4207 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4208 } else {
4209 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4210 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4211 val16 &= 0xcebf;
4212 switch (phy->req_line_speed) {
4213 case SPEED_10:
4214 break;
4215 case SPEED_100:
4216 val16 |= 0x2000;
4217 break;
4218 case SPEED_1000:
4219 val16 |= 0x0040;
4220 break;
4221 default:
4222 DP(NETIF_MSG_LINK,
4223 "Speed not supported: 0x%x\n", phy->req_line_speed);
4224 return;
4225 }
4226
4227 if (phy->req_duplex == DUPLEX_FULL)
4228 val16 |= 0x0100;
4229
4230 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4231 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4232
4233 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4234 phy->req_line_speed);
4235 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4236 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4237 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
4238 }
4239
4240
4241 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4242 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4243 if (fiber_mode)
4244 digctrl_kx1 = 1;
4245 else
4246 digctrl_kx1 &= 0xff4a;
4247
4248 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4249 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4250 digctrl_kx1);
4251
4252
4253 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4254 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4255 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4256 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4257 (digctrl_kx2 & ~(1<<2)));
4258
4259
4260 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4261 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4262 (digctrl_kx2 | (1<<2)));
4263
4264
4265 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4266 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4267 (digctrl_kx1 | 0x10));
4268 }
4269
4270 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4271 struct bnx2x_phy *phy,
4272 u8 reset)
4273 {
4274 u16 val;
4275
4276 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4277 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4278 if (reset)
4279 val |= 0xC000;
4280 else
4281 val &= 0x3FFF;
4282 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4283 MDIO_WC_REG_DIGITAL5_MISC6, val);
4284 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4285 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4286 }
4287
4288 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4289 struct link_params *params,
4290 u16 lane)
4291 {
4292 struct bnx2x *bp = params->bp;
4293 u16 i;
4294 static struct bnx2x_reg_set wc_regs[] = {
4295 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4296 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4297 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4298 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4299 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4300 0x0195},
4301 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4302 0x0007},
4303 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4304 0x0002},
4305 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4306 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4307 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4308 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4309 };
4310
4311 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4312 MDIO_WC_REG_RX66_CONTROL, (3<<13));
4313
4314 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4315 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4316 wc_regs[i].val);
4317
4318 lane = bnx2x_get_warpcore_lane(phy, params);
4319 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4320 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4321
4322 }
4323
4324 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4325 u32 chip_id,
4326 u32 shmem_base, u8 port,
4327 u8 *gpio_num, u8 *gpio_port)
4328 {
4329 u32 cfg_pin;
4330 *gpio_num = 0;
4331 *gpio_port = 0;
4332 if (CHIP_IS_E3(bp)) {
4333 cfg_pin = (REG_RD(bp, shmem_base +
4334 offsetof(struct shmem_region,
4335 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4336 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4337 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4338
4339
4340
4341
4342
4343
4344
4345 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4346 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4347 DP(NETIF_MSG_LINK,
4348 "No cfg pin %x for module detect indication\n",
4349 cfg_pin);
4350 return -EINVAL;
4351 }
4352
4353 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4354 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4355 } else {
4356 *gpio_num = MISC_REGISTERS_GPIO_3;
4357 *gpio_port = port;
4358 }
4359
4360 return 0;
4361 }
4362
4363 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4364 struct link_params *params)
4365 {
4366 struct bnx2x *bp = params->bp;
4367 u8 gpio_num, gpio_port;
4368 u32 gpio_val;
4369 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4370 params->shmem_base, params->port,
4371 &gpio_num, &gpio_port) != 0)
4372 return 0;
4373 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4374
4375
4376 if (gpio_val == 0)
4377 return 1;
4378 else
4379 return 0;
4380 }
4381 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4382 struct link_params *params)
4383 {
4384 u16 gp2_status_reg0, lane;
4385 struct bnx2x *bp = params->bp;
4386
4387 lane = bnx2x_get_warpcore_lane(phy, params);
4388
4389 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4390 &gp2_status_reg0);
4391
4392 return (gp2_status_reg0 >> (8+lane)) & 0x1;
4393 }
4394
4395 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4396 struct link_params *params,
4397 struct link_vars *vars)
4398 {
4399 struct bnx2x *bp = params->bp;
4400 u32 serdes_net_if;
4401 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4402
4403 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4404
4405 if (!vars->turn_to_run_wc_rt)
4406 return;
4407
4408 if (vars->rx_tx_asic_rst) {
4409 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4410 serdes_net_if = (REG_RD(bp, params->shmem_base +
4411 offsetof(struct shmem_region, dev_info.
4412 port_hw_config[params->port].default_cfg)) &
4413 PORT_HW_CFG_NET_SERDES_IF_MASK);
4414
4415 switch (serdes_net_if) {
4416 case PORT_HW_CFG_NET_SERDES_IF_KR:
4417
4418 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4419 &gp_status1);
4420 lnkup = (gp_status1 >> (8+lane)) & 0x1;
4421
4422 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4423
4424 if (lnkup_kr || lnkup) {
4425 vars->rx_tx_asic_rst = 0;
4426 } else {
4427
4428 bnx2x_warpcore_reset_lane(bp, phy, 1);
4429 bnx2x_warpcore_reset_lane(bp, phy, 0);
4430
4431
4432 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4433 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4434
4435 vars->rx_tx_asic_rst--;
4436 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4437 vars->rx_tx_asic_rst);
4438 }
4439 break;
4440
4441 default:
4442 break;
4443 }
4444
4445 }
4446
4447 }
4448 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4449 struct link_params *params)
4450 {
4451 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4452 struct bnx2x *bp = params->bp;
4453 bnx2x_warpcore_clear_regs(phy, params, lane);
4454 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4455 SPEED_10000) &&
4456 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4457 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4458 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4459 } else {
4460 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4461 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4462 }
4463 }
4464
4465 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4466 struct bnx2x_phy *phy,
4467 u8 tx_en)
4468 {
4469 struct bnx2x *bp = params->bp;
4470 u32 cfg_pin;
4471 u8 port = params->port;
4472
4473 cfg_pin = REG_RD(bp, params->shmem_base +
4474 offsetof(struct shmem_region,
4475 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4476 PORT_HW_CFG_E3_TX_LASER_MASK;
4477
4478 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4479
4480
4481 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4482 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4483 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4484 }
4485
4486 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4487 struct link_params *params,
4488 struct link_vars *vars)
4489 {
4490 struct bnx2x *bp = params->bp;
4491 u32 serdes_net_if;
4492 u8 fiber_mode;
4493 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4494 serdes_net_if = (REG_RD(bp, params->shmem_base +
4495 offsetof(struct shmem_region, dev_info.
4496 port_hw_config[params->port].default_cfg)) &
4497 PORT_HW_CFG_NET_SERDES_IF_MASK);
4498 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4499 "serdes_net_if = 0x%x\n",
4500 vars->line_speed, serdes_net_if);
4501 bnx2x_set_aer_mmd(params, phy);
4502 bnx2x_warpcore_reset_lane(bp, phy, 1);
4503 vars->phy_flags |= PHY_XGXS_FLAG;
4504 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4505 (phy->req_line_speed &&
4506 ((phy->req_line_speed == SPEED_100) ||
4507 (phy->req_line_speed == SPEED_10)))) {
4508 vars->phy_flags |= PHY_SGMII_FLAG;
4509 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4510 bnx2x_warpcore_clear_regs(phy, params, lane);
4511 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4512 } else {
4513 switch (serdes_net_if) {
4514 case PORT_HW_CFG_NET_SERDES_IF_KR:
4515
4516 if (params->loopback_mode != LOOPBACK_EXT)
4517 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4518 else {
4519 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4520 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4521 }
4522 break;
4523
4524 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4525 bnx2x_warpcore_clear_regs(phy, params, lane);
4526 if (vars->line_speed == SPEED_10000) {
4527 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4528 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4529 } else {
4530 if (SINGLE_MEDIA_DIRECT(params)) {
4531 DP(NETIF_MSG_LINK, "1G Fiber\n");
4532 fiber_mode = 1;
4533 } else {
4534 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4535 fiber_mode = 0;
4536 }
4537 bnx2x_warpcore_set_sgmii_speed(phy,
4538 params,
4539 fiber_mode,
4540 0);
4541 }
4542
4543 break;
4544
4545 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4546
4547
4548
4549
4550 if ((params->loopback_mode == LOOPBACK_NONE) ||
4551 (params->loopback_mode == LOOPBACK_EXT)) {
4552 if (bnx2x_is_sfp_module_plugged(phy, params))
4553 bnx2x_sfp_module_detection(phy, params);
4554 else
4555 bnx2x_sfp_e3_set_transmitter(params,
4556 phy, 1);
4557 }
4558
4559 bnx2x_warpcore_config_sfi(phy, params);
4560 break;
4561
4562 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4563 if (vars->line_speed != SPEED_20000) {
4564 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4565 return;
4566 }
4567 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4568 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4569
4570
4571 bnx2x_sfp_module_detection(phy, params);
4572 break;
4573 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4574 if (!params->loopback_mode) {
4575 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4576 } else {
4577 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4578 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4579 }
4580 break;
4581 default:
4582 DP(NETIF_MSG_LINK,
4583 "Unsupported Serdes Net Interface 0x%x\n",
4584 serdes_net_if);
4585 return;
4586 }
4587 }
4588
4589
4590 bnx2x_warpcore_reset_lane(bp, phy, 0);
4591 DP(NETIF_MSG_LINK, "Exit config init\n");
4592 }
4593
4594 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4595 struct link_params *params)
4596 {
4597 struct bnx2x *bp = params->bp;
4598 u16 val16, lane;
4599 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4600 bnx2x_set_mdio_emac_per_phy(bp, params);
4601 bnx2x_set_aer_mmd(params, phy);
4602
4603 bnx2x_warpcore_reset_lane(bp, phy, 1);
4604
4605
4606
4607 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4608 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4609
4610 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4611 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4612
4613
4614 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4615 MDIO_AER_BLOCK_AER_REG, 0);
4616
4617 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4618 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4619 ~0x10);
4620
4621 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4622 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4623 lane = bnx2x_get_warpcore_lane(phy, params);
4624
4625 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4626 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4627 val16 |= (0x11 << lane);
4628 if (phy->flags & FLAGS_WC_DUAL_MODE)
4629 val16 |= (0x22 << lane);
4630 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4631 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4632
4633 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4634 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4635 val16 &= ~(0x0303 << (lane << 1));
4636 val16 |= (0x0101 << (lane << 1));
4637 if (phy->flags & FLAGS_WC_DUAL_MODE) {
4638 val16 &= ~(0x0c0c << (lane << 1));
4639 val16 |= (0x0404 << (lane << 1));
4640 }
4641
4642 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4643 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4644
4645 bnx2x_set_aer_mmd(params, phy);
4646
4647 }
4648
4649 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4650 struct link_params *params)
4651 {
4652 struct bnx2x *bp = params->bp;
4653 u16 val16;
4654 u32 lane;
4655 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4656 params->loopback_mode, phy->req_line_speed);
4657
4658 if (phy->req_line_speed < SPEED_10000 ||
4659 phy->supported & SUPPORTED_20000baseKR2_Full) {
4660
4661
4662
4663 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4664 MDIO_AER_BLOCK_AER_REG, 0);
4665
4666 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4667 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4668 0x10);
4669
4670 lane = bnx2x_get_warpcore_lane(phy, params);
4671 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4672 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4673 val16 |= (1<<lane);
4674 if (phy->flags & FLAGS_WC_DUAL_MODE)
4675 val16 |= (2<<lane);
4676 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4677 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4678 val16);
4679
4680
4681 bnx2x_set_aer_mmd(params, phy);
4682 } else {
4683
4684 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4685 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4686 0x4000);
4687 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4688 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4689 }
4690 }
4691
4692
4693
4694 static void bnx2x_sync_link(struct link_params *params,
4695 struct link_vars *vars)
4696 {
4697 struct bnx2x *bp = params->bp;
4698 u8 link_10g_plus;
4699 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4700 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4701 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4702 if (vars->link_up) {
4703 DP(NETIF_MSG_LINK, "phy link up\n");
4704
4705 vars->phy_link_up = 1;
4706 vars->duplex = DUPLEX_FULL;
4707 switch (vars->link_status &
4708 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4709 case LINK_10THD:
4710 vars->duplex = DUPLEX_HALF;
4711
4712 case LINK_10TFD:
4713 vars->line_speed = SPEED_10;
4714 break;
4715
4716 case LINK_100TXHD:
4717 vars->duplex = DUPLEX_HALF;
4718
4719 case LINK_100T4:
4720 case LINK_100TXFD:
4721 vars->line_speed = SPEED_100;
4722 break;
4723
4724 case LINK_1000THD:
4725 vars->duplex = DUPLEX_HALF;
4726
4727 case LINK_1000TFD:
4728 vars->line_speed = SPEED_1000;
4729 break;
4730
4731 case LINK_2500THD:
4732 vars->duplex = DUPLEX_HALF;
4733
4734 case LINK_2500TFD:
4735 vars->line_speed = SPEED_2500;
4736 break;
4737
4738 case LINK_10GTFD:
4739 vars->line_speed = SPEED_10000;
4740 break;
4741 case LINK_20GTFD:
4742 vars->line_speed = SPEED_20000;
4743 break;
4744 default:
4745 break;
4746 }
4747 vars->flow_ctrl = 0;
4748 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4749 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4750
4751 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4752 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4753
4754 if (!vars->flow_ctrl)
4755 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4756
4757 if (vars->line_speed &&
4758 ((vars->line_speed == SPEED_10) ||
4759 (vars->line_speed == SPEED_100))) {
4760 vars->phy_flags |= PHY_SGMII_FLAG;
4761 } else {
4762 vars->phy_flags &= ~PHY_SGMII_FLAG;
4763 }
4764 if (vars->line_speed &&
4765 USES_WARPCORE(bp) &&
4766 (vars->line_speed == SPEED_1000))
4767 vars->phy_flags |= PHY_SGMII_FLAG;
4768
4769 link_10g_plus = (vars->line_speed >= SPEED_10000);
4770
4771 if (link_10g_plus) {
4772 if (USES_WARPCORE(bp))
4773 vars->mac_type = MAC_TYPE_XMAC;
4774 else
4775 vars->mac_type = MAC_TYPE_BMAC;
4776 } else {
4777 if (USES_WARPCORE(bp))
4778 vars->mac_type = MAC_TYPE_UMAC;
4779 else
4780 vars->mac_type = MAC_TYPE_EMAC;
4781 }
4782 } else {
4783 DP(NETIF_MSG_LINK, "phy link down\n");
4784
4785 vars->phy_link_up = 0;
4786
4787 vars->line_speed = 0;
4788 vars->duplex = DUPLEX_FULL;
4789 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4790
4791
4792 vars->mac_type = MAC_TYPE_NONE;
4793 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4794 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4795 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4796 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4797 }
4798 }
4799
4800 void bnx2x_link_status_update(struct link_params *params,
4801 struct link_vars *vars)
4802 {
4803 struct bnx2x *bp = params->bp;
4804 u8 port = params->port;
4805 u32 sync_offset, media_types;
4806
4807 set_phy_vars(params, vars);
4808
4809 vars->link_status = REG_RD(bp, params->shmem_base +
4810 offsetof(struct shmem_region,
4811 port_mb[port].link_status));
4812
4813
4814 if (params->loopback_mode != LOOPBACK_NONE &&
4815 params->loopback_mode != LOOPBACK_EXT)
4816 vars->link_status |= LINK_STATUS_LINK_UP;
4817
4818 if (bnx2x_eee_has_cap(params))
4819 vars->eee_status = REG_RD(bp, params->shmem2_base +
4820 offsetof(struct shmem2_region,
4821 eee_status[params->port]));
4822
4823 vars->phy_flags = PHY_XGXS_FLAG;
4824 bnx2x_sync_link(params, vars);
4825
4826 sync_offset = params->shmem_base +
4827 offsetof(struct shmem_region,
4828 dev_info.port_hw_config[port].media_type);
4829 media_types = REG_RD(bp, sync_offset);
4830
4831 params->phy[INT_PHY].media_type =
4832 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4833 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4834 params->phy[EXT_PHY1].media_type =
4835 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4836 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4837 params->phy[EXT_PHY2].media_type =
4838 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4839 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4840 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4841
4842
4843 sync_offset = params->shmem_base +
4844 offsetof(struct shmem_region,
4845 dev_info.port_hw_config[port].aeu_int_mask);
4846
4847 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4848
4849
4850 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4851 params->feature_config_flags |=
4852 FEATURE_CONFIG_PFC_ENABLED;
4853 else
4854 params->feature_config_flags &=
4855 ~FEATURE_CONFIG_PFC_ENABLED;
4856
4857 if (SHMEM2_HAS(bp, link_attr_sync))
4858 params->link_attr_sync = SHMEM2_RD(bp,
4859 link_attr_sync[params->port]);
4860
4861 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4862 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4863 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4864 vars->line_speed, vars->duplex, vars->flow_ctrl);
4865 }
4866
4867 static void bnx2x_set_master_ln(struct link_params *params,
4868 struct bnx2x_phy *phy)
4869 {
4870 struct bnx2x *bp = params->bp;
4871 u16 new_master_ln, ser_lane;
4872 ser_lane = ((params->lane_config &
4873 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4874 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4875
4876
4877 CL22_RD_OVER_CL45(bp, phy,
4878 MDIO_REG_BANK_XGXS_BLOCK2,
4879 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4880 &new_master_ln);
4881
4882 CL22_WR_OVER_CL45(bp, phy,
4883 MDIO_REG_BANK_XGXS_BLOCK2 ,
4884 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4885 (new_master_ln | ser_lane));
4886 }
4887
4888 static int bnx2x_reset_unicore(struct link_params *params,
4889 struct bnx2x_phy *phy,
4890 u8 set_serdes)
4891 {
4892 struct bnx2x *bp = params->bp;
4893 u16 mii_control;
4894 u16 i;
4895 CL22_RD_OVER_CL45(bp, phy,
4896 MDIO_REG_BANK_COMBO_IEEE0,
4897 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4898
4899
4900 CL22_WR_OVER_CL45(bp, phy,
4901 MDIO_REG_BANK_COMBO_IEEE0,
4902 MDIO_COMBO_IEEE0_MII_CONTROL,
4903 (mii_control |
4904 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4905 if (set_serdes)
4906 bnx2x_set_serdes_access(bp, params->port);
4907
4908
4909 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4910 udelay(5);
4911
4912
4913 CL22_RD_OVER_CL45(bp, phy,
4914 MDIO_REG_BANK_COMBO_IEEE0,
4915 MDIO_COMBO_IEEE0_MII_CONTROL,
4916 &mii_control);
4917
4918 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4919 udelay(5);
4920 return 0;
4921 }
4922 }
4923
4924 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4925 " Port %d\n",
4926 params->port);
4927 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4928 return -EINVAL;
4929
4930 }
4931
4932 static void bnx2x_set_swap_lanes(struct link_params *params,
4933 struct bnx2x_phy *phy)
4934 {
4935 struct bnx2x *bp = params->bp;
4936
4937
4938
4939 u16 rx_lane_swap, tx_lane_swap;
4940
4941 rx_lane_swap = ((params->lane_config &
4942 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4943 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4944 tx_lane_swap = ((params->lane_config &
4945 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4946 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4947
4948 if (rx_lane_swap != 0x1b) {
4949 CL22_WR_OVER_CL45(bp, phy,
4950 MDIO_REG_BANK_XGXS_BLOCK2,
4951 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4952 (rx_lane_swap |
4953 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4954 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4955 } else {
4956 CL22_WR_OVER_CL45(bp, phy,
4957 MDIO_REG_BANK_XGXS_BLOCK2,
4958 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4959 }
4960
4961 if (tx_lane_swap != 0x1b) {
4962 CL22_WR_OVER_CL45(bp, phy,
4963 MDIO_REG_BANK_XGXS_BLOCK2,
4964 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4965 (tx_lane_swap |
4966 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4967 } else {
4968 CL22_WR_OVER_CL45(bp, phy,
4969 MDIO_REG_BANK_XGXS_BLOCK2,
4970 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4971 }
4972 }
4973
4974 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4975 struct link_params *params)
4976 {
4977 struct bnx2x *bp = params->bp;
4978 u16 control2;
4979 CL22_RD_OVER_CL45(bp, phy,
4980 MDIO_REG_BANK_SERDES_DIGITAL,
4981 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4982 &control2);
4983 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4984 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4985 else
4986 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4987 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4988 phy->speed_cap_mask, control2);
4989 CL22_WR_OVER_CL45(bp, phy,
4990 MDIO_REG_BANK_SERDES_DIGITAL,
4991 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4992 control2);
4993
4994 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4995 (phy->speed_cap_mask &
4996 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4997 DP(NETIF_MSG_LINK, "XGXS\n");
4998
4999 CL22_WR_OVER_CL45(bp, phy,
5000 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5001 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
5002 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
5003
5004 CL22_RD_OVER_CL45(bp, phy,
5005 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5006 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5007 &control2);
5008
5009
5010 control2 |=
5011 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5012
5013 CL22_WR_OVER_CL45(bp, phy,
5014 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5015 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5016 control2);
5017
5018
5019 CL22_WR_OVER_CL45(bp, phy,
5020 MDIO_REG_BANK_XGXS_BLOCK2,
5021 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5022 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5023 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5024 }
5025 }
5026
5027 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
5028 struct link_params *params,
5029 struct link_vars *vars,
5030 u8 enable_cl73)
5031 {
5032 struct bnx2x *bp = params->bp;
5033 u16 reg_val;
5034
5035
5036 CL22_RD_OVER_CL45(bp, phy,
5037 MDIO_REG_BANK_COMBO_IEEE0,
5038 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5039
5040
5041 if (vars->line_speed == SPEED_AUTO_NEG)
5042 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5043 else
5044 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5045 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5046
5047 CL22_WR_OVER_CL45(bp, phy,
5048 MDIO_REG_BANK_COMBO_IEEE0,
5049 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5050
5051
5052
5053 CL22_RD_OVER_CL45(bp, phy,
5054 MDIO_REG_BANK_SERDES_DIGITAL,
5055 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
5056 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5057 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5058 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5059 if (vars->line_speed == SPEED_AUTO_NEG)
5060 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5061 else
5062 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5063
5064 CL22_WR_OVER_CL45(bp, phy,
5065 MDIO_REG_BANK_SERDES_DIGITAL,
5066 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5067
5068
5069 CL22_RD_OVER_CL45(bp, phy,
5070 MDIO_REG_BANK_BAM_NEXT_PAGE,
5071 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5072 ®_val);
5073 if (vars->line_speed == SPEED_AUTO_NEG) {
5074
5075 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5076 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5077 } else {
5078
5079 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5080 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5081 }
5082 CL22_WR_OVER_CL45(bp, phy,
5083 MDIO_REG_BANK_BAM_NEXT_PAGE,
5084 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5085 reg_val);
5086
5087 if (enable_cl73) {
5088
5089 CL22_WR_OVER_CL45(bp, phy,
5090 MDIO_REG_BANK_CL73_USERB0,
5091 MDIO_CL73_USERB0_CL73_UCTRL,
5092 0xe);
5093
5094
5095 CL22_WR_OVER_CL45(bp, phy,
5096 MDIO_REG_BANK_CL73_USERB0,
5097 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5098 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5099 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5100 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5101
5102
5103 CL22_RD_OVER_CL45(bp, phy,
5104 MDIO_REG_BANK_CL73_IEEEB1,
5105 MDIO_CL73_IEEEB1_AN_ADV2,
5106 ®_val);
5107 if (phy->speed_cap_mask &
5108 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5109 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5110 if (phy->speed_cap_mask &
5111 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5112 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5113
5114 CL22_WR_OVER_CL45(bp, phy,
5115 MDIO_REG_BANK_CL73_IEEEB1,
5116 MDIO_CL73_IEEEB1_AN_ADV2,
5117 reg_val);
5118
5119
5120 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5121
5122 } else
5123 reg_val = 0;
5124
5125 CL22_WR_OVER_CL45(bp, phy,
5126 MDIO_REG_BANK_CL73_IEEEB0,
5127 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5128 }
5129
5130
5131 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5132 struct link_params *params,
5133 struct link_vars *vars)
5134 {
5135 struct bnx2x *bp = params->bp;
5136 u16 reg_val;
5137
5138
5139 CL22_RD_OVER_CL45(bp, phy,
5140 MDIO_REG_BANK_COMBO_IEEE0,
5141 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5142 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5143 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5144 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5145 if (phy->req_duplex == DUPLEX_FULL)
5146 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5147 CL22_WR_OVER_CL45(bp, phy,
5148 MDIO_REG_BANK_COMBO_IEEE0,
5149 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5150
5151
5152
5153
5154 CL22_RD_OVER_CL45(bp, phy,
5155 MDIO_REG_BANK_SERDES_DIGITAL,
5156 MDIO_SERDES_DIGITAL_MISC1, ®_val);
5157
5158 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5159
5160 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5161 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5162
5163 if (!((vars->line_speed == SPEED_1000) ||
5164 (vars->line_speed == SPEED_100) ||
5165 (vars->line_speed == SPEED_10))) {
5166
5167 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5168 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5169 if (vars->line_speed == SPEED_10000)
5170 reg_val |=
5171 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5172 }
5173
5174 CL22_WR_OVER_CL45(bp, phy,
5175 MDIO_REG_BANK_SERDES_DIGITAL,
5176 MDIO_SERDES_DIGITAL_MISC1, reg_val);
5177
5178 }
5179
5180 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5181 struct link_params *params)
5182 {
5183 struct bnx2x *bp = params->bp;
5184 u16 val = 0;
5185
5186
5187 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5188 val |= MDIO_OVER_1G_UP1_2_5G;
5189 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5190 val |= MDIO_OVER_1G_UP1_10G;
5191 CL22_WR_OVER_CL45(bp, phy,
5192 MDIO_REG_BANK_OVER_1G,
5193 MDIO_OVER_1G_UP1, val);
5194
5195 CL22_WR_OVER_CL45(bp, phy,
5196 MDIO_REG_BANK_OVER_1G,
5197 MDIO_OVER_1G_UP3, 0x400);
5198 }
5199
5200 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5201 struct link_params *params,
5202 u16 ieee_fc)
5203 {
5204 struct bnx2x *bp = params->bp;
5205 u16 val;
5206
5207
5208 CL22_WR_OVER_CL45(bp, phy,
5209 MDIO_REG_BANK_COMBO_IEEE0,
5210 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5211 CL22_RD_OVER_CL45(bp, phy,
5212 MDIO_REG_BANK_CL73_IEEEB1,
5213 MDIO_CL73_IEEEB1_AN_ADV1, &val);
5214 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5215 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5216 CL22_WR_OVER_CL45(bp, phy,
5217 MDIO_REG_BANK_CL73_IEEEB1,
5218 MDIO_CL73_IEEEB1_AN_ADV1, val);
5219 }
5220
5221 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5222 struct link_params *params,
5223 u8 enable_cl73)
5224 {
5225 struct bnx2x *bp = params->bp;
5226 u16 mii_control;
5227
5228 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5229
5230
5231 if (enable_cl73) {
5232 CL22_RD_OVER_CL45(bp, phy,
5233 MDIO_REG_BANK_CL73_IEEEB0,
5234 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5235 &mii_control);
5236
5237 CL22_WR_OVER_CL45(bp, phy,
5238 MDIO_REG_BANK_CL73_IEEEB0,
5239 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5240 (mii_control |
5241 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5242 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5243 } else {
5244
5245 CL22_RD_OVER_CL45(bp, phy,
5246 MDIO_REG_BANK_COMBO_IEEE0,
5247 MDIO_COMBO_IEEE0_MII_CONTROL,
5248 &mii_control);
5249 DP(NETIF_MSG_LINK,
5250 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5251 mii_control);
5252 CL22_WR_OVER_CL45(bp, phy,
5253 MDIO_REG_BANK_COMBO_IEEE0,
5254 MDIO_COMBO_IEEE0_MII_CONTROL,
5255 (mii_control |
5256 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5257 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5258 }
5259 }
5260
5261 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5262 struct link_params *params,
5263 struct link_vars *vars)
5264 {
5265 struct bnx2x *bp = params->bp;
5266 u16 control1;
5267
5268
5269
5270 CL22_RD_OVER_CL45(bp, phy,
5271 MDIO_REG_BANK_SERDES_DIGITAL,
5272 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5273 &control1);
5274 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5275
5276 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5277 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5278 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5279 CL22_WR_OVER_CL45(bp, phy,
5280 MDIO_REG_BANK_SERDES_DIGITAL,
5281 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5282 control1);
5283
5284
5285 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5286
5287 u16 mii_control;
5288
5289 CL22_RD_OVER_CL45(bp, phy,
5290 MDIO_REG_BANK_COMBO_IEEE0,
5291 MDIO_COMBO_IEEE0_MII_CONTROL,
5292 &mii_control);
5293 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5294 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5295 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5296
5297 switch (vars->line_speed) {
5298 case SPEED_100:
5299 mii_control |=
5300 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5301 break;
5302 case SPEED_1000:
5303 mii_control |=
5304 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5305 break;
5306 case SPEED_10:
5307
5308 break;
5309 default:
5310
5311 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5312 vars->line_speed);
5313 break;
5314 }
5315
5316
5317 if (phy->req_duplex == DUPLEX_FULL)
5318 mii_control |=
5319 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5320 CL22_WR_OVER_CL45(bp, phy,
5321 MDIO_REG_BANK_COMBO_IEEE0,
5322 MDIO_COMBO_IEEE0_MII_CONTROL,
5323 mii_control);
5324
5325 } else {
5326
5327 bnx2x_restart_autoneg(phy, params, 0);
5328 }
5329 }
5330
5331
5332
5333 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5334 struct link_params *params)
5335 {
5336 struct bnx2x *bp = params->bp;
5337 u16 pd_10g, status2_1000x;
5338 if (phy->req_line_speed != SPEED_AUTO_NEG)
5339 return 0;
5340 CL22_RD_OVER_CL45(bp, phy,
5341 MDIO_REG_BANK_SERDES_DIGITAL,
5342 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5343 &status2_1000x);
5344 CL22_RD_OVER_CL45(bp, phy,
5345 MDIO_REG_BANK_SERDES_DIGITAL,
5346 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5347 &status2_1000x);
5348 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5349 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5350 params->port);
5351 return 1;
5352 }
5353
5354 CL22_RD_OVER_CL45(bp, phy,
5355 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5356 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5357 &pd_10g);
5358
5359 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5360 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5361 params->port);
5362 return 1;
5363 }
5364 return 0;
5365 }
5366
5367 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5368 struct link_params *params,
5369 struct link_vars *vars,
5370 u32 gp_status)
5371 {
5372 u16 ld_pause;
5373 u16 lp_pause;
5374 u16 pause_result;
5375 struct bnx2x *bp = params->bp;
5376 if ((gp_status &
5377 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5378 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5379 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5380 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5381
5382 CL22_RD_OVER_CL45(bp, phy,
5383 MDIO_REG_BANK_CL73_IEEEB1,
5384 MDIO_CL73_IEEEB1_AN_ADV1,
5385 &ld_pause);
5386 CL22_RD_OVER_CL45(bp, phy,
5387 MDIO_REG_BANK_CL73_IEEEB1,
5388 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5389 &lp_pause);
5390 pause_result = (ld_pause &
5391 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5392 pause_result |= (lp_pause &
5393 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5394 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5395 } else {
5396 CL22_RD_OVER_CL45(bp, phy,
5397 MDIO_REG_BANK_COMBO_IEEE0,
5398 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5399 &ld_pause);
5400 CL22_RD_OVER_CL45(bp, phy,
5401 MDIO_REG_BANK_COMBO_IEEE0,
5402 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5403 &lp_pause);
5404 pause_result = (ld_pause &
5405 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5406 pause_result |= (lp_pause &
5407 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5408 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5409 }
5410 bnx2x_pause_resolve(phy, params, vars, pause_result);
5411
5412 }
5413
5414 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5415 struct link_params *params,
5416 struct link_vars *vars,
5417 u32 gp_status)
5418 {
5419 struct bnx2x *bp = params->bp;
5420 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5421
5422
5423 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5424
5425 if (phy->req_line_speed == SPEED_AUTO_NEG)
5426 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5427
5428 vars->flow_ctrl = phy->req_flow_ctrl;
5429 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5430 vars->flow_ctrl = params->req_fc_auto_adv;
5431 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5432 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5433 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5434 vars->flow_ctrl = params->req_fc_auto_adv;
5435 return;
5436 }
5437 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5438 }
5439 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5440 }
5441
5442 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5443 struct link_params *params)
5444 {
5445 struct bnx2x *bp = params->bp;
5446 u16 rx_status, ustat_val, cl37_fsm_received;
5447 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5448
5449 CL22_RD_OVER_CL45(bp, phy,
5450 MDIO_REG_BANK_RX0,
5451 MDIO_RX0_RX_STATUS,
5452 &rx_status);
5453 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5454 (MDIO_RX0_RX_STATUS_SIGDET)) {
5455 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5456 "rx_status(0x80b0) = 0x%x\n", rx_status);
5457 CL22_WR_OVER_CL45(bp, phy,
5458 MDIO_REG_BANK_CL73_IEEEB0,
5459 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5460 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5461 return;
5462 }
5463
5464 CL22_RD_OVER_CL45(bp, phy,
5465 MDIO_REG_BANK_CL73_USERB0,
5466 MDIO_CL73_USERB0_CL73_USTAT1,
5467 &ustat_val);
5468 if ((ustat_val &
5469 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5470 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5471 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5472 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5473 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5474 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5475 return;
5476 }
5477
5478
5479
5480 CL22_RD_OVER_CL45(bp, phy,
5481 MDIO_REG_BANK_REMOTE_PHY,
5482 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5483 &cl37_fsm_received);
5484 if ((cl37_fsm_received &
5485 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5486 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5487 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5488 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5489 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5490 "misc_rx_status(0x8330) = 0x%x\n",
5491 cl37_fsm_received);
5492 return;
5493 }
5494
5495
5496
5497
5498
5499
5500
5501 CL22_WR_OVER_CL45(bp, phy,
5502 MDIO_REG_BANK_CL73_IEEEB0,
5503 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5504 0);
5505
5506 bnx2x_restart_autoneg(phy, params, 0);
5507 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5508 }
5509
5510 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5511 struct link_params *params,
5512 struct link_vars *vars,
5513 u32 gp_status)
5514 {
5515 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5516 vars->link_status |=
5517 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5518
5519 if (bnx2x_direct_parallel_detect_used(phy, params))
5520 vars->link_status |=
5521 LINK_STATUS_PARALLEL_DETECTION_USED;
5522 }
5523 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5524 struct link_params *params,
5525 struct link_vars *vars,
5526 u16 is_link_up,
5527 u16 speed_mask,
5528 u16 is_duplex)
5529 {
5530 struct bnx2x *bp = params->bp;
5531 if (phy->req_line_speed == SPEED_AUTO_NEG)
5532 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5533 if (is_link_up) {
5534 DP(NETIF_MSG_LINK, "phy link up\n");
5535
5536 vars->phy_link_up = 1;
5537 vars->link_status |= LINK_STATUS_LINK_UP;
5538
5539 switch (speed_mask) {
5540 case GP_STATUS_10M:
5541 vars->line_speed = SPEED_10;
5542 if (is_duplex == DUPLEX_FULL)
5543 vars->link_status |= LINK_10TFD;
5544 else
5545 vars->link_status |= LINK_10THD;
5546 break;
5547
5548 case GP_STATUS_100M:
5549 vars->line_speed = SPEED_100;
5550 if (is_duplex == DUPLEX_FULL)
5551 vars->link_status |= LINK_100TXFD;
5552 else
5553 vars->link_status |= LINK_100TXHD;
5554 break;
5555
5556 case GP_STATUS_1G:
5557 case GP_STATUS_1G_KX:
5558 vars->line_speed = SPEED_1000;
5559 if (is_duplex == DUPLEX_FULL)
5560 vars->link_status |= LINK_1000TFD;
5561 else
5562 vars->link_status |= LINK_1000THD;
5563 break;
5564
5565 case GP_STATUS_2_5G:
5566 vars->line_speed = SPEED_2500;
5567 if (is_duplex == DUPLEX_FULL)
5568 vars->link_status |= LINK_2500TFD;
5569 else
5570 vars->link_status |= LINK_2500THD;
5571 break;
5572
5573 case GP_STATUS_5G:
5574 case GP_STATUS_6G:
5575 DP(NETIF_MSG_LINK,
5576 "link speed unsupported gp_status 0x%x\n",
5577 speed_mask);
5578 return -EINVAL;
5579
5580 case GP_STATUS_10G_KX4:
5581 case GP_STATUS_10G_HIG:
5582 case GP_STATUS_10G_CX4:
5583 case GP_STATUS_10G_KR:
5584 case GP_STATUS_10G_SFI:
5585 case GP_STATUS_10G_XFI:
5586 vars->line_speed = SPEED_10000;
5587 vars->link_status |= LINK_10GTFD;
5588 break;
5589 case GP_STATUS_20G_DXGXS:
5590 case GP_STATUS_20G_KR2:
5591 vars->line_speed = SPEED_20000;
5592 vars->link_status |= LINK_20GTFD;
5593 break;
5594 default:
5595 DP(NETIF_MSG_LINK,
5596 "link speed unsupported gp_status 0x%x\n",
5597 speed_mask);
5598 return -EINVAL;
5599 }
5600 } else {
5601 DP(NETIF_MSG_LINK, "phy link down\n");
5602
5603 vars->phy_link_up = 0;
5604
5605 vars->duplex = DUPLEX_FULL;
5606 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5607 vars->mac_type = MAC_TYPE_NONE;
5608 }
5609 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5610 vars->phy_link_up, vars->line_speed);
5611 return 0;
5612 }
5613
5614 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5615 struct link_params *params,
5616 struct link_vars *vars)
5617 {
5618 struct bnx2x *bp = params->bp;
5619
5620 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5621 int rc = 0;
5622
5623
5624 CL22_RD_OVER_CL45(bp, phy,
5625 MDIO_REG_BANK_GP_STATUS,
5626 MDIO_GP_STATUS_TOP_AN_STATUS1,
5627 &gp_status);
5628 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5629 duplex = DUPLEX_FULL;
5630 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5631 link_up = 1;
5632 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5633 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5634 gp_status, link_up, speed_mask);
5635 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5636 duplex);
5637 if (rc == -EINVAL)
5638 return rc;
5639
5640 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5641 if (SINGLE_MEDIA_DIRECT(params)) {
5642 vars->duplex = duplex;
5643 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5644 if (phy->req_line_speed == SPEED_AUTO_NEG)
5645 bnx2x_xgxs_an_resolve(phy, params, vars,
5646 gp_status);
5647 }
5648 } else {
5649 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5650 SINGLE_MEDIA_DIRECT(params)) {
5651
5652 bnx2x_check_fallback_to_cl37(phy, params);
5653 }
5654 }
5655
5656
5657 if (SINGLE_MEDIA_DIRECT(params) &&
5658 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5659 u16 val;
5660
5661 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5662 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5663
5664 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5665 vars->link_status |=
5666 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5667 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5668 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5669 vars->link_status |=
5670 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5671
5672 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5673 MDIO_OVER_1G_LP_UP1, &val);
5674
5675 if (val & MDIO_OVER_1G_UP1_2_5G)
5676 vars->link_status |=
5677 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5678 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5679 vars->link_status |=
5680 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5681 }
5682
5683 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5684 vars->duplex, vars->flow_ctrl, vars->link_status);
5685 return rc;
5686 }
5687
5688 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5689 struct link_params *params,
5690 struct link_vars *vars)
5691 {
5692 struct bnx2x *bp = params->bp;
5693 u8 lane;
5694 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5695 int rc = 0;
5696 lane = bnx2x_get_warpcore_lane(phy, params);
5697
5698 if ((params->loopback_mode) &&
5699 (phy->flags & FLAGS_WC_DUAL_MODE)) {
5700 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5701 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5702 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5703 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5704 link_up &= 0x1;
5705 } else if ((phy->req_line_speed > SPEED_10000) &&
5706 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5707 u16 temp_link_up;
5708 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5709 1, &temp_link_up);
5710 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5711 1, &link_up);
5712 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5713 temp_link_up, link_up);
5714 link_up &= (1<<2);
5715 if (link_up)
5716 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5717 } else {
5718 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5719 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5720 &gp_status1);
5721 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5722
5723 link_up = ((gp_status1 >> 8) |
5724 (gp_status1 >> 12) |
5725 (gp_status1)) &
5726 (1 << lane);
5727 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5728 u16 an_link;
5729 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5730 MDIO_AN_REG_STATUS, &an_link);
5731 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5732 MDIO_AN_REG_STATUS, &an_link);
5733 link_up |= (an_link & (1<<2));
5734 }
5735 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5736 u16 pd, gp_status4;
5737 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5738
5739 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5740 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5741 &gp_status4);
5742 if (gp_status4 & ((1<<12)<<lane))
5743 vars->link_status |=
5744 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5745
5746
5747 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5748 MDIO_WC_REG_PAR_DET_10G_STATUS,
5749 &pd);
5750 if (pd & (1<<15))
5751 vars->link_status |=
5752 LINK_STATUS_PARALLEL_DETECTION_USED;
5753 }
5754 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5755 vars->duplex = duplex;
5756 }
5757 }
5758
5759 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5760 SINGLE_MEDIA_DIRECT(params)) {
5761 u16 val;
5762
5763 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5764 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5765
5766 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5767 vars->link_status |=
5768 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5769 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5770 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5771 vars->link_status |=
5772 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5773
5774 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5775 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5776
5777 if (val & MDIO_OVER_1G_UP1_2_5G)
5778 vars->link_status |=
5779 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5780 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5781 vars->link_status |=
5782 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5783
5784 }
5785
5786
5787 if (lane < 2) {
5788 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5789 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5790 } else {
5791 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5792 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5793 }
5794 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5795
5796 if ((lane & 1) == 0)
5797 gp_speed <<= 8;
5798 gp_speed &= 0x3f00;
5799 link_up = !!link_up;
5800
5801 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5802 duplex);
5803
5804
5805 if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5806 (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5807 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5808
5809 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5810 vars->duplex, vars->flow_ctrl, vars->link_status);
5811 return rc;
5812 }
5813 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5814 {
5815 struct bnx2x *bp = params->bp;
5816 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
5817 u16 lp_up2;
5818 u16 tx_driver;
5819 u16 bank;
5820
5821
5822 CL22_RD_OVER_CL45(bp, phy,
5823 MDIO_REG_BANK_OVER_1G,
5824 MDIO_OVER_1G_LP_UP2, &lp_up2);
5825
5826
5827 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5828 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5829 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5830
5831 if (lp_up2 == 0)
5832 return;
5833
5834 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5835 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5836 CL22_RD_OVER_CL45(bp, phy,
5837 bank,
5838 MDIO_TX0_TX_DRIVER, &tx_driver);
5839
5840
5841 if (lp_up2 !=
5842 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5843 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5844 tx_driver |= lp_up2;
5845 CL22_WR_OVER_CL45(bp, phy,
5846 bank,
5847 MDIO_TX0_TX_DRIVER, tx_driver);
5848 }
5849 }
5850 }
5851
5852 static int bnx2x_emac_program(struct link_params *params,
5853 struct link_vars *vars)
5854 {
5855 struct bnx2x *bp = params->bp;
5856 u8 port = params->port;
5857 u16 mode = 0;
5858
5859 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5860 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5861 EMAC_REG_EMAC_MODE,
5862 (EMAC_MODE_25G_MODE |
5863 EMAC_MODE_PORT_MII_10M |
5864 EMAC_MODE_HALF_DUPLEX));
5865 switch (vars->line_speed) {
5866 case SPEED_10:
5867 mode |= EMAC_MODE_PORT_MII_10M;
5868 break;
5869
5870 case SPEED_100:
5871 mode |= EMAC_MODE_PORT_MII;
5872 break;
5873
5874 case SPEED_1000:
5875 mode |= EMAC_MODE_PORT_GMII;
5876 break;
5877
5878 case SPEED_2500:
5879 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5880 break;
5881
5882 default:
5883
5884 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5885 vars->line_speed);
5886 return -EINVAL;
5887 }
5888
5889 if (vars->duplex == DUPLEX_HALF)
5890 mode |= EMAC_MODE_HALF_DUPLEX;
5891 bnx2x_bits_en(bp,
5892 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5893 mode);
5894
5895 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5896 return 0;
5897 }
5898
5899 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5900 struct link_params *params)
5901 {
5902
5903 u16 bank, i = 0;
5904 struct bnx2x *bp = params->bp;
5905
5906 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5907 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5908 CL22_WR_OVER_CL45(bp, phy,
5909 bank,
5910 MDIO_RX0_RX_EQ_BOOST,
5911 phy->rx_preemphasis[i]);
5912 }
5913
5914 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5915 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5916 CL22_WR_OVER_CL45(bp, phy,
5917 bank,
5918 MDIO_TX0_TX_DRIVER,
5919 phy->tx_preemphasis[i]);
5920 }
5921 }
5922
5923 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5924 struct link_params *params,
5925 struct link_vars *vars)
5926 {
5927 struct bnx2x *bp = params->bp;
5928 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5929 (params->loopback_mode == LOOPBACK_XGXS));
5930 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5931 if (SINGLE_MEDIA_DIRECT(params) &&
5932 (params->feature_config_flags &
5933 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5934 bnx2x_set_preemphasis(phy, params);
5935
5936
5937 if (vars->line_speed != SPEED_AUTO_NEG ||
5938 (SINGLE_MEDIA_DIRECT(params) &&
5939 params->loopback_mode == LOOPBACK_EXT)) {
5940 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5941
5942
5943 bnx2x_set_autoneg(phy, params, vars, 0);
5944
5945
5946 bnx2x_program_serdes(phy, params, vars);
5947
5948 } else {
5949 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5950
5951
5952 bnx2x_set_brcm_cl37_advertisement(phy, params);
5953
5954
5955 bnx2x_set_ieee_aneg_advertisement(phy, params,
5956 vars->ieee_fc);
5957
5958
5959 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5960
5961
5962 bnx2x_restart_autoneg(phy, params, enable_cl73);
5963 }
5964
5965 } else {
5966 DP(NETIF_MSG_LINK, "SGMII\n");
5967
5968 bnx2x_initialize_sgmii_process(phy, params, vars);
5969 }
5970 }
5971
5972 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5973 struct link_params *params,
5974 struct link_vars *vars)
5975 {
5976 int rc;
5977 vars->phy_flags |= PHY_XGXS_FLAG;
5978 if ((phy->req_line_speed &&
5979 ((phy->req_line_speed == SPEED_100) ||
5980 (phy->req_line_speed == SPEED_10))) ||
5981 (!phy->req_line_speed &&
5982 (phy->speed_cap_mask >=
5983 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5984 (phy->speed_cap_mask <
5985 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5986 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5987 vars->phy_flags |= PHY_SGMII_FLAG;
5988 else
5989 vars->phy_flags &= ~PHY_SGMII_FLAG;
5990
5991 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5992 bnx2x_set_aer_mmd(params, phy);
5993 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5994 bnx2x_set_master_ln(params, phy);
5995
5996 rc = bnx2x_reset_unicore(params, phy, 0);
5997
5998 if (rc)
5999 return rc;
6000
6001 bnx2x_set_aer_mmd(params, phy);
6002
6003 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
6004 bnx2x_set_master_ln(params, phy);
6005 bnx2x_set_swap_lanes(params, phy);
6006 }
6007
6008 return rc;
6009 }
6010
6011 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
6012 struct bnx2x_phy *phy,
6013 struct link_params *params)
6014 {
6015 u16 cnt, ctrl;
6016
6017 for (cnt = 0; cnt < 1000; cnt++) {
6018 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6019 bnx2x_cl22_read(bp, phy,
6020 MDIO_PMA_REG_CTRL, &ctrl);
6021 else
6022 bnx2x_cl45_read(bp, phy,
6023 MDIO_PMA_DEVAD,
6024 MDIO_PMA_REG_CTRL, &ctrl);
6025 if (!(ctrl & (1<<15)))
6026 break;
6027 usleep_range(1000, 2000);
6028 }
6029
6030 if (cnt == 1000)
6031 netdev_err(bp->dev, "Warning: PHY was not initialized,"
6032 " Port %d\n",
6033 params->port);
6034 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6035 return cnt;
6036 }
6037
6038 static void bnx2x_link_int_enable(struct link_params *params)
6039 {
6040 u8 port = params->port;
6041 u32 mask;
6042 struct bnx2x *bp = params->bp;
6043
6044
6045 if (CHIP_IS_E3(bp)) {
6046 mask = NIG_MASK_XGXS0_LINK_STATUS;
6047 if (!(SINGLE_MEDIA_DIRECT(params)))
6048 mask |= NIG_MASK_MI_INT;
6049 } else if (params->switch_cfg == SWITCH_CFG_10G) {
6050 mask = (NIG_MASK_XGXS0_LINK10G |
6051 NIG_MASK_XGXS0_LINK_STATUS);
6052 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
6053 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6054 params->phy[INT_PHY].type !=
6055 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6056 mask |= NIG_MASK_MI_INT;
6057 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6058 }
6059
6060 } else {
6061 mask = NIG_MASK_SERDES0_LINK_STATUS;
6062 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6063 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6064 params->phy[INT_PHY].type !=
6065 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6066 mask |= NIG_MASK_MI_INT;
6067 DP(NETIF_MSG_LINK, "enabled external phy int\n");
6068 }
6069 }
6070 bnx2x_bits_en(bp,
6071 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6072 mask);
6073
6074 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6075 (params->switch_cfg == SWITCH_CFG_10G),
6076 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6077 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6078 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6079 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6080 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6081 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6082 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6083 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6084 }
6085
6086 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6087 u8 exp_mi_int)
6088 {
6089 u32 latch_status = 0;
6090
6091
6092
6093
6094
6095
6096 latch_status = REG_RD(bp,
6097 NIG_REG_LATCH_STATUS_0 + port*8);
6098 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6099
6100 if (exp_mi_int)
6101 bnx2x_bits_en(bp,
6102 NIG_REG_STATUS_INTERRUPT_PORT0
6103 + port*4,
6104 NIG_STATUS_EMAC0_MI_INT);
6105 else
6106 bnx2x_bits_dis(bp,
6107 NIG_REG_STATUS_INTERRUPT_PORT0
6108 + port*4,
6109 NIG_STATUS_EMAC0_MI_INT);
6110
6111 if (latch_status & 1) {
6112
6113
6114 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6115 (latch_status & 0xfffe) | (latch_status & 1));
6116 }
6117
6118 }
6119
6120 static void bnx2x_link_int_ack(struct link_params *params,
6121 struct link_vars *vars, u8 is_10g_plus)
6122 {
6123 struct bnx2x *bp = params->bp;
6124 u8 port = params->port;
6125 u32 mask;
6126
6127
6128
6129 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6130 (NIG_STATUS_XGXS0_LINK10G |
6131 NIG_STATUS_XGXS0_LINK_STATUS |
6132 NIG_STATUS_SERDES0_LINK_STATUS));
6133 if (vars->phy_link_up) {
6134 if (USES_WARPCORE(bp))
6135 mask = NIG_STATUS_XGXS0_LINK_STATUS;
6136 else {
6137 if (is_10g_plus)
6138 mask = NIG_STATUS_XGXS0_LINK10G;
6139 else if (params->switch_cfg == SWITCH_CFG_10G) {
6140
6141
6142
6143 u32 ser_lane =
6144 ((params->lane_config &
6145 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6146 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6147 mask = ((1 << ser_lane) <<
6148 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6149 } else
6150 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6151 }
6152 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6153 mask);
6154 bnx2x_bits_en(bp,
6155 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6156 mask);
6157 }
6158 }
6159
6160 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6161 {
6162 str[0] = '\0';
6163 (*len)--;
6164 return 0;
6165 }
6166
6167 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6168 {
6169 u16 ret;
6170
6171 if (*len < 10) {
6172
6173 bnx2x_null_format_ver(num, str, len);
6174 return -EINVAL;
6175 }
6176
6177 ret = scnprintf(str, *len, "%hx.%hx", num >> 16, num);
6178 *len -= ret;
6179 return 0;
6180 }
6181
6182 static int bnx2x_3_seq_format_ver(u32 num, u8 *str, u16 *len)
6183 {
6184 u16 ret;
6185
6186 if (*len < 10) {
6187
6188 bnx2x_null_format_ver(num, str, len);
6189 return -EINVAL;
6190 }
6191
6192 ret = scnprintf(str, *len, "%hhx.%hhx.%hhx", num >> 16, num >> 8, num);
6193 *len -= ret;
6194 return 0;
6195 }
6196
6197 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6198 u16 len)
6199 {
6200 struct bnx2x *bp;
6201 u32 spirom_ver = 0;
6202 int status = 0;
6203 u8 *ver_p = version;
6204 u16 remain_len = len;
6205 if (version == NULL || params == NULL)
6206 return -EINVAL;
6207 bp = params->bp;
6208
6209
6210 version[0] = '\0';
6211 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6212
6213 if (params->phy[EXT_PHY1].format_fw_ver) {
6214 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6215 ver_p,
6216 &remain_len);
6217 ver_p += (len - remain_len);
6218 }
6219 if ((params->num_phys == MAX_PHYS) &&
6220 (params->phy[EXT_PHY2].ver_addr != 0)) {
6221 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6222 if (params->phy[EXT_PHY2].format_fw_ver) {
6223 *ver_p = '/';
6224 ver_p++;
6225 remain_len--;
6226 status |= params->phy[EXT_PHY2].format_fw_ver(
6227 spirom_ver,
6228 ver_p,
6229 &remain_len);
6230 ver_p = version + (len - remain_len);
6231 }
6232 }
6233 *ver_p = '\0';
6234 return status;
6235 }
6236
6237 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6238 struct link_params *params)
6239 {
6240 u8 port = params->port;
6241 struct bnx2x *bp = params->bp;
6242
6243 if (phy->req_line_speed != SPEED_1000) {
6244 u32 md_devad = 0;
6245
6246 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6247
6248 if (!CHIP_IS_E3(bp)) {
6249
6250 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6251 port*0x18));
6252
6253 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6254 0x5);
6255 }
6256
6257 bnx2x_cl45_write(bp, phy,
6258 5,
6259 (MDIO_REG_BANK_AER_BLOCK +
6260 (MDIO_AER_BLOCK_AER_REG & 0xf)),
6261 0x2800);
6262
6263 bnx2x_cl45_write(bp, phy,
6264 5,
6265 (MDIO_REG_BANK_CL73_IEEEB0 +
6266 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6267 0x6041);
6268 msleep(200);
6269
6270 bnx2x_set_aer_mmd(params, phy);
6271
6272 if (!CHIP_IS_E3(bp)) {
6273
6274 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6275 md_devad);
6276 }
6277 } else {
6278 u16 mii_ctrl;
6279 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6280 bnx2x_cl45_read(bp, phy, 5,
6281 (MDIO_REG_BANK_COMBO_IEEE0 +
6282 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6283 &mii_ctrl);
6284 bnx2x_cl45_write(bp, phy, 5,
6285 (MDIO_REG_BANK_COMBO_IEEE0 +
6286 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6287 mii_ctrl |
6288 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6289 }
6290 }
6291
6292 int bnx2x_set_led(struct link_params *params,
6293 struct link_vars *vars, u8 mode, u32 speed)
6294 {
6295 u8 port = params->port;
6296 u16 hw_led_mode = params->hw_led_mode;
6297 int rc = 0;
6298 u8 phy_idx;
6299 u32 tmp;
6300 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6301 struct bnx2x *bp = params->bp;
6302 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6303 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6304 speed, hw_led_mode);
6305
6306 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6307 if (params->phy[phy_idx].set_link_led) {
6308 params->phy[phy_idx].set_link_led(
6309 ¶ms->phy[phy_idx], params, mode);
6310 }
6311 }
6312
6313 switch (mode) {
6314 case LED_MODE_FRONT_PANEL_OFF:
6315 case LED_MODE_OFF:
6316 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6317 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6318 SHARED_HW_CFG_LED_MAC1);
6319
6320 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6321 if (params->phy[EXT_PHY1].type ==
6322 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6323 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6324 EMAC_LED_100MB_OVERRIDE |
6325 EMAC_LED_10MB_OVERRIDE);
6326 else
6327 tmp |= EMAC_LED_OVERRIDE;
6328
6329 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6330 break;
6331
6332 case LED_MODE_OPER:
6333
6334
6335
6336 if (!vars->link_up)
6337 break;
6338
6339 case LED_MODE_ON:
6340 if (((params->phy[EXT_PHY1].type ==
6341 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6342 (params->phy[EXT_PHY1].type ==
6343 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6344 CHIP_IS_E2(bp) && params->num_phys == 2) {
6345
6346 if (mode == LED_MODE_ON ||
6347 speed == SPEED_10000){
6348 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6349 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6350
6351 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6352 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6353 (tmp | EMAC_LED_OVERRIDE));
6354
6355
6356
6357
6358
6359 if (mode == LED_MODE_ON)
6360 return rc;
6361 }
6362 } else if (SINGLE_MEDIA_DIRECT(params)) {
6363
6364
6365
6366 if ((!CHIP_IS_E3(bp)) ||
6367 (CHIP_IS_E3(bp) &&
6368 mode == LED_MODE_ON))
6369 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6370
6371 if (CHIP_IS_E1x(bp) ||
6372 CHIP_IS_E2(bp) ||
6373 (mode == LED_MODE_ON))
6374 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6375 else
6376 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6377 hw_led_mode);
6378 } else if ((params->phy[EXT_PHY1].type ==
6379 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6380 (mode == LED_MODE_ON)) {
6381 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6382 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6383 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6384 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6385
6386
6387
6388 break;
6389 } else {
6390 u32 nig_led_mode = ((params->hw_led_mode <<
6391 SHARED_HW_CFG_LED_MODE_SHIFT) ==
6392 SHARED_HW_CFG_LED_EXTPHY2) ?
6393 (SHARED_HW_CFG_LED_PHY1 >>
6394 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
6395 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6396 nig_led_mode);
6397 }
6398
6399 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6400
6401 if (CHIP_IS_E3(bp))
6402 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6403 LED_BLINK_RATE_VAL_E3);
6404 else
6405 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6406 LED_BLINK_RATE_VAL_E1X_E2);
6407 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6408 port*4, 1);
6409 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6410 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6411 (tmp & (~EMAC_LED_OVERRIDE)));
6412
6413 if (CHIP_IS_E1(bp) &&
6414 ((speed == SPEED_2500) ||
6415 (speed == SPEED_1000) ||
6416 (speed == SPEED_100) ||
6417 (speed == SPEED_10))) {
6418
6419 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6420 + port*4, 1);
6421 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6422 port*4, 0);
6423 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6424 port*4, 1);
6425 }
6426 break;
6427
6428 default:
6429 rc = -EINVAL;
6430 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6431 mode);
6432 break;
6433 }
6434 return rc;
6435
6436 }
6437
6438
6439
6440
6441 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6442 u8 is_serdes)
6443 {
6444 struct bnx2x *bp = params->bp;
6445 u16 gp_status = 0, phy_index = 0;
6446 u8 ext_phy_link_up = 0, serdes_phy_type;
6447 struct link_vars temp_vars;
6448 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
6449
6450 if (CHIP_IS_E3(bp)) {
6451 u16 link_up;
6452 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6453 > SPEED_10000) {
6454
6455 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6456 1, &link_up);
6457 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6458 1, &link_up);
6459 link_up &= (1<<2);
6460 } else {
6461
6462 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6463 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6464 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6465 &gp_status);
6466 gp_status = ((gp_status >> 8) & 0xf) |
6467 ((gp_status >> 12) & 0xf);
6468 link_up = gp_status & (1 << lane);
6469 }
6470 if (!link_up)
6471 return -ESRCH;
6472 } else {
6473 CL22_RD_OVER_CL45(bp, int_phy,
6474 MDIO_REG_BANK_GP_STATUS,
6475 MDIO_GP_STATUS_TOP_AN_STATUS1,
6476 &gp_status);
6477
6478 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6479 return -ESRCH;
6480 }
6481
6482 if (params->loopback_mode == LOOPBACK_XGXS)
6483 return 0;
6484
6485 switch (params->num_phys) {
6486 case 1:
6487
6488 return 0;
6489 case 2:
6490 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6491 ¶ms->phy[EXT_PHY1],
6492 params, &temp_vars);
6493 break;
6494 case 3:
6495 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6496 phy_index++) {
6497 serdes_phy_type = ((params->phy[phy_index].media_type ==
6498 ETH_PHY_SFPP_10G_FIBER) ||
6499 (params->phy[phy_index].media_type ==
6500 ETH_PHY_SFP_1G_FIBER) ||
6501 (params->phy[phy_index].media_type ==
6502 ETH_PHY_XFP_FIBER) ||
6503 (params->phy[phy_index].media_type ==
6504 ETH_PHY_DA_TWINAX));
6505
6506 if (is_serdes != serdes_phy_type)
6507 continue;
6508 if (params->phy[phy_index].read_status) {
6509 ext_phy_link_up |=
6510 params->phy[phy_index].read_status(
6511 ¶ms->phy[phy_index],
6512 params, &temp_vars);
6513 }
6514 }
6515 break;
6516 }
6517 if (ext_phy_link_up)
6518 return 0;
6519 return -ESRCH;
6520 }
6521
6522 static int bnx2x_link_initialize(struct link_params *params,
6523 struct link_vars *vars)
6524 {
6525 u8 phy_index, non_ext_phy;
6526 struct bnx2x *bp = params->bp;
6527
6528
6529
6530
6531
6532 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6533
6534
6535
6536
6537
6538 if (!USES_WARPCORE(bp))
6539 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars);
6540
6541 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6542 (params->loopback_mode == LOOPBACK_XGXS));
6543
6544 if (non_ext_phy ||
6545 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6546 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6547 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
6548 if (vars->line_speed == SPEED_AUTO_NEG &&
6549 (CHIP_IS_E1x(bp) ||
6550 CHIP_IS_E2(bp)))
6551 bnx2x_set_parallel_detection(phy, params);
6552 if (params->phy[INT_PHY].config_init)
6553 params->phy[INT_PHY].config_init(phy, params, vars);
6554 }
6555
6556
6557
6558
6559 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6560
6561
6562 if (non_ext_phy) {
6563 if (params->phy[INT_PHY].supported &
6564 SUPPORTED_FIBRE)
6565 vars->link_status |= LINK_STATUS_SERDES_LINK;
6566 } else {
6567 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6568 phy_index++) {
6569
6570
6571
6572
6573
6574 if (params->phy[phy_index].supported &
6575 SUPPORTED_FIBRE)
6576 vars->link_status |= LINK_STATUS_SERDES_LINK;
6577
6578 if (phy_index == EXT_PHY2 &&
6579 (bnx2x_phy_selection(params) ==
6580 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6581 DP(NETIF_MSG_LINK,
6582 "Not initializing second phy\n");
6583 continue;
6584 }
6585 params->phy[phy_index].config_init(
6586 ¶ms->phy[phy_index],
6587 params, vars);
6588 }
6589 }
6590
6591 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6592 params->port*4,
6593 (NIG_STATUS_XGXS0_LINK10G |
6594 NIG_STATUS_XGXS0_LINK_STATUS |
6595 NIG_STATUS_SERDES0_LINK_STATUS |
6596 NIG_MASK_MI_INT));
6597 return 0;
6598 }
6599
6600 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6601 struct link_params *params)
6602 {
6603
6604 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6605 (0x1ff << (params->port*16)));
6606 }
6607
6608 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6609 struct link_params *params)
6610 {
6611 struct bnx2x *bp = params->bp;
6612 u8 gpio_port;
6613
6614 if (CHIP_IS_E2(bp))
6615 gpio_port = BP_PATH(bp);
6616 else
6617 gpio_port = params->port;
6618 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6619 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6620 gpio_port);
6621 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6622 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6623 gpio_port);
6624 DP(NETIF_MSG_LINK, "reset external PHY\n");
6625 }
6626
6627 static int bnx2x_update_link_down(struct link_params *params,
6628 struct link_vars *vars)
6629 {
6630 struct bnx2x *bp = params->bp;
6631 u8 port = params->port;
6632
6633 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6634 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6635 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6636
6637 vars->mac_type = MAC_TYPE_NONE;
6638
6639
6640 vars->link_status &= ~LINK_UPDATE_MASK;
6641 vars->line_speed = 0;
6642 bnx2x_update_mng(params, vars->link_status);
6643
6644
6645 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6646
6647
6648 if (!CHIP_IS_E3(bp))
6649 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6650
6651 usleep_range(10000, 20000);
6652
6653 if (CHIP_IS_E1x(bp) ||
6654 CHIP_IS_E2(bp))
6655 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6656
6657 if (CHIP_IS_E3(bp)) {
6658
6659 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6660 0);
6661 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6662 0);
6663 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6664 SHMEM_EEE_ACTIVE_BIT);
6665
6666 bnx2x_update_mng_eee(params, vars->eee_status);
6667 bnx2x_set_xmac_rxtx(params, 0);
6668 bnx2x_set_umac_rxtx(params, 0);
6669 }
6670
6671 return 0;
6672 }
6673
6674 static int bnx2x_update_link_up(struct link_params *params,
6675 struct link_vars *vars,
6676 u8 link_10g)
6677 {
6678 struct bnx2x *bp = params->bp;
6679 u8 phy_idx, port = params->port;
6680 int rc = 0;
6681
6682 vars->link_status |= (LINK_STATUS_LINK_UP |
6683 LINK_STATUS_PHYSICAL_LINK_FLAG);
6684 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6685
6686 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6687 vars->link_status |=
6688 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6689
6690 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6691 vars->link_status |=
6692 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6693 if (USES_WARPCORE(bp)) {
6694 if (link_10g) {
6695 if (bnx2x_xmac_enable(params, vars, 0) ==
6696 -ESRCH) {
6697 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6698 vars->link_up = 0;
6699 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6700 vars->link_status &= ~LINK_STATUS_LINK_UP;
6701 }
6702 } else
6703 bnx2x_umac_enable(params, vars, 0);
6704 bnx2x_set_led(params, vars,
6705 LED_MODE_OPER, vars->line_speed);
6706
6707 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6708 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6709 DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6710 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6711 (params->port << 2), 1);
6712 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6713 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6714 (params->port << 2), 0xfc20);
6715 }
6716 }
6717 if ((CHIP_IS_E1x(bp) ||
6718 CHIP_IS_E2(bp))) {
6719 if (link_10g) {
6720 if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6721 -ESRCH) {
6722 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6723 vars->link_up = 0;
6724 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6725 vars->link_status &= ~LINK_STATUS_LINK_UP;
6726 }
6727
6728 bnx2x_set_led(params, vars,
6729 LED_MODE_OPER, SPEED_10000);
6730 } else {
6731 rc = bnx2x_emac_program(params, vars);
6732 bnx2x_emac_enable(params, vars, 0);
6733
6734
6735 if ((vars->link_status &
6736 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6737 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6738 SINGLE_MEDIA_DIRECT(params))
6739 bnx2x_set_gmii_tx_driver(params);
6740 }
6741 }
6742
6743
6744 if (CHIP_IS_E1x(bp))
6745 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6746 vars->line_speed);
6747
6748
6749 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6750
6751
6752 bnx2x_update_mng(params, vars->link_status);
6753 bnx2x_update_mng_eee(params, vars->eee_status);
6754
6755 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6756 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6757 bnx2x_check_half_open_conn(params, vars, 0);
6758 break;
6759 }
6760 }
6761 msleep(20);
6762 return rc;
6763 }
6764
6765 static void bnx2x_chng_link_count(struct link_params *params, bool clear)
6766 {
6767 struct bnx2x *bp = params->bp;
6768 u32 addr, val;
6769
6770
6771 if (!(SHMEM2_HAS(bp, link_change_count)))
6772 return;
6773
6774 addr = params->shmem2_base +
6775 offsetof(struct shmem2_region, link_change_count[params->port]);
6776 if (clear)
6777 val = 0;
6778 else
6779 val = REG_RD(bp, addr) + 1;
6780 REG_WR(bp, addr, val);
6781 }
6782
6783
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793
6794
6795 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6796 {
6797 struct bnx2x *bp = params->bp;
6798 struct link_vars phy_vars[MAX_PHYS];
6799 u8 port = params->port;
6800 u8 link_10g_plus, phy_index;
6801 u32 prev_link_status = vars->link_status;
6802 u8 ext_phy_link_up = 0, cur_link_up;
6803 int rc = 0;
6804 u8 is_mi_int = 0;
6805 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6806 u8 active_external_phy = INT_PHY;
6807 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6808 vars->link_status &= ~LINK_UPDATE_MASK;
6809 for (phy_index = INT_PHY; phy_index < params->num_phys;
6810 phy_index++) {
6811 phy_vars[phy_index].flow_ctrl = 0;
6812 phy_vars[phy_index].link_status = 0;
6813 phy_vars[phy_index].line_speed = 0;
6814 phy_vars[phy_index].duplex = DUPLEX_FULL;
6815 phy_vars[phy_index].phy_link_up = 0;
6816 phy_vars[phy_index].link_up = 0;
6817 phy_vars[phy_index].fault_detected = 0;
6818
6819 phy_vars[phy_index].eee_status = vars->eee_status;
6820 }
6821
6822 if (USES_WARPCORE(bp))
6823 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]);
6824
6825 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6826 port, (vars->phy_flags & PHY_XGXS_FLAG),
6827 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6828
6829 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6830 port*0x18) > 0);
6831 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6832 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6833 is_mi_int,
6834 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6835
6836 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6837 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6838 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6839
6840
6841 if (!CHIP_IS_E3(bp))
6842 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6843
6844
6845
6846
6847
6848
6849
6850
6851 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6852 phy_index++) {
6853 struct bnx2x_phy *phy = ¶ms->phy[phy_index];
6854 if (!phy->read_status)
6855 continue;
6856
6857 cur_link_up = phy->read_status(phy, params,
6858 &phy_vars[phy_index]);
6859 if (cur_link_up) {
6860 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6861 phy_index);
6862 } else {
6863 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6864 phy_index);
6865 continue;
6866 }
6867
6868 if (!ext_phy_link_up) {
6869 ext_phy_link_up = 1;
6870 active_external_phy = phy_index;
6871 } else {
6872 switch (bnx2x_phy_selection(params)) {
6873 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6874 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6875
6876
6877
6878
6879 active_external_phy = EXT_PHY1;
6880 break;
6881 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6882
6883
6884
6885 active_external_phy = EXT_PHY2;
6886 break;
6887 default:
6888
6889
6890
6891
6892
6893
6894
6895
6896 DP(NETIF_MSG_LINK, "Invalid link indication"
6897 "mpc=0x%x. DISABLING LINK !!!\n",
6898 params->multi_phy_config);
6899 ext_phy_link_up = 0;
6900 break;
6901 }
6902 }
6903 }
6904 prev_line_speed = vars->line_speed;
6905
6906
6907
6908
6909
6910
6911 if (params->phy[INT_PHY].read_status)
6912 params->phy[INT_PHY].read_status(
6913 ¶ms->phy[INT_PHY],
6914 params, vars);
6915
6916
6917
6918
6919
6920
6921
6922 if (active_external_phy > INT_PHY) {
6923 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6924
6925
6926
6927 vars->link_status |= phy_vars[active_external_phy].link_status;
6928
6929
6930
6931
6932 if (active_external_phy == EXT_PHY1) {
6933 if (params->phy[EXT_PHY2].phy_specific_func) {
6934 DP(NETIF_MSG_LINK,
6935 "Disabling TX on EXT_PHY2\n");
6936 params->phy[EXT_PHY2].phy_specific_func(
6937 ¶ms->phy[EXT_PHY2],
6938 params, DISABLE_TX);
6939 }
6940 }
6941
6942 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6943 vars->duplex = phy_vars[active_external_phy].duplex;
6944 if (params->phy[active_external_phy].supported &
6945 SUPPORTED_FIBRE)
6946 vars->link_status |= LINK_STATUS_SERDES_LINK;
6947 else
6948 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6949
6950 vars->eee_status = phy_vars[active_external_phy].eee_status;
6951
6952 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6953 active_external_phy);
6954 }
6955
6956 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6957 phy_index++) {
6958 if (params->phy[phy_index].flags &
6959 FLAGS_REARM_LATCH_SIGNAL) {
6960 bnx2x_rearm_latch_signal(bp, port,
6961 phy_index ==
6962 active_external_phy);
6963 break;
6964 }
6965 }
6966 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6967 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6968 vars->link_status, ext_phy_line_speed);
6969
6970
6971
6972
6973
6974 if (vars->phy_link_up) {
6975 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6976 (ext_phy_line_speed != vars->line_speed)) {
6977 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6978 " different than the external"
6979 " link speed %d\n", vars->line_speed,
6980 ext_phy_line_speed);
6981 vars->phy_link_up = 0;
6982 } else if (prev_line_speed != vars->line_speed) {
6983 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6984 0);
6985 usleep_range(1000, 2000);
6986 }
6987 }
6988
6989
6990 link_10g_plus = (vars->line_speed >= SPEED_10000);
6991
6992 bnx2x_link_int_ack(params, vars, link_10g_plus);
6993
6994
6995
6996
6997
6998
6999
7000
7001 if (!(SINGLE_MEDIA_DIRECT(params))) {
7002 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
7003 " init_preceding = %d\n", ext_phy_link_up,
7004 vars->phy_link_up,
7005 params->phy[EXT_PHY1].flags &
7006 FLAGS_INIT_XGXS_FIRST);
7007 if (!(params->phy[EXT_PHY1].flags &
7008 FLAGS_INIT_XGXS_FIRST)
7009 && ext_phy_link_up && !vars->phy_link_up) {
7010 vars->line_speed = ext_phy_line_speed;
7011 if (vars->line_speed < SPEED_1000)
7012 vars->phy_flags |= PHY_SGMII_FLAG;
7013 else
7014 vars->phy_flags &= ~PHY_SGMII_FLAG;
7015
7016 if (params->phy[INT_PHY].config_init)
7017 params->phy[INT_PHY].config_init(
7018 ¶ms->phy[INT_PHY], params,
7019 vars);
7020 }
7021 }
7022
7023
7024
7025 vars->link_up = (vars->phy_link_up &&
7026 (ext_phy_link_up ||
7027 SINGLE_MEDIA_DIRECT(params)) &&
7028 (phy_vars[active_external_phy].fault_detected == 0));
7029
7030
7031 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
7032 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7033 else
7034 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7035
7036 if (vars->link_up)
7037 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
7038 else
7039 rc = bnx2x_update_link_down(params, vars);
7040
7041 if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)
7042 bnx2x_chng_link_count(params, false);
7043
7044
7045 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7046 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7047
7048 return rc;
7049 }
7050
7051
7052
7053
7054 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
7055 {
7056 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7057 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7058 usleep_range(1000, 2000);
7059 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7060 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7061 }
7062
7063 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
7064 u32 spirom_ver, u32 ver_addr)
7065 {
7066 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
7067 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
7068
7069 if (ver_addr)
7070 REG_WR(bp, ver_addr, spirom_ver);
7071 }
7072
7073 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7074 struct bnx2x_phy *phy,
7075 u8 port)
7076 {
7077 u16 fw_ver1, fw_ver2;
7078
7079 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7080 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7081 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7082 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7083 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7084 phy->ver_addr);
7085 }
7086
7087 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7088 struct bnx2x_phy *phy,
7089 struct link_vars *vars)
7090 {
7091 u16 val;
7092 bnx2x_cl45_read(bp, phy,
7093 MDIO_AN_DEVAD,
7094 MDIO_AN_REG_STATUS, &val);
7095 bnx2x_cl45_read(bp, phy,
7096 MDIO_AN_DEVAD,
7097 MDIO_AN_REG_STATUS, &val);
7098 if (val & (1<<5))
7099 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7100 if ((val & (1<<0)) == 0)
7101 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7102 }
7103
7104
7105
7106
7107 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7108 struct link_params *params,
7109 struct link_vars *vars)
7110 {
7111 struct bnx2x *bp = params->bp;
7112 if (phy->req_line_speed == SPEED_10 ||
7113 phy->req_line_speed == SPEED_100) {
7114 vars->flow_ctrl = phy->req_flow_ctrl;
7115 return;
7116 }
7117
7118 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7119 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7120 u16 pause_result;
7121 u16 ld_pause;
7122 u16 lp_pause;
7123 bnx2x_cl45_read(bp, phy,
7124 MDIO_AN_DEVAD,
7125 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7126
7127 bnx2x_cl45_read(bp, phy,
7128 MDIO_AN_DEVAD,
7129 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7130 pause_result = (ld_pause &
7131 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7132 pause_result |= (lp_pause &
7133 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7134
7135 bnx2x_pause_resolve(phy, params, vars, pause_result);
7136 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7137 pause_result);
7138 }
7139 }
7140 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7141 struct bnx2x_phy *phy,
7142 u8 port)
7143 {
7144 u32 count = 0;
7145 u16 fw_ver1, fw_msgout;
7146 int rc = 0;
7147
7148
7149
7150 bnx2x_cl45_write(bp, phy,
7151 MDIO_PMA_DEVAD,
7152 MDIO_PMA_REG_GEN_CTRL,
7153 0x0001);
7154
7155
7156 bnx2x_cl45_write(bp, phy,
7157 MDIO_PMA_DEVAD,
7158 MDIO_PMA_REG_GEN_CTRL,
7159 0x008c);
7160
7161 bnx2x_cl45_write(bp, phy,
7162 MDIO_PMA_DEVAD,
7163 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7164
7165
7166 bnx2x_cl45_write(bp, phy,
7167 MDIO_PMA_DEVAD,
7168 MDIO_PMA_REG_GEN_CTRL,
7169 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7170
7171
7172 bnx2x_cl45_write(bp, phy,
7173 MDIO_PMA_DEVAD,
7174 MDIO_PMA_REG_GEN_CTRL,
7175 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7176
7177
7178 msleep(100);
7179
7180
7181 do {
7182 count++;
7183 if (count > 300) {
7184 DP(NETIF_MSG_LINK,
7185 "bnx2x_8073_8727_external_rom_boot port %x:"
7186 "Download failed. fw version = 0x%x\n",
7187 port, fw_ver1);
7188 rc = -EINVAL;
7189 break;
7190 }
7191
7192 bnx2x_cl45_read(bp, phy,
7193 MDIO_PMA_DEVAD,
7194 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7195 bnx2x_cl45_read(bp, phy,
7196 MDIO_PMA_DEVAD,
7197 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7198
7199 usleep_range(1000, 2000);
7200 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7201 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7202 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7203
7204
7205 bnx2x_cl45_write(bp, phy,
7206 MDIO_PMA_DEVAD,
7207 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7208 bnx2x_save_bcm_spirom_ver(bp, phy, port);
7209
7210 DP(NETIF_MSG_LINK,
7211 "bnx2x_8073_8727_external_rom_boot port %x:"
7212 "Download complete. fw version = 0x%x\n",
7213 port, fw_ver1);
7214
7215 return rc;
7216 }
7217
7218
7219
7220
7221 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7222 {
7223
7224 u16 val;
7225
7226
7227 bnx2x_cl45_read(bp, phy,
7228 MDIO_PMA_DEVAD,
7229 MDIO_PMA_REG_8073_CHIP_REV, &val);
7230
7231 if (val != 1) {
7232
7233 return 0;
7234 }
7235
7236 bnx2x_cl45_read(bp, phy,
7237 MDIO_PMA_DEVAD,
7238 MDIO_PMA_REG_ROM_VER2, &val);
7239
7240
7241 if (val != 0x102)
7242 return 0;
7243
7244 return 1;
7245 }
7246
7247 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7248 {
7249 u16 val, cnt, cnt1 ;
7250
7251 bnx2x_cl45_read(bp, phy,
7252 MDIO_PMA_DEVAD,
7253 MDIO_PMA_REG_8073_CHIP_REV, &val);
7254
7255 if (val > 0) {
7256
7257 return 0;
7258 }
7259
7260
7261
7262
7263
7264
7265 for (cnt = 0; cnt < 1000; cnt++) {
7266 bnx2x_cl45_read(bp, phy,
7267 MDIO_PMA_DEVAD,
7268 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7269 &val);
7270
7271
7272
7273
7274 if (!(val & (1<<14)) || !(val & (1<<13))) {
7275 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7276 return 0;
7277 } else if (!(val & (1<<15))) {
7278 DP(NETIF_MSG_LINK, "bit 15 went off\n");
7279
7280
7281
7282
7283
7284 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7285 bnx2x_cl45_read(bp, phy,
7286 MDIO_PMA_DEVAD,
7287 MDIO_PMA_REG_8073_XAUI_WA, &val);
7288 if (val & (1<<15)) {
7289 DP(NETIF_MSG_LINK,
7290 "XAUI workaround has completed\n");
7291 return 0;
7292 }
7293 usleep_range(3000, 6000);
7294 }
7295 break;
7296 }
7297 usleep_range(3000, 6000);
7298 }
7299 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7300 return -EINVAL;
7301 }
7302
7303 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7304 {
7305
7306 bnx2x_cl45_write(bp, phy,
7307 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7308 bnx2x_cl45_write(bp, phy,
7309 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7310 bnx2x_cl45_write(bp, phy,
7311 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7312 bnx2x_cl45_write(bp, phy,
7313 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7314 }
7315
7316 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7317 struct bnx2x_phy *phy,
7318 struct link_vars *vars)
7319 {
7320 u16 cl37_val;
7321 struct bnx2x *bp = params->bp;
7322 bnx2x_cl45_read(bp, phy,
7323 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7324
7325 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7326
7327 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7328 if ((vars->ieee_fc &
7329 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7330 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7331 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7332 }
7333 if ((vars->ieee_fc &
7334 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7335 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7336 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7337 }
7338 if ((vars->ieee_fc &
7339 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7340 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7341 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7342 }
7343 DP(NETIF_MSG_LINK,
7344 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7345
7346 bnx2x_cl45_write(bp, phy,
7347 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7348 msleep(500);
7349 }
7350
7351 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7352 struct link_params *params,
7353 u32 action)
7354 {
7355 struct bnx2x *bp = params->bp;
7356 switch (action) {
7357 case PHY_INIT:
7358
7359 bnx2x_cl45_write(bp, phy,
7360 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7361 bnx2x_cl45_write(bp, phy,
7362 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
7363 break;
7364 }
7365 }
7366
7367 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7368 struct link_params *params,
7369 struct link_vars *vars)
7370 {
7371 struct bnx2x *bp = params->bp;
7372 u16 val = 0, tmp1;
7373 u8 gpio_port;
7374 DP(NETIF_MSG_LINK, "Init 8073\n");
7375
7376 if (CHIP_IS_E2(bp))
7377 gpio_port = BP_PATH(bp);
7378 else
7379 gpio_port = params->port;
7380
7381 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7382 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7383
7384 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7385 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7386
7387 bnx2x_8073_specific_func(phy, params, PHY_INIT);
7388 bnx2x_8073_set_pause_cl37(params, phy, vars);
7389
7390 bnx2x_cl45_read(bp, phy,
7391 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7392
7393 bnx2x_cl45_read(bp, phy,
7394 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7395
7396 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7397
7398
7399 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7400
7401 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7402
7403 bnx2x_cl45_read(bp, phy,
7404 MDIO_PMA_DEVAD,
7405 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7406 bnx2x_cl45_write(bp, phy,
7407 MDIO_PMA_DEVAD,
7408 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7409 (val | (3<<9)));
7410 }
7411
7412
7413
7414 if (REG_RD(bp, params->shmem_base +
7415 offsetof(struct shmem_region, dev_info.
7416 port_hw_config[params->port].default_cfg)) &
7417 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7418
7419 bnx2x_cl45_read(bp, phy,
7420 MDIO_AN_DEVAD,
7421 MDIO_AN_REG_8073_BAM, &val);
7422 bnx2x_cl45_write(bp, phy,
7423 MDIO_AN_DEVAD,
7424 MDIO_AN_REG_8073_BAM, val | 1);
7425 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7426 }
7427 if (params->loopback_mode == LOOPBACK_EXT) {
7428 bnx2x_807x_force_10G(bp, phy);
7429 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7430 return 0;
7431 } else {
7432 bnx2x_cl45_write(bp, phy,
7433 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7434 }
7435 if (phy->req_line_speed != SPEED_AUTO_NEG) {
7436 if (phy->req_line_speed == SPEED_10000) {
7437 val = (1<<7);
7438 } else if (phy->req_line_speed == SPEED_2500) {
7439 val = (1<<5);
7440
7441
7442
7443 } else
7444 val = (1<<5);
7445 } else {
7446 val = 0;
7447 if (phy->speed_cap_mask &
7448 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7449 val |= (1<<7);
7450
7451
7452 if (phy->speed_cap_mask &
7453 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7454 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7455 val |= (1<<5);
7456 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7457 }
7458
7459 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7460 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7461
7462 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7463 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7464 (phy->req_line_speed == SPEED_2500)) {
7465 u16 phy_ver;
7466
7467 bnx2x_cl45_read(bp, phy,
7468 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7469 &phy_ver);
7470 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7471 if (phy_ver > 0)
7472 tmp1 |= 1;
7473 else
7474 tmp1 &= 0xfffe;
7475 } else {
7476 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7477 tmp1 &= 0xfffe;
7478 }
7479
7480 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7481
7482
7483 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7484 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7485 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7486 0x20 : 0x40)));
7487
7488
7489 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7490
7491
7492
7493
7494
7495 if (bnx2x_8073_is_snr_needed(bp, phy))
7496 bnx2x_cl45_write(bp, phy,
7497 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7498 0xFB0C);
7499
7500
7501 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7502 tmp1 |= (1<<15);
7503 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7504
7505 bnx2x_ext_phy_set_pause(params, phy, vars);
7506
7507
7508 msleep(500);
7509 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7510 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7511 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7512 return 0;
7513 }
7514
7515 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7516 struct link_params *params,
7517 struct link_vars *vars)
7518 {
7519 struct bnx2x *bp = params->bp;
7520 u8 link_up = 0;
7521 u16 val1, val2;
7522 u16 link_status = 0;
7523 u16 an1000_status = 0;
7524
7525 bnx2x_cl45_read(bp, phy,
7526 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7527
7528 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7529
7530
7531 bnx2x_cl45_read(bp, phy,
7532 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7533 bnx2x_cl45_read(bp, phy,
7534 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7535 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7536
7537 bnx2x_cl45_read(bp, phy,
7538 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7539
7540
7541 bnx2x_cl45_read(bp, phy,
7542 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7543
7544 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7545
7546
7547 bnx2x_cl45_read(bp, phy,
7548 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7549 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7550
7551 bnx2x_cl45_read(bp, phy,
7552 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7553 bnx2x_cl45_read(bp, phy,
7554 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7555 link_up = ((val1 & 4) == 4);
7556 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7557
7558 if (link_up &&
7559 ((phy->req_line_speed != SPEED_10000))) {
7560 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7561 return 0;
7562 }
7563 bnx2x_cl45_read(bp, phy,
7564 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7565 bnx2x_cl45_read(bp, phy,
7566 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7567
7568
7569 bnx2x_cl45_read(bp, phy,
7570 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7571 bnx2x_cl45_read(bp, phy,
7572 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7573 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7574 "an_link_status=0x%x\n", val2, val1, an1000_status);
7575
7576 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7577 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7578
7579
7580
7581
7582 bnx2x_cl45_write(bp, phy,
7583 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7584 0x26BC);
7585
7586
7587 bnx2x_cl45_write(bp, phy,
7588 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7589 0x0333);
7590 }
7591 bnx2x_cl45_read(bp, phy,
7592 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7593 &link_status);
7594
7595
7596 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7597 link_up = 1;
7598 vars->line_speed = SPEED_10000;
7599 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7600 params->port);
7601 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7602 link_up = 1;
7603 vars->line_speed = SPEED_2500;
7604 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7605 params->port);
7606 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7607 link_up = 1;
7608 vars->line_speed = SPEED_1000;
7609 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7610 params->port);
7611 } else {
7612 link_up = 0;
7613 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7614 params->port);
7615 }
7616
7617 if (link_up) {
7618
7619 if (params->lane_config &
7620 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7621
7622 bnx2x_cl45_read(bp, phy,
7623 MDIO_XS_DEVAD,
7624 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7625
7626
7627
7628 if (vars->line_speed == SPEED_1000) {
7629 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7630 "the 8073\n");
7631 val1 |= (1<<3);
7632 } else
7633 val1 &= ~(1<<3);
7634
7635 bnx2x_cl45_write(bp, phy,
7636 MDIO_XS_DEVAD,
7637 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7638 val1);
7639 }
7640 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7641 bnx2x_8073_resolve_fc(phy, params, vars);
7642 vars->duplex = DUPLEX_FULL;
7643 }
7644
7645 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7646 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7647 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7648
7649 if (val1 & (1<<5))
7650 vars->link_status |=
7651 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7652 if (val1 & (1<<7))
7653 vars->link_status |=
7654 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7655 }
7656
7657 return link_up;
7658 }
7659
7660 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7661 struct link_params *params)
7662 {
7663 struct bnx2x *bp = params->bp;
7664 u8 gpio_port;
7665 if (CHIP_IS_E2(bp))
7666 gpio_port = BP_PATH(bp);
7667 else
7668 gpio_port = params->port;
7669 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7670 gpio_port);
7671 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7672 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7673 gpio_port);
7674 }
7675
7676
7677
7678
7679 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7680 struct link_params *params,
7681 struct link_vars *vars)
7682 {
7683 struct bnx2x *bp = params->bp;
7684 DP(NETIF_MSG_LINK, "init 8705\n");
7685
7686 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7687 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7688
7689 bnx2x_ext_phy_hw_reset(bp, params->port);
7690 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7691 bnx2x_wait_reset_complete(bp, phy, params);
7692
7693 bnx2x_cl45_write(bp, phy,
7694 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7695 bnx2x_cl45_write(bp, phy,
7696 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7697 bnx2x_cl45_write(bp, phy,
7698 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7699 bnx2x_cl45_write(bp, phy,
7700 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7701
7702 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7703 return 0;
7704 }
7705
7706 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7707 struct link_params *params,
7708 struct link_vars *vars)
7709 {
7710 u8 link_up = 0;
7711 u16 val1, rx_sd;
7712 struct bnx2x *bp = params->bp;
7713 DP(NETIF_MSG_LINK, "read status 8705\n");
7714 bnx2x_cl45_read(bp, phy,
7715 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7716 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7717
7718 bnx2x_cl45_read(bp, phy,
7719 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7720 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7721
7722 bnx2x_cl45_read(bp, phy,
7723 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7724
7725 bnx2x_cl45_read(bp, phy,
7726 MDIO_PMA_DEVAD, 0xc809, &val1);
7727 bnx2x_cl45_read(bp, phy,
7728 MDIO_PMA_DEVAD, 0xc809, &val1);
7729
7730 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7731 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7732 if (link_up) {
7733 vars->line_speed = SPEED_10000;
7734 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7735 }
7736 return link_up;
7737 }
7738
7739
7740
7741
7742 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7743 struct bnx2x_phy *phy,
7744 u8 pmd_dis)
7745 {
7746 struct bnx2x *bp = params->bp;
7747
7748
7749
7750 if (pmd_dis) {
7751 if (params->feature_config_flags &
7752 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7753 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7754 else {
7755 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7756 return;
7757 }
7758 } else
7759 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7760 bnx2x_cl45_write(bp, phy,
7761 MDIO_PMA_DEVAD,
7762 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7763 }
7764
7765 static u8 bnx2x_get_gpio_port(struct link_params *params)
7766 {
7767 u8 gpio_port;
7768 u32 swap_val, swap_override;
7769 struct bnx2x *bp = params->bp;
7770 if (CHIP_IS_E2(bp))
7771 gpio_port = BP_PATH(bp);
7772 else
7773 gpio_port = params->port;
7774 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7775 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7776 return gpio_port ^ (swap_val && swap_override);
7777 }
7778
7779 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7780 struct bnx2x_phy *phy,
7781 u8 tx_en)
7782 {
7783 u16 val;
7784 u8 port = params->port;
7785 struct bnx2x *bp = params->bp;
7786 u32 tx_en_mode;
7787
7788
7789 tx_en_mode = REG_RD(bp, params->shmem_base +
7790 offsetof(struct shmem_region,
7791 dev_info.port_hw_config[port].sfp_ctrl)) &
7792 PORT_HW_CFG_TX_LASER_MASK;
7793 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7794 "mode = %x\n", tx_en, port, tx_en_mode);
7795 switch (tx_en_mode) {
7796 case PORT_HW_CFG_TX_LASER_MDIO:
7797
7798 bnx2x_cl45_read(bp, phy,
7799 MDIO_PMA_DEVAD,
7800 MDIO_PMA_REG_PHY_IDENTIFIER,
7801 &val);
7802
7803 if (tx_en)
7804 val &= ~(1<<15);
7805 else
7806 val |= (1<<15);
7807
7808 bnx2x_cl45_write(bp, phy,
7809 MDIO_PMA_DEVAD,
7810 MDIO_PMA_REG_PHY_IDENTIFIER,
7811 val);
7812 break;
7813 case PORT_HW_CFG_TX_LASER_GPIO0:
7814 case PORT_HW_CFG_TX_LASER_GPIO1:
7815 case PORT_HW_CFG_TX_LASER_GPIO2:
7816 case PORT_HW_CFG_TX_LASER_GPIO3:
7817 {
7818 u16 gpio_pin;
7819 u8 gpio_port, gpio_mode;
7820 if (tx_en)
7821 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7822 else
7823 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7824
7825 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7826 gpio_port = bnx2x_get_gpio_port(params);
7827 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7828 break;
7829 }
7830 default:
7831 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7832 break;
7833 }
7834 }
7835
7836 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7837 struct bnx2x_phy *phy,
7838 u8 tx_en)
7839 {
7840 struct bnx2x *bp = params->bp;
7841 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7842 if (CHIP_IS_E3(bp))
7843 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7844 else
7845 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7846 }
7847
7848 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7849 struct link_params *params,
7850 u8 dev_addr, u16 addr, u8 byte_cnt,
7851 u8 *o_buf, u8 is_init)
7852 {
7853 struct bnx2x *bp = params->bp;
7854 u16 val = 0;
7855 u16 i;
7856 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7857 DP(NETIF_MSG_LINK,
7858 "Reading from eeprom is limited to 0xf\n");
7859 return -EINVAL;
7860 }
7861
7862 bnx2x_cl45_write(bp, phy,
7863 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7864 (byte_cnt | (dev_addr << 8)));
7865
7866
7867 bnx2x_cl45_write(bp, phy,
7868 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7869 addr);
7870
7871
7872 bnx2x_cl45_write(bp, phy,
7873 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7874 0x2c0f);
7875
7876
7877 for (i = 0; i < 100; i++) {
7878 bnx2x_cl45_read(bp, phy,
7879 MDIO_PMA_DEVAD,
7880 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7881 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7882 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7883 break;
7884 udelay(5);
7885 }
7886
7887 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7888 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7889 DP(NETIF_MSG_LINK,
7890 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7891 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7892 return -EINVAL;
7893 }
7894
7895
7896 for (i = 0; i < byte_cnt; i++) {
7897 bnx2x_cl45_read(bp, phy,
7898 MDIO_PMA_DEVAD,
7899 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7900 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7901 }
7902
7903 for (i = 0; i < 100; i++) {
7904 bnx2x_cl45_read(bp, phy,
7905 MDIO_PMA_DEVAD,
7906 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7907 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7908 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7909 return 0;
7910 usleep_range(1000, 2000);
7911 }
7912 return -EINVAL;
7913 }
7914
7915 static void bnx2x_warpcore_power_module(struct link_params *params,
7916 u8 power)
7917 {
7918 u32 pin_cfg;
7919 struct bnx2x *bp = params->bp;
7920
7921 pin_cfg = (REG_RD(bp, params->shmem_base +
7922 offsetof(struct shmem_region,
7923 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7924 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7925 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7926
7927 if (pin_cfg == PIN_CFG_NA)
7928 return;
7929 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7930 power, pin_cfg);
7931
7932
7933
7934 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7935 }
7936 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7937 struct link_params *params,
7938 u8 dev_addr,
7939 u16 addr, u8 byte_cnt,
7940 u8 *o_buf, u8 is_init)
7941 {
7942 int rc = 0;
7943 u8 i, j = 0, cnt = 0;
7944 u32 data_array[4];
7945 u16 addr32;
7946 struct bnx2x *bp = params->bp;
7947
7948 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7949 DP(NETIF_MSG_LINK,
7950 "Reading from eeprom is limited to 16 bytes\n");
7951 return -EINVAL;
7952 }
7953
7954
7955 addr32 = addr & (~0x3);
7956 do {
7957 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7958 bnx2x_warpcore_power_module(params, 0);
7959
7960 usleep_range(1000, 2000);
7961 bnx2x_warpcore_power_module(params, 1);
7962 }
7963 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt,
7964 data_array);
7965 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7966
7967 if (rc == 0) {
7968 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7969 o_buf[j] = *((u8 *)data_array + i);
7970 j++;
7971 }
7972 }
7973
7974 return rc;
7975 }
7976
7977 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7978 struct link_params *params,
7979 u8 dev_addr, u16 addr, u8 byte_cnt,
7980 u8 *o_buf, u8 is_init)
7981 {
7982 struct bnx2x *bp = params->bp;
7983 u16 val, i;
7984
7985 if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7986 DP(NETIF_MSG_LINK,
7987 "Reading from eeprom is limited to 0xf\n");
7988 return -EINVAL;
7989 }
7990
7991
7992
7993
7994
7995 bnx2x_cl45_write(bp, phy,
7996 MDIO_PMA_DEVAD,
7997 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7998 ((dev_addr << 8) | 1));
7999
8000
8001 bnx2x_cl45_read(bp, phy,
8002 MDIO_PMA_DEVAD,
8003 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8004 &val);
8005
8006
8007 bnx2x_cl45_write(bp, phy,
8008 MDIO_PMA_DEVAD,
8009 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8010 ((byte_cnt < 2) ? 2 : byte_cnt));
8011
8012
8013 bnx2x_cl45_write(bp, phy,
8014 MDIO_PMA_DEVAD,
8015 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8016 addr);
8017
8018 bnx2x_cl45_write(bp, phy,
8019 MDIO_PMA_DEVAD,
8020 0x8004,
8021 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
8022
8023
8024 bnx2x_cl45_write(bp, phy,
8025 MDIO_PMA_DEVAD,
8026 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8027 0x8002);
8028
8029
8030
8031 usleep_range(1000, 2000);
8032
8033
8034 for (i = 0; i < 100; i++) {
8035 bnx2x_cl45_read(bp, phy,
8036 MDIO_PMA_DEVAD,
8037 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8038 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8039 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8040 break;
8041 udelay(5);
8042 }
8043
8044 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8045 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8046 DP(NETIF_MSG_LINK,
8047 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8048 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8049 return -EFAULT;
8050 }
8051
8052
8053 for (i = 0; i < byte_cnt; i++) {
8054 bnx2x_cl45_read(bp, phy,
8055 MDIO_PMA_DEVAD,
8056 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8057 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8058 }
8059
8060 for (i = 0; i < 100; i++) {
8061 bnx2x_cl45_read(bp, phy,
8062 MDIO_PMA_DEVAD,
8063 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8064 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8065 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8066 return 0;
8067 usleep_range(1000, 2000);
8068 }
8069
8070 return -EINVAL;
8071 }
8072 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8073 struct link_params *params, u8 dev_addr,
8074 u16 addr, u16 byte_cnt, u8 *o_buf)
8075 {
8076 int rc = 0;
8077 struct bnx2x *bp = params->bp;
8078 u8 xfer_size;
8079 u8 *user_data = o_buf;
8080 read_sfp_module_eeprom_func_p read_func;
8081
8082 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8083 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8084 return -EINVAL;
8085 }
8086
8087 switch (phy->type) {
8088 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8089 read_func = bnx2x_8726_read_sfp_module_eeprom;
8090 break;
8091 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8092 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8093 read_func = bnx2x_8727_read_sfp_module_eeprom;
8094 break;
8095 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8096 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8097 break;
8098 default:
8099 return -EOPNOTSUPP;
8100 }
8101
8102 while (!rc && (byte_cnt > 0)) {
8103 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8104 SFP_EEPROM_PAGE_SIZE : byte_cnt;
8105 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8106 user_data, 0);
8107 byte_cnt -= xfer_size;
8108 user_data += xfer_size;
8109 addr += xfer_size;
8110 }
8111 return rc;
8112 }
8113
8114 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8115 struct link_params *params,
8116 u16 *edc_mode)
8117 {
8118 struct bnx2x *bp = params->bp;
8119 u32 sync_offset = 0, phy_idx, media_types;
8120 u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0;
8121 *edc_mode = EDC_MODE_LIMITING;
8122 phy->media_type = ETH_PHY_UNSPECIFIED;
8123
8124 if (bnx2x_read_sfp_module_eeprom(phy,
8125 params,
8126 I2C_DEV_ADDR_A0,
8127 0,
8128 SFP_EEPROM_FC_TX_TECH_ADDR + 1,
8129 (u8 *)val) != 0) {
8130 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8131 return -EINVAL;
8132 }
8133 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;
8134 params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] <<
8135 LINK_SFP_EEPROM_COMP_CODE_SHIFT;
8136 bnx2x_update_link_attr(params, params->link_attr_sync);
8137 switch (val[SFP_EEPROM_CON_TYPE_ADDR]) {
8138 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8139 {
8140 u8 copper_module_type;
8141 phy->media_type = ETH_PHY_DA_TWINAX;
8142
8143
8144
8145 copper_module_type = val[SFP_EEPROM_FC_TX_TECH_ADDR];
8146
8147 if (copper_module_type &
8148 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8149 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8150 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8151 *edc_mode = EDC_MODE_ACTIVE_DAC;
8152 else
8153 check_limiting_mode = 1;
8154 } else {
8155 *edc_mode = EDC_MODE_PASSIVE_DAC;
8156
8157
8158
8159
8160 if (copper_module_type &
8161 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8162 DP(NETIF_MSG_LINK,
8163 "Passive Copper cable detected\n");
8164 } else {
8165 DP(NETIF_MSG_LINK,
8166 "Unknown copper-cable-type\n");
8167 }
8168 }
8169 break;
8170 }
8171 case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
8172 case SFP_EEPROM_CON_TYPE_VAL_LC:
8173 case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8174 check_limiting_mode = 1;
8175 if (((val[SFP_EEPROM_10G_COMP_CODE_ADDR] &
8176 (SFP_EEPROM_10G_COMP_CODE_SR_MASK |
8177 SFP_EEPROM_10G_COMP_CODE_LR_MASK |
8178 SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) &&
8179 (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
8180 DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8181 phy->media_type = ETH_PHY_SFP_1G_FIBER;
8182 if (phy->req_line_speed != SPEED_1000) {
8183 u8 gport = params->port;
8184 phy->req_line_speed = SPEED_1000;
8185 if (!CHIP_IS_E1x(bp)) {
8186 gport = BP_PATH(bp) +
8187 (params->port << 1);
8188 }
8189 netdev_err(bp->dev,
8190 "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8191 gport);
8192 }
8193 if (val[SFP_EEPROM_1G_COMP_CODE_ADDR] &
8194 SFP_EEPROM_1G_COMP_CODE_BASE_T) {
8195 bnx2x_sfp_set_transmitter(params, phy, 0);
8196 msleep(40);
8197 bnx2x_sfp_set_transmitter(params, phy, 1);
8198 }
8199 } else {
8200 int idx, cfg_idx = 0;
8201 DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8202 for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8203 if (params->phy[idx].type == phy->type) {
8204 cfg_idx = LINK_CONFIG_IDX(idx);
8205 break;
8206 }
8207 }
8208 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8209 phy->req_line_speed = params->req_line_speed[cfg_idx];
8210 }
8211 break;
8212 default:
8213 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8214 val[SFP_EEPROM_CON_TYPE_ADDR]);
8215 return -EINVAL;
8216 }
8217 sync_offset = params->shmem_base +
8218 offsetof(struct shmem_region,
8219 dev_info.port_hw_config[params->port].media_type);
8220 media_types = REG_RD(bp, sync_offset);
8221
8222 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8223 if (&(params->phy[phy_idx]) == phy) {
8224 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8225 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8226 media_types |= ((phy->media_type &
8227 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8228 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8229 break;
8230 }
8231 }
8232 REG_WR(bp, sync_offset, media_types);
8233 if (check_limiting_mode) {
8234 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8235 if (bnx2x_read_sfp_module_eeprom(phy,
8236 params,
8237 I2C_DEV_ADDR_A0,
8238 SFP_EEPROM_OPTIONS_ADDR,
8239 SFP_EEPROM_OPTIONS_SIZE,
8240 options) != 0) {
8241 DP(NETIF_MSG_LINK,
8242 "Failed to read Option field from module EEPROM\n");
8243 return -EINVAL;
8244 }
8245 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8246 *edc_mode = EDC_MODE_LINEAR;
8247 else
8248 *edc_mode = EDC_MODE_LIMITING;
8249 }
8250 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8251 return 0;
8252 }
8253
8254
8255
8256 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8257 struct link_params *params)
8258 {
8259 struct bnx2x *bp = params->bp;
8260 u32 val, cmd;
8261 u32 fw_resp, fw_cmd_param;
8262 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8263 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8264 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8265 val = REG_RD(bp, params->shmem_base +
8266 offsetof(struct shmem_region, dev_info.
8267 port_feature_config[params->port].config));
8268 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8269 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8270 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8271 return 0;
8272 }
8273
8274 if (params->feature_config_flags &
8275 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8276
8277 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8278 } else if (params->feature_config_flags &
8279 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8280
8281 if (DUAL_MEDIA(params)) {
8282 DP(NETIF_MSG_LINK,
8283 "FW does not support OPT MDL verification\n");
8284 return -EINVAL;
8285 }
8286 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8287 } else {
8288
8289 DP(NETIF_MSG_LINK,
8290 "FW does not support OPT MDL verification\n");
8291 return -EINVAL;
8292 }
8293
8294 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8295 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8296 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8297 DP(NETIF_MSG_LINK, "Approved module\n");
8298 return 0;
8299 }
8300
8301
8302 if (bnx2x_read_sfp_module_eeprom(phy,
8303 params,
8304 I2C_DEV_ADDR_A0,
8305 SFP_EEPROM_VENDOR_NAME_ADDR,
8306 SFP_EEPROM_VENDOR_NAME_SIZE,
8307 (u8 *)vendor_name))
8308 vendor_name[0] = '\0';
8309 else
8310 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8311 if (bnx2x_read_sfp_module_eeprom(phy,
8312 params,
8313 I2C_DEV_ADDR_A0,
8314 SFP_EEPROM_PART_NO_ADDR,
8315 SFP_EEPROM_PART_NO_SIZE,
8316 (u8 *)vendor_pn))
8317 vendor_pn[0] = '\0';
8318 else
8319 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8320
8321 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
8322 " Port %d from %s part number %s\n",
8323 params->port, vendor_name, vendor_pn);
8324 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8325 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8326 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8327 return -EINVAL;
8328 }
8329
8330 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8331 struct link_params *params)
8332
8333 {
8334 u8 val;
8335 int rc;
8336 struct bnx2x *bp = params->bp;
8337 u16 timeout;
8338
8339
8340
8341
8342 for (timeout = 0; timeout < 60; timeout++) {
8343 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8344 rc = bnx2x_warpcore_read_sfp_module_eeprom(
8345 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8346 1);
8347 else
8348 rc = bnx2x_read_sfp_module_eeprom(phy, params,
8349 I2C_DEV_ADDR_A0,
8350 1, 1, &val);
8351 if (rc == 0) {
8352 DP(NETIF_MSG_LINK,
8353 "SFP+ module initialization took %d ms\n",
8354 timeout * 5);
8355 return 0;
8356 }
8357 usleep_range(5000, 10000);
8358 }
8359 rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8360 1, 1, &val);
8361 return rc;
8362 }
8363
8364 static void bnx2x_8727_power_module(struct bnx2x *bp,
8365 struct bnx2x_phy *phy,
8366 u8 is_power_up) {
8367
8368 u16 val;
8369
8370
8371
8372
8373
8374
8375
8376
8377
8378
8379
8380 if (phy->flags & FLAGS_NOC)
8381 return;
8382 if (is_power_up)
8383 val = (1<<4);
8384 else
8385
8386
8387
8388 val = (1<<1);
8389
8390 bnx2x_cl45_write(bp, phy,
8391 MDIO_PMA_DEVAD,
8392 MDIO_PMA_REG_8727_GPIO_CTRL,
8393 val);
8394 }
8395
8396 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8397 struct bnx2x_phy *phy,
8398 u16 edc_mode)
8399 {
8400 u16 cur_limiting_mode;
8401
8402 bnx2x_cl45_read(bp, phy,
8403 MDIO_PMA_DEVAD,
8404 MDIO_PMA_REG_ROM_VER2,
8405 &cur_limiting_mode);
8406 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8407 cur_limiting_mode);
8408
8409 if (edc_mode == EDC_MODE_LIMITING) {
8410 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8411 bnx2x_cl45_write(bp, phy,
8412 MDIO_PMA_DEVAD,
8413 MDIO_PMA_REG_ROM_VER2,
8414 EDC_MODE_LIMITING);
8415 } else {
8416
8417 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8418
8419
8420
8421
8422 if (cur_limiting_mode != EDC_MODE_LIMITING)
8423 return 0;
8424
8425 bnx2x_cl45_write(bp, phy,
8426 MDIO_PMA_DEVAD,
8427 MDIO_PMA_REG_LRM_MODE,
8428 0);
8429 bnx2x_cl45_write(bp, phy,
8430 MDIO_PMA_DEVAD,
8431 MDIO_PMA_REG_ROM_VER2,
8432 0x128);
8433 bnx2x_cl45_write(bp, phy,
8434 MDIO_PMA_DEVAD,
8435 MDIO_PMA_REG_MISC_CTRL0,
8436 0x4008);
8437 bnx2x_cl45_write(bp, phy,
8438 MDIO_PMA_DEVAD,
8439 MDIO_PMA_REG_LRM_MODE,
8440 0xaaaa);
8441 }
8442 return 0;
8443 }
8444
8445 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8446 struct bnx2x_phy *phy,
8447 u16 edc_mode)
8448 {
8449 u16 phy_identifier;
8450 u16 rom_ver2_val;
8451 bnx2x_cl45_read(bp, phy,
8452 MDIO_PMA_DEVAD,
8453 MDIO_PMA_REG_PHY_IDENTIFIER,
8454 &phy_identifier);
8455
8456 bnx2x_cl45_write(bp, phy,
8457 MDIO_PMA_DEVAD,
8458 MDIO_PMA_REG_PHY_IDENTIFIER,
8459 (phy_identifier & ~(1<<9)));
8460
8461 bnx2x_cl45_read(bp, phy,
8462 MDIO_PMA_DEVAD,
8463 MDIO_PMA_REG_ROM_VER2,
8464 &rom_ver2_val);
8465
8466 bnx2x_cl45_write(bp, phy,
8467 MDIO_PMA_DEVAD,
8468 MDIO_PMA_REG_ROM_VER2,
8469 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8470
8471 bnx2x_cl45_write(bp, phy,
8472 MDIO_PMA_DEVAD,
8473 MDIO_PMA_REG_PHY_IDENTIFIER,
8474 (phy_identifier | (1<<9)));
8475
8476 return 0;
8477 }
8478
8479 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8480 struct link_params *params,
8481 u32 action)
8482 {
8483 struct bnx2x *bp = params->bp;
8484 u16 val;
8485 switch (action) {
8486 case DISABLE_TX:
8487 bnx2x_sfp_set_transmitter(params, phy, 0);
8488 break;
8489 case ENABLE_TX:
8490 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8491 bnx2x_sfp_set_transmitter(params, phy, 1);
8492 break;
8493 case PHY_INIT:
8494 bnx2x_cl45_write(bp, phy,
8495 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8496 (1<<2) | (1<<5));
8497 bnx2x_cl45_write(bp, phy,
8498 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8499 0);
8500 bnx2x_cl45_write(bp, phy,
8501 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8502
8503 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8504 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8505 &val);
8506 val |= (1<<12);
8507 if (phy->flags & FLAGS_NOC)
8508 val |= (3<<5);
8509
8510
8511
8512 if (!(phy->flags & FLAGS_NOC))
8513 val &= 0xff8f;
8514 bnx2x_cl45_write(bp, phy,
8515 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8516 val);
8517 break;
8518 default:
8519 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8520 action);
8521 return;
8522 }
8523 }
8524
8525 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8526 u8 gpio_mode)
8527 {
8528 struct bnx2x *bp = params->bp;
8529
8530 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8531 offsetof(struct shmem_region,
8532 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8533 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8534 switch (fault_led_gpio) {
8535 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8536 return;
8537 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8538 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8539 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8540 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8541 {
8542 u8 gpio_port = bnx2x_get_gpio_port(params);
8543 u16 gpio_pin = fault_led_gpio -
8544 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8545 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8546 "pin %x port %x mode %x\n",
8547 gpio_pin, gpio_port, gpio_mode);
8548 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8549 }
8550 break;
8551 default:
8552 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8553 fault_led_gpio);
8554 }
8555 }
8556
8557 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8558 u8 gpio_mode)
8559 {
8560 u32 pin_cfg;
8561 u8 port = params->port;
8562 struct bnx2x *bp = params->bp;
8563 pin_cfg = (REG_RD(bp, params->shmem_base +
8564 offsetof(struct shmem_region,
8565 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8566 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8567 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8568 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8569 gpio_mode, pin_cfg);
8570 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8571 }
8572
8573 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8574 u8 gpio_mode)
8575 {
8576 struct bnx2x *bp = params->bp;
8577 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8578 if (CHIP_IS_E3(bp)) {
8579
8580
8581
8582 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8583 } else
8584 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8585 }
8586
8587 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8588 struct link_params *params)
8589 {
8590 struct bnx2x *bp = params->bp;
8591 bnx2x_warpcore_power_module(params, 0);
8592
8593 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8594
8595
8596 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8597 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8598 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8599 }
8600
8601 static void bnx2x_power_sfp_module(struct link_params *params,
8602 struct bnx2x_phy *phy,
8603 u8 power)
8604 {
8605 struct bnx2x *bp = params->bp;
8606 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8607
8608 switch (phy->type) {
8609 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8610 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8611 bnx2x_8727_power_module(params->bp, phy, power);
8612 break;
8613 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8614 bnx2x_warpcore_power_module(params, power);
8615 break;
8616 default:
8617 break;
8618 }
8619 }
8620 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8621 struct bnx2x_phy *phy,
8622 u16 edc_mode)
8623 {
8624 u16 val = 0;
8625 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8626 struct bnx2x *bp = params->bp;
8627
8628 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8629
8630 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8631 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8632 val &= ~(0xf << (lane << 2));
8633
8634 switch (edc_mode) {
8635 case EDC_MODE_LINEAR:
8636 case EDC_MODE_LIMITING:
8637 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8638 break;
8639 case EDC_MODE_PASSIVE_DAC:
8640 case EDC_MODE_ACTIVE_DAC:
8641 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8642 break;
8643 default:
8644 break;
8645 }
8646
8647 val |= (mode << (lane << 2));
8648 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8649 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8650
8651 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8652 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8653
8654
8655 bnx2x_warpcore_reset_lane(bp, phy, 1);
8656 bnx2x_warpcore_reset_lane(bp, phy, 0);
8657
8658 }
8659
8660 static void bnx2x_set_limiting_mode(struct link_params *params,
8661 struct bnx2x_phy *phy,
8662 u16 edc_mode)
8663 {
8664 switch (phy->type) {
8665 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8666 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8667 break;
8668 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8669 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8670 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8671 break;
8672 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8673 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8674 break;
8675 }
8676 }
8677
8678 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8679 struct link_params *params)
8680 {
8681 struct bnx2x *bp = params->bp;
8682 u16 edc_mode;
8683 int rc = 0;
8684
8685 u32 val = REG_RD(bp, params->shmem_base +
8686 offsetof(struct shmem_region, dev_info.
8687 port_feature_config[params->port].config));
8688
8689 bnx2x_sfp_set_transmitter(params, phy, 1);
8690 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8691 params->port);
8692
8693 bnx2x_power_sfp_module(params, phy, 1);
8694 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8695 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8696 return -EINVAL;
8697 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8698
8699 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8700 rc = -EINVAL;
8701
8702 bnx2x_set_sfp_module_fault_led(params,
8703 MISC_REGISTERS_GPIO_HIGH);
8704
8705
8706 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8707 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8708 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8709 bnx2x_power_sfp_module(params, phy, 0);
8710 return rc;
8711 }
8712 } else {
8713
8714 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8715 }
8716
8717
8718
8719
8720 bnx2x_set_limiting_mode(params, phy, edc_mode);
8721
8722
8723
8724
8725 if ((rc) &&
8726 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8727 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8728 bnx2x_sfp_set_transmitter(params, phy, 0);
8729
8730 return rc;
8731 }
8732
8733 void bnx2x_handle_module_detect_int(struct link_params *params)
8734 {
8735 struct bnx2x *bp = params->bp;
8736 struct bnx2x_phy *phy;
8737 u32 gpio_val;
8738 u8 gpio_num, gpio_port;
8739 if (CHIP_IS_E3(bp)) {
8740 phy = ¶ms->phy[INT_PHY];
8741
8742 bnx2x_sfp_set_transmitter(params, phy, 1);
8743 } else {
8744 phy = ¶ms->phy[EXT_PHY1];
8745 }
8746 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8747 params->port, &gpio_num, &gpio_port) ==
8748 -EINVAL) {
8749 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8750 return;
8751 }
8752
8753
8754 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8755
8756
8757 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8758
8759
8760 if (gpio_val == 0) {
8761 bnx2x_set_mdio_emac_per_phy(bp, params);
8762 bnx2x_set_aer_mmd(params, phy);
8763
8764 bnx2x_power_sfp_module(params, phy, 1);
8765 bnx2x_set_gpio_int(bp, gpio_num,
8766 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8767 gpio_port);
8768 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8769 bnx2x_sfp_module_detection(phy, params);
8770 if (CHIP_IS_E3(bp)) {
8771 u16 rx_tx_in_reset;
8772
8773
8774
8775
8776 bnx2x_cl45_read(bp, phy,
8777 MDIO_WC_DEVAD,
8778 MDIO_WC_REG_DIGITAL5_MISC6,
8779 &rx_tx_in_reset);
8780 if ((!rx_tx_in_reset) &&
8781 (params->link_flags &
8782 PHY_INITIALIZED)) {
8783 bnx2x_warpcore_reset_lane(bp, phy, 1);
8784 bnx2x_warpcore_config_sfi(phy, params);
8785 bnx2x_warpcore_reset_lane(bp, phy, 0);
8786 }
8787 }
8788 } else {
8789 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8790 }
8791 } else {
8792 bnx2x_set_gpio_int(bp, gpio_num,
8793 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8794 gpio_port);
8795
8796
8797
8798 phy->media_type = ETH_PHY_NOT_PRESENT;
8799 }
8800 }
8801
8802
8803
8804
8805 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8806 struct bnx2x_phy *phy,
8807 u16 alarm_status_offset,
8808 u16 alarm_ctrl_offset)
8809 {
8810 u16 alarm_status, val;
8811 bnx2x_cl45_read(bp, phy,
8812 MDIO_PMA_DEVAD, alarm_status_offset,
8813 &alarm_status);
8814 bnx2x_cl45_read(bp, phy,
8815 MDIO_PMA_DEVAD, alarm_status_offset,
8816 &alarm_status);
8817
8818 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8819 if (alarm_status & (1<<0))
8820 val &= ~(1<<0);
8821 else
8822 val |= (1<<0);
8823 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8824 }
8825
8826
8827
8828 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8829 struct link_params *params,
8830 struct link_vars *vars)
8831 {
8832 u8 link_up = 0;
8833 u16 val1, val2, rx_sd, pcs_status;
8834 struct bnx2x *bp = params->bp;
8835 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8836
8837 bnx2x_cl45_read(bp, phy,
8838 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8839
8840 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8841 MDIO_PMA_LASI_TXCTRL);
8842
8843
8844 bnx2x_cl45_read(bp, phy,
8845 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8846 bnx2x_cl45_read(bp, phy,
8847 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8848 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8849
8850 bnx2x_cl45_read(bp, phy,
8851 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8852 bnx2x_cl45_read(bp, phy,
8853 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8854 bnx2x_cl45_read(bp, phy,
8855 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8856 bnx2x_cl45_read(bp, phy,
8857 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8858
8859 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8860 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8861
8862
8863
8864 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8865 if (link_up) {
8866 if (val2 & (1<<1))
8867 vars->line_speed = SPEED_1000;
8868 else
8869 vars->line_speed = SPEED_10000;
8870 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8871 vars->duplex = DUPLEX_FULL;
8872 }
8873
8874
8875 if (vars->line_speed == SPEED_10000) {
8876 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8877 MDIO_PMA_LASI_TXSTAT, &val1);
8878 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8879 MDIO_PMA_LASI_TXSTAT, &val1);
8880 if (val1 & (1<<0))
8881 vars->fault_detected = 1;
8882 }
8883
8884 return link_up;
8885 }
8886
8887
8888
8889
8890 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8891 struct link_params *params,
8892 struct link_vars *vars)
8893 {
8894 u32 tx_en_mode;
8895 u16 cnt, val, tmp1;
8896 struct bnx2x *bp = params->bp;
8897
8898 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8899 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8900
8901 bnx2x_ext_phy_hw_reset(bp, params->port);
8902 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8903 bnx2x_wait_reset_complete(bp, phy, params);
8904
8905
8906 for (cnt = 0; cnt < 100; cnt++) {
8907 bnx2x_cl45_read(bp, phy,
8908 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8909 if (val)
8910 break;
8911 usleep_range(10000, 20000);
8912 }
8913 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8914 if ((params->feature_config_flags &
8915 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8916 u8 i;
8917 u16 reg;
8918 for (i = 0; i < 4; i++) {
8919 reg = MDIO_XS_8706_REG_BANK_RX0 +
8920 i*(MDIO_XS_8706_REG_BANK_RX1 -
8921 MDIO_XS_8706_REG_BANK_RX0);
8922 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8923
8924 val &= ~0x7;
8925
8926 val |= (phy->rx_preemphasis[i] & 0x7);
8927 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8928 " reg 0x%x <-- val 0x%x\n", reg, val);
8929 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8930 }
8931 }
8932
8933 if (phy->req_line_speed == SPEED_10000) {
8934 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8935
8936 bnx2x_cl45_write(bp, phy,
8937 MDIO_PMA_DEVAD,
8938 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8939 bnx2x_cl45_write(bp, phy,
8940 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8941 0);
8942
8943 bnx2x_cl45_write(bp, phy,
8944 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8945 } else {
8946
8947
8948
8949 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8950 bnx2x_cl45_write(bp, phy,
8951 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8952
8953
8954 bnx2x_cl45_write(bp, phy,
8955 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8956
8957 bnx2x_cl45_write(bp, phy,
8958 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8959
8960 bnx2x_cl45_write(bp, phy,
8961 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8962
8963
8964 bnx2x_cl45_write(bp, phy,
8965 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8966 bnx2x_cl45_write(bp, phy,
8967 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8968 0x0400);
8969 bnx2x_cl45_write(bp, phy,
8970 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8971 0x0004);
8972 }
8973 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8974
8975
8976
8977
8978
8979 tx_en_mode = REG_RD(bp, params->shmem_base +
8980 offsetof(struct shmem_region,
8981 dev_info.port_hw_config[params->port].sfp_ctrl))
8982 & PORT_HW_CFG_TX_LASER_MASK;
8983
8984 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8985 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8986 bnx2x_cl45_read(bp, phy,
8987 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8988 tmp1 |= 0x1;
8989 bnx2x_cl45_write(bp, phy,
8990 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8991 }
8992
8993 return 0;
8994 }
8995
8996 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8997 struct link_params *params,
8998 struct link_vars *vars)
8999 {
9000 return bnx2x_8706_8726_read_status(phy, params, vars);
9001 }
9002
9003
9004
9005
9006 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
9007 struct link_params *params)
9008 {
9009 struct bnx2x *bp = params->bp;
9010 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
9011 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9012 }
9013
9014 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
9015 struct link_params *params)
9016 {
9017 struct bnx2x *bp = params->bp;
9018
9019 msleep(100);
9020
9021
9022 bnx2x_cl45_write(bp, phy,
9023 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
9024
9025
9026 bnx2x_cl45_write(bp, phy,
9027 MDIO_PMA_DEVAD,
9028 MDIO_PMA_REG_GEN_CTRL,
9029 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
9030
9031 bnx2x_cl45_write(bp, phy,
9032 MDIO_PMA_DEVAD,
9033 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
9034
9035 bnx2x_cl45_write(bp, phy,
9036 MDIO_PMA_DEVAD,
9037 MDIO_PMA_REG_GEN_CTRL,
9038 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
9039
9040
9041 msleep(150);
9042
9043
9044 bnx2x_cl45_write(bp, phy,
9045 MDIO_PMA_DEVAD,
9046 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9047
9048 msleep(200);
9049 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
9050 }
9051
9052 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
9053 struct link_params *params,
9054 struct link_vars *vars)
9055 {
9056 struct bnx2x *bp = params->bp;
9057 u16 val1;
9058 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
9059 if (link_up) {
9060 bnx2x_cl45_read(bp, phy,
9061 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9062 &val1);
9063 if (val1 & (1<<15)) {
9064 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9065 link_up = 0;
9066 vars->line_speed = 0;
9067 }
9068 }
9069 return link_up;
9070 }
9071
9072
9073 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
9074 struct link_params *params,
9075 struct link_vars *vars)
9076 {
9077 struct bnx2x *bp = params->bp;
9078 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
9079
9080 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9081 bnx2x_wait_reset_complete(bp, phy, params);
9082
9083 bnx2x_8726_external_rom_boot(phy, params);
9084
9085
9086
9087
9088
9089
9090 bnx2x_sfp_module_detection(phy, params);
9091
9092 if (phy->req_line_speed == SPEED_1000) {
9093 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9094 bnx2x_cl45_write(bp, phy,
9095 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9096 bnx2x_cl45_write(bp, phy,
9097 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9098 bnx2x_cl45_write(bp, phy,
9099 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9100 bnx2x_cl45_write(bp, phy,
9101 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9102 0x400);
9103 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9104 (phy->speed_cap_mask &
9105 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9106 ((phy->speed_cap_mask &
9107 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9108 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9109 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9110
9111 bnx2x_ext_phy_set_pause(params, phy, vars);
9112 bnx2x_cl45_write(bp, phy,
9113 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9114 bnx2x_cl45_write(bp, phy,
9115 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9116 bnx2x_cl45_write(bp, phy,
9117 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9118 bnx2x_cl45_write(bp, phy,
9119 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9120 bnx2x_cl45_write(bp, phy,
9121 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9122
9123
9124
9125 bnx2x_cl45_write(bp, phy,
9126 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9127 bnx2x_cl45_write(bp, phy,
9128 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9129 0x400);
9130
9131 } else {
9132 bnx2x_cl45_write(bp, phy,
9133 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9134 }
9135
9136
9137 if ((params->feature_config_flags &
9138 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9139 DP(NETIF_MSG_LINK,
9140 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9141 phy->tx_preemphasis[0],
9142 phy->tx_preemphasis[1]);
9143 bnx2x_cl45_write(bp, phy,
9144 MDIO_PMA_DEVAD,
9145 MDIO_PMA_REG_8726_TX_CTRL1,
9146 phy->tx_preemphasis[0]);
9147
9148 bnx2x_cl45_write(bp, phy,
9149 MDIO_PMA_DEVAD,
9150 MDIO_PMA_REG_8726_TX_CTRL2,
9151 phy->tx_preemphasis[1]);
9152 }
9153
9154 return 0;
9155
9156 }
9157
9158 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9159 struct link_params *params)
9160 {
9161 struct bnx2x *bp = params->bp;
9162 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9163
9164 bnx2x_cl45_write(bp, phy,
9165 MDIO_PMA_DEVAD,
9166 MDIO_PMA_REG_GEN_CTRL, 0x0001);
9167 }
9168
9169
9170
9171
9172
9173 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9174 struct link_params *params, u8 mode)
9175 {
9176 struct bnx2x *bp = params->bp;
9177 u16 led_mode_bitmask = 0;
9178 u16 gpio_pins_bitmask = 0;
9179 u16 val;
9180
9181 if (!(phy->flags & FLAGS_NOC))
9182 return;
9183 switch (mode) {
9184 case LED_MODE_FRONT_PANEL_OFF:
9185 case LED_MODE_OFF:
9186 led_mode_bitmask = 0;
9187 gpio_pins_bitmask = 0x03;
9188 break;
9189 case LED_MODE_ON:
9190 led_mode_bitmask = 0;
9191 gpio_pins_bitmask = 0x02;
9192 break;
9193 case LED_MODE_OPER:
9194 led_mode_bitmask = 0x60;
9195 gpio_pins_bitmask = 0x11;
9196 break;
9197 }
9198 bnx2x_cl45_read(bp, phy,
9199 MDIO_PMA_DEVAD,
9200 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9201 &val);
9202 val &= 0xff8f;
9203 val |= led_mode_bitmask;
9204 bnx2x_cl45_write(bp, phy,
9205 MDIO_PMA_DEVAD,
9206 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9207 val);
9208 bnx2x_cl45_read(bp, phy,
9209 MDIO_PMA_DEVAD,
9210 MDIO_PMA_REG_8727_GPIO_CTRL,
9211 &val);
9212 val &= 0xffe0;
9213 val |= gpio_pins_bitmask;
9214 bnx2x_cl45_write(bp, phy,
9215 MDIO_PMA_DEVAD,
9216 MDIO_PMA_REG_8727_GPIO_CTRL,
9217 val);
9218 }
9219 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9220 struct link_params *params) {
9221 u32 swap_val, swap_override;
9222 u8 port;
9223
9224
9225
9226 struct bnx2x *bp = params->bp;
9227 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9228 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9229 port = (swap_val && swap_override) ^ 1;
9230 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9231 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9232 }
9233
9234 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9235 struct link_params *params)
9236 {
9237 struct bnx2x *bp = params->bp;
9238 u16 tmp1, val;
9239
9240 if ((phy->req_line_speed == SPEED_1000) ||
9241 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9242 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9243 bnx2x_cl45_write(bp, phy,
9244 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9245 bnx2x_cl45_write(bp, phy,
9246 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9247 bnx2x_cl45_read(bp, phy,
9248 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9249 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9250
9251
9252
9253 if (DUAL_MEDIA(params)) {
9254 bnx2x_cl45_read(bp, phy,
9255 MDIO_PMA_DEVAD,
9256 MDIO_PMA_REG_8727_PCS_GP, &val);
9257 val |= (3<<10);
9258 bnx2x_cl45_write(bp, phy,
9259 MDIO_PMA_DEVAD,
9260 MDIO_PMA_REG_8727_PCS_GP, val);
9261 }
9262 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9263 ((phy->speed_cap_mask &
9264 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9265 ((phy->speed_cap_mask &
9266 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9267 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9268
9269 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9270 bnx2x_cl45_write(bp, phy,
9271 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9272 bnx2x_cl45_write(bp, phy,
9273 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9274 } else {
9275
9276
9277
9278 bnx2x_cl45_write(bp, phy,
9279 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9280 0x0020);
9281 bnx2x_cl45_write(bp, phy,
9282 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9283 bnx2x_cl45_write(bp, phy,
9284 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9285 bnx2x_cl45_write(bp, phy,
9286 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9287 0x0008);
9288 }
9289 }
9290
9291 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9292 struct link_params *params,
9293 struct link_vars *vars)
9294 {
9295 u32 tx_en_mode;
9296 u16 tmp1, mod_abs, tmp2;
9297 struct bnx2x *bp = params->bp;
9298
9299
9300 bnx2x_wait_reset_complete(bp, phy, params);
9301
9302 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9303
9304 bnx2x_8727_specific_func(phy, params, PHY_INIT);
9305
9306
9307
9308 bnx2x_cl45_read(bp, phy,
9309 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9310
9311
9312
9313
9314 mod_abs &= ~(1<<8);
9315 if (!(phy->flags & FLAGS_NOC))
9316 mod_abs &= ~(1<<9);
9317 bnx2x_cl45_write(bp, phy,
9318 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9319
9320
9321 bnx2x_set_disable_pmd_transmit(params, phy, 0);
9322
9323 bnx2x_8727_power_module(bp, phy, 1);
9324
9325 bnx2x_cl45_read(bp, phy,
9326 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9327
9328 bnx2x_cl45_read(bp, phy,
9329 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9330
9331 bnx2x_8727_config_speed(phy, params);
9332
9333
9334
9335 if ((params->feature_config_flags &
9336 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9337 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9338 phy->tx_preemphasis[0],
9339 phy->tx_preemphasis[1]);
9340 bnx2x_cl45_write(bp, phy,
9341 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9342 phy->tx_preemphasis[0]);
9343
9344 bnx2x_cl45_write(bp, phy,
9345 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9346 phy->tx_preemphasis[1]);
9347 }
9348
9349
9350
9351
9352 tx_en_mode = REG_RD(bp, params->shmem_base +
9353 offsetof(struct shmem_region,
9354 dev_info.port_hw_config[params->port].sfp_ctrl))
9355 & PORT_HW_CFG_TX_LASER_MASK;
9356
9357 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9358
9359 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9360 bnx2x_cl45_read(bp, phy,
9361 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9362 tmp2 |= 0x1000;
9363 tmp2 &= 0xFFEF;
9364 bnx2x_cl45_write(bp, phy,
9365 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9366 bnx2x_cl45_read(bp, phy,
9367 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9368 &tmp2);
9369 bnx2x_cl45_write(bp, phy,
9370 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9371 (tmp2 & 0x7fff));
9372 }
9373
9374 return 0;
9375 }
9376
9377 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9378 struct link_params *params)
9379 {
9380 struct bnx2x *bp = params->bp;
9381 u16 mod_abs, rx_alarm_status;
9382 u32 val = REG_RD(bp, params->shmem_base +
9383 offsetof(struct shmem_region, dev_info.
9384 port_feature_config[params->port].
9385 config));
9386 bnx2x_cl45_read(bp, phy,
9387 MDIO_PMA_DEVAD,
9388 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9389 if (mod_abs & (1<<8)) {
9390
9391
9392 DP(NETIF_MSG_LINK,
9393 "MOD_ABS indication show module is absent\n");
9394 phy->media_type = ETH_PHY_NOT_PRESENT;
9395
9396
9397
9398
9399
9400
9401
9402 mod_abs &= ~(1<<8);
9403 if (!(phy->flags & FLAGS_NOC))
9404 mod_abs &= ~(1<<9);
9405 bnx2x_cl45_write(bp, phy,
9406 MDIO_PMA_DEVAD,
9407 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9408
9409
9410
9411
9412 bnx2x_cl45_read(bp, phy,
9413 MDIO_PMA_DEVAD,
9414 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9415
9416 } else {
9417
9418 DP(NETIF_MSG_LINK,
9419 "MOD_ABS indication show module is present\n");
9420
9421
9422
9423
9424
9425
9426
9427 mod_abs |= (1<<8);
9428 if (!(phy->flags & FLAGS_NOC))
9429 mod_abs |= (1<<9);
9430 bnx2x_cl45_write(bp, phy,
9431 MDIO_PMA_DEVAD,
9432 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9433
9434
9435
9436
9437
9438
9439 bnx2x_cl45_read(bp, phy,
9440 MDIO_PMA_DEVAD,
9441 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9442
9443
9444 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9445 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9446 bnx2x_sfp_set_transmitter(params, phy, 0);
9447
9448 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9449 bnx2x_sfp_module_detection(phy, params);
9450 else
9451 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9452
9453
9454 bnx2x_8727_config_speed(phy, params);
9455 }
9456
9457 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9458 rx_alarm_status);
9459
9460 }
9461
9462 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9463 struct link_params *params,
9464 struct link_vars *vars)
9465
9466 {
9467 struct bnx2x *bp = params->bp;
9468 u8 link_up = 0, oc_port = params->port;
9469 u16 link_status = 0;
9470 u16 rx_alarm_status, lasi_ctrl, val1;
9471
9472
9473 bnx2x_cl45_read(bp, phy,
9474 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9475 &lasi_ctrl);
9476 if (!lasi_ctrl)
9477 return 0;
9478
9479
9480 bnx2x_cl45_read(bp, phy,
9481 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9482 &rx_alarm_status);
9483 vars->line_speed = 0;
9484 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
9485
9486 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9487 MDIO_PMA_LASI_TXCTRL);
9488
9489 bnx2x_cl45_read(bp, phy,
9490 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9491
9492 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9493
9494
9495 bnx2x_cl45_read(bp, phy,
9496 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9497
9498
9499
9500
9501 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9502
9503 bnx2x_cl45_read(bp, phy,
9504 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9505 &val1);
9506
9507 if ((val1 & (1<<8)) == 0) {
9508 if (!CHIP_IS_E1x(bp))
9509 oc_port = BP_PATH(bp) + (params->port << 1);
9510 DP(NETIF_MSG_LINK,
9511 "8727 Power fault has been detected on port %d\n",
9512 oc_port);
9513 netdev_err(bp->dev, "Error: Power fault on Port %d has "
9514 "been detected and the power to "
9515 "that SFP+ module has been removed "
9516 "to prevent failure of the card. "
9517 "Please remove the SFP+ module and "
9518 "restart the system to clear this "
9519 "error.\n",
9520 oc_port);
9521
9522 bnx2x_cl45_write(bp, phy,
9523 MDIO_PMA_DEVAD,
9524 MDIO_PMA_LASI_RXCTRL, (1<<5));
9525
9526 bnx2x_cl45_read(bp, phy,
9527 MDIO_PMA_DEVAD,
9528 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9529
9530 val1 |= (1<<8);
9531 bnx2x_cl45_write(bp, phy,
9532 MDIO_PMA_DEVAD,
9533 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9534
9535 bnx2x_cl45_read(bp, phy,
9536 MDIO_PMA_DEVAD,
9537 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9538 bnx2x_8727_power_module(params->bp, phy, 0);
9539 return 0;
9540 }
9541 }
9542
9543
9544 if (rx_alarm_status & (1<<5)) {
9545 bnx2x_8727_handle_mod_abs(phy, params);
9546
9547 bnx2x_cl45_write(bp, phy,
9548 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9549 ((1<<5) | (1<<2)));
9550 }
9551
9552 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9553 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9554 bnx2x_sfp_set_transmitter(params, phy, 1);
9555 } else {
9556 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9557 return 0;
9558 }
9559
9560 bnx2x_cl45_read(bp, phy,
9561 MDIO_PMA_DEVAD,
9562 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9563
9564
9565
9566
9567 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9568 link_up = 1;
9569 vars->line_speed = SPEED_10000;
9570 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9571 params->port);
9572 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9573 link_up = 1;
9574 vars->line_speed = SPEED_1000;
9575 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9576 params->port);
9577 } else {
9578 link_up = 0;
9579 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9580 params->port);
9581 }
9582
9583
9584 if (vars->line_speed == SPEED_10000) {
9585 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9586 MDIO_PMA_LASI_TXSTAT, &val1);
9587
9588 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9589 MDIO_PMA_LASI_TXSTAT, &val1);
9590
9591 if (val1 & (1<<0)) {
9592 vars->fault_detected = 1;
9593 }
9594 }
9595
9596 if (link_up) {
9597 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9598 vars->duplex = DUPLEX_FULL;
9599 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9600 }
9601
9602 if ((DUAL_MEDIA(params)) &&
9603 (phy->req_line_speed == SPEED_1000)) {
9604 bnx2x_cl45_read(bp, phy,
9605 MDIO_PMA_DEVAD,
9606 MDIO_PMA_REG_8727_PCS_GP, &val1);
9607
9608
9609
9610 if (link_up)
9611 val1 &= ~(3<<10);
9612 else
9613 val1 |= (3<<10);
9614 bnx2x_cl45_write(bp, phy,
9615 MDIO_PMA_DEVAD,
9616 MDIO_PMA_REG_8727_PCS_GP, val1);
9617 }
9618 return link_up;
9619 }
9620
9621 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9622 struct link_params *params)
9623 {
9624 struct bnx2x *bp = params->bp;
9625
9626
9627 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9628
9629
9630 bnx2x_sfp_set_transmitter(params, phy, 0);
9631
9632 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9633
9634 }
9635
9636
9637
9638
9639 static int bnx2x_is_8483x_8485x(struct bnx2x_phy *phy)
9640 {
9641 return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9642 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||
9643 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));
9644 }
9645
9646 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9647 struct bnx2x *bp,
9648 u8 port)
9649 {
9650 u16 val, fw_ver2, cnt, i;
9651 static struct bnx2x_reg_set reg_set[] = {
9652 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9653 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9654 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9655 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9656 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9657 };
9658 u16 fw_ver1;
9659
9660 if (bnx2x_is_8483x_8485x(phy)) {
9661 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9662 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)
9663 fw_ver1 &= 0xfff;
9664 bnx2x_save_spirom_version(bp, port, fw_ver1, phy->ver_addr);
9665 } else {
9666
9667
9668 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9669 bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9670 reg_set[i].reg, reg_set[i].val);
9671
9672 for (cnt = 0; cnt < 100; cnt++) {
9673 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9674 if (val & 1)
9675 break;
9676 udelay(5);
9677 }
9678 if (cnt == 100) {
9679 DP(NETIF_MSG_LINK, "Unable to read 848xx "
9680 "phy fw version(1)\n");
9681 bnx2x_save_spirom_version(bp, port, 0,
9682 phy->ver_addr);
9683 return;
9684 }
9685
9686
9687
9688 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9689 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9690 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9691 for (cnt = 0; cnt < 100; cnt++) {
9692 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9693 if (val & 1)
9694 break;
9695 udelay(5);
9696 }
9697 if (cnt == 100) {
9698 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9699 "version(2)\n");
9700 bnx2x_save_spirom_version(bp, port, 0,
9701 phy->ver_addr);
9702 return;
9703 }
9704
9705
9706 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9707
9708 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9709
9710 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9711 phy->ver_addr);
9712 }
9713
9714 }
9715 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9716 struct bnx2x_phy *phy)
9717 {
9718 u16 val, led3_blink_rate, offset, i;
9719 static struct bnx2x_reg_set reg_set[] = {
9720 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9721 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9722 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9723 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9724 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9725 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9726 };
9727
9728 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
9729
9730 bnx2x_cl45_write(bp, phy,
9731 MDIO_PMA_DEVAD,
9732 MDIO_PMA_REG_8481_LED5_MASK,
9733 0x90);
9734 led3_blink_rate = 0x000f;
9735 } else {
9736 led3_blink_rate = 0x0000;
9737 }
9738
9739 bnx2x_cl45_write(bp, phy,
9740 MDIO_PMA_DEVAD,
9741 MDIO_PMA_REG_8481_LED3_BLINK,
9742 led3_blink_rate);
9743
9744
9745 bnx2x_cl45_read(bp, phy,
9746 MDIO_PMA_DEVAD,
9747 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9748 val &= 0xFE00;
9749 val |= 0x0092;
9750
9751 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)
9752 val |= 2 << 12;
9753
9754 bnx2x_cl45_write(bp, phy,
9755 MDIO_PMA_DEVAD,
9756 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9757
9758 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9759 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9760 reg_set[i].val);
9761
9762 if (bnx2x_is_8483x_8485x(phy))
9763 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9764 else
9765 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9766
9767 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)
9768 val = MDIO_PMA_REG_84858_ALLOW_GPHY_ACT |
9769 MDIO_PMA_REG_84823_LED3_STRETCH_EN;
9770 else
9771 val = MDIO_PMA_REG_84823_LED3_STRETCH_EN;
9772
9773
9774 bnx2x_cl45_read_or_write(bp, phy,
9775 MDIO_PMA_DEVAD,
9776 offset,
9777 val);
9778 }
9779
9780 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9781 struct link_params *params,
9782 u32 action)
9783 {
9784 struct bnx2x *bp = params->bp;
9785 switch (action) {
9786 case PHY_INIT:
9787 if (bnx2x_is_8483x_8485x(phy)) {
9788
9789 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9790 }
9791
9792
9793
9794
9795 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9796 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9797
9798 bnx2x_848xx_set_led(bp, phy);
9799 break;
9800 }
9801 }
9802
9803 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9804 struct link_params *params,
9805 struct link_vars *vars)
9806 {
9807 struct bnx2x *bp = params->bp;
9808 u16 autoneg_val, an_1000_val, an_10_100_val;
9809
9810 bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9811 bnx2x_cl45_write(bp, phy,
9812 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9813
9814
9815 bnx2x_cl45_read(bp, phy,
9816 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9817 &an_1000_val);
9818
9819 bnx2x_ext_phy_set_pause(params, phy, vars);
9820 bnx2x_cl45_read(bp, phy,
9821 MDIO_AN_DEVAD,
9822 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9823 &an_10_100_val);
9824 bnx2x_cl45_read(bp, phy,
9825 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9826 &autoneg_val);
9827
9828 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9829 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9830
9831 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9832 (phy->speed_cap_mask &
9833 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9834 (phy->req_line_speed == SPEED_1000)) {
9835 an_1000_val |= (1<<8);
9836 autoneg_val |= (1<<9 | 1<<12);
9837 if (phy->req_duplex == DUPLEX_FULL)
9838 an_1000_val |= (1<<9);
9839 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9840 } else
9841 an_1000_val &= ~((1<<8) | (1<<9));
9842
9843 bnx2x_cl45_write(bp, phy,
9844 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9845 an_1000_val);
9846
9847
9848 if (phy->req_line_speed == SPEED_AUTO_NEG) {
9849 if (phy->speed_cap_mask &
9850 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9851
9852
9853 autoneg_val |= (1<<9 | 1<<12);
9854 an_10_100_val |= (1<<8);
9855 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
9856 }
9857
9858 if (phy->speed_cap_mask &
9859 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9860
9861
9862 autoneg_val |= (1<<9 | 1<<12);
9863 an_10_100_val |= (1<<7);
9864 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
9865 }
9866
9867 if ((phy->speed_cap_mask &
9868 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9869 (phy->supported & SUPPORTED_10baseT_Full)) {
9870 an_10_100_val |= (1<<6);
9871 autoneg_val |= (1<<9 | 1<<12);
9872 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
9873 }
9874
9875 if ((phy->speed_cap_mask &
9876 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9877 (phy->supported & SUPPORTED_10baseT_Half)) {
9878 an_10_100_val |= (1<<5);
9879 autoneg_val |= (1<<9 | 1<<12);
9880 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
9881 }
9882 }
9883
9884
9885 if ((phy->req_line_speed == SPEED_100) &&
9886 (phy->supported &
9887 (SUPPORTED_100baseT_Half |
9888 SUPPORTED_100baseT_Full))) {
9889 autoneg_val |= (1<<13);
9890
9891 bnx2x_cl45_write(bp, phy,
9892 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9893 (1<<15 | 1<<9 | 7<<0));
9894
9895 an_10_100_val |= (1<<8) | (1<<7);
9896 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9897 }
9898 if ((phy->req_line_speed == SPEED_10) &&
9899 (phy->supported &
9900 (SUPPORTED_10baseT_Half |
9901 SUPPORTED_10baseT_Full))) {
9902
9903 bnx2x_cl45_write(bp, phy,
9904 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9905 (1<<15 | 1<<9 | 7<<0));
9906 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9907 }
9908
9909 bnx2x_cl45_write(bp, phy,
9910 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9911 an_10_100_val);
9912
9913 if (phy->req_duplex == DUPLEX_FULL)
9914 autoneg_val |= (1<<8);
9915
9916
9917
9918
9919 if (!bnx2x_is_8483x_8485x(phy) ||
9920 ((autoneg_val & (1<<12)) == 0))
9921 bnx2x_cl45_write(bp, phy,
9922 MDIO_AN_DEVAD,
9923 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9924
9925 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9926 (phy->speed_cap_mask &
9927 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9928 (phy->req_line_speed == SPEED_10000)) {
9929 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9930
9931
9932 bnx2x_cl45_read_or_write(
9933 bp, phy,
9934 MDIO_AN_DEVAD,
9935 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9936 0x1000);
9937 bnx2x_cl45_write(bp, phy,
9938 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9939 0x3200);
9940 } else
9941 bnx2x_cl45_write(bp, phy,
9942 MDIO_AN_DEVAD,
9943 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9944 1);
9945
9946 return 0;
9947 }
9948
9949 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9950 struct link_params *params,
9951 struct link_vars *vars)
9952 {
9953 struct bnx2x *bp = params->bp;
9954
9955 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9956 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9957
9958
9959 bnx2x_ext_phy_hw_reset(bp, params->port);
9960 bnx2x_wait_reset_complete(bp, phy, params);
9961
9962 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9963 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9964 }
9965
9966 #define PHY848xx_CMDHDLR_WAIT 300
9967 #define PHY848xx_CMDHDLR_MAX_ARGS 5
9968
9969 static int bnx2x_84858_cmd_hdlr(struct bnx2x_phy *phy,
9970 struct link_params *params,
9971 u16 fw_cmd,
9972 u16 cmd_args[], int argc)
9973 {
9974 int idx;
9975 u16 val;
9976 struct bnx2x *bp = params->bp;
9977
9978
9979
9980
9981
9982
9983
9984
9985 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
9986 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9987 MDIO_848xx_CMD_HDLR_STATUS, &val);
9988 if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) &&
9989 (val != PHY84858_STATUS_CMD_SYSTEM_BUSY))
9990 break;
9991 usleep_range(1000, 2000);
9992 }
9993 if (idx >= PHY848xx_CMDHDLR_WAIT) {
9994 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9995 return -EINVAL;
9996 }
9997
9998
9999
10000
10001
10002 for (idx = 0; idx < argc; idx++) {
10003 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10004 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10005 cmd_args[idx]);
10006 }
10007
10008
10009
10010
10011 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10012 MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10013
10014
10015
10016
10017
10018
10019 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10020 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10021 MDIO_848xx_CMD_HDLR_STATUS, &val);
10022 if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) ||
10023 (val == PHY84858_STATUS_CMD_COMPLETE_ERROR))
10024 break;
10025 usleep_range(1000, 2000);
10026 }
10027 if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10028 (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) {
10029 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
10030 return -EINVAL;
10031 }
10032
10033
10034
10035
10036
10037 for (idx = 0; idx < argc; idx++) {
10038 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10039 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10040 &cmd_args[idx]);
10041 }
10042
10043 return 0;
10044 }
10045
10046 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
10047 struct link_params *params, u16 fw_cmd,
10048 u16 cmd_args[], int argc, int process)
10049 {
10050 int idx;
10051 u16 val;
10052 struct bnx2x *bp = params->bp;
10053 int rc = 0;
10054
10055 if (process == PHY84833_MB_PROCESS2) {
10056
10057 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10058 MDIO_848xx_CMD_HDLR_STATUS,
10059 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
10060 }
10061
10062 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10063 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10064 MDIO_848xx_CMD_HDLR_STATUS, &val);
10065 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
10066 break;
10067 usleep_range(1000, 2000);
10068 }
10069 if (idx >= PHY848xx_CMDHDLR_WAIT) {
10070 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
10071
10072
10073
10074 if (val == PHY84833_STATUS_CMD_COMPLETE_PASS ||
10075 val == PHY84833_STATUS_CMD_COMPLETE_ERROR) {
10076 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10077 MDIO_848xx_CMD_HDLR_STATUS,
10078 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10079 }
10080 return -EINVAL;
10081 }
10082 if (process == PHY84833_MB_PROCESS1 ||
10083 process == PHY84833_MB_PROCESS2) {
10084
10085 for (idx = 0; idx < argc; idx++) {
10086 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10087 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10088 cmd_args[idx]);
10089 }
10090 }
10091
10092 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10093 MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10094 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10095 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10096 MDIO_848xx_CMD_HDLR_STATUS, &val);
10097 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
10098 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
10099 break;
10100 usleep_range(1000, 2000);
10101 }
10102 if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10103 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
10104 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
10105 rc = -EINVAL;
10106 }
10107 if (process == PHY84833_MB_PROCESS3 && rc == 0) {
10108
10109 for (idx = 0; idx < argc; idx++) {
10110 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10111 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10112 &cmd_args[idx]);
10113 }
10114 }
10115 if (val == PHY84833_STATUS_CMD_COMPLETE_ERROR ||
10116 val == PHY84833_STATUS_CMD_COMPLETE_PASS) {
10117 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10118 MDIO_848xx_CMD_HDLR_STATUS,
10119 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10120 }
10121 return rc;
10122 }
10123
10124 static int bnx2x_848xx_cmd_hdlr(struct bnx2x_phy *phy,
10125 struct link_params *params,
10126 u16 fw_cmd,
10127 u16 cmd_args[], int argc,
10128 int process)
10129 {
10130 struct bnx2x *bp = params->bp;
10131
10132 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||
10133 (REG_RD(bp, params->shmem2_base +
10134 offsetof(struct shmem2_region,
10135 link_attr_sync[params->port])) &
10136 LINK_ATTR_84858)) {
10137 return bnx2x_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10138 argc);
10139 } else {
10140 return bnx2x_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10141 argc, process);
10142 }
10143 }
10144
10145 static int bnx2x_848xx_pair_swap_cfg(struct bnx2x_phy *phy,
10146 struct link_params *params,
10147 struct link_vars *vars)
10148 {
10149 u32 pair_swap;
10150 u16 data[PHY848xx_CMDHDLR_MAX_ARGS];
10151 int status;
10152 struct bnx2x *bp = params->bp;
10153
10154
10155 pair_swap = REG_RD(bp, params->shmem_base +
10156 offsetof(struct shmem_region,
10157 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10158 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
10159
10160 if (pair_swap == 0)
10161 return 0;
10162
10163
10164 data[1] = (u16)pair_swap;
10165
10166 status = bnx2x_848xx_cmd_hdlr(phy, params,
10167 PHY848xx_CMD_SET_PAIR_SWAP, data,
10168 2, PHY84833_MB_PROCESS2);
10169 if (status == 0)
10170 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
10171
10172 return status;
10173 }
10174
10175 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
10176 u32 shmem_base_path[],
10177 u32 chip_id)
10178 {
10179 u32 reset_pin[2];
10180 u32 idx;
10181 u8 reset_gpios;
10182 if (CHIP_IS_E3(bp)) {
10183
10184 for (idx = 0; idx < 2; idx++) {
10185
10186 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10187 offsetof(struct shmem_region,
10188 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
10189 reset_pin[idx] = (reset_pin[idx] &
10190 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10191 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10192 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
10193 reset_pin[idx] = (1 << reset_pin[idx]);
10194 }
10195 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10196 } else {
10197
10198 for (idx = 0; idx < 2; idx++) {
10199 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10200 offsetof(struct shmem_region,
10201 dev_info.port_hw_config[0].default_cfg));
10202 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
10203 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
10204 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
10205 reset_pin[idx] = (1 << reset_pin[idx]);
10206 }
10207 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10208 }
10209
10210 return reset_gpios;
10211 }
10212
10213 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
10214 struct link_params *params)
10215 {
10216 struct bnx2x *bp = params->bp;
10217 u8 reset_gpios;
10218 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
10219 offsetof(struct shmem2_region,
10220 other_shmem_base_addr));
10221
10222 u32 shmem_base_path[2];
10223
10224
10225 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10226 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10227 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10228 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10229 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10230 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10231
10232 shmem_base_path[0] = params->shmem_base;
10233 shmem_base_path[1] = other_shmem_base_addr;
10234
10235 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10236 params->chip_id);
10237
10238 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10239 udelay(10);
10240 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10241 reset_gpios);
10242
10243 return 0;
10244 }
10245
10246 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10247 struct link_params *params,
10248 struct link_vars *vars)
10249 {
10250 int rc;
10251 struct bnx2x *bp = params->bp;
10252 u16 cmd_args = 0;
10253
10254 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10255
10256
10257 rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
10258 &cmd_args, 1, PHY84833_MB_PROCESS1);
10259 if (rc) {
10260 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10261 return rc;
10262 }
10263
10264 return bnx2x_eee_disable(phy, params, vars);
10265 }
10266
10267 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10268 struct link_params *params,
10269 struct link_vars *vars)
10270 {
10271 int rc;
10272 struct bnx2x *bp = params->bp;
10273 u16 cmd_args = 1;
10274
10275 rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
10276 &cmd_args, 1, PHY84833_MB_PROCESS1);
10277 if (rc) {
10278 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10279 return rc;
10280 }
10281
10282 return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10283 }
10284
10285 #define PHY84833_CONSTANT_LATENCY 1193
10286 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10287 struct link_params *params,
10288 struct link_vars *vars)
10289 {
10290 struct bnx2x *bp = params->bp;
10291 u8 port, initialize = 1;
10292 u16 val;
10293 u32 actual_phy_selection;
10294 u16 cmd_args[PHY848xx_CMDHDLR_MAX_ARGS];
10295 int rc = 0;
10296
10297 usleep_range(1000, 2000);
10298
10299 if (!(CHIP_IS_E1x(bp)))
10300 port = BP_PATH(bp);
10301 else
10302 port = params->port;
10303
10304 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10305 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10306 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10307 port);
10308 } else {
10309
10310 bnx2x_cl45_write(bp, phy,
10311 MDIO_PMA_DEVAD,
10312 MDIO_PMA_REG_CTRL, 0x8000);
10313 }
10314
10315 bnx2x_wait_reset_complete(bp, phy, params);
10316
10317
10318 msleep(50);
10319 if (!bnx2x_is_8483x_8485x(phy)) {
10320
10321
10322
10323 u16 temp;
10324 temp = vars->line_speed;
10325 vars->line_speed = SPEED_10000;
10326 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0);
10327 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars);
10328 vars->line_speed = temp;
10329 }
10330
10331 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10332 u16 hw_rev;
10333
10334 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10335 MDIO_AN_REG_848xx_ID_MSB, &hw_rev);
10336 if (hw_rev == BCM84858_PHY_ID) {
10337 params->link_attr_sync |= LINK_ATTR_84858;
10338 bnx2x_update_link_attr(params, params->link_attr_sync);
10339 }
10340 }
10341
10342
10343 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10344 MDIO_CTL_REG_84823_MEDIA, &val);
10345 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10346 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10347 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10348 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10349 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10350
10351 if (CHIP_IS_E3(bp)) {
10352 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10353 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10354 } else {
10355 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10356 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10357 }
10358
10359 actual_phy_selection = bnx2x_phy_selection(params);
10360
10361 switch (actual_phy_selection) {
10362 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10363
10364 break;
10365 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10366 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10367 break;
10368 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10369 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10370 break;
10371 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10372
10373 break;
10374 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10375 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10376 initialize = 0;
10377 break;
10378 }
10379 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10380 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10381
10382 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10383 MDIO_CTL_REG_84823_MEDIA, val);
10384 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10385 params->multi_phy_config, val);
10386
10387 if (bnx2x_is_8483x_8485x(phy)) {
10388 bnx2x_848xx_pair_swap_cfg(phy, params, vars);
10389
10390
10391 cmd_args[0] = 0x0;
10392 cmd_args[1] = 0x0;
10393 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10394 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10395 rc = bnx2x_848xx_cmd_hdlr(phy, params,
10396 PHY848xx_CMD_SET_EEE_MODE, cmd_args,
10397 4, PHY84833_MB_PROCESS1);
10398 if (rc)
10399 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10400 }
10401 if (initialize)
10402 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10403 else
10404 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10405
10406 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10407 u32 cms_enable = REG_RD(bp, params->shmem_base +
10408 offsetof(struct shmem_region,
10409 dev_info.port_hw_config[params->port].default_cfg)) &
10410 PORT_HW_CFG_ENABLE_CMS_MASK;
10411
10412 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10413 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10414 if (cms_enable)
10415 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10416 else
10417 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10418 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10419 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10420 }
10421
10422 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10423 MDIO_84833_TOP_CFG_FW_REV, &val);
10424
10425
10426 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10427 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10428 bnx2x_eee_has_cap(params)) {
10429 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10430 if (rc) {
10431 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10432 bnx2x_8483x_disable_eee(phy, params, vars);
10433 return rc;
10434 }
10435
10436 if ((phy->req_duplex == DUPLEX_FULL) &&
10437 (params->eee_mode & EEE_MODE_ADV_LPI) &&
10438 (bnx2x_eee_calc_timer(params) ||
10439 !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10440 rc = bnx2x_8483x_enable_eee(phy, params, vars);
10441 else
10442 rc = bnx2x_8483x_disable_eee(phy, params, vars);
10443 if (rc) {
10444 DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10445 return rc;
10446 }
10447 } else {
10448 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10449 }
10450
10451 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10452
10453
10454 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10455 MDIO_AN_REG_8481_AUX_CTRL, &val);
10456 val |= 0x4000;
10457 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10458 MDIO_AN_REG_8481_AUX_CTRL, val);
10459
10460 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10461 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, &val);
10462 val |= 0x1;
10463 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10464 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, val);
10465
10466
10467 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10468 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf46);
10469
10470 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10471 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, &val);
10472 val |= 0x4000;
10473 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10474 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, val);
10475 }
10476
10477 if (bnx2x_is_8483x_8485x(phy)) {
10478
10479 bnx2x_cl45_read_and_write(bp, phy,
10480 MDIO_CTL_DEVAD,
10481 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10482 (u16)~MDIO_84833_SUPER_ISOLATE);
10483 }
10484 return rc;
10485 }
10486
10487 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10488 struct link_params *params,
10489 struct link_vars *vars)
10490 {
10491 struct bnx2x *bp = params->bp;
10492 u16 val, val1, val2;
10493 u8 link_up = 0;
10494
10495
10496
10497
10498 bnx2x_cl45_read(bp, phy,
10499 MDIO_AN_DEVAD, 0xFFFA, &val1);
10500 bnx2x_cl45_read(bp, phy,
10501 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10502 &val2);
10503 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10504
10505
10506 if (val2 & (1<<11)) {
10507 vars->line_speed = SPEED_10000;
10508 vars->duplex = DUPLEX_FULL;
10509 link_up = 1;
10510 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10511 } else {
10512 u16 legacy_status, legacy_speed;
10513
10514
10515 bnx2x_cl45_write(bp, phy,
10516 MDIO_AN_DEVAD,
10517 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10518
10519
10520 bnx2x_cl45_read(bp, phy,
10521 MDIO_AN_DEVAD,
10522 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10523 &legacy_status);
10524
10525 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10526 legacy_status);
10527 link_up = ((legacy_status & (1<<11)) == (1<<11));
10528 legacy_speed = (legacy_status & (3<<9));
10529 if (legacy_speed == (0<<9))
10530 vars->line_speed = SPEED_10;
10531 else if (legacy_speed == (1<<9))
10532 vars->line_speed = SPEED_100;
10533 else if (legacy_speed == (2<<9))
10534 vars->line_speed = SPEED_1000;
10535 else {
10536 vars->line_speed = 0;
10537 link_up = 0;
10538 }
10539
10540 if (link_up) {
10541 if (legacy_status & (1<<8))
10542 vars->duplex = DUPLEX_FULL;
10543 else
10544 vars->duplex = DUPLEX_HALF;
10545
10546 DP(NETIF_MSG_LINK,
10547 "Link is up in %dMbps, is_duplex_full= %d\n",
10548 vars->line_speed,
10549 (vars->duplex == DUPLEX_FULL));
10550
10551 bnx2x_cl45_read(bp, phy,
10552 MDIO_AN_DEVAD,
10553 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10554 &val);
10555 if (val & (1<<5))
10556 vars->link_status |=
10557 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10558 bnx2x_cl45_read(bp, phy,
10559 MDIO_AN_DEVAD,
10560 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10561 &val);
10562 if ((val & (1<<0)) == 0)
10563 vars->link_status |=
10564 LINK_STATUS_PARALLEL_DETECTION_USED;
10565 }
10566 }
10567 if (link_up) {
10568 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10569 vars->line_speed);
10570 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10571
10572
10573 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10574 MDIO_AN_REG_CL37_FC_LP, &val);
10575 if (val & (1<<5))
10576 vars->link_status |=
10577 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10578 if (val & (1<<6))
10579 vars->link_status |=
10580 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10581 if (val & (1<<7))
10582 vars->link_status |=
10583 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10584 if (val & (1<<8))
10585 vars->link_status |=
10586 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10587 if (val & (1<<9))
10588 vars->link_status |=
10589 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10590
10591 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10592 MDIO_AN_REG_1000T_STATUS, &val);
10593
10594 if (val & (1<<10))
10595 vars->link_status |=
10596 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10597 if (val & (1<<11))
10598 vars->link_status |=
10599 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10600
10601 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10602 MDIO_AN_REG_MASTER_STATUS, &val);
10603
10604 if (val & (1<<11))
10605 vars->link_status |=
10606 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10607
10608
10609 if (bnx2x_is_8483x_8485x(phy))
10610 bnx2x_eee_an_resolve(phy, params, vars);
10611 }
10612
10613 return link_up;
10614 }
10615
10616 static int bnx2x_8485x_format_ver(u32 raw_ver, u8 *str, u16 *len)
10617 {
10618 u32 num;
10619
10620 num = ((raw_ver & 0xF80) >> 7) << 16 | ((raw_ver & 0x7F) << 8) |
10621 ((raw_ver & 0xF000) >> 12);
10622 return bnx2x_3_seq_format_ver(num, str, len);
10623 }
10624
10625 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10626 {
10627 u32 spirom_ver;
10628
10629 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10630 return bnx2x_format_ver(spirom_ver, str, len);
10631 }
10632
10633 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10634 struct link_params *params)
10635 {
10636 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10637 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10638 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10639 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10640 }
10641
10642 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10643 struct link_params *params)
10644 {
10645 bnx2x_cl45_write(params->bp, phy,
10646 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10647 bnx2x_cl45_write(params->bp, phy,
10648 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10649 }
10650
10651 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10652 struct link_params *params)
10653 {
10654 struct bnx2x *bp = params->bp;
10655 u8 port;
10656 u16 val16;
10657
10658 if (!(CHIP_IS_E1x(bp)))
10659 port = BP_PATH(bp);
10660 else
10661 port = params->port;
10662
10663 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10664 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10665 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10666 port);
10667 } else {
10668 bnx2x_cl45_read(bp, phy,
10669 MDIO_CTL_DEVAD,
10670 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10671 val16 |= MDIO_84833_SUPER_ISOLATE;
10672 bnx2x_cl45_write(bp, phy,
10673 MDIO_CTL_DEVAD,
10674 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10675 }
10676 }
10677
10678 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10679 struct link_params *params, u8 mode)
10680 {
10681 struct bnx2x *bp = params->bp;
10682 u16 val;
10683 u8 port;
10684
10685 if (!(CHIP_IS_E1x(bp)))
10686 port = BP_PATH(bp);
10687 else
10688 port = params->port;
10689
10690 switch (mode) {
10691 case LED_MODE_OFF:
10692
10693 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10694
10695 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10696 SHARED_HW_CFG_LED_EXTPHY1) {
10697
10698
10699 bnx2x_cl45_write(bp, phy,
10700 MDIO_PMA_DEVAD,
10701 MDIO_PMA_REG_8481_LED1_MASK,
10702 0x0);
10703
10704 bnx2x_cl45_write(bp, phy,
10705 MDIO_PMA_DEVAD,
10706 MDIO_PMA_REG_8481_LED2_MASK,
10707 0x0);
10708
10709 bnx2x_cl45_write(bp, phy,
10710 MDIO_PMA_DEVAD,
10711 MDIO_PMA_REG_8481_LED3_MASK,
10712 0x0);
10713
10714 bnx2x_cl45_write(bp, phy,
10715 MDIO_PMA_DEVAD,
10716 MDIO_PMA_REG_8481_LED5_MASK,
10717 0x0);
10718
10719 } else {
10720
10721 bnx2x_cl45_write(bp, phy,
10722 MDIO_PMA_DEVAD,
10723 MDIO_PMA_REG_8481_LED1_MASK,
10724 0x0);
10725
10726 if (phy->type ==
10727 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10728
10729 bnx2x_cl45_write(bp, phy,
10730 MDIO_PMA_DEVAD,
10731 MDIO_PMA_REG_8481_LED2_MASK,
10732 0x0);
10733
10734 bnx2x_cl45_write(bp, phy,
10735 MDIO_PMA_DEVAD,
10736 MDIO_PMA_REG_8481_LED3_MASK,
10737 0x0);
10738 }
10739 }
10740 break;
10741 case LED_MODE_FRONT_PANEL_OFF:
10742
10743 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10744 port);
10745
10746 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10747 SHARED_HW_CFG_LED_EXTPHY1) {
10748
10749
10750 bnx2x_cl45_write(bp, phy,
10751 MDIO_PMA_DEVAD,
10752 MDIO_PMA_REG_8481_LED1_MASK,
10753 0x0);
10754
10755 bnx2x_cl45_write(bp, phy,
10756 MDIO_PMA_DEVAD,
10757 MDIO_PMA_REG_8481_LED2_MASK,
10758 0x0);
10759
10760 bnx2x_cl45_write(bp, phy,
10761 MDIO_PMA_DEVAD,
10762 MDIO_PMA_REG_8481_LED3_MASK,
10763 0x0);
10764
10765 bnx2x_cl45_write(bp, phy,
10766 MDIO_PMA_DEVAD,
10767 MDIO_PMA_REG_8481_LED5_MASK,
10768 0x20);
10769
10770 } else {
10771 bnx2x_cl45_write(bp, phy,
10772 MDIO_PMA_DEVAD,
10773 MDIO_PMA_REG_8481_LED1_MASK,
10774 0x0);
10775 if (phy->type ==
10776 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10777
10778
10779
10780 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10781 params->port*4) &
10782 NIG_MASK_MI_INT) {
10783 params->link_flags |=
10784 LINK_FLAGS_INT_DISABLED;
10785
10786 bnx2x_bits_dis(
10787 bp,
10788 NIG_REG_MASK_INTERRUPT_PORT0 +
10789 params->port*4,
10790 NIG_MASK_MI_INT);
10791 }
10792 bnx2x_cl45_write(bp, phy,
10793 MDIO_PMA_DEVAD,
10794 MDIO_PMA_REG_8481_SIGNAL_MASK,
10795 0x0);
10796 }
10797 if (phy->type ==
10798 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10799
10800 bnx2x_cl45_write(bp, phy,
10801 MDIO_PMA_DEVAD,
10802 MDIO_PMA_REG_8481_LED2_MASK,
10803 0x0);
10804
10805 bnx2x_cl45_write(bp, phy,
10806 MDIO_PMA_DEVAD,
10807 MDIO_PMA_REG_8481_LED3_MASK,
10808 0x0);
10809 }
10810 }
10811 break;
10812 case LED_MODE_ON:
10813
10814 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10815
10816 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10817 SHARED_HW_CFG_LED_EXTPHY1) {
10818
10819 bnx2x_cl45_read(bp, phy,
10820 MDIO_PMA_DEVAD,
10821 MDIO_PMA_REG_8481_LINK_SIGNAL,
10822 &val);
10823 val &= 0x8000;
10824 val |= 0x2492;
10825
10826 bnx2x_cl45_write(bp, phy,
10827 MDIO_PMA_DEVAD,
10828 MDIO_PMA_REG_8481_LINK_SIGNAL,
10829 val);
10830
10831
10832 bnx2x_cl45_write(bp, phy,
10833 MDIO_PMA_DEVAD,
10834 MDIO_PMA_REG_8481_LED1_MASK,
10835 0x0);
10836
10837 bnx2x_cl45_write(bp, phy,
10838 MDIO_PMA_DEVAD,
10839 MDIO_PMA_REG_8481_LED2_MASK,
10840 0x20);
10841
10842 bnx2x_cl45_write(bp, phy,
10843 MDIO_PMA_DEVAD,
10844 MDIO_PMA_REG_8481_LED3_MASK,
10845 0x20);
10846
10847 bnx2x_cl45_write(bp, phy,
10848 MDIO_PMA_DEVAD,
10849 MDIO_PMA_REG_8481_LED5_MASK,
10850 0x0);
10851 } else {
10852 bnx2x_cl45_write(bp, phy,
10853 MDIO_PMA_DEVAD,
10854 MDIO_PMA_REG_8481_LED1_MASK,
10855 0x20);
10856 if (phy->type ==
10857 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10858
10859
10860
10861 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10862 params->port*4) &
10863 NIG_MASK_MI_INT) {
10864 params->link_flags |=
10865 LINK_FLAGS_INT_DISABLED;
10866
10867 bnx2x_bits_dis(
10868 bp,
10869 NIG_REG_MASK_INTERRUPT_PORT0 +
10870 params->port*4,
10871 NIG_MASK_MI_INT);
10872 }
10873 }
10874 if (phy->type ==
10875 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10876
10877 bnx2x_cl45_read(bp, phy,
10878 MDIO_PMA_DEVAD,
10879 MDIO_PMA_REG_8481_LINK_SIGNAL,
10880 &val);
10881 val &= ~(7<<6);
10882 val |= (2<<6);
10883 bnx2x_cl45_write(bp, phy,
10884 MDIO_PMA_DEVAD,
10885 MDIO_PMA_REG_8481_LINK_SIGNAL,
10886 val);
10887 bnx2x_cl45_write(bp, phy,
10888 MDIO_PMA_DEVAD,
10889 MDIO_PMA_REG_8481_LED3_MASK,
10890 0x20);
10891 } else {
10892 bnx2x_cl45_write(bp, phy,
10893 MDIO_PMA_DEVAD,
10894 MDIO_PMA_REG_8481_SIGNAL_MASK,
10895 0x20);
10896 }
10897 }
10898 break;
10899
10900 case LED_MODE_OPER:
10901
10902 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10903
10904 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10905 SHARED_HW_CFG_LED_EXTPHY1) {
10906
10907
10908 bnx2x_cl45_read(bp, phy,
10909 MDIO_PMA_DEVAD,
10910 MDIO_PMA_REG_8481_LINK_SIGNAL,
10911 &val);
10912
10913 if (!((val &
10914 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10915 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10916 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10917 bnx2x_cl45_write(bp, phy,
10918 MDIO_PMA_DEVAD,
10919 MDIO_PMA_REG_8481_LINK_SIGNAL,
10920 0xa492);
10921 }
10922
10923
10924 bnx2x_cl45_write(bp, phy,
10925 MDIO_PMA_DEVAD,
10926 MDIO_PMA_REG_8481_LED1_MASK,
10927 0x10);
10928
10929 bnx2x_cl45_write(bp, phy,
10930 MDIO_PMA_DEVAD,
10931 MDIO_PMA_REG_8481_LED2_MASK,
10932 0x80);
10933
10934 bnx2x_cl45_write(bp, phy,
10935 MDIO_PMA_DEVAD,
10936 MDIO_PMA_REG_8481_LED3_MASK,
10937 0x98);
10938
10939 bnx2x_cl45_write(bp, phy,
10940 MDIO_PMA_DEVAD,
10941 MDIO_PMA_REG_8481_LED5_MASK,
10942 0x40);
10943
10944 } else {
10945
10946
10947
10948
10949 val = ((params->hw_led_mode <<
10950 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10951 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10952
10953 bnx2x_cl45_write(bp, phy,
10954 MDIO_PMA_DEVAD,
10955 MDIO_PMA_REG_8481_LED1_MASK,
10956 val);
10957
10958
10959 bnx2x_cl45_read(bp, phy,
10960 MDIO_PMA_DEVAD,
10961 MDIO_PMA_REG_8481_LINK_SIGNAL,
10962 &val);
10963 val &= ~(7<<6);
10964 val |= (1<<6);
10965 bnx2x_cl45_write(bp, phy,
10966 MDIO_PMA_DEVAD,
10967 MDIO_PMA_REG_8481_LINK_SIGNAL,
10968 val);
10969 if (phy->type ==
10970 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10971 bnx2x_cl45_write(bp, phy,
10972 MDIO_PMA_DEVAD,
10973 MDIO_PMA_REG_8481_LED2_MASK,
10974 0x18);
10975 bnx2x_cl45_write(bp, phy,
10976 MDIO_PMA_DEVAD,
10977 MDIO_PMA_REG_8481_LED3_MASK,
10978 0x06);
10979 }
10980 if (phy->type ==
10981 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10982
10983
10984
10985 bnx2x_cl45_write(bp, phy,
10986 MDIO_PMA_DEVAD,
10987 MDIO_PMA_REG_8481_SIGNAL_MASK,
10988 0x40);
10989 if (params->link_flags &
10990 LINK_FLAGS_INT_DISABLED) {
10991 bnx2x_link_int_enable(params);
10992 params->link_flags &=
10993 ~LINK_FLAGS_INT_DISABLED;
10994 }
10995 }
10996 }
10997 break;
10998 }
10999
11000
11001
11002
11003 if (CHIP_IS_E3(bp)) {
11004 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
11005 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
11006 }
11007 }
11008
11009
11010
11011
11012 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
11013 struct link_params *params,
11014 u32 action)
11015 {
11016 struct bnx2x *bp = params->bp;
11017 u16 temp;
11018 switch (action) {
11019 case PHY_INIT:
11020
11021
11022 bnx2x_cl22_write(bp, phy,
11023 MDIO_REG_GPHY_SHADOW,
11024 MDIO_REG_GPHY_SHADOW_LED_SEL2);
11025 bnx2x_cl22_read(bp, phy,
11026 MDIO_REG_GPHY_SHADOW,
11027 &temp);
11028 temp &= ~(0xf << 4);
11029 temp |= (0x6 << 4);
11030 bnx2x_cl22_write(bp, phy,
11031 MDIO_REG_GPHY_SHADOW,
11032 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11033
11034 bnx2x_cl22_write(bp, phy,
11035 MDIO_REG_INTR_MASK,
11036 ~MDIO_REG_INTR_MASK_LINK_STATUS);
11037 break;
11038 }
11039 }
11040
11041 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
11042 struct link_params *params,
11043 struct link_vars *vars)
11044 {
11045 struct bnx2x *bp = params->bp;
11046 u8 port;
11047 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
11048 u32 cfg_pin;
11049
11050 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
11051 usleep_range(1000, 2000);
11052
11053
11054
11055
11056 port = params->port;
11057
11058 cfg_pin = (REG_RD(bp, params->shmem_base +
11059 offsetof(struct shmem_region,
11060 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11061 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11062 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11063
11064
11065 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
11066
11067
11068 msleep(50);
11069
11070
11071 bnx2x_cl22_write(bp, phy,
11072 MDIO_PMA_REG_CTRL, 0x8000);
11073 bnx2x_wait_reset_complete(bp, phy, params);
11074
11075
11076 msleep(50);
11077
11078
11079 bnx2x_54618se_specific_func(phy, params, PHY_INIT);
11080
11081 bnx2x_cl22_write(bp, phy,
11082 MDIO_REG_GPHY_SHADOW,
11083 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
11084 bnx2x_cl22_read(bp, phy,
11085 MDIO_REG_GPHY_SHADOW,
11086 &temp);
11087 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
11088 bnx2x_cl22_write(bp, phy,
11089 MDIO_REG_GPHY_SHADOW,
11090 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11091
11092
11093
11094 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
11095 fc_val = 0;
11096 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
11097 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
11098 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
11099
11100 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
11101 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
11102 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
11103
11104
11105 bnx2x_cl22_read(bp, phy,
11106 0x09,
11107 &an_1000_val);
11108
11109 bnx2x_cl22_read(bp, phy,
11110 0x04,
11111 &an_10_100_val);
11112
11113 bnx2x_cl22_read(bp, phy,
11114 MDIO_PMA_REG_CTRL,
11115 &autoneg_val);
11116
11117
11118 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
11119 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
11120 (1<<11));
11121
11122 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
11123 (phy->speed_cap_mask &
11124 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
11125 (phy->req_line_speed == SPEED_1000)) {
11126 an_1000_val |= (1<<8);
11127 autoneg_val |= (1<<9 | 1<<12);
11128 if (phy->req_duplex == DUPLEX_FULL)
11129 an_1000_val |= (1<<9);
11130 DP(NETIF_MSG_LINK, "Advertising 1G\n");
11131 } else
11132 an_1000_val &= ~((1<<8) | (1<<9));
11133
11134 bnx2x_cl22_write(bp, phy,
11135 0x09,
11136 an_1000_val);
11137 bnx2x_cl22_read(bp, phy,
11138 0x09,
11139 &an_1000_val);
11140
11141
11142 if (phy->req_line_speed == SPEED_AUTO_NEG) {
11143 if (phy->speed_cap_mask &
11144 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11145 an_10_100_val |= (1<<5);
11146 autoneg_val |= (1<<9 | 1<<12);
11147 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
11148 }
11149 if (phy->speed_cap_mask &
11150 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
11151 an_10_100_val |= (1<<6);
11152 autoneg_val |= (1<<9 | 1<<12);
11153 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
11154 }
11155 if (phy->speed_cap_mask &
11156 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
11157 an_10_100_val |= (1<<7);
11158 autoneg_val |= (1<<9 | 1<<12);
11159 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
11160 }
11161 if (phy->speed_cap_mask &
11162 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
11163 an_10_100_val |= (1<<8);
11164 autoneg_val |= (1<<9 | 1<<12);
11165 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
11166 }
11167 }
11168
11169
11170 if (phy->req_line_speed == SPEED_100) {
11171 autoneg_val |= (1<<13);
11172
11173 bnx2x_cl22_write(bp, phy,
11174 0x18,
11175 (1<<15 | 1<<9 | 7<<0));
11176 DP(NETIF_MSG_LINK, "Setting 100M force\n");
11177 }
11178 if (phy->req_line_speed == SPEED_10) {
11179
11180 bnx2x_cl22_write(bp, phy,
11181 0x18,
11182 (1<<15 | 1<<9 | 7<<0));
11183 DP(NETIF_MSG_LINK, "Setting 10M force\n");
11184 }
11185
11186 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
11187 int rc;
11188
11189 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
11190 MDIO_REG_GPHY_EXP_ACCESS_TOP |
11191 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
11192 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
11193 temp &= 0xfffe;
11194 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
11195
11196 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
11197 if (rc) {
11198 DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
11199 bnx2x_eee_disable(phy, params, vars);
11200 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
11201 (phy->req_duplex == DUPLEX_FULL) &&
11202 (bnx2x_eee_calc_timer(params) ||
11203 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
11204
11205
11206
11207
11208
11209 bnx2x_eee_advertise(phy, params, vars,
11210 SHMEM_EEE_1G_ADV);
11211 } else {
11212 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
11213 bnx2x_eee_disable(phy, params, vars);
11214 }
11215 } else {
11216 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
11217 SHMEM_EEE_SUPPORTED_SHIFT;
11218
11219 if (phy->flags & FLAGS_EEE) {
11220
11221 if (params->feature_config_flags &
11222 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
11223 temp = 6;
11224 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
11225 } else {
11226 temp = 0;
11227 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
11228 }
11229 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
11230 MDIO_AN_REG_EEE_ADV, temp);
11231 }
11232 }
11233
11234 bnx2x_cl22_write(bp, phy,
11235 0x04,
11236 an_10_100_val | fc_val);
11237
11238 if (phy->req_duplex == DUPLEX_FULL)
11239 autoneg_val |= (1<<8);
11240
11241 bnx2x_cl22_write(bp, phy,
11242 MDIO_PMA_REG_CTRL, autoneg_val);
11243
11244 return 0;
11245 }
11246
11247
11248 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
11249 struct link_params *params, u8 mode)
11250 {
11251 struct bnx2x *bp = params->bp;
11252 u16 temp;
11253
11254 bnx2x_cl22_write(bp, phy,
11255 MDIO_REG_GPHY_SHADOW,
11256 MDIO_REG_GPHY_SHADOW_LED_SEL1);
11257 bnx2x_cl22_read(bp, phy,
11258 MDIO_REG_GPHY_SHADOW,
11259 &temp);
11260 temp &= 0xff00;
11261
11262 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
11263 switch (mode) {
11264 case LED_MODE_FRONT_PANEL_OFF:
11265 case LED_MODE_OFF:
11266 temp |= 0x00ee;
11267 break;
11268 case LED_MODE_OPER:
11269 temp |= 0x0001;
11270 break;
11271 case LED_MODE_ON:
11272 temp |= 0x00ff;
11273 break;
11274 default:
11275 break;
11276 }
11277 bnx2x_cl22_write(bp, phy,
11278 MDIO_REG_GPHY_SHADOW,
11279 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11280 return;
11281 }
11282
11283
11284 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
11285 struct link_params *params)
11286 {
11287 struct bnx2x *bp = params->bp;
11288 u32 cfg_pin;
11289 u8 port;
11290
11291
11292
11293
11294 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
11295
11296
11297
11298 port = params->port;
11299 cfg_pin = (REG_RD(bp, params->shmem_base +
11300 offsetof(struct shmem_region,
11301 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11302 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11303 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11304
11305
11306 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
11307 }
11308
11309 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
11310 struct link_params *params,
11311 struct link_vars *vars)
11312 {
11313 struct bnx2x *bp = params->bp;
11314 u16 val;
11315 u8 link_up = 0;
11316 u16 legacy_status, legacy_speed;
11317
11318
11319 bnx2x_cl22_read(bp, phy,
11320 MDIO_REG_GPHY_AUX_STATUS,
11321 &legacy_status);
11322 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
11323
11324
11325 bnx2x_cl22_read(bp, phy,
11326 MDIO_REG_INTR_STATUS,
11327 &val);
11328
11329 link_up = ((legacy_status & (1<<2)) == (1<<2));
11330
11331 if (link_up) {
11332 legacy_speed = (legacy_status & (7<<8));
11333 if (legacy_speed == (7<<8)) {
11334 vars->line_speed = SPEED_1000;
11335 vars->duplex = DUPLEX_FULL;
11336 } else if (legacy_speed == (6<<8)) {
11337 vars->line_speed = SPEED_1000;
11338 vars->duplex = DUPLEX_HALF;
11339 } else if (legacy_speed == (5<<8)) {
11340 vars->line_speed = SPEED_100;
11341 vars->duplex = DUPLEX_FULL;
11342 }
11343
11344 else if (legacy_speed == (3<<8)) {
11345 vars->line_speed = SPEED_100;
11346 vars->duplex = DUPLEX_HALF;
11347 } else if (legacy_speed == (2<<8)) {
11348 vars->line_speed = SPEED_10;
11349 vars->duplex = DUPLEX_FULL;
11350 } else if (legacy_speed == (1<<8)) {
11351 vars->line_speed = SPEED_10;
11352 vars->duplex = DUPLEX_HALF;
11353 } else
11354 vars->line_speed = 0;
11355
11356 DP(NETIF_MSG_LINK,
11357 "Link is up in %dMbps, is_duplex_full= %d\n",
11358 vars->line_speed,
11359 (vars->duplex == DUPLEX_FULL));
11360
11361
11362 bnx2x_cl22_read(bp, phy,
11363 0x01,
11364 &val);
11365 if (val & (1<<5))
11366 vars->link_status |=
11367 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11368 bnx2x_cl22_read(bp, phy,
11369 0x06,
11370 &val);
11371 if ((val & (1<<0)) == 0)
11372 vars->link_status |=
11373 LINK_STATUS_PARALLEL_DETECTION_USED;
11374
11375 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11376 vars->line_speed);
11377
11378 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11379
11380 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11381
11382 bnx2x_cl22_read(bp, phy, 0x5, &val);
11383
11384 if (val & (1<<5))
11385 vars->link_status |=
11386 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11387 if (val & (1<<6))
11388 vars->link_status |=
11389 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11390 if (val & (1<<7))
11391 vars->link_status |=
11392 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11393 if (val & (1<<8))
11394 vars->link_status |=
11395 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11396 if (val & (1<<9))
11397 vars->link_status |=
11398 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11399
11400 bnx2x_cl22_read(bp, phy, 0xa, &val);
11401 if (val & (1<<10))
11402 vars->link_status |=
11403 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11404 if (val & (1<<11))
11405 vars->link_status |=
11406 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11407
11408 if ((phy->flags & FLAGS_EEE) &&
11409 bnx2x_eee_has_cap(params))
11410 bnx2x_eee_an_resolve(phy, params, vars);
11411 }
11412 }
11413 return link_up;
11414 }
11415
11416 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11417 struct link_params *params)
11418 {
11419 struct bnx2x *bp = params->bp;
11420 u16 val;
11421 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11422
11423 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11424
11425
11426
11427 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11428
11429
11430
11431
11432
11433
11434 bnx2x_cl22_read(bp, phy, 0x00, &val);
11435 val &= ~((1<<6) | (1<<12) | (1<<13));
11436 val |= (1<<6) | (1<<8);
11437 bnx2x_cl22_write(bp, phy, 0x00, val);
11438
11439
11440
11441
11442
11443 bnx2x_cl22_write(bp, phy, 0x18, 7);
11444 bnx2x_cl22_read(bp, phy, 0x18, &val);
11445 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11446
11447
11448 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11449
11450
11451
11452
11453 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11454 }
11455
11456
11457
11458
11459 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11460 struct link_params *params)
11461 {
11462 struct bnx2x *bp = params->bp;
11463
11464 bnx2x_cl45_write(bp, phy,
11465 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11466 }
11467
11468 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11469 struct link_params *params,
11470 struct link_vars *vars)
11471 {
11472 u16 fw_ver1, fw_ver2, val;
11473 struct bnx2x *bp = params->bp;
11474 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11475
11476
11477 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11478 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11479
11480 bnx2x_ext_phy_hw_reset(bp, params->port);
11481 bnx2x_wait_reset_complete(bp, phy, params);
11482
11483 bnx2x_cl45_write(bp, phy,
11484 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11485 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11486 bnx2x_cl45_write(bp, phy,
11487 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11488
11489 bnx2x_ext_phy_set_pause(params, phy, vars);
11490
11491 bnx2x_cl45_read(bp, phy,
11492 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11493 val |= 0x200;
11494 bnx2x_cl45_write(bp, phy,
11495 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11496
11497
11498 bnx2x_cl45_read(bp, phy,
11499 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11500
11501 bnx2x_cl45_read(bp, phy,
11502 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11503 bnx2x_save_spirom_version(bp, params->port,
11504 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11505 return 0;
11506 }
11507
11508 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11509 struct link_params *params,
11510 struct link_vars *vars)
11511 {
11512 struct bnx2x *bp = params->bp;
11513 u8 link_up;
11514 u16 val1, val2;
11515 bnx2x_cl45_read(bp, phy,
11516 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11517 bnx2x_cl45_read(bp, phy,
11518 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11519 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11520 val2, val1);
11521 bnx2x_cl45_read(bp, phy,
11522 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11523 bnx2x_cl45_read(bp, phy,
11524 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11525 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11526 val2, val1);
11527 link_up = ((val1 & 4) == 4);
11528
11529 if (link_up) {
11530 bnx2x_cl45_read(bp, phy,
11531 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11532 &val2);
11533 vars->line_speed = SPEED_10000;
11534 vars->duplex = DUPLEX_FULL;
11535 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11536 val2, (val2 & (1<<14)));
11537 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11538 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11539
11540
11541 if (val2 & (1<<11))
11542 vars->link_status |=
11543 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11544 }
11545 return link_up;
11546 }
11547
11548 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11549 {
11550 if (*len < 5)
11551 return -EINVAL;
11552 str[0] = (spirom_ver & 0xFF);
11553 str[1] = (spirom_ver & 0xFF00) >> 8;
11554 str[2] = (spirom_ver & 0xFF0000) >> 16;
11555 str[3] = (spirom_ver & 0xFF000000) >> 24;
11556 str[4] = '\0';
11557 *len -= 5;
11558 return 0;
11559 }
11560
11561 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11562 {
11563 u16 val, cnt;
11564
11565 bnx2x_cl45_read(bp, phy,
11566 MDIO_PMA_DEVAD,
11567 MDIO_PMA_REG_7101_RESET, &val);
11568
11569 for (cnt = 0; cnt < 10; cnt++) {
11570 msleep(50);
11571
11572 bnx2x_cl45_write(bp, phy,
11573 MDIO_PMA_DEVAD,
11574 MDIO_PMA_REG_7101_RESET,
11575 (val | (1<<15)));
11576
11577 bnx2x_cl45_read(bp, phy,
11578 MDIO_PMA_DEVAD,
11579 MDIO_PMA_REG_7101_RESET, &val);
11580
11581 if ((val & (1<<15)) == 0)
11582 break;
11583 }
11584 }
11585
11586 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11587 struct link_params *params) {
11588
11589 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11590 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11591
11592 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11593 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11594 }
11595
11596 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11597 struct link_params *params, u8 mode)
11598 {
11599 u16 val = 0;
11600 struct bnx2x *bp = params->bp;
11601 switch (mode) {
11602 case LED_MODE_FRONT_PANEL_OFF:
11603 case LED_MODE_OFF:
11604 val = 2;
11605 break;
11606 case LED_MODE_ON:
11607 val = 1;
11608 break;
11609 case LED_MODE_OPER:
11610 val = 0;
11611 break;
11612 }
11613 bnx2x_cl45_write(bp, phy,
11614 MDIO_PMA_DEVAD,
11615 MDIO_PMA_REG_7107_LINK_LED_CNTL,
11616 val);
11617 }
11618
11619
11620
11621
11622
11623 static const struct bnx2x_phy phy_null = {
11624 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11625 .addr = 0,
11626 .def_md_devad = 0,
11627 .flags = FLAGS_INIT_XGXS_FIRST,
11628 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11629 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11630 .mdio_ctrl = 0,
11631 .supported = 0,
11632 .media_type = ETH_PHY_NOT_PRESENT,
11633 .ver_addr = 0,
11634 .req_flow_ctrl = 0,
11635 .req_line_speed = 0,
11636 .speed_cap_mask = 0,
11637 .req_duplex = 0,
11638 .rsrv = 0,
11639 .config_init = (config_init_t)NULL,
11640 .read_status = (read_status_t)NULL,
11641 .link_reset = (link_reset_t)NULL,
11642 .config_loopback = (config_loopback_t)NULL,
11643 .format_fw_ver = (format_fw_ver_t)NULL,
11644 .hw_reset = (hw_reset_t)NULL,
11645 .set_link_led = (set_link_led_t)NULL,
11646 .phy_specific_func = (phy_specific_func_t)NULL
11647 };
11648
11649 static const struct bnx2x_phy phy_serdes = {
11650 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11651 .addr = 0xff,
11652 .def_md_devad = 0,
11653 .flags = 0,
11654 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11655 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11656 .mdio_ctrl = 0,
11657 .supported = (SUPPORTED_10baseT_Half |
11658 SUPPORTED_10baseT_Full |
11659 SUPPORTED_100baseT_Half |
11660 SUPPORTED_100baseT_Full |
11661 SUPPORTED_1000baseT_Full |
11662 SUPPORTED_2500baseX_Full |
11663 SUPPORTED_TP |
11664 SUPPORTED_Autoneg |
11665 SUPPORTED_Pause |
11666 SUPPORTED_Asym_Pause),
11667 .media_type = ETH_PHY_BASE_T,
11668 .ver_addr = 0,
11669 .req_flow_ctrl = 0,
11670 .req_line_speed = 0,
11671 .speed_cap_mask = 0,
11672 .req_duplex = 0,
11673 .rsrv = 0,
11674 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11675 .read_status = (read_status_t)bnx2x_link_settings_status,
11676 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11677 .config_loopback = (config_loopback_t)NULL,
11678 .format_fw_ver = (format_fw_ver_t)NULL,
11679 .hw_reset = (hw_reset_t)NULL,
11680 .set_link_led = (set_link_led_t)NULL,
11681 .phy_specific_func = (phy_specific_func_t)NULL
11682 };
11683
11684 static const struct bnx2x_phy phy_xgxs = {
11685 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11686 .addr = 0xff,
11687 .def_md_devad = 0,
11688 .flags = 0,
11689 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11690 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11691 .mdio_ctrl = 0,
11692 .supported = (SUPPORTED_10baseT_Half |
11693 SUPPORTED_10baseT_Full |
11694 SUPPORTED_100baseT_Half |
11695 SUPPORTED_100baseT_Full |
11696 SUPPORTED_1000baseT_Full |
11697 SUPPORTED_2500baseX_Full |
11698 SUPPORTED_10000baseT_Full |
11699 SUPPORTED_FIBRE |
11700 SUPPORTED_Autoneg |
11701 SUPPORTED_Pause |
11702 SUPPORTED_Asym_Pause),
11703 .media_type = ETH_PHY_CX4,
11704 .ver_addr = 0,
11705 .req_flow_ctrl = 0,
11706 .req_line_speed = 0,
11707 .speed_cap_mask = 0,
11708 .req_duplex = 0,
11709 .rsrv = 0,
11710 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11711 .read_status = (read_status_t)bnx2x_link_settings_status,
11712 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11713 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11714 .format_fw_ver = (format_fw_ver_t)NULL,
11715 .hw_reset = (hw_reset_t)NULL,
11716 .set_link_led = (set_link_led_t)NULL,
11717 .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11718 };
11719 static const struct bnx2x_phy phy_warpcore = {
11720 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11721 .addr = 0xff,
11722 .def_md_devad = 0,
11723 .flags = FLAGS_TX_ERROR_CHECK,
11724 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11725 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11726 .mdio_ctrl = 0,
11727 .supported = (SUPPORTED_10baseT_Half |
11728 SUPPORTED_10baseT_Full |
11729 SUPPORTED_100baseT_Half |
11730 SUPPORTED_100baseT_Full |
11731 SUPPORTED_1000baseT_Full |
11732 SUPPORTED_1000baseKX_Full |
11733 SUPPORTED_10000baseT_Full |
11734 SUPPORTED_10000baseKR_Full |
11735 SUPPORTED_20000baseKR2_Full |
11736 SUPPORTED_20000baseMLD2_Full |
11737 SUPPORTED_FIBRE |
11738 SUPPORTED_Autoneg |
11739 SUPPORTED_Pause |
11740 SUPPORTED_Asym_Pause),
11741 .media_type = ETH_PHY_UNSPECIFIED,
11742 .ver_addr = 0,
11743 .req_flow_ctrl = 0,
11744 .req_line_speed = 0,
11745 .speed_cap_mask = 0,
11746 0,
11747 0,
11748 .config_init = (config_init_t)bnx2x_warpcore_config_init,
11749 .read_status = (read_status_t)bnx2x_warpcore_read_status,
11750 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
11751 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11752 .format_fw_ver = (format_fw_ver_t)NULL,
11753 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
11754 .set_link_led = (set_link_led_t)NULL,
11755 .phy_specific_func = (phy_specific_func_t)NULL
11756 };
11757
11758
11759 static const struct bnx2x_phy phy_7101 = {
11760 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11761 .addr = 0xff,
11762 .def_md_devad = 0,
11763 .flags = FLAGS_FAN_FAILURE_DET_REQ,
11764 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11765 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11766 .mdio_ctrl = 0,
11767 .supported = (SUPPORTED_10000baseT_Full |
11768 SUPPORTED_TP |
11769 SUPPORTED_Autoneg |
11770 SUPPORTED_Pause |
11771 SUPPORTED_Asym_Pause),
11772 .media_type = ETH_PHY_BASE_T,
11773 .ver_addr = 0,
11774 .req_flow_ctrl = 0,
11775 .req_line_speed = 0,
11776 .speed_cap_mask = 0,
11777 .req_duplex = 0,
11778 .rsrv = 0,
11779 .config_init = (config_init_t)bnx2x_7101_config_init,
11780 .read_status = (read_status_t)bnx2x_7101_read_status,
11781 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11782 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11783 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
11784 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
11785 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
11786 .phy_specific_func = (phy_specific_func_t)NULL
11787 };
11788 static const struct bnx2x_phy phy_8073 = {
11789 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11790 .addr = 0xff,
11791 .def_md_devad = 0,
11792 .flags = 0,
11793 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11794 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11795 .mdio_ctrl = 0,
11796 .supported = (SUPPORTED_10000baseT_Full |
11797 SUPPORTED_2500baseX_Full |
11798 SUPPORTED_1000baseT_Full |
11799 SUPPORTED_FIBRE |
11800 SUPPORTED_Autoneg |
11801 SUPPORTED_Pause |
11802 SUPPORTED_Asym_Pause),
11803 .media_type = ETH_PHY_KR,
11804 .ver_addr = 0,
11805 .req_flow_ctrl = 0,
11806 .req_line_speed = 0,
11807 .speed_cap_mask = 0,
11808 .req_duplex = 0,
11809 .rsrv = 0,
11810 .config_init = (config_init_t)bnx2x_8073_config_init,
11811 .read_status = (read_status_t)bnx2x_8073_read_status,
11812 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
11813 .config_loopback = (config_loopback_t)NULL,
11814 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11815 .hw_reset = (hw_reset_t)NULL,
11816 .set_link_led = (set_link_led_t)NULL,
11817 .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11818 };
11819 static const struct bnx2x_phy phy_8705 = {
11820 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11821 .addr = 0xff,
11822 .def_md_devad = 0,
11823 .flags = FLAGS_INIT_XGXS_FIRST,
11824 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11825 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11826 .mdio_ctrl = 0,
11827 .supported = (SUPPORTED_10000baseT_Full |
11828 SUPPORTED_FIBRE |
11829 SUPPORTED_Pause |
11830 SUPPORTED_Asym_Pause),
11831 .media_type = ETH_PHY_XFP_FIBER,
11832 .ver_addr = 0,
11833 .req_flow_ctrl = 0,
11834 .req_line_speed = 0,
11835 .speed_cap_mask = 0,
11836 .req_duplex = 0,
11837 .rsrv = 0,
11838 .config_init = (config_init_t)bnx2x_8705_config_init,
11839 .read_status = (read_status_t)bnx2x_8705_read_status,
11840 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11841 .config_loopback = (config_loopback_t)NULL,
11842 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
11843 .hw_reset = (hw_reset_t)NULL,
11844 .set_link_led = (set_link_led_t)NULL,
11845 .phy_specific_func = (phy_specific_func_t)NULL
11846 };
11847 static const struct bnx2x_phy phy_8706 = {
11848 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11849 .addr = 0xff,
11850 .def_md_devad = 0,
11851 .flags = FLAGS_INIT_XGXS_FIRST,
11852 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11853 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11854 .mdio_ctrl = 0,
11855 .supported = (SUPPORTED_10000baseT_Full |
11856 SUPPORTED_1000baseT_Full |
11857 SUPPORTED_FIBRE |
11858 SUPPORTED_Pause |
11859 SUPPORTED_Asym_Pause),
11860 .media_type = ETH_PHY_SFPP_10G_FIBER,
11861 .ver_addr = 0,
11862 .req_flow_ctrl = 0,
11863 .req_line_speed = 0,
11864 .speed_cap_mask = 0,
11865 .req_duplex = 0,
11866 .rsrv = 0,
11867 .config_init = (config_init_t)bnx2x_8706_config_init,
11868 .read_status = (read_status_t)bnx2x_8706_read_status,
11869 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11870 .config_loopback = (config_loopback_t)NULL,
11871 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11872 .hw_reset = (hw_reset_t)NULL,
11873 .set_link_led = (set_link_led_t)NULL,
11874 .phy_specific_func = (phy_specific_func_t)NULL
11875 };
11876
11877 static const struct bnx2x_phy phy_8726 = {
11878 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11879 .addr = 0xff,
11880 .def_md_devad = 0,
11881 .flags = (FLAGS_INIT_XGXS_FIRST |
11882 FLAGS_TX_ERROR_CHECK),
11883 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11884 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11885 .mdio_ctrl = 0,
11886 .supported = (SUPPORTED_10000baseT_Full |
11887 SUPPORTED_1000baseT_Full |
11888 SUPPORTED_Autoneg |
11889 SUPPORTED_FIBRE |
11890 SUPPORTED_Pause |
11891 SUPPORTED_Asym_Pause),
11892 .media_type = ETH_PHY_NOT_PRESENT,
11893 .ver_addr = 0,
11894 .req_flow_ctrl = 0,
11895 .req_line_speed = 0,
11896 .speed_cap_mask = 0,
11897 .req_duplex = 0,
11898 .rsrv = 0,
11899 .config_init = (config_init_t)bnx2x_8726_config_init,
11900 .read_status = (read_status_t)bnx2x_8726_read_status,
11901 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
11902 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11903 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11904 .hw_reset = (hw_reset_t)NULL,
11905 .set_link_led = (set_link_led_t)NULL,
11906 .phy_specific_func = (phy_specific_func_t)NULL
11907 };
11908
11909 static const struct bnx2x_phy phy_8727 = {
11910 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11911 .addr = 0xff,
11912 .def_md_devad = 0,
11913 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11914 FLAGS_TX_ERROR_CHECK),
11915 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11916 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11917 .mdio_ctrl = 0,
11918 .supported = (SUPPORTED_10000baseT_Full |
11919 SUPPORTED_1000baseT_Full |
11920 SUPPORTED_FIBRE |
11921 SUPPORTED_Pause |
11922 SUPPORTED_Asym_Pause),
11923 .media_type = ETH_PHY_NOT_PRESENT,
11924 .ver_addr = 0,
11925 .req_flow_ctrl = 0,
11926 .req_line_speed = 0,
11927 .speed_cap_mask = 0,
11928 .req_duplex = 0,
11929 .rsrv = 0,
11930 .config_init = (config_init_t)bnx2x_8727_config_init,
11931 .read_status = (read_status_t)bnx2x_8727_read_status,
11932 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
11933 .config_loopback = (config_loopback_t)NULL,
11934 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11935 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
11936 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
11937 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11938 };
11939 static const struct bnx2x_phy phy_8481 = {
11940 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11941 .addr = 0xff,
11942 .def_md_devad = 0,
11943 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11944 FLAGS_REARM_LATCH_SIGNAL,
11945 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11946 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11947 .mdio_ctrl = 0,
11948 .supported = (SUPPORTED_10baseT_Half |
11949 SUPPORTED_10baseT_Full |
11950 SUPPORTED_100baseT_Half |
11951 SUPPORTED_100baseT_Full |
11952 SUPPORTED_1000baseT_Full |
11953 SUPPORTED_10000baseT_Full |
11954 SUPPORTED_TP |
11955 SUPPORTED_Autoneg |
11956 SUPPORTED_Pause |
11957 SUPPORTED_Asym_Pause),
11958 .media_type = ETH_PHY_BASE_T,
11959 .ver_addr = 0,
11960 .req_flow_ctrl = 0,
11961 .req_line_speed = 0,
11962 .speed_cap_mask = 0,
11963 .req_duplex = 0,
11964 .rsrv = 0,
11965 .config_init = (config_init_t)bnx2x_8481_config_init,
11966 .read_status = (read_status_t)bnx2x_848xx_read_status,
11967 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
11968 .config_loopback = (config_loopback_t)NULL,
11969 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11970 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
11971 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11972 .phy_specific_func = (phy_specific_func_t)NULL
11973 };
11974
11975 static const struct bnx2x_phy phy_84823 = {
11976 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11977 .addr = 0xff,
11978 .def_md_devad = 0,
11979 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
11980 FLAGS_REARM_LATCH_SIGNAL |
11981 FLAGS_TX_ERROR_CHECK),
11982 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11983 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11984 .mdio_ctrl = 0,
11985 .supported = (SUPPORTED_10baseT_Half |
11986 SUPPORTED_10baseT_Full |
11987 SUPPORTED_100baseT_Half |
11988 SUPPORTED_100baseT_Full |
11989 SUPPORTED_1000baseT_Full |
11990 SUPPORTED_10000baseT_Full |
11991 SUPPORTED_TP |
11992 SUPPORTED_Autoneg |
11993 SUPPORTED_Pause |
11994 SUPPORTED_Asym_Pause),
11995 .media_type = ETH_PHY_BASE_T,
11996 .ver_addr = 0,
11997 .req_flow_ctrl = 0,
11998 .req_line_speed = 0,
11999 .speed_cap_mask = 0,
12000 .req_duplex = 0,
12001 .rsrv = 0,
12002 .config_init = (config_init_t)bnx2x_848x3_config_init,
12003 .read_status = (read_status_t)bnx2x_848xx_read_status,
12004 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
12005 .config_loopback = (config_loopback_t)NULL,
12006 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
12007 .hw_reset = (hw_reset_t)NULL,
12008 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
12009 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12010 };
12011
12012 static const struct bnx2x_phy phy_84833 = {
12013 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
12014 .addr = 0xff,
12015 .def_md_devad = 0,
12016 .flags = (FLAGS_FAN_FAILURE_DET_REQ |
12017 FLAGS_REARM_LATCH_SIGNAL |
12018 FLAGS_TX_ERROR_CHECK),
12019 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12020 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12021 .mdio_ctrl = 0,
12022 .supported = (SUPPORTED_100baseT_Half |
12023 SUPPORTED_100baseT_Full |
12024 SUPPORTED_1000baseT_Full |
12025 SUPPORTED_10000baseT_Full |
12026 SUPPORTED_TP |
12027 SUPPORTED_Autoneg |
12028 SUPPORTED_Pause |
12029 SUPPORTED_Asym_Pause),
12030 .media_type = ETH_PHY_BASE_T,
12031 .ver_addr = 0,
12032 .req_flow_ctrl = 0,
12033 .req_line_speed = 0,
12034 .speed_cap_mask = 0,
12035 .req_duplex = 0,
12036 .rsrv = 0,
12037 .config_init = (config_init_t)bnx2x_848x3_config_init,
12038 .read_status = (read_status_t)bnx2x_848xx_read_status,
12039 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
12040 .config_loopback = (config_loopback_t)NULL,
12041 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
12042 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
12043 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
12044 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12045 };
12046
12047 static const struct bnx2x_phy phy_84834 = {
12048 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
12049 .addr = 0xff,
12050 .def_md_devad = 0,
12051 .flags = FLAGS_FAN_FAILURE_DET_REQ |
12052 FLAGS_REARM_LATCH_SIGNAL,
12053 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12054 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12055 .mdio_ctrl = 0,
12056 .supported = (SUPPORTED_100baseT_Half |
12057 SUPPORTED_100baseT_Full |
12058 SUPPORTED_1000baseT_Full |
12059 SUPPORTED_10000baseT_Full |
12060 SUPPORTED_TP |
12061 SUPPORTED_Autoneg |
12062 SUPPORTED_Pause |
12063 SUPPORTED_Asym_Pause),
12064 .media_type = ETH_PHY_BASE_T,
12065 .ver_addr = 0,
12066 .req_flow_ctrl = 0,
12067 .req_line_speed = 0,
12068 .speed_cap_mask = 0,
12069 .req_duplex = 0,
12070 .rsrv = 0,
12071 .config_init = (config_init_t)bnx2x_848x3_config_init,
12072 .read_status = (read_status_t)bnx2x_848xx_read_status,
12073 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
12074 .config_loopback = (config_loopback_t)NULL,
12075 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
12076 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
12077 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
12078 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12079 };
12080
12081 static const struct bnx2x_phy phy_84858 = {
12082 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858,
12083 .addr = 0xff,
12084 .def_md_devad = 0,
12085 .flags = FLAGS_FAN_FAILURE_DET_REQ |
12086 FLAGS_REARM_LATCH_SIGNAL,
12087 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12088 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12089 .mdio_ctrl = 0,
12090 .supported = (SUPPORTED_100baseT_Half |
12091 SUPPORTED_100baseT_Full |
12092 SUPPORTED_1000baseT_Full |
12093 SUPPORTED_10000baseT_Full |
12094 SUPPORTED_TP |
12095 SUPPORTED_Autoneg |
12096 SUPPORTED_Pause |
12097 SUPPORTED_Asym_Pause),
12098 .media_type = ETH_PHY_BASE_T,
12099 .ver_addr = 0,
12100 .req_flow_ctrl = 0,
12101 .req_line_speed = 0,
12102 .speed_cap_mask = 0,
12103 .req_duplex = 0,
12104 .rsrv = 0,
12105 .config_init = (config_init_t)bnx2x_848x3_config_init,
12106 .read_status = (read_status_t)bnx2x_848xx_read_status,
12107 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
12108 .config_loopback = (config_loopback_t)NULL,
12109 .format_fw_ver = (format_fw_ver_t)bnx2x_8485x_format_ver,
12110 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
12111 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
12112 .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12113 };
12114
12115 static const struct bnx2x_phy phy_54618se = {
12116 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
12117 .addr = 0xff,
12118 .def_md_devad = 0,
12119 .flags = FLAGS_INIT_XGXS_FIRST,
12120 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12121 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12122 .mdio_ctrl = 0,
12123 .supported = (SUPPORTED_10baseT_Half |
12124 SUPPORTED_10baseT_Full |
12125 SUPPORTED_100baseT_Half |
12126 SUPPORTED_100baseT_Full |
12127 SUPPORTED_1000baseT_Full |
12128 SUPPORTED_TP |
12129 SUPPORTED_Autoneg |
12130 SUPPORTED_Pause |
12131 SUPPORTED_Asym_Pause),
12132 .media_type = ETH_PHY_BASE_T,
12133 .ver_addr = 0,
12134 .req_flow_ctrl = 0,
12135 .req_line_speed = 0,
12136 .speed_cap_mask = 0,
12137 0,
12138 0,
12139 .config_init = (config_init_t)bnx2x_54618se_config_init,
12140 .read_status = (read_status_t)bnx2x_54618se_read_status,
12141 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
12142 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
12143 .format_fw_ver = (format_fw_ver_t)NULL,
12144 .hw_reset = (hw_reset_t)NULL,
12145 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led,
12146 .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
12147 };
12148
12149
12150
12151
12152
12153
12154 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
12155 struct bnx2x_phy *phy, u8 port,
12156 u8 phy_index)
12157 {
12158
12159 u32 rx = 0, tx = 0, i;
12160 for (i = 0; i < 2; i++) {
12161
12162
12163
12164
12165 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
12166 rx = REG_RD(bp, shmem_base +
12167 offsetof(struct shmem_region,
12168 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
12169
12170 tx = REG_RD(bp, shmem_base +
12171 offsetof(struct shmem_region,
12172 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
12173 } else {
12174 rx = REG_RD(bp, shmem_base +
12175 offsetof(struct shmem_region,
12176 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12177
12178 tx = REG_RD(bp, shmem_base +
12179 offsetof(struct shmem_region,
12180 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12181 }
12182
12183 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
12184 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
12185
12186 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
12187 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
12188 }
12189 }
12190
12191 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
12192 u8 phy_index, u8 port)
12193 {
12194 u32 ext_phy_config = 0;
12195 switch (phy_index) {
12196 case EXT_PHY1:
12197 ext_phy_config = REG_RD(bp, shmem_base +
12198 offsetof(struct shmem_region,
12199 dev_info.port_hw_config[port].external_phy_config));
12200 break;
12201 case EXT_PHY2:
12202 ext_phy_config = REG_RD(bp, shmem_base +
12203 offsetof(struct shmem_region,
12204 dev_info.port_hw_config[port].external_phy_config2));
12205 break;
12206 default:
12207 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
12208 return -EINVAL;
12209 }
12210
12211 return ext_phy_config;
12212 }
12213 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
12214 struct bnx2x_phy *phy)
12215 {
12216 u32 phy_addr;
12217 u32 chip_id;
12218 u32 switch_cfg = (REG_RD(bp, shmem_base +
12219 offsetof(struct shmem_region,
12220 dev_info.port_feature_config[port].link_config)) &
12221 PORT_FEATURE_CONNECTED_SWITCH_MASK);
12222 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
12223 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
12224
12225 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
12226 if (USES_WARPCORE(bp)) {
12227 u32 serdes_net_if;
12228 phy_addr = REG_RD(bp,
12229 MISC_REG_WC0_CTRL_PHY_ADDR);
12230 *phy = phy_warpcore;
12231 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
12232 phy->flags |= FLAGS_4_PORT_MODE;
12233 else
12234 phy->flags &= ~FLAGS_4_PORT_MODE;
12235
12236 serdes_net_if = (REG_RD(bp, shmem_base +
12237 offsetof(struct shmem_region, dev_info.
12238 port_hw_config[port].default_cfg)) &
12239 PORT_HW_CFG_NET_SERDES_IF_MASK);
12240
12241
12242
12243 switch (serdes_net_if) {
12244 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
12245 phy->supported &= (SUPPORTED_10baseT_Half |
12246 SUPPORTED_10baseT_Full |
12247 SUPPORTED_100baseT_Half |
12248 SUPPORTED_100baseT_Full |
12249 SUPPORTED_1000baseT_Full |
12250 SUPPORTED_FIBRE |
12251 SUPPORTED_Autoneg |
12252 SUPPORTED_Pause |
12253 SUPPORTED_Asym_Pause);
12254 phy->media_type = ETH_PHY_BASE_T;
12255 break;
12256 case PORT_HW_CFG_NET_SERDES_IF_XFI:
12257 phy->supported &= (SUPPORTED_1000baseT_Full |
12258 SUPPORTED_10000baseT_Full |
12259 SUPPORTED_FIBRE |
12260 SUPPORTED_Pause |
12261 SUPPORTED_Asym_Pause);
12262 phy->media_type = ETH_PHY_XFP_FIBER;
12263 break;
12264 case PORT_HW_CFG_NET_SERDES_IF_SFI:
12265 phy->supported &= (SUPPORTED_1000baseT_Full |
12266 SUPPORTED_10000baseT_Full |
12267 SUPPORTED_FIBRE |
12268 SUPPORTED_Pause |
12269 SUPPORTED_Asym_Pause);
12270 phy->media_type = ETH_PHY_SFPP_10G_FIBER;
12271 break;
12272 case PORT_HW_CFG_NET_SERDES_IF_KR:
12273 phy->media_type = ETH_PHY_KR;
12274 phy->supported &= (SUPPORTED_1000baseKX_Full |
12275 SUPPORTED_10000baseKR_Full |
12276 SUPPORTED_FIBRE |
12277 SUPPORTED_Autoneg |
12278 SUPPORTED_Pause |
12279 SUPPORTED_Asym_Pause);
12280 break;
12281 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
12282 phy->media_type = ETH_PHY_KR;
12283 phy->flags |= FLAGS_WC_DUAL_MODE;
12284 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
12285 SUPPORTED_FIBRE |
12286 SUPPORTED_Pause |
12287 SUPPORTED_Asym_Pause);
12288 break;
12289 case PORT_HW_CFG_NET_SERDES_IF_KR2:
12290 phy->media_type = ETH_PHY_KR;
12291 phy->flags |= FLAGS_WC_DUAL_MODE;
12292 phy->supported &= (SUPPORTED_20000baseKR2_Full |
12293 SUPPORTED_10000baseKR_Full |
12294 SUPPORTED_1000baseKX_Full |
12295 SUPPORTED_Autoneg |
12296 SUPPORTED_FIBRE |
12297 SUPPORTED_Pause |
12298 SUPPORTED_Asym_Pause);
12299 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12300 break;
12301 default:
12302 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
12303 serdes_net_if);
12304 break;
12305 }
12306
12307
12308
12309
12310
12311 if (CHIP_REV(bp) == CHIP_REV_Ax)
12312 phy->flags |= FLAGS_MDC_MDIO_WA;
12313 else
12314 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
12315 } else {
12316 switch (switch_cfg) {
12317 case SWITCH_CFG_1G:
12318 phy_addr = REG_RD(bp,
12319 NIG_REG_SERDES0_CTRL_PHY_ADDR +
12320 port * 0x10);
12321 *phy = phy_serdes;
12322 break;
12323 case SWITCH_CFG_10G:
12324 phy_addr = REG_RD(bp,
12325 NIG_REG_XGXS0_CTRL_PHY_ADDR +
12326 port * 0x18);
12327 *phy = phy_xgxs;
12328 break;
12329 default:
12330 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
12331 return -EINVAL;
12332 }
12333 }
12334 phy->addr = (u8)phy_addr;
12335 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
12336 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
12337 port);
12338 if (CHIP_IS_E2(bp))
12339 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
12340 else
12341 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
12342
12343 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12344 port, phy->addr, phy->mdio_ctrl);
12345
12346 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
12347 return 0;
12348 }
12349
12350 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
12351 u8 phy_index,
12352 u32 shmem_base,
12353 u32 shmem2_base,
12354 u8 port,
12355 struct bnx2x_phy *phy)
12356 {
12357 u32 ext_phy_config, phy_type, config2;
12358 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
12359 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
12360 phy_index, port);
12361 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12362
12363 switch (phy_type) {
12364 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12365 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12366 *phy = phy_8073;
12367 break;
12368 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12369 *phy = phy_8705;
12370 break;
12371 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12372 *phy = phy_8706;
12373 break;
12374 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12375 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12376 *phy = phy_8726;
12377 break;
12378 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12379
12380 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12381 *phy = phy_8727;
12382 phy->flags |= FLAGS_NOC;
12383 break;
12384 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12385 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12386 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12387 *phy = phy_8727;
12388 break;
12389 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12390 *phy = phy_8481;
12391 break;
12392 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12393 *phy = phy_84823;
12394 break;
12395 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12396 *phy = phy_84833;
12397 break;
12398 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12399 *phy = phy_84834;
12400 break;
12401 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
12402 *phy = phy_84858;
12403 break;
12404 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12405 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12406 *phy = phy_54618se;
12407 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12408 phy->flags |= FLAGS_EEE;
12409 break;
12410 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12411 *phy = phy_7101;
12412 break;
12413 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12414 *phy = phy_null;
12415 return -EINVAL;
12416 default:
12417 *phy = phy_null;
12418
12419 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12420 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12421 return -EINVAL;
12422 return 0;
12423 }
12424
12425 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12426 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12427
12428
12429
12430
12431
12432 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12433 dev_info.shared_hw_config.config2));
12434 if (phy_index == EXT_PHY1) {
12435 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12436 port_mb[port].ext_phy_fw_version);
12437
12438
12439 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12440 mdc_mdio_access = config2 &
12441 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12442 } else {
12443 u32 size = REG_RD(bp, shmem2_base);
12444
12445 if (size >
12446 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12447 phy->ver_addr = shmem2_base +
12448 offsetof(struct shmem2_region,
12449 ext_phy_fw_version2[port]);
12450 }
12451
12452 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12453 mdc_mdio_access = (config2 &
12454 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12455 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12456 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12457 }
12458 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12459
12460 if (bnx2x_is_8483x_8485x(phy) && (phy->ver_addr)) {
12461
12462
12463
12464 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12465 if (((raw_ver & 0x7F) <= 39) &&
12466 (((raw_ver & 0xF80) >> 7) <= 1))
12467 phy->supported &= ~(SUPPORTED_100baseT_Half |
12468 SUPPORTED_100baseT_Full);
12469 }
12470
12471 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12472 phy_type, port, phy_index);
12473 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
12474 phy->addr, phy->mdio_ctrl);
12475 return 0;
12476 }
12477
12478 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12479 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12480 {
12481 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12482 if (phy_index == INT_PHY)
12483 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12484
12485 return bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12486 port, phy);
12487 }
12488
12489 static void bnx2x_phy_def_cfg(struct link_params *params,
12490 struct bnx2x_phy *phy,
12491 u8 phy_index)
12492 {
12493 struct bnx2x *bp = params->bp;
12494 u32 link_config;
12495
12496 if (phy_index == EXT_PHY2) {
12497 link_config = REG_RD(bp, params->shmem_base +
12498 offsetof(struct shmem_region, dev_info.
12499 port_feature_config[params->port].link_config2));
12500 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12501 offsetof(struct shmem_region,
12502 dev_info.
12503 port_hw_config[params->port].speed_capability_mask2));
12504 } else {
12505 link_config = REG_RD(bp, params->shmem_base +
12506 offsetof(struct shmem_region, dev_info.
12507 port_feature_config[params->port].link_config));
12508 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12509 offsetof(struct shmem_region,
12510 dev_info.
12511 port_hw_config[params->port].speed_capability_mask));
12512 }
12513 DP(NETIF_MSG_LINK,
12514 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12515 phy_index, link_config, phy->speed_cap_mask);
12516
12517 phy->req_duplex = DUPLEX_FULL;
12518 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
12519 case PORT_FEATURE_LINK_SPEED_10M_HALF:
12520 phy->req_duplex = DUPLEX_HALF;
12521
12522 case PORT_FEATURE_LINK_SPEED_10M_FULL:
12523 phy->req_line_speed = SPEED_10;
12524 break;
12525 case PORT_FEATURE_LINK_SPEED_100M_HALF:
12526 phy->req_duplex = DUPLEX_HALF;
12527
12528 case PORT_FEATURE_LINK_SPEED_100M_FULL:
12529 phy->req_line_speed = SPEED_100;
12530 break;
12531 case PORT_FEATURE_LINK_SPEED_1G:
12532 phy->req_line_speed = SPEED_1000;
12533 break;
12534 case PORT_FEATURE_LINK_SPEED_2_5G:
12535 phy->req_line_speed = SPEED_2500;
12536 break;
12537 case PORT_FEATURE_LINK_SPEED_10G_CX4:
12538 phy->req_line_speed = SPEED_10000;
12539 break;
12540 default:
12541 phy->req_line_speed = SPEED_AUTO_NEG;
12542 break;
12543 }
12544
12545 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
12546 case PORT_FEATURE_FLOW_CONTROL_AUTO:
12547 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12548 break;
12549 case PORT_FEATURE_FLOW_CONTROL_TX:
12550 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12551 break;
12552 case PORT_FEATURE_FLOW_CONTROL_RX:
12553 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12554 break;
12555 case PORT_FEATURE_FLOW_CONTROL_BOTH:
12556 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12557 break;
12558 default:
12559 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12560 break;
12561 }
12562 }
12563
12564 u32 bnx2x_phy_selection(struct link_params *params)
12565 {
12566 u32 phy_config_swapped, prio_cfg;
12567 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12568
12569 phy_config_swapped = params->multi_phy_config &
12570 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12571
12572 prio_cfg = params->multi_phy_config &
12573 PORT_HW_CFG_PHY_SELECTION_MASK;
12574
12575 if (phy_config_swapped) {
12576 switch (prio_cfg) {
12577 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12578 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12579 break;
12580 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12581 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12582 break;
12583 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12584 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12585 break;
12586 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12587 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12588 break;
12589 }
12590 } else
12591 return_cfg = prio_cfg;
12592
12593 return return_cfg;
12594 }
12595
12596 int bnx2x_phy_probe(struct link_params *params)
12597 {
12598 u8 phy_index, actual_phy_idx;
12599 u32 phy_config_swapped, sync_offset, media_types;
12600 struct bnx2x *bp = params->bp;
12601 struct bnx2x_phy *phy;
12602 params->num_phys = 0;
12603 DP(NETIF_MSG_LINK, "Begin phy probe\n");
12604 phy_config_swapped = params->multi_phy_config &
12605 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12606
12607 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12608 phy_index++) {
12609 actual_phy_idx = phy_index;
12610 if (phy_config_swapped) {
12611 if (phy_index == EXT_PHY1)
12612 actual_phy_idx = EXT_PHY2;
12613 else if (phy_index == EXT_PHY2)
12614 actual_phy_idx = EXT_PHY1;
12615 }
12616 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12617 " actual_phy_idx %x\n", phy_config_swapped,
12618 phy_index, actual_phy_idx);
12619 phy = ¶ms->phy[actual_phy_idx];
12620 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12621 params->shmem2_base, params->port,
12622 phy) != 0) {
12623 params->num_phys = 0;
12624 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12625 phy_index);
12626 for (phy_index = INT_PHY;
12627 phy_index < MAX_PHYS;
12628 phy_index++)
12629 *phy = phy_null;
12630 return -EINVAL;
12631 }
12632 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12633 break;
12634
12635 if (params->feature_config_flags &
12636 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12637 phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12638
12639 if (!(params->feature_config_flags &
12640 FEATURE_CONFIG_MT_SUPPORT))
12641 phy->flags |= FLAGS_MDC_MDIO_WA_G;
12642
12643 sync_offset = params->shmem_base +
12644 offsetof(struct shmem_region,
12645 dev_info.port_hw_config[params->port].media_type);
12646 media_types = REG_RD(bp, sync_offset);
12647
12648
12649
12650
12651
12652 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12653 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12654 actual_phy_idx))) == 0) {
12655 media_types |= ((phy->media_type &
12656 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12657 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12658 actual_phy_idx));
12659 }
12660 REG_WR(bp, sync_offset, media_types);
12661
12662 bnx2x_phy_def_cfg(params, phy, phy_index);
12663 params->num_phys++;
12664 }
12665
12666 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12667 return 0;
12668 }
12669
12670 static void bnx2x_init_bmac_loopback(struct link_params *params,
12671 struct link_vars *vars)
12672 {
12673 struct bnx2x *bp = params->bp;
12674 vars->link_up = 1;
12675 vars->line_speed = SPEED_10000;
12676 vars->duplex = DUPLEX_FULL;
12677 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12678 vars->mac_type = MAC_TYPE_BMAC;
12679
12680 vars->phy_flags = PHY_XGXS_FLAG;
12681
12682 bnx2x_xgxs_deassert(params);
12683
12684
12685 bnx2x_bmac_enable(params, vars, 1, 1);
12686
12687 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12688 }
12689
12690 static void bnx2x_init_emac_loopback(struct link_params *params,
12691 struct link_vars *vars)
12692 {
12693 struct bnx2x *bp = params->bp;
12694 vars->link_up = 1;
12695 vars->line_speed = SPEED_1000;
12696 vars->duplex = DUPLEX_FULL;
12697 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12698 vars->mac_type = MAC_TYPE_EMAC;
12699
12700 vars->phy_flags = PHY_XGXS_FLAG;
12701
12702 bnx2x_xgxs_deassert(params);
12703
12704 bnx2x_emac_enable(params, vars, 1);
12705 bnx2x_emac_program(params, vars);
12706 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12707 }
12708
12709 static void bnx2x_init_xmac_loopback(struct link_params *params,
12710 struct link_vars *vars)
12711 {
12712 struct bnx2x *bp = params->bp;
12713 vars->link_up = 1;
12714 if (!params->req_line_speed[0])
12715 vars->line_speed = SPEED_10000;
12716 else
12717 vars->line_speed = params->req_line_speed[0];
12718 vars->duplex = DUPLEX_FULL;
12719 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12720 vars->mac_type = MAC_TYPE_XMAC;
12721 vars->phy_flags = PHY_XGXS_FLAG;
12722
12723
12724
12725 bnx2x_set_aer_mmd(params, ¶ms->phy[0]);
12726 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0);
12727 params->phy[INT_PHY].config_loopback(
12728 ¶ms->phy[INT_PHY],
12729 params);
12730
12731 bnx2x_xmac_enable(params, vars, 1);
12732 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12733 }
12734
12735 static void bnx2x_init_umac_loopback(struct link_params *params,
12736 struct link_vars *vars)
12737 {
12738 struct bnx2x *bp = params->bp;
12739 vars->link_up = 1;
12740 vars->line_speed = SPEED_1000;
12741 vars->duplex = DUPLEX_FULL;
12742 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12743 vars->mac_type = MAC_TYPE_UMAC;
12744 vars->phy_flags = PHY_XGXS_FLAG;
12745 bnx2x_umac_enable(params, vars, 1);
12746
12747 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12748 }
12749
12750 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12751 struct link_vars *vars)
12752 {
12753 struct bnx2x *bp = params->bp;
12754 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY];
12755 vars->link_up = 1;
12756 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12757 vars->duplex = DUPLEX_FULL;
12758 if (params->req_line_speed[0] == SPEED_1000)
12759 vars->line_speed = SPEED_1000;
12760 else if ((params->req_line_speed[0] == SPEED_20000) ||
12761 (int_phy->flags & FLAGS_WC_DUAL_MODE))
12762 vars->line_speed = SPEED_20000;
12763 else
12764 vars->line_speed = SPEED_10000;
12765
12766 if (!USES_WARPCORE(bp))
12767 bnx2x_xgxs_deassert(params);
12768 bnx2x_link_initialize(params, vars);
12769
12770 if (params->req_line_speed[0] == SPEED_1000) {
12771 if (USES_WARPCORE(bp))
12772 bnx2x_umac_enable(params, vars, 0);
12773 else {
12774 bnx2x_emac_program(params, vars);
12775 bnx2x_emac_enable(params, vars, 0);
12776 }
12777 } else {
12778 if (USES_WARPCORE(bp))
12779 bnx2x_xmac_enable(params, vars, 0);
12780 else
12781 bnx2x_bmac_enable(params, vars, 0, 1);
12782 }
12783
12784 if (params->loopback_mode == LOOPBACK_XGXS) {
12785
12786 int_phy->config_loopback(int_phy, params);
12787 } else {
12788
12789 u8 phy_index;
12790 for (phy_index = EXT_PHY1;
12791 phy_index < params->num_phys; phy_index++)
12792 if (params->phy[phy_index].config_loopback)
12793 params->phy[phy_index].config_loopback(
12794 ¶ms->phy[phy_index],
12795 params);
12796 }
12797 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12798
12799 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12800 }
12801
12802 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12803 {
12804 struct bnx2x *bp = params->bp;
12805 u8 val = en * 0x1F;
12806
12807
12808 if (!CHIP_IS_E1x(bp))
12809 val |= en * 0x20;
12810 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12811
12812 if (!CHIP_IS_E1(bp)) {
12813 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12814 en*0x3);
12815 }
12816
12817 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12818 NIG_REG_LLH0_BRB1_NOT_MCP), en);
12819 }
12820 static int bnx2x_avoid_link_flap(struct link_params *params,
12821 struct link_vars *vars)
12822 {
12823 u32 phy_idx;
12824 u32 dont_clear_stat, lfa_sts;
12825 struct bnx2x *bp = params->bp;
12826
12827 bnx2x_set_mdio_emac_per_phy(bp, params);
12828
12829 bnx2x_link_status_update(params, vars);
12830
12831
12832
12833
12834
12835
12836 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12837 struct bnx2x_phy *phy = ¶ms->phy[phy_idx];
12838 if (phy->phy_specific_func) {
12839 DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12840 phy->phy_specific_func(phy, params, PHY_INIT);
12841 }
12842 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12843 (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12844 (phy->media_type == ETH_PHY_DA_TWINAX))
12845 bnx2x_verify_sfp_module(phy, params);
12846 }
12847 lfa_sts = REG_RD(bp, params->lfa_base +
12848 offsetof(struct shmem_lfa,
12849 lfa_sts));
12850
12851 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12852
12853
12854 if (CHIP_IS_E3(bp)) {
12855 if (!dont_clear_stat) {
12856 REG_WR(bp, GRCBASE_MISC +
12857 MISC_REGISTERS_RESET_REG_2_CLEAR,
12858 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12859 params->port));
12860 REG_WR(bp, GRCBASE_MISC +
12861 MISC_REGISTERS_RESET_REG_2_SET,
12862 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12863 params->port));
12864 }
12865 if (vars->line_speed < SPEED_10000)
12866 bnx2x_umac_enable(params, vars, 0);
12867 else
12868 bnx2x_xmac_enable(params, vars, 0);
12869 } else {
12870 if (vars->line_speed < SPEED_10000)
12871 bnx2x_emac_enable(params, vars, 0);
12872 else
12873 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12874 }
12875
12876
12877 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12878 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12879 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12880 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12881
12882 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12883
12884 REG_WR(bp, params->lfa_base +
12885 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12886
12887
12888 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12889
12890
12891 bnx2x_link_int_enable(params);
12892 return 0;
12893 }
12894
12895 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12896 struct link_vars *vars,
12897 int lfa_status)
12898 {
12899 u32 lfa_sts, cfg_idx, tmp_val;
12900 struct bnx2x *bp = params->bp;
12901
12902 bnx2x_link_reset(params, vars, 1);
12903
12904 if (!params->lfa_base)
12905 return;
12906
12907 REG_WR(bp, params->lfa_base +
12908 offsetof(struct shmem_lfa, req_duplex),
12909 params->req_duplex[0] | (params->req_duplex[1] << 16));
12910
12911 REG_WR(bp, params->lfa_base +
12912 offsetof(struct shmem_lfa, req_flow_ctrl),
12913 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12914
12915 REG_WR(bp, params->lfa_base +
12916 offsetof(struct shmem_lfa, req_line_speed),
12917 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12918
12919 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12920 REG_WR(bp, params->lfa_base +
12921 offsetof(struct shmem_lfa,
12922 speed_cap_mask[cfg_idx]),
12923 params->speed_cap_mask[cfg_idx]);
12924 }
12925
12926 tmp_val = REG_RD(bp, params->lfa_base +
12927 offsetof(struct shmem_lfa, additional_config));
12928 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12929 tmp_val |= params->req_fc_auto_adv;
12930
12931 REG_WR(bp, params->lfa_base +
12932 offsetof(struct shmem_lfa, additional_config), tmp_val);
12933
12934 lfa_sts = REG_RD(bp, params->lfa_base +
12935 offsetof(struct shmem_lfa, lfa_sts));
12936
12937
12938 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12939
12940
12941 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12942 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12943 LFA_LINK_FLAP_REASON_OFFSET);
12944
12945
12946 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12947 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12948 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12949 << LINK_FLAP_COUNT_OFFSET));
12950 REG_WR(bp, params->lfa_base +
12951 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12952
12953 }
12954
12955 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12956 {
12957 int lfa_status;
12958 struct bnx2x *bp = params->bp;
12959 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12960 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12961 params->req_line_speed[0], params->req_flow_ctrl[0]);
12962 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12963 params->req_line_speed[1], params->req_flow_ctrl[1]);
12964 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12965 vars->link_status = 0;
12966 vars->phy_link_up = 0;
12967 vars->link_up = 0;
12968 vars->line_speed = 0;
12969 vars->duplex = DUPLEX_FULL;
12970 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12971 vars->mac_type = MAC_TYPE_NONE;
12972 vars->phy_flags = 0;
12973 vars->check_kr2_recovery_cnt = 0;
12974 params->link_flags = PHY_INITIALIZED;
12975
12976 bnx2x_set_rx_filter(params, 1);
12977 bnx2x_chng_link_count(params, true);
12978
12979 lfa_status = bnx2x_check_lfa(params);
12980
12981 if (lfa_status == 0) {
12982 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12983 return bnx2x_avoid_link_flap(params, vars);
12984 }
12985
12986 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12987 lfa_status);
12988 bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12989
12990
12991 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12992 (NIG_MASK_XGXS0_LINK_STATUS |
12993 NIG_MASK_XGXS0_LINK10G |
12994 NIG_MASK_SERDES0_LINK_STATUS |
12995 NIG_MASK_MI_INT));
12996
12997 bnx2x_emac_init(params, vars);
12998
12999 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
13000 vars->link_status |= LINK_STATUS_PFC_ENABLED;
13001
13002 if (params->num_phys == 0) {
13003 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
13004 return -EINVAL;
13005 }
13006 set_phy_vars(params, vars);
13007
13008 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
13009 switch (params->loopback_mode) {
13010 case LOOPBACK_BMAC:
13011 bnx2x_init_bmac_loopback(params, vars);
13012 break;
13013 case LOOPBACK_EMAC:
13014 bnx2x_init_emac_loopback(params, vars);
13015 break;
13016 case LOOPBACK_XMAC:
13017 bnx2x_init_xmac_loopback(params, vars);
13018 break;
13019 case LOOPBACK_UMAC:
13020 bnx2x_init_umac_loopback(params, vars);
13021 break;
13022 case LOOPBACK_XGXS:
13023 case LOOPBACK_EXT_PHY:
13024 bnx2x_init_xgxs_loopback(params, vars);
13025 break;
13026 default:
13027 if (!CHIP_IS_E3(bp)) {
13028 if (params->switch_cfg == SWITCH_CFG_10G)
13029 bnx2x_xgxs_deassert(params);
13030 else
13031 bnx2x_serdes_deassert(bp, params->port);
13032 }
13033 bnx2x_link_initialize(params, vars);
13034 msleep(30);
13035 bnx2x_link_int_enable(params);
13036 break;
13037 }
13038 bnx2x_update_mng(params, vars->link_status);
13039
13040 bnx2x_update_mng_eee(params, vars->eee_status);
13041 return 0;
13042 }
13043
13044 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
13045 u8 reset_ext_phy)
13046 {
13047 struct bnx2x *bp = params->bp;
13048 u8 phy_index, port = params->port, clear_latch_ind = 0;
13049 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
13050
13051 vars->link_status = 0;
13052 bnx2x_chng_link_count(params, true);
13053 bnx2x_update_mng(params, vars->link_status);
13054 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
13055 SHMEM_EEE_ACTIVE_BIT);
13056 bnx2x_update_mng_eee(params, vars->eee_status);
13057 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
13058 (NIG_MASK_XGXS0_LINK_STATUS |
13059 NIG_MASK_XGXS0_LINK10G |
13060 NIG_MASK_SERDES0_LINK_STATUS |
13061 NIG_MASK_MI_INT));
13062
13063
13064 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
13065
13066
13067 if (!CHIP_IS_E3(bp)) {
13068 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
13069 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
13070 }
13071
13072 if (!CHIP_IS_E3(bp)) {
13073 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
13074 } else {
13075 bnx2x_set_xmac_rxtx(params, 0);
13076 bnx2x_set_umac_rxtx(params, 0);
13077 }
13078
13079 if (!CHIP_IS_E3(bp))
13080 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
13081
13082 usleep_range(10000, 20000);
13083
13084
13085
13086
13087 bnx2x_set_mdio_emac_per_phy(bp, params);
13088 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
13089
13090 if (reset_ext_phy) {
13091 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
13092 phy_index++) {
13093 if (params->phy[phy_index].link_reset) {
13094 bnx2x_set_aer_mmd(params,
13095 ¶ms->phy[phy_index]);
13096 params->phy[phy_index].link_reset(
13097 ¶ms->phy[phy_index],
13098 params);
13099 }
13100 if (params->phy[phy_index].flags &
13101 FLAGS_REARM_LATCH_SIGNAL)
13102 clear_latch_ind = 1;
13103 }
13104 }
13105
13106 if (clear_latch_ind) {
13107
13108 bnx2x_rearm_latch_signal(bp, port, 0);
13109 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
13110 1 << NIG_LATCH_BC_ENABLE_MI_INT);
13111 }
13112 if (params->phy[INT_PHY].link_reset)
13113 params->phy[INT_PHY].link_reset(
13114 ¶ms->phy[INT_PHY], params);
13115
13116
13117 if (!CHIP_IS_E3(bp)) {
13118
13119 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
13120 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
13121 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
13122 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
13123 } else {
13124 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13125 bnx2x_set_xumac_nig(params, 0, 0);
13126 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13127 MISC_REGISTERS_RESET_REG_2_XMAC)
13128 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
13129 XMAC_CTRL_REG_SOFT_RESET);
13130 }
13131 vars->link_up = 0;
13132 vars->phy_flags = 0;
13133 return 0;
13134 }
13135 int bnx2x_lfa_reset(struct link_params *params,
13136 struct link_vars *vars)
13137 {
13138 struct bnx2x *bp = params->bp;
13139 vars->link_up = 0;
13140 vars->phy_flags = 0;
13141 params->link_flags &= ~PHY_INITIALIZED;
13142 if (!params->lfa_base)
13143 return bnx2x_link_reset(params, vars, 1);
13144
13145
13146
13147
13148 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13149
13150
13151
13152
13153
13154 if (!CHIP_IS_E3(bp))
13155 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
13156
13157 if (CHIP_IS_E3(bp)) {
13158 bnx2x_set_xmac_rxtx(params, 0);
13159 bnx2x_set_umac_rxtx(params, 0);
13160 }
13161
13162 usleep_range(10000, 20000);
13163
13164
13165
13166
13167 bnx2x_set_rx_filter(params, 0);
13168
13169
13170
13171
13172
13173
13174
13175 if (!CHIP_IS_E3(bp))
13176 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
13177
13178 if (CHIP_IS_E3(bp)) {
13179 bnx2x_set_xmac_rxtx(params, 1);
13180 bnx2x_set_umac_rxtx(params, 1);
13181 }
13182
13183 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13184 return 0;
13185 }
13186
13187
13188
13189
13190 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
13191 u32 shmem_base_path[],
13192 u32 shmem2_base_path[], u8 phy_index,
13193 u32 chip_id)
13194 {
13195 struct bnx2x_phy phy[PORT_MAX];
13196 struct bnx2x_phy *phy_blk[PORT_MAX];
13197 u16 val;
13198 s8 port = 0;
13199 s8 port_of_path = 0;
13200 u32 swap_val, swap_override;
13201 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13202 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13203 port ^= (swap_val && swap_override);
13204 bnx2x_ext_phy_hw_reset(bp, port);
13205
13206 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13207 u32 shmem_base, shmem2_base;
13208
13209 if (CHIP_IS_E1x(bp)) {
13210 shmem_base = shmem_base_path[0];
13211 shmem2_base = shmem2_base_path[0];
13212 port_of_path = port;
13213 } else {
13214 shmem_base = shmem_base_path[port];
13215 shmem2_base = shmem2_base_path[port];
13216 port_of_path = 0;
13217 }
13218
13219
13220 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13221 port_of_path, &phy[port]) !=
13222 0) {
13223 DP(NETIF_MSG_LINK, "populate_phy failed\n");
13224 return -EINVAL;
13225 }
13226
13227 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13228 port_of_path*4,
13229 (NIG_MASK_XGXS0_LINK_STATUS |
13230 NIG_MASK_XGXS0_LINK10G |
13231 NIG_MASK_SERDES0_LINK_STATUS |
13232 NIG_MASK_MI_INT));
13233
13234
13235
13236
13237 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
13238 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13239 port);
13240
13241
13242 bnx2x_cl45_write(bp, &phy[port],
13243 MDIO_PMA_DEVAD,
13244 MDIO_PMA_REG_CTRL,
13245 1<<15);
13246 }
13247
13248
13249 msleep(150);
13250
13251 if (phy[PORT_0].addr & 0x1) {
13252 phy_blk[PORT_0] = &(phy[PORT_1]);
13253 phy_blk[PORT_1] = &(phy[PORT_0]);
13254 } else {
13255 phy_blk[PORT_0] = &(phy[PORT_0]);
13256 phy_blk[PORT_1] = &(phy[PORT_1]);
13257 }
13258
13259
13260 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13261 if (CHIP_IS_E1x(bp))
13262 port_of_path = port;
13263 else
13264 port_of_path = 0;
13265
13266 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13267 phy_blk[port]->addr);
13268 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13269 port_of_path))
13270 return -EINVAL;
13271
13272
13273 bnx2x_cl45_read(bp, phy_blk[port],
13274 MDIO_PMA_DEVAD,
13275 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13276
13277
13278 bnx2x_cl45_write(bp, phy_blk[port],
13279 MDIO_PMA_DEVAD,
13280 MDIO_PMA_REG_TX_POWER_DOWN,
13281 (val | 1<<10));
13282 }
13283
13284
13285
13286
13287 msleep(600);
13288
13289
13290 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13291
13292
13293 bnx2x_cl45_read(bp, phy_blk[port],
13294 MDIO_PMA_DEVAD,
13295 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13296
13297 bnx2x_cl45_write(bp, phy_blk[port],
13298 MDIO_PMA_DEVAD,
13299 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
13300 usleep_range(15000, 30000);
13301
13302
13303 bnx2x_cl45_read(bp, phy_blk[port],
13304 MDIO_PMA_DEVAD,
13305 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
13306 bnx2x_cl45_write(bp, phy_blk[port],
13307 MDIO_PMA_DEVAD,
13308 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
13309
13310
13311 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
13312 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
13313 }
13314 return 0;
13315 }
13316 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
13317 u32 shmem_base_path[],
13318 u32 shmem2_base_path[], u8 phy_index,
13319 u32 chip_id)
13320 {
13321 u32 val;
13322 s8 port;
13323 struct bnx2x_phy phy;
13324
13325
13326 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13327 val |= ((1<<MISC_REGISTERS_GPIO_3)|
13328 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
13329 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13330
13331 bnx2x_ext_phy_hw_reset(bp, 0);
13332 usleep_range(5000, 10000);
13333 for (port = 0; port < PORT_MAX; port++) {
13334 u32 shmem_base, shmem2_base;
13335
13336
13337 if (CHIP_IS_E1x(bp)) {
13338 shmem_base = shmem_base_path[0];
13339 shmem2_base = shmem2_base_path[0];
13340 } else {
13341 shmem_base = shmem_base_path[port];
13342 shmem2_base = shmem2_base_path[port];
13343 }
13344
13345 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13346 port, &phy) !=
13347 0) {
13348 DP(NETIF_MSG_LINK, "populate phy failed\n");
13349 return -EINVAL;
13350 }
13351
13352
13353 bnx2x_cl45_write(bp, &phy,
13354 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
13355
13356
13357
13358 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
13359 MISC_REGISTERS_GPIO_HIGH,
13360 port);
13361 }
13362
13363 return 0;
13364 }
13365 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
13366 u8 *io_gpio, u8 *io_port)
13367 {
13368
13369 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
13370 offsetof(struct shmem_region,
13371 dev_info.port_hw_config[PORT_0].default_cfg));
13372 switch (phy_gpio_reset) {
13373 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
13374 *io_gpio = 0;
13375 *io_port = 0;
13376 break;
13377 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
13378 *io_gpio = 1;
13379 *io_port = 0;
13380 break;
13381 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
13382 *io_gpio = 2;
13383 *io_port = 0;
13384 break;
13385 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
13386 *io_gpio = 3;
13387 *io_port = 0;
13388 break;
13389 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
13390 *io_gpio = 0;
13391 *io_port = 1;
13392 break;
13393 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13394 *io_gpio = 1;
13395 *io_port = 1;
13396 break;
13397 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13398 *io_gpio = 2;
13399 *io_port = 1;
13400 break;
13401 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13402 *io_gpio = 3;
13403 *io_port = 1;
13404 break;
13405 default:
13406
13407 break;
13408 }
13409 }
13410
13411 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13412 u32 shmem_base_path[],
13413 u32 shmem2_base_path[], u8 phy_index,
13414 u32 chip_id)
13415 {
13416 s8 port, reset_gpio;
13417 u32 swap_val, swap_override;
13418 struct bnx2x_phy phy[PORT_MAX];
13419 struct bnx2x_phy *phy_blk[PORT_MAX];
13420 s8 port_of_path;
13421 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13422 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13423
13424 reset_gpio = MISC_REGISTERS_GPIO_1;
13425 port = 1;
13426
13427
13428
13429
13430 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13431 (u8 *)&reset_gpio, (u8 *)&port);
13432
13433
13434 port ^= (swap_val && swap_override);
13435
13436
13437 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13438 port);
13439 usleep_range(1000, 2000);
13440 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13441 port);
13442
13443 usleep_range(5000, 10000);
13444
13445
13446 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13447 u32 shmem_base, shmem2_base;
13448
13449
13450 if (CHIP_IS_E1x(bp)) {
13451 shmem_base = shmem_base_path[0];
13452 shmem2_base = shmem2_base_path[0];
13453 port_of_path = port;
13454 } else {
13455 shmem_base = shmem_base_path[port];
13456 shmem2_base = shmem2_base_path[port];
13457 port_of_path = 0;
13458 }
13459
13460
13461 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13462 port_of_path, &phy[port]) !=
13463 0) {
13464 DP(NETIF_MSG_LINK, "populate phy failed\n");
13465 return -EINVAL;
13466 }
13467
13468 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13469 port_of_path*4,
13470 (NIG_MASK_XGXS0_LINK_STATUS |
13471 NIG_MASK_XGXS0_LINK10G |
13472 NIG_MASK_SERDES0_LINK_STATUS |
13473 NIG_MASK_MI_INT));
13474
13475
13476
13477 bnx2x_cl45_write(bp, &phy[port],
13478 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13479 }
13480
13481
13482 msleep(150);
13483 if (phy[PORT_0].addr & 0x1) {
13484 phy_blk[PORT_0] = &(phy[PORT_1]);
13485 phy_blk[PORT_1] = &(phy[PORT_0]);
13486 } else {
13487 phy_blk[PORT_0] = &(phy[PORT_0]);
13488 phy_blk[PORT_1] = &(phy[PORT_1]);
13489 }
13490
13491 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13492 if (CHIP_IS_E1x(bp))
13493 port_of_path = port;
13494 else
13495 port_of_path = 0;
13496 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13497 phy_blk[port]->addr);
13498 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13499 port_of_path))
13500 return -EINVAL;
13501
13502 bnx2x_cl45_write(bp, phy_blk[port],
13503 MDIO_PMA_DEVAD,
13504 MDIO_PMA_REG_TX_DISABLE, 1);
13505
13506 }
13507 return 0;
13508 }
13509
13510 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13511 u32 shmem_base_path[],
13512 u32 shmem2_base_path[],
13513 u8 phy_index,
13514 u32 chip_id)
13515 {
13516 u8 reset_gpios;
13517 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13518 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13519 udelay(10);
13520 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13521 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13522 reset_gpios);
13523 return 0;
13524 }
13525
13526 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13527 u32 shmem2_base_path[], u8 phy_index,
13528 u32 ext_phy_type, u32 chip_id)
13529 {
13530 int rc = 0;
13531
13532 switch (ext_phy_type) {
13533 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13534 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13535 shmem2_base_path,
13536 phy_index, chip_id);
13537 break;
13538 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13539 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13540 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13541 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13542 shmem2_base_path,
13543 phy_index, chip_id);
13544 break;
13545
13546 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13547
13548
13549
13550 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13551 shmem2_base_path,
13552 phy_index, chip_id);
13553 break;
13554 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13555 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13556 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
13557
13558
13559
13560 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13561 shmem2_base_path,
13562 phy_index, chip_id);
13563 break;
13564 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13565 rc = -EINVAL;
13566 break;
13567 default:
13568 DP(NETIF_MSG_LINK,
13569 "ext_phy 0x%x common init not required\n",
13570 ext_phy_type);
13571 break;
13572 }
13573
13574 if (rc)
13575 netdev_err(bp->dev, "Warning: PHY was not initialized,"
13576 " Port %d\n",
13577 0);
13578 return rc;
13579 }
13580
13581 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13582 u32 shmem2_base_path[], u32 chip_id)
13583 {
13584 int rc = 0;
13585 u32 phy_ver, val;
13586 u8 phy_index = 0;
13587 u32 ext_phy_type, ext_phy_config;
13588
13589 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13590 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13591 DP(NETIF_MSG_LINK, "Begin common phy init\n");
13592 if (CHIP_IS_E3(bp)) {
13593
13594 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13595 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13596 }
13597
13598 phy_ver = REG_RD(bp, shmem_base_path[0] +
13599 offsetof(struct shmem_region,
13600 port_mb[PORT_0].ext_phy_fw_version));
13601 if (phy_ver) {
13602 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13603 phy_ver);
13604 return 0;
13605 }
13606
13607
13608 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13609 phy_index++) {
13610 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13611 shmem_base_path[0],
13612 phy_index, 0);
13613 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13614 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13615 shmem2_base_path,
13616 phy_index, ext_phy_type,
13617 chip_id);
13618 }
13619 return rc;
13620 }
13621
13622 static void bnx2x_check_over_curr(struct link_params *params,
13623 struct link_vars *vars)
13624 {
13625 struct bnx2x *bp = params->bp;
13626 u32 cfg_pin;
13627 u8 port = params->port;
13628 u32 pin_val;
13629
13630 cfg_pin = (REG_RD(bp, params->shmem_base +
13631 offsetof(struct shmem_region,
13632 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13633 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13634 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13635
13636
13637 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13638 return;
13639
13640 if (!pin_val) {
13641 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13642 netdev_err(bp->dev, "Error: Power fault on Port %d has"
13643 " been detected and the power to "
13644 "that SFP+ module has been removed"
13645 " to prevent failure of the card."
13646 " Please remove the SFP+ module and"
13647 " restart the system to clear this"
13648 " error.\n",
13649 params->port);
13650 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13651 bnx2x_warpcore_power_module(params, 0);
13652 }
13653 } else
13654 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13655 }
13656
13657
13658 static u8 bnx2x_analyze_link_error(struct link_params *params,
13659 struct link_vars *vars, u32 status,
13660 u32 phy_flag, u32 link_flag, u8 notify)
13661 {
13662 struct bnx2x *bp = params->bp;
13663
13664 u8 led_mode;
13665 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13666
13667 if ((status ^ old_status) == 0)
13668 return 0;
13669
13670
13671 switch (phy_flag) {
13672 case PHY_HALF_OPEN_CONN_FLAG:
13673 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13674 break;
13675 case PHY_SFP_TX_FAULT_FLAG:
13676 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13677 break;
13678 default:
13679 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13680 }
13681 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13682 old_status, status);
13683
13684
13685 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
13686 return 1;
13687
13688
13689
13690
13691 if (status) {
13692 vars->link_status &= ~LINK_STATUS_LINK_UP;
13693 vars->link_status |= link_flag;
13694 vars->link_up = 0;
13695 vars->phy_flags |= phy_flag;
13696
13697
13698 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13699
13700
13701
13702 led_mode = LED_MODE_OFF;
13703 } else {
13704 vars->link_status |= LINK_STATUS_LINK_UP;
13705 vars->link_status &= ~link_flag;
13706 vars->link_up = 1;
13707 vars->phy_flags &= ~phy_flag;
13708 led_mode = LED_MODE_OPER;
13709
13710
13711 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13712 }
13713 bnx2x_sync_link(params, vars);
13714
13715 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13716
13717
13718 bnx2x_update_mng(params, vars->link_status);
13719
13720
13721 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13722 if (notify)
13723 bnx2x_notify_link_changed(bp);
13724
13725 return 1;
13726 }
13727
13728
13729
13730
13731
13732
13733
13734
13735
13736
13737 static int bnx2x_check_half_open_conn(struct link_params *params,
13738 struct link_vars *vars,
13739 u8 notify)
13740 {
13741 struct bnx2x *bp = params->bp;
13742 u32 lss_status = 0;
13743 u32 mac_base;
13744
13745 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13746 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13747 return 0;
13748
13749 if (CHIP_IS_E3(bp) &&
13750 (REG_RD(bp, MISC_REG_RESET_REG_2) &
13751 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13752
13753
13754
13755
13756
13757 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13758
13759
13760 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13761 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13762 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13763 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13764 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13765 lss_status = 1;
13766
13767 bnx2x_analyze_link_error(params, vars, lss_status,
13768 PHY_HALF_OPEN_CONN_FLAG,
13769 LINK_STATUS_NONE, notify);
13770 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13771 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13772
13773 u32 lss_status_reg;
13774 u32 wb_data[2];
13775 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13776 NIG_REG_INGRESS_BMAC0_MEM;
13777
13778 if (CHIP_IS_E2(bp))
13779 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13780 else
13781 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13782
13783 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13784 lss_status = (wb_data[0] > 0);
13785
13786 bnx2x_analyze_link_error(params, vars, lss_status,
13787 PHY_HALF_OPEN_CONN_FLAG,
13788 LINK_STATUS_NONE, notify);
13789 }
13790 return 0;
13791 }
13792 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13793 struct link_params *params,
13794 struct link_vars *vars)
13795 {
13796 struct bnx2x *bp = params->bp;
13797 u32 cfg_pin, value = 0;
13798 u8 led_change, port = params->port;
13799
13800
13801 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13802 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13803 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13804 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13805
13806 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13807 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13808 return;
13809 }
13810
13811 led_change = bnx2x_analyze_link_error(params, vars, value,
13812 PHY_SFP_TX_FAULT_FLAG,
13813 LINK_STATUS_SFP_TX_FAULT, 1);
13814
13815 if (led_change) {
13816
13817 u8 led_mode;
13818
13819 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13820 led_mode = MISC_REGISTERS_GPIO_HIGH;
13821 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13822 } else {
13823 led_mode = MISC_REGISTERS_GPIO_LOW;
13824 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13825 }
13826
13827
13828 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13829 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13830 led_mode);
13831 bnx2x_set_e3_module_fault_led(params, led_mode);
13832 }
13833 }
13834 }
13835 static void bnx2x_kr2_recovery(struct link_params *params,
13836 struct link_vars *vars,
13837 struct bnx2x_phy *phy)
13838 {
13839 struct bnx2x *bp = params->bp;
13840 DP(NETIF_MSG_LINK, "KR2 recovery\n");
13841 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13842 bnx2x_warpcore_restart_AN_KR(phy, params);
13843 }
13844
13845 static void bnx2x_check_kr2_wa(struct link_params *params,
13846 struct link_vars *vars,
13847 struct bnx2x_phy *phy)
13848 {
13849 struct bnx2x *bp = params->bp;
13850 u16 base_page, next_page, not_kr2_device, lane;
13851 int sigdet;
13852
13853
13854
13855
13856
13857
13858 if (vars->check_kr2_recovery_cnt > 0) {
13859 vars->check_kr2_recovery_cnt--;
13860 return;
13861 }
13862
13863 sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13864 if (!sigdet) {
13865 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13866 bnx2x_kr2_recovery(params, vars, phy);
13867 DP(NETIF_MSG_LINK, "No sigdet\n");
13868 }
13869 return;
13870 }
13871
13872 lane = bnx2x_get_warpcore_lane(phy, params);
13873 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13874 MDIO_AER_BLOCK_AER_REG, lane);
13875 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13876 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13877 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13878 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13879 bnx2x_set_aer_mmd(params, phy);
13880
13881
13882 if (base_page == 0) {
13883 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13884 bnx2x_kr2_recovery(params, vars, phy);
13885 DP(NETIF_MSG_LINK, "No BP\n");
13886 }
13887 return;
13888 }
13889
13890
13891
13892
13893
13894 not_kr2_device = (((base_page & 0x8000) == 0) ||
13895 (((base_page & 0x8000) &&
13896 ((next_page & 0xe0) == 0x20))));
13897
13898
13899 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13900 if (!not_kr2_device) {
13901 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13902 next_page);
13903 bnx2x_kr2_recovery(params, vars, phy);
13904 }
13905 return;
13906 }
13907
13908 if (not_kr2_device) {
13909
13910 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13911 bnx2x_disable_kr2(params, vars, phy);
13912
13913 bnx2x_warpcore_restart_AN_KR(phy, params);
13914 return;
13915 }
13916 }
13917
13918 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13919 {
13920 u16 phy_idx;
13921 struct bnx2x *bp = params->bp;
13922 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13923 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13924 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]);
13925 if (bnx2x_check_half_open_conn(params, vars, 1) !=
13926 0)
13927 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13928 break;
13929 }
13930 }
13931
13932 if (CHIP_IS_E3(bp)) {
13933 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY];
13934 bnx2x_set_aer_mmd(params, phy);
13935 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
13936 (phy->speed_cap_mask &
13937 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
13938 (phy->req_line_speed == SPEED_20000))
13939 bnx2x_check_kr2_wa(params, vars, phy);
13940 bnx2x_check_over_curr(params, vars);
13941 if (vars->rx_tx_asic_rst)
13942 bnx2x_warpcore_config_runtime(phy, params, vars);
13943
13944 if ((REG_RD(bp, params->shmem_base +
13945 offsetof(struct shmem_region, dev_info.
13946 port_hw_config[params->port].default_cfg))
13947 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13948 PORT_HW_CFG_NET_SERDES_IF_SFI) {
13949 if (bnx2x_is_sfp_module_plugged(phy, params)) {
13950 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13951 } else if (vars->link_status &
13952 LINK_STATUS_SFP_TX_FAULT) {
13953
13954 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13955 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13956
13957 bnx2x_update_mng(params, vars->link_status);
13958 }
13959 }
13960 }
13961 }
13962
13963 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13964 u32 shmem_base,
13965 u32 shmem2_base,
13966 u8 port)
13967 {
13968 u8 phy_index, fan_failure_det_req = 0;
13969 struct bnx2x_phy phy;
13970 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13971 phy_index++) {
13972 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13973 port, &phy)
13974 != 0) {
13975 DP(NETIF_MSG_LINK, "populate phy failed\n");
13976 return 0;
13977 }
13978 fan_failure_det_req |= (phy.flags &
13979 FLAGS_FAN_FAILURE_DET_REQ);
13980 }
13981 return fan_failure_det_req;
13982 }
13983
13984 void bnx2x_hw_reset_phy(struct link_params *params)
13985 {
13986 u8 phy_index;
13987 struct bnx2x *bp = params->bp;
13988 bnx2x_update_mng(params, 0);
13989 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13990 (NIG_MASK_XGXS0_LINK_STATUS |
13991 NIG_MASK_XGXS0_LINK10G |
13992 NIG_MASK_SERDES0_LINK_STATUS |
13993 NIG_MASK_MI_INT));
13994
13995 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13996 phy_index++) {
13997 if (params->phy[phy_index].hw_reset) {
13998 params->phy[phy_index].hw_reset(
13999 ¶ms->phy[phy_index],
14000 params);
14001 params->phy[phy_index] = phy_null;
14002 }
14003 }
14004 }
14005
14006 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
14007 u32 chip_id, u32 shmem_base, u32 shmem2_base,
14008 u8 port)
14009 {
14010 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
14011 u32 val;
14012 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
14013 if (CHIP_IS_E3(bp)) {
14014 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
14015 shmem_base,
14016 port,
14017 &gpio_num,
14018 &gpio_port) != 0)
14019 return;
14020 } else {
14021 struct bnx2x_phy phy;
14022 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
14023 phy_index++) {
14024 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
14025 shmem2_base, port, &phy)
14026 != 0) {
14027 DP(NETIF_MSG_LINK, "populate phy failed\n");
14028 return;
14029 }
14030 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
14031 gpio_num = MISC_REGISTERS_GPIO_3;
14032 gpio_port = port;
14033 break;
14034 }
14035 }
14036 }
14037
14038 if (gpio_num == 0xff)
14039 return;
14040
14041
14042 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
14043
14044 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
14045 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
14046 gpio_port ^= (swap_val && swap_override);
14047
14048 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
14049 (gpio_num + (gpio_port << 2));
14050
14051 sync_offset = shmem_base +
14052 offsetof(struct shmem_region,
14053 dev_info.port_hw_config[port].aeu_int_mask);
14054 REG_WR(bp, sync_offset, vars->aeu_int_mask);
14055
14056 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
14057 gpio_num, gpio_port, vars->aeu_int_mask);
14058
14059 if (port == 0)
14060 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
14061 else
14062 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
14063
14064
14065 aeu_mask = REG_RD(bp, offset);
14066 aeu_mask |= vars->aeu_int_mask;
14067 REG_WR(bp, offset, aeu_mask);
14068
14069
14070 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
14071 val |= 1 << (gpio_num + (gpio_port << 2));
14072 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
14073 }