root/drivers/net/ethernet/broadcom/tg3.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
   3  * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
   4  *
   5  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   6  * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
   7  * Copyright (C) 2004 Sun Microsystems Inc.
   8  * Copyright (C) 2007-2016 Broadcom Corporation.
   9  * Copyright (C) 2016-2017 Broadcom Limited.
  10  * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom"
  11  * refers to Broadcom Inc. and/or its subsidiaries.
  12  */
  13 
  14 #ifndef _T3_H
  15 #define _T3_H
  16 
  17 #define TG3_64BIT_REG_HIGH              0x00UL
  18 #define TG3_64BIT_REG_LOW               0x04UL
  19 
  20 /* Descriptor block info. */
  21 #define TG3_BDINFO_HOST_ADDR            0x0UL /* 64-bit */
  22 #define TG3_BDINFO_MAXLEN_FLAGS         0x8UL /* 32-bit */
  23 #define  BDINFO_FLAGS_USE_EXT_RECV       0x00000001 /* ext rx_buffer_desc */
  24 #define  BDINFO_FLAGS_DISABLED           0x00000002
  25 #define  BDINFO_FLAGS_MAXLEN_MASK        0xffff0000
  26 #define  BDINFO_FLAGS_MAXLEN_SHIFT       16
  27 #define TG3_BDINFO_NIC_ADDR             0xcUL /* 32-bit */
  28 #define TG3_BDINFO_SIZE                 0x10UL
  29 
  30 #define TG3_RX_STD_MAX_SIZE_5700        512
  31 #define TG3_RX_STD_MAX_SIZE_5717        2048
  32 #define TG3_RX_JMB_MAX_SIZE_5700        256
  33 #define TG3_RX_JMB_MAX_SIZE_5717        1024
  34 #define TG3_RX_RET_MAX_SIZE_5700        1024
  35 #define TG3_RX_RET_MAX_SIZE_5705        512
  36 #define TG3_RX_RET_MAX_SIZE_5717        4096
  37 
  38 #define TG3_RSS_INDIR_TBL_SIZE          128
  39 
  40 /* First 256 bytes are a mirror of PCI config space. */
  41 #define TG3PCI_VENDOR                   0x00000000
  42 #define  TG3PCI_VENDOR_BROADCOM          0x14e4
  43 #define TG3PCI_DEVICE                   0x00000002
  44 #define  TG3PCI_DEVICE_TIGON3_1          0x1644 /* BCM5700 */
  45 #define  TG3PCI_DEVICE_TIGON3_2          0x1645 /* BCM5701 */
  46 #define  TG3PCI_DEVICE_TIGON3_3          0x1646 /* BCM5702 */
  47 #define  TG3PCI_DEVICE_TIGON3_4          0x1647 /* BCM5703 */
  48 #define  TG3PCI_DEVICE_TIGON3_5761S      0x1688
  49 #define  TG3PCI_DEVICE_TIGON3_5761SE     0x1689
  50 #define  TG3PCI_DEVICE_TIGON3_57780      0x1692
  51 #define  TG3PCI_DEVICE_TIGON3_5787M      0x1693
  52 #define  TG3PCI_DEVICE_TIGON3_57760      0x1690
  53 #define  TG3PCI_DEVICE_TIGON3_57790      0x1694
  54 #define  TG3PCI_DEVICE_TIGON3_57788      0x1691
  55 #define  TG3PCI_DEVICE_TIGON3_5785_G     0x1699 /* GPHY */
  56 #define  TG3PCI_DEVICE_TIGON3_5785_F     0x16a0 /* 10/100 only */
  57 #define  TG3PCI_DEVICE_TIGON3_5717       0x1655
  58 #define  TG3PCI_DEVICE_TIGON3_5717_C     0x1665
  59 #define  TG3PCI_DEVICE_TIGON3_5718       0x1656
  60 #define  TG3PCI_DEVICE_TIGON3_57781      0x16b1
  61 #define  TG3PCI_DEVICE_TIGON3_57785      0x16b5
  62 #define  TG3PCI_DEVICE_TIGON3_57761      0x16b0
  63 #define  TG3PCI_DEVICE_TIGON3_57765      0x16b4
  64 #define  TG3PCI_DEVICE_TIGON3_57791      0x16b2
  65 #define  TG3PCI_DEVICE_TIGON3_57795      0x16b6
  66 #define  TG3PCI_DEVICE_TIGON3_5719       0x1657
  67 #define  TG3PCI_DEVICE_TIGON3_5720       0x165f
  68 #define  TG3PCI_DEVICE_TIGON3_57762      0x1682
  69 #define  TG3PCI_DEVICE_TIGON3_57766      0x1686
  70 #define  TG3PCI_DEVICE_TIGON3_57786      0x16b3
  71 #define  TG3PCI_DEVICE_TIGON3_57782      0x16b7
  72 #define  TG3PCI_DEVICE_TIGON3_5762       0x1687
  73 #define  TG3PCI_DEVICE_TIGON3_5725       0x1643
  74 #define  TG3PCI_DEVICE_TIGON3_5727       0x16f3
  75 #define  TG3PCI_DEVICE_TIGON3_57764      0x1642
  76 #define  TG3PCI_DEVICE_TIGON3_57767      0x1683
  77 #define  TG3PCI_DEVICE_TIGON3_57787      0x1641
  78 /* 0x04 --> 0x2c unused */
  79 #define TG3PCI_SUBVENDOR_ID_BROADCOM            PCI_VENDOR_ID_BROADCOM
  80 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6    0x1644
  81 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5    0x0001
  82 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6    0x0002
  83 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9    0x0003
  84 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1    0x0005
  85 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8    0x0006
  86 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7    0x0007
  87 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10   0x0008
  88 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12   0x8008
  89 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1   0x0009
  90 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2   0x8009
  91 #define TG3PCI_SUBVENDOR_ID_3COM                PCI_VENDOR_ID_3COM
  92 #define TG3PCI_SUBDEVICE_ID_3COM_3C996T         0x1000
  93 #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT        0x1006
  94 #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX        0x1004
  95 #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T        0x1007
  96 #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01      0x1008
  97 #define TG3PCI_SUBVENDOR_ID_DELL                PCI_VENDOR_ID_DELL
  98 #define TG3PCI_SUBDEVICE_ID_DELL_VIPER          0x00d1
  99 #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR         0x0106
 100 #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT         0x0109
 101 #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT    0x010a
 102 #define TG3PCI_SUBDEVICE_ID_DELL_5762           0x07f0
 103 #define TG3PCI_SUBVENDOR_ID_COMPAQ              PCI_VENDOR_ID_COMPAQ
 104 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE      0x007c
 105 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2    0x009a
 106 #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING   0x007d
 107 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780       0x0085
 108 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2     0x0099
 109 #define TG3PCI_SUBVENDOR_ID_IBM                 PCI_VENDOR_ID_IBM
 110 #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2        0x0281
 111 #define TG3PCI_SUBDEVICE_ID_ACER_57780_A        0x0601
 112 #define TG3PCI_SUBDEVICE_ID_ACER_57780_B        0x0612
 113 #define TG3PCI_SUBDEVICE_ID_LENOVO_5787M        0x3056
 114 
 115 /* 0x30 --> 0x64 unused */
 116 #define TG3PCI_MSI_DATA                 0x00000064
 117 /* 0x66 --> 0x68 unused */
 118 #define TG3PCI_MISC_HOST_CTRL           0x00000068
 119 #define  MISC_HOST_CTRL_CLEAR_INT        0x00000001
 120 #define  MISC_HOST_CTRL_MASK_PCI_INT     0x00000002
 121 #define  MISC_HOST_CTRL_BYTE_SWAP        0x00000004
 122 #define  MISC_HOST_CTRL_WORD_SWAP        0x00000008
 123 #define  MISC_HOST_CTRL_PCISTATE_RW      0x00000010
 124 #define  MISC_HOST_CTRL_CLKREG_RW        0x00000020
 125 #define  MISC_HOST_CTRL_REGWORD_SWAP     0x00000040
 126 #define  MISC_HOST_CTRL_INDIR_ACCESS     0x00000080
 127 #define  MISC_HOST_CTRL_IRQ_MASK_MODE    0x00000100
 128 #define  MISC_HOST_CTRL_TAGGED_STATUS    0x00000200
 129 #define  MISC_HOST_CTRL_CHIPREV          0xffff0000
 130 #define  MISC_HOST_CTRL_CHIPREV_SHIFT    16
 131 
 132 #define  CHIPREV_ID_5700_A0              0x7000
 133 #define  CHIPREV_ID_5700_A1              0x7001
 134 #define  CHIPREV_ID_5700_B0              0x7100
 135 #define  CHIPREV_ID_5700_B1              0x7101
 136 #define  CHIPREV_ID_5700_B3              0x7102
 137 #define  CHIPREV_ID_5700_ALTIMA          0x7104
 138 #define  CHIPREV_ID_5700_C0              0x7200
 139 #define  CHIPREV_ID_5701_A0              0x0000
 140 #define  CHIPREV_ID_5701_B0              0x0100
 141 #define  CHIPREV_ID_5701_B2              0x0102
 142 #define  CHIPREV_ID_5701_B5              0x0105
 143 #define  CHIPREV_ID_5703_A0              0x1000
 144 #define  CHIPREV_ID_5703_A1              0x1001
 145 #define  CHIPREV_ID_5703_A2              0x1002
 146 #define  CHIPREV_ID_5703_A3              0x1003
 147 #define  CHIPREV_ID_5704_A0              0x2000
 148 #define  CHIPREV_ID_5704_A1              0x2001
 149 #define  CHIPREV_ID_5704_A2              0x2002
 150 #define  CHIPREV_ID_5704_A3              0x2003
 151 #define  CHIPREV_ID_5705_A0              0x3000
 152 #define  CHIPREV_ID_5705_A1              0x3001
 153 #define  CHIPREV_ID_5705_A2              0x3002
 154 #define  CHIPREV_ID_5705_A3              0x3003
 155 #define  CHIPREV_ID_5750_A0              0x4000
 156 #define  CHIPREV_ID_5750_A1              0x4001
 157 #define  CHIPREV_ID_5750_A3              0x4003
 158 #define  CHIPREV_ID_5750_C2              0x4202
 159 #define  CHIPREV_ID_5752_A0_HW           0x5000
 160 #define  CHIPREV_ID_5752_A0              0x6000
 161 #define  CHIPREV_ID_5752_A1              0x6001
 162 #define  CHIPREV_ID_5714_A2              0x9002
 163 #define  CHIPREV_ID_5906_A1              0xc001
 164 #define  CHIPREV_ID_57780_A0             0x57780000
 165 #define  CHIPREV_ID_57780_A1             0x57780001
 166 #define  CHIPREV_ID_5717_A0              0x05717000
 167 #define  CHIPREV_ID_5717_C0              0x05717200
 168 #define  CHIPREV_ID_57765_A0             0x57785000
 169 #define  CHIPREV_ID_5719_A0              0x05719000
 170 #define  CHIPREV_ID_5720_A0              0x05720000
 171 #define  CHIPREV_ID_5762_A0              0x05762000
 172 
 173 #define   ASIC_REV_5700                  0x07
 174 #define   ASIC_REV_5701                  0x00
 175 #define   ASIC_REV_5703                  0x01
 176 #define   ASIC_REV_5704                  0x02
 177 #define   ASIC_REV_5705                  0x03
 178 #define   ASIC_REV_5750                  0x04
 179 #define   ASIC_REV_5752                  0x06
 180 #define   ASIC_REV_5780                  0x08
 181 #define   ASIC_REV_5714                  0x09
 182 #define   ASIC_REV_5755                  0x0a
 183 #define   ASIC_REV_5787                  0x0b
 184 #define   ASIC_REV_5906                  0x0c
 185 #define   ASIC_REV_USE_PROD_ID_REG       0x0f
 186 #define   ASIC_REV_5784                  0x5784
 187 #define   ASIC_REV_5761                  0x5761
 188 #define   ASIC_REV_5785                  0x5785
 189 #define   ASIC_REV_57780                 0x57780
 190 #define   ASIC_REV_5717                  0x5717
 191 #define   ASIC_REV_57765                 0x57785
 192 #define   ASIC_REV_5719                  0x5719
 193 #define   ASIC_REV_5720                  0x5720
 194 #define   ASIC_REV_57766                 0x57766
 195 #define   ASIC_REV_5762                  0x5762
 196 #define   CHIPREV_5700_AX                0x70
 197 #define   CHIPREV_5700_BX                0x71
 198 #define   CHIPREV_5700_CX                0x72
 199 #define   CHIPREV_5701_AX                0x00
 200 #define   CHIPREV_5703_AX                0x10
 201 #define   CHIPREV_5704_AX                0x20
 202 #define   CHIPREV_5704_BX                0x21
 203 #define   CHIPREV_5750_AX                0x40
 204 #define   CHIPREV_5750_BX                0x41
 205 #define   CHIPREV_5784_AX                0x57840
 206 #define   CHIPREV_5761_AX                0x57610
 207 #define   CHIPREV_57765_AX               0x577650
 208 #define   METAL_REV_A0                   0x00
 209 #define   METAL_REV_A1                   0x01
 210 #define   METAL_REV_B0                   0x00
 211 #define   METAL_REV_B1                   0x01
 212 #define   METAL_REV_B2                   0x02
 213 #define TG3PCI_DMA_RW_CTRL              0x0000006c
 214 #define  DMA_RWCTRL_DIS_CACHE_ALIGNMENT  0x00000001
 215 #define  DMA_RWCTRL_TAGGED_STAT_WA       0x00000080
 216 #define  DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
 217 #define  DMA_RWCTRL_READ_BNDRY_MASK      0x00000700
 218 #define  DMA_RWCTRL_READ_BNDRY_DISAB     0x00000000
 219 #define  DMA_RWCTRL_READ_BNDRY_16        0x00000100
 220 #define  DMA_RWCTRL_READ_BNDRY_128_PCIX  0x00000100
 221 #define  DMA_RWCTRL_READ_BNDRY_32        0x00000200
 222 #define  DMA_RWCTRL_READ_BNDRY_256_PCIX  0x00000200
 223 #define  DMA_RWCTRL_READ_BNDRY_64        0x00000300
 224 #define  DMA_RWCTRL_READ_BNDRY_384_PCIX  0x00000300
 225 #define  DMA_RWCTRL_READ_BNDRY_128       0x00000400
 226 #define  DMA_RWCTRL_READ_BNDRY_256       0x00000500
 227 #define  DMA_RWCTRL_READ_BNDRY_512       0x00000600
 228 #define  DMA_RWCTRL_READ_BNDRY_1024      0x00000700
 229 #define  DMA_RWCTRL_WRITE_BNDRY_MASK     0x00003800
 230 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB    0x00000000
 231 #define  DMA_RWCTRL_WRITE_BNDRY_16       0x00000800
 232 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
 233 #define  DMA_RWCTRL_WRITE_BNDRY_32       0x00001000
 234 #define  DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
 235 #define  DMA_RWCTRL_WRITE_BNDRY_64       0x00001800
 236 #define  DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
 237 #define  DMA_RWCTRL_WRITE_BNDRY_128      0x00002000
 238 #define  DMA_RWCTRL_WRITE_BNDRY_256      0x00002800
 239 #define  DMA_RWCTRL_WRITE_BNDRY_512      0x00003000
 240 #define  DMA_RWCTRL_WRITE_BNDRY_1024     0x00003800
 241 #define  DMA_RWCTRL_ONE_DMA              0x00004000
 242 #define  DMA_RWCTRL_READ_WATER           0x00070000
 243 #define  DMA_RWCTRL_READ_WATER_SHIFT     16
 244 #define  DMA_RWCTRL_WRITE_WATER          0x00380000
 245 #define  DMA_RWCTRL_WRITE_WATER_SHIFT    19
 246 #define  DMA_RWCTRL_USE_MEM_READ_MULT    0x00400000
 247 #define  DMA_RWCTRL_ASSERT_ALL_BE        0x00800000
 248 #define  DMA_RWCTRL_PCI_READ_CMD         0x0f000000
 249 #define  DMA_RWCTRL_PCI_READ_CMD_SHIFT   24
 250 #define  DMA_RWCTRL_PCI_WRITE_CMD        0xf0000000
 251 #define  DMA_RWCTRL_PCI_WRITE_CMD_SHIFT  28
 252 #define  DMA_RWCTRL_WRITE_BNDRY_64_PCIE  0x10000000
 253 #define  DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
 254 #define  DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
 255 #define TG3PCI_PCISTATE                 0x00000070
 256 #define  PCISTATE_FORCE_RESET            0x00000001
 257 #define  PCISTATE_INT_NOT_ACTIVE         0x00000002
 258 #define  PCISTATE_CONV_PCI_MODE          0x00000004
 259 #define  PCISTATE_BUS_SPEED_HIGH         0x00000008
 260 #define  PCISTATE_BUS_32BIT              0x00000010
 261 #define  PCISTATE_ROM_ENABLE             0x00000020
 262 #define  PCISTATE_ROM_RETRY_ENABLE       0x00000040
 263 #define  PCISTATE_FLAT_VIEW              0x00000100
 264 #define  PCISTATE_RETRY_SAME_DMA         0x00002000
 265 #define  PCISTATE_ALLOW_APE_CTLSPC_WR    0x00010000
 266 #define  PCISTATE_ALLOW_APE_SHMEM_WR     0x00020000
 267 #define  PCISTATE_ALLOW_APE_PSPACE_WR    0x00040000
 268 #define TG3PCI_CLOCK_CTRL               0x00000074
 269 #define  CLOCK_CTRL_CORECLK_DISABLE      0x00000200
 270 #define  CLOCK_CTRL_RXCLK_DISABLE        0x00000400
 271 #define  CLOCK_CTRL_TXCLK_DISABLE        0x00000800
 272 #define  CLOCK_CTRL_ALTCLK               0x00001000
 273 #define  CLOCK_CTRL_PWRDOWN_PLL133       0x00008000
 274 #define  CLOCK_CTRL_44MHZ_CORE           0x00040000
 275 #define  CLOCK_CTRL_625_CORE             0x00100000
 276 #define  CLOCK_CTRL_FORCE_CLKRUN         0x00200000
 277 #define  CLOCK_CTRL_CLKRUN_OENABLE       0x00400000
 278 #define  CLOCK_CTRL_DELAY_PCI_GRANT      0x80000000
 279 #define TG3PCI_REG_BASE_ADDR            0x00000078
 280 #define TG3PCI_MEM_WIN_BASE_ADDR        0x0000007c
 281 #define TG3PCI_REG_DATA                 0x00000080
 282 #define TG3PCI_MEM_WIN_DATA             0x00000084
 283 #define TG3PCI_MISC_LOCAL_CTRL          0x00000090
 284 /* 0x94 --> 0x98 unused */
 285 #define TG3PCI_STD_RING_PROD_IDX        0x00000098 /* 64-bit */
 286 #define TG3PCI_RCV_RET_RING_CON_IDX     0x000000a0 /* 64-bit */
 287 /* 0xa8 --> 0xb8 unused */
 288 #define TG3PCI_DEV_STATUS_CTRL          0x000000b4
 289 #define  MAX_READ_REQ_SIZE_2048          0x00004000
 290 #define  MAX_READ_REQ_MASK               0x00007000
 291 #define TG3PCI_DUAL_MAC_CTRL            0x000000b8
 292 #define  DUAL_MAC_CTRL_CH_MASK           0x00000003
 293 #define  DUAL_MAC_CTRL_ID                0x00000004
 294 #define TG3PCI_PRODID_ASICREV           0x000000bc
 295 #define  PROD_ID_ASIC_REV_MASK           0x0fffffff
 296 /* 0xc0 --> 0xf4 unused */
 297 
 298 #define TG3PCI_GEN2_PRODID_ASICREV      0x000000f4
 299 #define TG3PCI_GEN15_PRODID_ASICREV     0x000000fc
 300 /* 0xf8 --> 0x200 unused */
 301 
 302 #define TG3_CORR_ERR_STAT               0x00000110
 303 #define  TG3_CORR_ERR_STAT_CLEAR        0xffffffff
 304 /* 0x114 --> 0x200 unused */
 305 
 306 /* Mailbox registers */
 307 #define MAILBOX_INTERRUPT_0             0x00000200 /* 64-bit */
 308 #define MAILBOX_INTERRUPT_1             0x00000208 /* 64-bit */
 309 #define MAILBOX_INTERRUPT_2             0x00000210 /* 64-bit */
 310 #define MAILBOX_INTERRUPT_3             0x00000218 /* 64-bit */
 311 #define MAILBOX_GENERAL_0               0x00000220 /* 64-bit */
 312 #define MAILBOX_GENERAL_1               0x00000228 /* 64-bit */
 313 #define MAILBOX_GENERAL_2               0x00000230 /* 64-bit */
 314 #define MAILBOX_GENERAL_3               0x00000238 /* 64-bit */
 315 #define MAILBOX_GENERAL_4               0x00000240 /* 64-bit */
 316 #define MAILBOX_GENERAL_5               0x00000248 /* 64-bit */
 317 #define MAILBOX_GENERAL_6               0x00000250 /* 64-bit */
 318 #define MAILBOX_GENERAL_7               0x00000258 /* 64-bit */
 319 #define MAILBOX_RELOAD_STAT             0x00000260 /* 64-bit */
 320 #define MAILBOX_RCV_STD_PROD_IDX        0x00000268 /* 64-bit */
 321 #define TG3_RX_STD_PROD_IDX_REG         (MAILBOX_RCV_STD_PROD_IDX + \
 322                                          TG3_64BIT_REG_LOW)
 323 #define MAILBOX_RCV_JUMBO_PROD_IDX      0x00000270 /* 64-bit */
 324 #define TG3_RX_JMB_PROD_IDX_REG         (MAILBOX_RCV_JUMBO_PROD_IDX + \
 325                                          TG3_64BIT_REG_LOW)
 326 #define MAILBOX_RCV_MINI_PROD_IDX       0x00000278 /* 64-bit */
 327 #define MAILBOX_RCVRET_CON_IDX_0        0x00000280 /* 64-bit */
 328 #define MAILBOX_RCVRET_CON_IDX_1        0x00000288 /* 64-bit */
 329 #define MAILBOX_RCVRET_CON_IDX_2        0x00000290 /* 64-bit */
 330 #define MAILBOX_RCVRET_CON_IDX_3        0x00000298 /* 64-bit */
 331 #define MAILBOX_RCVRET_CON_IDX_4        0x000002a0 /* 64-bit */
 332 #define MAILBOX_RCVRET_CON_IDX_5        0x000002a8 /* 64-bit */
 333 #define MAILBOX_RCVRET_CON_IDX_6        0x000002b0 /* 64-bit */
 334 #define MAILBOX_RCVRET_CON_IDX_7        0x000002b8 /* 64-bit */
 335 #define MAILBOX_RCVRET_CON_IDX_8        0x000002c0 /* 64-bit */
 336 #define MAILBOX_RCVRET_CON_IDX_9        0x000002c8 /* 64-bit */
 337 #define MAILBOX_RCVRET_CON_IDX_10       0x000002d0 /* 64-bit */
 338 #define MAILBOX_RCVRET_CON_IDX_11       0x000002d8 /* 64-bit */
 339 #define MAILBOX_RCVRET_CON_IDX_12       0x000002e0 /* 64-bit */
 340 #define MAILBOX_RCVRET_CON_IDX_13       0x000002e8 /* 64-bit */
 341 #define MAILBOX_RCVRET_CON_IDX_14       0x000002f0 /* 64-bit */
 342 #define MAILBOX_RCVRET_CON_IDX_15       0x000002f8 /* 64-bit */
 343 #define MAILBOX_SNDHOST_PROD_IDX_0      0x00000300 /* 64-bit */
 344 #define MAILBOX_SNDHOST_PROD_IDX_1      0x00000308 /* 64-bit */
 345 #define MAILBOX_SNDHOST_PROD_IDX_2      0x00000310 /* 64-bit */
 346 #define MAILBOX_SNDHOST_PROD_IDX_3      0x00000318 /* 64-bit */
 347 #define MAILBOX_SNDHOST_PROD_IDX_4      0x00000320 /* 64-bit */
 348 #define MAILBOX_SNDHOST_PROD_IDX_5      0x00000328 /* 64-bit */
 349 #define MAILBOX_SNDHOST_PROD_IDX_6      0x00000330 /* 64-bit */
 350 #define MAILBOX_SNDHOST_PROD_IDX_7      0x00000338 /* 64-bit */
 351 #define MAILBOX_SNDHOST_PROD_IDX_8      0x00000340 /* 64-bit */
 352 #define MAILBOX_SNDHOST_PROD_IDX_9      0x00000348 /* 64-bit */
 353 #define MAILBOX_SNDHOST_PROD_IDX_10     0x00000350 /* 64-bit */
 354 #define MAILBOX_SNDHOST_PROD_IDX_11     0x00000358 /* 64-bit */
 355 #define MAILBOX_SNDHOST_PROD_IDX_12     0x00000360 /* 64-bit */
 356 #define MAILBOX_SNDHOST_PROD_IDX_13     0x00000368 /* 64-bit */
 357 #define MAILBOX_SNDHOST_PROD_IDX_14     0x00000370 /* 64-bit */
 358 #define MAILBOX_SNDHOST_PROD_IDX_15     0x00000378 /* 64-bit */
 359 #define MAILBOX_SNDNIC_PROD_IDX_0       0x00000380 /* 64-bit */
 360 #define MAILBOX_SNDNIC_PROD_IDX_1       0x00000388 /* 64-bit */
 361 #define MAILBOX_SNDNIC_PROD_IDX_2       0x00000390 /* 64-bit */
 362 #define MAILBOX_SNDNIC_PROD_IDX_3       0x00000398 /* 64-bit */
 363 #define MAILBOX_SNDNIC_PROD_IDX_4       0x000003a0 /* 64-bit */
 364 #define MAILBOX_SNDNIC_PROD_IDX_5       0x000003a8 /* 64-bit */
 365 #define MAILBOX_SNDNIC_PROD_IDX_6       0x000003b0 /* 64-bit */
 366 #define MAILBOX_SNDNIC_PROD_IDX_7       0x000003b8 /* 64-bit */
 367 #define MAILBOX_SNDNIC_PROD_IDX_8       0x000003c0 /* 64-bit */
 368 #define MAILBOX_SNDNIC_PROD_IDX_9       0x000003c8 /* 64-bit */
 369 #define MAILBOX_SNDNIC_PROD_IDX_10      0x000003d0 /* 64-bit */
 370 #define MAILBOX_SNDNIC_PROD_IDX_11      0x000003d8 /* 64-bit */
 371 #define MAILBOX_SNDNIC_PROD_IDX_12      0x000003e0 /* 64-bit */
 372 #define MAILBOX_SNDNIC_PROD_IDX_13      0x000003e8 /* 64-bit */
 373 #define MAILBOX_SNDNIC_PROD_IDX_14      0x000003f0 /* 64-bit */
 374 #define MAILBOX_SNDNIC_PROD_IDX_15      0x000003f8 /* 64-bit */
 375 
 376 /* MAC control registers */
 377 #define MAC_MODE                        0x00000400
 378 #define  MAC_MODE_RESET                  0x00000001
 379 #define  MAC_MODE_HALF_DUPLEX            0x00000002
 380 #define  MAC_MODE_PORT_MODE_MASK         0x0000000c
 381 #define  MAC_MODE_PORT_MODE_TBI          0x0000000c
 382 #define  MAC_MODE_PORT_MODE_GMII         0x00000008
 383 #define  MAC_MODE_PORT_MODE_MII          0x00000004
 384 #define  MAC_MODE_PORT_MODE_NONE         0x00000000
 385 #define  MAC_MODE_PORT_INT_LPBACK        0x00000010
 386 #define  MAC_MODE_TAGGED_MAC_CTRL        0x00000080
 387 #define  MAC_MODE_TX_BURSTING            0x00000100
 388 #define  MAC_MODE_MAX_DEFER              0x00000200
 389 #define  MAC_MODE_LINK_POLARITY          0x00000400
 390 #define  MAC_MODE_RXSTAT_ENABLE          0x00000800
 391 #define  MAC_MODE_RXSTAT_CLEAR           0x00001000
 392 #define  MAC_MODE_RXSTAT_FLUSH           0x00002000
 393 #define  MAC_MODE_TXSTAT_ENABLE          0x00004000
 394 #define  MAC_MODE_TXSTAT_CLEAR           0x00008000
 395 #define  MAC_MODE_TXSTAT_FLUSH           0x00010000
 396 #define  MAC_MODE_SEND_CONFIGS           0x00020000
 397 #define  MAC_MODE_MAGIC_PKT_ENABLE       0x00040000
 398 #define  MAC_MODE_ACPI_ENABLE            0x00080000
 399 #define  MAC_MODE_MIP_ENABLE             0x00100000
 400 #define  MAC_MODE_TDE_ENABLE             0x00200000
 401 #define  MAC_MODE_RDE_ENABLE             0x00400000
 402 #define  MAC_MODE_FHDE_ENABLE            0x00800000
 403 #define  MAC_MODE_KEEP_FRAME_IN_WOL      0x01000000
 404 #define  MAC_MODE_APE_RX_EN              0x08000000
 405 #define  MAC_MODE_APE_TX_EN              0x10000000
 406 #define MAC_STATUS                      0x00000404
 407 #define  MAC_STATUS_PCS_SYNCED           0x00000001
 408 #define  MAC_STATUS_SIGNAL_DET           0x00000002
 409 #define  MAC_STATUS_RCVD_CFG             0x00000004
 410 #define  MAC_STATUS_CFG_CHANGED          0x00000008
 411 #define  MAC_STATUS_SYNC_CHANGED         0x00000010
 412 #define  MAC_STATUS_PORT_DEC_ERR         0x00000400
 413 #define  MAC_STATUS_LNKSTATE_CHANGED     0x00001000
 414 #define  MAC_STATUS_MI_COMPLETION        0x00400000
 415 #define  MAC_STATUS_MI_INTERRUPT         0x00800000
 416 #define  MAC_STATUS_AP_ERROR             0x01000000
 417 #define  MAC_STATUS_ODI_ERROR            0x02000000
 418 #define  MAC_STATUS_RXSTAT_OVERRUN       0x04000000
 419 #define  MAC_STATUS_TXSTAT_OVERRUN       0x08000000
 420 #define MAC_EVENT                       0x00000408
 421 #define  MAC_EVENT_PORT_DECODE_ERR       0x00000400
 422 #define  MAC_EVENT_LNKSTATE_CHANGED      0x00001000
 423 #define  MAC_EVENT_MI_COMPLETION         0x00400000
 424 #define  MAC_EVENT_MI_INTERRUPT          0x00800000
 425 #define  MAC_EVENT_AP_ERROR              0x01000000
 426 #define  MAC_EVENT_ODI_ERROR             0x02000000
 427 #define  MAC_EVENT_RXSTAT_OVERRUN        0x04000000
 428 #define  MAC_EVENT_TXSTAT_OVERRUN        0x08000000
 429 #define MAC_LED_CTRL                    0x0000040c
 430 #define  LED_CTRL_LNKLED_OVERRIDE        0x00000001
 431 #define  LED_CTRL_1000MBPS_ON            0x00000002
 432 #define  LED_CTRL_100MBPS_ON             0x00000004
 433 #define  LED_CTRL_10MBPS_ON              0x00000008
 434 #define  LED_CTRL_TRAFFIC_OVERRIDE       0x00000010
 435 #define  LED_CTRL_TRAFFIC_BLINK          0x00000020
 436 #define  LED_CTRL_TRAFFIC_LED            0x00000040
 437 #define  LED_CTRL_1000MBPS_STATUS        0x00000080
 438 #define  LED_CTRL_100MBPS_STATUS         0x00000100
 439 #define  LED_CTRL_10MBPS_STATUS          0x00000200
 440 #define  LED_CTRL_TRAFFIC_STATUS         0x00000400
 441 #define  LED_CTRL_MODE_MAC               0x00000000
 442 #define  LED_CTRL_MODE_PHY_1             0x00000800
 443 #define  LED_CTRL_MODE_PHY_2             0x00001000
 444 #define  LED_CTRL_MODE_SHASTA_MAC        0x00002000
 445 #define  LED_CTRL_MODE_SHARED            0x00004000
 446 #define  LED_CTRL_MODE_COMBO             0x00008000
 447 #define  LED_CTRL_BLINK_RATE_MASK        0x7ff80000
 448 #define  LED_CTRL_BLINK_RATE_SHIFT       19
 449 #define  LED_CTRL_BLINK_PER_OVERRIDE     0x00080000
 450 #define  LED_CTRL_BLINK_RATE_OVERRIDE    0x80000000
 451 #define MAC_ADDR_0_HIGH                 0x00000410 /* upper 2 bytes */
 452 #define MAC_ADDR_0_LOW                  0x00000414 /* lower 4 bytes */
 453 #define MAC_ADDR_1_HIGH                 0x00000418 /* upper 2 bytes */
 454 #define MAC_ADDR_1_LOW                  0x0000041c /* lower 4 bytes */
 455 #define MAC_ADDR_2_HIGH                 0x00000420 /* upper 2 bytes */
 456 #define MAC_ADDR_2_LOW                  0x00000424 /* lower 4 bytes */
 457 #define MAC_ADDR_3_HIGH                 0x00000428 /* upper 2 bytes */
 458 #define MAC_ADDR_3_LOW                  0x0000042c /* lower 4 bytes */
 459 #define MAC_ACPI_MBUF_PTR               0x00000430
 460 #define MAC_ACPI_LEN_OFFSET             0x00000434
 461 #define  ACPI_LENOFF_LEN_MASK            0x0000ffff
 462 #define  ACPI_LENOFF_LEN_SHIFT           0
 463 #define  ACPI_LENOFF_OFF_MASK            0x0fff0000
 464 #define  ACPI_LENOFF_OFF_SHIFT           16
 465 #define MAC_TX_BACKOFF_SEED             0x00000438
 466 #define  TX_BACKOFF_SEED_MASK            0x000003ff
 467 #define MAC_RX_MTU_SIZE                 0x0000043c
 468 #define  RX_MTU_SIZE_MASK                0x0000ffff
 469 #define MAC_PCS_TEST                    0x00000440
 470 #define  PCS_TEST_PATTERN_MASK           0x000fffff
 471 #define  PCS_TEST_PATTERN_SHIFT          0
 472 #define  PCS_TEST_ENABLE                 0x00100000
 473 #define MAC_TX_AUTO_NEG                 0x00000444
 474 #define  TX_AUTO_NEG_MASK                0x0000ffff
 475 #define  TX_AUTO_NEG_SHIFT               0
 476 #define MAC_RX_AUTO_NEG                 0x00000448
 477 #define  RX_AUTO_NEG_MASK                0x0000ffff
 478 #define  RX_AUTO_NEG_SHIFT               0
 479 #define MAC_MI_COM                      0x0000044c
 480 #define  MI_COM_CMD_MASK                 0x0c000000
 481 #define  MI_COM_CMD_WRITE                0x04000000
 482 #define  MI_COM_CMD_READ                 0x08000000
 483 #define  MI_COM_READ_FAILED              0x10000000
 484 #define  MI_COM_START                    0x20000000
 485 #define  MI_COM_BUSY                     0x20000000
 486 #define  MI_COM_PHY_ADDR_MASK            0x03e00000
 487 #define  MI_COM_PHY_ADDR_SHIFT           21
 488 #define  MI_COM_REG_ADDR_MASK            0x001f0000
 489 #define  MI_COM_REG_ADDR_SHIFT           16
 490 #define  MI_COM_DATA_MASK                0x0000ffff
 491 #define MAC_MI_STAT                     0x00000450
 492 #define  MAC_MI_STAT_LNKSTAT_ATTN_ENAB   0x00000001
 493 #define  MAC_MI_STAT_10MBPS_MODE         0x00000002
 494 #define MAC_MI_MODE                     0x00000454
 495 #define  MAC_MI_MODE_CLK_10MHZ           0x00000001
 496 #define  MAC_MI_MODE_SHORT_PREAMBLE      0x00000002
 497 #define  MAC_MI_MODE_AUTO_POLL           0x00000010
 498 #define  MAC_MI_MODE_500KHZ_CONST        0x00008000
 499 #define  MAC_MI_MODE_BASE                0x000c0000 /* XXX magic values XXX */
 500 #define MAC_AUTO_POLL_STATUS            0x00000458
 501 #define  MAC_AUTO_POLL_ERROR             0x00000001
 502 #define MAC_TX_MODE                     0x0000045c
 503 #define  TX_MODE_RESET                   0x00000001
 504 #define  TX_MODE_ENABLE                  0x00000002
 505 #define  TX_MODE_FLOW_CTRL_ENABLE        0x00000010
 506 #define  TX_MODE_BIG_BCKOFF_ENABLE       0x00000020
 507 #define  TX_MODE_LONG_PAUSE_ENABLE       0x00000040
 508 #define  TX_MODE_MBUF_LOCKUP_FIX         0x00000100
 509 #define  TX_MODE_JMB_FRM_LEN             0x00400000
 510 #define  TX_MODE_CNT_DN_MODE             0x00800000
 511 #define MAC_TX_STATUS                   0x00000460
 512 #define  TX_STATUS_XOFFED                0x00000001
 513 #define  TX_STATUS_SENT_XOFF             0x00000002
 514 #define  TX_STATUS_SENT_XON              0x00000004
 515 #define  TX_STATUS_LINK_UP               0x00000008
 516 #define  TX_STATUS_ODI_UNDERRUN          0x00000010
 517 #define  TX_STATUS_ODI_OVERRUN           0x00000020
 518 #define MAC_TX_LENGTHS                  0x00000464
 519 #define  TX_LENGTHS_SLOT_TIME_MASK       0x000000ff
 520 #define  TX_LENGTHS_SLOT_TIME_SHIFT      0
 521 #define  TX_LENGTHS_IPG_MASK             0x00000f00
 522 #define  TX_LENGTHS_IPG_SHIFT            8
 523 #define  TX_LENGTHS_IPG_CRS_MASK         0x00003000
 524 #define  TX_LENGTHS_IPG_CRS_SHIFT        12
 525 #define  TX_LENGTHS_JMB_FRM_LEN_MSK      0x00ff0000
 526 #define  TX_LENGTHS_CNT_DWN_VAL_MSK      0xff000000
 527 #define MAC_RX_MODE                     0x00000468
 528 #define  RX_MODE_RESET                   0x00000001
 529 #define  RX_MODE_ENABLE                  0x00000002
 530 #define  RX_MODE_FLOW_CTRL_ENABLE        0x00000004
 531 #define  RX_MODE_KEEP_MAC_CTRL           0x00000008
 532 #define  RX_MODE_KEEP_PAUSE              0x00000010
 533 #define  RX_MODE_ACCEPT_OVERSIZED        0x00000020
 534 #define  RX_MODE_ACCEPT_RUNTS            0x00000040
 535 #define  RX_MODE_LEN_CHECK               0x00000080
 536 #define  RX_MODE_PROMISC                 0x00000100
 537 #define  RX_MODE_NO_CRC_CHECK            0x00000200
 538 #define  RX_MODE_KEEP_VLAN_TAG           0x00000400
 539 #define  RX_MODE_RSS_IPV4_HASH_EN        0x00010000
 540 #define  RX_MODE_RSS_TCP_IPV4_HASH_EN    0x00020000
 541 #define  RX_MODE_RSS_IPV6_HASH_EN        0x00040000
 542 #define  RX_MODE_RSS_TCP_IPV6_HASH_EN    0x00080000
 543 #define  RX_MODE_RSS_ITBL_HASH_BITS_7    0x00700000
 544 #define  RX_MODE_RSS_ENABLE              0x00800000
 545 #define  RX_MODE_IPV6_CSUM_ENABLE        0x01000000
 546 #define  RX_MODE_IPV4_FRAG_FIX           0x02000000
 547 #define MAC_RX_STATUS                   0x0000046c
 548 #define  RX_STATUS_REMOTE_TX_XOFFED      0x00000001
 549 #define  RX_STATUS_XOFF_RCVD             0x00000002
 550 #define  RX_STATUS_XON_RCVD              0x00000004
 551 #define MAC_HASH_REG_0                  0x00000470
 552 #define MAC_HASH_REG_1                  0x00000474
 553 #define MAC_HASH_REG_2                  0x00000478
 554 #define MAC_HASH_REG_3                  0x0000047c
 555 #define MAC_RCV_RULE_0                  0x00000480
 556 #define MAC_RCV_VALUE_0                 0x00000484
 557 #define MAC_RCV_RULE_1                  0x00000488
 558 #define MAC_RCV_VALUE_1                 0x0000048c
 559 #define MAC_RCV_RULE_2                  0x00000490
 560 #define MAC_RCV_VALUE_2                 0x00000494
 561 #define MAC_RCV_RULE_3                  0x00000498
 562 #define MAC_RCV_VALUE_3                 0x0000049c
 563 #define MAC_RCV_RULE_4                  0x000004a0
 564 #define MAC_RCV_VALUE_4                 0x000004a4
 565 #define MAC_RCV_RULE_5                  0x000004a8
 566 #define MAC_RCV_VALUE_5                 0x000004ac
 567 #define MAC_RCV_RULE_6                  0x000004b0
 568 #define MAC_RCV_VALUE_6                 0x000004b4
 569 #define MAC_RCV_RULE_7                  0x000004b8
 570 #define MAC_RCV_VALUE_7                 0x000004bc
 571 #define MAC_RCV_RULE_8                  0x000004c0
 572 #define MAC_RCV_VALUE_8                 0x000004c4
 573 #define MAC_RCV_RULE_9                  0x000004c8
 574 #define MAC_RCV_VALUE_9                 0x000004cc
 575 #define MAC_RCV_RULE_10                 0x000004d0
 576 #define MAC_RCV_VALUE_10                0x000004d4
 577 #define MAC_RCV_RULE_11                 0x000004d8
 578 #define MAC_RCV_VALUE_11                0x000004dc
 579 #define MAC_RCV_RULE_12                 0x000004e0
 580 #define MAC_RCV_VALUE_12                0x000004e4
 581 #define MAC_RCV_RULE_13                 0x000004e8
 582 #define MAC_RCV_VALUE_13                0x000004ec
 583 #define MAC_RCV_RULE_14                 0x000004f0
 584 #define MAC_RCV_VALUE_14                0x000004f4
 585 #define MAC_RCV_RULE_15                 0x000004f8
 586 #define MAC_RCV_VALUE_15                0x000004fc
 587 #define  RCV_RULE_DISABLE_MASK           0x7fffffff
 588 #define MAC_RCV_RULE_CFG                0x00000500
 589 #define  RCV_RULE_CFG_DEFAULT_CLASS     0x00000008
 590 #define MAC_LOW_WMARK_MAX_RX_FRAME      0x00000504
 591 /* 0x508 --> 0x520 unused */
 592 #define MAC_HASHREGU_0                  0x00000520
 593 #define MAC_HASHREGU_1                  0x00000524
 594 #define MAC_HASHREGU_2                  0x00000528
 595 #define MAC_HASHREGU_3                  0x0000052c
 596 #define MAC_EXTADDR_0_HIGH              0x00000530
 597 #define MAC_EXTADDR_0_LOW               0x00000534
 598 #define MAC_EXTADDR_1_HIGH              0x00000538
 599 #define MAC_EXTADDR_1_LOW               0x0000053c
 600 #define MAC_EXTADDR_2_HIGH              0x00000540
 601 #define MAC_EXTADDR_2_LOW               0x00000544
 602 #define MAC_EXTADDR_3_HIGH              0x00000548
 603 #define MAC_EXTADDR_3_LOW               0x0000054c
 604 #define MAC_EXTADDR_4_HIGH              0x00000550
 605 #define MAC_EXTADDR_4_LOW               0x00000554
 606 #define MAC_EXTADDR_5_HIGH              0x00000558
 607 #define MAC_EXTADDR_5_LOW               0x0000055c
 608 #define MAC_EXTADDR_6_HIGH              0x00000560
 609 #define MAC_EXTADDR_6_LOW               0x00000564
 610 #define MAC_EXTADDR_7_HIGH              0x00000568
 611 #define MAC_EXTADDR_7_LOW               0x0000056c
 612 #define MAC_EXTADDR_8_HIGH              0x00000570
 613 #define MAC_EXTADDR_8_LOW               0x00000574
 614 #define MAC_EXTADDR_9_HIGH              0x00000578
 615 #define MAC_EXTADDR_9_LOW               0x0000057c
 616 #define MAC_EXTADDR_10_HIGH             0x00000580
 617 #define MAC_EXTADDR_10_LOW              0x00000584
 618 #define MAC_EXTADDR_11_HIGH             0x00000588
 619 #define MAC_EXTADDR_11_LOW              0x0000058c
 620 #define MAC_SERDES_CFG                  0x00000590
 621 #define  MAC_SERDES_CFG_EDGE_SELECT      0x00001000
 622 #define MAC_SERDES_STAT                 0x00000594
 623 /* 0x598 --> 0x5a0 unused */
 624 #define MAC_PHYCFG1                     0x000005a0
 625 #define  MAC_PHYCFG1_RGMII_INT           0x00000001
 626 #define  MAC_PHYCFG1_RXCLK_TO_MASK       0x00001ff0
 627 #define  MAC_PHYCFG1_RXCLK_TIMEOUT       0x00001000
 628 #define  MAC_PHYCFG1_TXCLK_TO_MASK       0x01ff0000
 629 #define  MAC_PHYCFG1_TXCLK_TIMEOUT       0x01000000
 630 #define  MAC_PHYCFG1_RGMII_EXT_RX_DEC    0x02000000
 631 #define  MAC_PHYCFG1_RGMII_SND_STAT_EN   0x04000000
 632 #define  MAC_PHYCFG1_TXC_DRV             0x20000000
 633 #define MAC_PHYCFG2                     0x000005a4
 634 #define  MAC_PHYCFG2_INBAND_ENABLE       0x00000001
 635 #define  MAC_PHYCFG2_EMODE_MASK_MASK     0x000001c0
 636 #define  MAC_PHYCFG2_EMODE_MASK_AC131    0x000000c0
 637 #define  MAC_PHYCFG2_EMODE_MASK_50610    0x00000100
 638 #define  MAC_PHYCFG2_EMODE_MASK_RT8211   0x00000000
 639 #define  MAC_PHYCFG2_EMODE_MASK_RT8201   0x000001c0
 640 #define  MAC_PHYCFG2_EMODE_COMP_MASK     0x00000e00
 641 #define  MAC_PHYCFG2_EMODE_COMP_AC131    0x00000600
 642 #define  MAC_PHYCFG2_EMODE_COMP_50610    0x00000400
 643 #define  MAC_PHYCFG2_EMODE_COMP_RT8211   0x00000800
 644 #define  MAC_PHYCFG2_EMODE_COMP_RT8201   0x00000000
 645 #define  MAC_PHYCFG2_FMODE_MASK_MASK     0x00007000
 646 #define  MAC_PHYCFG2_FMODE_MASK_AC131    0x00006000
 647 #define  MAC_PHYCFG2_FMODE_MASK_50610    0x00004000
 648 #define  MAC_PHYCFG2_FMODE_MASK_RT8211   0x00000000
 649 #define  MAC_PHYCFG2_FMODE_MASK_RT8201   0x00007000
 650 #define  MAC_PHYCFG2_FMODE_COMP_MASK     0x00038000
 651 #define  MAC_PHYCFG2_FMODE_COMP_AC131    0x00030000
 652 #define  MAC_PHYCFG2_FMODE_COMP_50610    0x00008000
 653 #define  MAC_PHYCFG2_FMODE_COMP_RT8211   0x00038000
 654 #define  MAC_PHYCFG2_FMODE_COMP_RT8201   0x00000000
 655 #define  MAC_PHYCFG2_GMODE_MASK_MASK     0x001c0000
 656 #define  MAC_PHYCFG2_GMODE_MASK_AC131    0x001c0000
 657 #define  MAC_PHYCFG2_GMODE_MASK_50610    0x00100000
 658 #define  MAC_PHYCFG2_GMODE_MASK_RT8211   0x00000000
 659 #define  MAC_PHYCFG2_GMODE_MASK_RT8201   0x001c0000
 660 #define  MAC_PHYCFG2_GMODE_COMP_MASK     0x00e00000
 661 #define  MAC_PHYCFG2_GMODE_COMP_AC131    0x00e00000
 662 #define  MAC_PHYCFG2_GMODE_COMP_50610    0x00000000
 663 #define  MAC_PHYCFG2_GMODE_COMP_RT8211   0x00200000
 664 #define  MAC_PHYCFG2_GMODE_COMP_RT8201   0x00000000
 665 #define  MAC_PHYCFG2_ACT_MASK_MASK       0x03000000
 666 #define  MAC_PHYCFG2_ACT_MASK_AC131      0x03000000
 667 #define  MAC_PHYCFG2_ACT_MASK_50610      0x01000000
 668 #define  MAC_PHYCFG2_ACT_MASK_RT8211     0x03000000
 669 #define  MAC_PHYCFG2_ACT_MASK_RT8201     0x01000000
 670 #define  MAC_PHYCFG2_ACT_COMP_MASK       0x0c000000
 671 #define  MAC_PHYCFG2_ACT_COMP_AC131      0x00000000
 672 #define  MAC_PHYCFG2_ACT_COMP_50610      0x00000000
 673 #define  MAC_PHYCFG2_ACT_COMP_RT8211     0x00000000
 674 #define  MAC_PHYCFG2_ACT_COMP_RT8201     0x08000000
 675 #define  MAC_PHYCFG2_QUAL_MASK_MASK      0x30000000
 676 #define  MAC_PHYCFG2_QUAL_MASK_AC131     0x30000000
 677 #define  MAC_PHYCFG2_QUAL_MASK_50610     0x30000000
 678 #define  MAC_PHYCFG2_QUAL_MASK_RT8211    0x30000000
 679 #define  MAC_PHYCFG2_QUAL_MASK_RT8201    0x30000000
 680 #define  MAC_PHYCFG2_QUAL_COMP_MASK      0xc0000000
 681 #define  MAC_PHYCFG2_QUAL_COMP_AC131     0x00000000
 682 #define  MAC_PHYCFG2_QUAL_COMP_50610     0x00000000
 683 #define  MAC_PHYCFG2_QUAL_COMP_RT8211    0x00000000
 684 #define  MAC_PHYCFG2_QUAL_COMP_RT8201    0x00000000
 685 #define MAC_PHYCFG2_50610_LED_MODES \
 686         (MAC_PHYCFG2_EMODE_MASK_50610 | \
 687          MAC_PHYCFG2_EMODE_COMP_50610 | \
 688          MAC_PHYCFG2_FMODE_MASK_50610 | \
 689          MAC_PHYCFG2_FMODE_COMP_50610 | \
 690          MAC_PHYCFG2_GMODE_MASK_50610 | \
 691          MAC_PHYCFG2_GMODE_COMP_50610 | \
 692          MAC_PHYCFG2_ACT_MASK_50610 | \
 693          MAC_PHYCFG2_ACT_COMP_50610 | \
 694          MAC_PHYCFG2_QUAL_MASK_50610 | \
 695          MAC_PHYCFG2_QUAL_COMP_50610)
 696 #define MAC_PHYCFG2_AC131_LED_MODES \
 697         (MAC_PHYCFG2_EMODE_MASK_AC131 | \
 698          MAC_PHYCFG2_EMODE_COMP_AC131 | \
 699          MAC_PHYCFG2_FMODE_MASK_AC131 | \
 700          MAC_PHYCFG2_FMODE_COMP_AC131 | \
 701          MAC_PHYCFG2_GMODE_MASK_AC131 | \
 702          MAC_PHYCFG2_GMODE_COMP_AC131 | \
 703          MAC_PHYCFG2_ACT_MASK_AC131 | \
 704          MAC_PHYCFG2_ACT_COMP_AC131 | \
 705          MAC_PHYCFG2_QUAL_MASK_AC131 | \
 706          MAC_PHYCFG2_QUAL_COMP_AC131)
 707 #define MAC_PHYCFG2_RTL8211C_LED_MODES \
 708         (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
 709          MAC_PHYCFG2_EMODE_COMP_RT8211 | \
 710          MAC_PHYCFG2_FMODE_MASK_RT8211 | \
 711          MAC_PHYCFG2_FMODE_COMP_RT8211 | \
 712          MAC_PHYCFG2_GMODE_MASK_RT8211 | \
 713          MAC_PHYCFG2_GMODE_COMP_RT8211 | \
 714          MAC_PHYCFG2_ACT_MASK_RT8211 | \
 715          MAC_PHYCFG2_ACT_COMP_RT8211 | \
 716          MAC_PHYCFG2_QUAL_MASK_RT8211 | \
 717          MAC_PHYCFG2_QUAL_COMP_RT8211)
 718 #define MAC_PHYCFG2_RTL8201E_LED_MODES \
 719         (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
 720          MAC_PHYCFG2_EMODE_COMP_RT8201 | \
 721          MAC_PHYCFG2_FMODE_MASK_RT8201 | \
 722          MAC_PHYCFG2_FMODE_COMP_RT8201 | \
 723          MAC_PHYCFG2_GMODE_MASK_RT8201 | \
 724          MAC_PHYCFG2_GMODE_COMP_RT8201 | \
 725          MAC_PHYCFG2_ACT_MASK_RT8201 | \
 726          MAC_PHYCFG2_ACT_COMP_RT8201 | \
 727          MAC_PHYCFG2_QUAL_MASK_RT8201 | \
 728          MAC_PHYCFG2_QUAL_COMP_RT8201)
 729 #define MAC_EXT_RGMII_MODE              0x000005a8
 730 #define  MAC_RGMII_MODE_TX_ENABLE        0x00000001
 731 #define  MAC_RGMII_MODE_TX_LOWPWR        0x00000002
 732 #define  MAC_RGMII_MODE_TX_RESET         0x00000004
 733 #define  MAC_RGMII_MODE_RX_INT_B         0x00000100
 734 #define  MAC_RGMII_MODE_RX_QUALITY       0x00000200
 735 #define  MAC_RGMII_MODE_RX_ACTIVITY      0x00000400
 736 #define  MAC_RGMII_MODE_RX_ENG_DET       0x00000800
 737 /* 0x5ac --> 0x5b0 unused */
 738 #define SERDES_RX_CTRL                  0x000005b0      /* 5780/5714 only */
 739 #define  SERDES_RX_SIG_DETECT            0x00000400
 740 #define SG_DIG_CTRL                     0x000005b0
 741 #define  SG_DIG_USING_HW_AUTONEG         0x80000000
 742 #define  SG_DIG_SOFT_RESET               0x40000000
 743 #define  SG_DIG_DISABLE_LINKRDY          0x20000000
 744 #define  SG_DIG_CRC16_CLEAR_N            0x01000000
 745 #define  SG_DIG_EN10B                    0x00800000
 746 #define  SG_DIG_CLEAR_STATUS             0x00400000
 747 #define  SG_DIG_LOCAL_DUPLEX_STATUS      0x00200000
 748 #define  SG_DIG_LOCAL_LINK_STATUS        0x00100000
 749 #define  SG_DIG_SPEED_STATUS_MASK        0x000c0000
 750 #define  SG_DIG_SPEED_STATUS_SHIFT       18
 751 #define  SG_DIG_JUMBO_PACKET_DISABLE     0x00020000
 752 #define  SG_DIG_RESTART_AUTONEG          0x00010000
 753 #define  SG_DIG_FIBER_MODE               0x00008000
 754 #define  SG_DIG_REMOTE_FAULT_MASK        0x00006000
 755 #define  SG_DIG_PAUSE_MASK               0x00001800
 756 #define  SG_DIG_PAUSE_CAP                0x00000800
 757 #define  SG_DIG_ASYM_PAUSE               0x00001000
 758 #define  SG_DIG_GBIC_ENABLE              0x00000400
 759 #define  SG_DIG_CHECK_END_ENABLE         0x00000200
 760 #define  SG_DIG_SGMII_AUTONEG_TIMER      0x00000100
 761 #define  SG_DIG_CLOCK_PHASE_SELECT       0x00000080
 762 #define  SG_DIG_GMII_INPUT_SELECT        0x00000040
 763 #define  SG_DIG_MRADV_CRC16_SELECT       0x00000020
 764 #define  SG_DIG_COMMA_DETECT_ENABLE      0x00000010
 765 #define  SG_DIG_AUTONEG_TIMER_REDUCE     0x00000008
 766 #define  SG_DIG_AUTONEG_LOW_ENABLE       0x00000004
 767 #define  SG_DIG_REMOTE_LOOPBACK          0x00000002
 768 #define  SG_DIG_LOOPBACK                 0x00000001
 769 #define  SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
 770                               SG_DIG_LOCAL_DUPLEX_STATUS | \
 771                               SG_DIG_LOCAL_LINK_STATUS | \
 772                               (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
 773                               SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
 774 #define SG_DIG_STATUS                   0x000005b4
 775 #define  SG_DIG_CRC16_BUS_MASK           0xffff0000
 776 #define  SG_DIG_PARTNER_FAULT_MASK       0x00600000 /* If !MRADV_CRC16_SELECT */
 777 #define  SG_DIG_PARTNER_ASYM_PAUSE       0x00100000 /* If !MRADV_CRC16_SELECT */
 778 #define  SG_DIG_PARTNER_PAUSE_CAPABLE    0x00080000 /* If !MRADV_CRC16_SELECT */
 779 #define  SG_DIG_PARTNER_HALF_DUPLEX      0x00040000 /* If !MRADV_CRC16_SELECT */
 780 #define  SG_DIG_PARTNER_FULL_DUPLEX      0x00020000 /* If !MRADV_CRC16_SELECT */
 781 #define  SG_DIG_PARTNER_NEXT_PAGE        0x00010000 /* If !MRADV_CRC16_SELECT */
 782 #define  SG_DIG_AUTONEG_STATE_MASK       0x00000ff0
 783 #define  SG_DIG_IS_SERDES                0x00000100
 784 #define  SG_DIG_COMMA_DETECTOR           0x00000008
 785 #define  SG_DIG_MAC_ACK_STATUS           0x00000004
 786 #define  SG_DIG_AUTONEG_COMPLETE         0x00000002
 787 #define  SG_DIG_AUTONEG_ERROR            0x00000001
 788 #define TG3_TX_TSTAMP_LSB               0x000005c0
 789 #define TG3_TX_TSTAMP_MSB               0x000005c4
 790 #define  TG3_TSTAMP_MASK                 0x7fffffffffffffffLL
 791 /* 0x5c8 --> 0x600 unused */
 792 #define MAC_TX_MAC_STATE_BASE           0x00000600 /* 16 bytes */
 793 #define MAC_RX_MAC_STATE_BASE           0x00000610 /* 20 bytes */
 794 /* 0x624 --> 0x670 unused */
 795 
 796 #define MAC_RSS_INDIR_TBL_0             0x00000630
 797 
 798 #define MAC_RSS_HASH_KEY_0              0x00000670
 799 #define MAC_RSS_HASH_KEY_1              0x00000674
 800 #define MAC_RSS_HASH_KEY_2              0x00000678
 801 #define MAC_RSS_HASH_KEY_3              0x0000067c
 802 #define MAC_RSS_HASH_KEY_4              0x00000680
 803 #define MAC_RSS_HASH_KEY_5              0x00000684
 804 #define MAC_RSS_HASH_KEY_6              0x00000688
 805 #define MAC_RSS_HASH_KEY_7              0x0000068c
 806 #define MAC_RSS_HASH_KEY_8              0x00000690
 807 #define MAC_RSS_HASH_KEY_9              0x00000694
 808 /* 0x698 --> 0x6b0 unused */
 809 
 810 #define TG3_RX_TSTAMP_LSB               0x000006b0
 811 #define TG3_RX_TSTAMP_MSB               0x000006b4
 812 /* 0x6b8 --> 0x6c8 unused */
 813 
 814 #define TG3_RX_PTP_CTL                  0x000006c8
 815 #define TG3_RX_PTP_CTL_SYNC_EVNT        0x00000001
 816 #define TG3_RX_PTP_CTL_DELAY_REQ        0x00000002
 817 #define TG3_RX_PTP_CTL_PDLAY_REQ        0x00000004
 818 #define TG3_RX_PTP_CTL_PDLAY_RES        0x00000008
 819 #define TG3_RX_PTP_CTL_ALL_V1_EVENTS    (TG3_RX_PTP_CTL_SYNC_EVNT | \
 820                                          TG3_RX_PTP_CTL_DELAY_REQ)
 821 #define TG3_RX_PTP_CTL_ALL_V2_EVENTS    (TG3_RX_PTP_CTL_SYNC_EVNT | \
 822                                          TG3_RX_PTP_CTL_DELAY_REQ | \
 823                                          TG3_RX_PTP_CTL_PDLAY_REQ | \
 824                                          TG3_RX_PTP_CTL_PDLAY_RES)
 825 #define TG3_RX_PTP_CTL_FOLLOW_UP        0x00000100
 826 #define TG3_RX_PTP_CTL_DELAY_RES        0x00000200
 827 #define TG3_RX_PTP_CTL_PDRES_FLW_UP     0x00000400
 828 #define TG3_RX_PTP_CTL_ANNOUNCE         0x00000800
 829 #define TG3_RX_PTP_CTL_SIGNALING        0x00001000
 830 #define TG3_RX_PTP_CTL_MANAGEMENT       0x00002000
 831 #define TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN  0x00800000
 832 #define TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN  0x01000000
 833 #define TG3_RX_PTP_CTL_RX_PTP_V2_EN     (TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | \
 834                                          TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN)
 835 #define TG3_RX_PTP_CTL_RX_PTP_V1_EN     0x02000000
 836 #define TG3_RX_PTP_CTL_HWTS_INTERLOCK   0x04000000
 837 /* 0x6cc --> 0x800 unused */
 838 
 839 #define MAC_TX_STATS_OCTETS             0x00000800
 840 #define MAC_TX_STATS_RESV1              0x00000804
 841 #define MAC_TX_STATS_COLLISIONS         0x00000808
 842 #define MAC_TX_STATS_XON_SENT           0x0000080c
 843 #define MAC_TX_STATS_XOFF_SENT          0x00000810
 844 #define MAC_TX_STATS_RESV2              0x00000814
 845 #define MAC_TX_STATS_MAC_ERRORS         0x00000818
 846 #define MAC_TX_STATS_SINGLE_COLLISIONS  0x0000081c
 847 #define MAC_TX_STATS_MULT_COLLISIONS    0x00000820
 848 #define MAC_TX_STATS_DEFERRED           0x00000824
 849 #define MAC_TX_STATS_RESV3              0x00000828
 850 #define MAC_TX_STATS_EXCESSIVE_COL      0x0000082c
 851 #define MAC_TX_STATS_LATE_COL           0x00000830
 852 #define MAC_TX_STATS_RESV4_1            0x00000834
 853 #define MAC_TX_STATS_RESV4_2            0x00000838
 854 #define MAC_TX_STATS_RESV4_3            0x0000083c
 855 #define MAC_TX_STATS_RESV4_4            0x00000840
 856 #define MAC_TX_STATS_RESV4_5            0x00000844
 857 #define MAC_TX_STATS_RESV4_6            0x00000848
 858 #define MAC_TX_STATS_RESV4_7            0x0000084c
 859 #define MAC_TX_STATS_RESV4_8            0x00000850
 860 #define MAC_TX_STATS_RESV4_9            0x00000854
 861 #define MAC_TX_STATS_RESV4_10           0x00000858
 862 #define MAC_TX_STATS_RESV4_11           0x0000085c
 863 #define MAC_TX_STATS_RESV4_12           0x00000860
 864 #define MAC_TX_STATS_RESV4_13           0x00000864
 865 #define MAC_TX_STATS_RESV4_14           0x00000868
 866 #define MAC_TX_STATS_UCAST              0x0000086c
 867 #define MAC_TX_STATS_MCAST              0x00000870
 868 #define MAC_TX_STATS_BCAST              0x00000874
 869 #define MAC_TX_STATS_RESV5_1            0x00000878
 870 #define MAC_TX_STATS_RESV5_2            0x0000087c
 871 #define MAC_RX_STATS_OCTETS             0x00000880
 872 #define MAC_RX_STATS_RESV1              0x00000884
 873 #define MAC_RX_STATS_FRAGMENTS          0x00000888
 874 #define MAC_RX_STATS_UCAST              0x0000088c
 875 #define MAC_RX_STATS_MCAST              0x00000890
 876 #define MAC_RX_STATS_BCAST              0x00000894
 877 #define MAC_RX_STATS_FCS_ERRORS         0x00000898
 878 #define MAC_RX_STATS_ALIGN_ERRORS       0x0000089c
 879 #define MAC_RX_STATS_XON_PAUSE_RECVD    0x000008a0
 880 #define MAC_RX_STATS_XOFF_PAUSE_RECVD   0x000008a4
 881 #define MAC_RX_STATS_MAC_CTRL_RECVD     0x000008a8
 882 #define MAC_RX_STATS_XOFF_ENTERED       0x000008ac
 883 #define MAC_RX_STATS_FRAME_TOO_LONG     0x000008b0
 884 #define MAC_RX_STATS_JABBERS            0x000008b4
 885 #define MAC_RX_STATS_UNDERSIZE          0x000008b8
 886 /* 0x8bc --> 0xc00 unused */
 887 
 888 /* Send data initiator control registers */
 889 #define SNDDATAI_MODE                   0x00000c00
 890 #define  SNDDATAI_MODE_RESET             0x00000001
 891 #define  SNDDATAI_MODE_ENABLE            0x00000002
 892 #define  SNDDATAI_MODE_STAT_OFLOW_ENAB   0x00000004
 893 #define SNDDATAI_STATUS                 0x00000c04
 894 #define  SNDDATAI_STATUS_STAT_OFLOW      0x00000004
 895 #define SNDDATAI_STATSCTRL              0x00000c08
 896 #define  SNDDATAI_SCTRL_ENABLE           0x00000001
 897 #define  SNDDATAI_SCTRL_FASTUPD          0x00000002
 898 #define  SNDDATAI_SCTRL_CLEAR            0x00000004
 899 #define  SNDDATAI_SCTRL_FLUSH            0x00000008
 900 #define  SNDDATAI_SCTRL_FORCE_ZERO       0x00000010
 901 #define SNDDATAI_STATSENAB              0x00000c0c
 902 #define SNDDATAI_STATSINCMASK           0x00000c10
 903 #define ISO_PKT_TX                      0x00000c20
 904 /* 0xc24 --> 0xc80 unused */
 905 #define SNDDATAI_COS_CNT_0              0x00000c80
 906 #define SNDDATAI_COS_CNT_1              0x00000c84
 907 #define SNDDATAI_COS_CNT_2              0x00000c88
 908 #define SNDDATAI_COS_CNT_3              0x00000c8c
 909 #define SNDDATAI_COS_CNT_4              0x00000c90
 910 #define SNDDATAI_COS_CNT_5              0x00000c94
 911 #define SNDDATAI_COS_CNT_6              0x00000c98
 912 #define SNDDATAI_COS_CNT_7              0x00000c9c
 913 #define SNDDATAI_COS_CNT_8              0x00000ca0
 914 #define SNDDATAI_COS_CNT_9              0x00000ca4
 915 #define SNDDATAI_COS_CNT_10             0x00000ca8
 916 #define SNDDATAI_COS_CNT_11             0x00000cac
 917 #define SNDDATAI_COS_CNT_12             0x00000cb0
 918 #define SNDDATAI_COS_CNT_13             0x00000cb4
 919 #define SNDDATAI_COS_CNT_14             0x00000cb8
 920 #define SNDDATAI_COS_CNT_15             0x00000cbc
 921 #define SNDDATAI_DMA_RDQ_FULL_CNT       0x00000cc0
 922 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT  0x00000cc4
 923 #define SNDDATAI_SDCQ_FULL_CNT          0x00000cc8
 924 #define SNDDATAI_NICRNG_SSND_PIDX_CNT   0x00000ccc
 925 #define SNDDATAI_STATS_UPDATED_CNT      0x00000cd0
 926 #define SNDDATAI_INTERRUPTS_CNT         0x00000cd4
 927 #define SNDDATAI_AVOID_INTERRUPTS_CNT   0x00000cd8
 928 #define SNDDATAI_SND_THRESH_HIT_CNT     0x00000cdc
 929 /* 0xce0 --> 0x1000 unused */
 930 
 931 /* Send data completion control registers */
 932 #define SNDDATAC_MODE                   0x00001000
 933 #define  SNDDATAC_MODE_RESET             0x00000001
 934 #define  SNDDATAC_MODE_ENABLE            0x00000002
 935 #define  SNDDATAC_MODE_CDELAY            0x00000010
 936 /* 0x1004 --> 0x1400 unused */
 937 
 938 /* Send BD ring selector */
 939 #define SNDBDS_MODE                     0x00001400
 940 #define  SNDBDS_MODE_RESET               0x00000001
 941 #define  SNDBDS_MODE_ENABLE              0x00000002
 942 #define  SNDBDS_MODE_ATTN_ENABLE         0x00000004
 943 #define SNDBDS_STATUS                   0x00001404
 944 #define  SNDBDS_STATUS_ERROR_ATTN        0x00000004
 945 #define SNDBDS_HWDIAG                   0x00001408
 946 /* 0x140c --> 0x1440 */
 947 #define SNDBDS_SEL_CON_IDX_0            0x00001440
 948 #define SNDBDS_SEL_CON_IDX_1            0x00001444
 949 #define SNDBDS_SEL_CON_IDX_2            0x00001448
 950 #define SNDBDS_SEL_CON_IDX_3            0x0000144c
 951 #define SNDBDS_SEL_CON_IDX_4            0x00001450
 952 #define SNDBDS_SEL_CON_IDX_5            0x00001454
 953 #define SNDBDS_SEL_CON_IDX_6            0x00001458
 954 #define SNDBDS_SEL_CON_IDX_7            0x0000145c
 955 #define SNDBDS_SEL_CON_IDX_8            0x00001460
 956 #define SNDBDS_SEL_CON_IDX_9            0x00001464
 957 #define SNDBDS_SEL_CON_IDX_10           0x00001468
 958 #define SNDBDS_SEL_CON_IDX_11           0x0000146c
 959 #define SNDBDS_SEL_CON_IDX_12           0x00001470
 960 #define SNDBDS_SEL_CON_IDX_13           0x00001474
 961 #define SNDBDS_SEL_CON_IDX_14           0x00001478
 962 #define SNDBDS_SEL_CON_IDX_15           0x0000147c
 963 /* 0x1480 --> 0x1800 unused */
 964 
 965 /* Send BD initiator control registers */
 966 #define SNDBDI_MODE                     0x00001800
 967 #define  SNDBDI_MODE_RESET               0x00000001
 968 #define  SNDBDI_MODE_ENABLE              0x00000002
 969 #define  SNDBDI_MODE_ATTN_ENABLE         0x00000004
 970 #define  SNDBDI_MODE_MULTI_TXQ_EN        0x00000020
 971 #define SNDBDI_STATUS                   0x00001804
 972 #define  SNDBDI_STATUS_ERROR_ATTN        0x00000004
 973 #define SNDBDI_IN_PROD_IDX_0            0x00001808
 974 #define SNDBDI_IN_PROD_IDX_1            0x0000180c
 975 #define SNDBDI_IN_PROD_IDX_2            0x00001810
 976 #define SNDBDI_IN_PROD_IDX_3            0x00001814
 977 #define SNDBDI_IN_PROD_IDX_4            0x00001818
 978 #define SNDBDI_IN_PROD_IDX_5            0x0000181c
 979 #define SNDBDI_IN_PROD_IDX_6            0x00001820
 980 #define SNDBDI_IN_PROD_IDX_7            0x00001824
 981 #define SNDBDI_IN_PROD_IDX_8            0x00001828
 982 #define SNDBDI_IN_PROD_IDX_9            0x0000182c
 983 #define SNDBDI_IN_PROD_IDX_10           0x00001830
 984 #define SNDBDI_IN_PROD_IDX_11           0x00001834
 985 #define SNDBDI_IN_PROD_IDX_12           0x00001838
 986 #define SNDBDI_IN_PROD_IDX_13           0x0000183c
 987 #define SNDBDI_IN_PROD_IDX_14           0x00001840
 988 #define SNDBDI_IN_PROD_IDX_15           0x00001844
 989 /* 0x1848 --> 0x1c00 unused */
 990 
 991 /* Send BD completion control registers */
 992 #define SNDBDC_MODE                     0x00001c00
 993 #define SNDBDC_MODE_RESET                0x00000001
 994 #define SNDBDC_MODE_ENABLE               0x00000002
 995 #define SNDBDC_MODE_ATTN_ENABLE          0x00000004
 996 /* 0x1c04 --> 0x2000 unused */
 997 
 998 /* Receive list placement control registers */
 999 #define RCVLPC_MODE                     0x00002000
1000 #define  RCVLPC_MODE_RESET               0x00000001
1001 #define  RCVLPC_MODE_ENABLE              0x00000002
1002 #define  RCVLPC_MODE_CLASS0_ATTN_ENAB    0x00000004
1003 #define  RCVLPC_MODE_MAPOOR_AATTN_ENAB   0x00000008
1004 #define  RCVLPC_MODE_STAT_OFLOW_ENAB     0x00000010
1005 #define RCVLPC_STATUS                   0x00002004
1006 #define  RCVLPC_STATUS_CLASS0            0x00000004
1007 #define  RCVLPC_STATUS_MAPOOR            0x00000008
1008 #define  RCVLPC_STATUS_STAT_OFLOW        0x00000010
1009 #define RCVLPC_LOCK                     0x00002008
1010 #define  RCVLPC_LOCK_REQ_MASK            0x0000ffff
1011 #define  RCVLPC_LOCK_REQ_SHIFT           0
1012 #define  RCVLPC_LOCK_GRANT_MASK          0xffff0000
1013 #define  RCVLPC_LOCK_GRANT_SHIFT         16
1014 #define RCVLPC_NON_EMPTY_BITS           0x0000200c
1015 #define  RCVLPC_NON_EMPTY_BITS_MASK      0x0000ffff
1016 #define RCVLPC_CONFIG                   0x00002010
1017 #define RCVLPC_STATSCTRL                0x00002014
1018 #define  RCVLPC_STATSCTRL_ENABLE         0x00000001
1019 #define  RCVLPC_STATSCTRL_FASTUPD        0x00000002
1020 #define RCVLPC_STATS_ENABLE             0x00002018
1021 #define  RCVLPC_STATSENAB_ASF_FIX        0x00000002
1022 #define  RCVLPC_STATSENAB_DACK_FIX       0x00040000
1023 #define  RCVLPC_STATSENAB_LNGBRST_RFIX   0x00400000
1024 #define RCVLPC_STATS_INCMASK            0x0000201c
1025 /* 0x2020 --> 0x2100 unused */
1026 #define RCVLPC_SELLST_BASE              0x00002100 /* 16 16-byte entries */
1027 #define  SELLST_TAIL                    0x00000004
1028 #define  SELLST_CONT                    0x00000008
1029 #define  SELLST_UNUSED                  0x0000000c
1030 #define RCVLPC_COS_CNTL_BASE            0x00002200 /* 16 4-byte entries */
1031 #define RCVLPC_DROP_FILTER_CNT          0x00002240
1032 #define RCVLPC_DMA_WQ_FULL_CNT          0x00002244
1033 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT   0x00002248
1034 #define RCVLPC_NO_RCV_BD_CNT            0x0000224c
1035 #define RCVLPC_IN_DISCARDS_CNT          0x00002250
1036 #define RCVLPC_IN_ERRORS_CNT            0x00002254
1037 #define RCVLPC_RCV_THRESH_HIT_CNT       0x00002258
1038 /* 0x225c --> 0x2400 unused */
1039 
1040 /* Receive Data and Receive BD Initiator Control */
1041 #define RCVDBDI_MODE                    0x00002400
1042 #define  RCVDBDI_MODE_RESET              0x00000001
1043 #define  RCVDBDI_MODE_ENABLE             0x00000002
1044 #define  RCVDBDI_MODE_JUMBOBD_NEEDED     0x00000004
1045 #define  RCVDBDI_MODE_FRM_TOO_BIG        0x00000008
1046 #define  RCVDBDI_MODE_INV_RING_SZ        0x00000010
1047 #define  RCVDBDI_MODE_LRG_RING_SZ        0x00010000
1048 #define RCVDBDI_STATUS                  0x00002404
1049 #define  RCVDBDI_STATUS_JUMBOBD_NEEDED   0x00000004
1050 #define  RCVDBDI_STATUS_FRM_TOO_BIG      0x00000008
1051 #define  RCVDBDI_STATUS_INV_RING_SZ      0x00000010
1052 #define RCVDBDI_SPLIT_FRAME_MINSZ       0x00002408
1053 /* 0x240c --> 0x2440 unused */
1054 #define RCVDBDI_JUMBO_BD                0x00002440 /* TG3_BDINFO_... */
1055 #define RCVDBDI_STD_BD                  0x00002450 /* TG3_BDINFO_... */
1056 #define RCVDBDI_MINI_BD                 0x00002460 /* TG3_BDINFO_... */
1057 #define RCVDBDI_JUMBO_CON_IDX           0x00002470
1058 #define RCVDBDI_STD_CON_IDX             0x00002474
1059 #define RCVDBDI_MINI_CON_IDX            0x00002478
1060 /* 0x247c --> 0x2480 unused */
1061 #define RCVDBDI_BD_PROD_IDX_0           0x00002480
1062 #define RCVDBDI_BD_PROD_IDX_1           0x00002484
1063 #define RCVDBDI_BD_PROD_IDX_2           0x00002488
1064 #define RCVDBDI_BD_PROD_IDX_3           0x0000248c
1065 #define RCVDBDI_BD_PROD_IDX_4           0x00002490
1066 #define RCVDBDI_BD_PROD_IDX_5           0x00002494
1067 #define RCVDBDI_BD_PROD_IDX_6           0x00002498
1068 #define RCVDBDI_BD_PROD_IDX_7           0x0000249c
1069 #define RCVDBDI_BD_PROD_IDX_8           0x000024a0
1070 #define RCVDBDI_BD_PROD_IDX_9           0x000024a4
1071 #define RCVDBDI_BD_PROD_IDX_10          0x000024a8
1072 #define RCVDBDI_BD_PROD_IDX_11          0x000024ac
1073 #define RCVDBDI_BD_PROD_IDX_12          0x000024b0
1074 #define RCVDBDI_BD_PROD_IDX_13          0x000024b4
1075 #define RCVDBDI_BD_PROD_IDX_14          0x000024b8
1076 #define RCVDBDI_BD_PROD_IDX_15          0x000024bc
1077 #define RCVDBDI_HWDIAG                  0x000024c0
1078 /* 0x24c4 --> 0x2800 unused */
1079 
1080 /* Receive Data Completion Control */
1081 #define RCVDCC_MODE                     0x00002800
1082 #define  RCVDCC_MODE_RESET               0x00000001
1083 #define  RCVDCC_MODE_ENABLE              0x00000002
1084 #define  RCVDCC_MODE_ATTN_ENABLE         0x00000004
1085 /* 0x2804 --> 0x2c00 unused */
1086 
1087 /* Receive BD Initiator Control Registers */
1088 #define RCVBDI_MODE                     0x00002c00
1089 #define  RCVBDI_MODE_RESET               0x00000001
1090 #define  RCVBDI_MODE_ENABLE              0x00000002
1091 #define  RCVBDI_MODE_RCB_ATTN_ENAB       0x00000004
1092 #define RCVBDI_STATUS                   0x00002c04
1093 #define  RCVBDI_STATUS_RCB_ATTN          0x00000004
1094 #define RCVBDI_JUMBO_PROD_IDX           0x00002c08
1095 #define RCVBDI_STD_PROD_IDX             0x00002c0c
1096 #define RCVBDI_MINI_PROD_IDX            0x00002c10
1097 #define RCVBDI_MINI_THRESH              0x00002c14
1098 #define RCVBDI_STD_THRESH               0x00002c18
1099 #define RCVBDI_JUMBO_THRESH             0x00002c1c
1100 /* 0x2c20 --> 0x2d00 unused */
1101 
1102 #define STD_REPLENISH_LWM               0x00002d00
1103 #define JMB_REPLENISH_LWM               0x00002d04
1104 /* 0x2d08 --> 0x3000 unused */
1105 
1106 /* Receive BD Completion Control Registers */
1107 #define RCVCC_MODE                      0x00003000
1108 #define  RCVCC_MODE_RESET                0x00000001
1109 #define  RCVCC_MODE_ENABLE               0x00000002
1110 #define  RCVCC_MODE_ATTN_ENABLE          0x00000004
1111 #define RCVCC_STATUS                    0x00003004
1112 #define  RCVCC_STATUS_ERROR_ATTN         0x00000004
1113 #define RCVCC_JUMP_PROD_IDX             0x00003008
1114 #define RCVCC_STD_PROD_IDX              0x0000300c
1115 #define RCVCC_MINI_PROD_IDX             0x00003010
1116 /* 0x3014 --> 0x3400 unused */
1117 
1118 /* Receive list selector control registers */
1119 #define RCVLSC_MODE                     0x00003400
1120 #define  RCVLSC_MODE_RESET               0x00000001
1121 #define  RCVLSC_MODE_ENABLE              0x00000002
1122 #define  RCVLSC_MODE_ATTN_ENABLE         0x00000004
1123 #define RCVLSC_STATUS                   0x00003404
1124 #define  RCVLSC_STATUS_ERROR_ATTN        0x00000004
1125 /* 0x3408 --> 0x3600 unused */
1126 
1127 #define TG3_CPMU_DRV_STATUS             0x0000344c
1128 
1129 /* CPMU registers */
1130 #define TG3_CPMU_CTRL                   0x00003600
1131 #define  CPMU_CTRL_LINK_IDLE_MODE        0x00000200
1132 #define  CPMU_CTRL_LINK_AWARE_MODE       0x00000400
1133 #define  CPMU_CTRL_LINK_SPEED_MODE       0x00004000
1134 #define  CPMU_CTRL_GPHY_10MB_RXONLY      0x00010000
1135 #define TG3_CPMU_LSPD_10MB_CLK          0x00003604
1136 #define  CPMU_LSPD_10MB_MACCLK_MASK      0x001f0000
1137 #define  CPMU_LSPD_10MB_MACCLK_6_25      0x00130000
1138 /* 0x3608 --> 0x360c unused */
1139 
1140 #define TG3_CPMU_LSPD_1000MB_CLK        0x0000360c
1141 #define  CPMU_LSPD_1000MB_MACCLK_62_5    0x00000000
1142 #define  CPMU_LSPD_1000MB_MACCLK_12_5    0x00110000
1143 #define  CPMU_LSPD_1000MB_MACCLK_MASK    0x001f0000
1144 #define TG3_CPMU_LNK_AWARE_PWRMD        0x00003610
1145 #define  CPMU_LNK_AWARE_MACCLK_MASK      0x001f0000
1146 #define  CPMU_LNK_AWARE_MACCLK_6_25      0x00130000
1147 /* 0x3614 --> 0x361c unused */
1148 
1149 #define TG3_CPMU_HST_ACC                0x0000361c
1150 #define  CPMU_HST_ACC_MACCLK_MASK        0x001f0000
1151 #define  CPMU_HST_ACC_MACCLK_6_25        0x00130000
1152 /* 0x3620 --> 0x3630 unused */
1153 
1154 #define TG3_CPMU_CLCK_ORIDE             0x00003624
1155 #define  CPMU_CLCK_ORIDE_MAC_ORIDE_EN    0x80000000
1156 
1157 #define TG3_CPMU_CLCK_ORIDE_ENABLE      0x00003628
1158 #define  TG3_CPMU_MAC_ORIDE_ENABLE       (1 << 13)
1159 
1160 #define TG3_CPMU_STATUS                 0x0000362c
1161 #define  TG3_CPMU_STATUS_FMSK_5717       0x20000000
1162 #define  TG3_CPMU_STATUS_FMSK_5719       0xc0000000
1163 #define  TG3_CPMU_STATUS_FSHFT_5719      30
1164 #define  TG3_CPMU_STATUS_LINK_MASK       0x180000
1165 
1166 #define TG3_CPMU_CLCK_STAT              0x00003630
1167 #define  CPMU_CLCK_STAT_MAC_CLCK_MASK    0x001f0000
1168 #define  CPMU_CLCK_STAT_MAC_CLCK_62_5    0x00000000
1169 #define  CPMU_CLCK_STAT_MAC_CLCK_12_5    0x00110000
1170 #define  CPMU_CLCK_STAT_MAC_CLCK_6_25    0x00130000
1171 /* 0x3634 --> 0x365c unused */
1172 
1173 #define TG3_CPMU_MUTEX_REQ              0x0000365c
1174 #define  CPMU_MUTEX_REQ_DRIVER           0x00001000
1175 #define TG3_CPMU_MUTEX_GNT              0x00003660
1176 #define  CPMU_MUTEX_GNT_DRIVER           0x00001000
1177 #define TG3_CPMU_PHY_STRAP              0x00003664
1178 #define TG3_CPMU_PHY_STRAP_IS_SERDES     0x00000020
1179 #define TG3_CPMU_PADRNG_CTL             0x00003668
1180 #define  TG3_CPMU_PADRNG_CTL_RDIV2       0x00040000
1181 /* 0x3664 --> 0x36b0 unused */
1182 
1183 #define TG3_CPMU_EEE_MODE               0x000036b0
1184 #define  TG3_CPMU_EEEMD_APE_TX_DET_EN    0x00000004
1185 #define  TG3_CPMU_EEEMD_ERLY_L1_XIT_DET  0x00000008
1186 #define  TG3_CPMU_EEEMD_SND_IDX_DET_EN   0x00000040
1187 #define  TG3_CPMU_EEEMD_LPI_ENABLE       0x00000080
1188 #define  TG3_CPMU_EEEMD_LPI_IN_TX        0x00000100
1189 #define  TG3_CPMU_EEEMD_LPI_IN_RX        0x00000200
1190 #define  TG3_CPMU_EEEMD_EEE_ENABLE       0x00100000
1191 #define TG3_CPMU_EEE_DBTMR1             0x000036b4
1192 #define  TG3_CPMU_DBTMR1_PCIEXIT_2047US  0x07ff0000
1193 #define  TG3_CPMU_DBTMR1_LNKIDLE_2047US  0x000007ff
1194 #define  TG3_CPMU_DBTMR1_LNKIDLE_MAX     0x0000ffff
1195 #define TG3_CPMU_EEE_DBTMR2             0x000036b8
1196 #define  TG3_CPMU_DBTMR2_APE_TX_2047US   0x07ff0000
1197 #define  TG3_CPMU_DBTMR2_TXIDXEQ_2047US  0x000007ff
1198 #define TG3_CPMU_EEE_LNKIDL_CTRL        0x000036bc
1199 #define  TG3_CPMU_EEE_LNKIDL_PCIE_NL0    0x01000000
1200 #define  TG3_CPMU_EEE_LNKIDL_UART_IDL    0x00000004
1201 #define  TG3_CPMU_EEE_LNKIDL_APE_TX_MT   0x00000002
1202 /* 0x36c0 --> 0x36d0 unused */
1203 
1204 #define TG3_CPMU_EEE_CTRL               0x000036d0
1205 #define TG3_CPMU_EEE_CTRL_EXIT_16_5_US   0x0000019d
1206 #define TG3_CPMU_EEE_CTRL_EXIT_36_US     0x00000384
1207 #define TG3_CPMU_EEE_CTRL_EXIT_20_1_US   0x000001f8
1208 /* 0x36d4 --> 0x3800 unused */
1209 
1210 /* Mbuf cluster free registers */
1211 #define MBFREE_MODE                     0x00003800
1212 #define  MBFREE_MODE_RESET               0x00000001
1213 #define  MBFREE_MODE_ENABLE              0x00000002
1214 #define MBFREE_STATUS                   0x00003804
1215 /* 0x3808 --> 0x3c00 unused */
1216 
1217 /* Host coalescing control registers */
1218 #define HOSTCC_MODE                     0x00003c00
1219 #define  HOSTCC_MODE_RESET               0x00000001
1220 #define  HOSTCC_MODE_ENABLE              0x00000002
1221 #define  HOSTCC_MODE_ATTN                0x00000004
1222 #define  HOSTCC_MODE_NOW                 0x00000008
1223 #define  HOSTCC_MODE_FULL_STATUS         0x00000000
1224 #define  HOSTCC_MODE_64BYTE              0x00000080
1225 #define  HOSTCC_MODE_32BYTE              0x00000100
1226 #define  HOSTCC_MODE_CLRTICK_RXBD        0x00000200
1227 #define  HOSTCC_MODE_CLRTICK_TXBD        0x00000400
1228 #define  HOSTCC_MODE_NOINT_ON_NOW        0x00000800
1229 #define  HOSTCC_MODE_NOINT_ON_FORCE      0x00001000
1230 #define  HOSTCC_MODE_COAL_VEC1_NOW       0x00002000
1231 #define HOSTCC_STATUS                   0x00003c04
1232 #define  HOSTCC_STATUS_ERROR_ATTN        0x00000004
1233 #define HOSTCC_RXCOL_TICKS              0x00003c08
1234 #define  LOW_RXCOL_TICKS                 0x00000032
1235 #define  LOW_RXCOL_TICKS_CLRTCKS         0x00000014
1236 #define  DEFAULT_RXCOL_TICKS             0x00000048
1237 #define  HIGH_RXCOL_TICKS                0x00000096
1238 #define  MAX_RXCOL_TICKS                 0x000003ff
1239 #define HOSTCC_TXCOL_TICKS              0x00003c0c
1240 #define  LOW_TXCOL_TICKS                 0x00000096
1241 #define  LOW_TXCOL_TICKS_CLRTCKS         0x00000048
1242 #define  DEFAULT_TXCOL_TICKS             0x0000012c
1243 #define  HIGH_TXCOL_TICKS                0x00000145
1244 #define  MAX_TXCOL_TICKS                 0x000003ff
1245 #define HOSTCC_RXMAX_FRAMES             0x00003c10
1246 #define  LOW_RXMAX_FRAMES                0x00000005
1247 #define  DEFAULT_RXMAX_FRAMES            0x00000008
1248 #define  HIGH_RXMAX_FRAMES               0x00000012
1249 #define  MAX_RXMAX_FRAMES                0x000000ff
1250 #define HOSTCC_TXMAX_FRAMES             0x00003c14
1251 #define  LOW_TXMAX_FRAMES                0x00000035
1252 #define  DEFAULT_TXMAX_FRAMES            0x0000004b
1253 #define  HIGH_TXMAX_FRAMES               0x00000052
1254 #define  MAX_TXMAX_FRAMES                0x000000ff
1255 #define HOSTCC_RXCOAL_TICK_INT          0x00003c18
1256 #define  DEFAULT_RXCOAL_TICK_INT         0x00000019
1257 #define  DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
1258 #define  MAX_RXCOAL_TICK_INT             0x000003ff
1259 #define HOSTCC_TXCOAL_TICK_INT          0x00003c1c
1260 #define  DEFAULT_TXCOAL_TICK_INT         0x00000019
1261 #define  DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
1262 #define  MAX_TXCOAL_TICK_INT             0x000003ff
1263 #define HOSTCC_RXCOAL_MAXF_INT          0x00003c20
1264 #define  DEFAULT_RXCOAL_MAXF_INT         0x00000005
1265 #define  MAX_RXCOAL_MAXF_INT             0x000000ff
1266 #define HOSTCC_TXCOAL_MAXF_INT          0x00003c24
1267 #define  DEFAULT_TXCOAL_MAXF_INT         0x00000005
1268 #define  MAX_TXCOAL_MAXF_INT             0x000000ff
1269 #define HOSTCC_STAT_COAL_TICKS          0x00003c28
1270 #define  DEFAULT_STAT_COAL_TICKS         0x000f4240
1271 #define  MAX_STAT_COAL_TICKS             0xd693d400
1272 #define  MIN_STAT_COAL_TICKS             0x00000064
1273 /* 0x3c2c --> 0x3c30 unused */
1274 #define HOSTCC_STATS_BLK_HOST_ADDR      0x00003c30 /* 64-bit */
1275 #define HOSTCC_STATUS_BLK_HOST_ADDR     0x00003c38 /* 64-bit */
1276 #define HOSTCC_STATS_BLK_NIC_ADDR       0x00003c40
1277 #define HOSTCC_STATUS_BLK_NIC_ADDR      0x00003c44
1278 #define HOSTCC_FLOW_ATTN                0x00003c48
1279 #define HOSTCC_FLOW_ATTN_MBUF_LWM        0x00000040
1280 /* 0x3c4c --> 0x3c50 unused */
1281 #define HOSTCC_JUMBO_CON_IDX            0x00003c50
1282 #define HOSTCC_STD_CON_IDX              0x00003c54
1283 #define HOSTCC_MINI_CON_IDX             0x00003c58
1284 /* 0x3c5c --> 0x3c80 unused */
1285 #define HOSTCC_RET_PROD_IDX_0           0x00003c80
1286 #define HOSTCC_RET_PROD_IDX_1           0x00003c84
1287 #define HOSTCC_RET_PROD_IDX_2           0x00003c88
1288 #define HOSTCC_RET_PROD_IDX_3           0x00003c8c
1289 #define HOSTCC_RET_PROD_IDX_4           0x00003c90
1290 #define HOSTCC_RET_PROD_IDX_5           0x00003c94
1291 #define HOSTCC_RET_PROD_IDX_6           0x00003c98
1292 #define HOSTCC_RET_PROD_IDX_7           0x00003c9c
1293 #define HOSTCC_RET_PROD_IDX_8           0x00003ca0
1294 #define HOSTCC_RET_PROD_IDX_9           0x00003ca4
1295 #define HOSTCC_RET_PROD_IDX_10          0x00003ca8
1296 #define HOSTCC_RET_PROD_IDX_11          0x00003cac
1297 #define HOSTCC_RET_PROD_IDX_12          0x00003cb0
1298 #define HOSTCC_RET_PROD_IDX_13          0x00003cb4
1299 #define HOSTCC_RET_PROD_IDX_14          0x00003cb8
1300 #define HOSTCC_RET_PROD_IDX_15          0x00003cbc
1301 #define HOSTCC_SND_CON_IDX_0            0x00003cc0
1302 #define HOSTCC_SND_CON_IDX_1            0x00003cc4
1303 #define HOSTCC_SND_CON_IDX_2            0x00003cc8
1304 #define HOSTCC_SND_CON_IDX_3            0x00003ccc
1305 #define HOSTCC_SND_CON_IDX_4            0x00003cd0
1306 #define HOSTCC_SND_CON_IDX_5            0x00003cd4
1307 #define HOSTCC_SND_CON_IDX_6            0x00003cd8
1308 #define HOSTCC_SND_CON_IDX_7            0x00003cdc
1309 #define HOSTCC_SND_CON_IDX_8            0x00003ce0
1310 #define HOSTCC_SND_CON_IDX_9            0x00003ce4
1311 #define HOSTCC_SND_CON_IDX_10           0x00003ce8
1312 #define HOSTCC_SND_CON_IDX_11           0x00003cec
1313 #define HOSTCC_SND_CON_IDX_12           0x00003cf0
1314 #define HOSTCC_SND_CON_IDX_13           0x00003cf4
1315 #define HOSTCC_SND_CON_IDX_14           0x00003cf8
1316 #define HOSTCC_SND_CON_IDX_15           0x00003cfc
1317 #define HOSTCC_STATBLCK_RING1           0x00003d00
1318 /* 0x3d00 --> 0x3d80 unused */
1319 
1320 #define HOSTCC_RXCOL_TICKS_VEC1         0x00003d80
1321 #define HOSTCC_TXCOL_TICKS_VEC1         0x00003d84
1322 #define HOSTCC_RXMAX_FRAMES_VEC1        0x00003d88
1323 #define HOSTCC_TXMAX_FRAMES_VEC1        0x00003d8c
1324 #define HOSTCC_RXCOAL_MAXF_INT_VEC1     0x00003d90
1325 #define HOSTCC_TXCOAL_MAXF_INT_VEC1     0x00003d94
1326 /* 0x3d98 --> 0x4000 unused */
1327 
1328 /* Memory arbiter control registers */
1329 #define MEMARB_MODE                     0x00004000
1330 #define  MEMARB_MODE_RESET               0x00000001
1331 #define  MEMARB_MODE_ENABLE              0x00000002
1332 #define MEMARB_STATUS                   0x00004004
1333 #define MEMARB_TRAP_ADDR_LOW            0x00004008
1334 #define MEMARB_TRAP_ADDR_HIGH           0x0000400c
1335 /* 0x4010 --> 0x4400 unused */
1336 
1337 /* Buffer manager control registers */
1338 #define BUFMGR_MODE                     0x00004400
1339 #define  BUFMGR_MODE_RESET               0x00000001
1340 #define  BUFMGR_MODE_ENABLE              0x00000002
1341 #define  BUFMGR_MODE_ATTN_ENABLE         0x00000004
1342 #define  BUFMGR_MODE_BM_TEST             0x00000008
1343 #define  BUFMGR_MODE_MBLOW_ATTN_ENAB     0x00000010
1344 #define  BUFMGR_MODE_NO_TX_UNDERRUN      0x80000000
1345 #define BUFMGR_STATUS                   0x00004404
1346 #define  BUFMGR_STATUS_ERROR             0x00000004
1347 #define  BUFMGR_STATUS_MBLOW             0x00000010
1348 #define BUFMGR_MB_POOL_ADDR             0x00004408
1349 #define BUFMGR_MB_POOL_SIZE             0x0000440c
1350 #define BUFMGR_MB_RDMA_LOW_WATER        0x00004410
1351 #define  DEFAULT_MB_RDMA_LOW_WATER       0x00000050
1352 #define  DEFAULT_MB_RDMA_LOW_WATER_5705  0x00000000
1353 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1354 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1355 #define BUFMGR_MB_MACRX_LOW_WATER       0x00004414
1356 #define  DEFAULT_MB_MACRX_LOW_WATER       0x00000020
1357 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
1358 #define  DEFAULT_MB_MACRX_LOW_WATER_5906  0x00000004
1359 #define  DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
1360 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1361 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1362 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
1363 #define BUFMGR_MB_HIGH_WATER            0x00004418
1364 #define  DEFAULT_MB_HIGH_WATER           0x00000060
1365 #define  DEFAULT_MB_HIGH_WATER_5705      0x00000060
1366 #define  DEFAULT_MB_HIGH_WATER_5906      0x00000010
1367 #define  DEFAULT_MB_HIGH_WATER_57765     0x000000a0
1368 #define  DEFAULT_MB_HIGH_WATER_JUMBO     0x0000017c
1369 #define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1370 #define  DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
1371 #define BUFMGR_RX_MB_ALLOC_REQ          0x0000441c
1372 #define  BUFMGR_MB_ALLOC_BIT             0x10000000
1373 #define BUFMGR_RX_MB_ALLOC_RESP         0x00004420
1374 #define BUFMGR_TX_MB_ALLOC_REQ          0x00004424
1375 #define BUFMGR_TX_MB_ALLOC_RESP         0x00004428
1376 #define BUFMGR_DMA_DESC_POOL_ADDR       0x0000442c
1377 #define BUFMGR_DMA_DESC_POOL_SIZE       0x00004430
1378 #define BUFMGR_DMA_LOW_WATER            0x00004434
1379 #define  DEFAULT_DMA_LOW_WATER           0x00000005
1380 #define BUFMGR_DMA_HIGH_WATER           0x00004438
1381 #define  DEFAULT_DMA_HIGH_WATER          0x0000000a
1382 #define BUFMGR_RX_DMA_ALLOC_REQ         0x0000443c
1383 #define BUFMGR_RX_DMA_ALLOC_RESP        0x00004440
1384 #define BUFMGR_TX_DMA_ALLOC_REQ         0x00004444
1385 #define BUFMGR_TX_DMA_ALLOC_RESP        0x00004448
1386 #define BUFMGR_HWDIAG_0                 0x0000444c
1387 #define BUFMGR_HWDIAG_1                 0x00004450
1388 #define BUFMGR_HWDIAG_2                 0x00004454
1389 /* 0x4458 --> 0x4800 unused */
1390 
1391 /* Read DMA control registers */
1392 #define RDMAC_MODE                      0x00004800
1393 #define  RDMAC_MODE_RESET                0x00000001
1394 #define  RDMAC_MODE_ENABLE               0x00000002
1395 #define  RDMAC_MODE_TGTABORT_ENAB        0x00000004
1396 #define  RDMAC_MODE_MSTABORT_ENAB        0x00000008
1397 #define  RDMAC_MODE_PARITYERR_ENAB       0x00000010
1398 #define  RDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1399 #define  RDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1400 #define  RDMAC_MODE_FIFOURUN_ENAB        0x00000080
1401 #define  RDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1402 #define  RDMAC_MODE_LNGREAD_ENAB         0x00000200
1403 #define  RDMAC_MODE_SPLIT_ENABLE         0x00000800
1404 #define  RDMAC_MODE_BD_SBD_CRPT_ENAB     0x00000800
1405 #define  RDMAC_MODE_SPLIT_RESET          0x00001000
1406 #define  RDMAC_MODE_MBUF_RBD_CRPT_ENAB   0x00001000
1407 #define  RDMAC_MODE_MBUF_SBD_CRPT_ENAB   0x00002000
1408 #define  RDMAC_MODE_FIFO_SIZE_128        0x00020000
1409 #define  RDMAC_MODE_FIFO_LONG_BURST      0x00030000
1410 #define  RDMAC_MODE_JMB_2K_MMRR          0x00800000
1411 #define  RDMAC_MODE_MULT_DMA_RD_DIS      0x01000000
1412 #define  RDMAC_MODE_IPV4_LSO_EN          0x08000000
1413 #define  RDMAC_MODE_IPV6_LSO_EN          0x10000000
1414 #define  RDMAC_MODE_H2BNC_VLAN_DET       0x20000000
1415 #define RDMAC_STATUS                    0x00004804
1416 #define  RDMAC_STATUS_TGTABORT           0x00000004
1417 #define  RDMAC_STATUS_MSTABORT           0x00000008
1418 #define  RDMAC_STATUS_PARITYERR          0x00000010
1419 #define  RDMAC_STATUS_ADDROFLOW          0x00000020
1420 #define  RDMAC_STATUS_FIFOOFLOW          0x00000040
1421 #define  RDMAC_STATUS_FIFOURUN           0x00000080
1422 #define  RDMAC_STATUS_FIFOOREAD          0x00000100
1423 #define  RDMAC_STATUS_LNGREAD            0x00000200
1424 /* 0x4808 --> 0x4890 unused */
1425 
1426 #define TG3_RDMA_RSRVCTRL_REG2          0x00004890
1427 #define TG3_LSO_RD_DMA_CRPTEN_CTRL2     0x000048a0
1428 
1429 #define TG3_RDMA_RSRVCTRL_REG           0x00004900
1430 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX  0x00000004
1431 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K  0x00000c00
1432 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK  0x00000ff0
1433 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K  0x000c0000
1434 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK  0x000ff000
1435 #define TG3_RDMA_RSRVCTRL_TXMRGN_320B    0x28000000
1436 #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK    0xffe00000
1437 /* 0x4904 --> 0x4910 unused */
1438 
1439 #define TG3_LSO_RD_DMA_CRPTEN_CTRL      0x00004910
1440 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K    0x00030000
1441 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K   0x000c0000
1442 #define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719         0x02000000
1443 #define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720         0x00200000
1444 /* 0x4914 --> 0x4be0 unused */
1445 
1446 #define TG3_NUM_RDMA_CHANNELS           4
1447 #define TG3_RDMA_LENGTH                 0x00004be0
1448 
1449 /* Write DMA control registers */
1450 #define WDMAC_MODE                      0x00004c00
1451 #define  WDMAC_MODE_RESET                0x00000001
1452 #define  WDMAC_MODE_ENABLE               0x00000002
1453 #define  WDMAC_MODE_TGTABORT_ENAB        0x00000004
1454 #define  WDMAC_MODE_MSTABORT_ENAB        0x00000008
1455 #define  WDMAC_MODE_PARITYERR_ENAB       0x00000010
1456 #define  WDMAC_MODE_ADDROFLOW_ENAB       0x00000020
1457 #define  WDMAC_MODE_FIFOOFLOW_ENAB       0x00000040
1458 #define  WDMAC_MODE_FIFOURUN_ENAB        0x00000080
1459 #define  WDMAC_MODE_FIFOOREAD_ENAB       0x00000100
1460 #define  WDMAC_MODE_LNGREAD_ENAB         0x00000200
1461 #define  WDMAC_MODE_RX_ACCEL             0x00000400
1462 #define  WDMAC_MODE_STATUS_TAG_FIX       0x20000000
1463 #define  WDMAC_MODE_BURST_ALL_DATA       0xc0000000
1464 #define WDMAC_STATUS                    0x00004c04
1465 #define  WDMAC_STATUS_TGTABORT           0x00000004
1466 #define  WDMAC_STATUS_MSTABORT           0x00000008
1467 #define  WDMAC_STATUS_PARITYERR          0x00000010
1468 #define  WDMAC_STATUS_ADDROFLOW          0x00000020
1469 #define  WDMAC_STATUS_FIFOOFLOW          0x00000040
1470 #define  WDMAC_STATUS_FIFOURUN           0x00000080
1471 #define  WDMAC_STATUS_FIFOOREAD          0x00000100
1472 #define  WDMAC_STATUS_LNGREAD            0x00000200
1473 /* 0x4c08 --> 0x5000 unused */
1474 
1475 /* Per-cpu register offsets (arm9) */
1476 #define CPU_MODE                        0x00000000
1477 #define  CPU_MODE_RESET                  0x00000001
1478 #define  CPU_MODE_HALT                   0x00000400
1479 #define CPU_STATE                       0x00000004
1480 #define CPU_EVTMASK                     0x00000008
1481 /* 0xc --> 0x1c reserved */
1482 #define CPU_PC                          0x0000001c
1483 #define CPU_INSN                        0x00000020
1484 #define CPU_SPAD_UFLOW                  0x00000024
1485 #define CPU_WDOG_CLEAR                  0x00000028
1486 #define CPU_WDOG_VECTOR                 0x0000002c
1487 #define CPU_WDOG_PC                     0x00000030
1488 #define CPU_HW_BP                       0x00000034
1489 /* 0x38 --> 0x44 unused */
1490 #define CPU_WDOG_SAVED_STATE            0x00000044
1491 #define CPU_LAST_BRANCH_ADDR            0x00000048
1492 #define CPU_SPAD_UFLOW_SET              0x0000004c
1493 /* 0x50 --> 0x200 unused */
1494 #define CPU_R0                          0x00000200
1495 #define CPU_R1                          0x00000204
1496 #define CPU_R2                          0x00000208
1497 #define CPU_R3                          0x0000020c
1498 #define CPU_R4                          0x00000210
1499 #define CPU_R5                          0x00000214
1500 #define CPU_R6                          0x00000218
1501 #define CPU_R7                          0x0000021c
1502 #define CPU_R8                          0x00000220
1503 #define CPU_R9                          0x00000224
1504 #define CPU_R10                         0x00000228
1505 #define CPU_R11                         0x0000022c
1506 #define CPU_R12                         0x00000230
1507 #define CPU_R13                         0x00000234
1508 #define CPU_R14                         0x00000238
1509 #define CPU_R15                         0x0000023c
1510 #define CPU_R16                         0x00000240
1511 #define CPU_R17                         0x00000244
1512 #define CPU_R18                         0x00000248
1513 #define CPU_R19                         0x0000024c
1514 #define CPU_R20                         0x00000250
1515 #define CPU_R21                         0x00000254
1516 #define CPU_R22                         0x00000258
1517 #define CPU_R23                         0x0000025c
1518 #define CPU_R24                         0x00000260
1519 #define CPU_R25                         0x00000264
1520 #define CPU_R26                         0x00000268
1521 #define CPU_R27                         0x0000026c
1522 #define CPU_R28                         0x00000270
1523 #define CPU_R29                         0x00000274
1524 #define CPU_R30                         0x00000278
1525 #define CPU_R31                         0x0000027c
1526 /* 0x280 --> 0x400 unused */
1527 
1528 #define RX_CPU_BASE                     0x00005000
1529 #define RX_CPU_MODE                     0x00005000
1530 #define RX_CPU_STATE                    0x00005004
1531 #define RX_CPU_PGMCTR                   0x0000501c
1532 #define RX_CPU_HWBKPT                   0x00005034
1533 #define TX_CPU_BASE                     0x00005400
1534 #define TX_CPU_MODE                     0x00005400
1535 #define TX_CPU_STATE                    0x00005404
1536 #define TX_CPU_PGMCTR                   0x0000541c
1537 
1538 #define VCPU_STATUS                     0x00005100
1539 #define  VCPU_STATUS_INIT_DONE           0x04000000
1540 #define  VCPU_STATUS_DRV_RESET           0x08000000
1541 
1542 #define VCPU_CFGSHDW                    0x00005104
1543 #define  VCPU_CFGSHDW_WOL_ENABLE         0x00000001
1544 #define  VCPU_CFGSHDW_WOL_MAGPKT         0x00000004
1545 #define  VCPU_CFGSHDW_ASPM_DBNC          0x00001000
1546 
1547 /* Mailboxes */
1548 #define GRCMBOX_BASE                    0x00005600
1549 #define GRCMBOX_INTERRUPT_0             0x00005800 /* 64-bit */
1550 #define GRCMBOX_INTERRUPT_1             0x00005808 /* 64-bit */
1551 #define GRCMBOX_INTERRUPT_2             0x00005810 /* 64-bit */
1552 #define GRCMBOX_INTERRUPT_3             0x00005818 /* 64-bit */
1553 #define GRCMBOX_GENERAL_0               0x00005820 /* 64-bit */
1554 #define GRCMBOX_GENERAL_1               0x00005828 /* 64-bit */
1555 #define GRCMBOX_GENERAL_2               0x00005830 /* 64-bit */
1556 #define GRCMBOX_GENERAL_3               0x00005838 /* 64-bit */
1557 #define GRCMBOX_GENERAL_4               0x00005840 /* 64-bit */
1558 #define GRCMBOX_GENERAL_5               0x00005848 /* 64-bit */
1559 #define GRCMBOX_GENERAL_6               0x00005850 /* 64-bit */
1560 #define GRCMBOX_GENERAL_7               0x00005858 /* 64-bit */
1561 #define GRCMBOX_RELOAD_STAT             0x00005860 /* 64-bit */
1562 #define GRCMBOX_RCVSTD_PROD_IDX         0x00005868 /* 64-bit */
1563 #define GRCMBOX_RCVJUMBO_PROD_IDX       0x00005870 /* 64-bit */
1564 #define GRCMBOX_RCVMINI_PROD_IDX        0x00005878 /* 64-bit */
1565 #define GRCMBOX_RCVRET_CON_IDX_0        0x00005880 /* 64-bit */
1566 #define GRCMBOX_RCVRET_CON_IDX_1        0x00005888 /* 64-bit */
1567 #define GRCMBOX_RCVRET_CON_IDX_2        0x00005890 /* 64-bit */
1568 #define GRCMBOX_RCVRET_CON_IDX_3        0x00005898 /* 64-bit */
1569 #define GRCMBOX_RCVRET_CON_IDX_4        0x000058a0 /* 64-bit */
1570 #define GRCMBOX_RCVRET_CON_IDX_5        0x000058a8 /* 64-bit */
1571 #define GRCMBOX_RCVRET_CON_IDX_6        0x000058b0 /* 64-bit */
1572 #define GRCMBOX_RCVRET_CON_IDX_7        0x000058b8 /* 64-bit */
1573 #define GRCMBOX_RCVRET_CON_IDX_8        0x000058c0 /* 64-bit */
1574 #define GRCMBOX_RCVRET_CON_IDX_9        0x000058c8 /* 64-bit */
1575 #define GRCMBOX_RCVRET_CON_IDX_10       0x000058d0 /* 64-bit */
1576 #define GRCMBOX_RCVRET_CON_IDX_11       0x000058d8 /* 64-bit */
1577 #define GRCMBOX_RCVRET_CON_IDX_12       0x000058e0 /* 64-bit */
1578 #define GRCMBOX_RCVRET_CON_IDX_13       0x000058e8 /* 64-bit */
1579 #define GRCMBOX_RCVRET_CON_IDX_14       0x000058f0 /* 64-bit */
1580 #define GRCMBOX_RCVRET_CON_IDX_15       0x000058f8 /* 64-bit */
1581 #define GRCMBOX_SNDHOST_PROD_IDX_0      0x00005900 /* 64-bit */
1582 #define GRCMBOX_SNDHOST_PROD_IDX_1      0x00005908 /* 64-bit */
1583 #define GRCMBOX_SNDHOST_PROD_IDX_2      0x00005910 /* 64-bit */
1584 #define GRCMBOX_SNDHOST_PROD_IDX_3      0x00005918 /* 64-bit */
1585 #define GRCMBOX_SNDHOST_PROD_IDX_4      0x00005920 /* 64-bit */
1586 #define GRCMBOX_SNDHOST_PROD_IDX_5      0x00005928 /* 64-bit */
1587 #define GRCMBOX_SNDHOST_PROD_IDX_6      0x00005930 /* 64-bit */
1588 #define GRCMBOX_SNDHOST_PROD_IDX_7      0x00005938 /* 64-bit */
1589 #define GRCMBOX_SNDHOST_PROD_IDX_8      0x00005940 /* 64-bit */
1590 #define GRCMBOX_SNDHOST_PROD_IDX_9      0x00005948 /* 64-bit */
1591 #define GRCMBOX_SNDHOST_PROD_IDX_10     0x00005950 /* 64-bit */
1592 #define GRCMBOX_SNDHOST_PROD_IDX_11     0x00005958 /* 64-bit */
1593 #define GRCMBOX_SNDHOST_PROD_IDX_12     0x00005960 /* 64-bit */
1594 #define GRCMBOX_SNDHOST_PROD_IDX_13     0x00005968 /* 64-bit */
1595 #define GRCMBOX_SNDHOST_PROD_IDX_14     0x00005970 /* 64-bit */
1596 #define GRCMBOX_SNDHOST_PROD_IDX_15     0x00005978 /* 64-bit */
1597 #define GRCMBOX_SNDNIC_PROD_IDX_0       0x00005980 /* 64-bit */
1598 #define GRCMBOX_SNDNIC_PROD_IDX_1       0x00005988 /* 64-bit */
1599 #define GRCMBOX_SNDNIC_PROD_IDX_2       0x00005990 /* 64-bit */
1600 #define GRCMBOX_SNDNIC_PROD_IDX_3       0x00005998 /* 64-bit */
1601 #define GRCMBOX_SNDNIC_PROD_IDX_4       0x000059a0 /* 64-bit */
1602 #define GRCMBOX_SNDNIC_PROD_IDX_5       0x000059a8 /* 64-bit */
1603 #define GRCMBOX_SNDNIC_PROD_IDX_6       0x000059b0 /* 64-bit */
1604 #define GRCMBOX_SNDNIC_PROD_IDX_7       0x000059b8 /* 64-bit */
1605 #define GRCMBOX_SNDNIC_PROD_IDX_8       0x000059c0 /* 64-bit */
1606 #define GRCMBOX_SNDNIC_PROD_IDX_9       0x000059c8 /* 64-bit */
1607 #define GRCMBOX_SNDNIC_PROD_IDX_10      0x000059d0 /* 64-bit */
1608 #define GRCMBOX_SNDNIC_PROD_IDX_11      0x000059d8 /* 64-bit */
1609 #define GRCMBOX_SNDNIC_PROD_IDX_12      0x000059e0 /* 64-bit */
1610 #define GRCMBOX_SNDNIC_PROD_IDX_13      0x000059e8 /* 64-bit */
1611 #define GRCMBOX_SNDNIC_PROD_IDX_14      0x000059f0 /* 64-bit */
1612 #define GRCMBOX_SNDNIC_PROD_IDX_15      0x000059f8 /* 64-bit */
1613 #define GRCMBOX_HIGH_PRIO_EV_VECTOR     0x00005a00
1614 #define GRCMBOX_HIGH_PRIO_EV_MASK       0x00005a04
1615 #define GRCMBOX_LOW_PRIO_EV_VEC         0x00005a08
1616 #define GRCMBOX_LOW_PRIO_EV_MASK        0x00005a0c
1617 /* 0x5a10 --> 0x5c00 */
1618 
1619 /* Flow Through queues */
1620 #define FTQ_RESET                       0x00005c00
1621 /* 0x5c04 --> 0x5c10 unused */
1622 #define FTQ_DMA_NORM_READ_CTL           0x00005c10
1623 #define FTQ_DMA_NORM_READ_FULL_CNT      0x00005c14
1624 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ   0x00005c18
1625 #define FTQ_DMA_NORM_READ_WRITE_PEEK    0x00005c1c
1626 #define FTQ_DMA_HIGH_READ_CTL           0x00005c20
1627 #define FTQ_DMA_HIGH_READ_FULL_CNT      0x00005c24
1628 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ   0x00005c28
1629 #define FTQ_DMA_HIGH_READ_WRITE_PEEK    0x00005c2c
1630 #define FTQ_DMA_COMP_DISC_CTL           0x00005c30
1631 #define FTQ_DMA_COMP_DISC_FULL_CNT      0x00005c34
1632 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ   0x00005c38
1633 #define FTQ_DMA_COMP_DISC_WRITE_PEEK    0x00005c3c
1634 #define FTQ_SEND_BD_COMP_CTL            0x00005c40
1635 #define FTQ_SEND_BD_COMP_FULL_CNT       0x00005c44
1636 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ    0x00005c48
1637 #define FTQ_SEND_BD_COMP_WRITE_PEEK     0x00005c4c
1638 #define FTQ_SEND_DATA_INIT_CTL          0x00005c50
1639 #define FTQ_SEND_DATA_INIT_FULL_CNT     0x00005c54
1640 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ  0x00005c58
1641 #define FTQ_SEND_DATA_INIT_WRITE_PEEK   0x00005c5c
1642 #define FTQ_DMA_NORM_WRITE_CTL          0x00005c60
1643 #define FTQ_DMA_NORM_WRITE_FULL_CNT     0x00005c64
1644 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ  0x00005c68
1645 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK   0x00005c6c
1646 #define FTQ_DMA_HIGH_WRITE_CTL          0x00005c70
1647 #define FTQ_DMA_HIGH_WRITE_FULL_CNT     0x00005c74
1648 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ  0x00005c78
1649 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK   0x00005c7c
1650 #define FTQ_SWTYPE1_CTL                 0x00005c80
1651 #define FTQ_SWTYPE1_FULL_CNT            0x00005c84
1652 #define FTQ_SWTYPE1_FIFO_ENQDEQ         0x00005c88
1653 #define FTQ_SWTYPE1_WRITE_PEEK          0x00005c8c
1654 #define FTQ_SEND_DATA_COMP_CTL          0x00005c90
1655 #define FTQ_SEND_DATA_COMP_FULL_CNT     0x00005c94
1656 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ  0x00005c98
1657 #define FTQ_SEND_DATA_COMP_WRITE_PEEK   0x00005c9c
1658 #define FTQ_HOST_COAL_CTL               0x00005ca0
1659 #define FTQ_HOST_COAL_FULL_CNT          0x00005ca4
1660 #define FTQ_HOST_COAL_FIFO_ENQDEQ       0x00005ca8
1661 #define FTQ_HOST_COAL_WRITE_PEEK        0x00005cac
1662 #define FTQ_MAC_TX_CTL                  0x00005cb0
1663 #define FTQ_MAC_TX_FULL_CNT             0x00005cb4
1664 #define FTQ_MAC_TX_FIFO_ENQDEQ          0x00005cb8
1665 #define FTQ_MAC_TX_WRITE_PEEK           0x00005cbc
1666 #define FTQ_MB_FREE_CTL                 0x00005cc0
1667 #define FTQ_MB_FREE_FULL_CNT            0x00005cc4
1668 #define FTQ_MB_FREE_FIFO_ENQDEQ         0x00005cc8
1669 #define FTQ_MB_FREE_WRITE_PEEK          0x00005ccc
1670 #define FTQ_RCVBD_COMP_CTL              0x00005cd0
1671 #define FTQ_RCVBD_COMP_FULL_CNT         0x00005cd4
1672 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ      0x00005cd8
1673 #define FTQ_RCVBD_COMP_WRITE_PEEK       0x00005cdc
1674 #define FTQ_RCVLST_PLMT_CTL             0x00005ce0
1675 #define FTQ_RCVLST_PLMT_FULL_CNT        0x00005ce4
1676 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ     0x00005ce8
1677 #define FTQ_RCVLST_PLMT_WRITE_PEEK      0x00005cec
1678 #define FTQ_RCVDATA_INI_CTL             0x00005cf0
1679 #define FTQ_RCVDATA_INI_FULL_CNT        0x00005cf4
1680 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ     0x00005cf8
1681 #define FTQ_RCVDATA_INI_WRITE_PEEK      0x00005cfc
1682 #define FTQ_RCVDATA_COMP_CTL            0x00005d00
1683 #define FTQ_RCVDATA_COMP_FULL_CNT       0x00005d04
1684 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ    0x00005d08
1685 #define FTQ_RCVDATA_COMP_WRITE_PEEK     0x00005d0c
1686 #define FTQ_SWTYPE2_CTL                 0x00005d10
1687 #define FTQ_SWTYPE2_FULL_CNT            0x00005d14
1688 #define FTQ_SWTYPE2_FIFO_ENQDEQ         0x00005d18
1689 #define FTQ_SWTYPE2_WRITE_PEEK          0x00005d1c
1690 /* 0x5d20 --> 0x6000 unused */
1691 
1692 /* Message signaled interrupt registers */
1693 #define MSGINT_MODE                     0x00006000
1694 #define  MSGINT_MODE_RESET               0x00000001
1695 #define  MSGINT_MODE_ENABLE              0x00000002
1696 #define  MSGINT_MODE_ONE_SHOT_DISABLE    0x00000020
1697 #define  MSGINT_MODE_MULTIVEC_EN         0x00000080
1698 #define MSGINT_STATUS                   0x00006004
1699 #define  MSGINT_STATUS_MSI_REQ           0x00000001
1700 #define MSGINT_FIFO                     0x00006008
1701 /* 0x600c --> 0x6400 unused */
1702 
1703 /* DMA completion registers */
1704 #define DMAC_MODE                       0x00006400
1705 #define  DMAC_MODE_RESET                 0x00000001
1706 #define  DMAC_MODE_ENABLE                0x00000002
1707 /* 0x6404 --> 0x6800 unused */
1708 
1709 /* GRC registers */
1710 #define GRC_MODE                        0x00006800
1711 #define  GRC_MODE_UPD_ON_COAL           0x00000001
1712 #define  GRC_MODE_BSWAP_NONFRM_DATA     0x00000002
1713 #define  GRC_MODE_WSWAP_NONFRM_DATA     0x00000004
1714 #define  GRC_MODE_BSWAP_DATA            0x00000010
1715 #define  GRC_MODE_WSWAP_DATA            0x00000020
1716 #define  GRC_MODE_BYTE_SWAP_B2HRX_DATA  0x00000040
1717 #define  GRC_MODE_WORD_SWAP_B2HRX_DATA  0x00000080
1718 #define  GRC_MODE_SPLITHDR              0x00000100
1719 #define  GRC_MODE_NOFRM_CRACKING        0x00000200
1720 #define  GRC_MODE_INCL_CRC              0x00000400
1721 #define  GRC_MODE_ALLOW_BAD_FRMS        0x00000800
1722 #define  GRC_MODE_NOIRQ_ON_SENDS        0x00002000
1723 #define  GRC_MODE_NOIRQ_ON_RCV          0x00004000
1724 #define  GRC_MODE_FORCE_PCI32BIT        0x00008000
1725 #define  GRC_MODE_B2HRX_ENABLE          0x00008000
1726 #define  GRC_MODE_HOST_STACKUP          0x00010000
1727 #define  GRC_MODE_HOST_SENDBDS          0x00020000
1728 #define  GRC_MODE_HTX2B_ENABLE          0x00040000
1729 #define  GRC_MODE_TIME_SYNC_ENABLE      0x00080000
1730 #define  GRC_MODE_NO_TX_PHDR_CSUM       0x00100000
1731 #define  GRC_MODE_NVRAM_WR_ENABLE       0x00200000
1732 #define  GRC_MODE_PCIE_TL_SEL           0x00000000
1733 #define  GRC_MODE_PCIE_PL_SEL           0x00400000
1734 #define  GRC_MODE_NO_RX_PHDR_CSUM       0x00800000
1735 #define  GRC_MODE_IRQ_ON_TX_CPU_ATTN    0x01000000
1736 #define  GRC_MODE_IRQ_ON_RX_CPU_ATTN    0x02000000
1737 #define  GRC_MODE_IRQ_ON_MAC_ATTN       0x04000000
1738 #define  GRC_MODE_IRQ_ON_DMA_ATTN       0x08000000
1739 #define  GRC_MODE_IRQ_ON_FLOW_ATTN      0x10000000
1740 #define  GRC_MODE_4X_NIC_SEND_RINGS     0x20000000
1741 #define  GRC_MODE_PCIE_DL_SEL           0x20000000
1742 #define  GRC_MODE_MCAST_FRM_ENABLE      0x40000000
1743 #define  GRC_MODE_PCIE_HI_1K_EN         0x80000000
1744 #define  GRC_MODE_PCIE_PORT_MASK        (GRC_MODE_PCIE_TL_SEL | \
1745                                          GRC_MODE_PCIE_PL_SEL | \
1746                                          GRC_MODE_PCIE_DL_SEL | \
1747                                          GRC_MODE_PCIE_HI_1K_EN)
1748 #define GRC_MISC_CFG                    0x00006804
1749 #define  GRC_MISC_CFG_CORECLK_RESET     0x00000001
1750 #define  GRC_MISC_CFG_PRESCALAR_MASK    0x000000fe
1751 #define  GRC_MISC_CFG_PRESCALAR_SHIFT   1
1752 #define  GRC_MISC_CFG_BOARD_ID_MASK     0x0001e000
1753 #define  GRC_MISC_CFG_BOARD_ID_5700     0x0001e000
1754 #define  GRC_MISC_CFG_BOARD_ID_5701     0x00000000
1755 #define  GRC_MISC_CFG_BOARD_ID_5702FE   0x00004000
1756 #define  GRC_MISC_CFG_BOARD_ID_5703     0x00000000
1757 #define  GRC_MISC_CFG_BOARD_ID_5703S    0x00002000
1758 #define  GRC_MISC_CFG_BOARD_ID_5704     0x00000000
1759 #define  GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1760 #define  GRC_MISC_CFG_BOARD_ID_5704_A2  0x00008000
1761 #define  GRC_MISC_CFG_BOARD_ID_5788     0x00010000
1762 #define  GRC_MISC_CFG_BOARD_ID_5788M    0x00018000
1763 #define  GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1764 #define  GRC_MISC_CFG_EPHY_IDDQ         0x00200000
1765 #define  GRC_MISC_CFG_KEEP_GPHY_POWER   0x04000000
1766 #define GRC_LOCAL_CTRL                  0x00006808
1767 #define  GRC_LCLCTRL_INT_ACTIVE         0x00000001
1768 #define  GRC_LCLCTRL_CLEARINT           0x00000002
1769 #define  GRC_LCLCTRL_SETINT             0x00000004
1770 #define  GRC_LCLCTRL_INT_ON_ATTN        0x00000008
1771 #define  GRC_LCLCTRL_GPIO_UART_SEL      0x00000010      /* 5755 only */
1772 #define  GRC_LCLCTRL_USE_SIG_DETECT     0x00000010      /* 5714/5780 only */
1773 #define  GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020      /* 5714/5780 only */
1774 #define  GRC_LCLCTRL_GPIO_INPUT3        0x00000020
1775 #define  GRC_LCLCTRL_GPIO_OE3           0x00000040
1776 #define  GRC_LCLCTRL_GPIO_OUTPUT3       0x00000080
1777 #define  GRC_LCLCTRL_GPIO_INPUT0        0x00000100
1778 #define  GRC_LCLCTRL_GPIO_INPUT1        0x00000200
1779 #define  GRC_LCLCTRL_GPIO_INPUT2        0x00000400
1780 #define  GRC_LCLCTRL_GPIO_OE0           0x00000800
1781 #define  GRC_LCLCTRL_GPIO_OE1           0x00001000
1782 #define  GRC_LCLCTRL_GPIO_OE2           0x00002000
1783 #define  GRC_LCLCTRL_GPIO_OUTPUT0       0x00004000
1784 #define  GRC_LCLCTRL_GPIO_OUTPUT1       0x00008000
1785 #define  GRC_LCLCTRL_GPIO_OUTPUT2       0x00010000
1786 #define  GRC_LCLCTRL_EXTMEM_ENABLE      0x00020000
1787 #define  GRC_LCLCTRL_MEMSZ_MASK         0x001c0000
1788 #define  GRC_LCLCTRL_MEMSZ_256K         0x00000000
1789 #define  GRC_LCLCTRL_MEMSZ_512K         0x00040000
1790 #define  GRC_LCLCTRL_MEMSZ_1M           0x00080000
1791 #define  GRC_LCLCTRL_MEMSZ_2M           0x000c0000
1792 #define  GRC_LCLCTRL_MEMSZ_4M           0x00100000
1793 #define  GRC_LCLCTRL_MEMSZ_8M           0x00140000
1794 #define  GRC_LCLCTRL_MEMSZ_16M          0x00180000
1795 #define  GRC_LCLCTRL_BANK_SELECT        0x00200000
1796 #define  GRC_LCLCTRL_SSRAM_TYPE         0x00400000
1797 #define  GRC_LCLCTRL_AUTO_SEEPROM       0x01000000
1798 #define GRC_TIMER                       0x0000680c
1799 #define GRC_RX_CPU_EVENT                0x00006810
1800 #define  GRC_RX_CPU_DRIVER_EVENT        0x00004000
1801 #define GRC_RX_TIMER_REF                0x00006814
1802 #define GRC_RX_CPU_SEM                  0x00006818
1803 #define GRC_REMOTE_RX_CPU_ATTN          0x0000681c
1804 #define GRC_TX_CPU_EVENT                0x00006820
1805 #define GRC_TX_TIMER_REF                0x00006824
1806 #define GRC_TX_CPU_SEM                  0x00006828
1807 #define GRC_REMOTE_TX_CPU_ATTN          0x0000682c
1808 #define GRC_MEM_POWER_UP                0x00006830 /* 64-bit */
1809 #define GRC_EEPROM_ADDR                 0x00006838
1810 #define  EEPROM_ADDR_WRITE              0x00000000
1811 #define  EEPROM_ADDR_READ               0x80000000
1812 #define  EEPROM_ADDR_COMPLETE           0x40000000
1813 #define  EEPROM_ADDR_FSM_RESET          0x20000000
1814 #define  EEPROM_ADDR_DEVID_MASK         0x1c000000
1815 #define  EEPROM_ADDR_DEVID_SHIFT        26
1816 #define  EEPROM_ADDR_START              0x02000000
1817 #define  EEPROM_ADDR_CLKPERD_SHIFT      16
1818 #define  EEPROM_ADDR_ADDR_MASK          0x0000ffff
1819 #define  EEPROM_ADDR_ADDR_SHIFT         0
1820 #define  EEPROM_DEFAULT_CLOCK_PERIOD    0x60
1821 #define  EEPROM_CHIP_SIZE               (64 * 1024)
1822 #define GRC_EEPROM_DATA                 0x0000683c
1823 #define GRC_EEPROM_CTRL                 0x00006840
1824 #define GRC_MDI_CTRL                    0x00006844
1825 #define GRC_SEEPROM_DELAY               0x00006848
1826 /* 0x684c --> 0x6890 unused */
1827 #define GRC_VCPU_EXT_CTRL               0x00006890
1828 #define GRC_VCPU_EXT_CTRL_HALT_CPU       0x00400000
1829 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL    0x20000000
1830 #define GRC_FASTBOOT_PC                 0x00006894      /* 5752, 5755, 5787 */
1831 
1832 #define TG3_EAV_REF_CLCK_LSB            0x00006900
1833 #define TG3_EAV_REF_CLCK_MSB            0x00006904
1834 #define TG3_EAV_REF_CLCK_CTL            0x00006908
1835 #define  TG3_EAV_REF_CLCK_CTL_STOP       0x00000002
1836 #define  TG3_EAV_REF_CLCK_CTL_RESUME     0x00000004
1837 #define  TG3_EAV_CTL_TSYNC_GPIO_MASK     (0x3 << 16)
1838 #define  TG3_EAV_CTL_TSYNC_WDOG0         (1 << 17)
1839 
1840 #define TG3_EAV_WATCHDOG0_LSB           0x00006918
1841 #define TG3_EAV_WATCHDOG0_MSB           0x0000691c
1842 #define  TG3_EAV_WATCHDOG0_EN            (1 << 31)
1843 #define  TG3_EAV_WATCHDOG_MSB_MASK      0x7fffffff
1844 
1845 #define TG3_EAV_REF_CLK_CORRECT_CTL     0x00006928
1846 #define  TG3_EAV_REF_CLK_CORRECT_EN      (1 << 31)
1847 #define  TG3_EAV_REF_CLK_CORRECT_NEG     (1 << 30)
1848 
1849 #define TG3_EAV_REF_CLK_CORRECT_MASK    0xffffff
1850 
1851 /* 0x692c --> 0x7000 unused */
1852 
1853 /* NVRAM Control registers */
1854 #define NVRAM_CMD                       0x00007000
1855 #define  NVRAM_CMD_RESET                 0x00000001
1856 #define  NVRAM_CMD_DONE                  0x00000008
1857 #define  NVRAM_CMD_GO                    0x00000010
1858 #define  NVRAM_CMD_WR                    0x00000020
1859 #define  NVRAM_CMD_RD                    0x00000000
1860 #define  NVRAM_CMD_ERASE                 0x00000040
1861 #define  NVRAM_CMD_FIRST                 0x00000080
1862 #define  NVRAM_CMD_LAST                  0x00000100
1863 #define  NVRAM_CMD_WREN                  0x00010000
1864 #define  NVRAM_CMD_WRDI                  0x00020000
1865 #define NVRAM_STAT                      0x00007004
1866 #define NVRAM_WRDATA                    0x00007008
1867 #define NVRAM_ADDR                      0x0000700c
1868 #define  NVRAM_ADDR_MSK                 0x07ffffff
1869 #define NVRAM_RDDATA                    0x00007010
1870 #define NVRAM_CFG1                      0x00007014
1871 #define  NVRAM_CFG1_FLASHIF_ENAB         0x00000001
1872 #define  NVRAM_CFG1_BUFFERED_MODE        0x00000002
1873 #define  NVRAM_CFG1_PASS_THRU            0x00000004
1874 #define  NVRAM_CFG1_STATUS_BITS          0x00000070
1875 #define  NVRAM_CFG1_BIT_BANG             0x00000008
1876 #define  NVRAM_CFG1_FLASH_SIZE           0x02000000
1877 #define  NVRAM_CFG1_COMPAT_BYPASS        0x80000000
1878 #define  NVRAM_CFG1_VENDOR_MASK          0x03000003
1879 #define  FLASH_VENDOR_ATMEL_EEPROM       0x02000000
1880 #define  FLASH_VENDOR_ATMEL_FLASH_BUFFERED       0x02000003
1881 #define  FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED     0x00000003
1882 #define  FLASH_VENDOR_ST                         0x03000001
1883 #define  FLASH_VENDOR_SAIFUN             0x01000003
1884 #define  FLASH_VENDOR_SST_SMALL          0x00000001
1885 #define  FLASH_VENDOR_SST_LARGE          0x02000001
1886 #define  NVRAM_CFG1_5752VENDOR_MASK      0x03c00003
1887 #define  NVRAM_CFG1_5762VENDOR_MASK      0x03e00003
1888 #define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ     0x00000000
1889 #define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ    0x02000000
1890 #define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED   0x02000003
1891 #define  FLASH_5752VENDOR_ST_M45PE10     0x02400000
1892 #define  FLASH_5752VENDOR_ST_M45PE20     0x02400002
1893 #define  FLASH_5752VENDOR_ST_M45PE40     0x02400001
1894 #define  FLASH_5755VENDOR_ATMEL_FLASH_1  0x03400001
1895 #define  FLASH_5755VENDOR_ATMEL_FLASH_2  0x03400002
1896 #define  FLASH_5755VENDOR_ATMEL_FLASH_3  0x03400000
1897 #define  FLASH_5755VENDOR_ATMEL_FLASH_4  0x00000003
1898 #define  FLASH_5755VENDOR_ATMEL_FLASH_5  0x02000003
1899 #define  FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ     0x03c00003
1900 #define  FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ    0x03c00002
1901 #define  FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ     0x03000003
1902 #define  FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ    0x03000002
1903 #define  FLASH_5787VENDOR_MICRO_EEPROM_64KHZ     0x03000000
1904 #define  FLASH_5787VENDOR_MICRO_EEPROM_376KHZ    0x02000000
1905 #define  FLASH_5761VENDOR_ATMEL_MDB021D  0x00800003
1906 #define  FLASH_5761VENDOR_ATMEL_MDB041D  0x00800000
1907 #define  FLASH_5761VENDOR_ATMEL_MDB081D  0x00800002
1908 #define  FLASH_5761VENDOR_ATMEL_MDB161D  0x00800001
1909 #define  FLASH_5761VENDOR_ATMEL_ADB021D  0x00000003
1910 #define  FLASH_5761VENDOR_ATMEL_ADB041D  0x00000000
1911 #define  FLASH_5761VENDOR_ATMEL_ADB081D  0x00000002
1912 #define  FLASH_5761VENDOR_ATMEL_ADB161D  0x00000001
1913 #define  FLASH_5761VENDOR_ST_M_M45PE20   0x02800001
1914 #define  FLASH_5761VENDOR_ST_M_M45PE40   0x02800000
1915 #define  FLASH_5761VENDOR_ST_M_M45PE80   0x02800002
1916 #define  FLASH_5761VENDOR_ST_M_M45PE16   0x02800003
1917 #define  FLASH_5761VENDOR_ST_A_M45PE20   0x02000001
1918 #define  FLASH_5761VENDOR_ST_A_M45PE40   0x02000000
1919 #define  FLASH_5761VENDOR_ST_A_M45PE80   0x02000002
1920 #define  FLASH_5761VENDOR_ST_A_M45PE16   0x02000003
1921 #define  FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1922 #define  FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1923 #define  FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1924 #define  FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1925 #define  FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1926 #define  FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1927 #define  FLASH_5717VENDOR_ATMEL_EEPROM   0x02000001
1928 #define  FLASH_5717VENDOR_MICRO_EEPROM   0x02000003
1929 #define  FLASH_5717VENDOR_ATMEL_MDB011D  0x01000001
1930 #define  FLASH_5717VENDOR_ATMEL_MDB021D  0x01000003
1931 #define  FLASH_5717VENDOR_ST_M_M25PE10   0x02000000
1932 #define  FLASH_5717VENDOR_ST_M_M25PE20   0x02000002
1933 #define  FLASH_5717VENDOR_ST_M_M45PE10   0x00000001
1934 #define  FLASH_5717VENDOR_ST_M_M45PE20   0x00000003
1935 #define  FLASH_5717VENDOR_ATMEL_ADB011B  0x01400000
1936 #define  FLASH_5717VENDOR_ATMEL_ADB021B  0x01400002
1937 #define  FLASH_5717VENDOR_ATMEL_ADB011D  0x01400001
1938 #define  FLASH_5717VENDOR_ATMEL_ADB021D  0x01400003
1939 #define  FLASH_5717VENDOR_ST_A_M25PE10   0x02400000
1940 #define  FLASH_5717VENDOR_ST_A_M25PE20   0x02400002
1941 #define  FLASH_5717VENDOR_ST_A_M45PE10   0x02400001
1942 #define  FLASH_5717VENDOR_ST_A_M45PE20   0x02400003
1943 #define  FLASH_5717VENDOR_ATMEL_45USPT   0x03400000
1944 #define  FLASH_5717VENDOR_ST_25USPT      0x03400002
1945 #define  FLASH_5717VENDOR_ST_45USPT      0x03400001
1946 #define  FLASH_5720_EEPROM_HD            0x00000001
1947 #define  FLASH_5720_EEPROM_LD            0x00000003
1948 #define  FLASH_5762_EEPROM_HD            0x02000001
1949 #define  FLASH_5762_EEPROM_LD            0x02000003
1950 #define  FLASH_5762_MX25L_100           0x00800000
1951 #define  FLASH_5762_MX25L_200           0x00800002
1952 #define  FLASH_5762_MX25L_400           0x00800001
1953 #define  FLASH_5762_MX25L_800           0x00800003
1954 #define  FLASH_5762_MX25L_160_320       0x03800002
1955 #define  FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
1956 #define  FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
1957 #define  FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
1958 #define  FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
1959 #define  FLASH_5720VENDOR_M_ST_M25PE10   0x02000000
1960 #define  FLASH_5720VENDOR_M_ST_M25PE20   0x02000002
1961 #define  FLASH_5720VENDOR_M_ST_M25PE40   0x02000001
1962 #define  FLASH_5720VENDOR_M_ST_M25PE80   0x02000003
1963 #define  FLASH_5720VENDOR_M_ST_M45PE10   0x03000000
1964 #define  FLASH_5720VENDOR_M_ST_M45PE20   0x03000002
1965 #define  FLASH_5720VENDOR_M_ST_M45PE40   0x03000001
1966 #define  FLASH_5720VENDOR_M_ST_M45PE80   0x03000003
1967 #define  FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
1968 #define  FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
1969 #define  FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
1970 #define  FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
1971 #define  FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
1972 #define  FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
1973 #define  FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
1974 #define  FLASH_5720VENDOR_A_ST_M25PE10   0x02800000
1975 #define  FLASH_5720VENDOR_A_ST_M25PE20   0x02800002
1976 #define  FLASH_5720VENDOR_A_ST_M25PE40   0x02800001
1977 #define  FLASH_5720VENDOR_A_ST_M25PE80   0x02800003
1978 #define  FLASH_5720VENDOR_A_ST_M45PE10   0x02c00000
1979 #define  FLASH_5720VENDOR_A_ST_M45PE20   0x02c00002
1980 #define  FLASH_5720VENDOR_A_ST_M45PE40   0x02c00001
1981 #define  FLASH_5720VENDOR_A_ST_M45PE80   0x02c00003
1982 #define  FLASH_5720VENDOR_ATMEL_45USPT   0x03c00000
1983 #define  FLASH_5720VENDOR_ST_25USPT      0x03c00002
1984 #define  FLASH_5720VENDOR_ST_45USPT      0x03c00001
1985 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK   0x70000000
1986 #define  FLASH_5752PAGE_SIZE_256         0x00000000
1987 #define  FLASH_5752PAGE_SIZE_512         0x10000000
1988 #define  FLASH_5752PAGE_SIZE_1K          0x20000000
1989 #define  FLASH_5752PAGE_SIZE_2K          0x30000000
1990 #define  FLASH_5752PAGE_SIZE_4K          0x40000000
1991 #define  FLASH_5752PAGE_SIZE_264         0x50000000
1992 #define  FLASH_5752PAGE_SIZE_528         0x60000000
1993 #define NVRAM_CFG2                      0x00007018
1994 #define NVRAM_CFG3                      0x0000701c
1995 #define NVRAM_SWARB                     0x00007020
1996 #define  SWARB_REQ_SET0                  0x00000001
1997 #define  SWARB_REQ_SET1                  0x00000002
1998 #define  SWARB_REQ_SET2                  0x00000004
1999 #define  SWARB_REQ_SET3                  0x00000008
2000 #define  SWARB_REQ_CLR0                  0x00000010
2001 #define  SWARB_REQ_CLR1                  0x00000020
2002 #define  SWARB_REQ_CLR2                  0x00000040
2003 #define  SWARB_REQ_CLR3                  0x00000080
2004 #define  SWARB_GNT0                      0x00000100
2005 #define  SWARB_GNT1                      0x00000200
2006 #define  SWARB_GNT2                      0x00000400
2007 #define  SWARB_GNT3                      0x00000800
2008 #define  SWARB_REQ0                      0x00001000
2009 #define  SWARB_REQ1                      0x00002000
2010 #define  SWARB_REQ2                      0x00004000
2011 #define  SWARB_REQ3                      0x00008000
2012 #define NVRAM_ACCESS                    0x00007024
2013 #define  ACCESS_ENABLE                   0x00000001
2014 #define  ACCESS_WR_ENABLE                0x00000002
2015 #define NVRAM_WRITE1                    0x00007028
2016 /* 0x702c unused */
2017 
2018 #define NVRAM_ADDR_LOCKOUT              0x00007030
2019 #define NVRAM_AUTOSENSE_STATUS         0x00007038
2020 #define AUTOSENSE_DEVID                        0x00000010
2021 #define AUTOSENSE_DEVID_MASK           0x00000007
2022 #define AUTOSENSE_SIZE_IN_MB           17
2023 /* 0x703c --> 0x7500 unused */
2024 
2025 #define OTP_MODE                        0x00007500
2026 #define OTP_MODE_OTP_THRU_GRC            0x00000001
2027 #define OTP_CTRL                        0x00007504
2028 #define OTP_CTRL_OTP_PROG_ENABLE         0x00200000
2029 #define OTP_CTRL_OTP_CMD_READ            0x00000000
2030 #define OTP_CTRL_OTP_CMD_INIT            0x00000008
2031 #define OTP_CTRL_OTP_CMD_START           0x00000001
2032 #define OTP_STATUS                      0x00007508
2033 #define OTP_STATUS_CMD_DONE              0x00000001
2034 #define OTP_ADDRESS                     0x0000750c
2035 #define OTP_ADDRESS_MAGIC1               0x000000a0
2036 #define OTP_ADDRESS_MAGIC2               0x00000080
2037 /* 0x7510 unused */
2038 
2039 #define OTP_READ_DATA                   0x00007514
2040 /* 0x7518 --> 0x7c04 unused */
2041 
2042 #define PCIE_TRANSACTION_CFG            0x00007c04
2043 #define PCIE_TRANS_CFG_1SHOT_MSI         0x20000000
2044 #define PCIE_TRANS_CFG_LOM               0x00000020
2045 /* 0x7c08 --> 0x7d28 unused */
2046 
2047 #define PCIE_PWR_MGMT_THRESH            0x00007d28
2048 #define PCIE_PWR_MGMT_L1_THRESH_MSK      0x0000ff00
2049 #define PCIE_PWR_MGMT_L1_THRESH_4MS      0x0000ff00
2050 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN    0x01000000
2051 /* 0x7d2c --> 0x7d54 unused */
2052 
2053 #define TG3_PCIE_LNKCTL                 0x00007d54
2054 #define  TG3_PCIE_LNKCTL_L1_PLL_PD_EN    0x00000008
2055 #define  TG3_PCIE_LNKCTL_L1_PLL_PD_DIS   0x00000080
2056 /* 0x7d58 --> 0x7e70 unused */
2057 
2058 #define TG3_PCIE_PHY_TSTCTL             0x00007e2c
2059 #define  TG3_PCIE_PHY_TSTCTL_PCIE10      0x00000040
2060 #define  TG3_PCIE_PHY_TSTCTL_PSCRAM      0x00000020
2061 
2062 #define TG3_PCIE_EIDLE_DELAY            0x00007e70
2063 #define  TG3_PCIE_EIDLE_DELAY_MASK       0x0000001f
2064 #define  TG3_PCIE_EIDLE_DELAY_13_CLKS    0x0000000c
2065 /* 0x7e74 --> 0x8000 unused */
2066 
2067 
2068 /* Alternate PCIE definitions */
2069 #define TG3_PCIE_TLDLPL_PORT            0x00007c00
2070 #define TG3_PCIE_DL_LO_FTSMAX           0x0000000c
2071 #define TG3_PCIE_DL_LO_FTSMAX_MSK       0x000000ff
2072 #define TG3_PCIE_DL_LO_FTSMAX_VAL       0x0000002c
2073 #define TG3_PCIE_PL_LO_PHYCTL1           0x00000004
2074 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN         0x00001000
2075 #define TG3_PCIE_PL_LO_PHYCTL5           0x00000014
2076 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ       0x80000000
2077 
2078 #define TG3_REG_BLK_SIZE                0x00008000
2079 
2080 /* OTP bit definitions */
2081 #define TG3_OTP_AGCTGT_MASK             0x000000e0
2082 #define TG3_OTP_AGCTGT_SHIFT            1
2083 #define TG3_OTP_HPFFLTR_MASK            0x00000300
2084 #define TG3_OTP_HPFFLTR_SHIFT           1
2085 #define TG3_OTP_HPFOVER_MASK            0x00000400
2086 #define TG3_OTP_HPFOVER_SHIFT           1
2087 #define TG3_OTP_LPFDIS_MASK             0x00000800
2088 #define TG3_OTP_LPFDIS_SHIFT            11
2089 #define TG3_OTP_VDAC_MASK               0xff000000
2090 #define TG3_OTP_VDAC_SHIFT              24
2091 #define TG3_OTP_10BTAMP_MASK            0x0000f000
2092 #define TG3_OTP_10BTAMP_SHIFT           8
2093 #define TG3_OTP_ROFF_MASK               0x00e00000
2094 #define TG3_OTP_ROFF_SHIFT              11
2095 #define TG3_OTP_RCOFF_MASK              0x001c0000
2096 #define TG3_OTP_RCOFF_SHIFT             16
2097 
2098 #define TG3_OTP_DEFAULT                 0x286c1640
2099 
2100 
2101 /* Hardware Legacy NVRAM layout */
2102 #define TG3_NVM_VPD_OFF                 0x100
2103 #define TG3_NVM_VPD_LEN                 256
2104 
2105 /* Hardware Selfboot NVRAM layout */
2106 #define TG3_NVM_HWSB_CFG1               0x00000004
2107 #define  TG3_NVM_HWSB_CFG1_MAJMSK       0xf8000000
2108 #define  TG3_NVM_HWSB_CFG1_MAJSFT       27
2109 #define  TG3_NVM_HWSB_CFG1_MINMSK       0x07c00000
2110 #define  TG3_NVM_HWSB_CFG1_MINSFT       22
2111 
2112 #define TG3_EEPROM_MAGIC                0x669955aa
2113 #define TG3_EEPROM_MAGIC_FW             0xa5000000
2114 #define TG3_EEPROM_MAGIC_FW_MSK         0xff000000
2115 #define TG3_EEPROM_SB_FORMAT_MASK       0x00e00000
2116 #define TG3_EEPROM_SB_FORMAT_1          0x00200000
2117 #define TG3_EEPROM_SB_REVISION_MASK     0x001f0000
2118 #define TG3_EEPROM_SB_REVISION_0        0x00000000
2119 #define TG3_EEPROM_SB_REVISION_2        0x00020000
2120 #define TG3_EEPROM_SB_REVISION_3        0x00030000
2121 #define TG3_EEPROM_SB_REVISION_4        0x00040000
2122 #define TG3_EEPROM_SB_REVISION_5        0x00050000
2123 #define TG3_EEPROM_SB_REVISION_6        0x00060000
2124 #define TG3_EEPROM_MAGIC_HW             0xabcd
2125 #define TG3_EEPROM_MAGIC_HW_MSK         0xffff
2126 
2127 #define TG3_NVM_DIR_START               0x18
2128 #define TG3_NVM_DIR_END                 0x78
2129 #define TG3_NVM_DIRENT_SIZE             0xc
2130 #define TG3_NVM_DIRTYPE_SHIFT           24
2131 #define TG3_NVM_DIRTYPE_LENMSK          0x003fffff
2132 #define TG3_NVM_DIRTYPE_ASFINI          1
2133 #define TG3_NVM_DIRTYPE_EXTVPD          20
2134 #define TG3_NVM_PTREV_BCVER             0x94
2135 #define TG3_NVM_BCVER_MAJMSK            0x0000ff00
2136 #define TG3_NVM_BCVER_MAJSFT            8
2137 #define TG3_NVM_BCVER_MINMSK            0x000000ff
2138 
2139 #define TG3_EEPROM_SB_F1R0_EDH_OFF      0x10
2140 #define TG3_EEPROM_SB_F1R2_EDH_OFF      0x14
2141 #define TG3_EEPROM_SB_F1R2_MBA_OFF      0x10
2142 #define TG3_EEPROM_SB_F1R3_EDH_OFF      0x18
2143 #define TG3_EEPROM_SB_F1R4_EDH_OFF      0x1c
2144 #define TG3_EEPROM_SB_F1R5_EDH_OFF      0x20
2145 #define TG3_EEPROM_SB_F1R6_EDH_OFF      0x4c
2146 #define TG3_EEPROM_SB_EDH_MAJ_MASK      0x00000700
2147 #define TG3_EEPROM_SB_EDH_MAJ_SHFT      8
2148 #define TG3_EEPROM_SB_EDH_MIN_MASK      0x000000ff
2149 #define TG3_EEPROM_SB_EDH_BLD_MASK      0x0000f800
2150 #define TG3_EEPROM_SB_EDH_BLD_SHFT      11
2151 
2152 
2153 /* 32K Window into NIC internal memory */
2154 #define NIC_SRAM_WIN_BASE               0x00008000
2155 
2156 /* Offsets into first 32k of NIC internal memory. */
2157 #define NIC_SRAM_PAGE_ZERO              0x00000000
2158 #define NIC_SRAM_SEND_RCB               0x00000100 /* 16 * TG3_BDINFO_... */
2159 #define NIC_SRAM_RCV_RET_RCB            0x00000200 /* 16 * TG3_BDINFO_... */
2160 #define NIC_SRAM_STATS_BLK              0x00000300
2161 #define NIC_SRAM_STATUS_BLK             0x00000b00
2162 
2163 #define NIC_SRAM_FIRMWARE_MBOX          0x00000b50
2164 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC1   0x4B657654
2165 #define  NIC_SRAM_FIRMWARE_MBOX_MAGIC2   0x4861764b /* !dma on linkchg */
2166 
2167 #define NIC_SRAM_DATA_SIG               0x00000b54
2168 #define  NIC_SRAM_DATA_SIG_MAGIC         0x4b657654 /* ascii for 'KevT' */
2169 
2170 #define NIC_SRAM_DATA_CFG                       0x00000b58
2171 #define  NIC_SRAM_DATA_CFG_LED_MODE_MASK         0x0000000c
2172 #define  NIC_SRAM_DATA_CFG_LED_MODE_MAC          0x00000000
2173 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_1        0x00000004
2174 #define  NIC_SRAM_DATA_CFG_LED_MODE_PHY_2        0x00000008
2175 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_MASK         0x00000030
2176 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN      0x00000000
2177 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER       0x00000010
2178 #define  NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER        0x00000020
2179 #define  NIC_SRAM_DATA_CFG_WOL_ENABLE            0x00000040
2180 #define  NIC_SRAM_DATA_CFG_ASF_ENABLE            0x00000080
2181 #define  NIC_SRAM_DATA_CFG_EEPROM_WP             0x00000100
2182 #define  NIC_SRAM_DATA_CFG_MINI_PCI              0x00001000
2183 #define  NIC_SRAM_DATA_CFG_FIBER_WOL             0x00004000
2184 #define  NIC_SRAM_DATA_CFG_NO_GPIO2              0x00100000
2185 #define  NIC_SRAM_DATA_CFG_APE_ENABLE            0x00200000
2186 
2187 #define NIC_SRAM_DATA_VER                       0x00000b5c
2188 #define  NIC_SRAM_DATA_VER_SHIFT                 16
2189 
2190 #define NIC_SRAM_DATA_PHY_ID            0x00000b74
2191 #define  NIC_SRAM_DATA_PHY_ID1_MASK      0xffff0000
2192 #define  NIC_SRAM_DATA_PHY_ID2_MASK      0x0000ffff
2193 
2194 #define NIC_SRAM_FW_CMD_MBOX            0x00000b78
2195 #define  FWCMD_NICDRV_ALIVE              0x00000001
2196 #define  FWCMD_NICDRV_PAUSE_FW           0x00000002
2197 #define  FWCMD_NICDRV_IPV4ADDR_CHG       0x00000003
2198 #define  FWCMD_NICDRV_IPV6ADDR_CHG       0x00000004
2199 #define  FWCMD_NICDRV_FIX_DMAR           0x00000005
2200 #define  FWCMD_NICDRV_FIX_DMAW           0x00000006
2201 #define  FWCMD_NICDRV_LINK_UPDATE        0x0000000c
2202 #define  FWCMD_NICDRV_ALIVE2             0x0000000d
2203 #define  FWCMD_NICDRV_ALIVE3             0x0000000e
2204 #define NIC_SRAM_FW_CMD_LEN_MBOX        0x00000b7c
2205 #define NIC_SRAM_FW_CMD_DATA_MBOX       0x00000b80
2206 #define NIC_SRAM_FW_ASF_STATUS_MBOX     0x00000c00
2207 #define NIC_SRAM_FW_DRV_STATE_MBOX      0x00000c04
2208 #define  DRV_STATE_START                 0x00000001
2209 #define  DRV_STATE_START_DONE            0x80000001
2210 #define  DRV_STATE_UNLOAD                0x00000002
2211 #define  DRV_STATE_UNLOAD_DONE           0x80000002
2212 #define  DRV_STATE_WOL                   0x00000003
2213 #define  DRV_STATE_SUSPEND               0x00000004
2214 
2215 #define NIC_SRAM_FW_RESET_TYPE_MBOX     0x00000c08
2216 
2217 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX     0x00000c14
2218 #define NIC_SRAM_MAC_ADDR_LOW_MBOX      0x00000c18
2219 
2220 #define NIC_SRAM_WOL_MBOX               0x00000d30
2221 #define  WOL_SIGNATURE                   0x474c0000
2222 #define  WOL_DRV_STATE_SHUTDOWN          0x00000001
2223 #define  WOL_DRV_WOL                     0x00000002
2224 #define  WOL_SET_MAGIC_PKT               0x00000004
2225 
2226 #define NIC_SRAM_DATA_CFG_2             0x00000d38
2227 
2228 #define  NIC_SRAM_DATA_CFG_2_APD_EN      0x00004000
2229 #define  SHASTA_EXT_LED_MODE_MASK        0x00018000
2230 #define  SHASTA_EXT_LED_LEGACY           0x00000000
2231 #define  SHASTA_EXT_LED_SHARED           0x00008000
2232 #define  SHASTA_EXT_LED_MAC              0x00010000
2233 #define  SHASTA_EXT_LED_COMBO            0x00018000
2234 
2235 #define NIC_SRAM_DATA_CFG_3             0x00000d3c
2236 #define  NIC_SRAM_ASPM_DEBOUNCE          0x00000002
2237 #define  NIC_SRAM_LNK_FLAP_AVOID         0x00400000
2238 #define  NIC_SRAM_1G_ON_VAUX_OK          0x00800000
2239 
2240 #define NIC_SRAM_DATA_CFG_4             0x00000d60
2241 #define  NIC_SRAM_GMII_MODE              0x00000002
2242 #define  NIC_SRAM_RGMII_INBAND_DISABLE   0x00000004
2243 #define  NIC_SRAM_RGMII_EXT_IBND_RX_EN   0x00000008
2244 #define  NIC_SRAM_RGMII_EXT_IBND_TX_EN   0x00000010
2245 
2246 #define NIC_SRAM_CPMU_STATUS            0x00000e00
2247 #define  NIC_SRAM_CPMUSTAT_SIG          0x0000362c
2248 #define  NIC_SRAM_CPMUSTAT_SIG_MSK      0x0000ffff
2249 
2250 #define NIC_SRAM_DATA_CFG_5             0x00000e0c
2251 #define  NIC_SRAM_DISABLE_1G_HALF_ADV   0x00000002
2252 
2253 #define NIC_SRAM_RX_MINI_BUFFER_DESC    0x00001000
2254 
2255 #define NIC_SRAM_DMA_DESC_POOL_BASE     0x00002000
2256 #define  NIC_SRAM_DMA_DESC_POOL_SIZE     0x00002000
2257 #define NIC_SRAM_TX_BUFFER_DESC         0x00004000 /* 512 entries */
2258 #define NIC_SRAM_RX_BUFFER_DESC         0x00006000 /* 256 entries */
2259 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC   0x00007000 /* 256 entries */
2260 #define NIC_SRAM_MBUF_POOL_BASE         0x00008000
2261 #define  NIC_SRAM_MBUF_POOL_SIZE96       0x00018000
2262 #define  NIC_SRAM_MBUF_POOL_SIZE64       0x00010000
2263 #define  NIC_SRAM_MBUF_POOL_BASE5705    0x00010000
2264 #define  NIC_SRAM_MBUF_POOL_SIZE5705    0x0000e000
2265 
2266 #define TG3_SRAM_RXCPU_SCRATCH_BASE_57766       0x00030000
2267 #define  TG3_SRAM_RXCPU_SCRATCH_SIZE_57766       0x00010000
2268 #define TG3_57766_FW_BASE_ADDR                  0x00030000
2269 #define TG3_57766_FW_HANDSHAKE                  0x0003fccc
2270 #define TG3_SBROM_IN_SERVICE_LOOP               0x51
2271 
2272 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700       128
2273 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755       64
2274 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906       32
2275 
2276 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700       64
2277 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717       16
2278 
2279 
2280 /* Currently this is fixed. */
2281 #define TG3_PHY_MII_ADDR                0x01
2282 
2283 
2284 /*** Tigon3 specific PHY MII registers. ***/
2285 #define MII_TG3_MMD_CTRL                0x0d /* MMD Access Control register */
2286 #define MII_TG3_MMD_CTRL_DATA_NOINC     0x4000
2287 #define MII_TG3_MMD_ADDRESS             0x0e /* MMD Address Data register */
2288 
2289 #define MII_TG3_EXT_CTRL                0x10 /* Extended control register */
2290 #define  MII_TG3_EXT_CTRL_FIFO_ELASTIC  0x0001
2291 #define  MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
2292 #define  MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
2293 #define  MII_TG3_EXT_CTRL_TBI           0x8000
2294 
2295 #define MII_TG3_EXT_STAT                0x11 /* Extended status register */
2296 #define  MII_TG3_EXT_STAT_MDIX          0x2000
2297 #define  MII_TG3_EXT_STAT_LPASS         0x0100
2298 
2299 #define MII_TG3_RXR_COUNTERS            0x14 /* Local/Remote Receiver Counts */
2300 #define MII_TG3_DSP_RW_PORT             0x15 /* DSP coefficient read/write port */
2301 #define MII_TG3_DSP_CONTROL             0x16 /* DSP control register */
2302 #define MII_TG3_DSP_ADDRESS             0x17 /* DSP address register */
2303 
2304 #define MII_TG3_DSP_TAP1                0x0001
2305 #define  MII_TG3_DSP_TAP1_AGCTGT_DFLT   0x0007
2306 #define MII_TG3_DSP_TAP26               0x001a
2307 #define  MII_TG3_DSP_TAP26_ALNOKO       0x0001
2308 #define  MII_TG3_DSP_TAP26_RMRXSTO      0x0002
2309 #define  MII_TG3_DSP_TAP26_OPCSINPT     0x0004
2310 #define MII_TG3_DSP_AADJ1CH0            0x001f
2311 #define MII_TG3_DSP_CH34TP2             0x4022
2312 #define MII_TG3_DSP_CH34TP2_HIBW01      0x01ff
2313 #define MII_TG3_DSP_AADJ1CH3            0x601f
2314 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ  0x0002
2315 #define MII_TG3_DSP_EXP1_INT_STAT       0x0f01
2316 #define MII_TG3_DSP_EXP8                0x0f08
2317 #define  MII_TG3_DSP_EXP8_REJ2MHz       0x0001
2318 #define  MII_TG3_DSP_EXP8_AEDW          0x0200
2319 #define MII_TG3_DSP_EXP75               0x0f75
2320 #define MII_TG3_DSP_EXP96               0x0f96
2321 #define MII_TG3_DSP_EXP97               0x0f97
2322 
2323 #define MII_TG3_AUX_CTRL                0x18 /* auxiliary control register */
2324 
2325 #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL   0x0000
2326 #define MII_TG3_AUXCTL_ACTL_TX_6DB      0x0400
2327 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA   0x0800
2328 #define MII_TG3_AUXCTL_ACTL_EXTPKTLEN   0x4000
2329 #define MII_TG3_AUXCTL_ACTL_EXTLOOPBK   0x8000
2330 
2331 #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL   0x0002
2332 #define MII_TG3_AUXCTL_PCTL_WOL_EN      0x0008
2333 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR  0x0010
2334 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
2335 #define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040
2336 #define MII_TG3_AUXCTL_PCTL_VREG_11V    0x0180
2337 
2338 #define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
2339 
2340 #define MII_TG3_AUXCTL_SHDWSEL_MISC     0x0007
2341 #define MII_TG3_AUXCTL_MISC_WIRESPD_EN  0x0010
2342 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
2343 #define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
2344 #define MII_TG3_AUXCTL_MISC_WREN        0x8000
2345 
2346 
2347 #define MII_TG3_AUX_STAT                0x19 /* auxiliary status register */
2348 #define MII_TG3_AUX_STAT_LPASS          0x0004
2349 #define MII_TG3_AUX_STAT_SPDMASK        0x0700
2350 #define MII_TG3_AUX_STAT_10HALF         0x0100
2351 #define MII_TG3_AUX_STAT_10FULL         0x0200
2352 #define MII_TG3_AUX_STAT_100HALF        0x0300
2353 #define MII_TG3_AUX_STAT_100_4          0x0400
2354 #define MII_TG3_AUX_STAT_100FULL        0x0500
2355 #define MII_TG3_AUX_STAT_1000HALF       0x0600
2356 #define MII_TG3_AUX_STAT_1000FULL       0x0700
2357 #define MII_TG3_AUX_STAT_100            0x0008
2358 #define MII_TG3_AUX_STAT_FULL           0x0001
2359 
2360 #define MII_TG3_ISTAT                   0x1a /* IRQ status register */
2361 #define MII_TG3_IMASK                   0x1b /* IRQ mask register */
2362 
2363 /* ISTAT/IMASK event bits */
2364 #define MII_TG3_INT_LINKCHG             0x0002
2365 #define MII_TG3_INT_SPEEDCHG            0x0004
2366 #define MII_TG3_INT_DUPLEXCHG           0x0008
2367 #define MII_TG3_INT_ANEG_PAGE_RX        0x0400
2368 
2369 #define MII_TG3_MISC_SHDW               0x1c
2370 #define MII_TG3_MISC_SHDW_WREN          0x8000
2371 
2372 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
2373 #define MII_TG3_MISC_SHDW_APD_ENABLE    0x0020
2374 #define MII_TG3_MISC_SHDW_APD_SEL       0x2800
2375 
2376 #define MII_TG3_MISC_SHDW_SCR5_C125OE   0x0001
2377 #define MII_TG3_MISC_SHDW_SCR5_DLLAPD   0x0002
2378 #define MII_TG3_MISC_SHDW_SCR5_SDTL     0x0004
2379 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM   0x0008
2380 #define MII_TG3_MISC_SHDW_SCR5_LPED     0x0010
2381 #define MII_TG3_MISC_SHDW_SCR5_SEL      0x1400
2382 
2383 #define MII_TG3_TEST1                   0x1e
2384 #define MII_TG3_TEST1_TRIM_EN           0x0010
2385 #define MII_TG3_TEST1_CRC_EN            0x8000
2386 
2387 /* Clause 45 expansion registers */
2388 #define TG3_CL45_D7_EEERES_STAT         0x803e
2389 #define TG3_CL45_D7_EEERES_STAT_LP_100TX        0x0002
2390 #define TG3_CL45_D7_EEERES_STAT_LP_1000T        0x0004
2391 
2392 
2393 /* Fast Ethernet Tranceiver definitions */
2394 #define MII_TG3_FET_PTEST               0x17
2395 #define  MII_TG3_FET_PTEST_TRIM_SEL     0x0010
2396 #define  MII_TG3_FET_PTEST_TRIM_2       0x0002
2397 #define  MII_TG3_FET_PTEST_FRC_TX_LINK  0x1000
2398 #define  MII_TG3_FET_PTEST_FRC_TX_LOCK  0x0800
2399 
2400 #define MII_TG3_FET_GEN_STAT            0x1c
2401 #define  MII_TG3_FET_GEN_STAT_MDIXSTAT  0x2000
2402 
2403 #define MII_TG3_FET_TEST                0x1f
2404 #define  MII_TG3_FET_SHADOW_EN          0x0080
2405 
2406 #define MII_TG3_FET_SHDW_MISCCTRL       0x10
2407 #define  MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
2408 
2409 #define MII_TG3_FET_SHDW_AUXMODE4       0x1a
2410 #define MII_TG3_FET_SHDW_AUXMODE4_SBPD  0x0008
2411 
2412 #define MII_TG3_FET_SHDW_AUXSTAT2       0x1b
2413 #define  MII_TG3_FET_SHDW_AUXSTAT2_APD  0x0020
2414 
2415 /* Serdes PHY Register Definitions */
2416 #define SERDES_TG3_1000X_STATUS         0x14
2417 #define  SERDES_TG3_SGMII_MODE           0x0001
2418 #define  SERDES_TG3_LINK_UP              0x0002
2419 #define  SERDES_TG3_FULL_DUPLEX          0x0004
2420 #define  SERDES_TG3_SPEED_100            0x0008
2421 #define  SERDES_TG3_SPEED_1000           0x0010
2422 
2423 /* APE registers.  Accessible through BAR1 */
2424 #define TG3_APE_GPIO_MSG                0x0008
2425 #define TG3_APE_GPIO_MSG_SHIFT          4
2426 #define TG3_APE_EVENT                   0x000c
2427 #define  APE_EVENT_1                     0x00000001
2428 #define TG3_APE_LOCK_REQ                0x002c
2429 #define  APE_LOCK_REQ_DRIVER             0x00001000
2430 #define TG3_APE_LOCK_GRANT              0x004c
2431 #define  APE_LOCK_GRANT_DRIVER           0x00001000
2432 #define TG3_APE_OTP_CTRL                0x00e8
2433 #define  APE_OTP_CTRL_PROG_EN            0x200000
2434 #define  APE_OTP_CTRL_CMD_RD             0x000000
2435 #define  APE_OTP_CTRL_START              0x000001
2436 #define TG3_APE_OTP_STATUS              0x00ec
2437 #define  APE_OTP_STATUS_CMD_DONE         0x000001
2438 #define TG3_APE_OTP_ADDR                0x00f0
2439 #define  APE_OTP_ADDR_CPU_ENABLE         0x80000000
2440 #define TG3_APE_OTP_RD_DATA             0x00f8
2441 
2442 #define OTP_ADDRESS_MAGIC0               0x00000050
2443 #define TG3_OTP_MAGIC0_VALID(val)               \
2444         ((((val) & 0xf0000000) == 0xa0000000) ||\
2445          (((val) & 0x0f000000) == 0x0a000000))
2446 
2447 /* APE shared memory.  Accessible through BAR1 */
2448 #define TG3_APE_SHMEM_BASE              0x4000
2449 #define TG3_APE_SEG_SIG                 0x4000
2450 #define  APE_SEG_SIG_MAGIC               0x41504521
2451 #define TG3_APE_FW_STATUS               0x400c
2452 #define  APE_FW_STATUS_READY             0x00000100
2453 #define TG3_APE_FW_FEATURES             0x4010
2454 #define  TG3_APE_FW_FEATURE_NCSI         0x00000002
2455 #define TG3_APE_FW_VERSION              0x4018
2456 #define  APE_FW_VERSION_MAJMSK           0xff000000
2457 #define  APE_FW_VERSION_MAJSFT           24
2458 #define  APE_FW_VERSION_MINMSK           0x00ff0000
2459 #define  APE_FW_VERSION_MINSFT           16
2460 #define  APE_FW_VERSION_REVMSK           0x0000ff00
2461 #define  APE_FW_VERSION_REVSFT           8
2462 #define  APE_FW_VERSION_BLDMSK           0x000000ff
2463 #define TG3_APE_SEG_MSG_BUF_OFF         0x401c
2464 #define TG3_APE_SEG_MSG_BUF_LEN         0x4020
2465 #define TG3_APE_HOST_SEG_SIG            0x4200
2466 #define  APE_HOST_SEG_SIG_MAGIC          0x484f5354
2467 #define TG3_APE_HOST_SEG_LEN            0x4204
2468 #define  APE_HOST_SEG_LEN_MAGIC          0x00000020
2469 #define TG3_APE_HOST_INIT_COUNT         0x4208
2470 #define TG3_APE_HOST_DRIVER_ID          0x420c
2471 #define  APE_HOST_DRIVER_ID_LINUX        0xf0000000
2472 #define  APE_HOST_DRIVER_ID_MAGIC(maj, min)     \
2473         (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
2474 #define TG3_APE_HOST_BEHAVIOR           0x4210
2475 #define  APE_HOST_BEHAV_NO_PHYLOCK       0x00000001
2476 #define TG3_APE_HOST_HEARTBEAT_INT_MS   0x4214
2477 #define  APE_HOST_HEARTBEAT_INT_DISABLE  0
2478 #define  APE_HOST_HEARTBEAT_INT_5SEC     5000
2479 #define TG3_APE_HOST_HEARTBEAT_COUNT    0x4218
2480 #define TG3_APE_HOST_DRVR_STATE         0x421c
2481 #define TG3_APE_HOST_DRVR_STATE_START    0x00000001
2482 #define TG3_APE_HOST_DRVR_STATE_UNLOAD   0x00000002
2483 #define TG3_APE_HOST_DRVR_STATE_WOL      0x00000003
2484 #define TG3_APE_HOST_WOL_SPEED          0x4224
2485 #define TG3_APE_HOST_WOL_SPEED_AUTO      0x00008000
2486 
2487 #define TG3_APE_EVENT_STATUS            0x4300
2488 
2489 #define  APE_EVENT_STATUS_DRIVER_EVNT    0x00000010
2490 #define  APE_EVENT_STATUS_STATE_CHNGE    0x00000500
2491 #define  APE_EVENT_STATUS_SCRTCHPD_READ  0x00001600
2492 #define  APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700
2493 #define  APE_EVENT_STATUS_STATE_START    0x00010000
2494 #define  APE_EVENT_STATUS_STATE_UNLOAD   0x00020000
2495 #define  APE_EVENT_STATUS_STATE_WOL      0x00030000
2496 #define  APE_EVENT_STATUS_STATE_SUSPEND  0x00040000
2497 #define  APE_EVENT_STATUS_EVENT_PENDING  0x80000000
2498 
2499 #define TG3_APE_PER_LOCK_REQ            0x8400
2500 #define  APE_LOCK_PER_REQ_DRIVER         0x00001000
2501 #define TG3_APE_PER_LOCK_GRANT          0x8420
2502 #define  APE_PER_LOCK_GRANT_DRIVER       0x00001000
2503 
2504 /* APE convenience enumerations. */
2505 #define TG3_APE_LOCK_PHY0               0
2506 #define TG3_APE_LOCK_GRC                1
2507 #define TG3_APE_LOCK_PHY1               2
2508 #define TG3_APE_LOCK_PHY2               3
2509 #define TG3_APE_LOCK_MEM                4
2510 #define TG3_APE_LOCK_PHY3               5
2511 #define TG3_APE_LOCK_GPIO               7
2512 
2513 #define TG3_APE_HB_INTERVAL             (tp->ape_hb_interval)
2514 #define TG3_EEPROM_SB_F1R2_MBA_OFF      0x10
2515 
2516 
2517 /* There are two ways to manage the TX descriptors on the tigon3.
2518  * Either the descriptors are in host DMA'able memory, or they
2519  * exist only in the cards on-chip SRAM.  All 16 send bds are under
2520  * the same mode, they may not be configured individually.
2521  *
2522  * This driver always uses host memory TX descriptors.
2523  *
2524  * To use host memory TX descriptors:
2525  *      1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
2526  *         Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
2527  *      2) Allocate DMA'able memory.
2528  *      3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2529  *         a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
2530  *            obtained in step 2
2531  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
2532  *         c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
2533  *            of TX descriptors.  Leave flags field clear.
2534  *      4) Access TX descriptors via host memory.  The chip
2535  *         will refetch into local SRAM as needed when producer
2536  *         index mailboxes are updated.
2537  *
2538  * To use on-chip TX descriptors:
2539  *      1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
2540  *         Make sure GRC_MODE_HOST_SENDBDS is clear.
2541  *      2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2542  *         a) Set TG3_BDINFO_HOST_ADDR to zero.
2543  *         b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
2544  *         c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
2545  *      3) Access TX descriptors directly in on-chip SRAM
2546  *         using normal {read,write}l().  (and not using
2547  *         pointer dereferencing of ioremap()'d memory like
2548  *         the broken Broadcom driver does)
2549  *
2550  * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
2551  * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
2552  */
2553 struct tg3_tx_buffer_desc {
2554         u32                             addr_hi;
2555         u32                             addr_lo;
2556 
2557         u32                             len_flags;
2558 #define TXD_FLAG_TCPUDP_CSUM            0x0001
2559 #define TXD_FLAG_IP_CSUM                0x0002
2560 #define TXD_FLAG_END                    0x0004
2561 #define TXD_FLAG_IP_FRAG                0x0008
2562 #define TXD_FLAG_JMB_PKT                0x0008
2563 #define TXD_FLAG_IP_FRAG_END            0x0010
2564 #define TXD_FLAG_HWTSTAMP               0x0020
2565 #define TXD_FLAG_VLAN                   0x0040
2566 #define TXD_FLAG_COAL_NOW               0x0080
2567 #define TXD_FLAG_CPU_PRE_DMA            0x0100
2568 #define TXD_FLAG_CPU_POST_DMA           0x0200
2569 #define TXD_FLAG_ADD_SRC_ADDR           0x1000
2570 #define TXD_FLAG_CHOOSE_SRC_ADDR        0x6000
2571 #define TXD_FLAG_NO_CRC                 0x8000
2572 #define TXD_LEN_SHIFT                   16
2573 
2574         u32                             vlan_tag;
2575 #define TXD_VLAN_TAG_SHIFT              0
2576 #define TXD_MSS_SHIFT                   16
2577 };
2578 
2579 #define TXD_ADDR                        0x00UL /* 64-bit */
2580 #define TXD_LEN_FLAGS                   0x08UL /* 32-bit (upper 16-bits are len) */
2581 #define TXD_VLAN_TAG                    0x0cUL /* 32-bit (upper 16-bits are tag) */
2582 #define TXD_SIZE                        0x10UL
2583 
2584 struct tg3_rx_buffer_desc {
2585         u32                             addr_hi;
2586         u32                             addr_lo;
2587 
2588         u32                             idx_len;
2589 #define RXD_IDX_MASK    0xffff0000
2590 #define RXD_IDX_SHIFT   16
2591 #define RXD_LEN_MASK    0x0000ffff
2592 #define RXD_LEN_SHIFT   0
2593 
2594         u32                             type_flags;
2595 #define RXD_TYPE_SHIFT  16
2596 #define RXD_FLAGS_SHIFT 0
2597 
2598 #define RXD_FLAG_END                    0x0004
2599 #define RXD_FLAG_MINI                   0x0800
2600 #define RXD_FLAG_JUMBO                  0x0020
2601 #define RXD_FLAG_VLAN                   0x0040
2602 #define RXD_FLAG_ERROR                  0x0400
2603 #define RXD_FLAG_IP_CSUM                0x1000
2604 #define RXD_FLAG_TCPUDP_CSUM            0x2000
2605 #define RXD_FLAG_IS_TCP                 0x4000
2606 #define RXD_FLAG_PTPSTAT_MASK           0x0210
2607 #define RXD_FLAG_PTPSTAT_PTPV1          0x0010
2608 #define RXD_FLAG_PTPSTAT_PTPV2          0x0200
2609 
2610         u32                             ip_tcp_csum;
2611 #define RXD_IPCSUM_MASK         0xffff0000
2612 #define RXD_IPCSUM_SHIFT        16
2613 #define RXD_TCPCSUM_MASK        0x0000ffff
2614 #define RXD_TCPCSUM_SHIFT       0
2615 
2616         u32                             err_vlan;
2617 
2618 #define RXD_VLAN_MASK                   0x0000ffff
2619 
2620 #define RXD_ERR_BAD_CRC                 0x00010000
2621 #define RXD_ERR_COLLISION               0x00020000
2622 #define RXD_ERR_LINK_LOST               0x00040000
2623 #define RXD_ERR_PHY_DECODE              0x00080000
2624 #define RXD_ERR_ODD_NIBBLE_RCVD_MII     0x00100000
2625 #define RXD_ERR_MAC_ABRT                0x00200000
2626 #define RXD_ERR_TOO_SMALL               0x00400000
2627 #define RXD_ERR_NO_RESOURCES            0x00800000
2628 #define RXD_ERR_HUGE_FRAME              0x01000000
2629 
2630 #define RXD_ERR_MASK    (RXD_ERR_BAD_CRC | RXD_ERR_COLLISION |          \
2631                          RXD_ERR_LINK_LOST | RXD_ERR_PHY_DECODE |       \
2632                          RXD_ERR_MAC_ABRT | RXD_ERR_TOO_SMALL |         \
2633                          RXD_ERR_NO_RESOURCES | RXD_ERR_HUGE_FRAME)
2634 
2635         u32                             reserved;
2636         u32                             opaque;
2637 #define RXD_OPAQUE_INDEX_MASK           0x0000ffff
2638 #define RXD_OPAQUE_INDEX_SHIFT          0
2639 #define RXD_OPAQUE_RING_STD             0x00010000
2640 #define RXD_OPAQUE_RING_JUMBO           0x00020000
2641 #define RXD_OPAQUE_RING_MINI            0x00040000
2642 #define RXD_OPAQUE_RING_MASK            0x00070000
2643 };
2644 
2645 struct tg3_ext_rx_buffer_desc {
2646         struct {
2647                 u32                     addr_hi;
2648                 u32                     addr_lo;
2649         }                               addrlist[3];
2650         u32                             len2_len1;
2651         u32                             resv_len3;
2652         struct tg3_rx_buffer_desc       std;
2653 };
2654 
2655 /* We only use this when testing out the DMA engine
2656  * at probe time.  This is the internal format of buffer
2657  * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2658  */
2659 struct tg3_internal_buffer_desc {
2660         u32                             addr_hi;
2661         u32                             addr_lo;
2662         u32                             nic_mbuf;
2663         /* XXX FIX THIS */
2664 #ifdef __BIG_ENDIAN
2665         u16                             cqid_sqid;
2666         u16                             len;
2667 #else
2668         u16                             len;
2669         u16                             cqid_sqid;
2670 #endif
2671         u32                             flags;
2672         u32                             __cookie1;
2673         u32                             __cookie2;
2674         u32                             __cookie3;
2675 };
2676 
2677 #define TG3_HW_STATUS_SIZE              0x50
2678 struct tg3_hw_status {
2679         u32                             status;
2680 #define SD_STATUS_UPDATED               0x00000001
2681 #define SD_STATUS_LINK_CHG              0x00000002
2682 #define SD_STATUS_ERROR                 0x00000004
2683 
2684         u32                             status_tag;
2685 
2686 #ifdef __BIG_ENDIAN
2687         u16                             rx_consumer;
2688         u16                             rx_jumbo_consumer;
2689 #else
2690         u16                             rx_jumbo_consumer;
2691         u16                             rx_consumer;
2692 #endif
2693 
2694 #ifdef __BIG_ENDIAN
2695         u16                             reserved;
2696         u16                             rx_mini_consumer;
2697 #else
2698         u16                             rx_mini_consumer;
2699         u16                             reserved;
2700 #endif
2701         struct {
2702 #ifdef __BIG_ENDIAN
2703                 u16                     tx_consumer;
2704                 u16                     rx_producer;
2705 #else
2706                 u16                     rx_producer;
2707                 u16                     tx_consumer;
2708 #endif
2709         }                               idx[16];
2710 };
2711 
2712 typedef struct {
2713         u32 high, low;
2714 } tg3_stat64_t;
2715 
2716 struct tg3_hw_stats {
2717         u8                              __reserved0[0x400-0x300];
2718 
2719         /* Statistics maintained by Receive MAC. */
2720         tg3_stat64_t                    rx_octets;
2721         u64                             __reserved1;
2722         tg3_stat64_t                    rx_fragments;
2723         tg3_stat64_t                    rx_ucast_packets;
2724         tg3_stat64_t                    rx_mcast_packets;
2725         tg3_stat64_t                    rx_bcast_packets;
2726         tg3_stat64_t                    rx_fcs_errors;
2727         tg3_stat64_t                    rx_align_errors;
2728         tg3_stat64_t                    rx_xon_pause_rcvd;
2729         tg3_stat64_t                    rx_xoff_pause_rcvd;
2730         tg3_stat64_t                    rx_mac_ctrl_rcvd;
2731         tg3_stat64_t                    rx_xoff_entered;
2732         tg3_stat64_t                    rx_frame_too_long_errors;
2733         tg3_stat64_t                    rx_jabbers;
2734         tg3_stat64_t                    rx_undersize_packets;
2735         tg3_stat64_t                    rx_in_length_errors;
2736         tg3_stat64_t                    rx_out_length_errors;
2737         tg3_stat64_t                    rx_64_or_less_octet_packets;
2738         tg3_stat64_t                    rx_65_to_127_octet_packets;
2739         tg3_stat64_t                    rx_128_to_255_octet_packets;
2740         tg3_stat64_t                    rx_256_to_511_octet_packets;
2741         tg3_stat64_t                    rx_512_to_1023_octet_packets;
2742         tg3_stat64_t                    rx_1024_to_1522_octet_packets;
2743         tg3_stat64_t                    rx_1523_to_2047_octet_packets;
2744         tg3_stat64_t                    rx_2048_to_4095_octet_packets;
2745         tg3_stat64_t                    rx_4096_to_8191_octet_packets;
2746         tg3_stat64_t                    rx_8192_to_9022_octet_packets;
2747 
2748         u64                             __unused0[37];
2749 
2750         /* Statistics maintained by Transmit MAC. */
2751         tg3_stat64_t                    tx_octets;
2752         u64                             __reserved2;
2753         tg3_stat64_t                    tx_collisions;
2754         tg3_stat64_t                    tx_xon_sent;
2755         tg3_stat64_t                    tx_xoff_sent;
2756         tg3_stat64_t                    tx_flow_control;
2757         tg3_stat64_t                    tx_mac_errors;
2758         tg3_stat64_t                    tx_single_collisions;
2759         tg3_stat64_t                    tx_mult_collisions;
2760         tg3_stat64_t                    tx_deferred;
2761         u64                             __reserved3;
2762         tg3_stat64_t                    tx_excessive_collisions;
2763         tg3_stat64_t                    tx_late_collisions;
2764         tg3_stat64_t                    tx_collide_2times;
2765         tg3_stat64_t                    tx_collide_3times;
2766         tg3_stat64_t                    tx_collide_4times;
2767         tg3_stat64_t                    tx_collide_5times;
2768         tg3_stat64_t                    tx_collide_6times;
2769         tg3_stat64_t                    tx_collide_7times;
2770         tg3_stat64_t                    tx_collide_8times;
2771         tg3_stat64_t                    tx_collide_9times;
2772         tg3_stat64_t                    tx_collide_10times;
2773         tg3_stat64_t                    tx_collide_11times;
2774         tg3_stat64_t                    tx_collide_12times;
2775         tg3_stat64_t                    tx_collide_13times;
2776         tg3_stat64_t                    tx_collide_14times;
2777         tg3_stat64_t                    tx_collide_15times;
2778         tg3_stat64_t                    tx_ucast_packets;
2779         tg3_stat64_t                    tx_mcast_packets;
2780         tg3_stat64_t                    tx_bcast_packets;
2781         tg3_stat64_t                    tx_carrier_sense_errors;
2782         tg3_stat64_t                    tx_discards;
2783         tg3_stat64_t                    tx_errors;
2784 
2785         u64                             __unused1[31];
2786 
2787         /* Statistics maintained by Receive List Placement. */
2788         tg3_stat64_t                    COS_rx_packets[16];
2789         tg3_stat64_t                    COS_rx_filter_dropped;
2790         tg3_stat64_t                    dma_writeq_full;
2791         tg3_stat64_t                    dma_write_prioq_full;
2792         tg3_stat64_t                    rxbds_empty;
2793         tg3_stat64_t                    rx_discards;
2794         tg3_stat64_t                    rx_errors;
2795         tg3_stat64_t                    rx_threshold_hit;
2796 
2797         u64                             __unused2[9];
2798 
2799         /* Statistics maintained by Send Data Initiator. */
2800         tg3_stat64_t                    COS_out_packets[16];
2801         tg3_stat64_t                    dma_readq_full;
2802         tg3_stat64_t                    dma_read_prioq_full;
2803         tg3_stat64_t                    tx_comp_queue_full;
2804 
2805         /* Statistics maintained by Host Coalescing. */
2806         tg3_stat64_t                    ring_set_send_prod_index;
2807         tg3_stat64_t                    ring_status_update;
2808         tg3_stat64_t                    nic_irqs;
2809         tg3_stat64_t                    nic_avoided_irqs;
2810         tg3_stat64_t                    nic_tx_threshold_hit;
2811 
2812         /* NOT a part of the hardware statistics block format.
2813          * These stats are here as storage for tg3_periodic_fetch_stats().
2814          */
2815         tg3_stat64_t                    mbuf_lwm_thresh_hit;
2816 
2817         u8                              __reserved4[0xb00-0x9c8];
2818 };
2819 
2820 #define TG3_SD_NUM_RECS                 3
2821 #define TG3_OCIR_LEN                    (sizeof(struct tg3_ocir))
2822 #define TG3_OCIR_SIG_MAGIC              0x5253434f
2823 #define TG3_OCIR_FLAG_ACTIVE            0x00000001
2824 
2825 #define TG3_TEMP_CAUTION_OFFSET         0xc8
2826 #define TG3_TEMP_MAX_OFFSET             0xcc
2827 #define TG3_TEMP_SENSOR_OFFSET          0xd4
2828 
2829 
2830 struct tg3_ocir {
2831         u32                             signature;
2832         u16                             version_flags;
2833         u16                             refresh_int;
2834         u32                             refresh_tmr;
2835         u32                             update_tmr;
2836         u32                             dst_base_addr;
2837         u16                             src_hdr_offset;
2838         u16                             src_hdr_length;
2839         u16                             src_data_offset;
2840         u16                             src_data_length;
2841         u16                             dst_hdr_offset;
2842         u16                             dst_data_offset;
2843         u16                             dst_reg_upd_offset;
2844         u16                             dst_sem_offset;
2845         u32                             reserved1[2];
2846         u32                             port0_flags;
2847         u32                             port1_flags;
2848         u32                             port2_flags;
2849         u32                             port3_flags;
2850         u32                             reserved2[1];
2851 };
2852 
2853 
2854 /* 'mapping' is superfluous as the chip does not write into
2855  * the tx/rx post rings so we could just fetch it from there.
2856  * But the cache behavior is better how we are doing it now.
2857  *
2858  * This driver uses new build_skb() API :
2859  * RX ring buffer contains pointer to kmalloc() data only,
2860  * skb are built only after Hardware filled the frame.
2861  */
2862 struct ring_info {
2863         u8                              *data;
2864         DEFINE_DMA_UNMAP_ADDR(mapping);
2865 };
2866 
2867 struct tg3_tx_ring_info {
2868         struct sk_buff                  *skb;
2869         DEFINE_DMA_UNMAP_ADDR(mapping);
2870         bool                            fragmented;
2871 };
2872 
2873 struct tg3_link_config {
2874         /* Describes what we're trying to get. */
2875         u32                             advertising;
2876         u32                             speed;
2877         u8                              duplex;
2878         u8                              autoneg;
2879         u8                              flowctrl;
2880 
2881         /* Describes what we actually have. */
2882         u8                              active_flowctrl;
2883 
2884         u8                              active_duplex;
2885         u32                             active_speed;
2886         u32                             rmt_adv;
2887 };
2888 
2889 struct tg3_bufmgr_config {
2890         u32             mbuf_read_dma_low_water;
2891         u32             mbuf_mac_rx_low_water;
2892         u32             mbuf_high_water;
2893 
2894         u32             mbuf_read_dma_low_water_jumbo;
2895         u32             mbuf_mac_rx_low_water_jumbo;
2896         u32             mbuf_high_water_jumbo;
2897 
2898         u32             dma_low_water;
2899         u32             dma_high_water;
2900 };
2901 
2902 struct tg3_ethtool_stats {
2903         /* Statistics maintained by Receive MAC. */
2904         u64             rx_octets;
2905         u64             rx_fragments;
2906         u64             rx_ucast_packets;
2907         u64             rx_mcast_packets;
2908         u64             rx_bcast_packets;
2909         u64             rx_fcs_errors;
2910         u64             rx_align_errors;
2911         u64             rx_xon_pause_rcvd;
2912         u64             rx_xoff_pause_rcvd;
2913         u64             rx_mac_ctrl_rcvd;
2914         u64             rx_xoff_entered;
2915         u64             rx_frame_too_long_errors;
2916         u64             rx_jabbers;
2917         u64             rx_undersize_packets;
2918         u64             rx_in_length_errors;
2919         u64             rx_out_length_errors;
2920         u64             rx_64_or_less_octet_packets;
2921         u64             rx_65_to_127_octet_packets;
2922         u64             rx_128_to_255_octet_packets;
2923         u64             rx_256_to_511_octet_packets;
2924         u64             rx_512_to_1023_octet_packets;
2925         u64             rx_1024_to_1522_octet_packets;
2926         u64             rx_1523_to_2047_octet_packets;
2927         u64             rx_2048_to_4095_octet_packets;
2928         u64             rx_4096_to_8191_octet_packets;
2929         u64             rx_8192_to_9022_octet_packets;
2930 
2931         /* Statistics maintained by Transmit MAC. */
2932         u64             tx_octets;
2933         u64             tx_collisions;
2934         u64             tx_xon_sent;
2935         u64             tx_xoff_sent;
2936         u64             tx_flow_control;
2937         u64             tx_mac_errors;
2938         u64             tx_single_collisions;
2939         u64             tx_mult_collisions;
2940         u64             tx_deferred;
2941         u64             tx_excessive_collisions;
2942         u64             tx_late_collisions;
2943         u64             tx_collide_2times;
2944         u64             tx_collide_3times;
2945         u64             tx_collide_4times;
2946         u64             tx_collide_5times;
2947         u64             tx_collide_6times;
2948         u64             tx_collide_7times;
2949         u64             tx_collide_8times;
2950         u64             tx_collide_9times;
2951         u64             tx_collide_10times;
2952         u64             tx_collide_11times;
2953         u64             tx_collide_12times;
2954         u64             tx_collide_13times;
2955         u64             tx_collide_14times;
2956         u64             tx_collide_15times;
2957         u64             tx_ucast_packets;
2958         u64             tx_mcast_packets;
2959         u64             tx_bcast_packets;
2960         u64             tx_carrier_sense_errors;
2961         u64             tx_discards;
2962         u64             tx_errors;
2963 
2964         /* Statistics maintained by Receive List Placement. */
2965         u64             dma_writeq_full;
2966         u64             dma_write_prioq_full;
2967         u64             rxbds_empty;
2968         u64             rx_discards;
2969         u64             rx_errors;
2970         u64             rx_threshold_hit;
2971 
2972         /* Statistics maintained by Send Data Initiator. */
2973         u64             dma_readq_full;
2974         u64             dma_read_prioq_full;
2975         u64             tx_comp_queue_full;
2976 
2977         /* Statistics maintained by Host Coalescing. */
2978         u64             ring_set_send_prod_index;
2979         u64             ring_status_update;
2980         u64             nic_irqs;
2981         u64             nic_avoided_irqs;
2982         u64             nic_tx_threshold_hit;
2983 
2984         u64             mbuf_lwm_thresh_hit;
2985 };
2986 
2987 struct tg3_rx_prodring_set {
2988         u32                             rx_std_prod_idx;
2989         u32                             rx_std_cons_idx;
2990         u32                             rx_jmb_prod_idx;
2991         u32                             rx_jmb_cons_idx;
2992         struct tg3_rx_buffer_desc       *rx_std;
2993         struct tg3_ext_rx_buffer_desc   *rx_jmb;
2994         struct ring_info                *rx_std_buffers;
2995         struct ring_info                *rx_jmb_buffers;
2996         dma_addr_t                      rx_std_mapping;
2997         dma_addr_t                      rx_jmb_mapping;
2998 };
2999 
3000 #define TG3_RSS_MAX_NUM_QS              4
3001 #define TG3_IRQ_MAX_VECS_RSS            (TG3_RSS_MAX_NUM_QS + 1)
3002 #define TG3_IRQ_MAX_VECS                TG3_IRQ_MAX_VECS_RSS
3003 
3004 struct tg3_napi {
3005         struct napi_struct              napi    ____cacheline_aligned;
3006         struct tg3                      *tp;
3007         struct tg3_hw_status            *hw_status;
3008 
3009         u32                             chk_msi_cnt;
3010         u32                             last_tag;
3011         u32                             last_irq_tag;
3012         u32                             int_mbox;
3013         u32                             coal_now;
3014 
3015         u32                             consmbox ____cacheline_aligned;
3016         u32                             rx_rcb_ptr;
3017         u32                             last_rx_cons;
3018         u16                             *rx_rcb_prod_idx;
3019         struct tg3_rx_prodring_set      prodring;
3020         struct tg3_rx_buffer_desc       *rx_rcb;
3021 
3022         u32                             tx_prod ____cacheline_aligned;
3023         u32                             tx_cons;
3024         u32                             tx_pending;
3025         u32                             last_tx_cons;
3026         u32                             prodmbox;
3027         struct tg3_tx_buffer_desc       *tx_ring;
3028         struct tg3_tx_ring_info         *tx_buffers;
3029 
3030         dma_addr_t                      status_mapping;
3031         dma_addr_t                      rx_rcb_mapping;
3032         dma_addr_t                      tx_desc_mapping;
3033 
3034         char                            irq_lbl[IFNAMSIZ];
3035         unsigned int                    irq_vec;
3036 };
3037 
3038 enum TG3_FLAGS {
3039         TG3_FLAG_TAGGED_STATUS = 0,
3040         TG3_FLAG_TXD_MBOX_HWBUG,
3041         TG3_FLAG_USE_LINKCHG_REG,
3042         TG3_FLAG_ERROR_PROCESSED,
3043         TG3_FLAG_ENABLE_ASF,
3044         TG3_FLAG_ASPM_WORKAROUND,
3045         TG3_FLAG_POLL_SERDES,
3046         TG3_FLAG_POLL_CPMU_LINK,
3047         TG3_FLAG_MBOX_WRITE_REORDER,
3048         TG3_FLAG_PCIX_TARGET_HWBUG,
3049         TG3_FLAG_WOL_SPEED_100MB,
3050         TG3_FLAG_WOL_ENABLE,
3051         TG3_FLAG_EEPROM_WRITE_PROT,
3052         TG3_FLAG_NVRAM,
3053         TG3_FLAG_NVRAM_BUFFERED,
3054         TG3_FLAG_SUPPORT_MSI,
3055         TG3_FLAG_SUPPORT_MSIX,
3056         TG3_FLAG_USING_MSI,
3057         TG3_FLAG_USING_MSIX,
3058         TG3_FLAG_PCIX_MODE,
3059         TG3_FLAG_PCI_HIGH_SPEED,
3060         TG3_FLAG_PCI_32BIT,
3061         TG3_FLAG_SRAM_USE_CONFIG,
3062         TG3_FLAG_TX_RECOVERY_PENDING,
3063         TG3_FLAG_WOL_CAP,
3064         TG3_FLAG_JUMBO_RING_ENABLE,
3065         TG3_FLAG_PAUSE_AUTONEG,
3066         TG3_FLAG_CPMU_PRESENT,
3067         TG3_FLAG_40BIT_DMA_BUG,
3068         TG3_FLAG_BROKEN_CHECKSUMS,
3069         TG3_FLAG_JUMBO_CAPABLE,
3070         TG3_FLAG_CHIP_RESETTING,
3071         TG3_FLAG_INIT_COMPLETE,
3072         TG3_FLAG_MAX_RXPEND_64,
3073         TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */
3074         TG3_FLAG_ASF_NEW_HANDSHAKE,
3075         TG3_FLAG_HW_AUTONEG,
3076         TG3_FLAG_IS_NIC,
3077         TG3_FLAG_FLASH,
3078         TG3_FLAG_FW_TSO,
3079         TG3_FLAG_HW_TSO_1,
3080         TG3_FLAG_HW_TSO_2,
3081         TG3_FLAG_HW_TSO_3,
3082         TG3_FLAG_TSO_CAPABLE,
3083         TG3_FLAG_TSO_BUG,
3084         TG3_FLAG_ICH_WORKAROUND,
3085         TG3_FLAG_1SHOT_MSI,
3086         TG3_FLAG_NO_FWARE_REPORTED,
3087         TG3_FLAG_NO_NVRAM_ADDR_TRANS,
3088         TG3_FLAG_ENABLE_APE,
3089         TG3_FLAG_PROTECTED_NVRAM,
3090         TG3_FLAG_5701_DMA_BUG,
3091         TG3_FLAG_USE_PHYLIB,
3092         TG3_FLAG_MDIOBUS_INITED,
3093         TG3_FLAG_LRG_PROD_RING_CAP,
3094         TG3_FLAG_RGMII_INBAND_DISABLE,
3095         TG3_FLAG_RGMII_EXT_IBND_RX_EN,
3096         TG3_FLAG_RGMII_EXT_IBND_TX_EN,
3097         TG3_FLAG_CLKREQ_BUG,
3098         TG3_FLAG_NO_NVRAM,
3099         TG3_FLAG_ENABLE_RSS,
3100         TG3_FLAG_ENABLE_TSS,
3101         TG3_FLAG_SHORT_DMA_BUG,
3102         TG3_FLAG_USE_JUMBO_BDFLAG,
3103         TG3_FLAG_L1PLLPD_EN,
3104         TG3_FLAG_APE_HAS_NCSI,
3105         TG3_FLAG_TX_TSTAMP_EN,
3106         TG3_FLAG_4K_FIFO_LIMIT,
3107         TG3_FLAG_5719_5720_RDMA_BUG,
3108         TG3_FLAG_RESET_TASK_PENDING,
3109         TG3_FLAG_PTP_CAPABLE,
3110         TG3_FLAG_5705_PLUS,
3111         TG3_FLAG_IS_5788,
3112         TG3_FLAG_5750_PLUS,
3113         TG3_FLAG_5780_CLASS,
3114         TG3_FLAG_5755_PLUS,
3115         TG3_FLAG_57765_PLUS,
3116         TG3_FLAG_57765_CLASS,
3117         TG3_FLAG_5717_PLUS,
3118         TG3_FLAG_IS_SSB_CORE,
3119         TG3_FLAG_FLUSH_POSTED_WRITES,
3120         TG3_FLAG_ROBOSWITCH,
3121         TG3_FLAG_ONE_DMA_AT_ONCE,
3122         TG3_FLAG_RGMII_MODE,
3123 
3124         /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
3125         TG3_FLAG_NUMBER_OF_FLAGS,       /* Last entry in enum TG3_FLAGS */
3126 };
3127 
3128 struct tg3_firmware_hdr {
3129         __be32 version; /* unused for fragments */
3130         __be32 base_addr;
3131         __be32 len;
3132 };
3133 #define TG3_FW_HDR_LEN         (sizeof(struct tg3_firmware_hdr))
3134 
3135 struct tg3 {
3136         /* begin "general, frequently-used members" cacheline section */
3137 
3138         /* If the IRQ handler (which runs lockless) needs to be
3139          * quiesced, the following bitmask state is used.  The
3140          * SYNC flag is set by non-IRQ context code to initiate
3141          * the quiescence.
3142          *
3143          * When the IRQ handler notices that SYNC is set, it
3144          * disables interrupts and returns.
3145          *
3146          * When all outstanding IRQ handlers have returned after
3147          * the SYNC flag has been set, the setter can be assured
3148          * that interrupts will no longer get run.
3149          *
3150          * In this way all SMP driver locks are never acquired
3151          * in hw IRQ context, only sw IRQ context or lower.
3152          */
3153         unsigned int                    irq_sync;
3154 
3155         /* SMP locking strategy:
3156          *
3157          * lock: Held during reset, PHY access, timer, and when
3158          *       updating tg3_flags.
3159          *
3160          * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
3161          *                netif_tx_lock when it needs to call
3162          *                netif_wake_queue.
3163          *
3164          * Both of these locks are to be held with BH safety.
3165          *
3166          * Because the IRQ handler, tg3_poll, and tg3_start_xmit
3167          * are running lockless, it is necessary to completely
3168          * quiesce the chip with tg3_netif_stop and tg3_full_lock
3169          * before reconfiguring the device.
3170          *
3171          * indirect_lock: Held when accessing registers indirectly
3172          *                with IRQ disabling.
3173          */
3174         spinlock_t                      lock;
3175         spinlock_t                      indirect_lock;
3176 
3177         u32                             (*read32) (struct tg3 *, u32);
3178         void                            (*write32) (struct tg3 *, u32, u32);
3179         u32                             (*read32_mbox) (struct tg3 *, u32);
3180         void                            (*write32_mbox) (struct tg3 *, u32,
3181                                                          u32);
3182         void __iomem                    *regs;
3183         void __iomem                    *aperegs;
3184         struct net_device               *dev;
3185         struct pci_dev                  *pdev;
3186 
3187         u32                             coal_now;
3188         u32                             msg_enable;
3189 
3190         struct ptp_clock_info           ptp_info;
3191         struct ptp_clock                *ptp_clock;
3192         s64                             ptp_adjust;
3193 
3194         /* begin "tx thread" cacheline section */
3195         void                            (*write32_tx_mbox) (struct tg3 *, u32,
3196                                                             u32);
3197         u32                             dma_limit;
3198         u32                             txq_req;
3199         u32                             txq_cnt;
3200         u32                             txq_max;
3201 
3202         /* begin "rx thread" cacheline section */
3203         struct tg3_napi                 napi[TG3_IRQ_MAX_VECS];
3204         void                            (*write32_rx_mbox) (struct tg3 *, u32,
3205                                                             u32);
3206         u32                             rx_copy_thresh;
3207         u32                             rx_std_ring_mask;
3208         u32                             rx_jmb_ring_mask;
3209         u32                             rx_ret_ring_mask;
3210         u32                             rx_pending;
3211         u32                             rx_jumbo_pending;
3212         u32                             rx_std_max_post;
3213         u32                             rx_offset;
3214         u32                             rx_pkt_map_sz;
3215         u32                             rxq_req;
3216         u32                             rxq_cnt;
3217         u32                             rxq_max;
3218         bool                            rx_refill;
3219 
3220 
3221         /* begin "everything else" cacheline(s) section */
3222         unsigned long                   rx_dropped;
3223         unsigned long                   tx_dropped;
3224         struct rtnl_link_stats64        net_stats_prev;
3225         struct tg3_ethtool_stats        estats_prev;
3226 
3227         DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
3228 
3229         union {
3230         unsigned long                   phy_crc_errors;
3231         unsigned long                   last_event_jiffies;
3232         };
3233 
3234         struct timer_list               timer;
3235         u16                             timer_counter;
3236         u16                             timer_multiplier;
3237         u32                             timer_offset;
3238         u16                             asf_counter;
3239         u16                             asf_multiplier;
3240 
3241         /* 1 second counter for transient serdes link events */
3242         u32                             serdes_counter;
3243 #define SERDES_AN_TIMEOUT_5704S         2
3244 #define SERDES_PARALLEL_DET_TIMEOUT     1
3245 #define SERDES_AN_TIMEOUT_5714S         1
3246 
3247         struct tg3_link_config          link_config;
3248         struct tg3_bufmgr_config        bufmgr_config;
3249 
3250         /* cache h/w values, often passed straight to h/w */
3251         u32                             rx_mode;
3252         u32                             tx_mode;
3253         u32                             mac_mode;
3254         u32                             mi_mode;
3255         u32                             misc_host_ctrl;
3256         u32                             grc_mode;
3257         u32                             grc_local_ctrl;
3258         u32                             dma_rwctrl;
3259         u32                             coalesce_mode;
3260         u32                             pwrmgmt_thresh;
3261         u32                             rxptpctl;
3262 
3263         /* PCI block */
3264         u32                             pci_chip_rev_id;
3265         u16                             pci_cmd;
3266         u8                              pci_cacheline_sz;
3267         u8                              pci_lat_timer;
3268 
3269         int                             pci_fn;
3270         int                             msi_cap;
3271         int                             pcix_cap;
3272         int                             pcie_readrq;
3273 
3274         struct mii_bus                  *mdio_bus;
3275         int                             old_link;
3276 
3277         u8                              phy_addr;
3278         u8                              phy_ape_lock;
3279 
3280         /* PHY info */
3281         u32                             phy_id;
3282 #define TG3_PHY_ID_MASK                 0xfffffff0
3283 #define TG3_PHY_ID_BCM5400              0x60008040
3284 #define TG3_PHY_ID_BCM5401              0x60008050
3285 #define TG3_PHY_ID_BCM5411              0x60008070
3286 #define TG3_PHY_ID_BCM5701              0x60008110
3287 #define TG3_PHY_ID_BCM5703              0x60008160
3288 #define TG3_PHY_ID_BCM5704              0x60008190
3289 #define TG3_PHY_ID_BCM5705              0x600081a0
3290 #define TG3_PHY_ID_BCM5750              0x60008180
3291 #define TG3_PHY_ID_BCM5752              0x60008100
3292 #define TG3_PHY_ID_BCM5714              0x60008340
3293 #define TG3_PHY_ID_BCM5780              0x60008350
3294 #define TG3_PHY_ID_BCM5755              0xbc050cc0
3295 #define TG3_PHY_ID_BCM5787              0xbc050ce0
3296 #define TG3_PHY_ID_BCM5756              0xbc050ed0
3297 #define TG3_PHY_ID_BCM5784              0xbc050fa0
3298 #define TG3_PHY_ID_BCM5761              0xbc050fd0
3299 #define TG3_PHY_ID_BCM5718C             0x5c0d8a00
3300 #define TG3_PHY_ID_BCM5718S             0xbc050ff0
3301 #define TG3_PHY_ID_BCM57765             0x5c0d8a40
3302 #define TG3_PHY_ID_BCM5719C             0x5c0d8a20
3303 #define TG3_PHY_ID_BCM5720C             0x5c0d8b60
3304 #define TG3_PHY_ID_BCM5762              0x85803780
3305 #define TG3_PHY_ID_BCM5906              0xdc00ac40
3306 #define TG3_PHY_ID_BCM8002              0x60010140
3307 #define TG3_PHY_ID_INVALID              0xffffffff
3308 
3309 #define PHY_ID_RTL8211C                 0x001cc910
3310 #define PHY_ID_RTL8201E                 0x00008200
3311 
3312 #define TG3_PHY_ID_REV_MASK             0x0000000f
3313 #define TG3_PHY_REV_BCM5401_B0          0x1
3314 
3315         /* This macro assumes the passed PHY ID is
3316          * already masked with TG3_PHY_ID_MASK.
3317          */
3318 #define TG3_KNOWN_PHY_ID(X)             \
3319         ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
3320          (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
3321          (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
3322          (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
3323          (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
3324          (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
3325          (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
3326          (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
3327          (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
3328          (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
3329          (X) == TG3_PHY_ID_BCM5720C || (X) == TG3_PHY_ID_BCM5762 || \
3330          (X) == TG3_PHY_ID_BCM8002)
3331 
3332         u32                             phy_flags;
3333 #define TG3_PHYFLG_IS_LOW_POWER         0x00000001
3334 #define TG3_PHYFLG_IS_CONNECTED         0x00000002
3335 #define TG3_PHYFLG_USE_MI_INTERRUPT     0x00000004
3336 #define TG3_PHYFLG_USER_CONFIGURED      0x00000008
3337 #define TG3_PHYFLG_PHY_SERDES           0x00000010
3338 #define TG3_PHYFLG_MII_SERDES           0x00000020
3339 #define TG3_PHYFLG_ANY_SERDES           (TG3_PHYFLG_PHY_SERDES |        \
3340                                         TG3_PHYFLG_MII_SERDES)
3341 #define TG3_PHYFLG_IS_FET               0x00000040
3342 #define TG3_PHYFLG_10_100_ONLY          0x00000080
3343 #define TG3_PHYFLG_ENABLE_APD           0x00000100
3344 #define TG3_PHYFLG_CAPACITIVE_COUPLING  0x00000200
3345 #define TG3_PHYFLG_NO_ETH_WIRE_SPEED    0x00000400
3346 #define TG3_PHYFLG_JITTER_BUG           0x00000800
3347 #define TG3_PHYFLG_ADJUST_TRIM          0x00001000
3348 #define TG3_PHYFLG_ADC_BUG              0x00002000
3349 #define TG3_PHYFLG_5704_A0_BUG          0x00004000
3350 #define TG3_PHYFLG_BER_BUG              0x00008000
3351 #define TG3_PHYFLG_SERDES_PREEMPHASIS   0x00010000
3352 #define TG3_PHYFLG_PARALLEL_DETECT      0x00020000
3353 #define TG3_PHYFLG_EEE_CAP              0x00040000
3354 #define TG3_PHYFLG_1G_ON_VAUX_OK        0x00080000
3355 #define TG3_PHYFLG_KEEP_LINK_ON_PWRDN   0x00100000
3356 #define TG3_PHYFLG_MDIX_STATE           0x00200000
3357 #define TG3_PHYFLG_DISABLE_1G_HD_ADV    0x00400000
3358 
3359         u32                             led_ctrl;
3360         u32                             phy_otp;
3361         u32                             setlpicnt;
3362         u8                              rss_ind_tbl[TG3_RSS_INDIR_TBL_SIZE];
3363 
3364 #define TG3_BPN_SIZE                    24
3365         char                            board_part_number[TG3_BPN_SIZE];
3366 #define TG3_VER_SIZE                    ETHTOOL_FWVERS_LEN
3367         char                            fw_ver[TG3_VER_SIZE];
3368         u32                             nic_sram_data_cfg;
3369         u32                             pci_clock_ctrl;
3370         struct pci_dev                  *pdev_peer;
3371 
3372         struct tg3_hw_stats             *hw_stats;
3373         dma_addr_t                      stats_mapping;
3374         struct work_struct              reset_task;
3375 
3376         int                             nvram_lock_cnt;
3377         u32                             nvram_size;
3378 #define TG3_NVRAM_SIZE_2KB              0x00000800
3379 #define TG3_NVRAM_SIZE_64KB             0x00010000
3380 #define TG3_NVRAM_SIZE_128KB            0x00020000
3381 #define TG3_NVRAM_SIZE_256KB            0x00040000
3382 #define TG3_NVRAM_SIZE_512KB            0x00080000
3383 #define TG3_NVRAM_SIZE_1MB              0x00100000
3384 #define TG3_NVRAM_SIZE_2MB              0x00200000
3385 
3386         u32                             nvram_pagesize;
3387         u32                             nvram_jedecnum;
3388 
3389 #define JEDEC_ATMEL                     0x1f
3390 #define JEDEC_ST                        0x20
3391 #define JEDEC_SAIFUN                    0x4f
3392 #define JEDEC_SST                       0xbf
3393 #define JEDEC_MACRONIX                 0xc2
3394 
3395 #define ATMEL_AT24C02_CHIP_SIZE         TG3_NVRAM_SIZE_2KB
3396 #define ATMEL_AT24C02_PAGE_SIZE         (8)
3397 
3398 #define ATMEL_AT24C64_CHIP_SIZE         TG3_NVRAM_SIZE_64KB
3399 #define ATMEL_AT24C64_PAGE_SIZE         (32)
3400 
3401 #define ATMEL_AT24C512_CHIP_SIZE        TG3_NVRAM_SIZE_512KB
3402 #define ATMEL_AT24C512_PAGE_SIZE        (128)
3403 
3404 #define ATMEL_AT45DB0X1B_PAGE_POS       9
3405 #define ATMEL_AT45DB0X1B_PAGE_SIZE      264
3406 
3407 #define ATMEL_AT25F512_PAGE_SIZE        256
3408 
3409 #define ST_M45PEX0_PAGE_SIZE            256
3410 
3411 #define SAIFUN_SA25F0XX_PAGE_SIZE       256
3412 
3413 #define SST_25VF0X0_PAGE_SIZE           4098
3414 
3415         unsigned int                    irq_max;
3416         unsigned int                    irq_cnt;
3417 
3418         struct ethtool_coalesce         coal;
3419         struct ethtool_eee              eee;
3420 
3421         /* firmware info */
3422         const char                      *fw_needed;
3423         const struct firmware           *fw;
3424         u32                             fw_len; /* includes BSS */
3425 
3426         struct device                   *hwmon_dev;
3427         bool                            link_up;
3428         bool                            pcierr_recovery;
3429 
3430         u32                             ape_hb;
3431         unsigned long                   ape_hb_interval;
3432         unsigned long                   ape_hb_jiffies;
3433 };
3434 
3435 /* Accessor macros for chip and asic attributes
3436  *
3437  * nb: Using static inlines equivalent to the accessor macros generates
3438  *     larger object code with gcc 4.7.
3439  *     Using statement expression macros to check tp with
3440  *     typecheck(struct tg3 *, tp) also creates larger objects.
3441  */
3442 #define tg3_chip_rev_id(tp)                                     \
3443         ((tp)->pci_chip_rev_id)
3444 #define tg3_asic_rev(tp)                                        \
3445         ((tp)->pci_chip_rev_id >> 12)
3446 #define tg3_chip_rev(tp)                                        \
3447         ((tp)->pci_chip_rev_id >> 8)
3448 
3449 #endif /* !(_T3_H) */