This source file includes following definitions.
- bcmgenet_writel
- bcmgenet_readl
- dmadesc_set_length_status
- dmadesc_get_length_status
- dmadesc_set_addr
- dmadesc_set
- dmadesc_get_addr
- bcmgenet_rbuf_ctrl_get
- bcmgenet_rbuf_ctrl_set
- bcmgenet_tbuf_ctrl_get
- bcmgenet_tbuf_ctrl_set
- bcmgenet_bp_mc_get
- bcmgenet_bp_mc_set
- dev_to_priv
- bcmgenet_tdma_readl
- bcmgenet_tdma_writel
- bcmgenet_rdma_readl
- bcmgenet_rdma_writel
- bcmgenet_tdma_ring_readl
- bcmgenet_tdma_ring_writel
- bcmgenet_rdma_ring_readl
- bcmgenet_rdma_ring_writel
- bcmgenet_begin
- bcmgenet_complete
- bcmgenet_get_link_ksettings
- bcmgenet_set_link_ksettings
- bcmgenet_set_rx_csum
- bcmgenet_set_tx_csum
- bcmgenet_set_features
- bcmgenet_get_msglevel
- bcmgenet_set_msglevel
- bcmgenet_get_coalesce
- bcmgenet_set_rx_coalesce
- bcmgenet_set_ring_rx_coalesce
- bcmgenet_set_coalesce
- bcmgenet_get_drvinfo
- bcmgenet_get_sset_count
- bcmgenet_get_strings
- bcmgenet_update_stat_misc
- bcmgenet_update_mib_counters
- bcmgenet_get_ethtool_stats
- bcmgenet_eee_enable_set
- bcmgenet_get_eee
- bcmgenet_set_eee
- bcmgenet_power_down
- bcmgenet_power_up
- bcmgenet_ioctl
- bcmgenet_get_txcb
- bcmgenet_put_txcb
- bcmgenet_rx_ring16_int_disable
- bcmgenet_rx_ring16_int_enable
- bcmgenet_rx_ring_int_disable
- bcmgenet_rx_ring_int_enable
- bcmgenet_tx_ring16_int_disable
- bcmgenet_tx_ring16_int_enable
- bcmgenet_tx_ring_int_enable
- bcmgenet_tx_ring_int_disable
- bcmgenet_free_tx_cb
- bcmgenet_free_rx_cb
- __bcmgenet_tx_reclaim
- bcmgenet_tx_reclaim
- bcmgenet_tx_poll
- bcmgenet_tx_reclaim_all
- bcmgenet_put_tx_csum
- bcmgenet_xmit
- bcmgenet_rx_refill
- bcmgenet_desc_rx
- bcmgenet_rx_poll
- bcmgenet_dim_work
- bcmgenet_alloc_rx_buffers
- bcmgenet_free_rx_buffers
- umac_enable_set
- reset_umac
- bcmgenet_intr_disable
- bcmgenet_link_intr_enable
- init_umac
- bcmgenet_init_dim
- bcmgenet_init_rx_coalesce
- bcmgenet_init_tx_ring
- bcmgenet_init_rx_ring
- bcmgenet_enable_tx_napi
- bcmgenet_disable_tx_napi
- bcmgenet_fini_tx_napi
- bcmgenet_init_tx_queues
- bcmgenet_enable_rx_napi
- bcmgenet_disable_rx_napi
- bcmgenet_fini_rx_napi
- bcmgenet_init_rx_queues
- bcmgenet_dma_teardown
- bcmgenet_fini_dma
- bcmgenet_init_dma
- bcmgenet_irq_task
- bcmgenet_isr1
- bcmgenet_isr0
- bcmgenet_wol_isr
- bcmgenet_poll_controller
- bcmgenet_umac_reset
- bcmgenet_set_hw_addr
- bcmgenet_dma_disable
- bcmgenet_enable_dma
- bcmgenet_hfb_clear
- bcmgenet_hfb_init
- bcmgenet_netif_start
- bcmgenet_open
- bcmgenet_netif_stop
- bcmgenet_close
- bcmgenet_dump_tx_queue
- bcmgenet_timeout
- bcmgenet_set_mdf_addr
- bcmgenet_set_rx_mode
- bcmgenet_set_mac_addr
- bcmgenet_get_stats
- bcmgenet_set_hw_params
- bcmgenet_probe
- bcmgenet_remove
- bcmgenet_resume
- bcmgenet_suspend
1
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6
7
8 #define pr_fmt(fmt) "bcmgenet: " fmt
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/types.h>
14 #include <linux/fcntl.h>
15 #include <linux/interrupt.h>
16 #include <linux/string.h>
17 #include <linux/if_ether.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/delay.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/pm.h>
24 #include <linux/clk.h>
25 #include <linux/of.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_net.h>
29 #include <linux/of_platform.h>
30 #include <net/arp.h>
31
32 #include <linux/mii.h>
33 #include <linux/ethtool.h>
34 #include <linux/netdevice.h>
35 #include <linux/inetdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/in.h>
39 #include <linux/ip.h>
40 #include <linux/ipv6.h>
41 #include <linux/phy.h>
42 #include <linux/platform_data/bcmgenet.h>
43
44 #include <asm/unaligned.h>
45
46 #include "bcmgenet.h"
47
48
49 #define GENET_MAX_MQ_CNT 4
50
51
52 #define GENET_Q0_PRIORITY 0
53
54 #define GENET_Q16_RX_BD_CNT \
55 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
56 #define GENET_Q16_TX_BD_CNT \
57 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
58
59 #define RX_BUF_LENGTH 2048
60 #define SKB_ALIGNMENT 32
61
62
63 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
64 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
65
66 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
67 TOTAL_DESC * DMA_DESC_SIZE)
68
69 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
73 {
74
75
76
77 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
78 __raw_writel(value, offset);
79 else
80 writel_relaxed(value, offset);
81 }
82
83 static inline u32 bcmgenet_readl(void __iomem *offset)
84 {
85 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
86 return __raw_readl(offset);
87 else
88 return readl_relaxed(offset);
89 }
90
91 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
92 void __iomem *d, u32 value)
93 {
94 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
95 }
96
97 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
98 void __iomem *d)
99 {
100 return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);
101 }
102
103 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
104 void __iomem *d,
105 dma_addr_t addr)
106 {
107 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
108
109
110
111
112
113 #ifdef CONFIG_PHYS_ADDR_T_64BIT
114 if (priv->hw_params->flags & GENET_HAS_40BITS)
115 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
116 #endif
117 }
118
119
120 static inline void dmadesc_set(struct bcmgenet_priv *priv,
121 void __iomem *d, dma_addr_t addr, u32 val)
122 {
123 dmadesc_set_addr(priv, d, addr);
124 dmadesc_set_length_status(priv, d, val);
125 }
126
127 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
128 void __iomem *d)
129 {
130 dma_addr_t addr;
131
132 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
133
134
135
136
137
138 #ifdef CONFIG_PHYS_ADDR_T_64BIT
139 if (priv->hw_params->flags & GENET_HAS_40BITS)
140 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
141 #endif
142 return addr;
143 }
144
145 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
146
147 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
148 NETIF_MSG_LINK)
149
150 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
151 {
152 if (GENET_IS_V1(priv))
153 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
154 else
155 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
156 }
157
158 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
159 {
160 if (GENET_IS_V1(priv))
161 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
162 else
163 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
164 }
165
166
167
168
169
170 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
171 {
172 if (GENET_IS_V1(priv))
173 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
174 else
175 return bcmgenet_readl(priv->base +
176 priv->hw_params->tbuf_offset + TBUF_CTRL);
177 }
178
179 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
180 {
181 if (GENET_IS_V1(priv))
182 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
183 else
184 bcmgenet_writel(val, priv->base +
185 priv->hw_params->tbuf_offset + TBUF_CTRL);
186 }
187
188 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
189 {
190 if (GENET_IS_V1(priv))
191 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
192 else
193 return bcmgenet_readl(priv->base +
194 priv->hw_params->tbuf_offset + TBUF_BP_MC);
195 }
196
197 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
198 {
199 if (GENET_IS_V1(priv))
200 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
201 else
202 bcmgenet_writel(val, priv->base +
203 priv->hw_params->tbuf_offset + TBUF_BP_MC);
204 }
205
206
207 enum dma_reg {
208 DMA_RING_CFG = 0,
209 DMA_CTRL,
210 DMA_STATUS,
211 DMA_SCB_BURST_SIZE,
212 DMA_ARB_CTRL,
213 DMA_PRIORITY_0,
214 DMA_PRIORITY_1,
215 DMA_PRIORITY_2,
216 DMA_INDEX2RING_0,
217 DMA_INDEX2RING_1,
218 DMA_INDEX2RING_2,
219 DMA_INDEX2RING_3,
220 DMA_INDEX2RING_4,
221 DMA_INDEX2RING_5,
222 DMA_INDEX2RING_6,
223 DMA_INDEX2RING_7,
224 DMA_RING0_TIMEOUT,
225 DMA_RING1_TIMEOUT,
226 DMA_RING2_TIMEOUT,
227 DMA_RING3_TIMEOUT,
228 DMA_RING4_TIMEOUT,
229 DMA_RING5_TIMEOUT,
230 DMA_RING6_TIMEOUT,
231 DMA_RING7_TIMEOUT,
232 DMA_RING8_TIMEOUT,
233 DMA_RING9_TIMEOUT,
234 DMA_RING10_TIMEOUT,
235 DMA_RING11_TIMEOUT,
236 DMA_RING12_TIMEOUT,
237 DMA_RING13_TIMEOUT,
238 DMA_RING14_TIMEOUT,
239 DMA_RING15_TIMEOUT,
240 DMA_RING16_TIMEOUT,
241 };
242
243 static const u8 bcmgenet_dma_regs_v3plus[] = {
244 [DMA_RING_CFG] = 0x00,
245 [DMA_CTRL] = 0x04,
246 [DMA_STATUS] = 0x08,
247 [DMA_SCB_BURST_SIZE] = 0x0C,
248 [DMA_ARB_CTRL] = 0x2C,
249 [DMA_PRIORITY_0] = 0x30,
250 [DMA_PRIORITY_1] = 0x34,
251 [DMA_PRIORITY_2] = 0x38,
252 [DMA_RING0_TIMEOUT] = 0x2C,
253 [DMA_RING1_TIMEOUT] = 0x30,
254 [DMA_RING2_TIMEOUT] = 0x34,
255 [DMA_RING3_TIMEOUT] = 0x38,
256 [DMA_RING4_TIMEOUT] = 0x3c,
257 [DMA_RING5_TIMEOUT] = 0x40,
258 [DMA_RING6_TIMEOUT] = 0x44,
259 [DMA_RING7_TIMEOUT] = 0x48,
260 [DMA_RING8_TIMEOUT] = 0x4c,
261 [DMA_RING9_TIMEOUT] = 0x50,
262 [DMA_RING10_TIMEOUT] = 0x54,
263 [DMA_RING11_TIMEOUT] = 0x58,
264 [DMA_RING12_TIMEOUT] = 0x5c,
265 [DMA_RING13_TIMEOUT] = 0x60,
266 [DMA_RING14_TIMEOUT] = 0x64,
267 [DMA_RING15_TIMEOUT] = 0x68,
268 [DMA_RING16_TIMEOUT] = 0x6C,
269 [DMA_INDEX2RING_0] = 0x70,
270 [DMA_INDEX2RING_1] = 0x74,
271 [DMA_INDEX2RING_2] = 0x78,
272 [DMA_INDEX2RING_3] = 0x7C,
273 [DMA_INDEX2RING_4] = 0x80,
274 [DMA_INDEX2RING_5] = 0x84,
275 [DMA_INDEX2RING_6] = 0x88,
276 [DMA_INDEX2RING_7] = 0x8C,
277 };
278
279 static const u8 bcmgenet_dma_regs_v2[] = {
280 [DMA_RING_CFG] = 0x00,
281 [DMA_CTRL] = 0x04,
282 [DMA_STATUS] = 0x08,
283 [DMA_SCB_BURST_SIZE] = 0x0C,
284 [DMA_ARB_CTRL] = 0x30,
285 [DMA_PRIORITY_0] = 0x34,
286 [DMA_PRIORITY_1] = 0x38,
287 [DMA_PRIORITY_2] = 0x3C,
288 [DMA_RING0_TIMEOUT] = 0x2C,
289 [DMA_RING1_TIMEOUT] = 0x30,
290 [DMA_RING2_TIMEOUT] = 0x34,
291 [DMA_RING3_TIMEOUT] = 0x38,
292 [DMA_RING4_TIMEOUT] = 0x3c,
293 [DMA_RING5_TIMEOUT] = 0x40,
294 [DMA_RING6_TIMEOUT] = 0x44,
295 [DMA_RING7_TIMEOUT] = 0x48,
296 [DMA_RING8_TIMEOUT] = 0x4c,
297 [DMA_RING9_TIMEOUT] = 0x50,
298 [DMA_RING10_TIMEOUT] = 0x54,
299 [DMA_RING11_TIMEOUT] = 0x58,
300 [DMA_RING12_TIMEOUT] = 0x5c,
301 [DMA_RING13_TIMEOUT] = 0x60,
302 [DMA_RING14_TIMEOUT] = 0x64,
303 [DMA_RING15_TIMEOUT] = 0x68,
304 [DMA_RING16_TIMEOUT] = 0x6C,
305 };
306
307 static const u8 bcmgenet_dma_regs_v1[] = {
308 [DMA_CTRL] = 0x00,
309 [DMA_STATUS] = 0x04,
310 [DMA_SCB_BURST_SIZE] = 0x0C,
311 [DMA_ARB_CTRL] = 0x30,
312 [DMA_PRIORITY_0] = 0x34,
313 [DMA_PRIORITY_1] = 0x38,
314 [DMA_PRIORITY_2] = 0x3C,
315 [DMA_RING0_TIMEOUT] = 0x2C,
316 [DMA_RING1_TIMEOUT] = 0x30,
317 [DMA_RING2_TIMEOUT] = 0x34,
318 [DMA_RING3_TIMEOUT] = 0x38,
319 [DMA_RING4_TIMEOUT] = 0x3c,
320 [DMA_RING5_TIMEOUT] = 0x40,
321 [DMA_RING6_TIMEOUT] = 0x44,
322 [DMA_RING7_TIMEOUT] = 0x48,
323 [DMA_RING8_TIMEOUT] = 0x4c,
324 [DMA_RING9_TIMEOUT] = 0x50,
325 [DMA_RING10_TIMEOUT] = 0x54,
326 [DMA_RING11_TIMEOUT] = 0x58,
327 [DMA_RING12_TIMEOUT] = 0x5c,
328 [DMA_RING13_TIMEOUT] = 0x60,
329 [DMA_RING14_TIMEOUT] = 0x64,
330 [DMA_RING15_TIMEOUT] = 0x68,
331 [DMA_RING16_TIMEOUT] = 0x6C,
332 };
333
334
335 static const u8 *bcmgenet_dma_regs;
336
337 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
338 {
339 return netdev_priv(dev_get_drvdata(dev));
340 }
341
342 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
343 enum dma_reg r)
344 {
345 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
346 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
347 }
348
349 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
350 u32 val, enum dma_reg r)
351 {
352 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
353 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
354 }
355
356 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
357 enum dma_reg r)
358 {
359 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
360 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
361 }
362
363 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
364 u32 val, enum dma_reg r)
365 {
366 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
367 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
368 }
369
370
371
372
373
374 enum dma_ring_reg {
375 TDMA_READ_PTR = 0,
376 RDMA_WRITE_PTR = TDMA_READ_PTR,
377 TDMA_READ_PTR_HI,
378 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
379 TDMA_CONS_INDEX,
380 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
381 TDMA_PROD_INDEX,
382 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
383 DMA_RING_BUF_SIZE,
384 DMA_START_ADDR,
385 DMA_START_ADDR_HI,
386 DMA_END_ADDR,
387 DMA_END_ADDR_HI,
388 DMA_MBUF_DONE_THRESH,
389 TDMA_FLOW_PERIOD,
390 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
391 TDMA_WRITE_PTR,
392 RDMA_READ_PTR = TDMA_WRITE_PTR,
393 TDMA_WRITE_PTR_HI,
394 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
395 };
396
397
398
399
400
401
402 static const u8 genet_dma_ring_regs_v4[] = {
403 [TDMA_READ_PTR] = 0x00,
404 [TDMA_READ_PTR_HI] = 0x04,
405 [TDMA_CONS_INDEX] = 0x08,
406 [TDMA_PROD_INDEX] = 0x0C,
407 [DMA_RING_BUF_SIZE] = 0x10,
408 [DMA_START_ADDR] = 0x14,
409 [DMA_START_ADDR_HI] = 0x18,
410 [DMA_END_ADDR] = 0x1C,
411 [DMA_END_ADDR_HI] = 0x20,
412 [DMA_MBUF_DONE_THRESH] = 0x24,
413 [TDMA_FLOW_PERIOD] = 0x28,
414 [TDMA_WRITE_PTR] = 0x2C,
415 [TDMA_WRITE_PTR_HI] = 0x30,
416 };
417
418 static const u8 genet_dma_ring_regs_v123[] = {
419 [TDMA_READ_PTR] = 0x00,
420 [TDMA_CONS_INDEX] = 0x04,
421 [TDMA_PROD_INDEX] = 0x08,
422 [DMA_RING_BUF_SIZE] = 0x0C,
423 [DMA_START_ADDR] = 0x10,
424 [DMA_END_ADDR] = 0x14,
425 [DMA_MBUF_DONE_THRESH] = 0x18,
426 [TDMA_FLOW_PERIOD] = 0x1C,
427 [TDMA_WRITE_PTR] = 0x20,
428 };
429
430
431 static const u8 *genet_dma_ring_regs;
432
433 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
434 unsigned int ring,
435 enum dma_ring_reg r)
436 {
437 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
438 (DMA_RING_SIZE * ring) +
439 genet_dma_ring_regs[r]);
440 }
441
442 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
443 unsigned int ring, u32 val,
444 enum dma_ring_reg r)
445 {
446 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
447 (DMA_RING_SIZE * ring) +
448 genet_dma_ring_regs[r]);
449 }
450
451 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
452 unsigned int ring,
453 enum dma_ring_reg r)
454 {
455 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
456 (DMA_RING_SIZE * ring) +
457 genet_dma_ring_regs[r]);
458 }
459
460 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
461 unsigned int ring, u32 val,
462 enum dma_ring_reg r)
463 {
464 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
465 (DMA_RING_SIZE * ring) +
466 genet_dma_ring_regs[r]);
467 }
468
469 static int bcmgenet_begin(struct net_device *dev)
470 {
471 struct bcmgenet_priv *priv = netdev_priv(dev);
472
473
474 return clk_prepare_enable(priv->clk);
475 }
476
477 static void bcmgenet_complete(struct net_device *dev)
478 {
479 struct bcmgenet_priv *priv = netdev_priv(dev);
480
481
482 clk_disable_unprepare(priv->clk);
483 }
484
485 static int bcmgenet_get_link_ksettings(struct net_device *dev,
486 struct ethtool_link_ksettings *cmd)
487 {
488 if (!netif_running(dev))
489 return -EINVAL;
490
491 if (!dev->phydev)
492 return -ENODEV;
493
494 phy_ethtool_ksettings_get(dev->phydev, cmd);
495
496 return 0;
497 }
498
499 static int bcmgenet_set_link_ksettings(struct net_device *dev,
500 const struct ethtool_link_ksettings *cmd)
501 {
502 if (!netif_running(dev))
503 return -EINVAL;
504
505 if (!dev->phydev)
506 return -ENODEV;
507
508 return phy_ethtool_ksettings_set(dev->phydev, cmd);
509 }
510
511 static int bcmgenet_set_rx_csum(struct net_device *dev,
512 netdev_features_t wanted)
513 {
514 struct bcmgenet_priv *priv = netdev_priv(dev);
515 u32 rbuf_chk_ctrl;
516 bool rx_csum_en;
517
518 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
519
520 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
521
522
523 if (rx_csum_en)
524 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
525 else
526 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
527 priv->desc_rxchk_en = rx_csum_en;
528
529
530
531
532 if (rx_csum_en && priv->crc_fwd_en)
533 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
534 else
535 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
536
537 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
538
539 return 0;
540 }
541
542 static int bcmgenet_set_tx_csum(struct net_device *dev,
543 netdev_features_t wanted)
544 {
545 struct bcmgenet_priv *priv = netdev_priv(dev);
546 bool desc_64b_en;
547 u32 tbuf_ctrl, rbuf_ctrl;
548
549 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
550 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
551
552 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
553
554
555 if (desc_64b_en) {
556 tbuf_ctrl |= RBUF_64B_EN;
557 rbuf_ctrl |= RBUF_64B_EN;
558 } else {
559 tbuf_ctrl &= ~RBUF_64B_EN;
560 rbuf_ctrl &= ~RBUF_64B_EN;
561 }
562 priv->desc_64b_en = desc_64b_en;
563
564 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
565 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
566
567 return 0;
568 }
569
570 static int bcmgenet_set_features(struct net_device *dev,
571 netdev_features_t features)
572 {
573 netdev_features_t changed = features ^ dev->features;
574 netdev_features_t wanted = dev->wanted_features;
575 int ret = 0;
576
577 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
578 ret = bcmgenet_set_tx_csum(dev, wanted);
579 if (changed & (NETIF_F_RXCSUM))
580 ret = bcmgenet_set_rx_csum(dev, wanted);
581
582 return ret;
583 }
584
585 static u32 bcmgenet_get_msglevel(struct net_device *dev)
586 {
587 struct bcmgenet_priv *priv = netdev_priv(dev);
588
589 return priv->msg_enable;
590 }
591
592 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
593 {
594 struct bcmgenet_priv *priv = netdev_priv(dev);
595
596 priv->msg_enable = level;
597 }
598
599 static int bcmgenet_get_coalesce(struct net_device *dev,
600 struct ethtool_coalesce *ec)
601 {
602 struct bcmgenet_priv *priv = netdev_priv(dev);
603 struct bcmgenet_rx_ring *ring;
604 unsigned int i;
605
606 ec->tx_max_coalesced_frames =
607 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
608 DMA_MBUF_DONE_THRESH);
609 ec->rx_max_coalesced_frames =
610 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
611 DMA_MBUF_DONE_THRESH);
612 ec->rx_coalesce_usecs =
613 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
614
615 for (i = 0; i < priv->hw_params->rx_queues; i++) {
616 ring = &priv->rx_rings[i];
617 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
618 }
619 ring = &priv->rx_rings[DESC_INDEX];
620 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
621
622 return 0;
623 }
624
625 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
626 u32 usecs, u32 pkts)
627 {
628 struct bcmgenet_priv *priv = ring->priv;
629 unsigned int i = ring->index;
630 u32 reg;
631
632 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
633
634 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
635 reg &= ~DMA_TIMEOUT_MASK;
636 reg |= DIV_ROUND_UP(usecs * 1000, 8192);
637 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
638 }
639
640 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
641 struct ethtool_coalesce *ec)
642 {
643 struct dim_cq_moder moder;
644 u32 usecs, pkts;
645
646 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
647 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
648 usecs = ring->rx_coalesce_usecs;
649 pkts = ring->rx_max_coalesced_frames;
650
651 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
652 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
653 usecs = moder.usec;
654 pkts = moder.pkts;
655 }
656
657 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
658 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
659 }
660
661 static int bcmgenet_set_coalesce(struct net_device *dev,
662 struct ethtool_coalesce *ec)
663 {
664 struct bcmgenet_priv *priv = netdev_priv(dev);
665 unsigned int i;
666
667
668
669
670
671 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
672 ec->tx_max_coalesced_frames == 0 ||
673 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
674 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
675 return -EINVAL;
676
677 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
678 return -EINVAL;
679
680
681
682
683
684 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
685 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low ||
686 ec->use_adaptive_tx_coalesce)
687 return -EOPNOTSUPP;
688
689
690
691
692 for (i = 0; i < priv->hw_params->tx_queues; i++)
693 bcmgenet_tdma_ring_writel(priv, i,
694 ec->tx_max_coalesced_frames,
695 DMA_MBUF_DONE_THRESH);
696 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
697 ec->tx_max_coalesced_frames,
698 DMA_MBUF_DONE_THRESH);
699
700 for (i = 0; i < priv->hw_params->rx_queues; i++)
701 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
702 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
703
704 return 0;
705 }
706
707
708 enum bcmgenet_stat_type {
709 BCMGENET_STAT_NETDEV = -1,
710 BCMGENET_STAT_MIB_RX,
711 BCMGENET_STAT_MIB_TX,
712 BCMGENET_STAT_RUNT,
713 BCMGENET_STAT_MISC,
714 BCMGENET_STAT_SOFT,
715 };
716
717 struct bcmgenet_stats {
718 char stat_string[ETH_GSTRING_LEN];
719 int stat_sizeof;
720 int stat_offset;
721 enum bcmgenet_stat_type type;
722
723 u16 reg_offset;
724 };
725
726 #define STAT_NETDEV(m) { \
727 .stat_string = __stringify(m), \
728 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
729 .stat_offset = offsetof(struct net_device_stats, m), \
730 .type = BCMGENET_STAT_NETDEV, \
731 }
732
733 #define STAT_GENET_MIB(str, m, _type) { \
734 .stat_string = str, \
735 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
736 .stat_offset = offsetof(struct bcmgenet_priv, m), \
737 .type = _type, \
738 }
739
740 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
741 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
742 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
743 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
744
745 #define STAT_GENET_MISC(str, m, offset) { \
746 .stat_string = str, \
747 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
748 .stat_offset = offsetof(struct bcmgenet_priv, m), \
749 .type = BCMGENET_STAT_MISC, \
750 .reg_offset = offset, \
751 }
752
753 #define STAT_GENET_Q(num) \
754 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
755 tx_rings[num].packets), \
756 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
757 tx_rings[num].bytes), \
758 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
759 rx_rings[num].bytes), \
760 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
761 rx_rings[num].packets), \
762 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
763 rx_rings[num].errors), \
764 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
765 rx_rings[num].dropped)
766
767
768
769
770 #define BCMGENET_STAT_OFFSET 0xc
771
772
773
774
775 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
776
777 STAT_NETDEV(rx_packets),
778 STAT_NETDEV(tx_packets),
779 STAT_NETDEV(rx_bytes),
780 STAT_NETDEV(tx_bytes),
781 STAT_NETDEV(rx_errors),
782 STAT_NETDEV(tx_errors),
783 STAT_NETDEV(rx_dropped),
784 STAT_NETDEV(tx_dropped),
785 STAT_NETDEV(multicast),
786
787 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
788 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
789 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
790 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
791 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
792 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
793 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
794 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
795 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
796 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
797 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
798 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
799 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
800 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
801 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
802 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
803 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
804 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
805 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
806 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
807 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
808 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
809 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
810 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
811 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
812 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
813 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
814 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
815 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
816
817 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
818 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
819 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
820 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
821 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
822 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
823 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
824 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
825 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
826 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
827 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
828 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
829 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
830 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
831 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
832 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
833 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
834 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
835 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
836 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
837 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
838 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
839 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
840 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
841 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
842 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
843 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
844 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
845 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
846
847 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
848 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
849 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
850 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
851
852 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
853 UMAC_RBUF_OVFL_CNT_V1),
854 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
855 UMAC_RBUF_ERR_CNT_V1),
856 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
857 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
858 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
859 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
860
861 STAT_GENET_Q(0),
862 STAT_GENET_Q(1),
863 STAT_GENET_Q(2),
864 STAT_GENET_Q(3),
865 STAT_GENET_Q(16),
866 };
867
868 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
869
870 static void bcmgenet_get_drvinfo(struct net_device *dev,
871 struct ethtool_drvinfo *info)
872 {
873 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
874 strlcpy(info->version, "v2.0", sizeof(info->version));
875 }
876
877 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
878 {
879 switch (string_set) {
880 case ETH_SS_STATS:
881 return BCMGENET_STATS_LEN;
882 default:
883 return -EOPNOTSUPP;
884 }
885 }
886
887 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
888 u8 *data)
889 {
890 int i;
891
892 switch (stringset) {
893 case ETH_SS_STATS:
894 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
895 memcpy(data + i * ETH_GSTRING_LEN,
896 bcmgenet_gstrings_stats[i].stat_string,
897 ETH_GSTRING_LEN);
898 }
899 break;
900 }
901 }
902
903 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
904 {
905 u16 new_offset;
906 u32 val;
907
908 switch (offset) {
909 case UMAC_RBUF_OVFL_CNT_V1:
910 if (GENET_IS_V2(priv))
911 new_offset = RBUF_OVFL_CNT_V2;
912 else
913 new_offset = RBUF_OVFL_CNT_V3PLUS;
914
915 val = bcmgenet_rbuf_readl(priv, new_offset);
916
917 if (val == ~0)
918 bcmgenet_rbuf_writel(priv, 0, new_offset);
919 break;
920 case UMAC_RBUF_ERR_CNT_V1:
921 if (GENET_IS_V2(priv))
922 new_offset = RBUF_ERR_CNT_V2;
923 else
924 new_offset = RBUF_ERR_CNT_V3PLUS;
925
926 val = bcmgenet_rbuf_readl(priv, new_offset);
927
928 if (val == ~0)
929 bcmgenet_rbuf_writel(priv, 0, new_offset);
930 break;
931 default:
932 val = bcmgenet_umac_readl(priv, offset);
933
934 if (val == ~0)
935 bcmgenet_umac_writel(priv, 0, offset);
936 break;
937 }
938
939 return val;
940 }
941
942 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
943 {
944 int i, j = 0;
945
946 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
947 const struct bcmgenet_stats *s;
948 u8 offset = 0;
949 u32 val = 0;
950 char *p;
951
952 s = &bcmgenet_gstrings_stats[i];
953 switch (s->type) {
954 case BCMGENET_STAT_NETDEV:
955 case BCMGENET_STAT_SOFT:
956 continue;
957 case BCMGENET_STAT_RUNT:
958 offset += BCMGENET_STAT_OFFSET;
959
960 case BCMGENET_STAT_MIB_TX:
961 offset += BCMGENET_STAT_OFFSET;
962
963 case BCMGENET_STAT_MIB_RX:
964 val = bcmgenet_umac_readl(priv,
965 UMAC_MIB_START + j + offset);
966 offset = 0;
967 break;
968 case BCMGENET_STAT_MISC:
969 if (GENET_IS_V1(priv)) {
970 val = bcmgenet_umac_readl(priv, s->reg_offset);
971
972 if (val == ~0)
973 bcmgenet_umac_writel(priv, 0,
974 s->reg_offset);
975 } else {
976 val = bcmgenet_update_stat_misc(priv,
977 s->reg_offset);
978 }
979 break;
980 }
981
982 j += s->stat_sizeof;
983 p = (char *)priv + s->stat_offset;
984 *(u32 *)p = val;
985 }
986 }
987
988 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
989 struct ethtool_stats *stats,
990 u64 *data)
991 {
992 struct bcmgenet_priv *priv = netdev_priv(dev);
993 int i;
994
995 if (netif_running(dev))
996 bcmgenet_update_mib_counters(priv);
997
998 dev->netdev_ops->ndo_get_stats(dev);
999
1000 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1001 const struct bcmgenet_stats *s;
1002 char *p;
1003
1004 s = &bcmgenet_gstrings_stats[i];
1005 if (s->type == BCMGENET_STAT_NETDEV)
1006 p = (char *)&dev->stats;
1007 else
1008 p = (char *)priv;
1009 p += s->stat_offset;
1010 if (sizeof(unsigned long) != sizeof(u32) &&
1011 s->stat_sizeof == sizeof(unsigned long))
1012 data[i] = *(unsigned long *)p;
1013 else
1014 data[i] = *(u32 *)p;
1015 }
1016 }
1017
1018 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1019 {
1020 struct bcmgenet_priv *priv = netdev_priv(dev);
1021 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1022 u32 reg;
1023
1024 if (enable && !priv->clk_eee_enabled) {
1025 clk_prepare_enable(priv->clk_eee);
1026 priv->clk_eee_enabled = true;
1027 }
1028
1029 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1030 if (enable)
1031 reg |= EEE_EN;
1032 else
1033 reg &= ~EEE_EN;
1034 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1035
1036
1037 reg = bcmgenet_readl(priv->base + off);
1038 if (enable)
1039 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1040 else
1041 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1042 bcmgenet_writel(reg, priv->base + off);
1043
1044
1045 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1046 if (enable)
1047 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1048 else
1049 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1050 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1051
1052 if (!enable && priv->clk_eee_enabled) {
1053 clk_disable_unprepare(priv->clk_eee);
1054 priv->clk_eee_enabled = false;
1055 }
1056
1057 priv->eee.eee_enabled = enable;
1058 priv->eee.eee_active = enable;
1059 }
1060
1061 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1062 {
1063 struct bcmgenet_priv *priv = netdev_priv(dev);
1064 struct ethtool_eee *p = &priv->eee;
1065
1066 if (GENET_IS_V1(priv))
1067 return -EOPNOTSUPP;
1068
1069 if (!dev->phydev)
1070 return -ENODEV;
1071
1072 e->eee_enabled = p->eee_enabled;
1073 e->eee_active = p->eee_active;
1074 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1075
1076 return phy_ethtool_get_eee(dev->phydev, e);
1077 }
1078
1079 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1080 {
1081 struct bcmgenet_priv *priv = netdev_priv(dev);
1082 struct ethtool_eee *p = &priv->eee;
1083 int ret = 0;
1084
1085 if (GENET_IS_V1(priv))
1086 return -EOPNOTSUPP;
1087
1088 if (!dev->phydev)
1089 return -ENODEV;
1090
1091 p->eee_enabled = e->eee_enabled;
1092
1093 if (!p->eee_enabled) {
1094 bcmgenet_eee_enable_set(dev, false);
1095 } else {
1096 ret = phy_init_eee(dev->phydev, 0);
1097 if (ret) {
1098 netif_err(priv, hw, dev, "EEE initialization failed\n");
1099 return ret;
1100 }
1101
1102 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1103 bcmgenet_eee_enable_set(dev, true);
1104 }
1105
1106 return phy_ethtool_set_eee(dev->phydev, e);
1107 }
1108
1109
1110 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1111 .begin = bcmgenet_begin,
1112 .complete = bcmgenet_complete,
1113 .get_strings = bcmgenet_get_strings,
1114 .get_sset_count = bcmgenet_get_sset_count,
1115 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1116 .get_drvinfo = bcmgenet_get_drvinfo,
1117 .get_link = ethtool_op_get_link,
1118 .get_msglevel = bcmgenet_get_msglevel,
1119 .set_msglevel = bcmgenet_set_msglevel,
1120 .get_wol = bcmgenet_get_wol,
1121 .set_wol = bcmgenet_set_wol,
1122 .get_eee = bcmgenet_get_eee,
1123 .set_eee = bcmgenet_set_eee,
1124 .nway_reset = phy_ethtool_nway_reset,
1125 .get_coalesce = bcmgenet_get_coalesce,
1126 .set_coalesce = bcmgenet_set_coalesce,
1127 .get_link_ksettings = bcmgenet_get_link_ksettings,
1128 .set_link_ksettings = bcmgenet_set_link_ksettings,
1129 .get_ts_info = ethtool_op_get_ts_info,
1130 };
1131
1132
1133 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1134 enum bcmgenet_power_mode mode)
1135 {
1136 int ret = 0;
1137 u32 reg;
1138
1139 switch (mode) {
1140 case GENET_POWER_CABLE_SENSE:
1141 phy_detach(priv->dev->phydev);
1142 break;
1143
1144 case GENET_POWER_WOL_MAGIC:
1145 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1146 break;
1147
1148 case GENET_POWER_PASSIVE:
1149
1150 if (priv->hw_params->flags & GENET_HAS_EXT) {
1151 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1152 if (GENET_IS_V5(priv))
1153 reg |= EXT_PWR_DOWN_PHY_EN |
1154 EXT_PWR_DOWN_PHY_RD |
1155 EXT_PWR_DOWN_PHY_SD |
1156 EXT_PWR_DOWN_PHY_RX |
1157 EXT_PWR_DOWN_PHY_TX |
1158 EXT_IDDQ_GLBL_PWR;
1159 else
1160 reg |= EXT_PWR_DOWN_PHY;
1161
1162 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1163 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1164
1165 bcmgenet_phy_power_set(priv->dev, false);
1166 }
1167 break;
1168 default:
1169 break;
1170 }
1171
1172 return ret;
1173 }
1174
1175 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1176 enum bcmgenet_power_mode mode)
1177 {
1178 u32 reg;
1179
1180 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1181 return;
1182
1183 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1184
1185 switch (mode) {
1186 case GENET_POWER_PASSIVE:
1187 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1188 if (GENET_IS_V5(priv)) {
1189 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1190 EXT_PWR_DOWN_PHY_RD |
1191 EXT_PWR_DOWN_PHY_SD |
1192 EXT_PWR_DOWN_PHY_RX |
1193 EXT_PWR_DOWN_PHY_TX |
1194 EXT_IDDQ_GLBL_PWR);
1195 reg |= EXT_PHY_RESET;
1196 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1197 mdelay(1);
1198
1199 reg &= ~EXT_PHY_RESET;
1200 } else {
1201 reg &= ~EXT_PWR_DOWN_PHY;
1202 reg |= EXT_PWR_DN_EN_LD;
1203 }
1204 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1205 bcmgenet_phy_power_set(priv->dev, true);
1206 break;
1207
1208 case GENET_POWER_CABLE_SENSE:
1209
1210 if (!GENET_IS_V5(priv)) {
1211 reg |= EXT_PWR_DN_EN_LD;
1212 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1213 }
1214 break;
1215 case GENET_POWER_WOL_MAGIC:
1216 bcmgenet_wol_power_up_cfg(priv, mode);
1217 return;
1218 default:
1219 break;
1220 }
1221 }
1222
1223
1224 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1225 {
1226 if (!netif_running(dev))
1227 return -EINVAL;
1228
1229 if (!dev->phydev)
1230 return -ENODEV;
1231
1232 return phy_mii_ioctl(dev->phydev, rq, cmd);
1233 }
1234
1235 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1236 struct bcmgenet_tx_ring *ring)
1237 {
1238 struct enet_cb *tx_cb_ptr;
1239
1240 tx_cb_ptr = ring->cbs;
1241 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1242
1243
1244 if (ring->write_ptr == ring->end_ptr)
1245 ring->write_ptr = ring->cb_ptr;
1246 else
1247 ring->write_ptr++;
1248
1249 return tx_cb_ptr;
1250 }
1251
1252 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1253 struct bcmgenet_tx_ring *ring)
1254 {
1255 struct enet_cb *tx_cb_ptr;
1256
1257 tx_cb_ptr = ring->cbs;
1258 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1259
1260
1261 if (ring->write_ptr == ring->cb_ptr)
1262 ring->write_ptr = ring->end_ptr;
1263 else
1264 ring->write_ptr--;
1265
1266 return tx_cb_ptr;
1267 }
1268
1269 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1270 {
1271 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1272 INTRL2_CPU_MASK_SET);
1273 }
1274
1275 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1276 {
1277 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1278 INTRL2_CPU_MASK_CLEAR);
1279 }
1280
1281 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1282 {
1283 bcmgenet_intrl2_1_writel(ring->priv,
1284 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1285 INTRL2_CPU_MASK_SET);
1286 }
1287
1288 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1289 {
1290 bcmgenet_intrl2_1_writel(ring->priv,
1291 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1292 INTRL2_CPU_MASK_CLEAR);
1293 }
1294
1295 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1296 {
1297 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1298 INTRL2_CPU_MASK_SET);
1299 }
1300
1301 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1302 {
1303 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1304 INTRL2_CPU_MASK_CLEAR);
1305 }
1306
1307 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1308 {
1309 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1310 INTRL2_CPU_MASK_CLEAR);
1311 }
1312
1313 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1314 {
1315 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1316 INTRL2_CPU_MASK_SET);
1317 }
1318
1319
1320
1321
1322
1323 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1324 struct enet_cb *cb)
1325 {
1326 struct sk_buff *skb;
1327
1328 skb = cb->skb;
1329
1330 if (skb) {
1331 cb->skb = NULL;
1332 if (cb == GENET_CB(skb)->first_cb)
1333 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1334 dma_unmap_len(cb, dma_len),
1335 DMA_TO_DEVICE);
1336 else
1337 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1338 dma_unmap_len(cb, dma_len),
1339 DMA_TO_DEVICE);
1340 dma_unmap_addr_set(cb, dma_addr, 0);
1341
1342 if (cb == GENET_CB(skb)->last_cb)
1343 return skb;
1344
1345 } else if (dma_unmap_addr(cb, dma_addr)) {
1346 dma_unmap_page(dev,
1347 dma_unmap_addr(cb, dma_addr),
1348 dma_unmap_len(cb, dma_len),
1349 DMA_TO_DEVICE);
1350 dma_unmap_addr_set(cb, dma_addr, 0);
1351 }
1352
1353 return NULL;
1354 }
1355
1356
1357 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1358 struct enet_cb *cb)
1359 {
1360 struct sk_buff *skb;
1361
1362 skb = cb->skb;
1363 cb->skb = NULL;
1364
1365 if (dma_unmap_addr(cb, dma_addr)) {
1366 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1367 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1368 dma_unmap_addr_set(cb, dma_addr, 0);
1369 }
1370
1371 return skb;
1372 }
1373
1374
1375 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1376 struct bcmgenet_tx_ring *ring)
1377 {
1378 struct bcmgenet_priv *priv = netdev_priv(dev);
1379 unsigned int txbds_processed = 0;
1380 unsigned int bytes_compl = 0;
1381 unsigned int pkts_compl = 0;
1382 unsigned int txbds_ready;
1383 unsigned int c_index;
1384 struct sk_buff *skb;
1385
1386
1387 if (ring->index == DESC_INDEX)
1388 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1389 INTRL2_CPU_CLEAR);
1390 else
1391 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1392 INTRL2_CPU_CLEAR);
1393
1394
1395 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1396 & DMA_C_INDEX_MASK;
1397 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1398
1399 netif_dbg(priv, tx_done, dev,
1400 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1401 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1402
1403
1404 while (txbds_processed < txbds_ready) {
1405 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1406 &priv->tx_cbs[ring->clean_ptr]);
1407 if (skb) {
1408 pkts_compl++;
1409 bytes_compl += GENET_CB(skb)->bytes_sent;
1410 dev_consume_skb_any(skb);
1411 }
1412
1413 txbds_processed++;
1414 if (likely(ring->clean_ptr < ring->end_ptr))
1415 ring->clean_ptr++;
1416 else
1417 ring->clean_ptr = ring->cb_ptr;
1418 }
1419
1420 ring->free_bds += txbds_processed;
1421 ring->c_index = c_index;
1422
1423 ring->packets += pkts_compl;
1424 ring->bytes += bytes_compl;
1425
1426 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1427 pkts_compl, bytes_compl);
1428
1429 return txbds_processed;
1430 }
1431
1432 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1433 struct bcmgenet_tx_ring *ring)
1434 {
1435 unsigned int released;
1436
1437 spin_lock_bh(&ring->lock);
1438 released = __bcmgenet_tx_reclaim(dev, ring);
1439 spin_unlock_bh(&ring->lock);
1440
1441 return released;
1442 }
1443
1444 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1445 {
1446 struct bcmgenet_tx_ring *ring =
1447 container_of(napi, struct bcmgenet_tx_ring, napi);
1448 unsigned int work_done = 0;
1449 struct netdev_queue *txq;
1450
1451 spin_lock(&ring->lock);
1452 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1453 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1454 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1455 netif_tx_wake_queue(txq);
1456 }
1457 spin_unlock(&ring->lock);
1458
1459 if (work_done == 0) {
1460 napi_complete(napi);
1461 ring->int_enable(ring);
1462
1463 return 0;
1464 }
1465
1466 return budget;
1467 }
1468
1469 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1470 {
1471 struct bcmgenet_priv *priv = netdev_priv(dev);
1472 int i;
1473
1474 if (netif_is_multiqueue(dev)) {
1475 for (i = 0; i < priv->hw_params->tx_queues; i++)
1476 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1477 }
1478
1479 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1480 }
1481
1482
1483
1484
1485 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1486 struct sk_buff *skb)
1487 {
1488 struct status_64 *status = NULL;
1489 struct sk_buff *new_skb;
1490 u16 offset;
1491 u8 ip_proto;
1492 __be16 ip_ver;
1493 u32 tx_csum_info;
1494
1495 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1496
1497
1498
1499 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1500 dev_kfree_skb(skb);
1501 if (!new_skb) {
1502 dev->stats.tx_dropped++;
1503 return NULL;
1504 }
1505 skb = new_skb;
1506 }
1507
1508 skb_push(skb, sizeof(*status));
1509 status = (struct status_64 *)skb->data;
1510
1511 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1512 ip_ver = skb->protocol;
1513 switch (ip_ver) {
1514 case htons(ETH_P_IP):
1515 ip_proto = ip_hdr(skb)->protocol;
1516 break;
1517 case htons(ETH_P_IPV6):
1518 ip_proto = ipv6_hdr(skb)->nexthdr;
1519 break;
1520 default:
1521 return skb;
1522 }
1523
1524 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1525 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1526 (offset + skb->csum_offset);
1527
1528
1529
1530
1531 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1532 tx_csum_info |= STATUS_TX_CSUM_LV;
1533 if (ip_proto == IPPROTO_UDP &&
1534 ip_ver == htons(ETH_P_IP))
1535 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1536 } else {
1537 tx_csum_info = 0;
1538 }
1539
1540 status->tx_csum_info = tx_csum_info;
1541 }
1542
1543 return skb;
1544 }
1545
1546 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1547 {
1548 struct bcmgenet_priv *priv = netdev_priv(dev);
1549 struct device *kdev = &priv->pdev->dev;
1550 struct bcmgenet_tx_ring *ring = NULL;
1551 struct enet_cb *tx_cb_ptr;
1552 struct netdev_queue *txq;
1553 int nr_frags, index;
1554 dma_addr_t mapping;
1555 unsigned int size;
1556 skb_frag_t *frag;
1557 u32 len_stat;
1558 int ret;
1559 int i;
1560
1561 index = skb_get_queue_mapping(skb);
1562
1563
1564
1565
1566
1567
1568
1569 if (index == 0)
1570 index = DESC_INDEX;
1571 else
1572 index -= 1;
1573
1574 ring = &priv->tx_rings[index];
1575 txq = netdev_get_tx_queue(dev, ring->queue);
1576
1577 nr_frags = skb_shinfo(skb)->nr_frags;
1578
1579 spin_lock(&ring->lock);
1580 if (ring->free_bds <= (nr_frags + 1)) {
1581 if (!netif_tx_queue_stopped(txq)) {
1582 netif_tx_stop_queue(txq);
1583 netdev_err(dev,
1584 "%s: tx ring %d full when queue %d awake\n",
1585 __func__, index, ring->queue);
1586 }
1587 ret = NETDEV_TX_BUSY;
1588 goto out;
1589 }
1590
1591 if (skb_padto(skb, ETH_ZLEN)) {
1592 ret = NETDEV_TX_OK;
1593 goto out;
1594 }
1595
1596
1597
1598
1599 GENET_CB(skb)->bytes_sent = skb->len;
1600
1601
1602 if (priv->desc_64b_en) {
1603 skb = bcmgenet_put_tx_csum(dev, skb);
1604 if (!skb) {
1605 ret = NETDEV_TX_OK;
1606 goto out;
1607 }
1608 }
1609
1610 for (i = 0; i <= nr_frags; i++) {
1611 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1612
1613 BUG_ON(!tx_cb_ptr);
1614
1615 if (!i) {
1616
1617 GENET_CB(skb)->first_cb = tx_cb_ptr;
1618 size = skb_headlen(skb);
1619 mapping = dma_map_single(kdev, skb->data, size,
1620 DMA_TO_DEVICE);
1621 } else {
1622
1623 frag = &skb_shinfo(skb)->frags[i - 1];
1624 size = skb_frag_size(frag);
1625 mapping = skb_frag_dma_map(kdev, frag, 0, size,
1626 DMA_TO_DEVICE);
1627 }
1628
1629 ret = dma_mapping_error(kdev, mapping);
1630 if (ret) {
1631 priv->mib.tx_dma_failed++;
1632 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1633 ret = NETDEV_TX_OK;
1634 goto out_unmap_frags;
1635 }
1636 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1637 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1638
1639 tx_cb_ptr->skb = skb;
1640
1641 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1642 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1643
1644 if (!i) {
1645 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1646 if (skb->ip_summed == CHECKSUM_PARTIAL)
1647 len_stat |= DMA_TX_DO_CSUM;
1648 }
1649 if (i == nr_frags)
1650 len_stat |= DMA_EOP;
1651
1652 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1653 }
1654
1655 GENET_CB(skb)->last_cb = tx_cb_ptr;
1656 skb_tx_timestamp(skb);
1657
1658
1659 ring->free_bds -= nr_frags + 1;
1660 ring->prod_index += nr_frags + 1;
1661 ring->prod_index &= DMA_P_INDEX_MASK;
1662
1663 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1664
1665 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1666 netif_tx_stop_queue(txq);
1667
1668 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
1669
1670 bcmgenet_tdma_ring_writel(priv, ring->index,
1671 ring->prod_index, TDMA_PROD_INDEX);
1672 out:
1673 spin_unlock(&ring->lock);
1674
1675 return ret;
1676
1677 out_unmap_frags:
1678
1679 bcmgenet_put_txcb(priv, ring);
1680
1681
1682 while (i-- > 0) {
1683 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
1684 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
1685 }
1686
1687 dev_kfree_skb(skb);
1688 goto out;
1689 }
1690
1691 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1692 struct enet_cb *cb)
1693 {
1694 struct device *kdev = &priv->pdev->dev;
1695 struct sk_buff *skb;
1696 struct sk_buff *rx_skb;
1697 dma_addr_t mapping;
1698
1699
1700 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
1701 GFP_ATOMIC | __GFP_NOWARN);
1702 if (!skb) {
1703 priv->mib.alloc_rx_buff_failed++;
1704 netif_err(priv, rx_err, priv->dev,
1705 "%s: Rx skb allocation failed\n", __func__);
1706 return NULL;
1707 }
1708
1709
1710 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1711 DMA_FROM_DEVICE);
1712 if (dma_mapping_error(kdev, mapping)) {
1713 priv->mib.rx_dma_failed++;
1714 dev_kfree_skb_any(skb);
1715 netif_err(priv, rx_err, priv->dev,
1716 "%s: Rx skb DMA mapping failed\n", __func__);
1717 return NULL;
1718 }
1719
1720
1721 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
1722
1723
1724 cb->skb = skb;
1725 dma_unmap_addr_set(cb, dma_addr, mapping);
1726 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
1727 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1728
1729
1730 return rx_skb;
1731 }
1732
1733
1734
1735
1736 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1737 unsigned int budget)
1738 {
1739 struct bcmgenet_priv *priv = ring->priv;
1740 struct net_device *dev = priv->dev;
1741 struct enet_cb *cb;
1742 struct sk_buff *skb;
1743 u32 dma_length_status;
1744 unsigned long dma_flag;
1745 int len;
1746 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1747 unsigned int bytes_processed = 0;
1748 unsigned int p_index, mask;
1749 unsigned int discards;
1750 unsigned int chksum_ok = 0;
1751
1752
1753 if (ring->index == DESC_INDEX) {
1754 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1755 INTRL2_CPU_CLEAR);
1756 } else {
1757 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1758 bcmgenet_intrl2_1_writel(priv,
1759 mask,
1760 INTRL2_CPU_CLEAR);
1761 }
1762
1763 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1764
1765 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1766 DMA_P_INDEX_DISCARD_CNT_MASK;
1767 if (discards > ring->old_discards) {
1768 discards = discards - ring->old_discards;
1769 ring->errors += discards;
1770 ring->old_discards += discards;
1771
1772
1773 if (ring->old_discards >= 0xC000) {
1774 ring->old_discards = 0;
1775 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1776 RDMA_PROD_INDEX);
1777 }
1778 }
1779
1780 p_index &= DMA_P_INDEX_MASK;
1781 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1782
1783 netif_dbg(priv, rx_status, dev,
1784 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1785
1786 while ((rxpktprocessed < rxpkttoprocess) &&
1787 (rxpktprocessed < budget)) {
1788 cb = &priv->rx_cbs[ring->read_ptr];
1789 skb = bcmgenet_rx_refill(priv, cb);
1790
1791 if (unlikely(!skb)) {
1792 ring->dropped++;
1793 goto next;
1794 }
1795
1796 if (!priv->desc_64b_en) {
1797 dma_length_status =
1798 dmadesc_get_length_status(priv, cb->bd_addr);
1799 } else {
1800 struct status_64 *status;
1801
1802 status = (struct status_64 *)skb->data;
1803 dma_length_status = status->length_status;
1804 }
1805
1806
1807
1808
1809 dma_flag = dma_length_status & 0xffff;
1810 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1811
1812 netif_dbg(priv, rx_status, dev,
1813 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1814 __func__, p_index, ring->c_index,
1815 ring->read_ptr, dma_length_status);
1816
1817 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1818 netif_err(priv, rx_status, dev,
1819 "dropping fragmented packet!\n");
1820 ring->errors++;
1821 dev_kfree_skb_any(skb);
1822 goto next;
1823 }
1824
1825
1826 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1827 DMA_RX_OV |
1828 DMA_RX_NO |
1829 DMA_RX_LG |
1830 DMA_RX_RXER))) {
1831 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1832 (unsigned int)dma_flag);
1833 if (dma_flag & DMA_RX_CRC_ERROR)
1834 dev->stats.rx_crc_errors++;
1835 if (dma_flag & DMA_RX_OV)
1836 dev->stats.rx_over_errors++;
1837 if (dma_flag & DMA_RX_NO)
1838 dev->stats.rx_frame_errors++;
1839 if (dma_flag & DMA_RX_LG)
1840 dev->stats.rx_length_errors++;
1841 dev->stats.rx_errors++;
1842 dev_kfree_skb_any(skb);
1843 goto next;
1844 }
1845
1846 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1847 priv->desc_rxchk_en;
1848
1849 skb_put(skb, len);
1850 if (priv->desc_64b_en) {
1851 skb_pull(skb, 64);
1852 len -= 64;
1853 }
1854
1855 if (likely(chksum_ok))
1856 skb->ip_summed = CHECKSUM_UNNECESSARY;
1857
1858
1859 skb_pull(skb, 2);
1860 len -= 2;
1861
1862 if (priv->crc_fwd_en) {
1863 skb_trim(skb, len - ETH_FCS_LEN);
1864 len -= ETH_FCS_LEN;
1865 }
1866
1867 bytes_processed += len;
1868
1869
1870 skb->protocol = eth_type_trans(skb, priv->dev);
1871 ring->packets++;
1872 ring->bytes += len;
1873 if (dma_flag & DMA_RX_MULT)
1874 dev->stats.multicast++;
1875
1876
1877 napi_gro_receive(&ring->napi, skb);
1878 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1879
1880 next:
1881 rxpktprocessed++;
1882 if (likely(ring->read_ptr < ring->end_ptr))
1883 ring->read_ptr++;
1884 else
1885 ring->read_ptr = ring->cb_ptr;
1886
1887 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1888 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1889 }
1890
1891 ring->dim.bytes = bytes_processed;
1892 ring->dim.packets = rxpktprocessed;
1893
1894 return rxpktprocessed;
1895 }
1896
1897
1898 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1899 {
1900 struct bcmgenet_rx_ring *ring = container_of(napi,
1901 struct bcmgenet_rx_ring, napi);
1902 struct dim_sample dim_sample = {};
1903 unsigned int work_done;
1904
1905 work_done = bcmgenet_desc_rx(ring, budget);
1906
1907 if (work_done < budget) {
1908 napi_complete_done(napi, work_done);
1909 ring->int_enable(ring);
1910 }
1911
1912 if (ring->dim.use_dim) {
1913 dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
1914 ring->dim.bytes, &dim_sample);
1915 net_dim(&ring->dim.dim, dim_sample);
1916 }
1917
1918 return work_done;
1919 }
1920
1921 static void bcmgenet_dim_work(struct work_struct *work)
1922 {
1923 struct dim *dim = container_of(work, struct dim, work);
1924 struct bcmgenet_net_dim *ndim =
1925 container_of(dim, struct bcmgenet_net_dim, dim);
1926 struct bcmgenet_rx_ring *ring =
1927 container_of(ndim, struct bcmgenet_rx_ring, dim);
1928 struct dim_cq_moder cur_profile =
1929 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
1930
1931 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
1932 dim->state = DIM_START_MEASURE;
1933 }
1934
1935
1936 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1937 struct bcmgenet_rx_ring *ring)
1938 {
1939 struct enet_cb *cb;
1940 struct sk_buff *skb;
1941 int i;
1942
1943 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1944
1945
1946 for (i = 0; i < ring->size; i++) {
1947 cb = ring->cbs + i;
1948 skb = bcmgenet_rx_refill(priv, cb);
1949 if (skb)
1950 dev_consume_skb_any(skb);
1951 if (!cb->skb)
1952 return -ENOMEM;
1953 }
1954
1955 return 0;
1956 }
1957
1958 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1959 {
1960 struct sk_buff *skb;
1961 struct enet_cb *cb;
1962 int i;
1963
1964 for (i = 0; i < priv->num_rx_bds; i++) {
1965 cb = &priv->rx_cbs[i];
1966
1967 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1968 if (skb)
1969 dev_consume_skb_any(skb);
1970 }
1971 }
1972
1973 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1974 {
1975 u32 reg;
1976
1977 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1978 if (enable)
1979 reg |= mask;
1980 else
1981 reg &= ~mask;
1982 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1983
1984
1985
1986
1987 if (enable == 0)
1988 usleep_range(1000, 2000);
1989 }
1990
1991 static void reset_umac(struct bcmgenet_priv *priv)
1992 {
1993
1994 bcmgenet_rbuf_ctrl_set(priv, 0);
1995 udelay(10);
1996
1997
1998 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1999
2000
2001 bcmgenet_umac_writel(priv, CMD_SW_RESET | CMD_LCL_LOOP_EN, UMAC_CMD);
2002 }
2003
2004 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2005 {
2006
2007 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2008 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2009 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2010 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2011 }
2012
2013 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2014 {
2015 u32 int0_enable = 0;
2016
2017
2018
2019
2020 if (priv->internal_phy) {
2021 int0_enable |= UMAC_IRQ_LINK_EVENT;
2022 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2023 int0_enable |= UMAC_IRQ_PHY_DET_R;
2024 } else if (priv->ext_phy) {
2025 int0_enable |= UMAC_IRQ_LINK_EVENT;
2026 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2027 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2028 int0_enable |= UMAC_IRQ_LINK_EVENT;
2029 }
2030 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2031 }
2032
2033 static void init_umac(struct bcmgenet_priv *priv)
2034 {
2035 struct device *kdev = &priv->pdev->dev;
2036 u32 reg;
2037 u32 int0_enable = 0;
2038
2039 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2040
2041 reset_umac(priv);
2042
2043
2044 bcmgenet_umac_writel(priv,
2045 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2046 UMAC_MIB_CTRL);
2047 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2048
2049 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2050
2051
2052 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2053 reg |= RBUF_ALIGN_2B;
2054 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2055
2056 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2057 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2058
2059 bcmgenet_intr_disable(priv);
2060
2061
2062 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2063 reg = bcmgenet_bp_mc_get(priv);
2064 reg |= BIT(priv->hw_params->bp_in_en_shift);
2065
2066
2067 if (netif_is_multiqueue(priv->dev))
2068 reg |= priv->hw_params->bp_in_mask;
2069 else
2070 reg &= ~priv->hw_params->bp_in_mask;
2071 bcmgenet_bp_mc_set(priv, reg);
2072 }
2073
2074
2075 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2076 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2077
2078 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2079
2080 dev_dbg(kdev, "done init umac\n");
2081 }
2082
2083 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2084 void (*cb)(struct work_struct *work))
2085 {
2086 struct bcmgenet_net_dim *dim = &ring->dim;
2087
2088 INIT_WORK(&dim->dim.work, cb);
2089 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2090 dim->event_ctr = 0;
2091 dim->packets = 0;
2092 dim->bytes = 0;
2093 }
2094
2095 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2096 {
2097 struct bcmgenet_net_dim *dim = &ring->dim;
2098 struct dim_cq_moder moder;
2099 u32 usecs, pkts;
2100
2101 usecs = ring->rx_coalesce_usecs;
2102 pkts = ring->rx_max_coalesced_frames;
2103
2104
2105 if (dim->use_dim) {
2106 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2107 usecs = moder.usec;
2108 pkts = moder.pkts;
2109 }
2110
2111 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2112 }
2113
2114
2115 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2116 unsigned int index, unsigned int size,
2117 unsigned int start_ptr, unsigned int end_ptr)
2118 {
2119 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2120 u32 words_per_bd = WORDS_PER_BD(priv);
2121 u32 flow_period_val = 0;
2122
2123 spin_lock_init(&ring->lock);
2124 ring->priv = priv;
2125 ring->index = index;
2126 if (index == DESC_INDEX) {
2127 ring->queue = 0;
2128 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2129 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2130 } else {
2131 ring->queue = index + 1;
2132 ring->int_enable = bcmgenet_tx_ring_int_enable;
2133 ring->int_disable = bcmgenet_tx_ring_int_disable;
2134 }
2135 ring->cbs = priv->tx_cbs + start_ptr;
2136 ring->size = size;
2137 ring->clean_ptr = start_ptr;
2138 ring->c_index = 0;
2139 ring->free_bds = size;
2140 ring->write_ptr = start_ptr;
2141 ring->cb_ptr = start_ptr;
2142 ring->end_ptr = end_ptr - 1;
2143 ring->prod_index = 0;
2144
2145
2146 if (index != DESC_INDEX)
2147 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2148
2149 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2150 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2151 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2152
2153 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2154 TDMA_FLOW_PERIOD);
2155 bcmgenet_tdma_ring_writel(priv, index,
2156 ((size << DMA_RING_SIZE_SHIFT) |
2157 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2158
2159
2160 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2161 DMA_START_ADDR);
2162 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2163 TDMA_READ_PTR);
2164 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2165 TDMA_WRITE_PTR);
2166 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2167 DMA_END_ADDR);
2168
2169
2170 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2171 NAPI_POLL_WEIGHT);
2172 }
2173
2174
2175 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2176 unsigned int index, unsigned int size,
2177 unsigned int start_ptr, unsigned int end_ptr)
2178 {
2179 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2180 u32 words_per_bd = WORDS_PER_BD(priv);
2181 int ret;
2182
2183 ring->priv = priv;
2184 ring->index = index;
2185 if (index == DESC_INDEX) {
2186 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2187 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2188 } else {
2189 ring->int_enable = bcmgenet_rx_ring_int_enable;
2190 ring->int_disable = bcmgenet_rx_ring_int_disable;
2191 }
2192 ring->cbs = priv->rx_cbs + start_ptr;
2193 ring->size = size;
2194 ring->c_index = 0;
2195 ring->read_ptr = start_ptr;
2196 ring->cb_ptr = start_ptr;
2197 ring->end_ptr = end_ptr - 1;
2198
2199 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2200 if (ret)
2201 return ret;
2202
2203 bcmgenet_init_dim(ring, bcmgenet_dim_work);
2204 bcmgenet_init_rx_coalesce(ring);
2205
2206
2207 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2208 NAPI_POLL_WEIGHT);
2209
2210 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2211 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2212 bcmgenet_rdma_ring_writel(priv, index,
2213 ((size << DMA_RING_SIZE_SHIFT) |
2214 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2215 bcmgenet_rdma_ring_writel(priv, index,
2216 (DMA_FC_THRESH_LO <<
2217 DMA_XOFF_THRESHOLD_SHIFT) |
2218 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2219
2220
2221 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2222 DMA_START_ADDR);
2223 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2224 RDMA_READ_PTR);
2225 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2226 RDMA_WRITE_PTR);
2227 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2228 DMA_END_ADDR);
2229
2230 return ret;
2231 }
2232
2233 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2234 {
2235 unsigned int i;
2236 struct bcmgenet_tx_ring *ring;
2237
2238 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2239 ring = &priv->tx_rings[i];
2240 napi_enable(&ring->napi);
2241 ring->int_enable(ring);
2242 }
2243
2244 ring = &priv->tx_rings[DESC_INDEX];
2245 napi_enable(&ring->napi);
2246 ring->int_enable(ring);
2247 }
2248
2249 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2250 {
2251 unsigned int i;
2252 struct bcmgenet_tx_ring *ring;
2253
2254 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2255 ring = &priv->tx_rings[i];
2256 napi_disable(&ring->napi);
2257 }
2258
2259 ring = &priv->tx_rings[DESC_INDEX];
2260 napi_disable(&ring->napi);
2261 }
2262
2263 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2264 {
2265 unsigned int i;
2266 struct bcmgenet_tx_ring *ring;
2267
2268 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2269 ring = &priv->tx_rings[i];
2270 netif_napi_del(&ring->napi);
2271 }
2272
2273 ring = &priv->tx_rings[DESC_INDEX];
2274 netif_napi_del(&ring->napi);
2275 }
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292 static void bcmgenet_init_tx_queues(struct net_device *dev)
2293 {
2294 struct bcmgenet_priv *priv = netdev_priv(dev);
2295 u32 i, dma_enable;
2296 u32 dma_ctrl, ring_cfg;
2297 u32 dma_priority[3] = {0, 0, 0};
2298
2299 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2300 dma_enable = dma_ctrl & DMA_EN;
2301 dma_ctrl &= ~DMA_EN;
2302 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2303
2304 dma_ctrl = 0;
2305 ring_cfg = 0;
2306
2307
2308 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2309
2310
2311 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2312 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2313 i * priv->hw_params->tx_bds_per_q,
2314 (i + 1) * priv->hw_params->tx_bds_per_q);
2315 ring_cfg |= (1 << i);
2316 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2317 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2318 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2319 }
2320
2321
2322 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2323 priv->hw_params->tx_queues *
2324 priv->hw_params->tx_bds_per_q,
2325 TOTAL_DESC);
2326 ring_cfg |= (1 << DESC_INDEX);
2327 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2328 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2329 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2330 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2331
2332
2333 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2334 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2335 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2336
2337
2338 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2339
2340
2341 if (dma_enable)
2342 dma_ctrl |= DMA_EN;
2343 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2344 }
2345
2346 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2347 {
2348 unsigned int i;
2349 struct bcmgenet_rx_ring *ring;
2350
2351 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2352 ring = &priv->rx_rings[i];
2353 napi_enable(&ring->napi);
2354 ring->int_enable(ring);
2355 }
2356
2357 ring = &priv->rx_rings[DESC_INDEX];
2358 napi_enable(&ring->napi);
2359 ring->int_enable(ring);
2360 }
2361
2362 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2363 {
2364 unsigned int i;
2365 struct bcmgenet_rx_ring *ring;
2366
2367 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2368 ring = &priv->rx_rings[i];
2369 napi_disable(&ring->napi);
2370 cancel_work_sync(&ring->dim.dim.work);
2371 }
2372
2373 ring = &priv->rx_rings[DESC_INDEX];
2374 napi_disable(&ring->napi);
2375 cancel_work_sync(&ring->dim.dim.work);
2376 }
2377
2378 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2379 {
2380 unsigned int i;
2381 struct bcmgenet_rx_ring *ring;
2382
2383 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2384 ring = &priv->rx_rings[i];
2385 netif_napi_del(&ring->napi);
2386 }
2387
2388 ring = &priv->rx_rings[DESC_INDEX];
2389 netif_napi_del(&ring->napi);
2390 }
2391
2392
2393
2394
2395
2396
2397
2398
2399 static int bcmgenet_init_rx_queues(struct net_device *dev)
2400 {
2401 struct bcmgenet_priv *priv = netdev_priv(dev);
2402 u32 i;
2403 u32 dma_enable;
2404 u32 dma_ctrl;
2405 u32 ring_cfg;
2406 int ret;
2407
2408 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2409 dma_enable = dma_ctrl & DMA_EN;
2410 dma_ctrl &= ~DMA_EN;
2411 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2412
2413 dma_ctrl = 0;
2414 ring_cfg = 0;
2415
2416
2417 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2418 ret = bcmgenet_init_rx_ring(priv, i,
2419 priv->hw_params->rx_bds_per_q,
2420 i * priv->hw_params->rx_bds_per_q,
2421 (i + 1) *
2422 priv->hw_params->rx_bds_per_q);
2423 if (ret)
2424 return ret;
2425
2426 ring_cfg |= (1 << i);
2427 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2428 }
2429
2430
2431 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2432 priv->hw_params->rx_queues *
2433 priv->hw_params->rx_bds_per_q,
2434 TOTAL_DESC);
2435 if (ret)
2436 return ret;
2437
2438 ring_cfg |= (1 << DESC_INDEX);
2439 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2440
2441
2442 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2443
2444
2445 if (dma_enable)
2446 dma_ctrl |= DMA_EN;
2447 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2448
2449 return 0;
2450 }
2451
2452 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2453 {
2454 int ret = 0;
2455 int timeout = 0;
2456 u32 reg;
2457 u32 dma_ctrl;
2458 int i;
2459
2460
2461 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2462 reg &= ~DMA_EN;
2463 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2464
2465
2466 while (timeout++ < DMA_TIMEOUT_VAL) {
2467 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2468 if (reg & DMA_DISABLED)
2469 break;
2470
2471 udelay(1);
2472 }
2473
2474 if (timeout == DMA_TIMEOUT_VAL) {
2475 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2476 ret = -ETIMEDOUT;
2477 }
2478
2479
2480 usleep_range(10000, 20000);
2481
2482
2483 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2484 reg &= ~DMA_EN;
2485 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2486
2487 timeout = 0;
2488
2489 while (timeout++ < DMA_TIMEOUT_VAL) {
2490 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2491 if (reg & DMA_DISABLED)
2492 break;
2493
2494 udelay(1);
2495 }
2496
2497 if (timeout == DMA_TIMEOUT_VAL) {
2498 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2499 ret = -ETIMEDOUT;
2500 }
2501
2502 dma_ctrl = 0;
2503 for (i = 0; i < priv->hw_params->rx_queues; i++)
2504 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2505 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2506 reg &= ~dma_ctrl;
2507 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2508
2509 dma_ctrl = 0;
2510 for (i = 0; i < priv->hw_params->tx_queues; i++)
2511 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2512 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2513 reg &= ~dma_ctrl;
2514 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2515
2516 return ret;
2517 }
2518
2519 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2520 {
2521 struct netdev_queue *txq;
2522 int i;
2523
2524 bcmgenet_fini_rx_napi(priv);
2525 bcmgenet_fini_tx_napi(priv);
2526
2527 for (i = 0; i < priv->num_tx_bds; i++)
2528 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev,
2529 priv->tx_cbs + i));
2530
2531 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2532 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2533 netdev_tx_reset_queue(txq);
2534 }
2535
2536 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2537 netdev_tx_reset_queue(txq);
2538
2539 bcmgenet_free_rx_buffers(priv);
2540 kfree(priv->rx_cbs);
2541 kfree(priv->tx_cbs);
2542 }
2543
2544
2545 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2546 {
2547 int ret;
2548 unsigned int i;
2549 struct enet_cb *cb;
2550
2551 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2552
2553
2554 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2555 priv->num_rx_bds = TOTAL_DESC;
2556 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2557 GFP_KERNEL);
2558 if (!priv->rx_cbs)
2559 return -ENOMEM;
2560
2561 for (i = 0; i < priv->num_rx_bds; i++) {
2562 cb = priv->rx_cbs + i;
2563 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2564 }
2565
2566
2567 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2568 priv->num_tx_bds = TOTAL_DESC;
2569 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2570 GFP_KERNEL);
2571 if (!priv->tx_cbs) {
2572 kfree(priv->rx_cbs);
2573 return -ENOMEM;
2574 }
2575
2576 for (i = 0; i < priv->num_tx_bds; i++) {
2577 cb = priv->tx_cbs + i;
2578 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2579 }
2580
2581
2582 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2583
2584
2585 ret = bcmgenet_init_rx_queues(priv->dev);
2586 if (ret) {
2587 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2588 bcmgenet_free_rx_buffers(priv);
2589 kfree(priv->rx_cbs);
2590 kfree(priv->tx_cbs);
2591 return ret;
2592 }
2593
2594
2595 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2596
2597
2598 bcmgenet_init_tx_queues(priv->dev);
2599
2600 return 0;
2601 }
2602
2603
2604 static void bcmgenet_irq_task(struct work_struct *work)
2605 {
2606 unsigned int status;
2607 struct bcmgenet_priv *priv = container_of(
2608 work, struct bcmgenet_priv, bcmgenet_irq_work);
2609
2610 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2611
2612 spin_lock_irq(&priv->lock);
2613 status = priv->irq0_stat;
2614 priv->irq0_stat = 0;
2615 spin_unlock_irq(&priv->lock);
2616
2617 if (status & UMAC_IRQ_PHY_DET_R &&
2618 priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
2619 phy_init_hw(priv->dev->phydev);
2620 genphy_config_aneg(priv->dev->phydev);
2621 }
2622
2623
2624 if (status & UMAC_IRQ_LINK_EVENT)
2625 phy_mac_interrupt(priv->dev->phydev);
2626
2627 }
2628
2629
2630 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2631 {
2632 struct bcmgenet_priv *priv = dev_id;
2633 struct bcmgenet_rx_ring *rx_ring;
2634 struct bcmgenet_tx_ring *tx_ring;
2635 unsigned int index, status;
2636
2637
2638 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2639 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2640
2641
2642 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2643
2644 netif_dbg(priv, intr, priv->dev,
2645 "%s: IRQ=0x%x\n", __func__, status);
2646
2647
2648 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2649 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2650 continue;
2651
2652 rx_ring = &priv->rx_rings[index];
2653 rx_ring->dim.event_ctr++;
2654
2655 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2656 rx_ring->int_disable(rx_ring);
2657 __napi_schedule_irqoff(&rx_ring->napi);
2658 }
2659 }
2660
2661
2662 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2663 if (!(status & BIT(index)))
2664 continue;
2665
2666 tx_ring = &priv->tx_rings[index];
2667
2668 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2669 tx_ring->int_disable(tx_ring);
2670 __napi_schedule_irqoff(&tx_ring->napi);
2671 }
2672 }
2673
2674 return IRQ_HANDLED;
2675 }
2676
2677
2678 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2679 {
2680 struct bcmgenet_priv *priv = dev_id;
2681 struct bcmgenet_rx_ring *rx_ring;
2682 struct bcmgenet_tx_ring *tx_ring;
2683 unsigned int status;
2684 unsigned long flags;
2685
2686
2687 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2688 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2689
2690
2691 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2692
2693 netif_dbg(priv, intr, priv->dev,
2694 "IRQ=0x%x\n", status);
2695
2696 if (status & UMAC_IRQ_RXDMA_DONE) {
2697 rx_ring = &priv->rx_rings[DESC_INDEX];
2698 rx_ring->dim.event_ctr++;
2699
2700 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2701 rx_ring->int_disable(rx_ring);
2702 __napi_schedule_irqoff(&rx_ring->napi);
2703 }
2704 }
2705
2706 if (status & UMAC_IRQ_TXDMA_DONE) {
2707 tx_ring = &priv->tx_rings[DESC_INDEX];
2708
2709 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2710 tx_ring->int_disable(tx_ring);
2711 __napi_schedule_irqoff(&tx_ring->napi);
2712 }
2713 }
2714
2715 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2716 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2717 wake_up(&priv->wq);
2718 }
2719
2720
2721 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
2722 if (status) {
2723
2724 spin_lock_irqsave(&priv->lock, flags);
2725 priv->irq0_stat |= status;
2726 spin_unlock_irqrestore(&priv->lock, flags);
2727
2728 schedule_work(&priv->bcmgenet_irq_work);
2729 }
2730
2731 return IRQ_HANDLED;
2732 }
2733
2734 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2735 {
2736 struct bcmgenet_priv *priv = dev_id;
2737
2738 pm_wakeup_event(&priv->pdev->dev, 0);
2739
2740 return IRQ_HANDLED;
2741 }
2742
2743 #ifdef CONFIG_NET_POLL_CONTROLLER
2744 static void bcmgenet_poll_controller(struct net_device *dev)
2745 {
2746 struct bcmgenet_priv *priv = netdev_priv(dev);
2747
2748
2749 disable_irq(priv->irq0);
2750 bcmgenet_isr0(priv->irq0, priv);
2751 enable_irq(priv->irq0);
2752
2753
2754 disable_irq(priv->irq1);
2755 bcmgenet_isr1(priv->irq1, priv);
2756 enable_irq(priv->irq1);
2757 }
2758 #endif
2759
2760 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2761 {
2762 u32 reg;
2763
2764 reg = bcmgenet_rbuf_ctrl_get(priv);
2765 reg |= BIT(1);
2766 bcmgenet_rbuf_ctrl_set(priv, reg);
2767 udelay(10);
2768
2769 reg &= ~BIT(1);
2770 bcmgenet_rbuf_ctrl_set(priv, reg);
2771 udelay(10);
2772 }
2773
2774 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2775 unsigned char *addr)
2776 {
2777 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2778 (addr[2] << 8) | addr[3], UMAC_MAC0);
2779 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2780 }
2781
2782
2783 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2784 {
2785 u32 reg;
2786 u32 dma_ctrl;
2787
2788
2789 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2790 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2791 reg &= ~dma_ctrl;
2792 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2793
2794 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2795 reg &= ~dma_ctrl;
2796 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2797
2798 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2799 udelay(10);
2800 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2801
2802 return dma_ctrl;
2803 }
2804
2805 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2806 {
2807 u32 reg;
2808
2809 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2810 reg |= dma_ctrl;
2811 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2812
2813 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2814 reg |= dma_ctrl;
2815 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2816 }
2817
2818
2819
2820
2821
2822 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2823 {
2824 u32 i;
2825
2826 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2827 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2828 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2829
2830 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2831 bcmgenet_rdma_writel(priv, 0x0, i);
2832
2833 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2834 bcmgenet_hfb_reg_writel(priv, 0x0,
2835 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2836
2837 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2838 priv->hw_params->hfb_filter_size; i++)
2839 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2840 }
2841
2842 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2843 {
2844 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2845 return;
2846
2847 bcmgenet_hfb_clear(priv);
2848 }
2849
2850 static void bcmgenet_netif_start(struct net_device *dev)
2851 {
2852 struct bcmgenet_priv *priv = netdev_priv(dev);
2853
2854
2855 bcmgenet_enable_rx_napi(priv);
2856
2857 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2858
2859 bcmgenet_enable_tx_napi(priv);
2860
2861
2862 bcmgenet_link_intr_enable(priv);
2863
2864 phy_start(dev->phydev);
2865 }
2866
2867 static int bcmgenet_open(struct net_device *dev)
2868 {
2869 struct bcmgenet_priv *priv = netdev_priv(dev);
2870 unsigned long dma_ctrl;
2871 u32 reg;
2872 int ret;
2873
2874 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2875
2876
2877 clk_prepare_enable(priv->clk);
2878
2879
2880
2881
2882 if (priv->internal_phy)
2883 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2884
2885
2886 bcmgenet_umac_reset(priv);
2887
2888 init_umac(priv);
2889
2890
2891 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2892 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2893
2894 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2895
2896 if (priv->internal_phy) {
2897 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2898 reg |= EXT_ENERGY_DET_MASK;
2899 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2900 }
2901
2902
2903 dma_ctrl = bcmgenet_dma_disable(priv);
2904
2905
2906 ret = bcmgenet_init_dma(priv);
2907 if (ret) {
2908 netdev_err(dev, "failed to initialize DMA\n");
2909 goto err_clk_disable;
2910 }
2911
2912
2913 bcmgenet_enable_dma(priv, dma_ctrl);
2914
2915
2916 bcmgenet_hfb_init(priv);
2917
2918 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2919 dev->name, priv);
2920 if (ret < 0) {
2921 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2922 goto err_fini_dma;
2923 }
2924
2925 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2926 dev->name, priv);
2927 if (ret < 0) {
2928 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2929 goto err_irq0;
2930 }
2931
2932 ret = bcmgenet_mii_probe(dev);
2933 if (ret) {
2934 netdev_err(dev, "failed to connect to PHY\n");
2935 goto err_irq1;
2936 }
2937
2938 bcmgenet_netif_start(dev);
2939
2940 netif_tx_start_all_queues(dev);
2941
2942 return 0;
2943
2944 err_irq1:
2945 free_irq(priv->irq1, priv);
2946 err_irq0:
2947 free_irq(priv->irq0, priv);
2948 err_fini_dma:
2949 bcmgenet_dma_teardown(priv);
2950 bcmgenet_fini_dma(priv);
2951 err_clk_disable:
2952 if (priv->internal_phy)
2953 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2954 clk_disable_unprepare(priv->clk);
2955 return ret;
2956 }
2957
2958 static void bcmgenet_netif_stop(struct net_device *dev)
2959 {
2960 struct bcmgenet_priv *priv = netdev_priv(dev);
2961
2962 bcmgenet_disable_tx_napi(priv);
2963 netif_tx_disable(dev);
2964
2965
2966 umac_enable_set(priv, CMD_RX_EN, false);
2967
2968 bcmgenet_dma_teardown(priv);
2969
2970
2971 umac_enable_set(priv, CMD_TX_EN, false);
2972
2973 phy_stop(dev->phydev);
2974 bcmgenet_disable_rx_napi(priv);
2975 bcmgenet_intr_disable(priv);
2976
2977
2978
2979
2980 cancel_work_sync(&priv->bcmgenet_irq_work);
2981
2982 priv->old_link = -1;
2983 priv->old_speed = -1;
2984 priv->old_duplex = -1;
2985 priv->old_pause = -1;
2986
2987
2988 bcmgenet_tx_reclaim_all(dev);
2989 bcmgenet_fini_dma(priv);
2990 }
2991
2992 static int bcmgenet_close(struct net_device *dev)
2993 {
2994 struct bcmgenet_priv *priv = netdev_priv(dev);
2995 int ret = 0;
2996
2997 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2998
2999 bcmgenet_netif_stop(dev);
3000
3001
3002 phy_disconnect(dev->phydev);
3003
3004 free_irq(priv->irq0, priv);
3005 free_irq(priv->irq1, priv);
3006
3007 if (priv->internal_phy)
3008 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3009
3010 clk_disable_unprepare(priv->clk);
3011
3012 return ret;
3013 }
3014
3015 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3016 {
3017 struct bcmgenet_priv *priv = ring->priv;
3018 u32 p_index, c_index, intsts, intmsk;
3019 struct netdev_queue *txq;
3020 unsigned int free_bds;
3021 bool txq_stopped;
3022
3023 if (!netif_msg_tx_err(priv))
3024 return;
3025
3026 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3027
3028 spin_lock(&ring->lock);
3029 if (ring->index == DESC_INDEX) {
3030 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3031 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3032 } else {
3033 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3034 intmsk = 1 << ring->index;
3035 }
3036 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3037 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3038 txq_stopped = netif_tx_queue_stopped(txq);
3039 free_bds = ring->free_bds;
3040 spin_unlock(&ring->lock);
3041
3042 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3043 "TX queue status: %s, interrupts: %s\n"
3044 "(sw)free_bds: %d (sw)size: %d\n"
3045 "(sw)p_index: %d (hw)p_index: %d\n"
3046 "(sw)c_index: %d (hw)c_index: %d\n"
3047 "(sw)clean_p: %d (sw)write_p: %d\n"
3048 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3049 ring->index, ring->queue,
3050 txq_stopped ? "stopped" : "active",
3051 intsts & intmsk ? "enabled" : "disabled",
3052 free_bds, ring->size,
3053 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3054 ring->c_index, c_index & DMA_C_INDEX_MASK,
3055 ring->clean_ptr, ring->write_ptr,
3056 ring->cb_ptr, ring->end_ptr);
3057 }
3058
3059 static void bcmgenet_timeout(struct net_device *dev)
3060 {
3061 struct bcmgenet_priv *priv = netdev_priv(dev);
3062 u32 int0_enable = 0;
3063 u32 int1_enable = 0;
3064 unsigned int q;
3065
3066 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3067
3068 for (q = 0; q < priv->hw_params->tx_queues; q++)
3069 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3070 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3071
3072 bcmgenet_tx_reclaim_all(dev);
3073
3074 for (q = 0; q < priv->hw_params->tx_queues; q++)
3075 int1_enable |= (1 << q);
3076
3077 int0_enable = UMAC_IRQ_TXDMA_DONE;
3078
3079
3080 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3081 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3082
3083 netif_trans_update(dev);
3084
3085 dev->stats.tx_errors++;
3086
3087 netif_tx_wake_all_queues(dev);
3088 }
3089
3090 #define MAX_MDF_FILTER 17
3091
3092 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3093 unsigned char *addr,
3094 int *i)
3095 {
3096 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3097 UMAC_MDF_ADDR + (*i * 4));
3098 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3099 addr[4] << 8 | addr[5],
3100 UMAC_MDF_ADDR + ((*i + 1) * 4));
3101 *i += 2;
3102 }
3103
3104 static void bcmgenet_set_rx_mode(struct net_device *dev)
3105 {
3106 struct bcmgenet_priv *priv = netdev_priv(dev);
3107 struct netdev_hw_addr *ha;
3108 int i, nfilter;
3109 u32 reg;
3110
3111 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3112
3113
3114 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3115
3116
3117
3118
3119
3120
3121
3122
3123 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3124 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3125 (nfilter > MAX_MDF_FILTER)) {
3126 reg |= CMD_PROMISC;
3127 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3128 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3129 return;
3130 } else {
3131 reg &= ~CMD_PROMISC;
3132 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3133 }
3134
3135
3136 i = 0;
3137
3138 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3139
3140 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3141
3142
3143 netdev_for_each_uc_addr(ha, dev)
3144 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3145
3146
3147 netdev_for_each_mc_addr(ha, dev)
3148 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3149
3150
3151 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3152 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3153 }
3154
3155
3156 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3157 {
3158 struct sockaddr *addr = p;
3159
3160
3161
3162
3163 if (netif_running(dev))
3164 return -EBUSY;
3165
3166 ether_addr_copy(dev->dev_addr, addr->sa_data);
3167
3168 return 0;
3169 }
3170
3171 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3172 {
3173 struct bcmgenet_priv *priv = netdev_priv(dev);
3174 unsigned long tx_bytes = 0, tx_packets = 0;
3175 unsigned long rx_bytes = 0, rx_packets = 0;
3176 unsigned long rx_errors = 0, rx_dropped = 0;
3177 struct bcmgenet_tx_ring *tx_ring;
3178 struct bcmgenet_rx_ring *rx_ring;
3179 unsigned int q;
3180
3181 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3182 tx_ring = &priv->tx_rings[q];
3183 tx_bytes += tx_ring->bytes;
3184 tx_packets += tx_ring->packets;
3185 }
3186 tx_ring = &priv->tx_rings[DESC_INDEX];
3187 tx_bytes += tx_ring->bytes;
3188 tx_packets += tx_ring->packets;
3189
3190 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3191 rx_ring = &priv->rx_rings[q];
3192
3193 rx_bytes += rx_ring->bytes;
3194 rx_packets += rx_ring->packets;
3195 rx_errors += rx_ring->errors;
3196 rx_dropped += rx_ring->dropped;
3197 }
3198 rx_ring = &priv->rx_rings[DESC_INDEX];
3199 rx_bytes += rx_ring->bytes;
3200 rx_packets += rx_ring->packets;
3201 rx_errors += rx_ring->errors;
3202 rx_dropped += rx_ring->dropped;
3203
3204 dev->stats.tx_bytes = tx_bytes;
3205 dev->stats.tx_packets = tx_packets;
3206 dev->stats.rx_bytes = rx_bytes;
3207 dev->stats.rx_packets = rx_packets;
3208 dev->stats.rx_errors = rx_errors;
3209 dev->stats.rx_missed_errors = rx_errors;
3210 dev->stats.rx_dropped = rx_dropped;
3211 return &dev->stats;
3212 }
3213
3214 static const struct net_device_ops bcmgenet_netdev_ops = {
3215 .ndo_open = bcmgenet_open,
3216 .ndo_stop = bcmgenet_close,
3217 .ndo_start_xmit = bcmgenet_xmit,
3218 .ndo_tx_timeout = bcmgenet_timeout,
3219 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3220 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3221 .ndo_do_ioctl = bcmgenet_ioctl,
3222 .ndo_set_features = bcmgenet_set_features,
3223 #ifdef CONFIG_NET_POLL_CONTROLLER
3224 .ndo_poll_controller = bcmgenet_poll_controller,
3225 #endif
3226 .ndo_get_stats = bcmgenet_get_stats,
3227 };
3228
3229
3230 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3231 [GENET_V1] = {
3232 .tx_queues = 0,
3233 .tx_bds_per_q = 0,
3234 .rx_queues = 0,
3235 .rx_bds_per_q = 0,
3236 .bp_in_en_shift = 16,
3237 .bp_in_mask = 0xffff,
3238 .hfb_filter_cnt = 16,
3239 .qtag_mask = 0x1F,
3240 .hfb_offset = 0x1000,
3241 .rdma_offset = 0x2000,
3242 .tdma_offset = 0x3000,
3243 .words_per_bd = 2,
3244 },
3245 [GENET_V2] = {
3246 .tx_queues = 4,
3247 .tx_bds_per_q = 32,
3248 .rx_queues = 0,
3249 .rx_bds_per_q = 0,
3250 .bp_in_en_shift = 16,
3251 .bp_in_mask = 0xffff,
3252 .hfb_filter_cnt = 16,
3253 .qtag_mask = 0x1F,
3254 .tbuf_offset = 0x0600,
3255 .hfb_offset = 0x1000,
3256 .hfb_reg_offset = 0x2000,
3257 .rdma_offset = 0x3000,
3258 .tdma_offset = 0x4000,
3259 .words_per_bd = 2,
3260 .flags = GENET_HAS_EXT,
3261 },
3262 [GENET_V3] = {
3263 .tx_queues = 4,
3264 .tx_bds_per_q = 32,
3265 .rx_queues = 0,
3266 .rx_bds_per_q = 0,
3267 .bp_in_en_shift = 17,
3268 .bp_in_mask = 0x1ffff,
3269 .hfb_filter_cnt = 48,
3270 .hfb_filter_size = 128,
3271 .qtag_mask = 0x3F,
3272 .tbuf_offset = 0x0600,
3273 .hfb_offset = 0x8000,
3274 .hfb_reg_offset = 0xfc00,
3275 .rdma_offset = 0x10000,
3276 .tdma_offset = 0x11000,
3277 .words_per_bd = 2,
3278 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3279 GENET_HAS_MOCA_LINK_DET,
3280 },
3281 [GENET_V4] = {
3282 .tx_queues = 4,
3283 .tx_bds_per_q = 32,
3284 .rx_queues = 0,
3285 .rx_bds_per_q = 0,
3286 .bp_in_en_shift = 17,
3287 .bp_in_mask = 0x1ffff,
3288 .hfb_filter_cnt = 48,
3289 .hfb_filter_size = 128,
3290 .qtag_mask = 0x3F,
3291 .tbuf_offset = 0x0600,
3292 .hfb_offset = 0x8000,
3293 .hfb_reg_offset = 0xfc00,
3294 .rdma_offset = 0x2000,
3295 .tdma_offset = 0x4000,
3296 .words_per_bd = 3,
3297 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3298 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3299 },
3300 [GENET_V5] = {
3301 .tx_queues = 4,
3302 .tx_bds_per_q = 32,
3303 .rx_queues = 0,
3304 .rx_bds_per_q = 0,
3305 .bp_in_en_shift = 17,
3306 .bp_in_mask = 0x1ffff,
3307 .hfb_filter_cnt = 48,
3308 .hfb_filter_size = 128,
3309 .qtag_mask = 0x3F,
3310 .tbuf_offset = 0x0600,
3311 .hfb_offset = 0x8000,
3312 .hfb_reg_offset = 0xfc00,
3313 .rdma_offset = 0x2000,
3314 .tdma_offset = 0x4000,
3315 .words_per_bd = 3,
3316 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3317 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3318 },
3319 };
3320
3321
3322 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3323 {
3324 struct bcmgenet_hw_params *params;
3325 u32 reg;
3326 u8 major;
3327 u16 gphy_rev;
3328
3329 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3330 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3331 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3332 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3333 } else if (GENET_IS_V3(priv)) {
3334 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3335 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3336 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3337 } else if (GENET_IS_V2(priv)) {
3338 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3339 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3340 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3341 } else if (GENET_IS_V1(priv)) {
3342 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3343 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3344 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3345 }
3346
3347
3348 priv->hw_params = &bcmgenet_hw_params[priv->version];
3349 params = priv->hw_params;
3350
3351
3352 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3353 major = (reg >> 24 & 0x0f);
3354 if (major == 6)
3355 major = 5;
3356 else if (major == 5)
3357 major = 4;
3358 else if (major == 0)
3359 major = 1;
3360 if (major != priv->version) {
3361 dev_err(&priv->pdev->dev,
3362 "GENET version mismatch, got: %d, configured for: %d\n",
3363 major, priv->version);
3364 }
3365
3366
3367 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3368 major, (reg >> 16) & 0x0f, reg & 0xffff);
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382 gphy_rev = reg & 0xffff;
3383
3384 if (GENET_IS_V5(priv)) {
3385
3386
3387
3388 if (gphy_rev != 0) {
3389 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3390 gphy_rev);
3391 }
3392
3393 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3394 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3395 return;
3396
3397 } else if ((gphy_rev & 0xf0) != 0) {
3398 priv->gphy_rev = gphy_rev << 8;
3399
3400 } else if ((gphy_rev & 0xff00) != 0) {
3401 priv->gphy_rev = gphy_rev;
3402 }
3403
3404 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3405 if (!(params->flags & GENET_HAS_40BITS))
3406 pr_warn("GENET does not support 40-bits PA\n");
3407 #endif
3408
3409 pr_debug("Configuration for version: %d\n"
3410 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3411 "BP << en: %2d, BP msk: 0x%05x\n"
3412 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3413 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3414 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3415 "Words/BD: %d\n",
3416 priv->version,
3417 params->tx_queues, params->tx_bds_per_q,
3418 params->rx_queues, params->rx_bds_per_q,
3419 params->bp_in_en_shift, params->bp_in_mask,
3420 params->hfb_filter_cnt, params->qtag_mask,
3421 params->tbuf_offset, params->hfb_offset,
3422 params->hfb_reg_offset,
3423 params->rdma_offset, params->tdma_offset,
3424 params->words_per_bd);
3425 }
3426
3427 static const struct of_device_id bcmgenet_match[] = {
3428 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3429 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3430 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3431 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3432 { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 },
3433 { },
3434 };
3435 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3436
3437 static int bcmgenet_probe(struct platform_device *pdev)
3438 {
3439 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3440 struct device_node *dn = pdev->dev.of_node;
3441 const struct of_device_id *of_id = NULL;
3442 struct bcmgenet_priv *priv;
3443 struct net_device *dev;
3444 const void *macaddr;
3445 unsigned int i;
3446 int err = -EIO;
3447 const char *phy_mode_str;
3448
3449
3450 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3451 GENET_MAX_MQ_CNT + 1);
3452 if (!dev) {
3453 dev_err(&pdev->dev, "can't allocate net device\n");
3454 return -ENOMEM;
3455 }
3456
3457 if (dn) {
3458 of_id = of_match_node(bcmgenet_match, dn);
3459 if (!of_id)
3460 return -EINVAL;
3461 }
3462
3463 priv = netdev_priv(dev);
3464 priv->irq0 = platform_get_irq(pdev, 0);
3465 priv->irq1 = platform_get_irq(pdev, 1);
3466 priv->wol_irq = platform_get_irq(pdev, 2);
3467 if (!priv->irq0 || !priv->irq1) {
3468 dev_err(&pdev->dev, "can't find IRQs\n");
3469 err = -EINVAL;
3470 goto err;
3471 }
3472
3473 if (dn) {
3474 macaddr = of_get_mac_address(dn);
3475 if (IS_ERR(macaddr)) {
3476 dev_err(&pdev->dev, "can't find MAC address\n");
3477 err = -EINVAL;
3478 goto err;
3479 }
3480 } else {
3481 macaddr = pd->mac_address;
3482 }
3483
3484 priv->base = devm_platform_ioremap_resource(pdev, 0);
3485 if (IS_ERR(priv->base)) {
3486 err = PTR_ERR(priv->base);
3487 goto err;
3488 }
3489
3490 spin_lock_init(&priv->lock);
3491
3492 SET_NETDEV_DEV(dev, &pdev->dev);
3493 dev_set_drvdata(&pdev->dev, dev);
3494 ether_addr_copy(dev->dev_addr, macaddr);
3495 dev->watchdog_timeo = 2 * HZ;
3496 dev->ethtool_ops = &bcmgenet_ethtool_ops;
3497 dev->netdev_ops = &bcmgenet_netdev_ops;
3498
3499 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3500
3501
3502 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3503 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3504
3505
3506 priv->wol_irq_disabled = true;
3507 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3508 dev->name, priv);
3509 if (!err)
3510 device_set_wakeup_capable(&pdev->dev, 1);
3511
3512
3513
3514
3515 dev->needed_headroom += 64;
3516
3517 netdev_boot_setup_check(dev);
3518
3519 priv->dev = dev;
3520 priv->pdev = pdev;
3521 if (of_id)
3522 priv->version = (enum bcmgenet_version)of_id->data;
3523 else
3524 priv->version = pd->genet_version;
3525
3526 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3527 if (IS_ERR(priv->clk)) {
3528 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3529 priv->clk = NULL;
3530 }
3531
3532 clk_prepare_enable(priv->clk);
3533
3534 bcmgenet_set_hw_params(priv);
3535
3536
3537 init_waitqueue_head(&priv->wq);
3538
3539 priv->rx_buf_len = RX_BUF_LENGTH;
3540 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3541
3542 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3543 if (IS_ERR(priv->clk_wol)) {
3544 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3545 priv->clk_wol = NULL;
3546 }
3547
3548 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3549 if (IS_ERR(priv->clk_eee)) {
3550 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3551 priv->clk_eee = NULL;
3552 }
3553
3554
3555
3556
3557 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3558 !strcasecmp(phy_mode_str, "internal"))
3559 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3560
3561 reset_umac(priv);
3562
3563 err = bcmgenet_mii_init(dev);
3564 if (err)
3565 goto err_clk_disable;
3566
3567
3568
3569
3570 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3571 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3572
3573
3574 for (i = 0; i < priv->hw_params->rx_queues; i++)
3575 priv->rx_rings[i].rx_max_coalesced_frames = 1;
3576 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
3577
3578
3579 netif_carrier_off(dev);
3580
3581
3582 clk_disable_unprepare(priv->clk);
3583
3584 err = register_netdev(dev);
3585 if (err)
3586 goto err;
3587
3588 return err;
3589
3590 err_clk_disable:
3591 clk_disable_unprepare(priv->clk);
3592 err:
3593 free_netdev(dev);
3594 return err;
3595 }
3596
3597 static int bcmgenet_remove(struct platform_device *pdev)
3598 {
3599 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3600
3601 dev_set_drvdata(&pdev->dev, NULL);
3602 unregister_netdev(priv->dev);
3603 bcmgenet_mii_exit(priv->dev);
3604 free_netdev(priv->dev);
3605
3606 return 0;
3607 }
3608
3609 #ifdef CONFIG_PM_SLEEP
3610 static int bcmgenet_resume(struct device *d)
3611 {
3612 struct net_device *dev = dev_get_drvdata(d);
3613 struct bcmgenet_priv *priv = netdev_priv(dev);
3614 unsigned long dma_ctrl;
3615 int ret;
3616 u32 reg;
3617
3618 if (!netif_running(dev))
3619 return 0;
3620
3621
3622 ret = clk_prepare_enable(priv->clk);
3623 if (ret)
3624 return ret;
3625
3626
3627
3628
3629 if (priv->internal_phy)
3630 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3631
3632 bcmgenet_umac_reset(priv);
3633
3634 init_umac(priv);
3635
3636
3637 if (priv->wolopts)
3638 clk_disable_unprepare(priv->clk_wol);
3639
3640 phy_init_hw(dev->phydev);
3641
3642
3643 genphy_config_aneg(dev->phydev);
3644 bcmgenet_mii_config(priv->dev, false);
3645
3646 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3647
3648 if (priv->internal_phy) {
3649 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3650 reg |= EXT_ENERGY_DET_MASK;
3651 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3652 }
3653
3654 if (priv->wolopts)
3655 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3656
3657
3658 dma_ctrl = bcmgenet_dma_disable(priv);
3659
3660
3661 ret = bcmgenet_init_dma(priv);
3662 if (ret) {
3663 netdev_err(dev, "failed to initialize DMA\n");
3664 goto out_clk_disable;
3665 }
3666
3667
3668 bcmgenet_enable_dma(priv, dma_ctrl);
3669
3670 if (!device_may_wakeup(d))
3671 phy_resume(dev->phydev);
3672
3673 if (priv->eee.eee_enabled)
3674 bcmgenet_eee_enable_set(dev, true);
3675
3676 bcmgenet_netif_start(dev);
3677
3678 netif_device_attach(dev);
3679
3680 return 0;
3681
3682 out_clk_disable:
3683 if (priv->internal_phy)
3684 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3685 clk_disable_unprepare(priv->clk);
3686 return ret;
3687 }
3688
3689 static int bcmgenet_suspend(struct device *d)
3690 {
3691 struct net_device *dev = dev_get_drvdata(d);
3692 struct bcmgenet_priv *priv = netdev_priv(dev);
3693 int ret = 0;
3694
3695 if (!netif_running(dev))
3696 return 0;
3697
3698 netif_device_detach(dev);
3699
3700 bcmgenet_netif_stop(dev);
3701
3702 if (!device_may_wakeup(d))
3703 phy_suspend(dev->phydev);
3704
3705
3706 if (device_may_wakeup(d) && priv->wolopts) {
3707 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3708 clk_prepare_enable(priv->clk_wol);
3709 } else if (priv->internal_phy) {
3710 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3711 }
3712
3713
3714 clk_disable_unprepare(priv->clk);
3715
3716 if (ret)
3717 bcmgenet_resume(d);
3718
3719 return ret;
3720 }
3721 #endif
3722
3723 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3724
3725 static struct platform_driver bcmgenet_driver = {
3726 .probe = bcmgenet_probe,
3727 .remove = bcmgenet_remove,
3728 .driver = {
3729 .name = "bcmgenet",
3730 .of_match_table = bcmgenet_match,
3731 .pm = &bcmgenet_pm_ops,
3732 },
3733 };
3734 module_platform_driver(bcmgenet_driver);
3735
3736 MODULE_AUTHOR("Broadcom Corporation");
3737 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3738 MODULE_ALIAS("platform:bcmgenet");
3739 MODULE_LICENSE("GPL");