root/drivers/net/ethernet/atheros/alx/reg.h

INCLUDED FROM

   1 /*
   2  * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
   3  *
   4  *  This file is free software: you may copy, redistribute and/or modify it
   5  *  under the terms of the GNU General Public License as published by the
   6  *  Free Software Foundation, either version 2 of the License, or (at your
   7  *  option) any later version.
   8  *
   9  *  This file is distributed in the hope that it will be useful, but
  10  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  *  General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  *
  17  * This file incorporates work covered by the following copyright and
  18  * permission notice:
  19  *
  20  * Copyright (c) 2012 Qualcomm Atheros, Inc.
  21  *
  22  * Permission to use, copy, modify, and/or distribute this software for any
  23  * purpose with or without fee is hereby granted, provided that the above
  24  * copyright notice and this permission notice appear in all copies.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  27  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  28  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  29  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  30  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  31  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  32  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  33  */
  34 
  35 #ifndef ALX_REG_H
  36 #define ALX_REG_H
  37 
  38 #define ALX_DEV_ID_AR8161                               0x1091
  39 #define ALX_DEV_ID_E2200                                0xe091
  40 #define ALX_DEV_ID_E2400                                0xe0a1
  41 #define ALX_DEV_ID_E2500                                0xe0b1
  42 #define ALX_DEV_ID_AR8162                               0x1090
  43 #define ALX_DEV_ID_AR8171                               0x10A1
  44 #define ALX_DEV_ID_AR8172                               0x10A0
  45 
  46 /* rev definition,
  47  * bit(0): with xD support
  48  * bit(1): with Card Reader function
  49  * bit(7:2): real revision
  50  */
  51 #define ALX_PCI_REVID_SHIFT                             3
  52 #define ALX_REV_A0                                      0
  53 #define ALX_REV_A1                                      1
  54 #define ALX_REV_B0                                      2
  55 #define ALX_REV_C0                                      3
  56 
  57 #define ALX_DEV_CTRL                                    0x0060
  58 #define ALX_DEV_CTRL_MAXRRS_MIN                         2
  59 
  60 #define ALX_MSIX_MASK                                   0x0090
  61 
  62 #define ALX_UE_SVRT                                     0x010C
  63 #define ALX_UE_SVRT_FCPROTERR                           BIT(13)
  64 #define ALX_UE_SVRT_DLPROTERR                           BIT(4)
  65 
  66 /* eeprom & flash load register */
  67 #define ALX_EFLD                                        0x0204
  68 #define ALX_EFLD_F_EXIST                                BIT(10)
  69 #define ALX_EFLD_E_EXIST                                BIT(9)
  70 #define ALX_EFLD_STAT                                   BIT(5)
  71 #define ALX_EFLD_START                                  BIT(0)
  72 
  73 /* eFuse load register */
  74 #define ALX_SLD                                         0x0218
  75 #define ALX_SLD_STAT                                    BIT(12)
  76 #define ALX_SLD_START                                   BIT(11)
  77 #define ALX_SLD_MAX_TO                                  100
  78 
  79 #define ALX_PDLL_TRNS1                                  0x1104
  80 #define ALX_PDLL_TRNS1_D3PLLOFF_EN                      BIT(11)
  81 
  82 #define ALX_PMCTRL                                      0x12F8
  83 #define ALX_PMCTRL_HOTRST_WTEN                          BIT(31)
  84 /* bit30: L0s/L1 controlled by MAC based on throughput(setting in 15A0) */
  85 #define ALX_PMCTRL_ASPM_FCEN                            BIT(30)
  86 #define ALX_PMCTRL_SADLY_EN                             BIT(29)
  87 #define ALX_PMCTRL_LCKDET_TIMER_MASK                    0xF
  88 #define ALX_PMCTRL_LCKDET_TIMER_SHIFT                   24
  89 #define ALX_PMCTRL_LCKDET_TIMER_DEF                     0xC
  90 /* bit[23:20] if pm_request_l1 time > @, then enter L0s not L1 */
  91 #define ALX_PMCTRL_L1REQ_TO_MASK                        0xF
  92 #define ALX_PMCTRL_L1REQ_TO_SHIFT                       20
  93 #define ALX_PMCTRL_L1REG_TO_DEF                         0xF
  94 #define ALX_PMCTRL_TXL1_AFTER_L0S                       BIT(19)
  95 #define ALX_PMCTRL_L1_TIMER_MASK                        0x7
  96 #define ALX_PMCTRL_L1_TIMER_SHIFT                       16
  97 #define ALX_PMCTRL_L1_TIMER_16US                        4
  98 #define ALX_PMCTRL_RCVR_WT_1US                          BIT(15)
  99 /* bit13: enable pcie clk switch in L1 state */
 100 #define ALX_PMCTRL_L1_CLKSW_EN                          BIT(13)
 101 #define ALX_PMCTRL_L0S_EN                               BIT(12)
 102 #define ALX_PMCTRL_RXL1_AFTER_L0S                       BIT(11)
 103 #define ALX_PMCTRL_L1_BUFSRX_EN                         BIT(7)
 104 /* bit6: power down serdes RX */
 105 #define ALX_PMCTRL_L1_SRDSRX_PWD                        BIT(6)
 106 #define ALX_PMCTRL_L1_SRDSPLL_EN                        BIT(5)
 107 #define ALX_PMCTRL_L1_SRDS_EN                           BIT(4)
 108 #define ALX_PMCTRL_L1_EN                                BIT(3)
 109 
 110 /*******************************************************/
 111 /* following registers are mapped only to memory space */
 112 /*******************************************************/
 113 
 114 #define ALX_MASTER                                      0x1400
 115 /* bit12: 1:alwys select pclk from serdes, not sw to 25M */
 116 #define ALX_MASTER_PCLKSEL_SRDS                         BIT(12)
 117 /* bit11: irq moduration for rx */
 118 #define ALX_MASTER_IRQMOD2_EN                           BIT(11)
 119 /* bit10: irq moduration for tx/rx */
 120 #define ALX_MASTER_IRQMOD1_EN                           BIT(10)
 121 #define ALX_MASTER_SYSALVTIMER_EN                       BIT(7)
 122 #define ALX_MASTER_OOB_DIS                              BIT(6)
 123 /* bit5: wakeup without pcie clk */
 124 #define ALX_MASTER_WAKEN_25M                            BIT(5)
 125 /* bit0: MAC & DMA reset */
 126 #define ALX_MASTER_DMA_MAC_RST                          BIT(0)
 127 #define ALX_DMA_MAC_RST_TO                              50
 128 
 129 #define ALX_IRQ_MODU_TIMER                              0x1408
 130 #define ALX_IRQ_MODU_TIMER1_MASK                        0xFFFF
 131 #define ALX_IRQ_MODU_TIMER1_SHIFT                       0
 132 
 133 #define ALX_PHY_CTRL                                    0x140C
 134 #define ALX_PHY_CTRL_100AB_EN                           BIT(17)
 135 /* bit14: affect MAC & PHY, go to low power sts */
 136 #define ALX_PHY_CTRL_POWER_DOWN                         BIT(14)
 137 /* bit13: 1:pll always ON, 0:can switch in lpw */
 138 #define ALX_PHY_CTRL_PLL_ON                             BIT(13)
 139 #define ALX_PHY_CTRL_RST_ANALOG                         BIT(12)
 140 #define ALX_PHY_CTRL_HIB_PULSE                          BIT(11)
 141 #define ALX_PHY_CTRL_HIB_EN                             BIT(10)
 142 #define ALX_PHY_CTRL_IDDQ                               BIT(7)
 143 #define ALX_PHY_CTRL_GATE_25M                           BIT(5)
 144 #define ALX_PHY_CTRL_LED_MODE                           BIT(2)
 145 /* bit0: out of dsp RST state */
 146 #define ALX_PHY_CTRL_DSPRST_OUT                         BIT(0)
 147 #define ALX_PHY_CTRL_DSPRST_TO                          80
 148 #define ALX_PHY_CTRL_CLS        (ALX_PHY_CTRL_LED_MODE | \
 149                                  ALX_PHY_CTRL_100AB_EN | \
 150                                  ALX_PHY_CTRL_PLL_ON)
 151 
 152 #define ALX_MAC_STS                                     0x1410
 153 #define ALX_MAC_STS_TXQ_BUSY                            BIT(3)
 154 #define ALX_MAC_STS_RXQ_BUSY                            BIT(2)
 155 #define ALX_MAC_STS_TXMAC_BUSY                          BIT(1)
 156 #define ALX_MAC_STS_RXMAC_BUSY                          BIT(0)
 157 #define ALX_MAC_STS_IDLE        (ALX_MAC_STS_TXQ_BUSY | \
 158                                  ALX_MAC_STS_RXQ_BUSY | \
 159                                  ALX_MAC_STS_TXMAC_BUSY | \
 160                                  ALX_MAC_STS_RXMAC_BUSY)
 161 
 162 #define ALX_MDIO                                        0x1414
 163 #define ALX_MDIO_MODE_EXT                               BIT(30)
 164 #define ALX_MDIO_BUSY                                   BIT(27)
 165 #define ALX_MDIO_CLK_SEL_MASK                           0x7
 166 #define ALX_MDIO_CLK_SEL_SHIFT                          24
 167 #define ALX_MDIO_CLK_SEL_25MD4                          0
 168 #define ALX_MDIO_CLK_SEL_25MD128                        7
 169 #define ALX_MDIO_START                                  BIT(23)
 170 #define ALX_MDIO_SPRES_PRMBL                            BIT(22)
 171 /* bit21: 1:read,0:write */
 172 #define ALX_MDIO_OP_READ                                BIT(21)
 173 #define ALX_MDIO_REG_MASK                               0x1F
 174 #define ALX_MDIO_REG_SHIFT                              16
 175 #define ALX_MDIO_DATA_MASK                              0xFFFF
 176 #define ALX_MDIO_DATA_SHIFT                             0
 177 #define ALX_MDIO_MAX_AC_TO                              120
 178 
 179 #define ALX_MDIO_EXTN                                   0x1448
 180 #define ALX_MDIO_EXTN_DEVAD_MASK                        0x1F
 181 #define ALX_MDIO_EXTN_DEVAD_SHIFT                       16
 182 #define ALX_MDIO_EXTN_REG_MASK                          0xFFFF
 183 #define ALX_MDIO_EXTN_REG_SHIFT                         0
 184 
 185 #define ALX_SERDES                                      0x1424
 186 #define ALX_SERDES_PHYCLK_SLWDWN                        BIT(18)
 187 #define ALX_SERDES_MACCLK_SLWDWN                        BIT(17)
 188 
 189 #define ALX_LPI_CTRL                                    0x1440
 190 #define ALX_LPI_CTRL_EN                                 BIT(0)
 191 
 192 /* for B0+, bit[13..] for C0+ */
 193 #define ALX_HRTBT_EXT_CTRL                              0x1AD0
 194 #define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_MASK             0x3F
 195 #define L1F_HRTBT_EXT_CTRL_PERIOD_HIGH_SHIFT            24
 196 #define L1F_HRTBT_EXT_CTRL_SWOI_STARTUP_PKT_EN          BIT(23)
 197 #define L1F_HRTBT_EXT_CTRL_IOAC_2_FRAGMENTED            BIT(22)
 198 #define L1F_HRTBT_EXT_CTRL_IOAC_1_FRAGMENTED            BIT(21)
 199 #define L1F_HRTBT_EXT_CTRL_IOAC_1_KEEPALIVE_EN          BIT(20)
 200 #define L1F_HRTBT_EXT_CTRL_IOAC_1_HAS_VLAN              BIT(19)
 201 #define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_8023               BIT(18)
 202 #define L1F_HRTBT_EXT_CTRL_IOAC_1_IS_IPV6               BIT(17)
 203 #define L1F_HRTBT_EXT_CTRL_IOAC_2_KEEPALIVE_EN          BIT(16)
 204 #define L1F_HRTBT_EXT_CTRL_IOAC_2_HAS_VLAN              BIT(15)
 205 #define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_8023               BIT(14)
 206 #define L1F_HRTBT_EXT_CTRL_IOAC_2_IS_IPV6               BIT(13)
 207 #define ALX_HRTBT_EXT_CTRL_NS_EN                        BIT(12)
 208 #define ALX_HRTBT_EXT_CTRL_FRAG_LEN_MASK                0xFF
 209 #define ALX_HRTBT_EXT_CTRL_FRAG_LEN_SHIFT               4
 210 #define ALX_HRTBT_EXT_CTRL_IS_8023                      BIT(3)
 211 #define ALX_HRTBT_EXT_CTRL_IS_IPV6                      BIT(2)
 212 #define ALX_HRTBT_EXT_CTRL_WAKEUP_EN                    BIT(1)
 213 #define ALX_HRTBT_EXT_CTRL_ARP_EN                       BIT(0)
 214 
 215 #define ALX_HRTBT_REM_IPV4_ADDR                         0x1AD4
 216 #define ALX_HRTBT_HOST_IPV4_ADDR                        0x1478
 217 #define ALX_HRTBT_REM_IPV6_ADDR3                        0x1AD8
 218 #define ALX_HRTBT_REM_IPV6_ADDR2                        0x1ADC
 219 #define ALX_HRTBT_REM_IPV6_ADDR1                        0x1AE0
 220 #define ALX_HRTBT_REM_IPV6_ADDR0                        0x1AE4
 221 
 222 /* 1B8C ~ 1B94 for C0+ */
 223 #define ALX_SWOI_ACER_CTRL                              0x1B8C
 224 #define ALX_SWOI_ORIG_ACK_NAK_EN                        BIT(20)
 225 #define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_MASK              0XFF
 226 #define ALX_SWOI_ORIG_ACK_NAK_PKT_LEN_SHIFT             12
 227 #define ALX_SWOI_ORIG_ACK_ADDR_MASK                     0XFFF
 228 #define ALX_SWOI_ORIG_ACK_ADDR_SHIFT                    0
 229 
 230 #define ALX_SWOI_IOAC_CTRL_2                            0x1B90
 231 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_MASK       0xFF
 232 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_FRAG_LEN_SHIFT      24
 233 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_MASK        0xFFF
 234 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_PKT_LEN_SHIFT       12
 235 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_MASK       0xFFF
 236 #define ALX_SWOI_IOAC_CTRL_2_SWOI_1_HDR_ADDR_SHIFT      0
 237 
 238 #define ALX_SWOI_IOAC_CTRL_3                            0x1B94
 239 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_MASK       0xFF
 240 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_FRAG_LEN_SHIFT      24
 241 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_MASK        0xFFF
 242 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_PKT_LEN_SHIFT       12
 243 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_MASK       0xFFF
 244 #define ALX_SWOI_IOAC_CTRL_3_SWOI_2_HDR_ADDR_SHIFT      0
 245 
 246 /* for B0 */
 247 #define ALX_IDLE_DECISN_TIMER                           0x1474
 248 /* 1ms */
 249 #define ALX_IDLE_DECISN_TIMER_DEF                       0x400
 250 
 251 #define ALX_MAC_CTRL                                    0x1480
 252 #define ALX_MAC_CTRL_FAST_PAUSE                         BIT(31)
 253 #define ALX_MAC_CTRL_WOLSPED_SWEN                       BIT(30)
 254 /* bit29: 1:legacy(hi5b), 0:marvl(lo5b)*/
 255 #define ALX_MAC_CTRL_MHASH_ALG_HI5B                     BIT(29)
 256 #define ALX_MAC_CTRL_BRD_EN                             BIT(26)
 257 #define ALX_MAC_CTRL_MULTIALL_EN                        BIT(25)
 258 #define ALX_MAC_CTRL_SPEED_MASK                         0x3
 259 #define ALX_MAC_CTRL_SPEED_SHIFT                        20
 260 #define ALX_MAC_CTRL_SPEED_10_100                       1
 261 #define ALX_MAC_CTRL_SPEED_1000                         2
 262 #define ALX_MAC_CTRL_PROMISC_EN                         BIT(15)
 263 #define ALX_MAC_CTRL_VLANSTRIP                          BIT(14)
 264 #define ALX_MAC_CTRL_PRMBLEN_MASK                       0xF
 265 #define ALX_MAC_CTRL_PRMBLEN_SHIFT                      10
 266 #define ALX_MAC_CTRL_PCRCE                              BIT(7)
 267 #define ALX_MAC_CTRL_CRCE                               BIT(6)
 268 #define ALX_MAC_CTRL_FULLD                              BIT(5)
 269 #define ALX_MAC_CTRL_RXFC_EN                            BIT(3)
 270 #define ALX_MAC_CTRL_TXFC_EN                            BIT(2)
 271 #define ALX_MAC_CTRL_RX_EN                              BIT(1)
 272 #define ALX_MAC_CTRL_TX_EN                              BIT(0)
 273 
 274 #define ALX_STAD0                                       0x1488
 275 #define ALX_STAD1                                       0x148C
 276 
 277 #define ALX_HASH_TBL0                                   0x1490
 278 #define ALX_HASH_TBL1                                   0x1494
 279 
 280 #define ALX_MTU                                         0x149C
 281 #define ALX_MTU_JUMBO_TH                                1514
 282 #define ALX_MTU_STD_ALGN                                1536
 283 
 284 #define ALX_SRAM5                                       0x1524
 285 #define ALX_SRAM_RXF_LEN_MASK                           0xFFF
 286 #define ALX_SRAM_RXF_LEN_SHIFT                          0
 287 #define ALX_SRAM_RXF_LEN_8K                             (8*1024)
 288 
 289 #define ALX_SRAM9                                       0x1534
 290 #define ALX_SRAM_LOAD_PTR                               BIT(0)
 291 
 292 #define ALX_RX_BASE_ADDR_HI                             0x1540
 293 
 294 #define ALX_TX_BASE_ADDR_HI                             0x1544
 295 
 296 #define ALX_RFD_ADDR_LO                                 0x1550
 297 #define ALX_RFD_RING_SZ                                 0x1560
 298 #define ALX_RFD_BUF_SZ                                  0x1564
 299 
 300 #define ALX_RRD_ADDR_LO                                 0x1568
 301 #define ALX_RRD_RING_SZ                                 0x1578
 302 
 303 /* pri3: highest, pri0: lowest */
 304 #define ALX_TPD_PRI3_ADDR_LO                            0x14E4
 305 #define ALX_TPD_PRI2_ADDR_LO                            0x14E0
 306 #define ALX_TPD_PRI1_ADDR_LO                            0x157C
 307 #define ALX_TPD_PRI0_ADDR_LO                            0x1580
 308 
 309 /* producer index is 16bit */
 310 #define ALX_TPD_PRI3_PIDX                               0x1618
 311 #define ALX_TPD_PRI2_PIDX                               0x161A
 312 #define ALX_TPD_PRI1_PIDX                               0x15F0
 313 #define ALX_TPD_PRI0_PIDX                               0x15F2
 314 
 315 /* consumer index is 16bit */
 316 #define ALX_TPD_PRI3_CIDX                               0x161C
 317 #define ALX_TPD_PRI2_CIDX                               0x161E
 318 #define ALX_TPD_PRI1_CIDX                               0x15F4
 319 #define ALX_TPD_PRI0_CIDX                               0x15F6
 320 
 321 #define ALX_TPD_RING_SZ                                 0x1584
 322 
 323 #define ALX_TXQ0                                        0x1590
 324 #define ALX_TXQ0_TXF_BURST_PREF_MASK                    0xFFFF
 325 #define ALX_TXQ0_TXF_BURST_PREF_SHIFT                   16
 326 #define ALX_TXQ_TXF_BURST_PREF_DEF                      0x200
 327 #define ALX_TXQ0_LSO_8023_EN                            BIT(7)
 328 #define ALX_TXQ0_MODE_ENHANCE                           BIT(6)
 329 #define ALX_TXQ0_EN                                     BIT(5)
 330 #define ALX_TXQ0_SUPT_IPOPT                             BIT(4)
 331 #define ALX_TXQ0_TPD_BURSTPREF_MASK                     0xF
 332 #define ALX_TXQ0_TPD_BURSTPREF_SHIFT                    0
 333 #define ALX_TXQ_TPD_BURSTPREF_DEF                       5
 334 
 335 #define ALX_TXQ1                                        0x1594
 336 /* bit11:  drop large packet, len > (rfd buf) */
 337 #define ALX_TXQ1_ERRLGPKT_DROP_EN                       BIT(11)
 338 #define ALX_TXQ1_JUMBO_TSO_TH                           (7*1024)
 339 
 340 #define ALX_RXQ0                                        0x15A0
 341 #define ALX_RXQ0_EN                                     BIT(31)
 342 #define ALX_RXQ0_RSS_HASH_EN                            BIT(29)
 343 #define ALX_RXQ0_RSS_MODE_MASK                          0x3
 344 #define ALX_RXQ0_RSS_MODE_SHIFT                         26
 345 #define ALX_RXQ0_RSS_MODE_DIS                           0
 346 #define ALX_RXQ0_RSS_MODE_MQMI                          3
 347 #define ALX_RXQ0_NUM_RFD_PREF_MASK                      0x3F
 348 #define ALX_RXQ0_NUM_RFD_PREF_SHIFT                     20
 349 #define ALX_RXQ0_NUM_RFD_PREF_DEF                       8
 350 #define ALX_RXQ0_IDT_TBL_SIZE_MASK                      0x1FF
 351 #define ALX_RXQ0_IDT_TBL_SIZE_SHIFT                     8
 352 #define ALX_RXQ0_IDT_TBL_SIZE_DEF                       0x100
 353 #define ALX_RXQ0_IDT_TBL_SIZE_NORMAL                    128
 354 #define ALX_RXQ0_IPV6_PARSE_EN                          BIT(7)
 355 #define ALX_RXQ0_RSS_HSTYP_MASK                         0xF
 356 #define ALX_RXQ0_RSS_HSTYP_SHIFT                        2
 357 #define ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN                  BIT(5)
 358 #define ALX_RXQ0_RSS_HSTYP_IPV6_EN                      BIT(4)
 359 #define ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN                  BIT(3)
 360 #define ALX_RXQ0_RSS_HSTYP_IPV4_EN                      BIT(2)
 361 #define ALX_RXQ0_RSS_HSTYP_ALL          (ALX_RXQ0_RSS_HSTYP_IPV6_TCP_EN | \
 362                                          ALX_RXQ0_RSS_HSTYP_IPV4_TCP_EN | \
 363                                          ALX_RXQ0_RSS_HSTYP_IPV6_EN | \
 364                                          ALX_RXQ0_RSS_HSTYP_IPV4_EN)
 365 #define ALX_RXQ0_ASPM_THRESH_MASK                       0x3
 366 #define ALX_RXQ0_ASPM_THRESH_SHIFT                      0
 367 #define ALX_RXQ0_ASPM_THRESH_100M                       3
 368 
 369 #define ALX_RXQ2                                        0x15A8
 370 #define ALX_RXQ2_RXF_XOFF_THRESH_MASK                   0xFFF
 371 #define ALX_RXQ2_RXF_XOFF_THRESH_SHIFT                  16
 372 #define ALX_RXQ2_RXF_XON_THRESH_MASK                    0xFFF
 373 #define ALX_RXQ2_RXF_XON_THRESH_SHIFT                   0
 374 /* Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) +
 375  *        rx-packet(1522) + delay-of-link(64)
 376  *      = 3212.
 377  */
 378 #define ALX_RXQ2_RXF_FLOW_CTRL_RSVD                     3212
 379 
 380 #define ALX_DMA                                         0x15C0
 381 #define ALX_DMA_RCHNL_SEL_MASK                          0x3
 382 #define ALX_DMA_RCHNL_SEL_SHIFT                         26
 383 #define ALX_DMA_WDLY_CNT_MASK                           0xF
 384 #define ALX_DMA_WDLY_CNT_SHIFT                          16
 385 #define ALX_DMA_WDLY_CNT_DEF                            4
 386 #define ALX_DMA_RDLY_CNT_MASK                           0x1F
 387 #define ALX_DMA_RDLY_CNT_SHIFT                          11
 388 #define ALX_DMA_RDLY_CNT_DEF                            15
 389 /* bit10: 0:tpd with pri, 1: data */
 390 #define ALX_DMA_RREQ_PRI_DATA                           BIT(10)
 391 #define ALX_DMA_RREQ_BLEN_MASK                          0x7
 392 #define ALX_DMA_RREQ_BLEN_SHIFT                         4
 393 #define ALX_DMA_RORDER_MODE_MASK                        0x7
 394 #define ALX_DMA_RORDER_MODE_SHIFT                       0
 395 #define ALX_DMA_RORDER_MODE_OUT                         4
 396 
 397 #define ALX_WOL0                                        0x14A0
 398 #define ALX_WOL0_PME_LINK                               BIT(5)
 399 #define ALX_WOL0_LINK_EN                                BIT(4)
 400 #define ALX_WOL0_PME_MAGIC_EN                           BIT(3)
 401 #define ALX_WOL0_MAGIC_EN                               BIT(2)
 402 
 403 #define ALX_RFD_PIDX                                    0x15E0
 404 
 405 #define ALX_RFD_CIDX                                    0x15F8
 406 
 407 /* MIB */
 408 #define ALX_MIB_BASE                                    0x1700
 409 
 410 #define ALX_MIB_RX_OK                                   (ALX_MIB_BASE + 0)
 411 #define ALX_MIB_RX_BCAST                                (ALX_MIB_BASE + 4)
 412 #define ALX_MIB_RX_MCAST                                (ALX_MIB_BASE + 8)
 413 #define ALX_MIB_RX_PAUSE                                (ALX_MIB_BASE + 12)
 414 #define ALX_MIB_RX_CTRL                                 (ALX_MIB_BASE + 16)
 415 #define ALX_MIB_RX_FCS_ERR                              (ALX_MIB_BASE + 20)
 416 #define ALX_MIB_RX_LEN_ERR                              (ALX_MIB_BASE + 24)
 417 #define ALX_MIB_RX_BYTE_CNT                             (ALX_MIB_BASE + 28)
 418 #define ALX_MIB_RX_RUNT                                 (ALX_MIB_BASE + 32)
 419 #define ALX_MIB_RX_FRAG                                 (ALX_MIB_BASE + 36)
 420 #define ALX_MIB_RX_SZ_64B                               (ALX_MIB_BASE + 40)
 421 #define ALX_MIB_RX_SZ_127B                              (ALX_MIB_BASE + 44)
 422 #define ALX_MIB_RX_SZ_255B                              (ALX_MIB_BASE + 48)
 423 #define ALX_MIB_RX_SZ_511B                              (ALX_MIB_BASE + 52)
 424 #define ALX_MIB_RX_SZ_1023B                             (ALX_MIB_BASE + 56)
 425 #define ALX_MIB_RX_SZ_1518B                             (ALX_MIB_BASE + 60)
 426 #define ALX_MIB_RX_SZ_MAX                               (ALX_MIB_BASE + 64)
 427 #define ALX_MIB_RX_OV_SZ                                (ALX_MIB_BASE + 68)
 428 #define ALX_MIB_RX_OV_RXF                               (ALX_MIB_BASE + 72)
 429 #define ALX_MIB_RX_OV_RRD                               (ALX_MIB_BASE + 76)
 430 #define ALX_MIB_RX_ALIGN_ERR                            (ALX_MIB_BASE + 80)
 431 #define ALX_MIB_RX_BCCNT                                (ALX_MIB_BASE + 84)
 432 #define ALX_MIB_RX_MCCNT                                (ALX_MIB_BASE + 88)
 433 #define ALX_MIB_RX_ERRADDR                              (ALX_MIB_BASE + 92)
 434 
 435 #define ALX_MIB_TX_OK                                   (ALX_MIB_BASE + 96)
 436 #define ALX_MIB_TX_BCAST                                (ALX_MIB_BASE + 100)
 437 #define ALX_MIB_TX_MCAST                                (ALX_MIB_BASE + 104)
 438 #define ALX_MIB_TX_PAUSE                                (ALX_MIB_BASE + 108)
 439 #define ALX_MIB_TX_EXC_DEFER                            (ALX_MIB_BASE + 112)
 440 #define ALX_MIB_TX_CTRL                                 (ALX_MIB_BASE + 116)
 441 #define ALX_MIB_TX_DEFER                                (ALX_MIB_BASE + 120)
 442 #define ALX_MIB_TX_BYTE_CNT                             (ALX_MIB_BASE + 124)
 443 #define ALX_MIB_TX_SZ_64B                               (ALX_MIB_BASE + 128)
 444 #define ALX_MIB_TX_SZ_127B                              (ALX_MIB_BASE + 132)
 445 #define ALX_MIB_TX_SZ_255B                              (ALX_MIB_BASE + 136)
 446 #define ALX_MIB_TX_SZ_511B                              (ALX_MIB_BASE + 140)
 447 #define ALX_MIB_TX_SZ_1023B                             (ALX_MIB_BASE + 144)
 448 #define ALX_MIB_TX_SZ_1518B                             (ALX_MIB_BASE + 148)
 449 #define ALX_MIB_TX_SZ_MAX                               (ALX_MIB_BASE + 152)
 450 #define ALX_MIB_TX_SINGLE_COL                           (ALX_MIB_BASE + 156)
 451 #define ALX_MIB_TX_MULTI_COL                            (ALX_MIB_BASE + 160)
 452 #define ALX_MIB_TX_LATE_COL                             (ALX_MIB_BASE + 164)
 453 #define ALX_MIB_TX_ABORT_COL                            (ALX_MIB_BASE + 168)
 454 #define ALX_MIB_TX_UNDERRUN                             (ALX_MIB_BASE + 172)
 455 #define ALX_MIB_TX_TRD_EOP                              (ALX_MIB_BASE + 176)
 456 #define ALX_MIB_TX_LEN_ERR                              (ALX_MIB_BASE + 180)
 457 #define ALX_MIB_TX_TRUNC                                (ALX_MIB_BASE + 184)
 458 #define ALX_MIB_TX_BCCNT                                (ALX_MIB_BASE + 188)
 459 #define ALX_MIB_TX_MCCNT                                (ALX_MIB_BASE + 192)
 460 #define ALX_MIB_UPDATE                                  (ALX_MIB_BASE + 196)
 461 
 462 
 463 #define ALX_ISR                                         0x1600
 464 #define ALX_ISR_DIS                                     BIT(31)
 465 #define ALX_ISR_RX_Q7                                   BIT(30)
 466 #define ALX_ISR_RX_Q6                                   BIT(29)
 467 #define ALX_ISR_RX_Q5                                   BIT(28)
 468 #define ALX_ISR_RX_Q4                                   BIT(27)
 469 #define ALX_ISR_PCIE_LNKDOWN                            BIT(26)
 470 #define ALX_ISR_RX_Q3                                   BIT(19)
 471 #define ALX_ISR_RX_Q2                                   BIT(18)
 472 #define ALX_ISR_RX_Q1                                   BIT(17)
 473 #define ALX_ISR_RX_Q0                                   BIT(16)
 474 #define ALX_ISR_TX_Q0                                   BIT(15)
 475 #define ALX_ISR_PHY                                     BIT(12)
 476 #define ALX_ISR_DMAW                                    BIT(10)
 477 #define ALX_ISR_DMAR                                    BIT(9)
 478 #define ALX_ISR_TXF_UR                                  BIT(8)
 479 #define ALX_ISR_TX_Q3                                   BIT(7)
 480 #define ALX_ISR_TX_Q2                                   BIT(6)
 481 #define ALX_ISR_TX_Q1                                   BIT(5)
 482 #define ALX_ISR_RFD_UR                                  BIT(4)
 483 #define ALX_ISR_RXF_OV                                  BIT(3)
 484 #define ALX_ISR_MANU                                    BIT(2)
 485 #define ALX_ISR_TIMER                                   BIT(1)
 486 #define ALX_ISR_SMB                                     BIT(0)
 487 
 488 #define ALX_IMR                                         0x1604
 489 
 490 /* re-send assert msg if SW no response */
 491 #define ALX_INT_RETRIG                                  0x1608
 492 /* 40ms */
 493 #define ALX_INT_RETRIG_TO                               20000
 494 
 495 #define ALX_SMB_TIMER                                   0x15C4
 496 
 497 #define ALX_TINT_TPD_THRSHLD                            0x15C8
 498 
 499 #define ALX_TINT_TIMER                                  0x15CC
 500 
 501 #define ALX_CLK_GATE                                    0x1814
 502 #define ALX_CLK_GATE_RXMAC                              BIT(5)
 503 #define ALX_CLK_GATE_TXMAC                              BIT(4)
 504 #define ALX_CLK_GATE_RXQ                                BIT(3)
 505 #define ALX_CLK_GATE_TXQ                                BIT(2)
 506 #define ALX_CLK_GATE_DMAR                               BIT(1)
 507 #define ALX_CLK_GATE_DMAW                               BIT(0)
 508 #define ALX_CLK_GATE_ALL                (ALX_CLK_GATE_RXMAC | \
 509                                          ALX_CLK_GATE_TXMAC | \
 510                                          ALX_CLK_GATE_RXQ | \
 511                                          ALX_CLK_GATE_TXQ | \
 512                                          ALX_CLK_GATE_DMAR | \
 513                                          ALX_CLK_GATE_DMAW)
 514 
 515 /* interop between drivers */
 516 #define ALX_DRV                                         0x1804
 517 #define ALX_DRV_PHY_AUTO                                BIT(28)
 518 #define ALX_DRV_PHY_1000                                BIT(27)
 519 #define ALX_DRV_PHY_100                                 BIT(26)
 520 #define ALX_DRV_PHY_10                                  BIT(25)
 521 #define ALX_DRV_PHY_DUPLEX                              BIT(24)
 522 /* bit23: adv Pause */
 523 #define ALX_DRV_PHY_PAUSE                               BIT(23)
 524 /* bit22: adv Asym Pause */
 525 #define ALX_DRV_PHY_MASK                                0xFF
 526 #define ALX_DRV_PHY_SHIFT                               21
 527 #define ALX_DRV_PHY_UNKNOWN                             0
 528 
 529 /* flag of phy inited */
 530 #define ALX_PHY_INITED                                  0x003F
 531 
 532 /* reg 1830 ~ 186C for C0+, 16 bit map patterns and wake packet detection */
 533 #define ALX_WOL_CTRL2                                   0x1830
 534 #define ALX_WOL_CTRL2_DATA_STORE                        BIT(3)
 535 #define ALX_WOL_CTRL2_PTRN_EVT                          BIT(2)
 536 #define ALX_WOL_CTRL2_PME_PTRN_EN                       BIT(1)
 537 #define ALX_WOL_CTRL2_PTRN_EN                           BIT(0)
 538 
 539 #define ALX_WOL_CTRL3                                   0x1834
 540 #define ALX_WOL_CTRL3_PTRN_ADDR_MASK                    0xFFFFF
 541 #define ALX_WOL_CTRL3_PTRN_ADDR_SHIFT                   0
 542 
 543 #define ALX_WOL_CTRL4                                   0x1838
 544 #define ALX_WOL_CTRL4_PT15_MATCH                        BIT(31)
 545 #define ALX_WOL_CTRL4_PT14_MATCH                        BIT(30)
 546 #define ALX_WOL_CTRL4_PT13_MATCH                        BIT(29)
 547 #define ALX_WOL_CTRL4_PT12_MATCH                        BIT(28)
 548 #define ALX_WOL_CTRL4_PT11_MATCH                        BIT(27)
 549 #define ALX_WOL_CTRL4_PT10_MATCH                        BIT(26)
 550 #define ALX_WOL_CTRL4_PT9_MATCH                         BIT(25)
 551 #define ALX_WOL_CTRL4_PT8_MATCH                         BIT(24)
 552 #define ALX_WOL_CTRL4_PT7_MATCH                         BIT(23)
 553 #define ALX_WOL_CTRL4_PT6_MATCH                         BIT(22)
 554 #define ALX_WOL_CTRL4_PT5_MATCH                         BIT(21)
 555 #define ALX_WOL_CTRL4_PT4_MATCH                         BIT(20)
 556 #define ALX_WOL_CTRL4_PT3_MATCH                         BIT(19)
 557 #define ALX_WOL_CTRL4_PT2_MATCH                         BIT(18)
 558 #define ALX_WOL_CTRL4_PT1_MATCH                         BIT(17)
 559 #define ALX_WOL_CTRL4_PT0_MATCH                         BIT(16)
 560 #define ALX_WOL_CTRL4_PT15_EN                           BIT(15)
 561 #define ALX_WOL_CTRL4_PT14_EN                           BIT(14)
 562 #define ALX_WOL_CTRL4_PT13_EN                           BIT(13)
 563 #define ALX_WOL_CTRL4_PT12_EN                           BIT(12)
 564 #define ALX_WOL_CTRL4_PT11_EN                           BIT(11)
 565 #define ALX_WOL_CTRL4_PT10_EN                           BIT(10)
 566 #define ALX_WOL_CTRL4_PT9_EN                            BIT(9)
 567 #define ALX_WOL_CTRL4_PT8_EN                            BIT(8)
 568 #define ALX_WOL_CTRL4_PT7_EN                            BIT(7)
 569 #define ALX_WOL_CTRL4_PT6_EN                            BIT(6)
 570 #define ALX_WOL_CTRL4_PT5_EN                            BIT(5)
 571 #define ALX_WOL_CTRL4_PT4_EN                            BIT(4)
 572 #define ALX_WOL_CTRL4_PT3_EN                            BIT(3)
 573 #define ALX_WOL_CTRL4_PT2_EN                            BIT(2)
 574 #define ALX_WOL_CTRL4_PT1_EN                            BIT(1)
 575 #define ALX_WOL_CTRL4_PT0_EN                            BIT(0)
 576 
 577 #define ALX_WOL_CTRL5                                   0x183C
 578 #define ALX_WOL_CTRL5_PT3_LEN_MASK                      0xFF
 579 #define ALX_WOL_CTRL5_PT3_LEN_SHIFT                     24
 580 #define ALX_WOL_CTRL5_PT2_LEN_MASK                      0xFF
 581 #define ALX_WOL_CTRL5_PT2_LEN_SHIFT                     16
 582 #define ALX_WOL_CTRL5_PT1_LEN_MASK                      0xFF
 583 #define ALX_WOL_CTRL5_PT1_LEN_SHIFT                     8
 584 #define ALX_WOL_CTRL5_PT0_LEN_MASK                      0xFF
 585 #define ALX_WOL_CTRL5_PT0_LEN_SHIFT                     0
 586 
 587 #define ALX_WOL_CTRL6                                   0x1840
 588 #define ALX_WOL_CTRL5_PT7_LEN_MASK                      0xFF
 589 #define ALX_WOL_CTRL5_PT7_LEN_SHIFT                     24
 590 #define ALX_WOL_CTRL5_PT6_LEN_MASK                      0xFF
 591 #define ALX_WOL_CTRL5_PT6_LEN_SHIFT                     16
 592 #define ALX_WOL_CTRL5_PT5_LEN_MASK                      0xFF
 593 #define ALX_WOL_CTRL5_PT5_LEN_SHIFT                     8
 594 #define ALX_WOL_CTRL5_PT4_LEN_MASK                      0xFF
 595 #define ALX_WOL_CTRL5_PT4_LEN_SHIFT                     0
 596 
 597 #define ALX_WOL_CTRL7                                   0x1844
 598 #define ALX_WOL_CTRL5_PT11_LEN_MASK                     0xFF
 599 #define ALX_WOL_CTRL5_PT11_LEN_SHIFT                    24
 600 #define ALX_WOL_CTRL5_PT10_LEN_MASK                     0xFF
 601 #define ALX_WOL_CTRL5_PT10_LEN_SHIFT                    16
 602 #define ALX_WOL_CTRL5_PT9_LEN_MASK                      0xFF
 603 #define ALX_WOL_CTRL5_PT9_LEN_SHIFT                     8
 604 #define ALX_WOL_CTRL5_PT8_LEN_MASK                      0xFF
 605 #define ALX_WOL_CTRL5_PT8_LEN_SHIFT                     0
 606 
 607 #define ALX_WOL_CTRL8                                   0x1848
 608 #define ALX_WOL_CTRL5_PT15_LEN_MASK                     0xFF
 609 #define ALX_WOL_CTRL5_PT15_LEN_SHIFT                    24
 610 #define ALX_WOL_CTRL5_PT14_LEN_MASK                     0xFF
 611 #define ALX_WOL_CTRL5_PT14_LEN_SHIFT                    16
 612 #define ALX_WOL_CTRL5_PT13_LEN_MASK                     0xFF
 613 #define ALX_WOL_CTRL5_PT13_LEN_SHIFT                    8
 614 #define ALX_WOL_CTRL5_PT12_LEN_MASK                     0xFF
 615 #define ALX_WOL_CTRL5_PT12_LEN_SHIFT                    0
 616 
 617 #define ALX_ACER_FIXED_PTN0                             0x1850
 618 #define ALX_ACER_FIXED_PTN0_MASK                        0xFFFFFFFF
 619 #define ALX_ACER_FIXED_PTN0_SHIFT                       0
 620 
 621 #define ALX_ACER_FIXED_PTN1                             0x1854
 622 #define ALX_ACER_FIXED_PTN1_MASK                        0xFFFF
 623 #define ALX_ACER_FIXED_PTN1_SHIFT                       0
 624 
 625 #define ALX_ACER_RANDOM_NUM0                            0x1858
 626 #define ALX_ACER_RANDOM_NUM0_MASK                       0xFFFFFFFF
 627 #define ALX_ACER_RANDOM_NUM0_SHIFT                      0
 628 
 629 #define ALX_ACER_RANDOM_NUM1                            0x185C
 630 #define ALX_ACER_RANDOM_NUM1_MASK                       0xFFFFFFFF
 631 #define ALX_ACER_RANDOM_NUM1_SHIFT                      0
 632 
 633 #define ALX_ACER_RANDOM_NUM2                            0x1860
 634 #define ALX_ACER_RANDOM_NUM2_MASK                       0xFFFFFFFF
 635 #define ALX_ACER_RANDOM_NUM2_SHIFT                      0
 636 
 637 #define ALX_ACER_RANDOM_NUM3                            0x1864
 638 #define ALX_ACER_RANDOM_NUM3_MASK                       0xFFFFFFFF
 639 #define ALX_ACER_RANDOM_NUM3_SHIFT                      0
 640 
 641 #define ALX_ACER_MAGIC                                  0x1868
 642 #define ALX_ACER_MAGIC_EN                               BIT(31)
 643 #define ALX_ACER_MAGIC_PME_EN                           BIT(30)
 644 #define ALX_ACER_MAGIC_MATCH                            BIT(29)
 645 #define ALX_ACER_MAGIC_FF_CHECK                         BIT(10)
 646 #define ALX_ACER_MAGIC_RAN_LEN_MASK                     0x1F
 647 #define ALX_ACER_MAGIC_RAN_LEN_SHIFT                    5
 648 #define ALX_ACER_MAGIC_FIX_LEN_MASK                     0x1F
 649 #define ALX_ACER_MAGIC_FIX_LEN_SHIFT                    0
 650 
 651 #define ALX_ACER_TIMER                                  0x186C
 652 #define ALX_ACER_TIMER_EN                               BIT(31)
 653 #define ALX_ACER_TIMER_PME_EN                           BIT(30)
 654 #define ALX_ACER_TIMER_MATCH                            BIT(29)
 655 #define ALX_ACER_TIMER_THRES_MASK                       0x1FFFF
 656 #define ALX_ACER_TIMER_THRES_SHIFT                      0
 657 #define ALX_ACER_TIMER_THRES_DEF                        1
 658 
 659 /* RSS definitions */
 660 #define ALX_RSS_KEY0                                    0x14B0
 661 #define ALX_RSS_KEY1                                    0x14B4
 662 #define ALX_RSS_KEY2                                    0x14B8
 663 #define ALX_RSS_KEY3                                    0x14BC
 664 #define ALX_RSS_KEY4                                    0x14C0
 665 #define ALX_RSS_KEY5                                    0x14C4
 666 #define ALX_RSS_KEY6                                    0x14C8
 667 #define ALX_RSS_KEY7                                    0x14CC
 668 #define ALX_RSS_KEY8                                    0x14D0
 669 #define ALX_RSS_KEY9                                    0x14D4
 670 
 671 #define ALX_RSS_IDT_TBL0                                0x1B00
 672 
 673 #define ALX_MSI_MAP_TBL1                                0x15D0
 674 #define ALX_MSI_MAP_TBL1_TXQ1_SHIFT                     20
 675 #define ALX_MSI_MAP_TBL1_TXQ0_SHIFT                     16
 676 #define ALX_MSI_MAP_TBL1_RXQ3_SHIFT                     12
 677 #define ALX_MSI_MAP_TBL1_RXQ2_SHIFT                     8
 678 #define ALX_MSI_MAP_TBL1_RXQ1_SHIFT                     4
 679 #define ALX_MSI_MAP_TBL1_RXQ0_SHIFT                     0
 680 
 681 #define ALX_MSI_MAP_TBL2                                0x15D8
 682 #define ALX_MSI_MAP_TBL2_TXQ3_SHIFT                     20
 683 #define ALX_MSI_MAP_TBL2_TXQ2_SHIFT                     16
 684 #define ALX_MSI_MAP_TBL2_RXQ7_SHIFT                     12
 685 #define ALX_MSI_MAP_TBL2_RXQ6_SHIFT                     8
 686 #define ALX_MSI_MAP_TBL2_RXQ5_SHIFT                     4
 687 #define ALX_MSI_MAP_TBL2_RXQ4_SHIFT                     0
 688 
 689 #define ALX_MSI_ID_MAP                                  0x15D4
 690 
 691 #define ALX_MSI_RETRANS_TIMER                           0x1920
 692 /* bit16: 1:line,0:standard */
 693 #define ALX_MSI_MASK_SEL_LINE                           BIT(16)
 694 #define ALX_MSI_RETRANS_TM_MASK                         0xFFFF
 695 #define ALX_MSI_RETRANS_TM_SHIFT                        0
 696 
 697 /* CR DMA ctrl */
 698 
 699 /* TX QoS */
 700 #define ALX_WRR                                         0x1938
 701 #define ALX_WRR_PRI_MASK                                0x3
 702 #define ALX_WRR_PRI_SHIFT                               29
 703 #define ALX_WRR_PRI_RESTRICT_NONE                       3
 704 #define ALX_WRR_PRI3_MASK                               0x1F
 705 #define ALX_WRR_PRI3_SHIFT                              24
 706 #define ALX_WRR_PRI2_MASK                               0x1F
 707 #define ALX_WRR_PRI2_SHIFT                              16
 708 #define ALX_WRR_PRI1_MASK                               0x1F
 709 #define ALX_WRR_PRI1_SHIFT                              8
 710 #define ALX_WRR_PRI0_MASK                               0x1F
 711 #define ALX_WRR_PRI0_SHIFT                              0
 712 
 713 #define ALX_HQTPD                                       0x193C
 714 #define ALX_HQTPD_BURST_EN                              BIT(31)
 715 #define ALX_HQTPD_Q3_NUMPREF_MASK                       0xF
 716 #define ALX_HQTPD_Q3_NUMPREF_SHIFT                      8
 717 #define ALX_HQTPD_Q2_NUMPREF_MASK                       0xF
 718 #define ALX_HQTPD_Q2_NUMPREF_SHIFT                      4
 719 #define ALX_HQTPD_Q1_NUMPREF_MASK                       0xF
 720 #define ALX_HQTPD_Q1_NUMPREF_SHIFT                      0
 721 
 722 #define ALX_MISC                                        0x19C0
 723 #define ALX_MISC_PSW_OCP_MASK                           0x7
 724 #define ALX_MISC_PSW_OCP_SHIFT                          21
 725 #define ALX_MISC_PSW_OCP_DEF                            0x7
 726 #define ALX_MISC_ISO_EN                                 BIT(12)
 727 #define ALX_MISC_INTNLOSC_OPEN                          BIT(3)
 728 
 729 #define ALX_MSIC2                                       0x19C8
 730 #define ALX_MSIC2_CALB_START                            BIT(0)
 731 
 732 #define ALX_MISC3                                       0x19CC
 733 /* bit1: 1:Software control 25M */
 734 #define ALX_MISC3_25M_BY_SW                             BIT(1)
 735 /* bit0: 25M switch to intnl OSC */
 736 #define ALX_MISC3_25M_NOTO_INTNL                        BIT(0)
 737 
 738 /* MSIX tbl in memory space */
 739 #define ALX_MSIX_ENTRY_BASE                             0x2000
 740 
 741 /********************* PHY regs definition ***************************/
 742 
 743 /* PHY Specific Status Register */
 744 #define ALX_MII_GIGA_PSSR                               0x11
 745 #define ALX_GIGA_PSSR_SPD_DPLX_RESOLVED                 0x0800
 746 #define ALX_GIGA_PSSR_DPLX                              0x2000
 747 #define ALX_GIGA_PSSR_SPEED                             0xC000
 748 #define ALX_GIGA_PSSR_10MBS                             0x0000
 749 #define ALX_GIGA_PSSR_100MBS                            0x4000
 750 #define ALX_GIGA_PSSR_1000MBS                           0x8000
 751 
 752 /* PHY Interrupt Enable Register */
 753 #define ALX_MII_IER                                     0x12
 754 #define ALX_IER_LINK_UP                                 0x0400
 755 #define ALX_IER_LINK_DOWN                               0x0800
 756 
 757 /* PHY Interrupt Status Register */
 758 #define ALX_MII_ISR                                     0x13
 759 
 760 #define ALX_MII_DBG_ADDR                                0x1D
 761 #define ALX_MII_DBG_DATA                                0x1E
 762 
 763 /***************************** debug port *************************************/
 764 
 765 #define ALX_MIIDBG_ANACTRL                              0x00
 766 #define ALX_ANACTRL_DEF                                 0x02EF
 767 
 768 #define ALX_MIIDBG_SYSMODCTRL                           0x04
 769 /* en half bias */
 770 #define ALX_SYSMODCTRL_IECHOADJ_DEF                     0xBB8B
 771 
 772 #define ALX_MIIDBG_SRDSYSMOD                            0x05
 773 #define ALX_SRDSYSMOD_DEEMP_EN                          0x0040
 774 #define ALX_SRDSYSMOD_DEF                               0x2C46
 775 
 776 #define ALX_MIIDBG_HIBNEG                               0x0B
 777 #define ALX_HIBNEG_PSHIB_EN                             0x8000
 778 #define ALX_HIBNEG_HIB_PSE                              0x1000
 779 #define ALX_HIBNEG_DEF                                  0xBC40
 780 #define ALX_HIBNEG_NOHIB        (ALX_HIBNEG_DEF & \
 781                                  ~(ALX_HIBNEG_PSHIB_EN | ALX_HIBNEG_HIB_PSE))
 782 
 783 #define ALX_MIIDBG_TST10BTCFG                           0x12
 784 #define ALX_TST10BTCFG_DEF                              0x4C04
 785 
 786 #define ALX_MIIDBG_AZ_ANADECT                           0x15
 787 #define ALX_AZ_ANADECT_DEF                              0x3220
 788 #define ALX_AZ_ANADECT_LONG                             0x3210
 789 
 790 #define ALX_MIIDBG_MSE16DB                              0x18
 791 #define ALX_MSE16DB_UP                                  0x05EA
 792 #define ALX_MSE16DB_DOWN                                0x02EA
 793 
 794 #define ALX_MIIDBG_MSE20DB                              0x1C
 795 #define ALX_MSE20DB_TH_MASK                             0x7F
 796 #define ALX_MSE20DB_TH_SHIFT                            2
 797 #define ALX_MSE20DB_TH_DEF                              0x2E
 798 #define ALX_MSE20DB_TH_HI                               0x54
 799 
 800 #define ALX_MIIDBG_AGC                                  0x23
 801 #define ALX_AGC_2_VGA_MASK                              0x3FU
 802 #define ALX_AGC_2_VGA_SHIFT                             8
 803 #define ALX_AGC_LONG1G_LIMT                             40
 804 #define ALX_AGC_LONG100M_LIMT                           44
 805 
 806 #define ALX_MIIDBG_LEGCYPS                              0x29
 807 #define ALX_LEGCYPS_EN                                  0x8000
 808 #define ALX_LEGCYPS_DEF                                 0x129D
 809 
 810 #define ALX_MIIDBG_TST100BTCFG                          0x36
 811 #define ALX_TST100BTCFG_DEF                             0xE12C
 812 
 813 #define ALX_MIIDBG_GREENCFG                             0x3B
 814 #define ALX_GREENCFG_DEF                                0x7078
 815 
 816 #define ALX_MIIDBG_GREENCFG2                            0x3D
 817 #define ALX_GREENCFG2_BP_GREEN                          0x8000
 818 #define ALX_GREENCFG2_GATE_DFSE_EN                      0x0080
 819 
 820 /******* dev 3 *********/
 821 #define ALX_MIIEXT_PCS                                  3
 822 
 823 #define ALX_MIIEXT_CLDCTRL3                             0x8003
 824 #define ALX_CLDCTRL3_BP_CABLE1TH_DET_GT                 0x8000
 825 
 826 #define ALX_MIIEXT_CLDCTRL5                             0x8005
 827 #define ALX_CLDCTRL5_BP_VD_HLFBIAS                      0x4000
 828 
 829 #define ALX_MIIEXT_CLDCTRL6                             0x8006
 830 #define ALX_CLDCTRL6_CAB_LEN_MASK                       0xFF
 831 #define ALX_CLDCTRL6_CAB_LEN_SHIFT                      0
 832 #define ALX_CLDCTRL6_CAB_LEN_SHORT1G                    116
 833 #define ALX_CLDCTRL6_CAB_LEN_SHORT100M                  152
 834 
 835 #define ALX_MIIEXT_VDRVBIAS                             0x8062
 836 #define ALX_VDRVBIAS_DEF                                0x3
 837 
 838 /********* dev 7 **********/
 839 #define ALX_MIIEXT_ANEG                                 7
 840 
 841 #define ALX_MIIEXT_LOCAL_EEEADV                         0x3C
 842 #define ALX_LOCAL_EEEADV_1000BT                         0x0004
 843 #define ALX_LOCAL_EEEADV_100BT                          0x0002
 844 
 845 #define ALX_MIIEXT_AFE                                  0x801A
 846 #define ALX_AFE_10BT_100M_TH                            0x0040
 847 
 848 #define ALX_MIIEXT_S3DIG10                              0x8023
 849 /* bit0: 1:bypass 10BT rx fifo, 0:original 10BT rx */
 850 #define ALX_MIIEXT_S3DIG10_SL                           0x0001
 851 #define ALX_MIIEXT_S3DIG10_DEF                          0
 852 
 853 #define ALX_MIIEXT_NLP78                                0x8027
 854 #define ALX_MIIEXT_NLP78_120M_DEF                       0x8A05
 855 
 856 #endif