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   9 #ifndef __XGENE_ENET_SGMAC_H__
  10 #define __XGENE_ENET_SGMAC_H__
  11 
  12 #define PHY_ADDR(src)           (((src)<<8) & GENMASK(12, 8))
  13 #define REG_ADDR(src)           ((src) & GENMASK(4, 0))
  14 #define PHY_CONTROL(src)        ((src) & GENMASK(15, 0))
  15 #define LINK_SPEED(src)         (((src) & GENMASK(11, 10)) >> 10)
  16 #define INT_PHY_ADDR                    0x1e
  17 #define SGMII_TBI_CONTROL_ADDR          0x44
  18 #define SGMII_CONTROL_ADDR              0x00
  19 #define SGMII_STATUS_ADDR               0x04
  20 #define SGMII_BASE_PAGE_ABILITY_ADDR    0x14
  21 #define AUTO_NEG_COMPLETE               BIT(5)
  22 #define LINK_STATUS                     BIT(2)
  23 #define LINK_UP                         BIT(15)
  24 #define MPA_IDLE_WITH_QMI_EMPTY         BIT(12)
  25 #define SG_RX_DV_GATE_REG_0_ADDR        0x05fc
  26 #define SGMII_EN                        0x1
  27 
  28 enum xgene_phy_speed {
  29         PHY_SPEED_10,
  30         PHY_SPEED_100,
  31         PHY_SPEED_1000
  32 };
  33 
  34 extern const struct xgene_mac_ops xgene_sgmac_ops;
  35 extern const struct xgene_port_ops xgene_sgport_ops;
  36 
  37 #endif