root/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /* Applied Micro X-Gene SoC Ethernet Driver
   3  *
   4  * Copyright (c) 2014, Applied Micro Circuits Corporation
   5  * Authors: Iyappan Subramanian <isubramanian@apm.com>
   6  *          Keyur Chudgar <kchudgar@apm.com>
   7  */
   8 
   9 #ifndef __XGENE_ENET_XGMAC_H__
  10 #define __XGENE_ENET_XGMAC_H__
  11 
  12 #define X2_BLOCK_ETH_MAC_CSR_OFFSET     0x3000
  13 #define BLOCK_AXG_MAC_OFFSET            0x0800
  14 #define BLOCK_AXG_STATS_OFFSET          0x0800
  15 #define BLOCK_AXG_MAC_CSR_OFFSET        0x2000
  16 #define BLOCK_PCS_OFFSET                0x3800
  17 
  18 #define XGENET_CONFIG_REG_ADDR          0x20
  19 #define XGENET_SRST_ADDR                0x00
  20 #define XGENET_CLKEN_ADDR               0x08
  21 
  22 #define CSR_CLK         BIT(0)
  23 #define XGENET_CLK      BIT(1)
  24 #define PCS_CLK         BIT(3)
  25 #define AN_REF_CLK      BIT(4)
  26 #define AN_CLK          BIT(5)
  27 #define AD_CLK          BIT(6)
  28 
  29 #define CSR_RST         BIT(0)
  30 #define XGENET_RST      BIT(1)
  31 #define PCS_RST         BIT(3)
  32 #define AN_REF_RST      BIT(4)
  33 #define AN_RST          BIT(5)
  34 #define AD_RST          BIT(6)
  35 
  36 #define AXGMAC_CONFIG_0                 0x0000
  37 #define AXGMAC_CONFIG_1                 0x0004
  38 #define HSTMACRST                       BIT(31)
  39 #define HSTTCTLEN                       BIT(31)
  40 #define HSTTFEN                         BIT(30)
  41 #define HSTRCTLEN                       BIT(29)
  42 #define HSTRFEN                         BIT(28)
  43 #define HSTPPEN                         BIT(7)
  44 #define HSTDRPLT64                      BIT(5)
  45 #define HSTLENCHK                       BIT(3)
  46 #define HSTMACADR_LSW_ADDR              0x0010
  47 #define HSTMACADR_MSW_ADDR              0x0014
  48 #define HSTMAXFRAME_LENGTH_ADDR         0x0020
  49 
  50 #define XG_MCX_RX_DV_GATE_REG_0_ADDR    0x0004
  51 #define XG_MCX_ECM_CFG_0_ADDR           0x0074
  52 #define XG_MCX_MULTI_DPF0_ADDR          0x007c
  53 #define XG_MCX_MULTI_DPF1_ADDR          0x0080
  54 #define XG_DEF_PAUSE_THRES              0x390
  55 #define XG_DEF_PAUSE_OFF_THRES          0x2c0
  56 #define XG_RSIF_CONFIG_REG_ADDR         0x00a0
  57 #define XG_RSIF_CLE_BUFF_THRESH                0x3
  58 #define RSIF_CLE_BUFF_THRESH_SET(dst, val)     xgene_set_bits(dst, val, 0, 3)
  59 #define XG_RSIF_CONFIG1_REG_ADDR       0x00b8
  60 #define XG_RSIF_PLC_CLE_BUFF_THRESH    0x1
  61 #define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 2)
  62 #define XG_MCX_ECM_CONFIG0_REG_0_ADDR          0x0070
  63 #define XG_MCX_ICM_ECM_DROP_COUNT_REG0_ADDR    0x0124
  64 #define XCLE_BYPASS_REG0_ADDR           0x0160
  65 #define XCLE_BYPASS_REG1_ADDR           0x0164
  66 #define XG_CFG_BYPASS_ADDR              0x0204
  67 #define XG_CFG_LINK_AGGR_RESUME_0_ADDR  0x0214
  68 #define XG_LINK_STATUS_ADDR             0x0228
  69 #define XG_TSIF_MSS_REG0_ADDR           0x02a4
  70 #define XG_DEBUG_REG_ADDR               0x0400
  71 #define XG_ENET_SPARE_CFG_REG_ADDR      0x040c
  72 #define XG_ENET_SPARE_CFG_REG_1_ADDR    0x0410
  73 #define XGENET_RX_DV_GATE_REG_0_ADDR    0x0804
  74 #define XGENET_ECM_CONFIG0_REG_0        0x0870
  75 #define XGENET_ICM_ECM_DROP_COUNT_REG0  0x0924
  76 #define XGENET_CSR_ECM_CFG_0_ADDR       0x0880
  77 #define XGENET_CSR_MULTI_DPF0_ADDR      0x0888
  78 #define XGENET_CSR_MULTI_DPF1_ADDR      0x088c
  79 #define XG_RXBUF_PAUSE_THRESH           0x0020
  80 #define XG_MCX_ICM_CONFIG0_REG_0_ADDR   0x00e0
  81 #define XG_MCX_ICM_CONFIG2_REG_0_ADDR   0x00e8
  82 
  83 #define PCS_CONTROL_1                   0x0000
  84 #define PCS_CTRL_PCS_RST                BIT(15)
  85 
  86 extern const struct xgene_mac_ops xgene_xgmac_ops;
  87 extern const struct xgene_port_ops xgene_xgport_ops;
  88 
  89 #endif /* __XGENE_ENET_XGMAC_H__ */