root/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 1999 - 2010 Intel Corporation.
   4  * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
   5  *
   6  * This code was derived from the Intel e1000e Linux driver.
   7  */
   8 
   9 #ifndef _PCH_GBE_H_
  10 #define _PCH_GBE_H_
  11 
  12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13 
  14 #include <linux/mii.h>
  15 #include <linux/delay.h>
  16 #include <linux/pci.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/vmalloc.h>
  21 #include <net/ip.h>
  22 #include <net/tcp.h>
  23 #include <net/udp.h>
  24 
  25 /**
  26  * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
  27  * @high        Denotes the 1st to 4th byte from the initial of MAC address
  28  * @low         Denotes the 5th to 6th byte from the initial of MAC address
  29  */
  30 struct pch_gbe_regs_mac_adr {
  31         u32 high;
  32         u32 low;
  33 };
  34 /**
  35  * pch_udc_regs - Structure holding values of MAC registers
  36  */
  37 struct pch_gbe_regs {
  38         u32 INT_ST;
  39         u32 INT_EN;
  40         u32 MODE;
  41         u32 RESET;
  42         u32 TCPIP_ACC;
  43         u32 EX_LIST;
  44         u32 INT_ST_HOLD;
  45         u32 PHY_INT_CTRL;
  46         u32 MAC_RX_EN;
  47         u32 RX_FCTRL;
  48         u32 PAUSE_REQ;
  49         u32 RX_MODE;
  50         u32 TX_MODE;
  51         u32 RX_FIFO_ST;
  52         u32 TX_FIFO_ST;
  53         u32 TX_FID;
  54         u32 TX_RESULT;
  55         u32 PAUSE_PKT1;
  56         u32 PAUSE_PKT2;
  57         u32 PAUSE_PKT3;
  58         u32 PAUSE_PKT4;
  59         u32 PAUSE_PKT5;
  60         u32 reserve[2];
  61         struct pch_gbe_regs_mac_adr mac_adr[16];
  62         u32 ADDR_MASK;
  63         u32 MIIM;
  64         u32 MAC_ADDR_LOAD;
  65         u32 RGMII_ST;
  66         u32 RGMII_CTRL;
  67         u32 reserve3[3];
  68         u32 DMA_CTRL;
  69         u32 reserve4[3];
  70         u32 RX_DSC_BASE;
  71         u32 RX_DSC_SIZE;
  72         u32 RX_DSC_HW_P;
  73         u32 RX_DSC_HW_P_HLD;
  74         u32 RX_DSC_SW_P;
  75         u32 reserve5[3];
  76         u32 TX_DSC_BASE;
  77         u32 TX_DSC_SIZE;
  78         u32 TX_DSC_HW_P;
  79         u32 TX_DSC_HW_P_HLD;
  80         u32 TX_DSC_SW_P;
  81         u32 reserve6[3];
  82         u32 RX_DMA_ST;
  83         u32 TX_DMA_ST;
  84         u32 reserve7[2];
  85         u32 WOL_ST;
  86         u32 WOL_CTRL;
  87         u32 WOL_ADDR_MASK;
  88 };
  89 
  90 /* Interrupt Status */
  91 /* Interrupt Status Hold */
  92 /* Interrupt Enable */
  93 #define PCH_GBE_INT_RX_DMA_CMPLT  0x00000001 /* Receive DMA Transfer Complete */
  94 #define PCH_GBE_INT_RX_VALID      0x00000002 /* MAC Normal Receive Complete */
  95 #define PCH_GBE_INT_RX_FRAME_ERR  0x00000004 /* Receive frame error */
  96 #define PCH_GBE_INT_RX_FIFO_ERR   0x00000008 /* Receive FIFO Overflow */
  97 #define PCH_GBE_INT_RX_DMA_ERR    0x00000010 /* Receive DMA Transfer Error */
  98 #define PCH_GBE_INT_RX_DSC_EMP    0x00000020 /* Receive Descriptor Empty */
  99 #define PCH_GBE_INT_TX_CMPLT      0x00000100 /* MAC Transmission Complete */
 100 #define PCH_GBE_INT_TX_DMA_CMPLT  0x00000200 /* DMA Transfer Complete */
 101 #define PCH_GBE_INT_TX_FIFO_ERR   0x00000400 /* Transmission FIFO underflow. */
 102 #define PCH_GBE_INT_TX_DMA_ERR    0x00000800 /* Transmission DMA Error */
 103 #define PCH_GBE_INT_PAUSE_CMPLT   0x00001000 /* Pause Transmission complete */
 104 #define PCH_GBE_INT_MIIM_CMPLT    0x00010000 /* MIIM I/F Read completion */
 105 #define PCH_GBE_INT_PHY_INT       0x00100000 /* Interruption from PHY */
 106 #define PCH_GBE_INT_WOL_DET       0x01000000 /* Wake On LAN Event detection. */
 107 #define PCH_GBE_INT_TCPIP_ERR     0x10000000 /* TCP/IP Accelerator Error */
 108 
 109 /* Mode */
 110 #define PCH_GBE_MODE_MII_ETHER      0x00000000  /* GIGA Ethernet Mode [MII] */
 111 #define PCH_GBE_MODE_GMII_ETHER     0x80000000  /* GIGA Ethernet Mode [GMII] */
 112 #define PCH_GBE_MODE_HALF_DUPLEX    0x00000000  /* Duplex Mode [half duplex] */
 113 #define PCH_GBE_MODE_FULL_DUPLEX    0x40000000  /* Duplex Mode [full duplex] */
 114 #define PCH_GBE_MODE_FR_BST         0x04000000  /* Frame bursting is done */
 115 
 116 /* Reset */
 117 #define PCH_GBE_ALL_RST         0x80000000  /* All reset */
 118 #define PCH_GBE_TX_RST          0x00008000  /* TX MAC, TX FIFO, TX DMA reset */
 119 #define PCH_GBE_RX_RST          0x00004000  /* RX MAC, RX FIFO, RX DMA reset */
 120 
 121 /* TCP/IP Accelerator Control */
 122 #define PCH_GBE_EX_LIST_EN      0x00000008  /* External List Enable */
 123 #define PCH_GBE_RX_TCPIPACC_OFF 0x00000004  /* RX TCP/IP ACC Disabled */
 124 #define PCH_GBE_TX_TCPIPACC_EN  0x00000002  /* TX TCP/IP ACC Enable */
 125 #define PCH_GBE_RX_TCPIPACC_EN  0x00000001  /* RX TCP/IP ACC Enable */
 126 
 127 /* MAC RX Enable */
 128 #define PCH_GBE_MRE_MAC_RX_EN   0x00000001      /* MAC Receive Enable */
 129 
 130 /* RX Flow Control */
 131 #define PCH_GBE_FL_CTRL_EN      0x80000000  /* Pause packet is enabled */
 132 
 133 /* Pause Packet Request */
 134 #define PCH_GBE_PS_PKT_RQ       0x80000000  /* Pause packet Request */
 135 
 136 /* RX Mode */
 137 #define PCH_GBE_ADD_FIL_EN      0x80000000  /* Address Filtering Enable */
 138 /* Multicast Filtering Enable */
 139 #define PCH_GBE_MLT_FIL_EN      0x40000000
 140 /* Receive Almost Empty Threshold */
 141 #define PCH_GBE_RH_ALM_EMP_4    0x00000000      /* 4 words */
 142 #define PCH_GBE_RH_ALM_EMP_8    0x00004000      /* 8 words */
 143 #define PCH_GBE_RH_ALM_EMP_16   0x00008000      /* 16 words */
 144 #define PCH_GBE_RH_ALM_EMP_32   0x0000C000      /* 32 words */
 145 /* Receive Almost Full Threshold */
 146 #define PCH_GBE_RH_ALM_FULL_4   0x00000000      /* 4 words */
 147 #define PCH_GBE_RH_ALM_FULL_8   0x00001000      /* 8 words */
 148 #define PCH_GBE_RH_ALM_FULL_16  0x00002000      /* 16 words */
 149 #define PCH_GBE_RH_ALM_FULL_32  0x00003000      /* 32 words */
 150 /* RX FIFO Read Triger Threshold */
 151 #define PCH_GBE_RH_RD_TRG_4     0x00000000      /* 4 words */
 152 #define PCH_GBE_RH_RD_TRG_8     0x00000200      /* 8 words */
 153 #define PCH_GBE_RH_RD_TRG_16    0x00000400      /* 16 words */
 154 #define PCH_GBE_RH_RD_TRG_32    0x00000600      /* 32 words */
 155 #define PCH_GBE_RH_RD_TRG_64    0x00000800      /* 64 words */
 156 #define PCH_GBE_RH_RD_TRG_128   0x00000A00      /* 128 words */
 157 #define PCH_GBE_RH_RD_TRG_256   0x00000C00      /* 256 words */
 158 #define PCH_GBE_RH_RD_TRG_512   0x00000E00      /* 512 words */
 159 
 160 /* Receive Descriptor bit definitions */
 161 #define PCH_GBE_RXD_ACC_STAT_BCAST          0x00000400
 162 #define PCH_GBE_RXD_ACC_STAT_MCAST          0x00000200
 163 #define PCH_GBE_RXD_ACC_STAT_UCAST          0x00000100
 164 #define PCH_GBE_RXD_ACC_STAT_TCPIPOK        0x000000C0
 165 #define PCH_GBE_RXD_ACC_STAT_IPOK           0x00000080
 166 #define PCH_GBE_RXD_ACC_STAT_TCPOK          0x00000040
 167 #define PCH_GBE_RXD_ACC_STAT_IP6ERR         0x00000020
 168 #define PCH_GBE_RXD_ACC_STAT_OFLIST         0x00000010
 169 #define PCH_GBE_RXD_ACC_STAT_TYPEIP         0x00000008
 170 #define PCH_GBE_RXD_ACC_STAT_MACL           0x00000004
 171 #define PCH_GBE_RXD_ACC_STAT_PPPOE          0x00000002
 172 #define PCH_GBE_RXD_ACC_STAT_VTAGT          0x00000001
 173 #define PCH_GBE_RXD_GMAC_STAT_PAUSE         0x0200
 174 #define PCH_GBE_RXD_GMAC_STAT_MARBR         0x0100
 175 #define PCH_GBE_RXD_GMAC_STAT_MARMLT        0x0080
 176 #define PCH_GBE_RXD_GMAC_STAT_MARIND        0x0040
 177 #define PCH_GBE_RXD_GMAC_STAT_MARNOTMT      0x0020
 178 #define PCH_GBE_RXD_GMAC_STAT_TLONG         0x0010
 179 #define PCH_GBE_RXD_GMAC_STAT_TSHRT         0x0008
 180 #define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL      0x0004
 181 #define PCH_GBE_RXD_GMAC_STAT_NBLERR        0x0002
 182 #define PCH_GBE_RXD_GMAC_STAT_CRCERR        0x0001
 183 
 184 /* Transmit Descriptor bit definitions */
 185 #define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF      0x0008
 186 #define PCH_GBE_TXD_CTRL_ITAG               0x0004
 187 #define PCH_GBE_TXD_CTRL_ICRC               0x0002
 188 #define PCH_GBE_TXD_CTRL_APAD               0x0001
 189 #define PCH_GBE_TXD_WORDS_SHIFT             2
 190 #define PCH_GBE_TXD_GMAC_STAT_CMPLT         0x2000
 191 #define PCH_GBE_TXD_GMAC_STAT_ABT           0x1000
 192 #define PCH_GBE_TXD_GMAC_STAT_EXCOL         0x0800
 193 #define PCH_GBE_TXD_GMAC_STAT_SNGCOL        0x0400
 194 #define PCH_GBE_TXD_GMAC_STAT_MLTCOL        0x0200
 195 #define PCH_GBE_TXD_GMAC_STAT_CRSER         0x0100
 196 #define PCH_GBE_TXD_GMAC_STAT_TLNG          0x0080
 197 #define PCH_GBE_TXD_GMAC_STAT_TSHRT         0x0040
 198 #define PCH_GBE_TXD_GMAC_STAT_LTCOL         0x0020
 199 #define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW      0x0010
 200 #define PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK   0x000F
 201 
 202 /* TX Mode */
 203 #define PCH_GBE_TM_NO_RTRY     0x80000000 /* No Retransmission */
 204 #define PCH_GBE_TM_LONG_PKT    0x40000000 /* Long Packt TX Enable */
 205 #define PCH_GBE_TM_ST_AND_FD   0x20000000 /* Stare and Forward */
 206 #define PCH_GBE_TM_SHORT_PKT   0x10000000 /* Short Packet TX Enable */
 207 #define PCH_GBE_TM_LTCOL_RETX  0x08000000 /* Retransmission at Late Collision */
 208 /* Frame Start Threshold */
 209 #define PCH_GBE_TM_TH_TX_STRT_4    0x00000000    /* 4 words */
 210 #define PCH_GBE_TM_TH_TX_STRT_8    0x00004000    /* 8 words */
 211 #define PCH_GBE_TM_TH_TX_STRT_16   0x00008000    /* 16 words */
 212 #define PCH_GBE_TM_TH_TX_STRT_32   0x0000C000    /* 32 words */
 213 /* Transmit Almost Empty Threshold */
 214 #define PCH_GBE_TM_TH_ALM_EMP_4    0x00000000    /* 4 words */
 215 #define PCH_GBE_TM_TH_ALM_EMP_8    0x00000800    /* 8 words */
 216 #define PCH_GBE_TM_TH_ALM_EMP_16   0x00001000    /* 16 words */
 217 #define PCH_GBE_TM_TH_ALM_EMP_32   0x00001800    /* 32 words */
 218 #define PCH_GBE_TM_TH_ALM_EMP_64   0x00002000    /* 64 words */
 219 #define PCH_GBE_TM_TH_ALM_EMP_128  0x00002800    /* 128 words */
 220 #define PCH_GBE_TM_TH_ALM_EMP_256  0x00003000    /* 256 words */
 221 #define PCH_GBE_TM_TH_ALM_EMP_512  0x00003800    /* 512 words */
 222 /* Transmit Almost Full Threshold */
 223 #define PCH_GBE_TM_TH_ALM_FULL_4   0x00000000    /* 4 words */
 224 #define PCH_GBE_TM_TH_ALM_FULL_8   0x00000200    /* 8 words */
 225 #define PCH_GBE_TM_TH_ALM_FULL_16  0x00000400    /* 16 words */
 226 #define PCH_GBE_TM_TH_ALM_FULL_32  0x00000600    /* 32 words */
 227 
 228 /* RX FIFO Status */
 229 #define PCH_GBE_RF_ALM_FULL     0x80000000  /* RX FIFO is almost full. */
 230 #define PCH_GBE_RF_ALM_EMP      0x40000000  /* RX FIFO is almost empty. */
 231 #define PCH_GBE_RF_RD_TRG       0x20000000  /* Become more than RH_RD_TRG. */
 232 #define PCH_GBE_RF_STRWD        0x1FFE0000  /* The word count of RX FIFO. */
 233 #define PCH_GBE_RF_RCVING       0x00010000  /* Stored in RX FIFO. */
 234 
 235 /* MAC Address Mask */
 236 #define PCH_GBE_BUSY                0x80000000
 237 
 238 /* MIIM  */
 239 #define PCH_GBE_MIIM_OPER_WRITE     0x04000000
 240 #define PCH_GBE_MIIM_OPER_READ      0x00000000
 241 #define PCH_GBE_MIIM_OPER_READY     0x04000000
 242 #define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
 243 #define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
 244 
 245 /* RGMII Status */
 246 #define PCH_GBE_LINK_UP             0x80000008
 247 #define PCH_GBE_RXC_SPEED_MSK       0x00000006
 248 #define PCH_GBE_RXC_SPEED_2_5M      0x00000000    /* 2.5MHz */
 249 #define PCH_GBE_RXC_SPEED_25M       0x00000002    /* 25MHz  */
 250 #define PCH_GBE_RXC_SPEED_125M      0x00000004    /* 100MHz */
 251 #define PCH_GBE_DUPLEX_FULL         0x00000001
 252 
 253 /* RGMII Control */
 254 #define PCH_GBE_CRS_SEL             0x00000010
 255 #define PCH_GBE_RGMII_RATE_125M     0x00000000
 256 #define PCH_GBE_RGMII_RATE_25M      0x00000008
 257 #define PCH_GBE_RGMII_RATE_2_5M     0x0000000C
 258 #define PCH_GBE_RGMII_MODE_GMII     0x00000000
 259 #define PCH_GBE_RGMII_MODE_RGMII    0x00000002
 260 #define PCH_GBE_CHIP_TYPE_EXTERNAL  0x00000000
 261 #define PCH_GBE_CHIP_TYPE_INTERNAL  0x00000001
 262 
 263 /* DMA Control */
 264 #define PCH_GBE_RX_DMA_EN       0x00000002   /* Enables Receive DMA */
 265 #define PCH_GBE_TX_DMA_EN       0x00000001   /* Enables Transmission DMA */
 266 
 267 /* RX DMA STATUS */
 268 #define PCH_GBE_IDLE_CHECK       0xFFFFFFFE
 269 
 270 /* Wake On LAN Status */
 271 #define PCH_GBE_WLS_BR          0x00000008 /* Broadcas Address */
 272 #define PCH_GBE_WLS_MLT         0x00000004 /* Multicast Address */
 273 
 274 /* The Frame registered in Address Recognizer */
 275 #define PCH_GBE_WLS_IND         0x00000002
 276 #define PCH_GBE_WLS_MP          0x00000001 /* Magic packet Address */
 277 
 278 /* Wake On LAN Control */
 279 #define PCH_GBE_WLC_WOL_MODE    0x00010000
 280 #define PCH_GBE_WLC_IGN_TLONG   0x00000100
 281 #define PCH_GBE_WLC_IGN_TSHRT   0x00000080
 282 #define PCH_GBE_WLC_IGN_OCTER   0x00000040
 283 #define PCH_GBE_WLC_IGN_NBLER   0x00000020
 284 #define PCH_GBE_WLC_IGN_CRCER   0x00000010
 285 #define PCH_GBE_WLC_BR          0x00000008
 286 #define PCH_GBE_WLC_MLT         0x00000004
 287 #define PCH_GBE_WLC_IND         0x00000002
 288 #define PCH_GBE_WLC_MP          0x00000001
 289 
 290 /* Wake On LAN Address Mask */
 291 #define PCH_GBE_WLA_BUSY        0x80000000
 292 
 293 
 294 
 295 /* TX/RX descriptor defines */
 296 #define PCH_GBE_MAX_TXD                     4096
 297 #define PCH_GBE_DEFAULT_TXD                  256
 298 #define PCH_GBE_MIN_TXD                        8
 299 #define PCH_GBE_MAX_RXD                     4096
 300 #define PCH_GBE_DEFAULT_RXD                  256
 301 #define PCH_GBE_MIN_RXD                        8
 302 
 303 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
 304 #define PCH_GBE_TX_DESC_MULTIPLE               8
 305 #define PCH_GBE_RX_DESC_MULTIPLE               8
 306 
 307 /* Read/Write operation is done through MII Management IF */
 308 #define PCH_GBE_HAL_MIIM_READ          ((u32)0x00000000)
 309 #define PCH_GBE_HAL_MIIM_WRITE         ((u32)0x04000000)
 310 
 311 /* flow control values */
 312 #define PCH_GBE_FC_NONE                 0
 313 #define PCH_GBE_FC_RX_PAUSE             1
 314 #define PCH_GBE_FC_TX_PAUSE             2
 315 #define PCH_GBE_FC_FULL                 3
 316 #define PCH_GBE_FC_DEFAULT              PCH_GBE_FC_FULL
 317 
 318 /**
 319  * struct pch_gbe_mac_info - MAC information
 320  * @addr[6]:            Store the MAC address
 321  * @fc:                 Mode of flow control
 322  * @fc_autoneg:         Auto negotiation enable for flow control setting
 323  * @tx_fc_enable:       Enable flag of Transmit flow control
 324  * @max_frame_size:     Max transmit frame size
 325  * @min_frame_size:     Min transmit frame size
 326  * @autoneg:            Auto negotiation enable
 327  * @link_speed:         Link speed
 328  * @link_duplex:        Link duplex
 329  */
 330 struct pch_gbe_mac_info {
 331         u8 addr[6];
 332         u8 fc;
 333         u8 fc_autoneg;
 334         u8 tx_fc_enable;
 335         u32 max_frame_size;
 336         u32 min_frame_size;
 337         u8 autoneg;
 338         u16 link_speed;
 339         u16 link_duplex;
 340 };
 341 
 342 /**
 343  * struct pch_gbe_phy_info - PHY information
 344  * @addr:               PHY address
 345  * @id:                 PHY's identifier
 346  * @revision:           PHY's revision
 347  * @reset_delay_us:     HW reset delay time[us]
 348  * @autoneg_advertised: Autoneg advertised
 349  */
 350 struct pch_gbe_phy_info {
 351         u32 addr;
 352         u32 id;
 353         u32 revision;
 354         u32 reset_delay_us;
 355         u16 autoneg_advertised;
 356 };
 357 
 358 /*!
 359  * @ingroup Gigabit Ether driver Layer
 360  * @struct  pch_gbe_hw
 361  * @brief   Hardware information
 362  */
 363 struct pch_gbe_hw {
 364         void *back;
 365 
 366         struct pch_gbe_regs  __iomem *reg;
 367         spinlock_t miim_lock;
 368 
 369         struct pch_gbe_mac_info mac;
 370         struct pch_gbe_phy_info phy;
 371 };
 372 
 373 /**
 374  * struct pch_gbe_rx_desc - Receive Descriptor
 375  * @buffer_addr:        RX Frame Buffer Address
 376  * @tcp_ip_status:      TCP/IP Accelerator Status
 377  * @rx_words_eob:       RX word count and Byte position
 378  * @gbec_status:        GMAC Status
 379  * @dma_status:         DMA Status
 380  * @reserved1:          Reserved
 381  * @reserved2:          Reserved
 382  */
 383 struct pch_gbe_rx_desc {
 384         u32 buffer_addr;
 385         u32 tcp_ip_status;
 386         u16 rx_words_eob;
 387         u16 gbec_status;
 388         u8 dma_status;
 389         u8 reserved1;
 390         u16 reserved2;
 391 };
 392 
 393 /**
 394  * struct pch_gbe_tx_desc - Transmit Descriptor
 395  * @buffer_addr:        TX Frame Buffer Address
 396  * @length:             Data buffer length
 397  * @reserved1:          Reserved
 398  * @tx_words_eob:       TX word count and Byte position
 399  * @tx_frame_ctrl:      TX Frame Control
 400  * @dma_status:         DMA Status
 401  * @reserved2:          Reserved
 402  * @gbec_status:        GMAC Status
 403  */
 404 struct pch_gbe_tx_desc {
 405         u32 buffer_addr;
 406         u16 length;
 407         u16 reserved1;
 408         u16 tx_words_eob;
 409         u16 tx_frame_ctrl;
 410         u8 dma_status;
 411         u8 reserved2;
 412         u16 gbec_status;
 413 };
 414 
 415 
 416 /**
 417  * struct pch_gbe_buffer - Buffer information
 418  * @skb:        pointer to a socket buffer
 419  * @dma:        DMA address
 420  * @time_stamp: time stamp
 421  * @length:     data size
 422  */
 423 struct pch_gbe_buffer {
 424         struct sk_buff *skb;
 425         dma_addr_t dma;
 426         unsigned char *rx_buffer;
 427         unsigned long time_stamp;
 428         u16 length;
 429         bool mapped;
 430 };
 431 
 432 /**
 433  * struct pch_gbe_tx_ring - tx ring information
 434  * @desc:       pointer to the descriptor ring memory
 435  * @dma:        physical address of the descriptor ring
 436  * @size:       length of descriptor ring in bytes
 437  * @count:      number of descriptors in the ring
 438  * @next_to_use:        next descriptor to associate a buffer with
 439  * @next_to_clean:      next descriptor to check for DD status bit
 440  * @buffer_info:        array of buffer information structs
 441  */
 442 struct pch_gbe_tx_ring {
 443         struct pch_gbe_tx_desc *desc;
 444         dma_addr_t dma;
 445         unsigned int size;
 446         unsigned int count;
 447         unsigned int next_to_use;
 448         unsigned int next_to_clean;
 449         struct pch_gbe_buffer *buffer_info;
 450 };
 451 
 452 /**
 453  * struct pch_gbe_rx_ring - rx ring information
 454  * @desc:       pointer to the descriptor ring memory
 455  * @dma:        physical address of the descriptor ring
 456  * @size:       length of descriptor ring in bytes
 457  * @count:      number of descriptors in the ring
 458  * @next_to_use:        next descriptor to associate a buffer with
 459  * @next_to_clean:      next descriptor to check for DD status bit
 460  * @buffer_info:        array of buffer information structs
 461  */
 462 struct pch_gbe_rx_ring {
 463         struct pch_gbe_rx_desc *desc;
 464         dma_addr_t dma;
 465         unsigned char *rx_buff_pool;
 466         dma_addr_t rx_buff_pool_logic;
 467         unsigned int rx_buff_pool_size;
 468         unsigned int size;
 469         unsigned int count;
 470         unsigned int next_to_use;
 471         unsigned int next_to_clean;
 472         struct pch_gbe_buffer *buffer_info;
 473 };
 474 
 475 /**
 476  * struct pch_gbe_hw_stats - Statistics counters collected by the MAC
 477  * @rx_packets:             total packets received
 478  * @tx_packets:             total packets transmitted
 479  * @rx_bytes:               total bytes received
 480  * @tx_bytes:               total bytes transmitted
 481  * @rx_errors:              bad packets received
 482  * @tx_errors:              packet transmit problems
 483  * @rx_dropped:             no space in Linux buffers
 484  * @tx_dropped:             no space available in Linux
 485  * @multicast:              multicast packets received
 486  * @collisions:             collisions
 487  * @rx_crc_errors:          received packet with crc error
 488  * @rx_frame_errors:        received frame alignment error
 489  * @rx_alloc_buff_failed:   allocate failure of a receive buffer
 490  * @tx_length_errors:       transmit length error
 491  * @tx_aborted_errors:      transmit aborted error
 492  * @tx_carrier_errors:      transmit carrier error
 493  * @tx_timeout_count:       Number of transmit timeout
 494  * @tx_restart_count:       Number of transmit restert
 495  * @intr_rx_dsc_empty_count:    Interrupt count of receive descriptor empty
 496  * @intr_rx_frame_err_count:    Interrupt count of receive frame error
 497  * @intr_rx_fifo_err_count:     Interrupt count of receive FIFO error
 498  * @intr_rx_dma_err_count:      Interrupt count of receive DMA error
 499  * @intr_tx_fifo_err_count:     Interrupt count of transmit FIFO error
 500  * @intr_tx_dma_err_count:      Interrupt count of transmit DMA error
 501  * @intr_tcpip_err_count:       Interrupt count of TCP/IP Accelerator
 502  */
 503 struct pch_gbe_hw_stats {
 504         u32 rx_packets;
 505         u32 tx_packets;
 506         u32 rx_bytes;
 507         u32 tx_bytes;
 508         u32 rx_errors;
 509         u32 tx_errors;
 510         u32 rx_dropped;
 511         u32 tx_dropped;
 512         u32 multicast;
 513         u32 collisions;
 514         u32 rx_crc_errors;
 515         u32 rx_frame_errors;
 516         u32 rx_alloc_buff_failed;
 517         u32 tx_length_errors;
 518         u32 tx_aborted_errors;
 519         u32 tx_carrier_errors;
 520         u32 tx_timeout_count;
 521         u32 tx_restart_count;
 522         u32 intr_rx_dsc_empty_count;
 523         u32 intr_rx_frame_err_count;
 524         u32 intr_rx_fifo_err_count;
 525         u32 intr_rx_dma_err_count;
 526         u32 intr_tx_fifo_err_count;
 527         u32 intr_tx_dma_err_count;
 528         u32 intr_tcpip_err_count;
 529 };
 530 
 531 /**
 532  * struct pch_gbe_privdata - PCI Device ID driver data
 533  * @phy_tx_clk_delay:           Bool, configure the PHY TX delay in software
 534  * @phy_disable_hibernate:      Bool, disable PHY hibernation
 535  * @platform_init:              Platform initialization callback, called from
 536  *                              probe, prior to PHY initialization.
 537  */
 538 struct pch_gbe_privdata {
 539         bool phy_tx_clk_delay;
 540         bool phy_disable_hibernate;
 541         int (*platform_init)(struct pci_dev *pdev);
 542 };
 543 
 544 /**
 545  * struct pch_gbe_adapter - board specific private data structure
 546  * @stats_lock: Spinlock structure for status
 547  * @ethtool_lock:       Spinlock structure for ethtool
 548  * @irq_sem:            Semaphore for interrupt
 549  * @netdev:             Pointer of network device structure
 550  * @pdev:               Pointer of pci device structure
 551  * @polling_netdev:     Pointer of polling network device structure
 552  * @napi:               NAPI structure
 553  * @hw:                 Pointer of hardware structure
 554  * @stats:              Hardware status
 555  * @reset_task:         Reset task
 556  * @mii:                MII information structure
 557  * @watchdog_timer:     Watchdog timer list
 558  * @wake_up_evt:        Wake up event
 559  * @config_space:       Configuration space
 560  * @msg_enable:         Driver message level
 561  * @led_status:         LED status
 562  * @tx_ring:            Pointer of Tx descriptor ring structure
 563  * @rx_ring:            Pointer of Rx descriptor ring structure
 564  * @rx_buffer_len:      Receive buffer length
 565  * @tx_queue_len:       Transmit queue length
 566  * @pch_gbe_privdata:   PCI Device ID driver_data
 567  */
 568 
 569 struct pch_gbe_adapter {
 570         spinlock_t stats_lock;
 571         spinlock_t ethtool_lock;
 572         atomic_t irq_sem;
 573         struct net_device *netdev;
 574         struct pci_dev *pdev;
 575         int irq;
 576         struct net_device *polling_netdev;
 577         struct napi_struct napi;
 578         struct pch_gbe_hw hw;
 579         struct pch_gbe_hw_stats stats;
 580         struct work_struct reset_task;
 581         struct mii_if_info mii;
 582         struct timer_list watchdog_timer;
 583         u32 wake_up_evt;
 584         u32 *config_space;
 585         unsigned long led_status;
 586         struct pch_gbe_tx_ring *tx_ring;
 587         struct pch_gbe_rx_ring *rx_ring;
 588         unsigned long rx_buffer_len;
 589         unsigned long tx_queue_len;
 590         bool rx_stop_flag;
 591         int hwts_tx_en;
 592         int hwts_rx_en;
 593         struct pci_dev *ptp_pdev;
 594         struct pch_gbe_privdata *pdata;
 595 };
 596 
 597 #define pch_gbe_hw_to_adapter(hw)       container_of(hw, struct pch_gbe_adapter, hw)
 598 
 599 extern const char pch_driver_version[];
 600 
 601 /* pch_gbe_main.c */
 602 int pch_gbe_up(struct pch_gbe_adapter *adapter);
 603 void pch_gbe_down(struct pch_gbe_adapter *adapter);
 604 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter);
 605 void pch_gbe_reset(struct pch_gbe_adapter *adapter);
 606 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
 607                                struct pch_gbe_tx_ring *txdr);
 608 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
 609                                struct pch_gbe_rx_ring *rxdr);
 610 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
 611                                struct pch_gbe_tx_ring *tx_ring);
 612 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
 613                                struct pch_gbe_rx_ring *rx_ring);
 614 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter);
 615 u32 pch_ch_control_read(struct pci_dev *pdev);
 616 void pch_ch_control_write(struct pci_dev *pdev, u32 val);
 617 u32 pch_ch_event_read(struct pci_dev *pdev);
 618 void pch_ch_event_write(struct pci_dev *pdev, u32 val);
 619 u32 pch_src_uuid_lo_read(struct pci_dev *pdev);
 620 u32 pch_src_uuid_hi_read(struct pci_dev *pdev);
 621 u64 pch_rx_snap_read(struct pci_dev *pdev);
 622 u64 pch_tx_snap_read(struct pci_dev *pdev);
 623 int pch_set_station_address(u8 *addr, struct pci_dev *pdev);
 624 
 625 /* pch_gbe_param.c */
 626 void pch_gbe_check_options(struct pch_gbe_adapter *adapter);
 627 
 628 /* pch_gbe_ethtool.c */
 629 void pch_gbe_set_ethtool_ops(struct net_device *netdev);
 630 
 631 /* pch_gbe_mac.c */
 632 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw);
 633 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
 634                           u16 data);
 635 #endif /* _PCH_GBE_H_ */