root/drivers/net/ethernet/silan/sc92031.c

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DEFINITIONS

This source file includes following definitions.
  1. _sc92031_dummy_read
  2. _sc92031_mii_wait
  3. _sc92031_mii_cmd
  4. _sc92031_mii_scan
  5. _sc92031_mii_read
  6. _sc92031_mii_write
  7. sc92031_disable_interrupts
  8. sc92031_enable_interrupts
  9. _sc92031_disable_tx_rx
  10. _sc92031_enable_tx_rx
  11. _sc92031_tx_clear
  12. _sc92031_set_mar
  13. _sc92031_set_rx_config
  14. _sc92031_check_media
  15. _sc92031_phy_reset
  16. _sc92031_reset
  17. _sc92031_tx_tasklet
  18. _sc92031_rx_tasklet_error
  19. _sc92031_rx_tasklet
  20. _sc92031_link_tasklet
  21. sc92031_tasklet
  22. sc92031_interrupt
  23. sc92031_get_stats
  24. sc92031_start_xmit
  25. sc92031_open
  26. sc92031_stop
  27. sc92031_set_multicast_list
  28. sc92031_tx_timeout
  29. sc92031_poll_controller
  30. sc92031_ethtool_get_link_ksettings
  31. sc92031_ethtool_set_link_ksettings
  32. sc92031_ethtool_get_wol
  33. sc92031_ethtool_set_wol
  34. sc92031_ethtool_nway_reset
  35. sc92031_ethtool_get_strings
  36. sc92031_ethtool_get_sset_count
  37. sc92031_ethtool_get_ethtool_stats
  38. sc92031_probe
  39. sc92031_remove
  40. sc92031_suspend
  41. sc92031_resume

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*  Silan SC92031 PCI Fast Ethernet Adapter driver
   3  *
   4  *  Based on vendor drivers:
   5  *  Silan Fast Ethernet Netcard Driver:
   6  *    MODULE_AUTHOR ("gaoyonghong");
   7  *    MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
   8  *    MODULE_LICENSE("GPL");
   9  *  8139D Fast Ethernet driver:
  10  *    (C) 2002 by gaoyonghong
  11  *    MODULE_AUTHOR ("gaoyonghong");
  12  *    MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
  13  *    MODULE_LICENSE("GPL");
  14  *  Both are almost identical and seem to be based on pci-skeleton.c
  15  *
  16  *  Rewritten for 2.6 by Cesar Eduardo Barros
  17  *
  18  *  A datasheet for this chip can be found at
  19  *  http://www.silan.com.cn/english/product/pdf/SC92031AY.pdf 
  20  */
  21 
  22 /* Note about set_mac_address: I don't know how to change the hardware
  23  * matching, so you need to enable IFF_PROMISC when using it.
  24  */
  25 
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/delay.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/crc32.h>
  37 
  38 #include <asm/irq.h>
  39 
  40 #define SC92031_NAME "sc92031"
  41 
  42 /* BAR 0 is MMIO, BAR 1 is PIO */
  43 #define SC92031_USE_PIO 0
  44 
  45 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
  46 static int multicast_filter_limit = 64;
  47 module_param(multicast_filter_limit, int, 0);
  48 MODULE_PARM_DESC(multicast_filter_limit,
  49         "Maximum number of filtered multicast addresses");
  50 
  51 static int media;
  52 module_param(media, int, 0);
  53 MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
  54         " 0x01 = 10M half, 0x02 = 10M full,"
  55         " 0x04 = 100M half, 0x08 = 100M full)");
  56 
  57 /* Size of the in-memory receive ring. */
  58 #define  RX_BUF_LEN_IDX  3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
  59 #define  RX_BUF_LEN     (8192 << RX_BUF_LEN_IDX)
  60 
  61 /* Number of Tx descriptor registers. */
  62 #define  NUM_TX_DESC       4
  63 
  64 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
  65 #define  MAX_ETH_FRAME_SIZE       1536
  66 
  67 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
  68 #define  TX_BUF_SIZE       MAX_ETH_FRAME_SIZE
  69 #define  TX_BUF_TOT_LEN    (TX_BUF_SIZE * NUM_TX_DESC)
  70 
  71 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */
  72 #define  RX_FIFO_THRESH    7     /* Rx buffer level before first PCI xfer.  */
  73 
  74 /* Time in jiffies before concluding the transmitter is hung. */
  75 #define  TX_TIMEOUT     (4*HZ)
  76 
  77 #define  SILAN_STATS_NUM    2    /* number of ETHTOOL_GSTATS */
  78 
  79 /* media options */
  80 #define  AUTOSELECT    0x00
  81 #define  M10_HALF      0x01
  82 #define  M10_FULL      0x02
  83 #define  M100_HALF     0x04
  84 #define  M100_FULL     0x08
  85 
  86  /* Symbolic offsets to registers. */
  87 enum  silan_registers {
  88    Config0    = 0x00,         // Config0
  89    Config1    = 0x04,         // Config1
  90    RxBufWPtr  = 0x08,         // Rx buffer writer poiter
  91    IntrStatus = 0x0C,         // Interrupt status
  92    IntrMask   = 0x10,         // Interrupt mask
  93    RxbufAddr  = 0x14,         // Rx buffer start address
  94    RxBufRPtr  = 0x18,         // Rx buffer read pointer
  95    Txstatusall = 0x1C,        // Transmit status of all descriptors
  96    TxStatus0  = 0x20,         // Transmit status (Four 32bit registers).
  97    TxAddr0    = 0x30,         // Tx descriptors (also four 32bit).
  98    RxConfig   = 0x40,         // Rx configuration
  99    MAC0       = 0x44,         // Ethernet hardware address.
 100    MAR0       = 0x4C,         // Multicast filter.
 101    RxStatus0  = 0x54,         // Rx status
 102    TxConfig   = 0x5C,         // Tx configuration
 103    PhyCtrl    = 0x60,         // physical control
 104    FlowCtrlConfig = 0x64,     // flow control
 105    Miicmd0    = 0x68,         // Mii command0 register
 106    Miicmd1    = 0x6C,         // Mii command1 register
 107    Miistatus  = 0x70,         // Mii status register
 108    Timercnt   = 0x74,         // Timer counter register
 109    TimerIntr  = 0x78,         // Timer interrupt register
 110    PMConfig   = 0x7C,         // Power Manager configuration
 111    CRC0       = 0x80,         // Power Manager CRC ( Two 32bit regisers)
 112    Wakeup0    = 0x88,         // power Manager wakeup( Eight 64bit regiser)
 113    LSBCRC0    = 0xC8,         // power Manager LSBCRC(Two 32bit regiser)
 114    TestD0     = 0xD0,
 115    TestD4     = 0xD4,
 116    TestD8     = 0xD8,
 117 };
 118 
 119 #define MII_JAB             16
 120 #define MII_OutputStatus    24
 121 
 122 #define PHY_16_JAB_ENB      0x1000
 123 #define PHY_16_PORT_ENB     0x1
 124 
 125 enum IntrStatusBits {
 126    LinkFail       = 0x80000000,
 127    LinkOK         = 0x40000000,
 128    TimeOut        = 0x20000000,
 129    RxOverflow     = 0x0040,
 130    RxOK           = 0x0020,
 131    TxOK           = 0x0001,
 132    IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
 133 };
 134 
 135 enum TxStatusBits {
 136    TxCarrierLost = 0x20000000,
 137    TxAborted     = 0x10000000,
 138    TxOutOfWindow = 0x08000000,
 139    TxNccShift    = 22,
 140    EarlyTxThresShift = 16,
 141    TxStatOK      = 0x8000,
 142    TxUnderrun    = 0x4000,
 143    TxOwn         = 0x2000,
 144 };
 145 
 146 enum RxStatusBits {
 147    RxStatesOK   = 0x80000,
 148    RxBadAlign   = 0x40000,
 149    RxHugeFrame  = 0x20000,
 150    RxSmallFrame = 0x10000,
 151    RxCRCOK      = 0x8000,
 152    RxCrlFrame   = 0x4000,
 153    Rx_Broadcast = 0x2000,
 154    Rx_Multicast = 0x1000,
 155    RxAddrMatch  = 0x0800,
 156    MiiErr       = 0x0400,
 157 };
 158 
 159 enum RxConfigBits {
 160    RxFullDx    = 0x80000000,
 161    RxEnb       = 0x40000000,
 162    RxSmall     = 0x20000000,
 163    RxHuge      = 0x10000000,
 164    RxErr       = 0x08000000,
 165    RxAllphys   = 0x04000000,
 166    RxMulticast = 0x02000000,
 167    RxBroadcast = 0x01000000,
 168    RxLoopBack  = (1 << 23) | (1 << 22),
 169    LowThresholdShift  = 12,
 170    HighThresholdShift = 2,
 171 };
 172 
 173 enum TxConfigBits {
 174    TxFullDx       = 0x80000000,
 175    TxEnb          = 0x40000000,
 176    TxEnbPad       = 0x20000000,
 177    TxEnbHuge      = 0x10000000,
 178    TxEnbFCS       = 0x08000000,
 179    TxNoBackOff    = 0x04000000,
 180    TxEnbPrem      = 0x02000000,
 181    TxCareLostCrs  = 0x1000000,
 182    TxExdCollNum   = 0xf00000,
 183    TxDataRate     = 0x80000,
 184 };
 185 
 186 enum PhyCtrlconfigbits {
 187    PhyCtrlAne         = 0x80000000,
 188    PhyCtrlSpd100      = 0x40000000,
 189    PhyCtrlSpd10       = 0x20000000,
 190    PhyCtrlPhyBaseAddr = 0x1f000000,
 191    PhyCtrlDux         = 0x800000,
 192    PhyCtrlReset       = 0x400000,
 193 };
 194 
 195 enum FlowCtrlConfigBits {
 196    FlowCtrlFullDX = 0x80000000,
 197    FlowCtrlEnb    = 0x40000000,
 198 };
 199 
 200 enum Config0Bits {
 201    Cfg0_Reset  = 0x80000000,
 202    Cfg0_Anaoff = 0x40000000,
 203    Cfg0_LDPS   = 0x20000000,
 204 };
 205 
 206 enum Config1Bits {
 207    Cfg1_EarlyRx = 1 << 31,
 208    Cfg1_EarlyTx = 1 << 30,
 209 
 210    //rx buffer size
 211    Cfg1_Rcv8K   = 0x0,
 212    Cfg1_Rcv16K  = 0x1,
 213    Cfg1_Rcv32K  = 0x3,
 214    Cfg1_Rcv64K  = 0x7,
 215    Cfg1_Rcv128K = 0xf,
 216 };
 217 
 218 enum MiiCmd0Bits {
 219    Mii_Divider = 0x20000000,
 220    Mii_WRITE   = 0x400000,
 221    Mii_READ    = 0x200000,
 222    Mii_SCAN    = 0x100000,
 223    Mii_Tamod   = 0x80000,
 224    Mii_Drvmod  = 0x40000,
 225    Mii_mdc     = 0x20000,
 226    Mii_mdoen   = 0x10000,
 227    Mii_mdo     = 0x8000,
 228    Mii_mdi     = 0x4000,
 229 };
 230 
 231 enum MiiStatusBits {
 232     Mii_StatusBusy = 0x80000000,
 233 };
 234 
 235 enum PMConfigBits {
 236    PM_Enable  = 1 << 31,
 237    PM_LongWF  = 1 << 30,
 238    PM_Magic   = 1 << 29,
 239    PM_LANWake = 1 << 28,
 240    PM_LWPTN   = (1 << 27 | 1<< 26),
 241    PM_LinkUp  = 1 << 25,
 242    PM_WakeUp  = 1 << 24,
 243 };
 244 
 245 /* Locking rules:
 246  * priv->lock protects most of the fields of priv and most of the
 247  * hardware registers. It does not have to protect against softirqs
 248  * between sc92031_disable_interrupts and sc92031_enable_interrupts;
 249  * it also does not need to be used in ->open and ->stop while the
 250  * device interrupts are off.
 251  * Not having to protect against softirqs is very useful due to heavy
 252  * use of mdelay() at _sc92031_reset.
 253  * Functions prefixed with _sc92031_ must be called with the lock held;
 254  * functions prefixed with sc92031_ must be called without the lock held.
 255  */
 256 
 257 /* Locking rules for the interrupt:
 258  * - the interrupt and the tasklet never run at the same time
 259  * - neither run between sc92031_disable_interrupts and
 260  *   sc92031_enable_interrupt
 261  */
 262 
 263 struct sc92031_priv {
 264         spinlock_t              lock;
 265         /* iomap.h cookie */
 266         void __iomem            *port_base;
 267         /* pci device structure */
 268         struct pci_dev          *pdev;
 269         /* tasklet */
 270         struct tasklet_struct   tasklet;
 271 
 272         /* CPU address of rx ring */
 273         void                    *rx_ring;
 274         /* PCI address of rx ring */
 275         dma_addr_t              rx_ring_dma_addr;
 276         /* PCI address of rx ring read pointer */
 277         dma_addr_t              rx_ring_tail;
 278 
 279         /* tx ring write index */
 280         unsigned                tx_head;
 281         /* tx ring read index */
 282         unsigned                tx_tail;
 283         /* CPU address of tx bounce buffer */
 284         void                    *tx_bufs;
 285         /* PCI address of tx bounce buffer */
 286         dma_addr_t              tx_bufs_dma_addr;
 287 
 288         /* copies of some hardware registers */
 289         u32                     intr_status;
 290         atomic_t                intr_mask;
 291         u32                     rx_config;
 292         u32                     tx_config;
 293         u32                     pm_config;
 294 
 295         /* copy of some flags from dev->flags */
 296         unsigned int            mc_flags;
 297 
 298         /* for ETHTOOL_GSTATS */
 299         u64                     tx_timeouts;
 300         u64                     rx_loss;
 301 
 302         /* for dev->get_stats */
 303         long                    rx_value;
 304 };
 305 
 306 /* I don't know which registers can be safely read; however, I can guess
 307  * MAC0 is one of them. */
 308 static inline void _sc92031_dummy_read(void __iomem *port_base)
 309 {
 310         ioread32(port_base + MAC0);
 311 }
 312 
 313 static u32 _sc92031_mii_wait(void __iomem *port_base)
 314 {
 315         u32 mii_status;
 316 
 317         do {
 318                 udelay(10);
 319                 mii_status = ioread32(port_base + Miistatus);
 320         } while (mii_status & Mii_StatusBusy);
 321 
 322         return mii_status;
 323 }
 324 
 325 static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
 326 {
 327         iowrite32(Mii_Divider, port_base + Miicmd0);
 328 
 329         _sc92031_mii_wait(port_base);
 330 
 331         iowrite32(cmd1, port_base + Miicmd1);
 332         iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
 333 
 334         return _sc92031_mii_wait(port_base);
 335 }
 336 
 337 static void _sc92031_mii_scan(void __iomem *port_base)
 338 {
 339         _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
 340 }
 341 
 342 static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
 343 {
 344         return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
 345 }
 346 
 347 static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
 348 {
 349         _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
 350 }
 351 
 352 static void sc92031_disable_interrupts(struct net_device *dev)
 353 {
 354         struct sc92031_priv *priv = netdev_priv(dev);
 355         void __iomem *port_base = priv->port_base;
 356 
 357         /* tell the tasklet/interrupt not to enable interrupts */
 358         atomic_set(&priv->intr_mask, 0);
 359         wmb();
 360 
 361         /* stop interrupts */
 362         iowrite32(0, port_base + IntrMask);
 363         _sc92031_dummy_read(port_base);
 364 
 365         /* wait for any concurrent interrupt/tasklet to finish */
 366         synchronize_irq(priv->pdev->irq);
 367         tasklet_disable(&priv->tasklet);
 368 }
 369 
 370 static void sc92031_enable_interrupts(struct net_device *dev)
 371 {
 372         struct sc92031_priv *priv = netdev_priv(dev);
 373         void __iomem *port_base = priv->port_base;
 374 
 375         tasklet_enable(&priv->tasklet);
 376 
 377         atomic_set(&priv->intr_mask, IntrBits);
 378         wmb();
 379 
 380         iowrite32(IntrBits, port_base + IntrMask);
 381 }
 382 
 383 static void _sc92031_disable_tx_rx(struct net_device *dev)
 384 {
 385         struct sc92031_priv *priv = netdev_priv(dev);
 386         void __iomem *port_base = priv->port_base;
 387 
 388         priv->rx_config &= ~RxEnb;
 389         priv->tx_config &= ~TxEnb;
 390         iowrite32(priv->rx_config, port_base + RxConfig);
 391         iowrite32(priv->tx_config, port_base + TxConfig);
 392 }
 393 
 394 static void _sc92031_enable_tx_rx(struct net_device *dev)
 395 {
 396         struct sc92031_priv *priv = netdev_priv(dev);
 397         void __iomem *port_base = priv->port_base;
 398 
 399         priv->rx_config |= RxEnb;
 400         priv->tx_config |= TxEnb;
 401         iowrite32(priv->rx_config, port_base + RxConfig);
 402         iowrite32(priv->tx_config, port_base + TxConfig);
 403 }
 404 
 405 static void _sc92031_tx_clear(struct net_device *dev)
 406 {
 407         struct sc92031_priv *priv = netdev_priv(dev);
 408 
 409         while (priv->tx_head - priv->tx_tail > 0) {
 410                 priv->tx_tail++;
 411                 dev->stats.tx_dropped++;
 412         }
 413         priv->tx_head = priv->tx_tail = 0;
 414 }
 415 
 416 static void _sc92031_set_mar(struct net_device *dev)
 417 {
 418         struct sc92031_priv *priv = netdev_priv(dev);
 419         void __iomem *port_base = priv->port_base;
 420         u32 mar0 = 0, mar1 = 0;
 421 
 422         if ((dev->flags & IFF_PROMISC) ||
 423             netdev_mc_count(dev) > multicast_filter_limit ||
 424             (dev->flags & IFF_ALLMULTI))
 425                 mar0 = mar1 = 0xffffffff;
 426         else if (dev->flags & IFF_MULTICAST) {
 427                 struct netdev_hw_addr *ha;
 428 
 429                 netdev_for_each_mc_addr(ha, dev) {
 430                         u32 crc;
 431                         unsigned bit = 0;
 432 
 433                         crc = ~ether_crc(ETH_ALEN, ha->addr);
 434                         crc >>= 24;
 435 
 436                         if (crc & 0x01) bit |= 0x02;
 437                         if (crc & 0x02) bit |= 0x01;
 438                         if (crc & 0x10) bit |= 0x20;
 439                         if (crc & 0x20) bit |= 0x10;
 440                         if (crc & 0x40) bit |= 0x08;
 441                         if (crc & 0x80) bit |= 0x04;
 442 
 443                         if (bit > 31)
 444                                 mar0 |= 0x1 << (bit - 32);
 445                         else
 446                                 mar1 |= 0x1 << bit;
 447                 }
 448         }
 449 
 450         iowrite32(mar0, port_base + MAR0);
 451         iowrite32(mar1, port_base + MAR0 + 4);
 452 }
 453 
 454 static void _sc92031_set_rx_config(struct net_device *dev)
 455 {
 456         struct sc92031_priv *priv = netdev_priv(dev);
 457         void __iomem *port_base = priv->port_base;
 458         unsigned int old_mc_flags;
 459         u32 rx_config_bits = 0;
 460 
 461         old_mc_flags = priv->mc_flags;
 462 
 463         if (dev->flags & IFF_PROMISC)
 464                 rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
 465                                 | RxMulticast | RxAllphys;
 466 
 467         if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
 468                 rx_config_bits |= RxMulticast;
 469 
 470         if (dev->flags & IFF_BROADCAST)
 471                 rx_config_bits |= RxBroadcast;
 472 
 473         priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
 474                         | RxMulticast | RxAllphys);
 475         priv->rx_config |= rx_config_bits;
 476 
 477         priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
 478                         | IFF_MULTICAST | IFF_BROADCAST);
 479 
 480         if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
 481                 iowrite32(priv->rx_config, port_base + RxConfig);
 482 }
 483 
 484 static bool _sc92031_check_media(struct net_device *dev)
 485 {
 486         struct sc92031_priv *priv = netdev_priv(dev);
 487         void __iomem *port_base = priv->port_base;
 488         u16 bmsr;
 489 
 490         bmsr = _sc92031_mii_read(port_base, MII_BMSR);
 491         rmb();
 492         if (bmsr & BMSR_LSTATUS) {
 493                 bool speed_100, duplex_full;
 494                 u32 flow_ctrl_config = 0;
 495                 u16 output_status = _sc92031_mii_read(port_base,
 496                                 MII_OutputStatus);
 497                 _sc92031_mii_scan(port_base);
 498 
 499                 speed_100 = output_status & 0x2;
 500                 duplex_full = output_status & 0x4;
 501 
 502                 /* Initial Tx/Rx configuration */
 503                 priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
 504                 priv->tx_config = 0x48800000;
 505 
 506                 /* NOTE: vendor driver had dead code here to enable tx padding */
 507 
 508                 if (!speed_100)
 509                         priv->tx_config |= 0x80000;
 510 
 511                 // configure rx mode
 512                 _sc92031_set_rx_config(dev);
 513 
 514                 if (duplex_full) {
 515                         priv->rx_config |= RxFullDx;
 516                         priv->tx_config |= TxFullDx;
 517                         flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
 518                 } else {
 519                         priv->rx_config &= ~RxFullDx;
 520                         priv->tx_config &= ~TxFullDx;
 521                 }
 522 
 523                 _sc92031_set_mar(dev);
 524                 _sc92031_set_rx_config(dev);
 525                 _sc92031_enable_tx_rx(dev);
 526                 iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
 527 
 528                 netif_carrier_on(dev);
 529 
 530                 if (printk_ratelimit())
 531                         printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
 532                                 dev->name,
 533                                 speed_100 ? "100" : "10",
 534                                 duplex_full ? "full" : "half");
 535                 return true;
 536         } else {
 537                 _sc92031_mii_scan(port_base);
 538 
 539                 netif_carrier_off(dev);
 540 
 541                 _sc92031_disable_tx_rx(dev);
 542 
 543                 if (printk_ratelimit())
 544                         printk(KERN_INFO "%s: link down\n", dev->name);
 545                 return false;
 546         }
 547 }
 548 
 549 static void _sc92031_phy_reset(struct net_device *dev)
 550 {
 551         struct sc92031_priv *priv = netdev_priv(dev);
 552         void __iomem *port_base = priv->port_base;
 553         u32 phy_ctrl;
 554 
 555         phy_ctrl = ioread32(port_base + PhyCtrl);
 556         phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
 557         phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
 558 
 559         switch (media) {
 560         default:
 561         case AUTOSELECT:
 562                 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
 563                 break;
 564         case M10_HALF:
 565                 phy_ctrl |= PhyCtrlSpd10;
 566                 break;
 567         case M10_FULL:
 568                 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
 569                 break;
 570         case M100_HALF:
 571                 phy_ctrl |= PhyCtrlSpd100;
 572                 break;
 573         case M100_FULL:
 574                 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
 575                 break;
 576         }
 577 
 578         iowrite32(phy_ctrl, port_base + PhyCtrl);
 579         mdelay(10);
 580 
 581         phy_ctrl &= ~PhyCtrlReset;
 582         iowrite32(phy_ctrl, port_base + PhyCtrl);
 583         mdelay(1);
 584 
 585         _sc92031_mii_write(port_base, MII_JAB,
 586                         PHY_16_JAB_ENB | PHY_16_PORT_ENB);
 587         _sc92031_mii_scan(port_base);
 588 
 589         netif_carrier_off(dev);
 590         netif_stop_queue(dev);
 591 }
 592 
 593 static void _sc92031_reset(struct net_device *dev)
 594 {
 595         struct sc92031_priv *priv = netdev_priv(dev);
 596         void __iomem *port_base = priv->port_base;
 597 
 598         /* disable PM */
 599         iowrite32(0, port_base + PMConfig);
 600 
 601         /* soft reset the chip */
 602         iowrite32(Cfg0_Reset, port_base + Config0);
 603         mdelay(200);
 604 
 605         iowrite32(0, port_base + Config0);
 606         mdelay(10);
 607 
 608         /* disable interrupts */
 609         iowrite32(0, port_base + IntrMask);
 610 
 611         /* clear multicast address */
 612         iowrite32(0, port_base + MAR0);
 613         iowrite32(0, port_base + MAR0 + 4);
 614 
 615         /* init rx ring */
 616         iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
 617         priv->rx_ring_tail = priv->rx_ring_dma_addr;
 618 
 619         /* init tx ring */
 620         _sc92031_tx_clear(dev);
 621 
 622         /* clear old register values */
 623         priv->intr_status = 0;
 624         atomic_set(&priv->intr_mask, 0);
 625         priv->rx_config = 0;
 626         priv->tx_config = 0;
 627         priv->mc_flags = 0;
 628 
 629         /* configure rx buffer size */
 630         /* NOTE: vendor driver had dead code here to enable early tx/rx */
 631         iowrite32(Cfg1_Rcv64K, port_base + Config1);
 632 
 633         _sc92031_phy_reset(dev);
 634         _sc92031_check_media(dev);
 635 
 636         /* calculate rx fifo overflow */
 637         priv->rx_value = 0;
 638 
 639         /* enable PM */
 640         iowrite32(priv->pm_config, port_base + PMConfig);
 641 
 642         /* clear intr register */
 643         ioread32(port_base + IntrStatus);
 644 }
 645 
 646 static void _sc92031_tx_tasklet(struct net_device *dev)
 647 {
 648         struct sc92031_priv *priv = netdev_priv(dev);
 649         void __iomem *port_base = priv->port_base;
 650 
 651         unsigned old_tx_tail;
 652         unsigned entry;
 653         u32 tx_status;
 654 
 655         old_tx_tail = priv->tx_tail;
 656         while (priv->tx_head - priv->tx_tail > 0) {
 657                 entry = priv->tx_tail % NUM_TX_DESC;
 658                 tx_status = ioread32(port_base + TxStatus0 + entry * 4);
 659 
 660                 if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
 661                         break;
 662 
 663                 priv->tx_tail++;
 664 
 665                 if (tx_status & TxStatOK) {
 666                         dev->stats.tx_bytes += tx_status & 0x1fff;
 667                         dev->stats.tx_packets++;
 668                         /* Note: TxCarrierLost is always asserted at 100mbps. */
 669                         dev->stats.collisions += (tx_status >> 22) & 0xf;
 670                 }
 671 
 672                 if (tx_status & (TxOutOfWindow | TxAborted)) {
 673                         dev->stats.tx_errors++;
 674 
 675                         if (tx_status & TxAborted)
 676                                 dev->stats.tx_aborted_errors++;
 677 
 678                         if (tx_status & TxCarrierLost)
 679                                 dev->stats.tx_carrier_errors++;
 680 
 681                         if (tx_status & TxOutOfWindow)
 682                                 dev->stats.tx_window_errors++;
 683                 }
 684 
 685                 if (tx_status & TxUnderrun)
 686                         dev->stats.tx_fifo_errors++;
 687         }
 688 
 689         if (priv->tx_tail != old_tx_tail)
 690                 if (netif_queue_stopped(dev))
 691                         netif_wake_queue(dev);
 692 }
 693 
 694 static void _sc92031_rx_tasklet_error(struct net_device *dev,
 695                                       u32 rx_status, unsigned rx_size)
 696 {
 697         if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
 698                 dev->stats.rx_errors++;
 699                 dev->stats.rx_length_errors++;
 700         }
 701 
 702         if (!(rx_status & RxStatesOK)) {
 703                 dev->stats.rx_errors++;
 704 
 705                 if (rx_status & (RxHugeFrame | RxSmallFrame))
 706                         dev->stats.rx_length_errors++;
 707 
 708                 if (rx_status & RxBadAlign)
 709                         dev->stats.rx_frame_errors++;
 710 
 711                 if (!(rx_status & RxCRCOK))
 712                         dev->stats.rx_crc_errors++;
 713         } else {
 714                 struct sc92031_priv *priv = netdev_priv(dev);
 715                 priv->rx_loss++;
 716         }
 717 }
 718 
 719 static void _sc92031_rx_tasklet(struct net_device *dev)
 720 {
 721         struct sc92031_priv *priv = netdev_priv(dev);
 722         void __iomem *port_base = priv->port_base;
 723 
 724         dma_addr_t rx_ring_head;
 725         unsigned rx_len;
 726         unsigned rx_ring_offset;
 727         void *rx_ring = priv->rx_ring;
 728 
 729         rx_ring_head = ioread32(port_base + RxBufWPtr);
 730         rmb();
 731 
 732         /* rx_ring_head is only 17 bits in the RxBufWPtr register.
 733          * we need to change it to 32 bits physical address
 734          */
 735         rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
 736         rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
 737         if (rx_ring_head < priv->rx_ring_dma_addr)
 738                 rx_ring_head += RX_BUF_LEN;
 739 
 740         if (rx_ring_head >= priv->rx_ring_tail)
 741                 rx_len = rx_ring_head - priv->rx_ring_tail;
 742         else
 743                 rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
 744 
 745         if (!rx_len)
 746                 return;
 747 
 748         if (unlikely(rx_len > RX_BUF_LEN)) {
 749                 if (printk_ratelimit())
 750                         printk(KERN_ERR "%s: rx packets length > rx buffer\n",
 751                                         dev->name);
 752                 return;
 753         }
 754 
 755         rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
 756 
 757         while (rx_len) {
 758                 u32 rx_status;
 759                 unsigned rx_size, rx_size_align, pkt_size;
 760                 struct sk_buff *skb;
 761 
 762                 rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
 763                 rmb();
 764 
 765                 rx_size = rx_status >> 20;
 766                 rx_size_align = (rx_size + 3) & ~3;     // for 4 bytes aligned
 767                 pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
 768 
 769                 rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
 770 
 771                 if (unlikely(rx_status == 0 ||
 772                              rx_size > (MAX_ETH_FRAME_SIZE + 4) ||
 773                              rx_size < 16 ||
 774                              !(rx_status & RxStatesOK))) {
 775                         _sc92031_rx_tasklet_error(dev, rx_status, rx_size);
 776                         break;
 777                 }
 778 
 779                 if (unlikely(rx_size_align + 4 > rx_len)) {
 780                         if (printk_ratelimit())
 781                                 printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
 782                         break;
 783                 }
 784 
 785                 rx_len -= rx_size_align + 4;
 786 
 787                 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
 788                 if (unlikely(!skb)) {
 789                         if (printk_ratelimit())
 790                                 printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
 791                                                 dev->name, pkt_size);
 792                         goto next;
 793                 }
 794 
 795                 if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
 796                         skb_put_data(skb, rx_ring + rx_ring_offset,
 797                                      RX_BUF_LEN - rx_ring_offset);
 798                         skb_put_data(skb, rx_ring,
 799                                      pkt_size - (RX_BUF_LEN - rx_ring_offset));
 800                 } else {
 801                         skb_put_data(skb, rx_ring + rx_ring_offset, pkt_size);
 802                 }
 803 
 804                 skb->protocol = eth_type_trans(skb, dev);
 805                 netif_rx(skb);
 806 
 807                 dev->stats.rx_bytes += pkt_size;
 808                 dev->stats.rx_packets++;
 809 
 810                 if (rx_status & Rx_Multicast)
 811                         dev->stats.multicast++;
 812 
 813         next:
 814                 rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
 815         }
 816         mb();
 817 
 818         priv->rx_ring_tail = rx_ring_head;
 819         iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
 820 }
 821 
 822 static void _sc92031_link_tasklet(struct net_device *dev)
 823 {
 824         if (_sc92031_check_media(dev))
 825                 netif_wake_queue(dev);
 826         else {
 827                 netif_stop_queue(dev);
 828                 dev->stats.tx_carrier_errors++;
 829         }
 830 }
 831 
 832 static void sc92031_tasklet(unsigned long data)
 833 {
 834         struct net_device *dev = (struct net_device *)data;
 835         struct sc92031_priv *priv = netdev_priv(dev);
 836         void __iomem *port_base = priv->port_base;
 837         u32 intr_status, intr_mask;
 838 
 839         intr_status = priv->intr_status;
 840 
 841         spin_lock(&priv->lock);
 842 
 843         if (unlikely(!netif_running(dev)))
 844                 goto out;
 845 
 846         if (intr_status & TxOK)
 847                 _sc92031_tx_tasklet(dev);
 848 
 849         if (intr_status & RxOK)
 850                 _sc92031_rx_tasklet(dev);
 851 
 852         if (intr_status & RxOverflow)
 853                 dev->stats.rx_errors++;
 854 
 855         if (intr_status & TimeOut) {
 856                 dev->stats.rx_errors++;
 857                 dev->stats.rx_length_errors++;
 858         }
 859 
 860         if (intr_status & (LinkFail | LinkOK))
 861                 _sc92031_link_tasklet(dev);
 862 
 863 out:
 864         intr_mask = atomic_read(&priv->intr_mask);
 865         rmb();
 866 
 867         iowrite32(intr_mask, port_base + IntrMask);
 868 
 869         spin_unlock(&priv->lock);
 870 }
 871 
 872 static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
 873 {
 874         struct net_device *dev = dev_id;
 875         struct sc92031_priv *priv = netdev_priv(dev);
 876         void __iomem *port_base = priv->port_base;
 877         u32 intr_status, intr_mask;
 878 
 879         /* mask interrupts before clearing IntrStatus */
 880         iowrite32(0, port_base + IntrMask);
 881         _sc92031_dummy_read(port_base);
 882 
 883         intr_status = ioread32(port_base + IntrStatus);
 884         if (unlikely(intr_status == 0xffffffff))
 885                 return IRQ_NONE;        // hardware has gone missing
 886 
 887         intr_status &= IntrBits;
 888         if (!intr_status)
 889                 goto out_none;
 890 
 891         priv->intr_status = intr_status;
 892         tasklet_schedule(&priv->tasklet);
 893 
 894         return IRQ_HANDLED;
 895 
 896 out_none:
 897         intr_mask = atomic_read(&priv->intr_mask);
 898         rmb();
 899 
 900         iowrite32(intr_mask, port_base + IntrMask);
 901 
 902         return IRQ_NONE;
 903 }
 904 
 905 static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
 906 {
 907         struct sc92031_priv *priv = netdev_priv(dev);
 908         void __iomem *port_base = priv->port_base;
 909 
 910         // FIXME I do not understand what is this trying to do.
 911         if (netif_running(dev)) {
 912                 int temp;
 913 
 914                 spin_lock_bh(&priv->lock);
 915 
 916                 /* Update the error count. */
 917                 temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
 918 
 919                 if (temp == 0xffff) {
 920                         priv->rx_value += temp;
 921                         dev->stats.rx_fifo_errors = priv->rx_value;
 922                 } else
 923                         dev->stats.rx_fifo_errors = temp + priv->rx_value;
 924 
 925                 spin_unlock_bh(&priv->lock);
 926         }
 927 
 928         return &dev->stats;
 929 }
 930 
 931 static netdev_tx_t sc92031_start_xmit(struct sk_buff *skb,
 932                                       struct net_device *dev)
 933 {
 934         struct sc92031_priv *priv = netdev_priv(dev);
 935         void __iomem *port_base = priv->port_base;
 936         unsigned len;
 937         unsigned entry;
 938         u32 tx_status;
 939 
 940         if (unlikely(skb->len > TX_BUF_SIZE)) {
 941                 dev->stats.tx_dropped++;
 942                 goto out;
 943         }
 944 
 945         spin_lock(&priv->lock);
 946 
 947         if (unlikely(!netif_carrier_ok(dev))) {
 948                 dev->stats.tx_dropped++;
 949                 goto out_unlock;
 950         }
 951 
 952         BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
 953 
 954         entry = priv->tx_head++ % NUM_TX_DESC;
 955 
 956         skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
 957 
 958         len = skb->len;
 959         if (len < ETH_ZLEN) {
 960                 memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
 961                                 0, ETH_ZLEN - len);
 962                 len = ETH_ZLEN;
 963         }
 964 
 965         wmb();
 966 
 967         if (len < 100)
 968                 tx_status = len;
 969         else if (len < 300)
 970                 tx_status = 0x30000 | len;
 971         else
 972                 tx_status = 0x50000 | len;
 973 
 974         iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
 975                         port_base + TxAddr0 + entry * 4);
 976         iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
 977 
 978         if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
 979                 netif_stop_queue(dev);
 980 
 981 out_unlock:
 982         spin_unlock(&priv->lock);
 983 
 984 out:
 985         dev_consume_skb_any(skb);
 986 
 987         return NETDEV_TX_OK;
 988 }
 989 
 990 static int sc92031_open(struct net_device *dev)
 991 {
 992         int err;
 993         struct sc92031_priv *priv = netdev_priv(dev);
 994         struct pci_dev *pdev = priv->pdev;
 995 
 996         priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN,
 997                         &priv->rx_ring_dma_addr);
 998         if (unlikely(!priv->rx_ring)) {
 999                 err = -ENOMEM;
1000                 goto out_alloc_rx_ring;
1001         }
1002 
1003         priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN,
1004                         &priv->tx_bufs_dma_addr);
1005         if (unlikely(!priv->tx_bufs)) {
1006                 err = -ENOMEM;
1007                 goto out_alloc_tx_bufs;
1008         }
1009         priv->tx_head = priv->tx_tail = 0;
1010 
1011         err = request_irq(pdev->irq, sc92031_interrupt,
1012                         IRQF_SHARED, dev->name, dev);
1013         if (unlikely(err < 0))
1014                 goto out_request_irq;
1015 
1016         priv->pm_config = 0;
1017 
1018         /* Interrupts already disabled by sc92031_stop or sc92031_probe */
1019         spin_lock_bh(&priv->lock);
1020 
1021         _sc92031_reset(dev);
1022 
1023         spin_unlock_bh(&priv->lock);
1024         sc92031_enable_interrupts(dev);
1025 
1026         if (netif_carrier_ok(dev))
1027                 netif_start_queue(dev);
1028         else
1029                 netif_tx_disable(dev);
1030 
1031         return 0;
1032 
1033 out_request_irq:
1034         pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1035                         priv->tx_bufs_dma_addr);
1036 out_alloc_tx_bufs:
1037         pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1038                         priv->rx_ring_dma_addr);
1039 out_alloc_rx_ring:
1040         return err;
1041 }
1042 
1043 static int sc92031_stop(struct net_device *dev)
1044 {
1045         struct sc92031_priv *priv = netdev_priv(dev);
1046         struct pci_dev *pdev = priv->pdev;
1047 
1048         netif_tx_disable(dev);
1049 
1050         /* Disable interrupts, stop Tx and Rx. */
1051         sc92031_disable_interrupts(dev);
1052 
1053         spin_lock_bh(&priv->lock);
1054 
1055         _sc92031_disable_tx_rx(dev);
1056         _sc92031_tx_clear(dev);
1057 
1058         spin_unlock_bh(&priv->lock);
1059 
1060         free_irq(pdev->irq, dev);
1061         pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1062                         priv->tx_bufs_dma_addr);
1063         pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1064                         priv->rx_ring_dma_addr);
1065 
1066         return 0;
1067 }
1068 
1069 static void sc92031_set_multicast_list(struct net_device *dev)
1070 {
1071         struct sc92031_priv *priv = netdev_priv(dev);
1072 
1073         spin_lock_bh(&priv->lock);
1074 
1075         _sc92031_set_mar(dev);
1076         _sc92031_set_rx_config(dev);
1077 
1078         spin_unlock_bh(&priv->lock);
1079 }
1080 
1081 static void sc92031_tx_timeout(struct net_device *dev)
1082 {
1083         struct sc92031_priv *priv = netdev_priv(dev);
1084 
1085         /* Disable interrupts by clearing the interrupt mask.*/
1086         sc92031_disable_interrupts(dev);
1087 
1088         spin_lock(&priv->lock);
1089 
1090         priv->tx_timeouts++;
1091 
1092         _sc92031_reset(dev);
1093 
1094         spin_unlock(&priv->lock);
1095 
1096         /* enable interrupts */
1097         sc92031_enable_interrupts(dev);
1098 
1099         if (netif_carrier_ok(dev))
1100                 netif_wake_queue(dev);
1101 }
1102 
1103 #ifdef CONFIG_NET_POLL_CONTROLLER
1104 static void sc92031_poll_controller(struct net_device *dev)
1105 {
1106         struct sc92031_priv *priv = netdev_priv(dev);
1107         const int irq = priv->pdev->irq;
1108 
1109         disable_irq(irq);
1110         if (sc92031_interrupt(irq, dev) != IRQ_NONE)
1111                 sc92031_tasklet((unsigned long)dev);
1112         enable_irq(irq);
1113 }
1114 #endif
1115 
1116 static int
1117 sc92031_ethtool_get_link_ksettings(struct net_device *dev,
1118                                    struct ethtool_link_ksettings *cmd)
1119 {
1120         struct sc92031_priv *priv = netdev_priv(dev);
1121         void __iomem *port_base = priv->port_base;
1122         u8 phy_address;
1123         u32 phy_ctrl;
1124         u16 output_status;
1125         u32 supported, advertising;
1126 
1127         spin_lock_bh(&priv->lock);
1128 
1129         phy_address = ioread32(port_base + Miicmd1) >> 27;
1130         phy_ctrl = ioread32(port_base + PhyCtrl);
1131 
1132         output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1133         _sc92031_mii_scan(port_base);
1134 
1135         spin_unlock_bh(&priv->lock);
1136 
1137         supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
1138                         | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
1139                         | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
1140 
1141         advertising = ADVERTISED_TP | ADVERTISED_MII;
1142 
1143         if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1144                         == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1145                 advertising |= ADVERTISED_Autoneg;
1146 
1147         if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
1148                 advertising |= ADVERTISED_10baseT_Half;
1149 
1150         if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
1151                         == (PhyCtrlSpd10 | PhyCtrlDux))
1152                 advertising |= ADVERTISED_10baseT_Full;
1153 
1154         if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
1155                 advertising |= ADVERTISED_100baseT_Half;
1156 
1157         if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
1158                         == (PhyCtrlSpd100 | PhyCtrlDux))
1159                 advertising |= ADVERTISED_100baseT_Full;
1160 
1161         if (phy_ctrl & PhyCtrlAne)
1162                 advertising |= ADVERTISED_Autoneg;
1163 
1164         cmd->base.speed = (output_status & 0x2) ? SPEED_100 : SPEED_10;
1165         cmd->base.duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
1166         cmd->base.port = PORT_MII;
1167         cmd->base.phy_address = phy_address;
1168         cmd->base.autoneg = (phy_ctrl & PhyCtrlAne) ?
1169                 AUTONEG_ENABLE : AUTONEG_DISABLE;
1170 
1171         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1172                                                 supported);
1173         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1174                                                 advertising);
1175 
1176         return 0;
1177 }
1178 
1179 static int
1180 sc92031_ethtool_set_link_ksettings(struct net_device *dev,
1181                                    const struct ethtool_link_ksettings *cmd)
1182 {
1183         struct sc92031_priv *priv = netdev_priv(dev);
1184         void __iomem *port_base = priv->port_base;
1185         u32 speed = cmd->base.speed;
1186         u32 phy_ctrl;
1187         u32 old_phy_ctrl;
1188         u32 advertising;
1189 
1190         ethtool_convert_link_mode_to_legacy_u32(&advertising,
1191                                                 cmd->link_modes.advertising);
1192 
1193         if (!(speed == SPEED_10 || speed == SPEED_100))
1194                 return -EINVAL;
1195         if (!(cmd->base.duplex == DUPLEX_HALF ||
1196               cmd->base.duplex == DUPLEX_FULL))
1197                 return -EINVAL;
1198         if (!(cmd->base.port == PORT_MII))
1199                 return -EINVAL;
1200         if (!(cmd->base.phy_address == 0x1f))
1201                 return -EINVAL;
1202         if (!(cmd->base.autoneg == AUTONEG_DISABLE ||
1203               cmd->base.autoneg == AUTONEG_ENABLE))
1204                 return -EINVAL;
1205 
1206         if (cmd->base.autoneg == AUTONEG_ENABLE) {
1207                 if (!(advertising & (ADVERTISED_Autoneg
1208                                 | ADVERTISED_100baseT_Full
1209                                 | ADVERTISED_100baseT_Half
1210                                 | ADVERTISED_10baseT_Full
1211                                 | ADVERTISED_10baseT_Half)))
1212                         return -EINVAL;
1213 
1214                 phy_ctrl = PhyCtrlAne;
1215 
1216                 // FIXME: I'm not sure what the original code was trying to do
1217                 if (advertising & ADVERTISED_Autoneg)
1218                         phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
1219                 if (advertising & ADVERTISED_100baseT_Full)
1220                         phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
1221                 if (advertising & ADVERTISED_100baseT_Half)
1222                         phy_ctrl |= PhyCtrlSpd100;
1223                 if (advertising & ADVERTISED_10baseT_Full)
1224                         phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
1225                 if (advertising & ADVERTISED_10baseT_Half)
1226                         phy_ctrl |= PhyCtrlSpd10;
1227         } else {
1228                 // FIXME: Whole branch guessed
1229                 phy_ctrl = 0;
1230 
1231                 if (speed == SPEED_10)
1232                         phy_ctrl |= PhyCtrlSpd10;
1233                 else /* cmd->speed == SPEED_100 */
1234                         phy_ctrl |= PhyCtrlSpd100;
1235 
1236                 if (cmd->base.duplex == DUPLEX_FULL)
1237                         phy_ctrl |= PhyCtrlDux;
1238         }
1239 
1240         spin_lock_bh(&priv->lock);
1241 
1242         old_phy_ctrl = ioread32(port_base + PhyCtrl);
1243         phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
1244                         | PhyCtrlSpd100 | PhyCtrlSpd10);
1245         if (phy_ctrl != old_phy_ctrl)
1246                 iowrite32(phy_ctrl, port_base + PhyCtrl);
1247 
1248         spin_unlock_bh(&priv->lock);
1249 
1250         return 0;
1251 }
1252 
1253 static void sc92031_ethtool_get_wol(struct net_device *dev,
1254                 struct ethtool_wolinfo *wolinfo)
1255 {
1256         struct sc92031_priv *priv = netdev_priv(dev);
1257         void __iomem *port_base = priv->port_base;
1258         u32 pm_config;
1259 
1260         spin_lock_bh(&priv->lock);
1261         pm_config = ioread32(port_base + PMConfig);
1262         spin_unlock_bh(&priv->lock);
1263 
1264         // FIXME: Guessed
1265         wolinfo->supported = WAKE_PHY | WAKE_MAGIC
1266                         | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1267         wolinfo->wolopts = 0;
1268 
1269         if (pm_config & PM_LinkUp)
1270                 wolinfo->wolopts |= WAKE_PHY;
1271 
1272         if (pm_config & PM_Magic)
1273                 wolinfo->wolopts |= WAKE_MAGIC;
1274 
1275         if (pm_config & PM_WakeUp)
1276                 // FIXME: Guessed
1277                 wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1278 }
1279 
1280 static int sc92031_ethtool_set_wol(struct net_device *dev,
1281                 struct ethtool_wolinfo *wolinfo)
1282 {
1283         struct sc92031_priv *priv = netdev_priv(dev);
1284         void __iomem *port_base = priv->port_base;
1285         u32 pm_config;
1286 
1287         spin_lock_bh(&priv->lock);
1288 
1289         pm_config = ioread32(port_base + PMConfig)
1290                         & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
1291 
1292         if (wolinfo->wolopts & WAKE_PHY)
1293                 pm_config |= PM_LinkUp;
1294 
1295         if (wolinfo->wolopts & WAKE_MAGIC)
1296                 pm_config |= PM_Magic;
1297 
1298         // FIXME: Guessed
1299         if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
1300                 pm_config |= PM_WakeUp;
1301 
1302         priv->pm_config = pm_config;
1303         iowrite32(pm_config, port_base + PMConfig);
1304 
1305         spin_unlock_bh(&priv->lock);
1306 
1307         return 0;
1308 }
1309 
1310 static int sc92031_ethtool_nway_reset(struct net_device *dev)
1311 {
1312         int err = 0;
1313         struct sc92031_priv *priv = netdev_priv(dev);
1314         void __iomem *port_base = priv->port_base;
1315         u16 bmcr;
1316 
1317         spin_lock_bh(&priv->lock);
1318 
1319         bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1320         if (!(bmcr & BMCR_ANENABLE)) {
1321                 err = -EINVAL;
1322                 goto out;
1323         }
1324 
1325         _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1326 
1327 out:
1328         _sc92031_mii_scan(port_base);
1329 
1330         spin_unlock_bh(&priv->lock);
1331 
1332         return err;
1333 }
1334 
1335 static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
1336         "tx_timeout",
1337         "rx_loss",
1338 };
1339 
1340 static void sc92031_ethtool_get_strings(struct net_device *dev,
1341                 u32 stringset, u8 *data)
1342 {
1343         if (stringset == ETH_SS_STATS)
1344                 memcpy(data, sc92031_ethtool_stats_strings,
1345                                 SILAN_STATS_NUM * ETH_GSTRING_LEN);
1346 }
1347 
1348 static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset)
1349 {
1350         switch (sset) {
1351         case ETH_SS_STATS:
1352                 return SILAN_STATS_NUM;
1353         default:
1354                 return -EOPNOTSUPP;
1355         }
1356 }
1357 
1358 static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
1359                 struct ethtool_stats *stats, u64 *data)
1360 {
1361         struct sc92031_priv *priv = netdev_priv(dev);
1362 
1363         spin_lock_bh(&priv->lock);
1364         data[0] = priv->tx_timeouts;
1365         data[1] = priv->rx_loss;
1366         spin_unlock_bh(&priv->lock);
1367 }
1368 
1369 static const struct ethtool_ops sc92031_ethtool_ops = {
1370         .get_wol                = sc92031_ethtool_get_wol,
1371         .set_wol                = sc92031_ethtool_set_wol,
1372         .nway_reset             = sc92031_ethtool_nway_reset,
1373         .get_link               = ethtool_op_get_link,
1374         .get_strings            = sc92031_ethtool_get_strings,
1375         .get_sset_count         = sc92031_ethtool_get_sset_count,
1376         .get_ethtool_stats      = sc92031_ethtool_get_ethtool_stats,
1377         .get_link_ksettings     = sc92031_ethtool_get_link_ksettings,
1378         .set_link_ksettings     = sc92031_ethtool_set_link_ksettings,
1379 };
1380 
1381 
1382 static const struct net_device_ops sc92031_netdev_ops = {
1383         .ndo_get_stats          = sc92031_get_stats,
1384         .ndo_start_xmit         = sc92031_start_xmit,
1385         .ndo_open               = sc92031_open,
1386         .ndo_stop               = sc92031_stop,
1387         .ndo_set_rx_mode        = sc92031_set_multicast_list,
1388         .ndo_validate_addr      = eth_validate_addr,
1389         .ndo_set_mac_address    = eth_mac_addr,
1390         .ndo_tx_timeout         = sc92031_tx_timeout,
1391 #ifdef CONFIG_NET_POLL_CONTROLLER
1392         .ndo_poll_controller    = sc92031_poll_controller,
1393 #endif
1394 };
1395 
1396 static int sc92031_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1397 {
1398         int err;
1399         void __iomem* port_base;
1400         struct net_device *dev;
1401         struct sc92031_priv *priv;
1402         u32 mac0, mac1;
1403 
1404         err = pci_enable_device(pdev);
1405         if (unlikely(err < 0))
1406                 goto out_enable_device;
1407 
1408         pci_set_master(pdev);
1409 
1410         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1411         if (unlikely(err < 0))
1412                 goto out_set_dma_mask;
1413 
1414         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1415         if (unlikely(err < 0))
1416                 goto out_set_dma_mask;
1417 
1418         err = pci_request_regions(pdev, SC92031_NAME);
1419         if (unlikely(err < 0))
1420                 goto out_request_regions;
1421 
1422         port_base = pci_iomap(pdev, SC92031_USE_PIO, 0);
1423         if (unlikely(!port_base)) {
1424                 err = -EIO;
1425                 goto out_iomap;
1426         }
1427 
1428         dev = alloc_etherdev(sizeof(struct sc92031_priv));
1429         if (unlikely(!dev)) {
1430                 err = -ENOMEM;
1431                 goto out_alloc_etherdev;
1432         }
1433 
1434         pci_set_drvdata(pdev, dev);
1435         SET_NETDEV_DEV(dev, &pdev->dev);
1436 
1437         /* faked with skb_copy_and_csum_dev */
1438         dev->features = NETIF_F_SG | NETIF_F_HIGHDMA |
1439                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1440 
1441         dev->netdev_ops         = &sc92031_netdev_ops;
1442         dev->watchdog_timeo     = TX_TIMEOUT;
1443         dev->ethtool_ops        = &sc92031_ethtool_ops;
1444 
1445         priv = netdev_priv(dev);
1446         spin_lock_init(&priv->lock);
1447         priv->port_base = port_base;
1448         priv->pdev = pdev;
1449         tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev);
1450         /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1451          * sc92031_open will work correctly */
1452         tasklet_disable_nosync(&priv->tasklet);
1453 
1454         /* PCI PM Wakeup */
1455         iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1456 
1457         mac0 = ioread32(port_base + MAC0);
1458         mac1 = ioread32(port_base + MAC0 + 4);
1459         dev->dev_addr[0] = mac0 >> 24;
1460         dev->dev_addr[1] = mac0 >> 16;
1461         dev->dev_addr[2] = mac0 >> 8;
1462         dev->dev_addr[3] = mac0;
1463         dev->dev_addr[4] = mac1 >> 8;
1464         dev->dev_addr[5] = mac1;
1465 
1466         err = register_netdev(dev);
1467         if (err < 0)
1468                 goto out_register_netdev;
1469 
1470         printk(KERN_INFO "%s: SC92031 at 0x%lx, %pM, IRQ %d\n", dev->name,
1471                (long)pci_resource_start(pdev, SC92031_USE_PIO), dev->dev_addr,
1472                pdev->irq);
1473 
1474         return 0;
1475 
1476 out_register_netdev:
1477         free_netdev(dev);
1478 out_alloc_etherdev:
1479         pci_iounmap(pdev, port_base);
1480 out_iomap:
1481         pci_release_regions(pdev);
1482 out_request_regions:
1483 out_set_dma_mask:
1484         pci_disable_device(pdev);
1485 out_enable_device:
1486         return err;
1487 }
1488 
1489 static void sc92031_remove(struct pci_dev *pdev)
1490 {
1491         struct net_device *dev = pci_get_drvdata(pdev);
1492         struct sc92031_priv *priv = netdev_priv(dev);
1493         void __iomem* port_base = priv->port_base;
1494 
1495         unregister_netdev(dev);
1496         free_netdev(dev);
1497         pci_iounmap(pdev, port_base);
1498         pci_release_regions(pdev);
1499         pci_disable_device(pdev);
1500 }
1501 
1502 static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state)
1503 {
1504         struct net_device *dev = pci_get_drvdata(pdev);
1505         struct sc92031_priv *priv = netdev_priv(dev);
1506 
1507         pci_save_state(pdev);
1508 
1509         if (!netif_running(dev))
1510                 goto out;
1511 
1512         netif_device_detach(dev);
1513 
1514         /* Disable interrupts, stop Tx and Rx. */
1515         sc92031_disable_interrupts(dev);
1516 
1517         spin_lock_bh(&priv->lock);
1518 
1519         _sc92031_disable_tx_rx(dev);
1520         _sc92031_tx_clear(dev);
1521 
1522         spin_unlock_bh(&priv->lock);
1523 
1524 out:
1525         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1526 
1527         return 0;
1528 }
1529 
1530 static int sc92031_resume(struct pci_dev *pdev)
1531 {
1532         struct net_device *dev = pci_get_drvdata(pdev);
1533         struct sc92031_priv *priv = netdev_priv(dev);
1534 
1535         pci_restore_state(pdev);
1536         pci_set_power_state(pdev, PCI_D0);
1537 
1538         if (!netif_running(dev))
1539                 goto out;
1540 
1541         /* Interrupts already disabled by sc92031_suspend */
1542         spin_lock_bh(&priv->lock);
1543 
1544         _sc92031_reset(dev);
1545 
1546         spin_unlock_bh(&priv->lock);
1547         sc92031_enable_interrupts(dev);
1548 
1549         netif_device_attach(dev);
1550 
1551         if (netif_carrier_ok(dev))
1552                 netif_wake_queue(dev);
1553         else
1554                 netif_tx_disable(dev);
1555 
1556 out:
1557         return 0;
1558 }
1559 
1560 static const struct pci_device_id sc92031_pci_device_id_table[] = {
1561         { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x2031) },
1562         { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x8139) },
1563         { PCI_DEVICE(0x1088, 0x2031) },
1564         { 0, }
1565 };
1566 MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
1567 
1568 static struct pci_driver sc92031_pci_driver = {
1569         .name           = SC92031_NAME,
1570         .id_table       = sc92031_pci_device_id_table,
1571         .probe          = sc92031_probe,
1572         .remove         = sc92031_remove,
1573         .suspend        = sc92031_suspend,
1574         .resume         = sc92031_resume,
1575 };
1576 
1577 module_pci_driver(sc92031_pci_driver);
1578 MODULE_LICENSE("GPL");
1579 MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
1580 MODULE_DESCRIPTION("Silan SC92031 PCI Fast Ethernet Adapter driver");

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