This source file includes following definitions.
- tp_to_dev
- rtl_lock_work
- rtl_unlock_work
- rtl_lock_config_regs
- rtl_unlock_config_regs
- rtl_tx_performance_tweak
- rtl_is_8125
- rtl_is_8168evl_up
- rtl_supports_eee
- rtl_read_mac_from_reg
- rtl_udelay
- rtl_loop_wait
- rtl_udelay_loop_wait_high
- rtl_udelay_loop_wait_low
- rtl_msleep_loop_wait_high
- rtl_msleep_loop_wait_low
- rtl_ocp_reg_failure
- DECLARE_RTL_COND
- r8168_phy_ocp_write
- r8168_phy_ocp_read
- r8168_mac_ocp_write
- r8168_mac_ocp_read
- r8168_mac_ocp_modify
- r8168g_mdio_write
- r8168g_mdio_read
- mac_mcu_write
- mac_mcu_read
- DECLARE_RTL_COND
- r8169_mdio_write
- r8169_mdio_read
- DECLARE_RTL_COND
- r8168dp_1_mdio_access
- r8168dp_1_mdio_write
- r8168dp_1_mdio_read
- r8168dp_2_mdio_start
- r8168dp_2_mdio_stop
- r8168dp_2_mdio_write
- r8168dp_2_mdio_read
- rtl_writephy
- rtl_readphy
- rtl_patchphy
- rtl_w0w1_phy
- DECLARE_RTL_COND
- rtl_ephy_write
- rtl_ephy_read
- DECLARE_RTL_COND
- _rtl_eri_write
- rtl_eri_write
- _rtl_eri_read
- rtl_eri_read
- rtl_w0w1_eri
- rtl_eri_set_bits
- rtl_eri_clear_bits
- r8168dp_ocp_read
- r8168ep_ocp_read
- r8168dp_ocp_write
- r8168ep_ocp_write
- r8168dp_oob_notify
- rtl8168_get_ocp_reg
- DECLARE_RTL_COND
- DECLARE_RTL_COND
- DECLARE_RTL_COND
- rtl8168ep_stop_cmac
- rtl8168dp_driver_start
- rtl8168ep_driver_start
- rtl8168_driver_start
- rtl8168dp_driver_stop
- rtl8168ep_driver_stop
- rtl8168_driver_stop
- r8168dp_check_dash
- r8168ep_check_dash
- r8168_check_dash
- rtl_reset_packet_filter
- DECLARE_RTL_COND
- rtl8168d_efuse_read
- rtl_get_events
- rtl_ack_events
- rtl_irq_disable
- rtl_irq_enable
- rtl8169_irq_mask_and_ack
- rtl_link_chg_patch
- rtl8169_get_wol
- __rtl8169_set_wol
- rtl8169_set_wol
- rtl8169_get_drvinfo
- rtl8169_get_regs_len
- rtl8169_fix_features
- rtl8169_set_features
- rtl8169_tx_vlan_tag
- rtl8169_rx_vlan_tag
- rtl8169_get_regs
- rtl8169_get_msglevel
- rtl8169_set_msglevel
- rtl8169_get_sset_count
- DECLARE_RTL_COND
- rtl8169_do_counters
- rtl8169_reset_counters
- rtl8169_update_counters
- rtl8169_init_counter_offsets
- rtl8169_get_ethtool_stats
- rtl8169_get_strings
- rtl_get_coalesce
- rtl_coalesce_choose_scale
- rtl_set_coalesce
- rtl8169_get_eee
- rtl8169_set_eee
- rtl_enable_eee
- rtl8169_get_mac_version
- __rtl_writephy_batch
- rtl_release_firmware
- rtl_apply_firmware
- rtl_apply_firmware_cond
- rtl8168_config_eee_mac
- rtl8125_config_eee_mac
- rtl8168f_config_eee_phy
- rtl8168g_config_eee_phy
- rtl8168h_config_eee_phy
- rtl8125_config_eee_phy
- rtl8169s_hw_phy_config
- rtl8169sb_hw_phy_config
- rtl8169scd_hw_phy_config_quirk
- rtl8169scd_hw_phy_config
- rtl8169sce_hw_phy_config
- rtl8168bb_hw_phy_config
- rtl8168bef_hw_phy_config
- rtl8168cp_1_hw_phy_config
- rtl8168cp_2_hw_phy_config
- rtl8168c_1_hw_phy_config
- rtl8168c_2_hw_phy_config
- rtl8168c_3_hw_phy_config
- rtl8168c_4_hw_phy_config
- rtl8168d_1_hw_phy_config
- rtl8168d_2_hw_phy_config
- rtl8168d_3_hw_phy_config
- rtl8168d_4_hw_phy_config
- rtl8168e_1_hw_phy_config
- rtl_rar_exgmac_set
- rtl8168e_2_hw_phy_config
- rtl8168f_hw_phy_config
- rtl8168f_1_hw_phy_config
- rtl8168f_2_hw_phy_config
- rtl8411_hw_phy_config
- rtl8168g_disable_aldps
- rtl8168g_phy_adjust_10m_aldps
- rtl8168g_1_hw_phy_config
- rtl8168g_2_hw_phy_config
- rtl8168h_1_hw_phy_config
- rtl8168h_2_hw_phy_config
- rtl8168ep_1_hw_phy_config
- rtl8168ep_2_hw_phy_config
- rtl8102e_hw_phy_config
- rtl8105e_hw_phy_config
- rtl8402_hw_phy_config
- rtl8106e_hw_phy_config
- rtl8125_1_hw_phy_config
- rtl8125_2_hw_phy_config
- rtl_hw_phy_config
- rtl_schedule_task
- rtl8169_init_phy
- rtl_rar_set
- rtl_set_mac_address
- rtl8169_ioctl
- rtl_wol_suspend_quirk
- rtl_pll_power_down
- rtl_pll_power_up
- rtl_init_rxcfg
- rtl8169_init_ring_indexes
- r8168c_hw_jumbo_enable
- r8168c_hw_jumbo_disable
- r8168dp_hw_jumbo_enable
- r8168dp_hw_jumbo_disable
- r8168e_hw_jumbo_enable
- r8168e_hw_jumbo_disable
- r8168b_0_hw_jumbo_enable
- r8168b_0_hw_jumbo_disable
- r8168b_1_hw_jumbo_enable
- r8168b_1_hw_jumbo_disable
- rtl_hw_jumbo_enable
- rtl_hw_jumbo_disable
- rtl_jumbo_config
- DECLARE_RTL_COND
- rtl_hw_reset
- rtl_request_firmware
- rtl_rx_close
- DECLARE_RTL_COND
- DECLARE_RTL_COND
- rtl8169_hw_reset
- rtl_set_tx_config_registers
- rtl_set_rx_max_size
- rtl_set_rx_tx_desc_registers
- rtl8169_set_magic_reg
- rtl_set_rx_mode
- DECLARE_RTL_COND
- rtl_csi_write
- rtl_csi_read
- rtl_csi_access_enable
- rtl_set_def_aspm_entry_latency
- __rtl_ephy_init
- rtl_disable_clock_request
- rtl_enable_clock_request
- rtl_pcie_state_l2l3_disable
- rtl_hw_aspm_clkreq_enable
- rtl_set_fifo_size
- rtl8168g_set_pause_thresholds
- rtl_hw_start_8168bb
- rtl_hw_start_8168bef
- __rtl_hw_start_8168cp
- rtl_hw_start_8168cp_1
- rtl_hw_start_8168cp_2
- rtl_hw_start_8168cp_3
- rtl_hw_start_8168c_1
- rtl_hw_start_8168c_2
- rtl_hw_start_8168c_3
- rtl_hw_start_8168c_4
- rtl_hw_start_8168d
- rtl_hw_start_8168dp
- rtl_hw_start_8168d_4
- rtl_hw_start_8168e_1
- rtl_hw_start_8168e_2
- rtl_hw_start_8168f
- rtl_hw_start_8168f_1
- rtl_hw_start_8411
- rtl_hw_start_8168g
- rtl_hw_start_8168g_1
- rtl_hw_start_8168g_2
- rtl_hw_start_8411_2
- rtl_hw_start_8168h_1
- rtl_hw_start_8168ep
- rtl_hw_start_8168ep_1
- rtl_hw_start_8168ep_2
- rtl_hw_start_8168ep_3
- rtl_hw_start_8102e_1
- rtl_hw_start_8102e_2
- rtl_hw_start_8102e_3
- rtl_hw_start_8105e_1
- rtl_hw_start_8105e_2
- rtl_hw_start_8402
- rtl_hw_start_8106
- DECLARE_RTL_COND
- rtl_hw_start_8125_common
- rtl_hw_start_8125_1
- rtl_hw_start_8125_2
- rtl_hw_config
- rtl_hw_start_8125
- rtl_hw_start_8168
- rtl_hw_start_8169
- rtl_hw_start
- rtl8169_change_mtu
- rtl8169_make_unusable_by_asic
- rtl8169_mark_to_asic
- rtl8169_alloc_rx_data
- rtl8169_rx_clear
- rtl8169_mark_as_last_descriptor
- rtl8169_rx_fill
- rtl8169_init_ring
- rtl8169_unmap_tx_skb
- rtl8169_tx_clear_range
- rtl8169_tx_clear
- rtl_reset_work
- rtl8169_tx_timeout
- rtl8169_get_txd_opts1
- rtl8169_xmit_frags
- rtl_test_hw_pad_bug
- msdn_giant_send_check
- rtl8169_tso_csum_v1
- rtl8169_tso_csum_v2
- rtl_tx_slots_avail
- rtl_chip_supports_csum_v2
- rtl8169_doorbell
- rtl8169_start_xmit
- rtl8169_features_check
- rtl8169_pcierr_interrupt
- rtl_tx
- rtl8169_fragmented_frame
- rtl8169_rx_csum
- rtl_rx
- rtl8169_interrupt
- rtl_task
- rtl8169_poll
- rtl8169_rx_missed
- r8169_phylink_handler
- r8169_phy_connect
- rtl8169_down
- rtl8169_close
- rtl8169_netpoll
- rtl_open
- rtl8169_get_stats64
- rtl8169_net_suspend
- rtl8169_suspend
- __rtl8169_resume
- rtl8169_resume
- rtl8169_runtime_suspend
- rtl8169_runtime_resume
- rtl8169_runtime_idle
- rtl_wol_shutdown_quirk
- rtl_shutdown
- rtl_remove_one
- rtl_set_irq_mask
- rtl_alloc_irq
- rtl_read_mac_address
- DECLARE_RTL_COND
- DECLARE_RTL_COND
- r8169_mdio_read_reg
- r8169_mdio_write_reg
- r8169_mdio_register
- rtl_hw_init_8168g
- rtl_hw_init_8125
- rtl_hw_initialize
- rtl_jumbo_max
- rtl_disable_clk
- rtl_get_ether_clk
- rtl_init_mac_address
- rtl_init_one
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12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
23 #include <linux/in.h>
24 #include <linux/io.h>
25 #include <linux/ip.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/prefetch.h>
31 #include <linux/ipv6.h>
32 #include <net/ip6_checksum.h>
33
34 #include "r8169_firmware.h"
35
36 #define MODULENAME "r8169"
37
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
58
59 #define R8169_MSG_DEFAULT \
60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61
62
63
64 #define MC_FILTER_LIMIT 32
65
66 #define TX_DMA_BURST 7
67 #define InterFrameGap 0x03
68
69 #define R8169_REGS_SIZE 256
70 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
71 #define NUM_TX_DESC 64
72 #define NUM_RX_DESC 256U
73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75
76 #define RTL_CFG_NO_GBIT 1
77
78
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
85
86 enum mac_version {
87
88 RTL_GIGA_MAC_VER_02,
89 RTL_GIGA_MAC_VER_03,
90 RTL_GIGA_MAC_VER_04,
91 RTL_GIGA_MAC_VER_05,
92 RTL_GIGA_MAC_VER_06,
93 RTL_GIGA_MAC_VER_07,
94 RTL_GIGA_MAC_VER_08,
95 RTL_GIGA_MAC_VER_09,
96 RTL_GIGA_MAC_VER_10,
97 RTL_GIGA_MAC_VER_11,
98 RTL_GIGA_MAC_VER_12,
99 RTL_GIGA_MAC_VER_13,
100 RTL_GIGA_MAC_VER_14,
101 RTL_GIGA_MAC_VER_15,
102 RTL_GIGA_MAC_VER_16,
103 RTL_GIGA_MAC_VER_17,
104 RTL_GIGA_MAC_VER_18,
105 RTL_GIGA_MAC_VER_19,
106 RTL_GIGA_MAC_VER_20,
107 RTL_GIGA_MAC_VER_21,
108 RTL_GIGA_MAC_VER_22,
109 RTL_GIGA_MAC_VER_23,
110 RTL_GIGA_MAC_VER_24,
111 RTL_GIGA_MAC_VER_25,
112 RTL_GIGA_MAC_VER_26,
113 RTL_GIGA_MAC_VER_27,
114 RTL_GIGA_MAC_VER_28,
115 RTL_GIGA_MAC_VER_29,
116 RTL_GIGA_MAC_VER_30,
117 RTL_GIGA_MAC_VER_31,
118 RTL_GIGA_MAC_VER_32,
119 RTL_GIGA_MAC_VER_33,
120 RTL_GIGA_MAC_VER_34,
121 RTL_GIGA_MAC_VER_35,
122 RTL_GIGA_MAC_VER_36,
123 RTL_GIGA_MAC_VER_37,
124 RTL_GIGA_MAC_VER_38,
125 RTL_GIGA_MAC_VER_39,
126 RTL_GIGA_MAC_VER_40,
127 RTL_GIGA_MAC_VER_41,
128 RTL_GIGA_MAC_VER_42,
129 RTL_GIGA_MAC_VER_43,
130 RTL_GIGA_MAC_VER_44,
131 RTL_GIGA_MAC_VER_45,
132 RTL_GIGA_MAC_VER_46,
133 RTL_GIGA_MAC_VER_47,
134 RTL_GIGA_MAC_VER_48,
135 RTL_GIGA_MAC_VER_49,
136 RTL_GIGA_MAC_VER_50,
137 RTL_GIGA_MAC_VER_51,
138 RTL_GIGA_MAC_VER_60,
139 RTL_GIGA_MAC_VER_61,
140 RTL_GIGA_MAC_NONE
141 };
142
143 #define JUMBO_1K ETH_DATA_LEN
144 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
145 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
146 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
147 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
148
149 static const struct {
150 const char *name;
151 const char *fw_name;
152 } rtl_chip_infos[] = {
153
154 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
155 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
156 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
157 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
158 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
159
160 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
161 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
162 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
163 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
164 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
165 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
166 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
167 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
168 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
169 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
170 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
171 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
172 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
173 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
174 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
175 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
176 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
177 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
178 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
179 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
180 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
181 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
182 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
183 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
184 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
185 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
186 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
187 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
188 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
189 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
190 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
191 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
192 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
193 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
194 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
195 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
196 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
197 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
198 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
199 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
200 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
201 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
202 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
203 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
204 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
205 [RTL_GIGA_MAC_VER_60] = {"RTL8125" },
206 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3},
207 };
208
209 static const struct pci_device_id rtl8169_pci_tbl[] = {
210 { PCI_VDEVICE(REALTEK, 0x2502) },
211 { PCI_VDEVICE(REALTEK, 0x2600) },
212 { PCI_VDEVICE(REALTEK, 0x8129) },
213 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
214 { PCI_VDEVICE(REALTEK, 0x8161) },
215 { PCI_VDEVICE(REALTEK, 0x8167) },
216 { PCI_VDEVICE(REALTEK, 0x8168) },
217 { PCI_VDEVICE(NCUBE, 0x8168) },
218 { PCI_VDEVICE(REALTEK, 0x8169) },
219 { PCI_VENDOR_ID_DLINK, 0x4300,
220 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
221 { PCI_VDEVICE(DLINK, 0x4300) },
222 { PCI_VDEVICE(DLINK, 0x4302) },
223 { PCI_VDEVICE(AT, 0xc107) },
224 { PCI_VDEVICE(USR, 0x0116) },
225 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
226 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
227 { PCI_VDEVICE(REALTEK, 0x8125) },
228 { PCI_VDEVICE(REALTEK, 0x3000) },
229 {}
230 };
231
232 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
233
234 static struct {
235 u32 msg_enable;
236 } debug = { -1 };
237
238 enum rtl_registers {
239 MAC0 = 0,
240 MAC4 = 4,
241 MAR0 = 8,
242 CounterAddrLow = 0x10,
243 CounterAddrHigh = 0x14,
244 TxDescStartAddrLow = 0x20,
245 TxDescStartAddrHigh = 0x24,
246 TxHDescStartAddrLow = 0x28,
247 TxHDescStartAddrHigh = 0x2c,
248 FLASH = 0x30,
249 ERSR = 0x36,
250 ChipCmd = 0x37,
251 TxPoll = 0x38,
252 IntrMask = 0x3c,
253 IntrStatus = 0x3e,
254
255 TxConfig = 0x40,
256 #define TXCFG_AUTO_FIFO (1 << 7)
257 #define TXCFG_EMPTY (1 << 11)
258
259 RxConfig = 0x44,
260 #define RX128_INT_EN (1 << 15)
261 #define RX_MULTI_EN (1 << 14)
262 #define RXCFG_FIFO_SHIFT 13
263
264 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
265 #define RX_EARLY_OFF (1 << 11)
266 #define RXCFG_DMA_SHIFT 8
267
268 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
269
270 RxMissed = 0x4c,
271 Cfg9346 = 0x50,
272 Config0 = 0x51,
273 Config1 = 0x52,
274 Config2 = 0x53,
275 #define PME_SIGNAL (1 << 5)
276
277 Config3 = 0x54,
278 Config4 = 0x55,
279 Config5 = 0x56,
280 PHYAR = 0x60,
281 PHYstatus = 0x6c,
282 RxMaxSize = 0xda,
283 CPlusCmd = 0xe0,
284 IntrMitigate = 0xe2,
285
286 #define RTL_COALESCE_MASK 0x0f
287 #define RTL_COALESCE_SHIFT 4
288 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
289 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
290
291 RxDescAddrLow = 0xe4,
292 RxDescAddrHigh = 0xe8,
293 EarlyTxThres = 0xec,
294
295 #define NoEarlyTx 0x3f
296
297 MaxTxPacketSize = 0xec,
298
299 #define TxPacketMax (8064 >> 7)
300 #define EarlySize 0x27
301
302 FuncEvent = 0xf0,
303 FuncEventMask = 0xf4,
304 FuncPresetState = 0xf8,
305 IBCR0 = 0xf8,
306 IBCR2 = 0xf9,
307 IBIMR0 = 0xfa,
308 IBISR0 = 0xfb,
309 FuncForceEvent = 0xfc,
310 };
311
312 enum rtl8168_8101_registers {
313 CSIDR = 0x64,
314 CSIAR = 0x68,
315 #define CSIAR_FLAG 0x80000000
316 #define CSIAR_WRITE_CMD 0x80000000
317 #define CSIAR_BYTE_ENABLE 0x0000f000
318 #define CSIAR_ADDR_MASK 0x00000fff
319 PMCH = 0x6f,
320 EPHYAR = 0x80,
321 #define EPHYAR_FLAG 0x80000000
322 #define EPHYAR_WRITE_CMD 0x80000000
323 #define EPHYAR_REG_MASK 0x1f
324 #define EPHYAR_REG_SHIFT 16
325 #define EPHYAR_DATA_MASK 0xffff
326 DLLPR = 0xd0,
327 #define PFM_EN (1 << 6)
328 #define TX_10M_PS_EN (1 << 7)
329 DBG_REG = 0xd1,
330 #define FIX_NAK_1 (1 << 4)
331 #define FIX_NAK_2 (1 << 3)
332 TWSI = 0xd2,
333 MCU = 0xd3,
334 #define NOW_IS_OOB (1 << 7)
335 #define TX_EMPTY (1 << 5)
336 #define RX_EMPTY (1 << 4)
337 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
338 #define EN_NDP (1 << 3)
339 #define EN_OOB_RESET (1 << 2)
340 #define LINK_LIST_RDY (1 << 1)
341 EFUSEAR = 0xdc,
342 #define EFUSEAR_FLAG 0x80000000
343 #define EFUSEAR_WRITE_CMD 0x80000000
344 #define EFUSEAR_READ_CMD 0x00000000
345 #define EFUSEAR_REG_MASK 0x03ff
346 #define EFUSEAR_REG_SHIFT 8
347 #define EFUSEAR_DATA_MASK 0xff
348 MISC_1 = 0xf2,
349 #define PFM_D3COLD_EN (1 << 6)
350 };
351
352 enum rtl8168_registers {
353 LED_FREQ = 0x1a,
354 EEE_LED = 0x1b,
355 ERIDR = 0x70,
356 ERIAR = 0x74,
357 #define ERIAR_FLAG 0x80000000
358 #define ERIAR_WRITE_CMD 0x80000000
359 #define ERIAR_READ_CMD 0x00000000
360 #define ERIAR_ADDR_BYTE_ALIGN 4
361 #define ERIAR_TYPE_SHIFT 16
362 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
363 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
364 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
365 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
366 #define ERIAR_MASK_SHIFT 12
367 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
368 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
369 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
370 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
371 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
372 EPHY_RXER_NUM = 0x7c,
373 OCPDR = 0xb0,
374 #define OCPDR_WRITE_CMD 0x80000000
375 #define OCPDR_READ_CMD 0x00000000
376 #define OCPDR_REG_MASK 0x7f
377 #define OCPDR_GPHY_REG_SHIFT 16
378 #define OCPDR_DATA_MASK 0xffff
379 OCPAR = 0xb4,
380 #define OCPAR_FLAG 0x80000000
381 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
382 #define OCPAR_GPHY_READ_CMD 0x0000f060
383 GPHY_OCP = 0xb8,
384 RDSAR1 = 0xd0,
385 MISC = 0xf0,
386 #define TXPLA_RST (1 << 29)
387 #define DISABLE_LAN_EN (1 << 23)
388 #define PWM_EN (1 << 22)
389 #define RXDV_GATED_EN (1 << 19)
390 #define EARLY_TALLY_EN (1 << 16)
391 };
392
393 enum rtl8125_registers {
394 IntrMask_8125 = 0x38,
395 IntrStatus_8125 = 0x3c,
396 TxPoll_8125 = 0x90,
397 MAC0_BKP = 0x19e0,
398 };
399
400 #define RX_VLAN_INNER_8125 BIT(22)
401 #define RX_VLAN_OUTER_8125 BIT(23)
402 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
403
404 #define RX_FETCH_DFLT_8125 (8 << 27)
405
406 enum rtl_register_content {
407
408 SYSErr = 0x8000,
409 PCSTimeout = 0x4000,
410 SWInt = 0x0100,
411 TxDescUnavail = 0x0080,
412 RxFIFOOver = 0x0040,
413 LinkChg = 0x0020,
414 RxOverflow = 0x0010,
415 TxErr = 0x0008,
416 TxOK = 0x0004,
417 RxErr = 0x0002,
418 RxOK = 0x0001,
419
420
421 RxRWT = (1 << 22),
422 RxRES = (1 << 21),
423 RxRUNT = (1 << 20),
424 RxCRC = (1 << 19),
425
426
427 StopReq = 0x80,
428 CmdReset = 0x10,
429 CmdRxEnb = 0x08,
430 CmdTxEnb = 0x04,
431 RxBufEmpty = 0x01,
432
433
434 HPQ = 0x80,
435 NPQ = 0x40,
436 FSWInt = 0x01,
437
438
439 Cfg9346_Lock = 0x00,
440 Cfg9346_Unlock = 0xc0,
441
442
443 AcceptErr = 0x20,
444 AcceptRunt = 0x10,
445 AcceptBroadcast = 0x08,
446 AcceptMulticast = 0x04,
447 AcceptMyPhys = 0x02,
448 AcceptAllPhys = 0x01,
449 #define RX_CONFIG_ACCEPT_MASK 0x3f
450
451
452 TxInterFrameGapShift = 24,
453 TxDMAShift = 8,
454
455
456 LEDS1 = (1 << 7),
457 LEDS0 = (1 << 6),
458 Speed_down = (1 << 4),
459 MEMMAP = (1 << 3),
460 IOMAP = (1 << 2),
461 VPD = (1 << 1),
462 PMEnable = (1 << 0),
463
464
465 ClkReqEn = (1 << 7),
466 MSIEnable = (1 << 5),
467 PCI_Clock_66MHz = 0x01,
468 PCI_Clock_33MHz = 0x00,
469
470
471 MagicPacket = (1 << 5),
472 LinkUp = (1 << 4),
473 Jumbo_En0 = (1 << 2),
474 Rdy_to_L23 = (1 << 1),
475 Beacon_en = (1 << 0),
476
477
478 Jumbo_En1 = (1 << 1),
479
480
481 BWF = (1 << 6),
482 MWF = (1 << 5),
483 UWF = (1 << 4),
484 Spi_en = (1 << 3),
485 LanWake = (1 << 1),
486 PMEStatus = (1 << 0),
487 ASPM_en = (1 << 0),
488
489
490 EnableBist = (1 << 15),
491 Mac_dbgo_oe = (1 << 14),
492 Normal_mode = (1 << 13),
493 Force_half_dup = (1 << 12),
494 Force_rxflow_en = (1 << 11),
495 Force_txflow_en = (1 << 10),
496 Cxpl_dbg_sel = (1 << 9),
497 ASF = (1 << 8),
498 PktCntrDisable = (1 << 7),
499 Mac_dbgo_sel = 0x001c,
500 RxVlan = (1 << 6),
501 RxChkSum = (1 << 5),
502 PCIDAC = (1 << 4),
503 PCIMulRW = (1 << 3),
504 #define INTT_MASK GENMASK(1, 0)
505 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
506
507
508 TBI_Enable = 0x80,
509 TxFlowCtrl = 0x40,
510 RxFlowCtrl = 0x20,
511 _1000bpsF = 0x10,
512 _100bps = 0x08,
513 _10bps = 0x04,
514 LinkStatus = 0x02,
515 FullDup = 0x01,
516
517
518 CounterReset = 0x1,
519
520
521 CounterDump = 0x8,
522
523
524 MagicPacket_v2 = (1 << 16),
525 };
526
527 enum rtl_desc_bit {
528
529 DescOwn = (1 << 31),
530 RingEnd = (1 << 30),
531 FirstFrag = (1 << 29),
532 LastFrag = (1 << 28),
533 };
534
535
536 enum rtl_tx_desc_bit {
537
538 TD_LSO = (1 << 27),
539 #define TD_MSS_MAX 0x07ffu
540
541
542 TxVlanTag = (1 << 17),
543 };
544
545
546 enum rtl_tx_desc_bit_0 {
547
548 #define TD0_MSS_SHIFT 16
549 TD0_TCP_CS = (1 << 16),
550 TD0_UDP_CS = (1 << 17),
551 TD0_IP_CS = (1 << 18),
552 };
553
554
555 enum rtl_tx_desc_bit_1 {
556
557 TD1_GTSENV4 = (1 << 26),
558 TD1_GTSENV6 = (1 << 25),
559 #define GTTCPHO_SHIFT 18
560 #define GTTCPHO_MAX 0x7f
561
562
563 #define TCPHO_SHIFT 18
564 #define TCPHO_MAX 0x3ff
565 #define TD1_MSS_SHIFT 18
566 TD1_IPv6_CS = (1 << 28),
567 TD1_IPv4_CS = (1 << 29),
568 TD1_TCP_CS = (1 << 30),
569 TD1_UDP_CS = (1 << 31),
570 };
571
572 enum rtl_rx_desc_bit {
573
574 PID1 = (1 << 18),
575 PID0 = (1 << 17),
576
577 #define RxProtoUDP (PID1)
578 #define RxProtoTCP (PID0)
579 #define RxProtoIP (PID1 | PID0)
580 #define RxProtoMask RxProtoIP
581
582 IPFail = (1 << 16),
583 UDPFail = (1 << 15),
584 TCPFail = (1 << 14),
585 RxVlanTag = (1 << 16),
586 };
587
588 #define RsvdMask 0x3fffc000
589
590 #define RTL_GSO_MAX_SIZE_V1 32000
591 #define RTL_GSO_MAX_SEGS_V1 24
592 #define RTL_GSO_MAX_SIZE_V2 64000
593 #define RTL_GSO_MAX_SEGS_V2 64
594
595 struct TxDesc {
596 __le32 opts1;
597 __le32 opts2;
598 __le64 addr;
599 };
600
601 struct RxDesc {
602 __le32 opts1;
603 __le32 opts2;
604 __le64 addr;
605 };
606
607 struct ring_info {
608 struct sk_buff *skb;
609 u32 len;
610 };
611
612 struct rtl8169_counters {
613 __le64 tx_packets;
614 __le64 rx_packets;
615 __le64 tx_errors;
616 __le32 rx_errors;
617 __le16 rx_missed;
618 __le16 align_errors;
619 __le32 tx_one_collision;
620 __le32 tx_multi_collision;
621 __le64 rx_unicast;
622 __le64 rx_broadcast;
623 __le32 rx_multicast;
624 __le16 tx_aborted;
625 __le16 tx_underun;
626 };
627
628 struct rtl8169_tc_offsets {
629 bool inited;
630 __le64 tx_errors;
631 __le32 tx_multi_collision;
632 __le16 tx_aborted;
633 };
634
635 enum rtl_flag {
636 RTL_FLAG_TASK_ENABLED = 0,
637 RTL_FLAG_TASK_RESET_PENDING,
638 RTL_FLAG_MAX
639 };
640
641 struct rtl8169_stats {
642 u64 packets;
643 u64 bytes;
644 struct u64_stats_sync syncp;
645 };
646
647 struct rtl8169_private {
648 void __iomem *mmio_addr;
649 struct pci_dev *pci_dev;
650 struct net_device *dev;
651 struct phy_device *phydev;
652 struct napi_struct napi;
653 u32 msg_enable;
654 enum mac_version mac_version;
655 u32 cur_rx;
656 u32 cur_tx;
657 u32 dirty_tx;
658 struct rtl8169_stats rx_stats;
659 struct rtl8169_stats tx_stats;
660 struct TxDesc *TxDescArray;
661 struct RxDesc *RxDescArray;
662 dma_addr_t TxPhyAddr;
663 dma_addr_t RxPhyAddr;
664 struct page *Rx_databuff[NUM_RX_DESC];
665 struct ring_info tx_skb[NUM_TX_DESC];
666 u16 cp_cmd;
667 u32 irq_mask;
668 struct clk *clk;
669
670 struct {
671 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
672 struct mutex mutex;
673 struct work_struct work;
674 } wk;
675
676 unsigned irq_enabled:1;
677 unsigned supports_gmii:1;
678 unsigned aspm_manageable:1;
679 dma_addr_t counters_phys_addr;
680 struct rtl8169_counters *counters;
681 struct rtl8169_tc_offsets tc_offset;
682 u32 saved_wolopts;
683 int eee_adv;
684
685 const char *fw_name;
686 struct rtl_fw *rtl_fw;
687
688 u32 ocp_base;
689 };
690
691 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
692
693 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
694 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
695 module_param_named(debug, debug.msg_enable, int, 0);
696 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
697 MODULE_SOFTDEP("pre: realtek");
698 MODULE_LICENSE("GPL");
699 MODULE_FIRMWARE(FIRMWARE_8168D_1);
700 MODULE_FIRMWARE(FIRMWARE_8168D_2);
701 MODULE_FIRMWARE(FIRMWARE_8168E_1);
702 MODULE_FIRMWARE(FIRMWARE_8168E_2);
703 MODULE_FIRMWARE(FIRMWARE_8168E_3);
704 MODULE_FIRMWARE(FIRMWARE_8105E_1);
705 MODULE_FIRMWARE(FIRMWARE_8168F_1);
706 MODULE_FIRMWARE(FIRMWARE_8168F_2);
707 MODULE_FIRMWARE(FIRMWARE_8402_1);
708 MODULE_FIRMWARE(FIRMWARE_8411_1);
709 MODULE_FIRMWARE(FIRMWARE_8411_2);
710 MODULE_FIRMWARE(FIRMWARE_8106E_1);
711 MODULE_FIRMWARE(FIRMWARE_8106E_2);
712 MODULE_FIRMWARE(FIRMWARE_8168G_2);
713 MODULE_FIRMWARE(FIRMWARE_8168G_3);
714 MODULE_FIRMWARE(FIRMWARE_8168H_1);
715 MODULE_FIRMWARE(FIRMWARE_8168H_2);
716 MODULE_FIRMWARE(FIRMWARE_8107E_1);
717 MODULE_FIRMWARE(FIRMWARE_8107E_2);
718 MODULE_FIRMWARE(FIRMWARE_8125A_3);
719
720 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
721 {
722 return &tp->pci_dev->dev;
723 }
724
725 static void rtl_lock_work(struct rtl8169_private *tp)
726 {
727 mutex_lock(&tp->wk.mutex);
728 }
729
730 static void rtl_unlock_work(struct rtl8169_private *tp)
731 {
732 mutex_unlock(&tp->wk.mutex);
733 }
734
735 static void rtl_lock_config_regs(struct rtl8169_private *tp)
736 {
737 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
738 }
739
740 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
741 {
742 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
743 }
744
745 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
746 {
747 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
748 PCI_EXP_DEVCTL_READRQ, force);
749 }
750
751 static bool rtl_is_8125(struct rtl8169_private *tp)
752 {
753 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
754 }
755
756 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
757 {
758 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
759 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
760 tp->mac_version <= RTL_GIGA_MAC_VER_51;
761 }
762
763 static bool rtl_supports_eee(struct rtl8169_private *tp)
764 {
765 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
766 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
767 tp->mac_version != RTL_GIGA_MAC_VER_39;
768 }
769
770 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
771 {
772 int i;
773
774 for (i = 0; i < ETH_ALEN; i++)
775 mac[i] = RTL_R8(tp, reg + i);
776 }
777
778 struct rtl_cond {
779 bool (*check)(struct rtl8169_private *);
780 const char *msg;
781 };
782
783 static void rtl_udelay(unsigned int d)
784 {
785 udelay(d);
786 }
787
788 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
789 void (*delay)(unsigned int), unsigned int d, int n,
790 bool high)
791 {
792 int i;
793
794 for (i = 0; i < n; i++) {
795 if (c->check(tp) == high)
796 return true;
797 delay(d);
798 }
799 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
800 c->msg, !high, n, d);
801 return false;
802 }
803
804 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
805 const struct rtl_cond *c,
806 unsigned int d, int n)
807 {
808 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
809 }
810
811 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
812 const struct rtl_cond *c,
813 unsigned int d, int n)
814 {
815 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
816 }
817
818 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
819 const struct rtl_cond *c,
820 unsigned int d, int n)
821 {
822 return rtl_loop_wait(tp, c, msleep, d, n, true);
823 }
824
825 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
826 const struct rtl_cond *c,
827 unsigned int d, int n)
828 {
829 return rtl_loop_wait(tp, c, msleep, d, n, false);
830 }
831
832 #define DECLARE_RTL_COND(name) \
833 static bool name ## _check(struct rtl8169_private *); \
834 \
835 static const struct rtl_cond name = { \
836 .check = name ## _check, \
837 .msg = #name \
838 }; \
839 \
840 static bool name ## _check(struct rtl8169_private *tp)
841
842 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
843 {
844 if (reg & 0xffff0001) {
845 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
846 return true;
847 }
848 return false;
849 }
850
851 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
852 {
853 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
854 }
855
856 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
857 {
858 if (rtl_ocp_reg_failure(tp, reg))
859 return;
860
861 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
862
863 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
864 }
865
866 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
867 {
868 if (rtl_ocp_reg_failure(tp, reg))
869 return 0;
870
871 RTL_W32(tp, GPHY_OCP, reg << 15);
872
873 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
874 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
875 }
876
877 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
878 {
879 if (rtl_ocp_reg_failure(tp, reg))
880 return;
881
882 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
883 }
884
885 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
886 {
887 if (rtl_ocp_reg_failure(tp, reg))
888 return 0;
889
890 RTL_W32(tp, OCPDR, reg << 15);
891
892 return RTL_R32(tp, OCPDR);
893 }
894
895 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
896 u16 set)
897 {
898 u16 data = r8168_mac_ocp_read(tp, reg);
899
900 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
901 }
902
903 #define OCP_STD_PHY_BASE 0xa400
904
905 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
906 {
907 if (reg == 0x1f) {
908 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
909 return;
910 }
911
912 if (tp->ocp_base != OCP_STD_PHY_BASE)
913 reg -= 0x10;
914
915 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
916 }
917
918 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
919 {
920 if (reg == 0x1f)
921 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
922
923 if (tp->ocp_base != OCP_STD_PHY_BASE)
924 reg -= 0x10;
925
926 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
927 }
928
929 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
930 {
931 if (reg == 0x1f) {
932 tp->ocp_base = value << 4;
933 return;
934 }
935
936 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
937 }
938
939 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
940 {
941 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
942 }
943
944 DECLARE_RTL_COND(rtl_phyar_cond)
945 {
946 return RTL_R32(tp, PHYAR) & 0x80000000;
947 }
948
949 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
950 {
951 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
952
953 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
954
955
956
957
958 udelay(20);
959 }
960
961 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
962 {
963 int value;
964
965 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
966
967 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
968 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
969
970
971
972
973
974 udelay(20);
975
976 return value;
977 }
978
979 DECLARE_RTL_COND(rtl_ocpar_cond)
980 {
981 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
982 }
983
984 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
985 {
986 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
987 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
988 RTL_W32(tp, EPHY_RXER_NUM, 0);
989
990 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
991 }
992
993 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
994 {
995 r8168dp_1_mdio_access(tp, reg,
996 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
997 }
998
999 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1000 {
1001 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1002
1003 mdelay(1);
1004 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1005 RTL_W32(tp, EPHY_RXER_NUM, 0);
1006
1007 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1008 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
1009 }
1010
1011 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1012
1013 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1014 {
1015 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1016 }
1017
1018 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1019 {
1020 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1021 }
1022
1023 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1024 {
1025 r8168dp_2_mdio_start(tp);
1026
1027 r8169_mdio_write(tp, reg, value);
1028
1029 r8168dp_2_mdio_stop(tp);
1030 }
1031
1032 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1033 {
1034 int value;
1035
1036
1037 if (reg == MII_PHYSID2)
1038 return 0xc912;
1039
1040 r8168dp_2_mdio_start(tp);
1041
1042 value = r8169_mdio_read(tp, reg);
1043
1044 r8168dp_2_mdio_stop(tp);
1045
1046 return value;
1047 }
1048
1049 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1050 {
1051 switch (tp->mac_version) {
1052 case RTL_GIGA_MAC_VER_27:
1053 r8168dp_1_mdio_write(tp, location, val);
1054 break;
1055 case RTL_GIGA_MAC_VER_28:
1056 case RTL_GIGA_MAC_VER_31:
1057 r8168dp_2_mdio_write(tp, location, val);
1058 break;
1059 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1060 r8168g_mdio_write(tp, location, val);
1061 break;
1062 default:
1063 r8169_mdio_write(tp, location, val);
1064 break;
1065 }
1066 }
1067
1068 static int rtl_readphy(struct rtl8169_private *tp, int location)
1069 {
1070 switch (tp->mac_version) {
1071 case RTL_GIGA_MAC_VER_27:
1072 return r8168dp_1_mdio_read(tp, location);
1073 case RTL_GIGA_MAC_VER_28:
1074 case RTL_GIGA_MAC_VER_31:
1075 return r8168dp_2_mdio_read(tp, location);
1076 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1077 return r8168g_mdio_read(tp, location);
1078 default:
1079 return r8169_mdio_read(tp, location);
1080 }
1081 }
1082
1083 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1084 {
1085 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1086 }
1087
1088 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1089 {
1090 int val;
1091
1092 val = rtl_readphy(tp, reg_addr);
1093 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1094 }
1095
1096 DECLARE_RTL_COND(rtl_ephyar_cond)
1097 {
1098 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1099 }
1100
1101 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1102 {
1103 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1104 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1105
1106 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1107
1108 udelay(10);
1109 }
1110
1111 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1112 {
1113 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1114
1115 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1116 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1117 }
1118
1119 DECLARE_RTL_COND(rtl_eriar_cond)
1120 {
1121 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1122 }
1123
1124 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1125 u32 val, int type)
1126 {
1127 BUG_ON((addr & 3) || (mask == 0));
1128 RTL_W32(tp, ERIDR, val);
1129 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1130
1131 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1132 }
1133
1134 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1135 u32 val)
1136 {
1137 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1138 }
1139
1140 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1141 {
1142 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1143
1144 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1145 RTL_R32(tp, ERIDR) : ~0;
1146 }
1147
1148 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1149 {
1150 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1151 }
1152
1153 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1154 u32 m)
1155 {
1156 u32 val;
1157
1158 val = rtl_eri_read(tp, addr);
1159 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1160 }
1161
1162 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1163 u32 p)
1164 {
1165 rtl_w0w1_eri(tp, addr, mask, p, 0);
1166 }
1167
1168 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1169 u32 m)
1170 {
1171 rtl_w0w1_eri(tp, addr, mask, 0, m);
1172 }
1173
1174 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1175 {
1176 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1177 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1178 RTL_R32(tp, OCPDR) : ~0;
1179 }
1180
1181 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1182 {
1183 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1184 }
1185
1186 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1187 u32 data)
1188 {
1189 RTL_W32(tp, OCPDR, data);
1190 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1191 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1192 }
1193
1194 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1195 u32 data)
1196 {
1197 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1198 data, ERIAR_OOB);
1199 }
1200
1201 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1202 {
1203 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1204
1205 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1206 }
1207
1208 #define OOB_CMD_RESET 0x00
1209 #define OOB_CMD_DRIVER_START 0x05
1210 #define OOB_CMD_DRIVER_STOP 0x06
1211
1212 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1213 {
1214 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1215 }
1216
1217 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1218 {
1219 u16 reg;
1220
1221 reg = rtl8168_get_ocp_reg(tp);
1222
1223 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1224 }
1225
1226 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1227 {
1228 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1229 }
1230
1231 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1232 {
1233 return RTL_R8(tp, IBISR0) & 0x20;
1234 }
1235
1236 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1237 {
1238 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1239 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1240 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1241 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1242 }
1243
1244 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1245 {
1246 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1247 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1248 }
1249
1250 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1251 {
1252 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1253 r8168ep_ocp_write(tp, 0x01, 0x30,
1254 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1255 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1256 }
1257
1258 static void rtl8168_driver_start(struct rtl8169_private *tp)
1259 {
1260 switch (tp->mac_version) {
1261 case RTL_GIGA_MAC_VER_27:
1262 case RTL_GIGA_MAC_VER_28:
1263 case RTL_GIGA_MAC_VER_31:
1264 rtl8168dp_driver_start(tp);
1265 break;
1266 case RTL_GIGA_MAC_VER_49:
1267 case RTL_GIGA_MAC_VER_50:
1268 case RTL_GIGA_MAC_VER_51:
1269 rtl8168ep_driver_start(tp);
1270 break;
1271 default:
1272 BUG();
1273 break;
1274 }
1275 }
1276
1277 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1278 {
1279 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1280 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1281 }
1282
1283 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1284 {
1285 rtl8168ep_stop_cmac(tp);
1286 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1287 r8168ep_ocp_write(tp, 0x01, 0x30,
1288 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1289 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1290 }
1291
1292 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1293 {
1294 switch (tp->mac_version) {
1295 case RTL_GIGA_MAC_VER_27:
1296 case RTL_GIGA_MAC_VER_28:
1297 case RTL_GIGA_MAC_VER_31:
1298 rtl8168dp_driver_stop(tp);
1299 break;
1300 case RTL_GIGA_MAC_VER_49:
1301 case RTL_GIGA_MAC_VER_50:
1302 case RTL_GIGA_MAC_VER_51:
1303 rtl8168ep_driver_stop(tp);
1304 break;
1305 default:
1306 BUG();
1307 break;
1308 }
1309 }
1310
1311 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1312 {
1313 u16 reg = rtl8168_get_ocp_reg(tp);
1314
1315 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1316 }
1317
1318 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1319 {
1320 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1321 }
1322
1323 static bool r8168_check_dash(struct rtl8169_private *tp)
1324 {
1325 switch (tp->mac_version) {
1326 case RTL_GIGA_MAC_VER_27:
1327 case RTL_GIGA_MAC_VER_28:
1328 case RTL_GIGA_MAC_VER_31:
1329 return r8168dp_check_dash(tp);
1330 case RTL_GIGA_MAC_VER_49:
1331 case RTL_GIGA_MAC_VER_50:
1332 case RTL_GIGA_MAC_VER_51:
1333 return r8168ep_check_dash(tp);
1334 default:
1335 return false;
1336 }
1337 }
1338
1339 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1340 {
1341 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1342 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1343 }
1344
1345 DECLARE_RTL_COND(rtl_efusear_cond)
1346 {
1347 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1348 }
1349
1350 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1351 {
1352 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1353
1354 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1355 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1356 }
1357
1358 static u32 rtl_get_events(struct rtl8169_private *tp)
1359 {
1360 if (rtl_is_8125(tp))
1361 return RTL_R32(tp, IntrStatus_8125);
1362 else
1363 return RTL_R16(tp, IntrStatus);
1364 }
1365
1366 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1367 {
1368 if (rtl_is_8125(tp))
1369 RTL_W32(tp, IntrStatus_8125, bits);
1370 else
1371 RTL_W16(tp, IntrStatus, bits);
1372 }
1373
1374 static void rtl_irq_disable(struct rtl8169_private *tp)
1375 {
1376 if (rtl_is_8125(tp))
1377 RTL_W32(tp, IntrMask_8125, 0);
1378 else
1379 RTL_W16(tp, IntrMask, 0);
1380 tp->irq_enabled = 0;
1381 }
1382
1383 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1384 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1385 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1386
1387 static void rtl_irq_enable(struct rtl8169_private *tp)
1388 {
1389 tp->irq_enabled = 1;
1390 if (rtl_is_8125(tp))
1391 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1392 else
1393 RTL_W16(tp, IntrMask, tp->irq_mask);
1394 }
1395
1396 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1397 {
1398 rtl_irq_disable(tp);
1399 rtl_ack_events(tp, 0xffffffff);
1400
1401 RTL_R8(tp, ChipCmd);
1402 }
1403
1404 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1405 {
1406 struct net_device *dev = tp->dev;
1407 struct phy_device *phydev = tp->phydev;
1408
1409 if (!netif_running(dev))
1410 return;
1411
1412 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1413 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1414 if (phydev->speed == SPEED_1000) {
1415 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1416 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1417 } else if (phydev->speed == SPEED_100) {
1418 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1419 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1420 } else {
1421 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1422 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1423 }
1424 rtl_reset_packet_filter(tp);
1425 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1426 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1427 if (phydev->speed == SPEED_1000) {
1428 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1429 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1430 } else {
1431 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1432 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1433 }
1434 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1435 if (phydev->speed == SPEED_10) {
1436 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1437 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1438 } else {
1439 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1440 }
1441 }
1442 }
1443
1444 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1445
1446 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1447 {
1448 struct rtl8169_private *tp = netdev_priv(dev);
1449
1450 rtl_lock_work(tp);
1451 wol->supported = WAKE_ANY;
1452 wol->wolopts = tp->saved_wolopts;
1453 rtl_unlock_work(tp);
1454 }
1455
1456 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1457 {
1458 static const struct {
1459 u32 opt;
1460 u16 reg;
1461 u8 mask;
1462 } cfg[] = {
1463 { WAKE_PHY, Config3, LinkUp },
1464 { WAKE_UCAST, Config5, UWF },
1465 { WAKE_BCAST, Config5, BWF },
1466 { WAKE_MCAST, Config5, MWF },
1467 { WAKE_ANY, Config5, LanWake },
1468 { WAKE_MAGIC, Config3, MagicPacket }
1469 };
1470 unsigned int i, tmp = ARRAY_SIZE(cfg);
1471 u8 options;
1472
1473 rtl_unlock_config_regs(tp);
1474
1475 if (rtl_is_8168evl_up(tp)) {
1476 tmp--;
1477 if (wolopts & WAKE_MAGIC)
1478 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1479 MagicPacket_v2);
1480 else
1481 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1482 MagicPacket_v2);
1483 } else if (rtl_is_8125(tp)) {
1484 tmp--;
1485 if (wolopts & WAKE_MAGIC)
1486 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1487 else
1488 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1489 }
1490
1491 for (i = 0; i < tmp; i++) {
1492 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1493 if (wolopts & cfg[i].opt)
1494 options |= cfg[i].mask;
1495 RTL_W8(tp, cfg[i].reg, options);
1496 }
1497
1498 switch (tp->mac_version) {
1499 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1500 options = RTL_R8(tp, Config1) & ~PMEnable;
1501 if (wolopts)
1502 options |= PMEnable;
1503 RTL_W8(tp, Config1, options);
1504 break;
1505 case RTL_GIGA_MAC_VER_34:
1506 case RTL_GIGA_MAC_VER_37:
1507 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51:
1508 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1509 if (wolopts)
1510 options |= PME_SIGNAL;
1511 RTL_W8(tp, Config2, options);
1512 break;
1513 default:
1514 break;
1515 }
1516
1517 rtl_lock_config_regs(tp);
1518
1519 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1520 tp->dev->wol_enabled = wolopts ? 1 : 0;
1521 }
1522
1523 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1524 {
1525 struct rtl8169_private *tp = netdev_priv(dev);
1526 struct device *d = tp_to_dev(tp);
1527
1528 if (wol->wolopts & ~WAKE_ANY)
1529 return -EINVAL;
1530
1531 pm_runtime_get_noresume(d);
1532
1533 rtl_lock_work(tp);
1534
1535 tp->saved_wolopts = wol->wolopts;
1536
1537 if (pm_runtime_active(d))
1538 __rtl8169_set_wol(tp, tp->saved_wolopts);
1539
1540 rtl_unlock_work(tp);
1541
1542 pm_runtime_put_noidle(d);
1543
1544 return 0;
1545 }
1546
1547 static void rtl8169_get_drvinfo(struct net_device *dev,
1548 struct ethtool_drvinfo *info)
1549 {
1550 struct rtl8169_private *tp = netdev_priv(dev);
1551 struct rtl_fw *rtl_fw = tp->rtl_fw;
1552
1553 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1554 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1555 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1556 if (rtl_fw)
1557 strlcpy(info->fw_version, rtl_fw->version,
1558 sizeof(info->fw_version));
1559 }
1560
1561 static int rtl8169_get_regs_len(struct net_device *dev)
1562 {
1563 return R8169_REGS_SIZE;
1564 }
1565
1566 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1567 netdev_features_t features)
1568 {
1569 struct rtl8169_private *tp = netdev_priv(dev);
1570
1571 if (dev->mtu > TD_MSS_MAX)
1572 features &= ~NETIF_F_ALL_TSO;
1573
1574 if (dev->mtu > JUMBO_1K &&
1575 tp->mac_version > RTL_GIGA_MAC_VER_06)
1576 features &= ~NETIF_F_IP_CSUM;
1577
1578 return features;
1579 }
1580
1581 static int rtl8169_set_features(struct net_device *dev,
1582 netdev_features_t features)
1583 {
1584 struct rtl8169_private *tp = netdev_priv(dev);
1585 u32 rx_config;
1586
1587 rtl_lock_work(tp);
1588
1589 rx_config = RTL_R32(tp, RxConfig);
1590 if (features & NETIF_F_RXALL)
1591 rx_config |= (AcceptErr | AcceptRunt);
1592 else
1593 rx_config &= ~(AcceptErr | AcceptRunt);
1594
1595 if (rtl_is_8125(tp)) {
1596 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1597 rx_config |= RX_VLAN_8125;
1598 else
1599 rx_config &= ~RX_VLAN_8125;
1600 }
1601
1602 RTL_W32(tp, RxConfig, rx_config);
1603
1604 if (features & NETIF_F_RXCSUM)
1605 tp->cp_cmd |= RxChkSum;
1606 else
1607 tp->cp_cmd &= ~RxChkSum;
1608
1609 if (!rtl_is_8125(tp)) {
1610 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1611 tp->cp_cmd |= RxVlan;
1612 else
1613 tp->cp_cmd &= ~RxVlan;
1614 }
1615
1616 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1617 RTL_R16(tp, CPlusCmd);
1618
1619 rtl_unlock_work(tp);
1620
1621 return 0;
1622 }
1623
1624 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1625 {
1626 return (skb_vlan_tag_present(skb)) ?
1627 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1628 }
1629
1630 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1631 {
1632 u32 opts2 = le32_to_cpu(desc->opts2);
1633
1634 if (opts2 & RxVlanTag)
1635 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1636 }
1637
1638 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1639 void *p)
1640 {
1641 struct rtl8169_private *tp = netdev_priv(dev);
1642 u32 __iomem *data = tp->mmio_addr;
1643 u32 *dw = p;
1644 int i;
1645
1646 rtl_lock_work(tp);
1647 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1648 memcpy_fromio(dw++, data++, 4);
1649 rtl_unlock_work(tp);
1650 }
1651
1652 static u32 rtl8169_get_msglevel(struct net_device *dev)
1653 {
1654 struct rtl8169_private *tp = netdev_priv(dev);
1655
1656 return tp->msg_enable;
1657 }
1658
1659 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1660 {
1661 struct rtl8169_private *tp = netdev_priv(dev);
1662
1663 tp->msg_enable = value;
1664 }
1665
1666 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1667 "tx_packets",
1668 "rx_packets",
1669 "tx_errors",
1670 "rx_errors",
1671 "rx_missed",
1672 "align_errors",
1673 "tx_single_collisions",
1674 "tx_multi_collisions",
1675 "unicast",
1676 "broadcast",
1677 "multicast",
1678 "tx_aborted",
1679 "tx_underrun",
1680 };
1681
1682 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1683 {
1684 switch (sset) {
1685 case ETH_SS_STATS:
1686 return ARRAY_SIZE(rtl8169_gstrings);
1687 default:
1688 return -EOPNOTSUPP;
1689 }
1690 }
1691
1692 DECLARE_RTL_COND(rtl_counters_cond)
1693 {
1694 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1695 }
1696
1697 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1698 {
1699 dma_addr_t paddr = tp->counters_phys_addr;
1700 u32 cmd;
1701
1702 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1703 RTL_R32(tp, CounterAddrHigh);
1704 cmd = (u64)paddr & DMA_BIT_MASK(32);
1705 RTL_W32(tp, CounterAddrLow, cmd);
1706 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1707
1708 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1709 }
1710
1711 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1712 {
1713
1714
1715
1716
1717 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1718 return true;
1719
1720 return rtl8169_do_counters(tp, CounterReset);
1721 }
1722
1723 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1724 {
1725 u8 val = RTL_R8(tp, ChipCmd);
1726
1727
1728
1729
1730
1731 if (!(val & CmdRxEnb) || val == 0xff)
1732 return true;
1733
1734 return rtl8169_do_counters(tp, CounterDump);
1735 }
1736
1737 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1738 {
1739 struct rtl8169_counters *counters = tp->counters;
1740 bool ret = false;
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757 if (tp->tc_offset.inited)
1758 return true;
1759
1760
1761 if (rtl8169_reset_counters(tp))
1762 ret = true;
1763
1764 if (rtl8169_update_counters(tp))
1765 ret = true;
1766
1767 tp->tc_offset.tx_errors = counters->tx_errors;
1768 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1769 tp->tc_offset.tx_aborted = counters->tx_aborted;
1770 tp->tc_offset.inited = true;
1771
1772 return ret;
1773 }
1774
1775 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1776 struct ethtool_stats *stats, u64 *data)
1777 {
1778 struct rtl8169_private *tp = netdev_priv(dev);
1779 struct device *d = tp_to_dev(tp);
1780 struct rtl8169_counters *counters = tp->counters;
1781
1782 ASSERT_RTNL();
1783
1784 pm_runtime_get_noresume(d);
1785
1786 if (pm_runtime_active(d))
1787 rtl8169_update_counters(tp);
1788
1789 pm_runtime_put_noidle(d);
1790
1791 data[0] = le64_to_cpu(counters->tx_packets);
1792 data[1] = le64_to_cpu(counters->rx_packets);
1793 data[2] = le64_to_cpu(counters->tx_errors);
1794 data[3] = le32_to_cpu(counters->rx_errors);
1795 data[4] = le16_to_cpu(counters->rx_missed);
1796 data[5] = le16_to_cpu(counters->align_errors);
1797 data[6] = le32_to_cpu(counters->tx_one_collision);
1798 data[7] = le32_to_cpu(counters->tx_multi_collision);
1799 data[8] = le64_to_cpu(counters->rx_unicast);
1800 data[9] = le64_to_cpu(counters->rx_broadcast);
1801 data[10] = le32_to_cpu(counters->rx_multicast);
1802 data[11] = le16_to_cpu(counters->tx_aborted);
1803 data[12] = le16_to_cpu(counters->tx_underun);
1804 }
1805
1806 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1807 {
1808 switch(stringset) {
1809 case ETH_SS_STATS:
1810 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1811 break;
1812 }
1813 }
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844 struct rtl_coalesce_scale {
1845
1846 u32 nsecs[2];
1847 };
1848
1849
1850 struct rtl_coalesce_info {
1851 u32 speed;
1852 struct rtl_coalesce_scale scalev[4];
1853 };
1854
1855
1856 #define rxtx_x1822(r, t) { \
1857 {{(r), (t)}}, \
1858 {{(r)*8, (t)*8}}, \
1859 {{(r)*8*2, (t)*8*2}}, \
1860 {{(r)*8*2*2, (t)*8*2*2}}, \
1861 }
1862 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1863
1864 { SPEED_10, rxtx_x1822(40960, 40960) },
1865 { SPEED_100, rxtx_x1822( 2560, 2560) },
1866 { SPEED_1000, rxtx_x1822( 320, 320) },
1867 { 0 },
1868 };
1869
1870 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1871
1872 { SPEED_10, rxtx_x1822(40960, 40960) },
1873 { SPEED_100, rxtx_x1822( 2560, 2560) },
1874 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1875 { 0 },
1876 };
1877 #undef rxtx_x1822
1878
1879
1880 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1881 {
1882 struct rtl8169_private *tp = netdev_priv(dev);
1883 const struct rtl_coalesce_info *ci;
1884
1885 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1886 ci = rtl_coalesce_info_8169;
1887 else
1888 ci = rtl_coalesce_info_8168_8136;
1889
1890 for (; ci->speed; ci++) {
1891 if (tp->phydev->speed == ci->speed)
1892 return ci;
1893 }
1894
1895 return ERR_PTR(-ELNRNG);
1896 }
1897
1898 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1899 {
1900 struct rtl8169_private *tp = netdev_priv(dev);
1901 const struct rtl_coalesce_info *ci;
1902 const struct rtl_coalesce_scale *scale;
1903 struct {
1904 u32 *max_frames;
1905 u32 *usecs;
1906 } coal_settings [] = {
1907 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1908 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1909 }, *p = coal_settings;
1910 int i;
1911 u16 w;
1912
1913 if (rtl_is_8125(tp))
1914 return -EOPNOTSUPP;
1915
1916 memset(ec, 0, sizeof(*ec));
1917
1918
1919 ci = rtl_coalesce_info(dev);
1920 if (IS_ERR(ci))
1921 return PTR_ERR(ci);
1922
1923 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1924
1925
1926 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1927 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1928 w >>= RTL_COALESCE_SHIFT;
1929 *p->usecs = w & RTL_COALESCE_MASK;
1930 }
1931
1932 for (i = 0; i < 2; i++) {
1933 p = coal_settings + i;
1934 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1935
1936
1937
1938
1939
1940 if (!*p->usecs && !*p->max_frames)
1941 *p->max_frames = 1;
1942 }
1943
1944 return 0;
1945 }
1946
1947
1948 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1949 struct net_device *dev, u32 nsec, u16 *cp01)
1950 {
1951 const struct rtl_coalesce_info *ci;
1952 u16 i;
1953
1954 ci = rtl_coalesce_info(dev);
1955 if (IS_ERR(ci))
1956 return ERR_CAST(ci);
1957
1958 for (i = 0; i < 4; i++) {
1959 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1960 ci->scalev[i].nsecs[1]);
1961 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1962 *cp01 = i;
1963 return &ci->scalev[i];
1964 }
1965 }
1966
1967 return ERR_PTR(-EINVAL);
1968 }
1969
1970 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1971 {
1972 struct rtl8169_private *tp = netdev_priv(dev);
1973 const struct rtl_coalesce_scale *scale;
1974 struct {
1975 u32 frames;
1976 u32 usecs;
1977 } coal_settings [] = {
1978 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1979 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1980 }, *p = coal_settings;
1981 u16 w = 0, cp01;
1982 int i;
1983
1984 if (rtl_is_8125(tp))
1985 return -EOPNOTSUPP;
1986
1987 scale = rtl_coalesce_choose_scale(dev,
1988 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1989 if (IS_ERR(scale))
1990 return PTR_ERR(scale);
1991
1992 for (i = 0; i < 2; i++, p++) {
1993 u32 units;
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007 if (p->frames == 1) {
2008 p->frames = 0;
2009 }
2010
2011 units = p->usecs * 1000 / scale->nsecs[i];
2012 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2013 return -EINVAL;
2014
2015 w <<= RTL_COALESCE_SHIFT;
2016 w |= units;
2017 w <<= RTL_COALESCE_SHIFT;
2018 w |= p->frames >> 2;
2019 }
2020
2021 rtl_lock_work(tp);
2022
2023 RTL_W16(tp, IntrMitigate, swab16(w));
2024
2025 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2026 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2027 RTL_R16(tp, CPlusCmd);
2028
2029 rtl_unlock_work(tp);
2030
2031 return 0;
2032 }
2033
2034 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2035 {
2036 struct rtl8169_private *tp = netdev_priv(dev);
2037 struct device *d = tp_to_dev(tp);
2038 int ret;
2039
2040 if (!rtl_supports_eee(tp))
2041 return -EOPNOTSUPP;
2042
2043 pm_runtime_get_noresume(d);
2044
2045 if (!pm_runtime_active(d)) {
2046 ret = -EOPNOTSUPP;
2047 } else {
2048 ret = phy_ethtool_get_eee(tp->phydev, data);
2049 }
2050
2051 pm_runtime_put_noidle(d);
2052
2053 return ret;
2054 }
2055
2056 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2057 {
2058 struct rtl8169_private *tp = netdev_priv(dev);
2059 struct device *d = tp_to_dev(tp);
2060 int ret;
2061
2062 if (!rtl_supports_eee(tp))
2063 return -EOPNOTSUPP;
2064
2065 pm_runtime_get_noresume(d);
2066
2067 if (!pm_runtime_active(d)) {
2068 ret = -EOPNOTSUPP;
2069 goto out;
2070 }
2071
2072 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2073 dev->phydev->duplex != DUPLEX_FULL) {
2074 ret = -EPROTONOSUPPORT;
2075 goto out;
2076 }
2077
2078 ret = phy_ethtool_set_eee(tp->phydev, data);
2079
2080 if (!ret)
2081 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
2082 MDIO_AN_EEE_ADV);
2083 out:
2084 pm_runtime_put_noidle(d);
2085 return ret;
2086 }
2087
2088 static const struct ethtool_ops rtl8169_ethtool_ops = {
2089 .get_drvinfo = rtl8169_get_drvinfo,
2090 .get_regs_len = rtl8169_get_regs_len,
2091 .get_link = ethtool_op_get_link,
2092 .get_coalesce = rtl_get_coalesce,
2093 .set_coalesce = rtl_set_coalesce,
2094 .get_msglevel = rtl8169_get_msglevel,
2095 .set_msglevel = rtl8169_set_msglevel,
2096 .get_regs = rtl8169_get_regs,
2097 .get_wol = rtl8169_get_wol,
2098 .set_wol = rtl8169_set_wol,
2099 .get_strings = rtl8169_get_strings,
2100 .get_sset_count = rtl8169_get_sset_count,
2101 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2102 .get_ts_info = ethtool_op_get_ts_info,
2103 .nway_reset = phy_ethtool_nway_reset,
2104 .get_eee = rtl8169_get_eee,
2105 .set_eee = rtl8169_set_eee,
2106 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2107 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2108 };
2109
2110 static void rtl_enable_eee(struct rtl8169_private *tp)
2111 {
2112 struct phy_device *phydev = tp->phydev;
2113 int adv;
2114
2115
2116 if (tp->eee_adv >= 0)
2117 adv = tp->eee_adv;
2118 else
2119 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2120
2121 if (adv >= 0)
2122 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
2123 }
2124
2125 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2126 {
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138 static const struct rtl_mac_info {
2139 u16 mask;
2140 u16 val;
2141 u16 mac_version;
2142 } mac_info[] = {
2143
2144 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2145 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2146
2147
2148 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2149 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2150 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2151
2152
2153 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2154 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2155
2156
2157 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2158 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2159 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2160 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2161
2162
2163 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2164 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2165 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2166
2167
2168 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2169 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2170 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2171
2172
2173 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2174 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2175
2176
2177 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2178 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2179 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2180
2181
2182 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2183 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2184 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2185 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2186 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2187 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2188 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2189
2190
2191 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2192 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2193 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2194
2195
2196 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2197 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2198 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2199 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2200 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2201 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2202 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2203 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2204 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2205
2206 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_13 },
2207 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2208 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2209 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2210 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2211 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2212
2213 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2214 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2215
2216
2217 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2218 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2219 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2220 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2221 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2222
2223
2224 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2225 };
2226 const struct rtl_mac_info *p = mac_info;
2227 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2228
2229 while ((reg & p->mask) != p->val)
2230 p++;
2231 tp->mac_version = p->mac_version;
2232
2233 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2234 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2235 } else if (!tp->supports_gmii) {
2236 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2237 tp->mac_version = RTL_GIGA_MAC_VER_43;
2238 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2239 tp->mac_version = RTL_GIGA_MAC_VER_47;
2240 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2241 tp->mac_version = RTL_GIGA_MAC_VER_48;
2242 }
2243 }
2244
2245 struct phy_reg {
2246 u16 reg;
2247 u16 val;
2248 };
2249
2250 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2251 const struct phy_reg *regs, int len)
2252 {
2253 while (len-- > 0) {
2254 rtl_writephy(tp, regs->reg, regs->val);
2255 regs++;
2256 }
2257 }
2258
2259 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2260
2261 static void rtl_release_firmware(struct rtl8169_private *tp)
2262 {
2263 if (tp->rtl_fw) {
2264 rtl_fw_release_firmware(tp->rtl_fw);
2265 kfree(tp->rtl_fw);
2266 tp->rtl_fw = NULL;
2267 }
2268 }
2269
2270 static void rtl_apply_firmware(struct rtl8169_private *tp)
2271 {
2272
2273 if (tp->rtl_fw)
2274 rtl_fw_write_firmware(tp, tp->rtl_fw);
2275 }
2276
2277 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2278 {
2279 if (rtl_readphy(tp, reg) != val)
2280 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2281 else
2282 rtl_apply_firmware(tp);
2283 }
2284
2285 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2286 {
2287
2288 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2289 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2290
2291 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2292 }
2293
2294 static void rtl8125_config_eee_mac(struct rtl8169_private *tp)
2295 {
2296 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2297 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2298 }
2299
2300 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2301 {
2302 struct phy_device *phydev = tp->phydev;
2303
2304 phy_write(phydev, 0x1f, 0x0007);
2305 phy_write(phydev, 0x1e, 0x0020);
2306 phy_set_bits(phydev, 0x15, BIT(8));
2307
2308 phy_write(phydev, 0x1f, 0x0005);
2309 phy_write(phydev, 0x05, 0x8b85);
2310 phy_set_bits(phydev, 0x06, BIT(13));
2311
2312 phy_write(phydev, 0x1f, 0x0000);
2313 }
2314
2315 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2316 {
2317 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2318 }
2319
2320 static void rtl8168h_config_eee_phy(struct rtl8169_private *tp)
2321 {
2322 struct phy_device *phydev = tp->phydev;
2323
2324 rtl8168g_config_eee_phy(tp);
2325
2326 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
2327 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
2328 }
2329
2330 static void rtl8125_config_eee_phy(struct rtl8169_private *tp)
2331 {
2332 struct phy_device *phydev = tp->phydev;
2333
2334 rtl8168h_config_eee_phy(tp);
2335
2336 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000);
2337 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
2338 }
2339
2340 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2341 {
2342 static const struct phy_reg phy_reg_init[] = {
2343 { 0x1f, 0x0001 },
2344 { 0x06, 0x006e },
2345 { 0x08, 0x0708 },
2346 { 0x15, 0x4000 },
2347 { 0x18, 0x65c7 },
2348
2349 { 0x1f, 0x0001 },
2350 { 0x03, 0x00a1 },
2351 { 0x02, 0x0008 },
2352 { 0x01, 0x0120 },
2353 { 0x00, 0x1000 },
2354 { 0x04, 0x0800 },
2355 { 0x04, 0x0000 },
2356
2357 { 0x03, 0xff41 },
2358 { 0x02, 0xdf60 },
2359 { 0x01, 0x0140 },
2360 { 0x00, 0x0077 },
2361 { 0x04, 0x7800 },
2362 { 0x04, 0x7000 },
2363
2364 { 0x03, 0x802f },
2365 { 0x02, 0x4f02 },
2366 { 0x01, 0x0409 },
2367 { 0x00, 0xf0f9 },
2368 { 0x04, 0x9800 },
2369 { 0x04, 0x9000 },
2370
2371 { 0x03, 0xdf01 },
2372 { 0x02, 0xdf20 },
2373 { 0x01, 0xff95 },
2374 { 0x00, 0xba00 },
2375 { 0x04, 0xa800 },
2376 { 0x04, 0xa000 },
2377
2378 { 0x03, 0xff41 },
2379 { 0x02, 0xdf20 },
2380 { 0x01, 0x0140 },
2381 { 0x00, 0x00bb },
2382 { 0x04, 0xb800 },
2383 { 0x04, 0xb000 },
2384
2385 { 0x03, 0xdf41 },
2386 { 0x02, 0xdc60 },
2387 { 0x01, 0x6340 },
2388 { 0x00, 0x007d },
2389 { 0x04, 0xd800 },
2390 { 0x04, 0xd000 },
2391
2392 { 0x03, 0xdf01 },
2393 { 0x02, 0xdf20 },
2394 { 0x01, 0x100a },
2395 { 0x00, 0xa0ff },
2396 { 0x04, 0xf800 },
2397 { 0x04, 0xf000 },
2398
2399 { 0x1f, 0x0000 },
2400 { 0x0b, 0x0000 },
2401 { 0x00, 0x9200 }
2402 };
2403
2404 rtl_writephy_batch(tp, phy_reg_init);
2405 }
2406
2407 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2408 {
2409 static const struct phy_reg phy_reg_init[] = {
2410 { 0x1f, 0x0002 },
2411 { 0x01, 0x90d0 },
2412 { 0x1f, 0x0000 }
2413 };
2414
2415 rtl_writephy_batch(tp, phy_reg_init);
2416 }
2417
2418 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2419 {
2420 struct pci_dev *pdev = tp->pci_dev;
2421
2422 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2423 (pdev->subsystem_device != 0xe000))
2424 return;
2425
2426 rtl_writephy(tp, 0x1f, 0x0001);
2427 rtl_writephy(tp, 0x10, 0xf01b);
2428 rtl_writephy(tp, 0x1f, 0x0000);
2429 }
2430
2431 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2432 {
2433 static const struct phy_reg phy_reg_init[] = {
2434 { 0x1f, 0x0001 },
2435 { 0x04, 0x0000 },
2436 { 0x03, 0x00a1 },
2437 { 0x02, 0x0008 },
2438 { 0x01, 0x0120 },
2439 { 0x00, 0x1000 },
2440 { 0x04, 0x0800 },
2441 { 0x04, 0x9000 },
2442 { 0x03, 0x802f },
2443 { 0x02, 0x4f02 },
2444 { 0x01, 0x0409 },
2445 { 0x00, 0xf099 },
2446 { 0x04, 0x9800 },
2447 { 0x04, 0xa000 },
2448 { 0x03, 0xdf01 },
2449 { 0x02, 0xdf20 },
2450 { 0x01, 0xff95 },
2451 { 0x00, 0xba00 },
2452 { 0x04, 0xa800 },
2453 { 0x04, 0xf000 },
2454 { 0x03, 0xdf01 },
2455 { 0x02, 0xdf20 },
2456 { 0x01, 0x101a },
2457 { 0x00, 0xa0ff },
2458 { 0x04, 0xf800 },
2459 { 0x04, 0x0000 },
2460 { 0x1f, 0x0000 },
2461
2462 { 0x1f, 0x0001 },
2463 { 0x10, 0xf41b },
2464 { 0x14, 0xfb54 },
2465 { 0x18, 0xf5c7 },
2466 { 0x1f, 0x0000 },
2467
2468 { 0x1f, 0x0001 },
2469 { 0x17, 0x0cc0 },
2470 { 0x1f, 0x0000 }
2471 };
2472
2473 rtl_writephy_batch(tp, phy_reg_init);
2474
2475 rtl8169scd_hw_phy_config_quirk(tp);
2476 }
2477
2478 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2479 {
2480 static const struct phy_reg phy_reg_init[] = {
2481 { 0x1f, 0x0001 },
2482 { 0x04, 0x0000 },
2483 { 0x03, 0x00a1 },
2484 { 0x02, 0x0008 },
2485 { 0x01, 0x0120 },
2486 { 0x00, 0x1000 },
2487 { 0x04, 0x0800 },
2488 { 0x04, 0x9000 },
2489 { 0x03, 0x802f },
2490 { 0x02, 0x4f02 },
2491 { 0x01, 0x0409 },
2492 { 0x00, 0xf099 },
2493 { 0x04, 0x9800 },
2494 { 0x04, 0xa000 },
2495 { 0x03, 0xdf01 },
2496 { 0x02, 0xdf20 },
2497 { 0x01, 0xff95 },
2498 { 0x00, 0xba00 },
2499 { 0x04, 0xa800 },
2500 { 0x04, 0xf000 },
2501 { 0x03, 0xdf01 },
2502 { 0x02, 0xdf20 },
2503 { 0x01, 0x101a },
2504 { 0x00, 0xa0ff },
2505 { 0x04, 0xf800 },
2506 { 0x04, 0x0000 },
2507 { 0x1f, 0x0000 },
2508
2509 { 0x1f, 0x0001 },
2510 { 0x0b, 0x8480 },
2511 { 0x1f, 0x0000 },
2512
2513 { 0x1f, 0x0001 },
2514 { 0x18, 0x67c7 },
2515 { 0x04, 0x2000 },
2516 { 0x03, 0x002f },
2517 { 0x02, 0x4360 },
2518 { 0x01, 0x0109 },
2519 { 0x00, 0x3022 },
2520 { 0x04, 0x2800 },
2521 { 0x1f, 0x0000 },
2522
2523 { 0x1f, 0x0001 },
2524 { 0x17, 0x0cc0 },
2525 { 0x1f, 0x0000 }
2526 };
2527
2528 rtl_writephy_batch(tp, phy_reg_init);
2529 }
2530
2531 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2532 {
2533 static const struct phy_reg phy_reg_init[] = {
2534 { 0x10, 0xf41b },
2535 { 0x1f, 0x0000 }
2536 };
2537
2538 rtl_writephy(tp, 0x1f, 0x0001);
2539 rtl_patchphy(tp, 0x16, 1 << 0);
2540
2541 rtl_writephy_batch(tp, phy_reg_init);
2542 }
2543
2544 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2545 {
2546 static const struct phy_reg phy_reg_init[] = {
2547 { 0x1f, 0x0001 },
2548 { 0x10, 0xf41b },
2549 { 0x1f, 0x0000 }
2550 };
2551
2552 rtl_writephy_batch(tp, phy_reg_init);
2553 }
2554
2555 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2556 {
2557 static const struct phy_reg phy_reg_init[] = {
2558 { 0x1f, 0x0000 },
2559 { 0x1d, 0x0f00 },
2560 { 0x1f, 0x0002 },
2561 { 0x0c, 0x1ec8 },
2562 { 0x1f, 0x0000 }
2563 };
2564
2565 rtl_writephy_batch(tp, phy_reg_init);
2566 }
2567
2568 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2569 {
2570 static const struct phy_reg phy_reg_init[] = {
2571 { 0x1f, 0x0001 },
2572 { 0x1d, 0x3d98 },
2573 { 0x1f, 0x0000 }
2574 };
2575
2576 rtl_writephy(tp, 0x1f, 0x0000);
2577 rtl_patchphy(tp, 0x14, 1 << 5);
2578 rtl_patchphy(tp, 0x0d, 1 << 5);
2579
2580 rtl_writephy_batch(tp, phy_reg_init);
2581 }
2582
2583 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2584 {
2585 static const struct phy_reg phy_reg_init[] = {
2586 { 0x1f, 0x0001 },
2587 { 0x12, 0x2300 },
2588 { 0x1f, 0x0002 },
2589 { 0x00, 0x88d4 },
2590 { 0x01, 0x82b1 },
2591 { 0x03, 0x7002 },
2592 { 0x08, 0x9e30 },
2593 { 0x09, 0x01f0 },
2594 { 0x0a, 0x5500 },
2595 { 0x0c, 0x00c8 },
2596 { 0x1f, 0x0003 },
2597 { 0x12, 0xc096 },
2598 { 0x16, 0x000a },
2599 { 0x1f, 0x0000 },
2600 { 0x1f, 0x0000 },
2601 { 0x09, 0x2000 },
2602 { 0x09, 0x0000 }
2603 };
2604
2605 rtl_writephy_batch(tp, phy_reg_init);
2606
2607 rtl_patchphy(tp, 0x14, 1 << 5);
2608 rtl_patchphy(tp, 0x0d, 1 << 5);
2609 rtl_writephy(tp, 0x1f, 0x0000);
2610 }
2611
2612 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2613 {
2614 static const struct phy_reg phy_reg_init[] = {
2615 { 0x1f, 0x0001 },
2616 { 0x12, 0x2300 },
2617 { 0x03, 0x802f },
2618 { 0x02, 0x4f02 },
2619 { 0x01, 0x0409 },
2620 { 0x00, 0xf099 },
2621 { 0x04, 0x9800 },
2622 { 0x04, 0x9000 },
2623 { 0x1d, 0x3d98 },
2624 { 0x1f, 0x0002 },
2625 { 0x0c, 0x7eb8 },
2626 { 0x06, 0x0761 },
2627 { 0x1f, 0x0003 },
2628 { 0x16, 0x0f0a },
2629 { 0x1f, 0x0000 }
2630 };
2631
2632 rtl_writephy_batch(tp, phy_reg_init);
2633
2634 rtl_patchphy(tp, 0x16, 1 << 0);
2635 rtl_patchphy(tp, 0x14, 1 << 5);
2636 rtl_patchphy(tp, 0x0d, 1 << 5);
2637 rtl_writephy(tp, 0x1f, 0x0000);
2638 }
2639
2640 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2641 {
2642 static const struct phy_reg phy_reg_init[] = {
2643 { 0x1f, 0x0001 },
2644 { 0x12, 0x2300 },
2645 { 0x1d, 0x3d98 },
2646 { 0x1f, 0x0002 },
2647 { 0x0c, 0x7eb8 },
2648 { 0x06, 0x5461 },
2649 { 0x1f, 0x0003 },
2650 { 0x16, 0x0f0a },
2651 { 0x1f, 0x0000 }
2652 };
2653
2654 rtl_writephy_batch(tp, phy_reg_init);
2655
2656 rtl_patchphy(tp, 0x16, 1 << 0);
2657 rtl_patchphy(tp, 0x14, 1 << 5);
2658 rtl_patchphy(tp, 0x0d, 1 << 5);
2659 rtl_writephy(tp, 0x1f, 0x0000);
2660 }
2661
2662 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2663 {
2664 rtl8168c_3_hw_phy_config(tp);
2665 }
2666
2667 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2668
2669 { 0x1f, 0x0001 },
2670 { 0x06, 0x4064 },
2671 { 0x07, 0x2863 },
2672 { 0x08, 0x059c },
2673 { 0x09, 0x26b4 },
2674 { 0x0a, 0x6a19 },
2675 { 0x0b, 0xdcc8 },
2676 { 0x10, 0xf06d },
2677 { 0x14, 0x7f68 },
2678 { 0x18, 0x7fd9 },
2679 { 0x1c, 0xf0ff },
2680 { 0x1d, 0x3d9c },
2681 { 0x1f, 0x0003 },
2682 { 0x12, 0xf49f },
2683 { 0x13, 0x070b },
2684 { 0x1a, 0x05ad },
2685 { 0x14, 0x94c0 },
2686
2687
2688
2689
2690
2691 { 0x1f, 0x0002 },
2692 { 0x06, 0x5561 },
2693 { 0x1f, 0x0005 },
2694 { 0x05, 0x8332 },
2695 { 0x06, 0x5561 },
2696
2697
2698
2699
2700
2701 { 0x1f, 0x0001 },
2702 { 0x17, 0x0cc0 },
2703
2704 { 0x1f, 0x0000 },
2705 { 0x0d, 0xf880 }
2706 };
2707
2708 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2709 { 0x1f, 0x0002 },
2710 { 0x05, 0x669a },
2711 { 0x1f, 0x0005 },
2712 { 0x05, 0x8330 },
2713 { 0x06, 0x669a },
2714 { 0x1f, 0x0002 }
2715 };
2716
2717 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2718 {
2719 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2720
2721
2722
2723
2724
2725 rtl_writephy(tp, 0x1f, 0x0002);
2726 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2727 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2728
2729 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2730 int val;
2731
2732 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2733
2734 val = rtl_readphy(tp, 0x0d);
2735
2736 if ((val & 0x00ff) != 0x006c) {
2737 static const u32 set[] = {
2738 0x0065, 0x0066, 0x0067, 0x0068,
2739 0x0069, 0x006a, 0x006b, 0x006c
2740 };
2741 int i;
2742
2743 rtl_writephy(tp, 0x1f, 0x0002);
2744
2745 val &= 0xff00;
2746 for (i = 0; i < ARRAY_SIZE(set); i++)
2747 rtl_writephy(tp, 0x0d, val | set[i]);
2748 }
2749 } else {
2750 static const struct phy_reg phy_reg_init[] = {
2751 { 0x1f, 0x0002 },
2752 { 0x05, 0x6662 },
2753 { 0x1f, 0x0005 },
2754 { 0x05, 0x8330 },
2755 { 0x06, 0x6662 }
2756 };
2757
2758 rtl_writephy_batch(tp, phy_reg_init);
2759 }
2760
2761
2762 rtl_writephy(tp, 0x1f, 0x0002);
2763 rtl_patchphy(tp, 0x0d, 0x0300);
2764 rtl_patchphy(tp, 0x0f, 0x0010);
2765
2766
2767 rtl_writephy(tp, 0x1f, 0x0002);
2768 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2769 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2770
2771 rtl_writephy(tp, 0x1f, 0x0005);
2772 rtl_writephy(tp, 0x05, 0x001b);
2773
2774 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2775
2776 rtl_writephy(tp, 0x1f, 0x0000);
2777 }
2778
2779 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2780 {
2781 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2782
2783 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2784 int val;
2785
2786 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2787
2788 val = rtl_readphy(tp, 0x0d);
2789 if ((val & 0x00ff) != 0x006c) {
2790 static const u32 set[] = {
2791 0x0065, 0x0066, 0x0067, 0x0068,
2792 0x0069, 0x006a, 0x006b, 0x006c
2793 };
2794 int i;
2795
2796 rtl_writephy(tp, 0x1f, 0x0002);
2797
2798 val &= 0xff00;
2799 for (i = 0; i < ARRAY_SIZE(set); i++)
2800 rtl_writephy(tp, 0x0d, val | set[i]);
2801 }
2802 } else {
2803 static const struct phy_reg phy_reg_init[] = {
2804 { 0x1f, 0x0002 },
2805 { 0x05, 0x2642 },
2806 { 0x1f, 0x0005 },
2807 { 0x05, 0x8330 },
2808 { 0x06, 0x2642 }
2809 };
2810
2811 rtl_writephy_batch(tp, phy_reg_init);
2812 }
2813
2814
2815 rtl_writephy(tp, 0x1f, 0x0002);
2816 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2817 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2818
2819
2820 rtl_writephy(tp, 0x1f, 0x0002);
2821 rtl_patchphy(tp, 0x0f, 0x0017);
2822
2823 rtl_writephy(tp, 0x1f, 0x0005);
2824 rtl_writephy(tp, 0x05, 0x001b);
2825
2826 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2827
2828 rtl_writephy(tp, 0x1f, 0x0000);
2829 }
2830
2831 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2832 {
2833 static const struct phy_reg phy_reg_init[] = {
2834 { 0x1f, 0x0002 },
2835 { 0x10, 0x0008 },
2836 { 0x0d, 0x006c },
2837
2838 { 0x1f, 0x0000 },
2839 { 0x0d, 0xf880 },
2840
2841 { 0x1f, 0x0001 },
2842 { 0x17, 0x0cc0 },
2843
2844 { 0x1f, 0x0001 },
2845 { 0x0b, 0xa4d8 },
2846 { 0x09, 0x281c },
2847 { 0x07, 0x2883 },
2848 { 0x0a, 0x6b35 },
2849 { 0x1d, 0x3da4 },
2850 { 0x1c, 0xeffd },
2851 { 0x14, 0x7f52 },
2852 { 0x18, 0x7fc6 },
2853 { 0x08, 0x0601 },
2854 { 0x06, 0x4063 },
2855 { 0x10, 0xf074 },
2856 { 0x1f, 0x0003 },
2857 { 0x13, 0x0789 },
2858 { 0x12, 0xf4bd },
2859 { 0x1a, 0x04fd },
2860 { 0x14, 0x84b0 },
2861 { 0x1f, 0x0000 },
2862 { 0x00, 0x9200 },
2863
2864 { 0x1f, 0x0005 },
2865 { 0x01, 0x0340 },
2866 { 0x1f, 0x0001 },
2867 { 0x04, 0x4000 },
2868 { 0x03, 0x1d21 },
2869 { 0x02, 0x0c32 },
2870 { 0x01, 0x0200 },
2871 { 0x00, 0x5554 },
2872 { 0x04, 0x4800 },
2873 { 0x04, 0x4000 },
2874 { 0x04, 0xf000 },
2875 { 0x03, 0xdf01 },
2876 { 0x02, 0xdf20 },
2877 { 0x01, 0x101a },
2878 { 0x00, 0xa0ff },
2879 { 0x04, 0xf800 },
2880 { 0x04, 0xf000 },
2881 { 0x1f, 0x0000 },
2882
2883 { 0x1f, 0x0007 },
2884 { 0x1e, 0x0023 },
2885 { 0x16, 0x0000 },
2886 { 0x1f, 0x0000 }
2887 };
2888
2889 rtl_writephy_batch(tp, phy_reg_init);
2890 }
2891
2892 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2893 {
2894 static const struct phy_reg phy_reg_init[] = {
2895 { 0x1f, 0x0001 },
2896 { 0x17, 0x0cc0 },
2897
2898 { 0x1f, 0x0007 },
2899 { 0x1e, 0x002d },
2900 { 0x18, 0x0040 },
2901 { 0x1f, 0x0000 }
2902 };
2903
2904 rtl_writephy_batch(tp, phy_reg_init);
2905 rtl_patchphy(tp, 0x0d, 1 << 5);
2906 }
2907
2908 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2909 {
2910 static const struct phy_reg phy_reg_init[] = {
2911
2912 { 0x1f, 0x0005 },
2913 { 0x05, 0x8b80 },
2914 { 0x06, 0xc896 },
2915 { 0x1f, 0x0000 },
2916
2917
2918 { 0x1f, 0x0001 },
2919 { 0x0b, 0x6c20 },
2920 { 0x07, 0x2872 },
2921 { 0x1c, 0xefff },
2922 { 0x1f, 0x0003 },
2923 { 0x14, 0x6420 },
2924 { 0x1f, 0x0000 },
2925
2926
2927 { 0x1f, 0x0007 },
2928 { 0x1e, 0x002f },
2929 { 0x15, 0x1919 },
2930 { 0x1f, 0x0000 },
2931
2932 { 0x1f, 0x0007 },
2933 { 0x1e, 0x00ac },
2934 { 0x18, 0x0006 },
2935 { 0x1f, 0x0000 }
2936 };
2937
2938 rtl_apply_firmware(tp);
2939
2940 rtl_writephy_batch(tp, phy_reg_init);
2941
2942
2943 rtl_writephy(tp, 0x1f, 0x0007);
2944 rtl_writephy(tp, 0x1e, 0x0023);
2945 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2946 rtl_writephy(tp, 0x1f, 0x0000);
2947
2948
2949 rtl_writephy(tp, 0x1f, 0x0002);
2950 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2951 rtl_writephy(tp, 0x1f, 0x0000);
2952
2953
2954 rtl_writephy(tp, 0x1f, 0x0007);
2955 rtl_writephy(tp, 0x1e, 0x002d);
2956 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2957 rtl_writephy(tp, 0x1f, 0x0000);
2958 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2959
2960 rtl_writephy(tp, 0x1f, 0x0005);
2961 rtl_writephy(tp, 0x05, 0x8b86);
2962 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2963 rtl_writephy(tp, 0x1f, 0x0000);
2964
2965 rtl_writephy(tp, 0x1f, 0x0005);
2966 rtl_writephy(tp, 0x05, 0x8b85);
2967 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2968 rtl_writephy(tp, 0x1f, 0x0007);
2969 rtl_writephy(tp, 0x1e, 0x0020);
2970 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2971 rtl_writephy(tp, 0x1f, 0x0006);
2972 rtl_writephy(tp, 0x00, 0x5a00);
2973 rtl_writephy(tp, 0x1f, 0x0000);
2974 rtl_writephy(tp, 0x0d, 0x0007);
2975 rtl_writephy(tp, 0x0e, 0x003c);
2976 rtl_writephy(tp, 0x0d, 0x4007);
2977 rtl_writephy(tp, 0x0e, 0x0000);
2978 rtl_writephy(tp, 0x0d, 0x0000);
2979 }
2980
2981 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2982 {
2983 const u16 w[] = {
2984 addr[0] | (addr[1] << 8),
2985 addr[2] | (addr[3] << 8),
2986 addr[4] | (addr[5] << 8)
2987 };
2988
2989 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2990 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2991 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2992 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2993 }
2994
2995 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2996 {
2997 static const struct phy_reg phy_reg_init[] = {
2998
2999 { 0x1f, 0x0004 },
3000 { 0x1f, 0x0007 },
3001 { 0x1e, 0x00ac },
3002 { 0x18, 0x0006 },
3003 { 0x1f, 0x0002 },
3004 { 0x1f, 0x0000 },
3005 { 0x1f, 0x0000 },
3006
3007
3008 { 0x1f, 0x0003 },
3009 { 0x09, 0xa20f },
3010 { 0x1f, 0x0000 },
3011 { 0x1f, 0x0000 },
3012
3013
3014 { 0x1f, 0x0005 },
3015 { 0x05, 0x8b5b },
3016 { 0x06, 0x9222 },
3017 { 0x05, 0x8b6d },
3018 { 0x06, 0x8000 },
3019 { 0x05, 0x8b76 },
3020 { 0x06, 0x8000 },
3021 { 0x1f, 0x0000 }
3022 };
3023
3024 rtl_apply_firmware(tp);
3025
3026 rtl_writephy_batch(tp, phy_reg_init);
3027
3028
3029 rtl_writephy(tp, 0x1f, 0x0005);
3030 rtl_writephy(tp, 0x05, 0x8b80);
3031 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3032 rtl_writephy(tp, 0x1f, 0x0000);
3033
3034
3035 rtl_writephy(tp, 0x1f, 0x0004);
3036 rtl_writephy(tp, 0x1f, 0x0007);
3037 rtl_writephy(tp, 0x1e, 0x002d);
3038 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3039 rtl_writephy(tp, 0x1f, 0x0002);
3040 rtl_writephy(tp, 0x1f, 0x0000);
3041 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3042
3043
3044 rtl_writephy(tp, 0x1f, 0x0005);
3045 rtl_writephy(tp, 0x05, 0x8b86);
3046 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3047 rtl_writephy(tp, 0x1f, 0x0000);
3048
3049
3050 rtl_writephy(tp, 0x1f, 0x0005);
3051 rtl_writephy(tp, 0x05, 0x8b85);
3052 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3053 rtl_writephy(tp, 0x1f, 0x0000);
3054
3055 rtl8168f_config_eee_phy(tp);
3056 rtl_enable_eee(tp);
3057
3058
3059 rtl_writephy(tp, 0x1f, 0x0003);
3060 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3061 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3062 rtl_writephy(tp, 0x1f, 0x0000);
3063 rtl_writephy(tp, 0x1f, 0x0005);
3064 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3065 rtl_writephy(tp, 0x1f, 0x0000);
3066
3067
3068 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3069 }
3070
3071 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3072 {
3073
3074 rtl_writephy(tp, 0x1f, 0x0005);
3075 rtl_writephy(tp, 0x05, 0x8b80);
3076 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3077 rtl_writephy(tp, 0x1f, 0x0000);
3078
3079
3080 rtl_writephy(tp, 0x1f, 0x0007);
3081 rtl_writephy(tp, 0x1e, 0x002d);
3082 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3083 rtl_writephy(tp, 0x1f, 0x0000);
3084 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3085
3086
3087 rtl_writephy(tp, 0x1f, 0x0005);
3088 rtl_writephy(tp, 0x05, 0x8b86);
3089 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3090 rtl_writephy(tp, 0x1f, 0x0000);
3091
3092 rtl8168f_config_eee_phy(tp);
3093 rtl_enable_eee(tp);
3094 }
3095
3096 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3097 {
3098 static const struct phy_reg phy_reg_init[] = {
3099
3100 { 0x1f, 0x0003 },
3101 { 0x09, 0xa20f },
3102 { 0x1f, 0x0000 },
3103
3104
3105 { 0x1f, 0x0005 },
3106 { 0x05, 0x8b55 },
3107 { 0x06, 0x0000 },
3108 { 0x05, 0x8b5e },
3109 { 0x06, 0x0000 },
3110 { 0x05, 0x8b67 },
3111 { 0x06, 0x0000 },
3112 { 0x05, 0x8b70 },
3113 { 0x06, 0x0000 },
3114 { 0x1f, 0x0000 },
3115 { 0x1f, 0x0007 },
3116 { 0x1e, 0x0078 },
3117 { 0x17, 0x0000 },
3118 { 0x19, 0x00fb },
3119 { 0x1f, 0x0000 },
3120
3121
3122 { 0x1f, 0x0005 },
3123 { 0x05, 0x8b79 },
3124 { 0x06, 0xaa00 },
3125 { 0x1f, 0x0000 },
3126
3127
3128 { 0x1f, 0x0003 },
3129 { 0x01, 0x328a },
3130 { 0x1f, 0x0000 }
3131 };
3132
3133 rtl_apply_firmware(tp);
3134
3135 rtl_writephy_batch(tp, phy_reg_init);
3136
3137 rtl8168f_hw_phy_config(tp);
3138
3139
3140 rtl_writephy(tp, 0x1f, 0x0005);
3141 rtl_writephy(tp, 0x05, 0x8b85);
3142 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3143 rtl_writephy(tp, 0x1f, 0x0000);
3144 }
3145
3146 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3147 {
3148 rtl_apply_firmware(tp);
3149
3150 rtl8168f_hw_phy_config(tp);
3151 }
3152
3153 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3154 {
3155 static const struct phy_reg phy_reg_init[] = {
3156
3157 { 0x1f, 0x0003 },
3158 { 0x09, 0xa20f },
3159 { 0x1f, 0x0000 },
3160
3161
3162 { 0x1f, 0x0005 },
3163 { 0x05, 0x8b55 },
3164 { 0x06, 0x0000 },
3165 { 0x05, 0x8b5e },
3166 { 0x06, 0x0000 },
3167 { 0x05, 0x8b67 },
3168 { 0x06, 0x0000 },
3169 { 0x05, 0x8b70 },
3170 { 0x06, 0x0000 },
3171 { 0x1f, 0x0000 },
3172 { 0x1f, 0x0007 },
3173 { 0x1e, 0x0078 },
3174 { 0x17, 0x0000 },
3175 { 0x19, 0x00aa },
3176 { 0x1f, 0x0000 },
3177
3178
3179 { 0x1f, 0x0005 },
3180 { 0x05, 0x8b79 },
3181 { 0x06, 0xaa00 },
3182 { 0x1f, 0x0000 },
3183
3184
3185 { 0x1f, 0x0003 },
3186 { 0x01, 0x328a },
3187 { 0x1f, 0x0000 }
3188 };
3189
3190
3191 rtl_apply_firmware(tp);
3192
3193 rtl8168f_hw_phy_config(tp);
3194
3195
3196 rtl_writephy(tp, 0x1f, 0x0005);
3197 rtl_writephy(tp, 0x05, 0x8b85);
3198 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3199 rtl_writephy(tp, 0x1f, 0x0000);
3200
3201 rtl_writephy_batch(tp, phy_reg_init);
3202
3203
3204 rtl_writephy(tp, 0x1f, 0x0005);
3205 rtl_writephy(tp, 0x05, 0x8b54);
3206 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3207 rtl_writephy(tp, 0x05, 0x8b5d);
3208 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3209 rtl_writephy(tp, 0x05, 0x8a7c);
3210 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3211 rtl_writephy(tp, 0x05, 0x8a7f);
3212 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3213 rtl_writephy(tp, 0x05, 0x8a82);
3214 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3215 rtl_writephy(tp, 0x05, 0x8a85);
3216 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3217 rtl_writephy(tp, 0x05, 0x8a88);
3218 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3219 rtl_writephy(tp, 0x1f, 0x0000);
3220
3221
3222 rtl_writephy(tp, 0x1f, 0x0005);
3223 rtl_writephy(tp, 0x05, 0x8b85);
3224 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3225 rtl_writephy(tp, 0x1f, 0x0000);
3226
3227
3228 rtl_writephy(tp, 0x1f, 0x0003);
3229 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3230 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3231 rtl_writephy(tp, 0x1f, 0x0000);
3232 }
3233
3234 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3235 {
3236 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3237 }
3238
3239 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3240 {
3241 struct phy_device *phydev = tp->phydev;
3242
3243 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3244 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3245 phy_write(phydev, 0x1f, 0x0a43);
3246 phy_write(phydev, 0x13, 0x8084);
3247 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3248 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3249
3250 phy_write(phydev, 0x1f, 0x0000);
3251 }
3252
3253 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3254 {
3255 int ret;
3256
3257 rtl_apply_firmware(tp);
3258
3259 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3260 if (ret & BIT(8))
3261 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3262 else
3263 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3264
3265 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3266 if (ret & BIT(8))
3267 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
3268 else
3269 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
3270
3271
3272 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3273
3274 rtl8168g_phy_adjust_10m_aldps(tp);
3275
3276
3277 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3278
3279
3280 rtl_writephy(tp, 0x1f, 0x0a43);
3281 rtl_writephy(tp, 0x13, 0x8012);
3282 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3283
3284 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3285
3286
3287 rtl_writephy(tp, 0x1f, 0x0bcd);
3288 rtl_writephy(tp, 0x14, 0x5065);
3289 rtl_writephy(tp, 0x14, 0xd065);
3290 rtl_writephy(tp, 0x1f, 0x0bc8);
3291 rtl_writephy(tp, 0x11, 0x5655);
3292 rtl_writephy(tp, 0x1f, 0x0bcd);
3293 rtl_writephy(tp, 0x14, 0x1065);
3294 rtl_writephy(tp, 0x14, 0x9065);
3295 rtl_writephy(tp, 0x14, 0x1065);
3296 rtl_writephy(tp, 0x1f, 0x0000);
3297
3298 rtl8168g_disable_aldps(tp);
3299 rtl8168g_config_eee_phy(tp);
3300 rtl_enable_eee(tp);
3301 }
3302
3303 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3304 {
3305 rtl_apply_firmware(tp);
3306 rtl8168g_config_eee_phy(tp);
3307 rtl_enable_eee(tp);
3308 }
3309
3310 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3311 {
3312 u16 dout_tapbin;
3313 u32 data;
3314
3315 rtl_apply_firmware(tp);
3316
3317
3318 rtl_writephy(tp, 0x1f, 0x0a43);
3319 rtl_writephy(tp, 0x13, 0x809b);
3320 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3321 rtl_writephy(tp, 0x13, 0x80a2);
3322 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3323 rtl_writephy(tp, 0x13, 0x80a4);
3324 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3325 rtl_writephy(tp, 0x13, 0x809c);
3326 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3327 rtl_writephy(tp, 0x1f, 0x0000);
3328
3329
3330 rtl_writephy(tp, 0x1f, 0x0a43);
3331 rtl_writephy(tp, 0x13, 0x80ad);
3332 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3333 rtl_writephy(tp, 0x13, 0x80b4);
3334 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3335 rtl_writephy(tp, 0x13, 0x80ac);
3336 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3337 rtl_writephy(tp, 0x1f, 0x0000);
3338
3339
3340 rtl_writephy(tp, 0x1f, 0x0a43);
3341 rtl_writephy(tp, 0x13, 0x808e);
3342 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3343 rtl_writephy(tp, 0x13, 0x8090);
3344 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3345 rtl_writephy(tp, 0x13, 0x8092);
3346 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3347 rtl_writephy(tp, 0x1f, 0x0000);
3348
3349
3350 dout_tapbin = 0;
3351 rtl_writephy(tp, 0x1f, 0x0a46);
3352 data = rtl_readphy(tp, 0x13);
3353 data &= 3;
3354 data <<= 2;
3355 dout_tapbin |= data;
3356 data = rtl_readphy(tp, 0x12);
3357 data &= 0xc000;
3358 data >>= 14;
3359 dout_tapbin |= data;
3360 dout_tapbin = ~(dout_tapbin^0x08);
3361 dout_tapbin <<= 12;
3362 dout_tapbin &= 0xf000;
3363 rtl_writephy(tp, 0x1f, 0x0a43);
3364 rtl_writephy(tp, 0x13, 0x827a);
3365 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3366 rtl_writephy(tp, 0x13, 0x827b);
3367 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3368 rtl_writephy(tp, 0x13, 0x827c);
3369 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3370 rtl_writephy(tp, 0x13, 0x827d);
3371 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3372
3373 rtl_writephy(tp, 0x1f, 0x0a43);
3374 rtl_writephy(tp, 0x13, 0x0811);
3375 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3376 rtl_writephy(tp, 0x1f, 0x0a42);
3377 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3378 rtl_writephy(tp, 0x1f, 0x0000);
3379
3380
3381 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3382
3383
3384 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3385
3386 rtl_writephy(tp, 0x1f, 0x0a43);
3387 rtl_writephy(tp, 0x13, 0x803f);
3388 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3389 rtl_writephy(tp, 0x13, 0x8047);
3390 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3391 rtl_writephy(tp, 0x13, 0x804f);
3392 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3393 rtl_writephy(tp, 0x13, 0x8057);
3394 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3395 rtl_writephy(tp, 0x13, 0x805f);
3396 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3397 rtl_writephy(tp, 0x13, 0x8067);
3398 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3399 rtl_writephy(tp, 0x13, 0x806f);
3400 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3401 rtl_writephy(tp, 0x1f, 0x0000);
3402
3403
3404 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3405
3406 rtl8168g_disable_aldps(tp);
3407 rtl8168h_config_eee_phy(tp);
3408 rtl_enable_eee(tp);
3409 }
3410
3411 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3412 {
3413 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3414 u16 rlen;
3415 u32 data;
3416
3417 rtl_apply_firmware(tp);
3418
3419
3420 rtl_writephy(tp, 0x1f, 0x0a43);
3421 rtl_writephy(tp, 0x13, 0x808a);
3422 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3423 rtl_writephy(tp, 0x1f, 0x0000);
3424
3425
3426 rtl_writephy(tp, 0x1f, 0x0a43);
3427 rtl_writephy(tp, 0x13, 0x0811);
3428 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3429 rtl_writephy(tp, 0x1f, 0x0a42);
3430 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3431 rtl_writephy(tp, 0x1f, 0x0000);
3432
3433
3434 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3435
3436 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3437 data = r8168_mac_ocp_read(tp, 0xdd02);
3438 ioffset_p3 = ((data & 0x80)>>7);
3439 ioffset_p3 <<= 3;
3440
3441 data = r8168_mac_ocp_read(tp, 0xdd00);
3442 ioffset_p3 |= ((data & (0xe000))>>13);
3443 ioffset_p2 = ((data & (0x1e00))>>9);
3444 ioffset_p1 = ((data & (0x01e0))>>5);
3445 ioffset_p0 = ((data & 0x0010)>>4);
3446 ioffset_p0 <<= 3;
3447 ioffset_p0 |= (data & (0x07));
3448 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3449
3450 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3451 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3452 rtl_writephy(tp, 0x1f, 0x0bcf);
3453 rtl_writephy(tp, 0x16, data);
3454 rtl_writephy(tp, 0x1f, 0x0000);
3455 }
3456
3457
3458 rtl_writephy(tp, 0x1f, 0x0bcd);
3459 data = rtl_readphy(tp, 0x16);
3460 data &= 0x000f;
3461 rlen = 0;
3462 if (data > 3)
3463 rlen = data - 3;
3464 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3465 rtl_writephy(tp, 0x17, data);
3466 rtl_writephy(tp, 0x1f, 0x0bcd);
3467 rtl_writephy(tp, 0x1f, 0x0000);
3468
3469
3470 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3471
3472 rtl8168g_disable_aldps(tp);
3473 rtl8168g_config_eee_phy(tp);
3474 rtl_enable_eee(tp);
3475 }
3476
3477 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3478 {
3479
3480 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3481
3482 rtl8168g_phy_adjust_10m_aldps(tp);
3483
3484
3485 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3486
3487
3488 rtl_writephy(tp, 0x1f, 0x0a43);
3489 rtl_writephy(tp, 0x13, 0x8012);
3490 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3491 rtl_writephy(tp, 0x1f, 0x0000);
3492
3493
3494 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3495
3496 rtl8168g_disable_aldps(tp);
3497 rtl8168g_config_eee_phy(tp);
3498 rtl_enable_eee(tp);
3499 }
3500
3501 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3502 {
3503 rtl8168g_phy_adjust_10m_aldps(tp);
3504
3505
3506 rtl_writephy(tp, 0x1f, 0x0a43);
3507 rtl_writephy(tp, 0x13, 0x8012);
3508 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3509 rtl_writephy(tp, 0x1f, 0x0000);
3510
3511
3512 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3513
3514
3515 rtl_writephy(tp, 0x1f, 0x0a43);
3516 rtl_writephy(tp, 0x13, 0x80f3);
3517 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3518 rtl_writephy(tp, 0x13, 0x80f0);
3519 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3520 rtl_writephy(tp, 0x13, 0x80ef);
3521 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3522 rtl_writephy(tp, 0x13, 0x80f6);
3523 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3524 rtl_writephy(tp, 0x13, 0x80ec);
3525 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3526 rtl_writephy(tp, 0x13, 0x80ed);
3527 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3528 rtl_writephy(tp, 0x13, 0x80f2);
3529 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3530 rtl_writephy(tp, 0x13, 0x80f4);
3531 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3532 rtl_writephy(tp, 0x1f, 0x0a43);
3533 rtl_writephy(tp, 0x13, 0x8110);
3534 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3535 rtl_writephy(tp, 0x13, 0x810f);
3536 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3537 rtl_writephy(tp, 0x13, 0x8111);
3538 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3539 rtl_writephy(tp, 0x13, 0x8113);
3540 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3541 rtl_writephy(tp, 0x13, 0x8115);
3542 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3543 rtl_writephy(tp, 0x13, 0x810e);
3544 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3545 rtl_writephy(tp, 0x13, 0x810c);
3546 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3547 rtl_writephy(tp, 0x13, 0x810b);
3548 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3549 rtl_writephy(tp, 0x1f, 0x0a43);
3550 rtl_writephy(tp, 0x13, 0x80d1);
3551 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3552 rtl_writephy(tp, 0x13, 0x80cd);
3553 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3554 rtl_writephy(tp, 0x13, 0x80d3);
3555 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3556 rtl_writephy(tp, 0x13, 0x80d5);
3557 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3558 rtl_writephy(tp, 0x13, 0x80d7);
3559 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3560
3561
3562 rtl_writephy(tp, 0x1f, 0x0bcd);
3563 rtl_writephy(tp, 0x14, 0x5065);
3564 rtl_writephy(tp, 0x14, 0xd065);
3565 rtl_writephy(tp, 0x1f, 0x0bc8);
3566 rtl_writephy(tp, 0x12, 0x00ed);
3567 rtl_writephy(tp, 0x1f, 0x0bcd);
3568 rtl_writephy(tp, 0x14, 0x1065);
3569 rtl_writephy(tp, 0x14, 0x9065);
3570 rtl_writephy(tp, 0x14, 0x1065);
3571 rtl_writephy(tp, 0x1f, 0x0000);
3572
3573 rtl8168g_disable_aldps(tp);
3574 rtl8168g_config_eee_phy(tp);
3575 rtl_enable_eee(tp);
3576 }
3577
3578 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3579 {
3580 static const struct phy_reg phy_reg_init[] = {
3581 { 0x1f, 0x0003 },
3582 { 0x08, 0x441d },
3583 { 0x01, 0x9100 },
3584 { 0x1f, 0x0000 }
3585 };
3586
3587 rtl_writephy(tp, 0x1f, 0x0000);
3588 rtl_patchphy(tp, 0x11, 1 << 12);
3589 rtl_patchphy(tp, 0x19, 1 << 13);
3590 rtl_patchphy(tp, 0x10, 1 << 15);
3591
3592 rtl_writephy_batch(tp, phy_reg_init);
3593 }
3594
3595 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3596 {
3597 static const struct phy_reg phy_reg_init[] = {
3598 { 0x1f, 0x0005 },
3599 { 0x1a, 0x0000 },
3600 { 0x1f, 0x0000 },
3601
3602 { 0x1f, 0x0004 },
3603 { 0x1c, 0x0000 },
3604 { 0x1f, 0x0000 },
3605
3606 { 0x1f, 0x0001 },
3607 { 0x15, 0x7701 },
3608 { 0x1f, 0x0000 }
3609 };
3610
3611
3612 rtl_writephy(tp, 0x1f, 0x0000);
3613 rtl_writephy(tp, 0x18, 0x0310);
3614 msleep(100);
3615
3616 rtl_apply_firmware(tp);
3617
3618 rtl_writephy_batch(tp, phy_reg_init);
3619 }
3620
3621 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3622 {
3623
3624 rtl_writephy(tp, 0x1f, 0x0000);
3625 rtl_writephy(tp, 0x18, 0x0310);
3626 msleep(20);
3627
3628 rtl_apply_firmware(tp);
3629
3630
3631 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3632 rtl_writephy(tp, 0x1f, 0x0004);
3633 rtl_writephy(tp, 0x10, 0x401f);
3634 rtl_writephy(tp, 0x19, 0x7030);
3635 rtl_writephy(tp, 0x1f, 0x0000);
3636 }
3637
3638 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3639 {
3640 static const struct phy_reg phy_reg_init[] = {
3641 { 0x1f, 0x0004 },
3642 { 0x10, 0xc07f },
3643 { 0x19, 0x7030 },
3644 { 0x1f, 0x0000 }
3645 };
3646
3647
3648 rtl_writephy(tp, 0x1f, 0x0000);
3649 rtl_writephy(tp, 0x18, 0x0310);
3650 msleep(100);
3651
3652 rtl_apply_firmware(tp);
3653
3654 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3655 rtl_writephy_batch(tp, phy_reg_init);
3656
3657 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3658 }
3659
3660 static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp)
3661 {
3662 struct phy_device *phydev = tp->phydev;
3663
3664 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084);
3665 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3666 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006);
3667 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3668 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100);
3669 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000);
3670 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400);
3671 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff);
3672 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff);
3673
3674 phy_write(phydev, 0x1f, 0x0a43);
3675 phy_write(phydev, 0x13, 0x80ea);
3676 phy_modify(phydev, 0x14, 0xff00, 0xc400);
3677 phy_write(phydev, 0x13, 0x80eb);
3678 phy_modify(phydev, 0x14, 0x0700, 0x0300);
3679 phy_write(phydev, 0x13, 0x80f8);
3680 phy_modify(phydev, 0x14, 0xff00, 0x1c00);
3681 phy_write(phydev, 0x13, 0x80f1);
3682 phy_modify(phydev, 0x14, 0xff00, 0x3000);
3683 phy_write(phydev, 0x13, 0x80fe);
3684 phy_modify(phydev, 0x14, 0xff00, 0xa500);
3685 phy_write(phydev, 0x13, 0x8102);
3686 phy_modify(phydev, 0x14, 0xff00, 0x5000);
3687 phy_write(phydev, 0x13, 0x8105);
3688 phy_modify(phydev, 0x14, 0xff00, 0x3300);
3689 phy_write(phydev, 0x13, 0x8100);
3690 phy_modify(phydev, 0x14, 0xff00, 0x7000);
3691 phy_write(phydev, 0x13, 0x8104);
3692 phy_modify(phydev, 0x14, 0xff00, 0xf000);
3693 phy_write(phydev, 0x13, 0x8106);
3694 phy_modify(phydev, 0x14, 0xff00, 0x6500);
3695 phy_write(phydev, 0x13, 0x80dc);
3696 phy_modify(phydev, 0x14, 0xff00, 0xed00);
3697 phy_write(phydev, 0x13, 0x80df);
3698 phy_set_bits(phydev, 0x14, BIT(8));
3699 phy_write(phydev, 0x13, 0x80e1);
3700 phy_clear_bits(phydev, 0x14, BIT(8));
3701 phy_write(phydev, 0x1f, 0x0000);
3702
3703 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038);
3704 phy_write_paged(phydev, 0xa43, 0x13, 0x819f);
3705 phy_write_paged(phydev, 0xa43, 0x14, 0xd0b6);
3706
3707 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555);
3708 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00);
3709 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000);
3710 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
3711
3712 rtl8125_config_eee_phy(tp);
3713 rtl_enable_eee(tp);
3714 }
3715
3716 static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp)
3717 {
3718 struct phy_device *phydev = tp->phydev;
3719 int i;
3720
3721 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3722 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff);
3723 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3724 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000);
3725 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002);
3726 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044);
3727 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000);
3728 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000);
3729 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002);
3730 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8);
3731 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff);
3732 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030);
3733
3734 phy_write(phydev, 0x1f, 0x0b87);
3735 phy_write(phydev, 0x16, 0x80a2);
3736 phy_write(phydev, 0x17, 0x0153);
3737 phy_write(phydev, 0x16, 0x809c);
3738 phy_write(phydev, 0x17, 0x0153);
3739 phy_write(phydev, 0x1f, 0x0000);
3740
3741 phy_write(phydev, 0x1f, 0x0a43);
3742 phy_write(phydev, 0x13, 0x81B3);
3743 phy_write(phydev, 0x14, 0x0043);
3744 phy_write(phydev, 0x14, 0x00A7);
3745 phy_write(phydev, 0x14, 0x00D6);
3746 phy_write(phydev, 0x14, 0x00EC);
3747 phy_write(phydev, 0x14, 0x00F6);
3748 phy_write(phydev, 0x14, 0x00FB);
3749 phy_write(phydev, 0x14, 0x00FD);
3750 phy_write(phydev, 0x14, 0x00FF);
3751 phy_write(phydev, 0x14, 0x00BB);
3752 phy_write(phydev, 0x14, 0x0058);
3753 phy_write(phydev, 0x14, 0x0029);
3754 phy_write(phydev, 0x14, 0x0013);
3755 phy_write(phydev, 0x14, 0x0009);
3756 phy_write(phydev, 0x14, 0x0004);
3757 phy_write(phydev, 0x14, 0x0002);
3758 for (i = 0; i < 25; i++)
3759 phy_write(phydev, 0x14, 0x0000);
3760
3761 phy_write(phydev, 0x13, 0x8257);
3762 phy_write(phydev, 0x14, 0x020F);
3763
3764 phy_write(phydev, 0x13, 0x80EA);
3765 phy_write(phydev, 0x14, 0x7843);
3766 phy_write(phydev, 0x1f, 0x0000);
3767
3768 rtl_apply_firmware(tp);
3769
3770 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000);
3771
3772 phy_write(phydev, 0x1f, 0x0a43);
3773 phy_write(phydev, 0x13, 0x81a2);
3774 phy_set_bits(phydev, 0x14, BIT(8));
3775 phy_write(phydev, 0x1f, 0x0000);
3776
3777 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00);
3778 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000);
3779 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020);
3780 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000);
3781 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000);
3782 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
3783
3784 rtl8125_config_eee_phy(tp);
3785 rtl_enable_eee(tp);
3786 }
3787
3788 static void rtl_hw_phy_config(struct net_device *dev)
3789 {
3790 static const rtl_generic_fct phy_configs[] = {
3791
3792 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3793 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3794 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3795 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3796 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3797
3798 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3799 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3800 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3801 [RTL_GIGA_MAC_VER_10] = NULL,
3802 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3803 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3804 [RTL_GIGA_MAC_VER_13] = NULL,
3805 [RTL_GIGA_MAC_VER_14] = NULL,
3806 [RTL_GIGA_MAC_VER_15] = NULL,
3807 [RTL_GIGA_MAC_VER_16] = NULL,
3808 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3809 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3810 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3811 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3812 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3813 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3814 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3815 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3816 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3817 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3818 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3819 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3820 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3821 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3822 [RTL_GIGA_MAC_VER_31] = NULL,
3823 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3824 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3825 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3826 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3827 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3828 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3829 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3830 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3831 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3832 [RTL_GIGA_MAC_VER_41] = NULL,
3833 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3834 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3835 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3836 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3837 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3838 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3839 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3840 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3841 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3842 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3843 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config,
3844 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config,
3845 };
3846 struct rtl8169_private *tp = netdev_priv(dev);
3847
3848 if (phy_configs[tp->mac_version])
3849 phy_configs[tp->mac_version](tp);
3850 }
3851
3852 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3853 {
3854 if (!test_and_set_bit(flag, tp->wk.flags))
3855 schedule_work(&tp->wk.work);
3856 }
3857
3858 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3859 {
3860 rtl_hw_phy_config(dev);
3861
3862 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3863 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3864 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3865 netif_dbg(tp, drv, dev,
3866 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3867 RTL_W8(tp, 0x82, 0x01);
3868 }
3869
3870
3871 phy_speed_up(tp->phydev);
3872
3873 genphy_soft_reset(tp->phydev);
3874 }
3875
3876 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3877 {
3878 rtl_lock_work(tp);
3879
3880 rtl_unlock_config_regs(tp);
3881
3882 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3883 RTL_R32(tp, MAC4);
3884
3885 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3886 RTL_R32(tp, MAC0);
3887
3888 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3889 rtl_rar_exgmac_set(tp, addr);
3890
3891 rtl_lock_config_regs(tp);
3892
3893 rtl_unlock_work(tp);
3894 }
3895
3896 static int rtl_set_mac_address(struct net_device *dev, void *p)
3897 {
3898 struct rtl8169_private *tp = netdev_priv(dev);
3899 struct device *d = tp_to_dev(tp);
3900 int ret;
3901
3902 ret = eth_mac_addr(dev, p);
3903 if (ret)
3904 return ret;
3905
3906 pm_runtime_get_noresume(d);
3907
3908 if (pm_runtime_active(d))
3909 rtl_rar_set(tp, dev->dev_addr);
3910
3911 pm_runtime_put_noidle(d);
3912
3913 return 0;
3914 }
3915
3916 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3917 {
3918 struct rtl8169_private *tp = netdev_priv(dev);
3919
3920 if (!netif_running(dev))
3921 return -ENODEV;
3922
3923 return phy_mii_ioctl(tp->phydev, ifr, cmd);
3924 }
3925
3926 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3927 {
3928 switch (tp->mac_version) {
3929 case RTL_GIGA_MAC_VER_25:
3930 case RTL_GIGA_MAC_VER_26:
3931 case RTL_GIGA_MAC_VER_29:
3932 case RTL_GIGA_MAC_VER_30:
3933 case RTL_GIGA_MAC_VER_32:
3934 case RTL_GIGA_MAC_VER_33:
3935 case RTL_GIGA_MAC_VER_34:
3936 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61:
3937 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3938 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3939 break;
3940 default:
3941 break;
3942 }
3943 }
3944
3945 static void rtl_pll_power_down(struct rtl8169_private *tp)
3946 {
3947 if (r8168_check_dash(tp))
3948 return;
3949
3950 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3951 tp->mac_version == RTL_GIGA_MAC_VER_33)
3952 rtl_ephy_write(tp, 0x19, 0xff64);
3953
3954 if (device_may_wakeup(tp_to_dev(tp))) {
3955 phy_speed_down(tp->phydev, false);
3956 rtl_wol_suspend_quirk(tp);
3957 return;
3958 }
3959
3960 switch (tp->mac_version) {
3961 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3962 case RTL_GIGA_MAC_VER_37:
3963 case RTL_GIGA_MAC_VER_39:
3964 case RTL_GIGA_MAC_VER_43:
3965 case RTL_GIGA_MAC_VER_44:
3966 case RTL_GIGA_MAC_VER_45:
3967 case RTL_GIGA_MAC_VER_46:
3968 case RTL_GIGA_MAC_VER_47:
3969 case RTL_GIGA_MAC_VER_48:
3970 case RTL_GIGA_MAC_VER_50:
3971 case RTL_GIGA_MAC_VER_51:
3972 case RTL_GIGA_MAC_VER_60:
3973 case RTL_GIGA_MAC_VER_61:
3974 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3975 break;
3976 case RTL_GIGA_MAC_VER_40:
3977 case RTL_GIGA_MAC_VER_41:
3978 case RTL_GIGA_MAC_VER_49:
3979 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3980 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3981 break;
3982 default:
3983 break;
3984 }
3985 }
3986
3987 static void rtl_pll_power_up(struct rtl8169_private *tp)
3988 {
3989 switch (tp->mac_version) {
3990 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3991 case RTL_GIGA_MAC_VER_37:
3992 case RTL_GIGA_MAC_VER_39:
3993 case RTL_GIGA_MAC_VER_43:
3994 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3995 break;
3996 case RTL_GIGA_MAC_VER_44:
3997 case RTL_GIGA_MAC_VER_45:
3998 case RTL_GIGA_MAC_VER_46:
3999 case RTL_GIGA_MAC_VER_47:
4000 case RTL_GIGA_MAC_VER_48:
4001 case RTL_GIGA_MAC_VER_50:
4002 case RTL_GIGA_MAC_VER_51:
4003 case RTL_GIGA_MAC_VER_60:
4004 case RTL_GIGA_MAC_VER_61:
4005 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4006 break;
4007 case RTL_GIGA_MAC_VER_40:
4008 case RTL_GIGA_MAC_VER_41:
4009 case RTL_GIGA_MAC_VER_49:
4010 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4011 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4012 break;
4013 default:
4014 break;
4015 }
4016
4017 phy_resume(tp->phydev);
4018
4019 msleep(20);
4020 }
4021
4022 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4023 {
4024 switch (tp->mac_version) {
4025 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4026 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4027 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4028 break;
4029 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4030 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4031 case RTL_GIGA_MAC_VER_38:
4032 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4033 break;
4034 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4035 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4036 break;
4037 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
4038 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 |
4039 RX_DMA_BURST);
4040 break;
4041 default:
4042 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4043 break;
4044 }
4045 }
4046
4047 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4048 {
4049 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4050 }
4051
4052 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4053 {
4054 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4055 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4056 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4057 }
4058
4059 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4060 {
4061 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4062 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4063 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4064 }
4065
4066 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4067 {
4068 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4069 }
4070
4071 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4072 {
4073 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4074 }
4075
4076 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4077 {
4078 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4079 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4080 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4081 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4082 }
4083
4084 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4085 {
4086 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4087 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4088 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4089 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4090 }
4091
4092 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4093 {
4094 rtl_tx_performance_tweak(tp,
4095 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4096 }
4097
4098 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4099 {
4100 rtl_tx_performance_tweak(tp,
4101 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4102 }
4103
4104 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4105 {
4106 r8168b_0_hw_jumbo_enable(tp);
4107
4108 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4109 }
4110
4111 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4112 {
4113 r8168b_0_hw_jumbo_disable(tp);
4114
4115 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4116 }
4117
4118 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4119 {
4120 rtl_unlock_config_regs(tp);
4121 switch (tp->mac_version) {
4122 case RTL_GIGA_MAC_VER_11:
4123 r8168b_0_hw_jumbo_enable(tp);
4124 break;
4125 case RTL_GIGA_MAC_VER_12:
4126 case RTL_GIGA_MAC_VER_17:
4127 r8168b_1_hw_jumbo_enable(tp);
4128 break;
4129 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4130 r8168c_hw_jumbo_enable(tp);
4131 break;
4132 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4133 r8168dp_hw_jumbo_enable(tp);
4134 break;
4135 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
4136 r8168e_hw_jumbo_enable(tp);
4137 break;
4138 default:
4139 break;
4140 }
4141 rtl_lock_config_regs(tp);
4142 }
4143
4144 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4145 {
4146 rtl_unlock_config_regs(tp);
4147 switch (tp->mac_version) {
4148 case RTL_GIGA_MAC_VER_11:
4149 r8168b_0_hw_jumbo_disable(tp);
4150 break;
4151 case RTL_GIGA_MAC_VER_12:
4152 case RTL_GIGA_MAC_VER_17:
4153 r8168b_1_hw_jumbo_disable(tp);
4154 break;
4155 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4156 r8168c_hw_jumbo_disable(tp);
4157 break;
4158 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4159 r8168dp_hw_jumbo_disable(tp);
4160 break;
4161 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
4162 r8168e_hw_jumbo_disable(tp);
4163 break;
4164 default:
4165 break;
4166 }
4167 rtl_lock_config_regs(tp);
4168 }
4169
4170 static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu)
4171 {
4172 if (mtu > ETH_DATA_LEN)
4173 rtl_hw_jumbo_enable(tp);
4174 else
4175 rtl_hw_jumbo_disable(tp);
4176 }
4177
4178 DECLARE_RTL_COND(rtl_chipcmd_cond)
4179 {
4180 return RTL_R8(tp, ChipCmd) & CmdReset;
4181 }
4182
4183 static void rtl_hw_reset(struct rtl8169_private *tp)
4184 {
4185 RTL_W8(tp, ChipCmd, CmdReset);
4186
4187 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4188 }
4189
4190 static void rtl_request_firmware(struct rtl8169_private *tp)
4191 {
4192 struct rtl_fw *rtl_fw;
4193
4194
4195 if (tp->rtl_fw || !tp->fw_name)
4196 return;
4197
4198 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4199 if (!rtl_fw) {
4200 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4201 return;
4202 }
4203
4204 rtl_fw->phy_write = rtl_writephy;
4205 rtl_fw->phy_read = rtl_readphy;
4206 rtl_fw->mac_mcu_write = mac_mcu_write;
4207 rtl_fw->mac_mcu_read = mac_mcu_read;
4208 rtl_fw->fw_name = tp->fw_name;
4209 rtl_fw->dev = tp_to_dev(tp);
4210
4211 if (rtl_fw_request_firmware(rtl_fw))
4212 kfree(rtl_fw);
4213 else
4214 tp->rtl_fw = rtl_fw;
4215 }
4216
4217 static void rtl_rx_close(struct rtl8169_private *tp)
4218 {
4219 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4220 }
4221
4222 DECLARE_RTL_COND(rtl_npq_cond)
4223 {
4224 return RTL_R8(tp, TxPoll) & NPQ;
4225 }
4226
4227 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4228 {
4229 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4230 }
4231
4232 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4233 {
4234
4235 rtl8169_irq_mask_and_ack(tp);
4236
4237 rtl_rx_close(tp);
4238
4239 switch (tp->mac_version) {
4240 case RTL_GIGA_MAC_VER_27:
4241 case RTL_GIGA_MAC_VER_28:
4242 case RTL_GIGA_MAC_VER_31:
4243 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4244 break;
4245 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4246 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4247 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4248 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4249 break;
4250 default:
4251 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4252 udelay(100);
4253 break;
4254 }
4255
4256 rtl_hw_reset(tp);
4257 }
4258
4259 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4260 {
4261 u32 val = TX_DMA_BURST << TxDMAShift |
4262 InterFrameGap << TxInterFrameGapShift;
4263
4264 if (rtl_is_8168evl_up(tp))
4265 val |= TXCFG_AUTO_FIFO;
4266
4267 RTL_W32(tp, TxConfig, val);
4268 }
4269
4270 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4271 {
4272
4273 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4274 }
4275
4276 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4277 {
4278
4279
4280
4281
4282
4283 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4284 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4285 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4286 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4287 }
4288
4289 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4290 {
4291 u32 val;
4292
4293 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4294 val = 0x000fff00;
4295 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4296 val = 0x00ffff00;
4297 else
4298 return;
4299
4300 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4301 val |= 0xff;
4302
4303 RTL_W32(tp, 0x7c, val);
4304 }
4305
4306 static void rtl_set_rx_mode(struct net_device *dev)
4307 {
4308 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4309
4310 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
4311 struct rtl8169_private *tp = netdev_priv(dev);
4312 u32 tmp;
4313
4314 if (dev->flags & IFF_PROMISC) {
4315
4316 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4317 rx_mode |= AcceptAllPhys;
4318 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4319 dev->flags & IFF_ALLMULTI ||
4320 tp->mac_version == RTL_GIGA_MAC_VER_35) {
4321
4322 } else if (netdev_mc_empty(dev)) {
4323 rx_mode &= ~AcceptMulticast;
4324 } else {
4325 struct netdev_hw_addr *ha;
4326
4327 mc_filter[1] = mc_filter[0] = 0;
4328 netdev_for_each_mc_addr(ha, dev) {
4329 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4330 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4331 }
4332
4333 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4334 tmp = mc_filter[0];
4335 mc_filter[0] = swab32(mc_filter[1]);
4336 mc_filter[1] = swab32(tmp);
4337 }
4338 }
4339
4340 if (dev->features & NETIF_F_RXALL)
4341 rx_mode |= (AcceptErr | AcceptRunt);
4342
4343 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4344 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4345
4346 tmp = RTL_R32(tp, RxConfig);
4347 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
4348 }
4349
4350 DECLARE_RTL_COND(rtl_csiar_cond)
4351 {
4352 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4353 }
4354
4355 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4356 {
4357 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4358
4359 RTL_W32(tp, CSIDR, value);
4360 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4361 CSIAR_BYTE_ENABLE | func << 16);
4362
4363 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4364 }
4365
4366 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4367 {
4368 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4369
4370 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4371 CSIAR_BYTE_ENABLE);
4372
4373 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4374 RTL_R32(tp, CSIDR) : ~0;
4375 }
4376
4377 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4378 {
4379 struct pci_dev *pdev = tp->pci_dev;
4380 u32 csi;
4381
4382
4383
4384
4385
4386 if (pdev->cfg_size > 0x070f &&
4387 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4388 return;
4389
4390 netdev_notice_once(tp->dev,
4391 "No native access to PCI extended config space, falling back to CSI\n");
4392 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4393 rtl_csi_write(tp, 0x070c, csi | val << 24);
4394 }
4395
4396 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4397 {
4398 rtl_csi_access_enable(tp, 0x27);
4399 }
4400
4401 struct ephy_info {
4402 unsigned int offset;
4403 u16 mask;
4404 u16 bits;
4405 };
4406
4407 static void __rtl_ephy_init(struct rtl8169_private *tp,
4408 const struct ephy_info *e, int len)
4409 {
4410 u16 w;
4411
4412 while (len-- > 0) {
4413 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4414 rtl_ephy_write(tp, e->offset, w);
4415 e++;
4416 }
4417 }
4418
4419 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4420
4421 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4422 {
4423 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4424 PCI_EXP_LNKCTL_CLKREQ_EN);
4425 }
4426
4427 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4428 {
4429 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4430 PCI_EXP_LNKCTL_CLKREQ_EN);
4431 }
4432
4433 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4434 {
4435
4436 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4437 }
4438
4439 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4440 {
4441
4442 if (enable && tp->aspm_manageable) {
4443 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4444 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4445 } else {
4446 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4447 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4448 }
4449
4450 udelay(10);
4451 }
4452
4453 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4454 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4455 {
4456
4457
4458
4459 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4460 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4461 }
4462
4463 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4464 u8 low, u8 high)
4465 {
4466
4467 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4468 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4469 }
4470
4471 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4472 {
4473 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4474 }
4475
4476 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4477 {
4478 rtl_hw_start_8168bb(tp);
4479
4480 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4481 }
4482
4483 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4484 {
4485 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4486
4487 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4488
4489 rtl_disable_clock_request(tp);
4490 }
4491
4492 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4493 {
4494 static const struct ephy_info e_info_8168cp[] = {
4495 { 0x01, 0, 0x0001 },
4496 { 0x02, 0x0800, 0x1000 },
4497 { 0x03, 0, 0x0042 },
4498 { 0x06, 0x0080, 0x0000 },
4499 { 0x07, 0, 0x2000 }
4500 };
4501
4502 rtl_set_def_aspm_entry_latency(tp);
4503
4504 rtl_ephy_init(tp, e_info_8168cp);
4505
4506 __rtl_hw_start_8168cp(tp);
4507 }
4508
4509 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4510 {
4511 rtl_set_def_aspm_entry_latency(tp);
4512
4513 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4514 }
4515
4516 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4517 {
4518 rtl_set_def_aspm_entry_latency(tp);
4519
4520 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4521
4522
4523 RTL_W8(tp, DBG_REG, 0x20);
4524 }
4525
4526 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4527 {
4528 static const struct ephy_info e_info_8168c_1[] = {
4529 { 0x02, 0x0800, 0x1000 },
4530 { 0x03, 0, 0x0002 },
4531 { 0x06, 0x0080, 0x0000 }
4532 };
4533
4534 rtl_set_def_aspm_entry_latency(tp);
4535
4536 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4537
4538 rtl_ephy_init(tp, e_info_8168c_1);
4539
4540 __rtl_hw_start_8168cp(tp);
4541 }
4542
4543 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4544 {
4545 static const struct ephy_info e_info_8168c_2[] = {
4546 { 0x01, 0, 0x0001 },
4547 { 0x03, 0x0400, 0x0020 }
4548 };
4549
4550 rtl_set_def_aspm_entry_latency(tp);
4551
4552 rtl_ephy_init(tp, e_info_8168c_2);
4553
4554 __rtl_hw_start_8168cp(tp);
4555 }
4556
4557 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4558 {
4559 rtl_hw_start_8168c_2(tp);
4560 }
4561
4562 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4563 {
4564 rtl_set_def_aspm_entry_latency(tp);
4565
4566 __rtl_hw_start_8168cp(tp);
4567 }
4568
4569 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4570 {
4571 rtl_set_def_aspm_entry_latency(tp);
4572
4573 rtl_disable_clock_request(tp);
4574
4575 if (tp->dev->mtu <= ETH_DATA_LEN)
4576 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4577 }
4578
4579 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4580 {
4581 rtl_set_def_aspm_entry_latency(tp);
4582
4583 if (tp->dev->mtu <= ETH_DATA_LEN)
4584 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4585
4586 rtl_disable_clock_request(tp);
4587 }
4588
4589 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4590 {
4591 static const struct ephy_info e_info_8168d_4[] = {
4592 { 0x0b, 0x0000, 0x0048 },
4593 { 0x19, 0x0020, 0x0050 },
4594 { 0x0c, 0x0100, 0x0020 },
4595 { 0x10, 0x0004, 0x0000 },
4596 };
4597
4598 rtl_set_def_aspm_entry_latency(tp);
4599
4600 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4601
4602 rtl_ephy_init(tp, e_info_8168d_4);
4603
4604 rtl_enable_clock_request(tp);
4605 }
4606
4607 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4608 {
4609 static const struct ephy_info e_info_8168e_1[] = {
4610 { 0x00, 0x0200, 0x0100 },
4611 { 0x00, 0x0000, 0x0004 },
4612 { 0x06, 0x0002, 0x0001 },
4613 { 0x06, 0x0000, 0x0030 },
4614 { 0x07, 0x0000, 0x2000 },
4615 { 0x00, 0x0000, 0x0020 },
4616 { 0x03, 0x5800, 0x2000 },
4617 { 0x03, 0x0000, 0x0001 },
4618 { 0x01, 0x0800, 0x1000 },
4619 { 0x07, 0x0000, 0x4000 },
4620 { 0x1e, 0x0000, 0x2000 },
4621 { 0x19, 0xffff, 0xfe6c },
4622 { 0x0a, 0x0000, 0x0040 }
4623 };
4624
4625 rtl_set_def_aspm_entry_latency(tp);
4626
4627 rtl_ephy_init(tp, e_info_8168e_1);
4628
4629 rtl_disable_clock_request(tp);
4630
4631
4632 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4633 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4634
4635 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4636 }
4637
4638 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4639 {
4640 static const struct ephy_info e_info_8168e_2[] = {
4641 { 0x09, 0x0000, 0x0080 },
4642 { 0x19, 0x0000, 0x0224 },
4643 { 0x00, 0x0000, 0x0004 },
4644 { 0x0c, 0x3df0, 0x0200 },
4645 };
4646
4647 rtl_set_def_aspm_entry_latency(tp);
4648
4649 rtl_ephy_init(tp, e_info_8168e_2);
4650
4651 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4652 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4653 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4654 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4655 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4656 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4657 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4658
4659 rtl_disable_clock_request(tp);
4660
4661 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4662
4663 rtl8168_config_eee_mac(tp);
4664
4665 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4666 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4667 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4668
4669 rtl_hw_aspm_clkreq_enable(tp, true);
4670 }
4671
4672 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4673 {
4674 rtl_set_def_aspm_entry_latency(tp);
4675
4676 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4677
4678 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4679 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4680 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4681 rtl_reset_packet_filter(tp);
4682 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4683 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4684 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4685 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4686
4687 rtl_disable_clock_request(tp);
4688
4689 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4690 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4691 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4692 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4693
4694 rtl8168_config_eee_mac(tp);
4695 }
4696
4697 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4698 {
4699 static const struct ephy_info e_info_8168f_1[] = {
4700 { 0x06, 0x00c0, 0x0020 },
4701 { 0x08, 0x0001, 0x0002 },
4702 { 0x09, 0x0000, 0x0080 },
4703 { 0x19, 0x0000, 0x0224 },
4704 { 0x00, 0x0000, 0x0004 },
4705 { 0x0c, 0x3df0, 0x0200 },
4706 };
4707
4708 rtl_hw_start_8168f(tp);
4709
4710 rtl_ephy_init(tp, e_info_8168f_1);
4711
4712 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4713 }
4714
4715 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4716 {
4717 static const struct ephy_info e_info_8168f_1[] = {
4718 { 0x06, 0x00c0, 0x0020 },
4719 { 0x0f, 0xffff, 0x5200 },
4720 { 0x19, 0x0000, 0x0224 },
4721 { 0x00, 0x0000, 0x0004 },
4722 { 0x0c, 0x3df0, 0x0200 },
4723 };
4724
4725 rtl_hw_start_8168f(tp);
4726 rtl_pcie_state_l2l3_disable(tp);
4727
4728 rtl_ephy_init(tp, e_info_8168f_1);
4729
4730 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4731 }
4732
4733 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4734 {
4735 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4736 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4737
4738 rtl_set_def_aspm_entry_latency(tp);
4739
4740 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4741
4742 rtl_reset_packet_filter(tp);
4743 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4744
4745 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4746
4747 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4748 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4749
4750 rtl8168_config_eee_mac(tp);
4751
4752 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4753 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4754
4755 rtl_pcie_state_l2l3_disable(tp);
4756 }
4757
4758 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4759 {
4760 static const struct ephy_info e_info_8168g_1[] = {
4761 { 0x00, 0x0008, 0x0000 },
4762 { 0x0c, 0x3ff0, 0x0820 },
4763 { 0x1e, 0x0000, 0x0001 },
4764 { 0x19, 0x8000, 0x0000 }
4765 };
4766
4767 rtl_hw_start_8168g(tp);
4768
4769
4770 rtl_hw_aspm_clkreq_enable(tp, false);
4771 rtl_ephy_init(tp, e_info_8168g_1);
4772 rtl_hw_aspm_clkreq_enable(tp, true);
4773 }
4774
4775 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4776 {
4777 static const struct ephy_info e_info_8168g_2[] = {
4778 { 0x00, 0x0008, 0x0000 },
4779 { 0x0c, 0x3ff0, 0x0820 },
4780 { 0x19, 0xffff, 0x7c00 },
4781 { 0x1e, 0xffff, 0x20eb },
4782 { 0x0d, 0xffff, 0x1666 },
4783 { 0x00, 0xffff, 0x10a3 },
4784 { 0x06, 0xffff, 0xf050 },
4785 { 0x04, 0x0000, 0x0010 },
4786 { 0x1d, 0x4000, 0x0000 },
4787 };
4788
4789 rtl_hw_start_8168g(tp);
4790
4791
4792 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4793 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4794 rtl_ephy_init(tp, e_info_8168g_2);
4795 }
4796
4797 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4798 {
4799 static const struct ephy_info e_info_8411_2[] = {
4800 { 0x00, 0x0008, 0x0000 },
4801 { 0x0c, 0x37d0, 0x0820 },
4802 { 0x1e, 0x0000, 0x0001 },
4803 { 0x19, 0x8021, 0x0000 },
4804 { 0x1e, 0x0000, 0x2000 },
4805 { 0x0d, 0x0100, 0x0200 },
4806 { 0x00, 0x0000, 0x0080 },
4807 { 0x06, 0x0000, 0x0010 },
4808 { 0x04, 0x0000, 0x0010 },
4809 { 0x1d, 0x0000, 0x4000 },
4810 };
4811
4812 rtl_hw_start_8168g(tp);
4813
4814
4815 rtl_hw_aspm_clkreq_enable(tp, false);
4816 rtl_ephy_init(tp, e_info_8411_2);
4817
4818
4819
4820
4821 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4822 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4823 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4824 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4825 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4826 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4827 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4828 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4829 mdelay(3);
4830 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4831
4832 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4833 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4834 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4835 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4836 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4837 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4838 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4839 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4840 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4841 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4842 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4843 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4844 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4845 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4846 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4847 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4848 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4849 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4850 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4851 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4852 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4853 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4854 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4855 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4856 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4857 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4858 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4859 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4860 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4861 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4862 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4863 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4864 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4865 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4866 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4867 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4868 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4869 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4870 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4871 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4872 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4873 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4874 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4875 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4876 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4877 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4878 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4879 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4880 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4881 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4882 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4883 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4884 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4885 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4886 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4887 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4888 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4889 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4890 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4891 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4892 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4893 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4894 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4895 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4896 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4897 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4898 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4899 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4900 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4901 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4902 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4903 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4904 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4905 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4906 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4907 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4908 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4909 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4910 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4911 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4912 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4913 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4914 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4915 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4916 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4917 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4918 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4919 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4920 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4921 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4922 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4923 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4924 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4925 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4926 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4927 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4928 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4929 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4930 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4931 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4932 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4933 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4934 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4935 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4936 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4937 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4938 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4939 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4940 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4941 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4942 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4943
4944 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4945
4946 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4947 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4948 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4949 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4950 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4951 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4952 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4953
4954 rtl_hw_aspm_clkreq_enable(tp, true);
4955 }
4956
4957 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4958 {
4959 static const struct ephy_info e_info_8168h_1[] = {
4960 { 0x1e, 0x0800, 0x0001 },
4961 { 0x1d, 0x0000, 0x0800 },
4962 { 0x05, 0xffff, 0x2089 },
4963 { 0x06, 0xffff, 0x5881 },
4964 { 0x04, 0xffff, 0x854a },
4965 { 0x01, 0xffff, 0x068b }
4966 };
4967 int rg_saw_cnt;
4968
4969
4970 rtl_hw_aspm_clkreq_enable(tp, false);
4971 rtl_ephy_init(tp, e_info_8168h_1);
4972
4973 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4974 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4975
4976 rtl_set_def_aspm_entry_latency(tp);
4977
4978 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4979
4980 rtl_reset_packet_filter(tp);
4981
4982 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4983
4984 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4985
4986 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4987
4988 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4989
4990 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4991 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4992
4993 rtl8168_config_eee_mac(tp);
4994
4995 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4996 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4997
4998 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4999
5000 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5001
5002 rtl_pcie_state_l2l3_disable(tp);
5003
5004 rtl_writephy(tp, 0x1f, 0x0c42);
5005 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5006 rtl_writephy(tp, 0x1f, 0x0000);
5007 if (rg_saw_cnt > 0) {
5008 u16 sw_cnt_1ms_ini;
5009
5010 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5011 sw_cnt_1ms_ini &= 0x0fff;
5012 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
5013 }
5014
5015 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
5016 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
5017 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
5018 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
5019
5020 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5021 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5022 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5023 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5024
5025 rtl_hw_aspm_clkreq_enable(tp, true);
5026 }
5027
5028 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5029 {
5030 rtl8168ep_stop_cmac(tp);
5031
5032 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5033 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5034
5035 rtl_set_def_aspm_entry_latency(tp);
5036
5037 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5038
5039 rtl_reset_packet_filter(tp);
5040
5041 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5042
5043 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5044
5045 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5046
5047 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5048 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5049
5050 rtl8168_config_eee_mac(tp);
5051
5052 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5053
5054 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5055
5056 rtl_pcie_state_l2l3_disable(tp);
5057 }
5058
5059 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5060 {
5061 static const struct ephy_info e_info_8168ep_1[] = {
5062 { 0x00, 0xffff, 0x10ab },
5063 { 0x06, 0xffff, 0xf030 },
5064 { 0x08, 0xffff, 0x2006 },
5065 { 0x0d, 0xffff, 0x1666 },
5066 { 0x0c, 0x3ff0, 0x0000 }
5067 };
5068
5069
5070 rtl_hw_aspm_clkreq_enable(tp, false);
5071 rtl_ephy_init(tp, e_info_8168ep_1);
5072
5073 rtl_hw_start_8168ep(tp);
5074
5075 rtl_hw_aspm_clkreq_enable(tp, true);
5076 }
5077
5078 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5079 {
5080 static const struct ephy_info e_info_8168ep_2[] = {
5081 { 0x00, 0xffff, 0x10a3 },
5082 { 0x19, 0xffff, 0xfc00 },
5083 { 0x1e, 0xffff, 0x20ea }
5084 };
5085
5086
5087 rtl_hw_aspm_clkreq_enable(tp, false);
5088 rtl_ephy_init(tp, e_info_8168ep_2);
5089
5090 rtl_hw_start_8168ep(tp);
5091
5092 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5093 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5094
5095 rtl_hw_aspm_clkreq_enable(tp, true);
5096 }
5097
5098 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5099 {
5100 static const struct ephy_info e_info_8168ep_3[] = {
5101 { 0x00, 0x0000, 0x0080 },
5102 { 0x0d, 0x0100, 0x0200 },
5103 { 0x19, 0x8021, 0x0000 },
5104 { 0x1e, 0x0000, 0x2000 },
5105 };
5106
5107
5108 rtl_hw_aspm_clkreq_enable(tp, false);
5109 rtl_ephy_init(tp, e_info_8168ep_3);
5110
5111 rtl_hw_start_8168ep(tp);
5112
5113 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5114 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5115
5116 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
5117 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5118 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
5119
5120 rtl_hw_aspm_clkreq_enable(tp, true);
5121 }
5122
5123 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5124 {
5125 static const struct ephy_info e_info_8102e_1[] = {
5126 { 0x01, 0, 0x6e65 },
5127 { 0x02, 0, 0x091f },
5128 { 0x03, 0, 0xc2f9 },
5129 { 0x06, 0, 0xafb5 },
5130 { 0x07, 0, 0x0e00 },
5131 { 0x19, 0, 0xec80 },
5132 { 0x01, 0, 0x2e65 },
5133 { 0x01, 0, 0x6e65 }
5134 };
5135 u8 cfg1;
5136
5137 rtl_set_def_aspm_entry_latency(tp);
5138
5139 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5140
5141 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5142
5143 RTL_W8(tp, Config1,
5144 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5145 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5146
5147 cfg1 = RTL_R8(tp, Config1);
5148 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5149 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5150
5151 rtl_ephy_init(tp, e_info_8102e_1);
5152 }
5153
5154 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5155 {
5156 rtl_set_def_aspm_entry_latency(tp);
5157
5158 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5159
5160 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5161 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5162 }
5163
5164 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5165 {
5166 rtl_hw_start_8102e_2(tp);
5167
5168 rtl_ephy_write(tp, 0x03, 0xc2f9);
5169 }
5170
5171 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5172 {
5173 static const struct ephy_info e_info_8105e_1[] = {
5174 { 0x07, 0, 0x4000 },
5175 { 0x19, 0, 0x0200 },
5176 { 0x19, 0, 0x0020 },
5177 { 0x1e, 0, 0x2000 },
5178 { 0x03, 0, 0x0001 },
5179 { 0x19, 0, 0x0100 },
5180 { 0x19, 0, 0x0004 },
5181 { 0x0a, 0, 0x0020 }
5182 };
5183
5184
5185 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5186
5187
5188 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5189
5190 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5191 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5192
5193 rtl_ephy_init(tp, e_info_8105e_1);
5194
5195 rtl_pcie_state_l2l3_disable(tp);
5196 }
5197
5198 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5199 {
5200 rtl_hw_start_8105e_1(tp);
5201 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5202 }
5203
5204 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5205 {
5206 static const struct ephy_info e_info_8402[] = {
5207 { 0x19, 0xffff, 0xff64 },
5208 { 0x1e, 0, 0x4000 }
5209 };
5210
5211 rtl_set_def_aspm_entry_latency(tp);
5212
5213
5214 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5215
5216 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5217
5218 rtl_ephy_init(tp, e_info_8402);
5219
5220 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5221
5222 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5223 rtl_reset_packet_filter(tp);
5224 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5225 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5226 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5227
5228 rtl_pcie_state_l2l3_disable(tp);
5229 }
5230
5231 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5232 {
5233 rtl_hw_aspm_clkreq_enable(tp, false);
5234
5235
5236 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5237
5238 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5239 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5240 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5241
5242 rtl_pcie_state_l2l3_disable(tp);
5243 rtl_hw_aspm_clkreq_enable(tp, true);
5244 }
5245
5246 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
5247 {
5248 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
5249 }
5250
5251 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
5252 {
5253 rtl_pcie_state_l2l3_disable(tp);
5254
5255 RTL_W16(tp, 0x382, 0x221b);
5256 RTL_W8(tp, 0x4500, 0);
5257 RTL_W16(tp, 0x4800, 0);
5258
5259
5260 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
5261
5262 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
5263
5264 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
5265 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
5266
5267 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
5268 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5269 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
5270
5271
5272 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
5273
5274 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
5275 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
5276 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
5277 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
5278 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
5279 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
5280 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
5281 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
5282 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067);
5283 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
5284 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
5285 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0);
5286 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
5287 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
5288 udelay(1);
5289 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
5290 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
5291
5292 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
5293
5294 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
5295
5296 rtl8125_config_eee_mac(tp);
5297
5298 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5299 udelay(10);
5300 }
5301
5302 static void rtl_hw_start_8125_1(struct rtl8169_private *tp)
5303 {
5304 static const struct ephy_info e_info_8125_1[] = {
5305 { 0x01, 0xffff, 0xa812 },
5306 { 0x09, 0xffff, 0x520c },
5307 { 0x04, 0xffff, 0xd000 },
5308 { 0x0d, 0xffff, 0xf702 },
5309 { 0x0a, 0xffff, 0x8653 },
5310 { 0x06, 0xffff, 0x001e },
5311 { 0x08, 0xffff, 0x3595 },
5312 { 0x20, 0xffff, 0x9455 },
5313 { 0x21, 0xffff, 0x99ff },
5314 { 0x02, 0xffff, 0x6046 },
5315 { 0x29, 0xffff, 0xfe00 },
5316 { 0x23, 0xffff, 0xab62 },
5317
5318 { 0x41, 0xffff, 0xa80c },
5319 { 0x49, 0xffff, 0x520c },
5320 { 0x44, 0xffff, 0xd000 },
5321 { 0x4d, 0xffff, 0xf702 },
5322 { 0x4a, 0xffff, 0x8653 },
5323 { 0x46, 0xffff, 0x001e },
5324 { 0x48, 0xffff, 0x3595 },
5325 { 0x60, 0xffff, 0x9455 },
5326 { 0x61, 0xffff, 0x99ff },
5327 { 0x42, 0xffff, 0x6046 },
5328 { 0x69, 0xffff, 0xfe00 },
5329 { 0x63, 0xffff, 0xab62 },
5330 };
5331
5332 rtl_set_def_aspm_entry_latency(tp);
5333
5334
5335 rtl_hw_aspm_clkreq_enable(tp, false);
5336 rtl_ephy_init(tp, e_info_8125_1);
5337
5338 rtl_hw_start_8125_common(tp);
5339 }
5340
5341 static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
5342 {
5343 static const struct ephy_info e_info_8125_2[] = {
5344 { 0x04, 0xffff, 0xd000 },
5345 { 0x0a, 0xffff, 0x8653 },
5346 { 0x23, 0xffff, 0xab66 },
5347 { 0x20, 0xffff, 0x9455 },
5348 { 0x21, 0xffff, 0x99ff },
5349 { 0x29, 0xffff, 0xfe04 },
5350
5351 { 0x44, 0xffff, 0xd000 },
5352 { 0x4a, 0xffff, 0x8653 },
5353 { 0x63, 0xffff, 0xab66 },
5354 { 0x60, 0xffff, 0x9455 },
5355 { 0x61, 0xffff, 0x99ff },
5356 { 0x69, 0xffff, 0xfe04 },
5357 };
5358
5359 rtl_set_def_aspm_entry_latency(tp);
5360
5361
5362 rtl_hw_aspm_clkreq_enable(tp, false);
5363 rtl_ephy_init(tp, e_info_8125_2);
5364
5365 rtl_hw_start_8125_common(tp);
5366 }
5367
5368 static void rtl_hw_config(struct rtl8169_private *tp)
5369 {
5370 static const rtl_generic_fct hw_configs[] = {
5371 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5372 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5373 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5374 [RTL_GIGA_MAC_VER_10] = NULL,
5375 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5376 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5377 [RTL_GIGA_MAC_VER_13] = NULL,
5378 [RTL_GIGA_MAC_VER_14] = NULL,
5379 [RTL_GIGA_MAC_VER_15] = NULL,
5380 [RTL_GIGA_MAC_VER_16] = NULL,
5381 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5382 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5383 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5384 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5385 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5386 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5387 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5388 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5389 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5390 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5391 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5392 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5393 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5394 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5395 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5396 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5397 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5398 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5399 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5400 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5401 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5402 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5403 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5404 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5405 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5406 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5407 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5408 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5409 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5410 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5411 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5412 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5413 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5414 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5415 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5416 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1,
5417 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2,
5418 };
5419
5420 if (hw_configs[tp->mac_version])
5421 hw_configs[tp->mac_version](tp);
5422 }
5423
5424 static void rtl_hw_start_8125(struct rtl8169_private *tp)
5425 {
5426 int i;
5427
5428
5429 for (i = 0xa00; i < 0xb00; i += 4)
5430 RTL_W32(tp, i, 0);
5431
5432 rtl_hw_config(tp);
5433 }
5434
5435 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5436 {
5437 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5438 tp->mac_version == RTL_GIGA_MAC_VER_16)
5439 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5440 PCI_EXP_DEVCTL_NOSNOOP_EN);
5441
5442 if (rtl_is_8168evl_up(tp))
5443 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5444 else
5445 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5446
5447 rtl_hw_config(tp);
5448
5449
5450 RTL_W16(tp, IntrMitigate, 0x0000);
5451 }
5452
5453 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5454 {
5455 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5456 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5457
5458 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5459
5460 tp->cp_cmd |= PCIMulRW;
5461
5462 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5463 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5464 netif_dbg(tp, drv, tp->dev,
5465 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5466 tp->cp_cmd |= (1 << 14);
5467 }
5468
5469 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5470
5471 rtl8169_set_magic_reg(tp, tp->mac_version);
5472
5473 RTL_W32(tp, RxMissed, 0);
5474
5475
5476 RTL_W16(tp, IntrMitigate, 0x0000);
5477 }
5478
5479 static void rtl_hw_start(struct rtl8169_private *tp)
5480 {
5481 rtl_unlock_config_regs(tp);
5482
5483 tp->cp_cmd &= CPCMD_MASK;
5484 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5485
5486 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5487 rtl_hw_start_8169(tp);
5488 else if (rtl_is_8125(tp))
5489 rtl_hw_start_8125(tp);
5490 else
5491 rtl_hw_start_8168(tp);
5492
5493 rtl_set_rx_max_size(tp);
5494 rtl_set_rx_tx_desc_registers(tp);
5495 rtl_lock_config_regs(tp);
5496
5497 rtl_jumbo_config(tp, tp->dev->mtu);
5498
5499
5500 RTL_R16(tp, CPlusCmd);
5501 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5502 rtl_init_rxcfg(tp);
5503 rtl_set_tx_config_registers(tp);
5504 rtl_set_rx_mode(tp->dev);
5505 rtl_irq_enable(tp);
5506 }
5507
5508 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5509 {
5510 struct rtl8169_private *tp = netdev_priv(dev);
5511
5512 rtl_jumbo_config(tp, new_mtu);
5513
5514 dev->mtu = new_mtu;
5515 netdev_update_features(dev);
5516
5517 return 0;
5518 }
5519
5520 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5521 {
5522 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5523 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5524 }
5525
5526 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5527 {
5528 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5529
5530
5531 dma_wmb();
5532
5533 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5534 }
5535
5536 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5537 struct RxDesc *desc)
5538 {
5539 struct device *d = tp_to_dev(tp);
5540 int node = dev_to_node(d);
5541 dma_addr_t mapping;
5542 struct page *data;
5543
5544 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
5545 if (!data)
5546 return NULL;
5547
5548 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5549 if (unlikely(dma_mapping_error(d, mapping))) {
5550 if (net_ratelimit())
5551 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5552 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
5553 return NULL;
5554 }
5555
5556 desc->addr = cpu_to_le64(mapping);
5557 rtl8169_mark_to_asic(desc);
5558
5559 return data;
5560 }
5561
5562 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5563 {
5564 unsigned int i;
5565
5566 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
5567 dma_unmap_page(tp_to_dev(tp),
5568 le64_to_cpu(tp->RxDescArray[i].addr),
5569 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5570 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
5571 tp->Rx_databuff[i] = NULL;
5572 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5573 }
5574 }
5575
5576 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5577 {
5578 desc->opts1 |= cpu_to_le32(RingEnd);
5579 }
5580
5581 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5582 {
5583 unsigned int i;
5584
5585 for (i = 0; i < NUM_RX_DESC; i++) {
5586 struct page *data;
5587
5588 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5589 if (!data) {
5590 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5591 goto err_out;
5592 }
5593 tp->Rx_databuff[i] = data;
5594 }
5595
5596 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5597 return 0;
5598
5599 err_out:
5600 rtl8169_rx_clear(tp);
5601 return -ENOMEM;
5602 }
5603
5604 static int rtl8169_init_ring(struct rtl8169_private *tp)
5605 {
5606 rtl8169_init_ring_indexes(tp);
5607
5608 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5609 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5610
5611 return rtl8169_rx_fill(tp);
5612 }
5613
5614 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5615 struct TxDesc *desc)
5616 {
5617 unsigned int len = tx_skb->len;
5618
5619 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5620
5621 desc->opts1 = 0x00;
5622 desc->opts2 = 0x00;
5623 desc->addr = 0x00;
5624 tx_skb->len = 0;
5625 }
5626
5627 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5628 unsigned int n)
5629 {
5630 unsigned int i;
5631
5632 for (i = 0; i < n; i++) {
5633 unsigned int entry = (start + i) % NUM_TX_DESC;
5634 struct ring_info *tx_skb = tp->tx_skb + entry;
5635 unsigned int len = tx_skb->len;
5636
5637 if (len) {
5638 struct sk_buff *skb = tx_skb->skb;
5639
5640 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5641 tp->TxDescArray + entry);
5642 if (skb) {
5643 dev_consume_skb_any(skb);
5644 tx_skb->skb = NULL;
5645 }
5646 }
5647 }
5648 }
5649
5650 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5651 {
5652 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5653 tp->cur_tx = tp->dirty_tx = 0;
5654 netdev_reset_queue(tp->dev);
5655 }
5656
5657 static void rtl_reset_work(struct rtl8169_private *tp)
5658 {
5659 struct net_device *dev = tp->dev;
5660 int i;
5661
5662 napi_disable(&tp->napi);
5663 netif_stop_queue(dev);
5664 synchronize_rcu();
5665
5666 rtl8169_hw_reset(tp);
5667
5668 for (i = 0; i < NUM_RX_DESC; i++)
5669 rtl8169_mark_to_asic(tp->RxDescArray + i);
5670
5671 rtl8169_tx_clear(tp);
5672 rtl8169_init_ring_indexes(tp);
5673
5674 napi_enable(&tp->napi);
5675 rtl_hw_start(tp);
5676 netif_wake_queue(dev);
5677 }
5678
5679 static void rtl8169_tx_timeout(struct net_device *dev)
5680 {
5681 struct rtl8169_private *tp = netdev_priv(dev);
5682
5683 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5684 }
5685
5686 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5687 {
5688 u32 status = opts0 | len;
5689
5690 if (entry == NUM_TX_DESC - 1)
5691 status |= RingEnd;
5692
5693 return cpu_to_le32(status);
5694 }
5695
5696 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5697 u32 *opts)
5698 {
5699 struct skb_shared_info *info = skb_shinfo(skb);
5700 unsigned int cur_frag, entry;
5701 struct TxDesc *uninitialized_var(txd);
5702 struct device *d = tp_to_dev(tp);
5703
5704 entry = tp->cur_tx;
5705 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5706 const skb_frag_t *frag = info->frags + cur_frag;
5707 dma_addr_t mapping;
5708 u32 len;
5709 void *addr;
5710
5711 entry = (entry + 1) % NUM_TX_DESC;
5712
5713 txd = tp->TxDescArray + entry;
5714 len = skb_frag_size(frag);
5715 addr = skb_frag_address(frag);
5716 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5717 if (unlikely(dma_mapping_error(d, mapping))) {
5718 if (net_ratelimit())
5719 netif_err(tp, drv, tp->dev,
5720 "Failed to map TX fragments DMA!\n");
5721 goto err_out;
5722 }
5723
5724 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5725 txd->opts2 = cpu_to_le32(opts[1]);
5726 txd->addr = cpu_to_le64(mapping);
5727
5728 tp->tx_skb[entry].len = len;
5729 }
5730
5731 if (cur_frag) {
5732 tp->tx_skb[entry].skb = skb;
5733 txd->opts1 |= cpu_to_le32(LastFrag);
5734 }
5735
5736 return cur_frag;
5737
5738 err_out:
5739 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5740 return -EIO;
5741 }
5742
5743 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5744 {
5745 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5746 }
5747
5748
5749
5750
5751
5752 static int msdn_giant_send_check(struct sk_buff *skb)
5753 {
5754 const struct ipv6hdr *ipv6h;
5755 struct tcphdr *th;
5756 int ret;
5757
5758 ret = skb_cow_head(skb, 0);
5759 if (ret)
5760 return ret;
5761
5762 ipv6h = ipv6_hdr(skb);
5763 th = tcp_hdr(skb);
5764
5765 th->check = 0;
5766 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5767
5768 return ret;
5769 }
5770
5771 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5772 {
5773 u32 mss = skb_shinfo(skb)->gso_size;
5774
5775 if (mss) {
5776 opts[0] |= TD_LSO;
5777 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5778 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5779 const struct iphdr *ip = ip_hdr(skb);
5780
5781 if (ip->protocol == IPPROTO_TCP)
5782 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5783 else if (ip->protocol == IPPROTO_UDP)
5784 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5785 else
5786 WARN_ON_ONCE(1);
5787 }
5788 }
5789
5790 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5791 struct sk_buff *skb, u32 *opts)
5792 {
5793 u32 transport_offset = (u32)skb_transport_offset(skb);
5794 u32 mss = skb_shinfo(skb)->gso_size;
5795
5796 if (mss) {
5797 switch (vlan_get_protocol(skb)) {
5798 case htons(ETH_P_IP):
5799 opts[0] |= TD1_GTSENV4;
5800 break;
5801
5802 case htons(ETH_P_IPV6):
5803 if (msdn_giant_send_check(skb))
5804 return false;
5805
5806 opts[0] |= TD1_GTSENV6;
5807 break;
5808
5809 default:
5810 WARN_ON_ONCE(1);
5811 break;
5812 }
5813
5814 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5815 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5816 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5817 u8 ip_protocol;
5818
5819 switch (vlan_get_protocol(skb)) {
5820 case htons(ETH_P_IP):
5821 opts[1] |= TD1_IPv4_CS;
5822 ip_protocol = ip_hdr(skb)->protocol;
5823 break;
5824
5825 case htons(ETH_P_IPV6):
5826 opts[1] |= TD1_IPv6_CS;
5827 ip_protocol = ipv6_hdr(skb)->nexthdr;
5828 break;
5829
5830 default:
5831 ip_protocol = IPPROTO_RAW;
5832 break;
5833 }
5834
5835 if (ip_protocol == IPPROTO_TCP)
5836 opts[1] |= TD1_TCP_CS;
5837 else if (ip_protocol == IPPROTO_UDP)
5838 opts[1] |= TD1_UDP_CS;
5839 else
5840 WARN_ON_ONCE(1);
5841
5842 opts[1] |= transport_offset << TCPHO_SHIFT;
5843 } else {
5844 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5845 return !eth_skb_pad(skb);
5846 }
5847
5848 return true;
5849 }
5850
5851 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5852 unsigned int nr_frags)
5853 {
5854 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5855
5856
5857 return slots_avail > nr_frags;
5858 }
5859
5860
5861 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5862 {
5863 switch (tp->mac_version) {
5864 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5865 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5866 return false;
5867 default:
5868 return true;
5869 }
5870 }
5871
5872 static void rtl8169_doorbell(struct rtl8169_private *tp)
5873 {
5874 if (rtl_is_8125(tp))
5875 RTL_W16(tp, TxPoll_8125, BIT(0));
5876 else
5877 RTL_W8(tp, TxPoll, NPQ);
5878 }
5879
5880 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5881 struct net_device *dev)
5882 {
5883 struct rtl8169_private *tp = netdev_priv(dev);
5884 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5885 struct TxDesc *txd = tp->TxDescArray + entry;
5886 struct device *d = tp_to_dev(tp);
5887 dma_addr_t mapping;
5888 u32 opts[2], len;
5889 bool stop_queue;
5890 bool door_bell;
5891 int frags;
5892
5893 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5894 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5895 goto err_stop_0;
5896 }
5897
5898 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5899 goto err_stop_0;
5900
5901 opts[1] = rtl8169_tx_vlan_tag(skb);
5902 opts[0] = DescOwn;
5903
5904 if (rtl_chip_supports_csum_v2(tp)) {
5905 if (!rtl8169_tso_csum_v2(tp, skb, opts))
5906 goto err_dma_0;
5907 } else {
5908 rtl8169_tso_csum_v1(skb, opts);
5909 }
5910
5911 len = skb_headlen(skb);
5912 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5913 if (unlikely(dma_mapping_error(d, mapping))) {
5914 if (net_ratelimit())
5915 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5916 goto err_dma_0;
5917 }
5918
5919 tp->tx_skb[entry].len = len;
5920 txd->addr = cpu_to_le64(mapping);
5921
5922 frags = rtl8169_xmit_frags(tp, skb, opts);
5923 if (frags < 0)
5924 goto err_dma_1;
5925 else if (frags)
5926 opts[0] |= FirstFrag;
5927 else {
5928 opts[0] |= FirstFrag | LastFrag;
5929 tp->tx_skb[entry].skb = skb;
5930 }
5931
5932 txd->opts2 = cpu_to_le32(opts[1]);
5933
5934 skb_tx_timestamp(skb);
5935
5936
5937 dma_wmb();
5938
5939 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
5940
5941 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5942
5943
5944 wmb();
5945
5946 tp->cur_tx += frags + 1;
5947
5948 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
5949 if (unlikely(stop_queue)) {
5950
5951
5952
5953 smp_wmb();
5954 netif_stop_queue(dev);
5955 door_bell = true;
5956 }
5957
5958 if (door_bell)
5959 rtl8169_doorbell(tp);
5960
5961 if (unlikely(stop_queue)) {
5962
5963
5964
5965
5966
5967
5968
5969 smp_mb();
5970 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5971 netif_start_queue(dev);
5972 }
5973
5974 return NETDEV_TX_OK;
5975
5976 err_dma_1:
5977 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5978 err_dma_0:
5979 dev_kfree_skb_any(skb);
5980 dev->stats.tx_dropped++;
5981 return NETDEV_TX_OK;
5982
5983 err_stop_0:
5984 netif_stop_queue(dev);
5985 dev->stats.tx_dropped++;
5986 return NETDEV_TX_BUSY;
5987 }
5988
5989 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
5990 struct net_device *dev,
5991 netdev_features_t features)
5992 {
5993 int transport_offset = skb_transport_offset(skb);
5994 struct rtl8169_private *tp = netdev_priv(dev);
5995
5996 if (skb_is_gso(skb)) {
5997 if (transport_offset > GTTCPHO_MAX &&
5998 rtl_chip_supports_csum_v2(tp))
5999 features &= ~NETIF_F_ALL_TSO;
6000 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6001 if (skb->len < ETH_ZLEN) {
6002 switch (tp->mac_version) {
6003 case RTL_GIGA_MAC_VER_11:
6004 case RTL_GIGA_MAC_VER_12:
6005 case RTL_GIGA_MAC_VER_17:
6006 case RTL_GIGA_MAC_VER_34:
6007 features &= ~NETIF_F_CSUM_MASK;
6008 break;
6009 default:
6010 break;
6011 }
6012 }
6013
6014 if (transport_offset > TCPHO_MAX &&
6015 rtl_chip_supports_csum_v2(tp))
6016 features &= ~NETIF_F_CSUM_MASK;
6017 }
6018
6019 return vlan_features_check(skb, features);
6020 }
6021
6022 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6023 {
6024 struct rtl8169_private *tp = netdev_priv(dev);
6025 struct pci_dev *pdev = tp->pci_dev;
6026 u16 pci_status, pci_cmd;
6027
6028 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6029 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6030
6031 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6032 pci_cmd, pci_status);
6033
6034
6035
6036
6037
6038
6039
6040
6041
6042 if (pdev->broken_parity_status)
6043 pci_cmd &= ~PCI_COMMAND_PARITY;
6044 else
6045 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6046
6047 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6048
6049 pci_write_config_word(pdev, PCI_STATUS,
6050 pci_status & (PCI_STATUS_DETECTED_PARITY |
6051 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6052 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6053
6054 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6055 }
6056
6057 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6058 int budget)
6059 {
6060 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6061
6062 dirty_tx = tp->dirty_tx;
6063 smp_rmb();
6064 tx_left = tp->cur_tx - dirty_tx;
6065
6066 while (tx_left > 0) {
6067 unsigned int entry = dirty_tx % NUM_TX_DESC;
6068 struct ring_info *tx_skb = tp->tx_skb + entry;
6069 u32 status;
6070
6071 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6072 if (status & DescOwn)
6073 break;
6074
6075
6076
6077
6078
6079 dma_rmb();
6080
6081 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6082 tp->TxDescArray + entry);
6083 if (tx_skb->skb) {
6084 pkts_compl++;
6085 bytes_compl += tx_skb->skb->len;
6086 napi_consume_skb(tx_skb->skb, budget);
6087 tx_skb->skb = NULL;
6088 }
6089 dirty_tx++;
6090 tx_left--;
6091 }
6092
6093 if (tp->dirty_tx != dirty_tx) {
6094 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6095
6096 u64_stats_update_begin(&tp->tx_stats.syncp);
6097 tp->tx_stats.packets += pkts_compl;
6098 tp->tx_stats.bytes += bytes_compl;
6099 u64_stats_update_end(&tp->tx_stats.syncp);
6100
6101 tp->dirty_tx = dirty_tx;
6102
6103
6104
6105
6106
6107
6108
6109 smp_mb();
6110 if (netif_queue_stopped(dev) &&
6111 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6112 netif_wake_queue(dev);
6113 }
6114
6115
6116
6117
6118
6119
6120 if (tp->cur_tx != dirty_tx)
6121 rtl8169_doorbell(tp);
6122 }
6123 }
6124
6125 static inline int rtl8169_fragmented_frame(u32 status)
6126 {
6127 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6128 }
6129
6130 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6131 {
6132 u32 status = opts1 & RxProtoMask;
6133
6134 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6135 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6136 skb->ip_summed = CHECKSUM_UNNECESSARY;
6137 else
6138 skb_checksum_none_assert(skb);
6139 }
6140
6141 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6142 {
6143 unsigned int cur_rx, rx_left;
6144 unsigned int count;
6145
6146 cur_rx = tp->cur_rx;
6147
6148 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6149 unsigned int entry = cur_rx % NUM_RX_DESC;
6150 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
6151 struct RxDesc *desc = tp->RxDescArray + entry;
6152 u32 status;
6153
6154 status = le32_to_cpu(desc->opts1);
6155 if (status & DescOwn)
6156 break;
6157
6158
6159
6160
6161
6162 dma_rmb();
6163
6164 if (unlikely(status & RxRES)) {
6165 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6166 status);
6167 dev->stats.rx_errors++;
6168 if (status & (RxRWT | RxRUNT))
6169 dev->stats.rx_length_errors++;
6170 if (status & RxCRC)
6171 dev->stats.rx_crc_errors++;
6172 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6173 dev->features & NETIF_F_RXALL) {
6174 goto process_pkt;
6175 }
6176 } else {
6177 unsigned int pkt_size;
6178 struct sk_buff *skb;
6179
6180 process_pkt:
6181 pkt_size = status & GENMASK(13, 0);
6182 if (likely(!(dev->features & NETIF_F_RXFCS)))
6183 pkt_size -= ETH_FCS_LEN;
6184
6185
6186
6187
6188
6189 if (unlikely(rtl8169_fragmented_frame(status))) {
6190 dev->stats.rx_dropped++;
6191 dev->stats.rx_length_errors++;
6192 goto release_descriptor;
6193 }
6194
6195 skb = napi_alloc_skb(&tp->napi, pkt_size);
6196 if (unlikely(!skb)) {
6197 dev->stats.rx_dropped++;
6198 goto release_descriptor;
6199 }
6200
6201 dma_sync_single_for_cpu(tp_to_dev(tp),
6202 le64_to_cpu(desc->addr),
6203 pkt_size, DMA_FROM_DEVICE);
6204 prefetch(rx_buf);
6205 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
6206 skb->tail += pkt_size;
6207 skb->len = pkt_size;
6208
6209 dma_sync_single_for_device(tp_to_dev(tp),
6210 le64_to_cpu(desc->addr),
6211 pkt_size, DMA_FROM_DEVICE);
6212
6213 rtl8169_rx_csum(skb, status);
6214 skb->protocol = eth_type_trans(skb, dev);
6215
6216 rtl8169_rx_vlan_tag(desc, skb);
6217
6218 if (skb->pkt_type == PACKET_MULTICAST)
6219 dev->stats.multicast++;
6220
6221 napi_gro_receive(&tp->napi, skb);
6222
6223 u64_stats_update_begin(&tp->rx_stats.syncp);
6224 tp->rx_stats.packets++;
6225 tp->rx_stats.bytes += pkt_size;
6226 u64_stats_update_end(&tp->rx_stats.syncp);
6227 }
6228 release_descriptor:
6229 desc->opts2 = 0;
6230 rtl8169_mark_to_asic(desc);
6231 }
6232
6233 count = cur_rx - tp->cur_rx;
6234 tp->cur_rx = cur_rx;
6235
6236 return count;
6237 }
6238
6239 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6240 {
6241 struct rtl8169_private *tp = dev_instance;
6242 u32 status = rtl_get_events(tp);
6243
6244 if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
6245 !(status & tp->irq_mask))
6246 return IRQ_NONE;
6247
6248 if (unlikely(status & SYSErr)) {
6249 rtl8169_pcierr_interrupt(tp->dev);
6250 goto out;
6251 }
6252
6253 if (status & LinkChg)
6254 phy_mac_interrupt(tp->phydev);
6255
6256 if (unlikely(status & RxFIFOOver &&
6257 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6258 netif_stop_queue(tp->dev);
6259
6260 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6261 }
6262
6263 rtl_irq_disable(tp);
6264 napi_schedule_irqoff(&tp->napi);
6265 out:
6266 rtl_ack_events(tp, status);
6267
6268 return IRQ_HANDLED;
6269 }
6270
6271 static void rtl_task(struct work_struct *work)
6272 {
6273 static const struct {
6274 int bitnr;
6275 void (*action)(struct rtl8169_private *);
6276 } rtl_work[] = {
6277 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6278 };
6279 struct rtl8169_private *tp =
6280 container_of(work, struct rtl8169_private, wk.work);
6281 struct net_device *dev = tp->dev;
6282 int i;
6283
6284 rtl_lock_work(tp);
6285
6286 if (!netif_running(dev) ||
6287 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6288 goto out_unlock;
6289
6290 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6291 bool pending;
6292
6293 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6294 if (pending)
6295 rtl_work[i].action(tp);
6296 }
6297
6298 out_unlock:
6299 rtl_unlock_work(tp);
6300 }
6301
6302 static int rtl8169_poll(struct napi_struct *napi, int budget)
6303 {
6304 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6305 struct net_device *dev = tp->dev;
6306 int work_done;
6307
6308 work_done = rtl_rx(dev, tp, (u32) budget);
6309
6310 rtl_tx(dev, tp, budget);
6311
6312 if (work_done < budget) {
6313 napi_complete_done(napi, work_done);
6314 rtl_irq_enable(tp);
6315 }
6316
6317 return work_done;
6318 }
6319
6320 static void rtl8169_rx_missed(struct net_device *dev)
6321 {
6322 struct rtl8169_private *tp = netdev_priv(dev);
6323
6324 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6325 return;
6326
6327 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6328 RTL_W32(tp, RxMissed, 0);
6329 }
6330
6331 static void r8169_phylink_handler(struct net_device *ndev)
6332 {
6333 struct rtl8169_private *tp = netdev_priv(ndev);
6334
6335 if (netif_carrier_ok(ndev)) {
6336 rtl_link_chg_patch(tp);
6337 pm_request_resume(&tp->pci_dev->dev);
6338 } else {
6339 pm_runtime_idle(&tp->pci_dev->dev);
6340 }
6341
6342 if (net_ratelimit())
6343 phy_print_status(tp->phydev);
6344 }
6345
6346 static int r8169_phy_connect(struct rtl8169_private *tp)
6347 {
6348 struct phy_device *phydev = tp->phydev;
6349 phy_interface_t phy_mode;
6350 int ret;
6351
6352 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6353 PHY_INTERFACE_MODE_MII;
6354
6355 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6356 phy_mode);
6357 if (ret)
6358 return ret;
6359
6360 if (!tp->supports_gmii)
6361 phy_set_max_speed(phydev, SPEED_100);
6362
6363 phy_support_asym_pause(phydev);
6364
6365 phy_attached_info(phydev);
6366
6367 return 0;
6368 }
6369
6370 static void rtl8169_down(struct net_device *dev)
6371 {
6372 struct rtl8169_private *tp = netdev_priv(dev);
6373
6374 phy_stop(tp->phydev);
6375
6376 napi_disable(&tp->napi);
6377 netif_stop_queue(dev);
6378
6379 rtl8169_hw_reset(tp);
6380
6381
6382
6383
6384
6385 rtl8169_rx_missed(dev);
6386
6387
6388 synchronize_rcu();
6389
6390 rtl8169_tx_clear(tp);
6391
6392 rtl8169_rx_clear(tp);
6393
6394 rtl_pll_power_down(tp);
6395 }
6396
6397 static int rtl8169_close(struct net_device *dev)
6398 {
6399 struct rtl8169_private *tp = netdev_priv(dev);
6400 struct pci_dev *pdev = tp->pci_dev;
6401
6402 pm_runtime_get_sync(&pdev->dev);
6403
6404
6405 rtl8169_update_counters(tp);
6406
6407 rtl_lock_work(tp);
6408
6409 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6410
6411 rtl8169_down(dev);
6412 rtl_unlock_work(tp);
6413
6414 cancel_work_sync(&tp->wk.work);
6415
6416 phy_disconnect(tp->phydev);
6417
6418 pci_free_irq(pdev, 0, tp);
6419
6420 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6421 tp->RxPhyAddr);
6422 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6423 tp->TxPhyAddr);
6424 tp->TxDescArray = NULL;
6425 tp->RxDescArray = NULL;
6426
6427 pm_runtime_put_sync(&pdev->dev);
6428
6429 return 0;
6430 }
6431
6432 #ifdef CONFIG_NET_POLL_CONTROLLER
6433 static void rtl8169_netpoll(struct net_device *dev)
6434 {
6435 struct rtl8169_private *tp = netdev_priv(dev);
6436
6437 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6438 }
6439 #endif
6440
6441 static int rtl_open(struct net_device *dev)
6442 {
6443 struct rtl8169_private *tp = netdev_priv(dev);
6444 struct pci_dev *pdev = tp->pci_dev;
6445 int retval = -ENOMEM;
6446
6447 pm_runtime_get_sync(&pdev->dev);
6448
6449
6450
6451
6452
6453 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6454 &tp->TxPhyAddr, GFP_KERNEL);
6455 if (!tp->TxDescArray)
6456 goto err_pm_runtime_put;
6457
6458 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6459 &tp->RxPhyAddr, GFP_KERNEL);
6460 if (!tp->RxDescArray)
6461 goto err_free_tx_0;
6462
6463 retval = rtl8169_init_ring(tp);
6464 if (retval < 0)
6465 goto err_free_rx_1;
6466
6467 rtl_request_firmware(tp);
6468
6469 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6470 dev->name);
6471 if (retval < 0)
6472 goto err_release_fw_2;
6473
6474 retval = r8169_phy_connect(tp);
6475 if (retval)
6476 goto err_free_irq;
6477
6478 rtl_lock_work(tp);
6479
6480 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6481
6482 napi_enable(&tp->napi);
6483
6484 rtl8169_init_phy(dev, tp);
6485
6486 rtl_pll_power_up(tp);
6487
6488 rtl_hw_start(tp);
6489
6490 if (!rtl8169_init_counter_offsets(tp))
6491 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6492
6493 phy_start(tp->phydev);
6494 netif_start_queue(dev);
6495
6496 rtl_unlock_work(tp);
6497
6498 pm_runtime_put_sync(&pdev->dev);
6499 out:
6500 return retval;
6501
6502 err_free_irq:
6503 pci_free_irq(pdev, 0, tp);
6504 err_release_fw_2:
6505 rtl_release_firmware(tp);
6506 rtl8169_rx_clear(tp);
6507 err_free_rx_1:
6508 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6509 tp->RxPhyAddr);
6510 tp->RxDescArray = NULL;
6511 err_free_tx_0:
6512 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6513 tp->TxPhyAddr);
6514 tp->TxDescArray = NULL;
6515 err_pm_runtime_put:
6516 pm_runtime_put_noidle(&pdev->dev);
6517 goto out;
6518 }
6519
6520 static void
6521 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6522 {
6523 struct rtl8169_private *tp = netdev_priv(dev);
6524 struct pci_dev *pdev = tp->pci_dev;
6525 struct rtl8169_counters *counters = tp->counters;
6526 unsigned int start;
6527
6528 pm_runtime_get_noresume(&pdev->dev);
6529
6530 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6531 rtl8169_rx_missed(dev);
6532
6533 do {
6534 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6535 stats->rx_packets = tp->rx_stats.packets;
6536 stats->rx_bytes = tp->rx_stats.bytes;
6537 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6538
6539 do {
6540 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6541 stats->tx_packets = tp->tx_stats.packets;
6542 stats->tx_bytes = tp->tx_stats.bytes;
6543 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6544
6545 stats->rx_dropped = dev->stats.rx_dropped;
6546 stats->tx_dropped = dev->stats.tx_dropped;
6547 stats->rx_length_errors = dev->stats.rx_length_errors;
6548 stats->rx_errors = dev->stats.rx_errors;
6549 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6550 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6551 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6552 stats->multicast = dev->stats.multicast;
6553
6554
6555
6556
6557
6558 if (pm_runtime_active(&pdev->dev))
6559 rtl8169_update_counters(tp);
6560
6561
6562
6563
6564
6565 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6566 le64_to_cpu(tp->tc_offset.tx_errors);
6567 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6568 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6569 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6570 le16_to_cpu(tp->tc_offset.tx_aborted);
6571
6572 pm_runtime_put_noidle(&pdev->dev);
6573 }
6574
6575 static void rtl8169_net_suspend(struct net_device *dev)
6576 {
6577 struct rtl8169_private *tp = netdev_priv(dev);
6578
6579 if (!netif_running(dev))
6580 return;
6581
6582 phy_stop(tp->phydev);
6583 netif_device_detach(dev);
6584
6585 rtl_lock_work(tp);
6586 napi_disable(&tp->napi);
6587
6588 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6589
6590 rtl_unlock_work(tp);
6591
6592 rtl_pll_power_down(tp);
6593 }
6594
6595 #ifdef CONFIG_PM
6596
6597 static int rtl8169_suspend(struct device *device)
6598 {
6599 struct net_device *dev = dev_get_drvdata(device);
6600 struct rtl8169_private *tp = netdev_priv(dev);
6601
6602 rtl8169_net_suspend(dev);
6603 clk_disable_unprepare(tp->clk);
6604
6605 return 0;
6606 }
6607
6608 static void __rtl8169_resume(struct net_device *dev)
6609 {
6610 struct rtl8169_private *tp = netdev_priv(dev);
6611
6612 netif_device_attach(dev);
6613
6614 rtl_pll_power_up(tp);
6615 rtl8169_init_phy(dev, tp);
6616
6617 phy_start(tp->phydev);
6618
6619 rtl_lock_work(tp);
6620 napi_enable(&tp->napi);
6621 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6622 rtl_reset_work(tp);
6623 rtl_unlock_work(tp);
6624 }
6625
6626 static int rtl8169_resume(struct device *device)
6627 {
6628 struct net_device *dev = dev_get_drvdata(device);
6629 struct rtl8169_private *tp = netdev_priv(dev);
6630
6631 rtl_rar_set(tp, dev->dev_addr);
6632
6633 clk_prepare_enable(tp->clk);
6634
6635 if (netif_running(dev))
6636 __rtl8169_resume(dev);
6637
6638 return 0;
6639 }
6640
6641 static int rtl8169_runtime_suspend(struct device *device)
6642 {
6643 struct net_device *dev = dev_get_drvdata(device);
6644 struct rtl8169_private *tp = netdev_priv(dev);
6645
6646 if (!tp->TxDescArray)
6647 return 0;
6648
6649 rtl_lock_work(tp);
6650 __rtl8169_set_wol(tp, WAKE_ANY);
6651 rtl_unlock_work(tp);
6652
6653 rtl8169_net_suspend(dev);
6654
6655
6656 rtl8169_rx_missed(dev);
6657 rtl8169_update_counters(tp);
6658
6659 return 0;
6660 }
6661
6662 static int rtl8169_runtime_resume(struct device *device)
6663 {
6664 struct net_device *dev = dev_get_drvdata(device);
6665 struct rtl8169_private *tp = netdev_priv(dev);
6666
6667 rtl_rar_set(tp, dev->dev_addr);
6668
6669 if (!tp->TxDescArray)
6670 return 0;
6671
6672 rtl_lock_work(tp);
6673 __rtl8169_set_wol(tp, tp->saved_wolopts);
6674 rtl_unlock_work(tp);
6675
6676 __rtl8169_resume(dev);
6677
6678 return 0;
6679 }
6680
6681 static int rtl8169_runtime_idle(struct device *device)
6682 {
6683 struct net_device *dev = dev_get_drvdata(device);
6684
6685 if (!netif_running(dev) || !netif_carrier_ok(dev))
6686 pm_schedule_suspend(device, 10000);
6687
6688 return -EBUSY;
6689 }
6690
6691 static const struct dev_pm_ops rtl8169_pm_ops = {
6692 .suspend = rtl8169_suspend,
6693 .resume = rtl8169_resume,
6694 .freeze = rtl8169_suspend,
6695 .thaw = rtl8169_resume,
6696 .poweroff = rtl8169_suspend,
6697 .restore = rtl8169_resume,
6698 .runtime_suspend = rtl8169_runtime_suspend,
6699 .runtime_resume = rtl8169_runtime_resume,
6700 .runtime_idle = rtl8169_runtime_idle,
6701 };
6702
6703 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6704
6705 #else
6706
6707 #define RTL8169_PM_OPS NULL
6708
6709 #endif
6710
6711 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6712 {
6713
6714 switch (tp->mac_version) {
6715 case RTL_GIGA_MAC_VER_11:
6716 case RTL_GIGA_MAC_VER_12:
6717 case RTL_GIGA_MAC_VER_17:
6718 pci_clear_master(tp->pci_dev);
6719
6720 RTL_W8(tp, ChipCmd, CmdRxEnb);
6721
6722 RTL_R8(tp, ChipCmd);
6723 break;
6724 default:
6725 break;
6726 }
6727 }
6728
6729 static void rtl_shutdown(struct pci_dev *pdev)
6730 {
6731 struct net_device *dev = pci_get_drvdata(pdev);
6732 struct rtl8169_private *tp = netdev_priv(dev);
6733
6734 rtl8169_net_suspend(dev);
6735
6736
6737 rtl_rar_set(tp, dev->perm_addr);
6738
6739 rtl8169_hw_reset(tp);
6740
6741 if (system_state == SYSTEM_POWER_OFF) {
6742 if (tp->saved_wolopts) {
6743 rtl_wol_suspend_quirk(tp);
6744 rtl_wol_shutdown_quirk(tp);
6745 }
6746
6747 pci_wake_from_d3(pdev, true);
6748 pci_set_power_state(pdev, PCI_D3hot);
6749 }
6750 }
6751
6752 static void rtl_remove_one(struct pci_dev *pdev)
6753 {
6754 struct net_device *dev = pci_get_drvdata(pdev);
6755 struct rtl8169_private *tp = netdev_priv(dev);
6756
6757 if (r8168_check_dash(tp))
6758 rtl8168_driver_stop(tp);
6759
6760 netif_napi_del(&tp->napi);
6761
6762 unregister_netdev(dev);
6763 mdiobus_unregister(tp->phydev->mdio.bus);
6764
6765 rtl_release_firmware(tp);
6766
6767 if (pci_dev_run_wake(pdev))
6768 pm_runtime_get_noresume(&pdev->dev);
6769
6770
6771 rtl_rar_set(tp, dev->perm_addr);
6772 }
6773
6774 static const struct net_device_ops rtl_netdev_ops = {
6775 .ndo_open = rtl_open,
6776 .ndo_stop = rtl8169_close,
6777 .ndo_get_stats64 = rtl8169_get_stats64,
6778 .ndo_start_xmit = rtl8169_start_xmit,
6779 .ndo_features_check = rtl8169_features_check,
6780 .ndo_tx_timeout = rtl8169_tx_timeout,
6781 .ndo_validate_addr = eth_validate_addr,
6782 .ndo_change_mtu = rtl8169_change_mtu,
6783 .ndo_fix_features = rtl8169_fix_features,
6784 .ndo_set_features = rtl8169_set_features,
6785 .ndo_set_mac_address = rtl_set_mac_address,
6786 .ndo_do_ioctl = rtl8169_ioctl,
6787 .ndo_set_rx_mode = rtl_set_rx_mode,
6788 #ifdef CONFIG_NET_POLL_CONTROLLER
6789 .ndo_poll_controller = rtl8169_netpoll,
6790 #endif
6791
6792 };
6793
6794 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6795 {
6796 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6797
6798 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6799 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6800 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6801
6802 tp->irq_mask |= RxFIFOOver;
6803 else
6804 tp->irq_mask |= RxOverflow;
6805 }
6806
6807 static int rtl_alloc_irq(struct rtl8169_private *tp)
6808 {
6809 unsigned int flags;
6810
6811 switch (tp->mac_version) {
6812 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6813 rtl_unlock_config_regs(tp);
6814 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6815 rtl_lock_config_regs(tp);
6816
6817 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
6818 flags = PCI_IRQ_LEGACY;
6819 break;
6820 default:
6821 flags = PCI_IRQ_ALL_TYPES;
6822 break;
6823 }
6824
6825 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6826 }
6827
6828 static void rtl_read_mac_address(struct rtl8169_private *tp,
6829 u8 mac_addr[ETH_ALEN])
6830 {
6831
6832 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6833 u32 value = rtl_eri_read(tp, 0xe0);
6834
6835 mac_addr[0] = (value >> 0) & 0xff;
6836 mac_addr[1] = (value >> 8) & 0xff;
6837 mac_addr[2] = (value >> 16) & 0xff;
6838 mac_addr[3] = (value >> 24) & 0xff;
6839
6840 value = rtl_eri_read(tp, 0xe4);
6841 mac_addr[4] = (value >> 0) & 0xff;
6842 mac_addr[5] = (value >> 8) & 0xff;
6843 } else if (rtl_is_8125(tp)) {
6844 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
6845 }
6846 }
6847
6848 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6849 {
6850 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6851 }
6852
6853 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6854 {
6855 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6856 }
6857
6858 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6859 {
6860 struct rtl8169_private *tp = mii_bus->priv;
6861
6862 if (phyaddr > 0)
6863 return -ENODEV;
6864
6865 return rtl_readphy(tp, phyreg);
6866 }
6867
6868 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6869 int phyreg, u16 val)
6870 {
6871 struct rtl8169_private *tp = mii_bus->priv;
6872
6873 if (phyaddr > 0)
6874 return -ENODEV;
6875
6876 rtl_writephy(tp, phyreg, val);
6877
6878 return 0;
6879 }
6880
6881 static int r8169_mdio_register(struct rtl8169_private *tp)
6882 {
6883 struct pci_dev *pdev = tp->pci_dev;
6884 struct mii_bus *new_bus;
6885 int ret;
6886
6887 new_bus = devm_mdiobus_alloc(&pdev->dev);
6888 if (!new_bus)
6889 return -ENOMEM;
6890
6891 new_bus->name = "r8169";
6892 new_bus->priv = tp;
6893 new_bus->parent = &pdev->dev;
6894 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6895 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6896
6897 new_bus->read = r8169_mdio_read_reg;
6898 new_bus->write = r8169_mdio_write_reg;
6899
6900 ret = mdiobus_register(new_bus);
6901 if (ret)
6902 return ret;
6903
6904 tp->phydev = mdiobus_get_phy(new_bus, 0);
6905 if (!tp->phydev) {
6906 mdiobus_unregister(new_bus);
6907 return -ENODEV;
6908 } else if (!tp->phydev->drv) {
6909
6910
6911
6912 dev_err(&pdev->dev, "realtek.ko not loaded, maybe it needs to be added to initramfs?\n");
6913 mdiobus_unregister(new_bus);
6914 return -EUNATCH;
6915 }
6916
6917
6918 phy_suspend(tp->phydev);
6919
6920 return 0;
6921 }
6922
6923 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6924 {
6925 tp->ocp_base = OCP_STD_PHY_BASE;
6926
6927 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6928
6929 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6930 return;
6931
6932 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6933 return;
6934
6935 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6936 msleep(1);
6937 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6938
6939 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6940
6941 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6942 return;
6943
6944 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
6945
6946 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6947 }
6948
6949 static void rtl_hw_init_8125(struct rtl8169_private *tp)
6950 {
6951 tp->ocp_base = OCP_STD_PHY_BASE;
6952
6953 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6954
6955 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6956 return;
6957
6958 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6959 msleep(1);
6960 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6961
6962 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6963
6964 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6965 return;
6966
6967 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
6968 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
6969 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
6970
6971 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6972 }
6973
6974 static void rtl_hw_initialize(struct rtl8169_private *tp)
6975 {
6976 switch (tp->mac_version) {
6977 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6978 rtl8168ep_stop_cmac(tp);
6979
6980 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6981 rtl_hw_init_8168g(tp);
6982 break;
6983 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
6984 rtl_hw_init_8125(tp);
6985 break;
6986 default:
6987 break;
6988 }
6989 }
6990
6991 static int rtl_jumbo_max(struct rtl8169_private *tp)
6992 {
6993
6994 if (!tp->supports_gmii)
6995 return JUMBO_1K;
6996
6997 switch (tp->mac_version) {
6998
6999 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
7000 return JUMBO_7K;
7001
7002 case RTL_GIGA_MAC_VER_11:
7003 case RTL_GIGA_MAC_VER_12:
7004 case RTL_GIGA_MAC_VER_17:
7005 return JUMBO_4K;
7006
7007 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7008 return JUMBO_6K;
7009 default:
7010 return JUMBO_9K;
7011 }
7012 }
7013
7014 static void rtl_disable_clk(void *data)
7015 {
7016 clk_disable_unprepare(data);
7017 }
7018
7019 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7020 {
7021 struct device *d = tp_to_dev(tp);
7022 struct clk *clk;
7023 int rc;
7024
7025 clk = devm_clk_get(d, "ether_clk");
7026 if (IS_ERR(clk)) {
7027 rc = PTR_ERR(clk);
7028 if (rc == -ENOENT)
7029
7030 rc = 0;
7031 else if (rc != -EPROBE_DEFER)
7032 dev_err(d, "failed to get clk: %d\n", rc);
7033 } else {
7034 tp->clk = clk;
7035 rc = clk_prepare_enable(clk);
7036 if (rc)
7037 dev_err(d, "failed to enable clk: %d\n", rc);
7038 else
7039 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7040 }
7041
7042 return rc;
7043 }
7044
7045 static void rtl_init_mac_address(struct rtl8169_private *tp)
7046 {
7047 struct net_device *dev = tp->dev;
7048 u8 *mac_addr = dev->dev_addr;
7049 int rc;
7050
7051 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
7052 if (!rc)
7053 goto done;
7054
7055 rtl_read_mac_address(tp, mac_addr);
7056 if (is_valid_ether_addr(mac_addr))
7057 goto done;
7058
7059 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
7060 if (is_valid_ether_addr(mac_addr))
7061 goto done;
7062
7063 eth_hw_addr_random(dev);
7064 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
7065 done:
7066 rtl_rar_set(tp, mac_addr);
7067 }
7068
7069 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7070 {
7071 struct rtl8169_private *tp;
7072 struct net_device *dev;
7073 int chipset, region;
7074 int jumbo_max, rc;
7075
7076 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7077 if (!dev)
7078 return -ENOMEM;
7079
7080 SET_NETDEV_DEV(dev, &pdev->dev);
7081 dev->netdev_ops = &rtl_netdev_ops;
7082 tp = netdev_priv(dev);
7083 tp->dev = dev;
7084 tp->pci_dev = pdev;
7085 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7086 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
7087 tp->eee_adv = -1;
7088
7089
7090 rc = rtl_get_ether_clk(tp);
7091 if (rc)
7092 return rc;
7093
7094
7095
7096
7097 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
7098 PCIE_LINK_STATE_L1);
7099 tp->aspm_manageable = !rc;
7100
7101
7102 rc = pcim_enable_device(pdev);
7103 if (rc < 0) {
7104 dev_err(&pdev->dev, "enable failure\n");
7105 return rc;
7106 }
7107
7108 if (pcim_set_mwi(pdev) < 0)
7109 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7110
7111
7112 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7113 if (region < 0) {
7114 dev_err(&pdev->dev, "no MMIO resource found\n");
7115 return -ENODEV;
7116 }
7117
7118
7119 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7120 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7121 return -ENODEV;
7122 }
7123
7124 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7125 if (rc < 0) {
7126 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7127 return rc;
7128 }
7129
7130 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7131
7132
7133 rtl8169_get_mac_version(tp);
7134 if (tp->mac_version == RTL_GIGA_MAC_NONE)
7135 return -ENODEV;
7136
7137 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7138
7139 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7140 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
7141 dev->features |= NETIF_F_HIGHDMA;
7142
7143 rtl_init_rxcfg(tp);
7144
7145 rtl8169_irq_mask_and_ack(tp);
7146
7147 rtl_hw_initialize(tp);
7148
7149 rtl_hw_reset(tp);
7150
7151 pci_set_master(pdev);
7152
7153 chipset = tp->mac_version;
7154
7155 rc = rtl_alloc_irq(tp);
7156 if (rc < 0) {
7157 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7158 return rc;
7159 }
7160
7161 mutex_init(&tp->wk.mutex);
7162 INIT_WORK(&tp->wk.work, rtl_task);
7163 u64_stats_init(&tp->rx_stats.syncp);
7164 u64_stats_init(&tp->tx_stats.syncp);
7165
7166 rtl_init_mac_address(tp);
7167
7168 dev->ethtool_ops = &rtl8169_ethtool_ops;
7169
7170 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7171
7172 dev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
7173 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7174 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
7175 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7176 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7177 NETIF_F_HIGHDMA;
7178 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7179
7180 tp->cp_cmd |= RxChkSum;
7181
7182 if (!rtl_is_8125(tp))
7183 tp->cp_cmd |= RxVlan;
7184
7185
7186
7187
7188 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7189
7190 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7191
7192 if (rtl_chip_supports_csum_v2(tp)) {
7193 dev->hw_features |= NETIF_F_IPV6_CSUM;
7194 dev->features |= NETIF_F_IPV6_CSUM;
7195 }
7196
7197
7198
7199
7200
7201
7202 if (rtl_chip_supports_csum_v2(tp)) {
7203 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
7204 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
7205 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
7206 } else {
7207 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
7208 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
7209 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
7210 }
7211
7212 dev->hw_features |= NETIF_F_RXALL;
7213 dev->hw_features |= NETIF_F_RXFCS;
7214
7215
7216 dev->min_mtu = ETH_ZLEN;
7217 jumbo_max = rtl_jumbo_max(tp);
7218 dev->max_mtu = jumbo_max;
7219
7220 rtl_set_irq_mask(tp);
7221
7222 tp->fw_name = rtl_chip_infos[chipset].fw_name;
7223
7224 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7225 &tp->counters_phys_addr,
7226 GFP_KERNEL);
7227 if (!tp->counters)
7228 return -ENOMEM;
7229
7230 pci_set_drvdata(pdev, dev);
7231
7232 rc = r8169_mdio_register(tp);
7233 if (rc)
7234 return rc;
7235
7236
7237 rtl_pll_power_down(tp);
7238
7239 rc = register_netdev(dev);
7240 if (rc)
7241 goto err_mdio_unregister;
7242
7243 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7244 rtl_chip_infos[chipset].name, dev->dev_addr,
7245 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7246 pci_irq_vector(pdev, 0));
7247
7248 if (jumbo_max > JUMBO_1K)
7249 netif_info(tp, probe, dev,
7250 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7251 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7252 "ok" : "ko");
7253
7254 if (r8168_check_dash(tp))
7255 rtl8168_driver_start(tp);
7256
7257 if (pci_dev_run_wake(pdev))
7258 pm_runtime_put_sync(&pdev->dev);
7259
7260 return 0;
7261
7262 err_mdio_unregister:
7263 mdiobus_unregister(tp->phydev->mdio.bus);
7264 return rc;
7265 }
7266
7267 static struct pci_driver rtl8169_pci_driver = {
7268 .name = MODULENAME,
7269 .id_table = rtl8169_pci_tbl,
7270 .probe = rtl_init_one,
7271 .remove = rtl_remove_one,
7272 .shutdown = rtl_shutdown,
7273 .driver.pm = RTL8169_PM_OPS,
7274 };
7275
7276 module_pci_driver(rtl8169_pci_driver);