drivers/net/ethernet/apple/mace.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
mace_probe
mace_remove
dbdma_reset
mace_reset
__mace_set_address
mace_set_address
mace_clean_rings
mace_open
mace_close
mace_set_timeout
mace_xmit_start
mace_set_multicast
mace_handle_misc_intrs
mace_interrupt
mace_tx_timeout
mace_txdma_intr
mace_rxdma_intr
mace_init
mace_cleanup
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Network device driver for the MACE ethernet controller on
   4  * Apple Powermacs.  Assumes it's under a DBDMA controller.
   5  *
   6  * Copyright (C) 1996 Paul Mackerras.
   7  */
   8 
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/delay.h>
  14 #include <linux/string.h>
  15 #include <linux/timer.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/crc32.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/bitrev.h>
  21 #include <linux/slab.h>
  22 #include <asm/prom.h>
  23 #include <asm/dbdma.h>
  24 #include <asm/io.h>
  25 #include <asm/pgtable.h>
  26 #include <asm/macio.h>
  27 
  28 #include "mace.h"
  29 
  30 static int port_aaui = -1;
  31 
  32 #define N_RX_RING       8
  33 #define N_TX_RING       6
  34 #define MAX_TX_ACTIVE   1
  35 #define NCMDS_TX        1       /* dma commands per element in tx ring */
  36 #define RX_BUFLEN       (ETH_FRAME_LEN + 8)
  37 #define TX_TIMEOUT      HZ      /* 1 second */
  38 
  39 /* Chip rev needs workaround on HW & multicast addr change */
  40 #define BROKEN_ADDRCHG_REV      0x0941
  41 
  42 /* Bits in transmit DMA status */
  43 #define TX_DMA_ERR      0x80
  44 
  45 struct mace_data {
  46     volatile struct mace __iomem *mace;
  47     volatile struct dbdma_regs __iomem *tx_dma;
  48     int tx_dma_intr;
  49     volatile struct dbdma_regs __iomem *rx_dma;
  50     int rx_dma_intr;
  51     volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
  52     volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
  53     struct sk_buff *rx_bufs[N_RX_RING];
  54     int rx_fill;
  55     int rx_empty;
  56     struct sk_buff *tx_bufs[N_TX_RING];
  57     int tx_fill;
  58     int tx_empty;
  59     unsigned char maccc;
  60     unsigned char tx_fullup;
  61     unsigned char tx_active;
  62     unsigned char tx_bad_runt;
  63     struct timer_list tx_timeout;
  64     int timeout_active;
  65     int port_aaui;
  66     int chipid;
  67     struct macio_dev *mdev;
  68     spinlock_t lock;
  69 };
  70 
  71 /*
  72  * Number of bytes of private data per MACE: allow enough for
  73  * the rx and tx dma commands plus a branch dma command each,
  74  * and another 16 bytes to allow us to align the dma command
  75  * buffers on a 16 byte boundary.
  76  */
  77 #define PRIV_BYTES      (sizeof(struct mace_data) \
  78         + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
  79 
  80 static int mace_open(struct net_device *dev);
  81 static int mace_close(struct net_device *dev);
  82 static netdev_tx_t mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
  83 static void mace_set_multicast(struct net_device *dev);
  84 static void mace_reset(struct net_device *dev);
  85 static int mace_set_address(struct net_device *dev, void *addr);
  86 static irqreturn_t mace_interrupt(int irq, void *dev_id);
  87 static irqreturn_t mace_txdma_intr(int irq, void *dev_id);
  88 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id);
  89 static void mace_set_timeout(struct net_device *dev);
  90 static void mace_tx_timeout(struct timer_list *t);
  91 static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma);
  92 static inline void mace_clean_rings(struct mace_data *mp);
  93 static void __mace_set_address(struct net_device *dev, void *addr);
  94 
  95 /*
  96  * If we can't get a skbuff when we need it, we use this area for DMA.
  97  */
  98 static unsigned char *dummy_buf;
  99 
 100 static const struct net_device_ops mace_netdev_ops = {
 101         .ndo_open               = mace_open,
 102         .ndo_stop               = mace_close,
 103         .ndo_start_xmit         = mace_xmit_start,
 104         .ndo_set_rx_mode        = mace_set_multicast,
 105         .ndo_set_mac_address    = mace_set_address,
 106         .ndo_validate_addr      = eth_validate_addr,
 107 };
 108 
 109 static int mace_probe(struct macio_dev *mdev, const struct of_device_id *match)
 110 {
 111         struct device_node *mace = macio_get_of_node(mdev);
 112         struct net_device *dev;
 113         struct mace_data *mp;
 114         const unsigned char *addr;
 115         int j, rev, rc = -EBUSY;
 116 
 117         if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
 118                 printk(KERN_ERR "can't use MACE %pOF: need 3 addrs and 3 irqs\n",
 119                        mace);
 120                 return -ENODEV;
 121         }
 122 
 123         addr = of_get_property(mace, "mac-address", NULL);
 124         if (addr == NULL) {
 125                 addr = of_get_property(mace, "local-mac-address", NULL);
 126                 if (addr == NULL) {
 127                         printk(KERN_ERR "Can't get mac-address for MACE %pOF\n",
 128                                mace);
 129                         return -ENODEV;
 130                 }
 131         }
 132 
 133         /*
 134          * lazy allocate the driver-wide dummy buffer. (Note that we
 135          * never have more than one MACE in the system anyway)
 136          */
 137         if (dummy_buf == NULL) {
 138                 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
 139                 if (dummy_buf == NULL)
 140                         return -ENOMEM;
 141         }
 142 
 143         if (macio_request_resources(mdev, "mace")) {
 144                 printk(KERN_ERR "MACE: can't request IO resources !\n");
 145                 return -EBUSY;
 146         }
 147 
 148         dev = alloc_etherdev(PRIV_BYTES);
 149         if (!dev) {
 150                 rc = -ENOMEM;
 151                 goto err_release;
 152         }
 153         SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
 154 
 155         mp = netdev_priv(dev);
 156         mp->mdev = mdev;
 157         macio_set_drvdata(mdev, dev);
 158 
 159         dev->base_addr = macio_resource_start(mdev, 0);
 160         mp->mace = ioremap(dev->base_addr, 0x1000);
 161         if (mp->mace == NULL) {
 162                 printk(KERN_ERR "MACE: can't map IO resources !\n");
 163                 rc = -ENOMEM;
 164                 goto err_free;
 165         }
 166         dev->irq = macio_irq(mdev, 0);
 167 
 168         rev = addr[0] == 0 && addr[1] == 0xA0;
 169         for (j = 0; j < 6; ++j) {
 170                 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j];
 171         }
 172         mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
 173                         in_8(&mp->mace->chipid_lo);
 174 
 175 
 176         mp = netdev_priv(dev);
 177         mp->maccc = ENXMT | ENRCV;
 178 
 179         mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
 180         if (mp->tx_dma == NULL) {
 181                 printk(KERN_ERR "MACE: can't map TX DMA resources !\n");
 182                 rc = -ENOMEM;
 183                 goto err_unmap_io;
 184         }
 185         mp->tx_dma_intr = macio_irq(mdev, 1);
 186 
 187         mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000);
 188         if (mp->rx_dma == NULL) {
 189                 printk(KERN_ERR "MACE: can't map RX DMA resources !\n");
 190                 rc = -ENOMEM;
 191                 goto err_unmap_tx_dma;
 192         }
 193         mp->rx_dma_intr = macio_irq(mdev, 2);
 194 
 195         mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
 196         mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
 197 
 198         memset((char *) mp->tx_cmds, 0,
 199                (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
 200         timer_setup(&mp->tx_timeout, mace_tx_timeout, 0);
 201         spin_lock_init(&mp->lock);
 202         mp->timeout_active = 0;
 203 
 204         if (port_aaui >= 0)
 205                 mp->port_aaui = port_aaui;
 206         else {
 207                 /* Apple Network Server uses the AAUI port */
 208                 if (of_machine_is_compatible("AAPL,ShinerESB"))
 209                         mp->port_aaui = 1;
 210                 else {
 211 #ifdef CONFIG_MACE_AAUI_PORT
 212                         mp->port_aaui = 1;
 213 #else
 214                         mp->port_aaui = 0;
 215 #endif
 216                 }
 217         }
 218 
 219         dev->netdev_ops = &mace_netdev_ops;
 220 
 221         /*
 222          * Most of what is below could be moved to mace_open()
 223          */
 224         mace_reset(dev);
 225 
 226         rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev);
 227         if (rc) {
 228                 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
 229                 goto err_unmap_rx_dma;
 230         }
 231         rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev);
 232         if (rc) {
 233                 printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr);
 234                 goto err_free_irq;
 235         }
 236         rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev);
 237         if (rc) {
 238                 printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr);
 239                 goto err_free_tx_irq;
 240         }
 241 
 242         rc = register_netdev(dev);
 243         if (rc) {
 244                 printk(KERN_ERR "MACE: Cannot register net device, aborting.\n");
 245                 goto err_free_rx_irq;
 246         }
 247 
 248         printk(KERN_INFO "%s: MACE at %pM, chip revision %d.%d\n",
 249                dev->name, dev->dev_addr,
 250                mp->chipid >> 8, mp->chipid & 0xff);
 251 
 252         return 0;
 253 
 254  err_free_rx_irq:
 255         free_irq(macio_irq(mdev, 2), dev);
 256  err_free_tx_irq:
 257         free_irq(macio_irq(mdev, 1), dev);
 258  err_free_irq:
 259         free_irq(macio_irq(mdev, 0), dev);
 260  err_unmap_rx_dma:
 261         iounmap(mp->rx_dma);
 262  err_unmap_tx_dma:
 263         iounmap(mp->tx_dma);
 264  err_unmap_io:
 265         iounmap(mp->mace);
 266  err_free:
 267         free_netdev(dev);
 268  err_release:
 269         macio_release_resources(mdev);
 270 
 271         return rc;
 272 }
 273 
 274 static int mace_remove(struct macio_dev *mdev)
 275 {
 276         struct net_device *dev = macio_get_drvdata(mdev);
 277         struct mace_data *mp;
 278 
 279         BUG_ON(dev == NULL);
 280 
 281         macio_set_drvdata(mdev, NULL);
 282 
 283         mp = netdev_priv(dev);
 284 
 285         unregister_netdev(dev);
 286 
 287         free_irq(dev->irq, dev);
 288         free_irq(mp->tx_dma_intr, dev);
 289         free_irq(mp->rx_dma_intr, dev);
 290 
 291         iounmap(mp->rx_dma);
 292         iounmap(mp->tx_dma);
 293         iounmap(mp->mace);
 294 
 295         free_netdev(dev);
 296 
 297         macio_release_resources(mdev);
 298 
 299         return 0;
 300 }
 301 
 302 static void dbdma_reset(volatile struct dbdma_regs __iomem *dma)
 303 {
 304     int i;
 305 
 306     out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
 307 
 308     /*
 309      * Yes this looks peculiar, but apparently it needs to be this
 310      * way on some machines.
 311      */
 312     for (i = 200; i > 0; --i)
 313         if (le32_to_cpu(dma->control) & RUN)
 314             udelay(1);
 315 }
 316 
 317 static void mace_reset(struct net_device *dev)
 318 {
 319     struct mace_data *mp = netdev_priv(dev);
 320     volatile struct mace __iomem *mb = mp->mace;
 321     int i;
 322 
 323     /* soft-reset the chip */
 324     i = 200;
 325     while (--i) {
 326         out_8(&mb->biucc, SWRST);
 327         if (in_8(&mb->biucc) & SWRST) {
 328             udelay(10);
 329             continue;
 330         }
 331         break;
 332     }
 333     if (!i) {
 334         printk(KERN_ERR "mace: cannot reset chip!\n");
 335         return;
 336     }
 337 
 338     out_8(&mb->imr, 0xff);      /* disable all intrs for now */
 339     i = in_8(&mb->ir);
 340     out_8(&mb->maccc, 0);       /* turn off tx, rx */
 341 
 342     out_8(&mb->biucc, XMTSP_64);
 343     out_8(&mb->utr, RTRD);
 344     out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
 345     out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
 346     out_8(&mb->rcvfc, 0);
 347 
 348     /* load up the hardware address */
 349     __mace_set_address(dev, dev->dev_addr);
 350 
 351     /* clear the multicast filter */
 352     if (mp->chipid == BROKEN_ADDRCHG_REV)
 353         out_8(&mb->iac, LOGADDR);
 354     else {
 355         out_8(&mb->iac, ADDRCHG | LOGADDR);
 356         while ((in_8(&mb->iac) & ADDRCHG) != 0)
 357                 ;
 358     }
 359     for (i = 0; i < 8; ++i)
 360         out_8(&mb->ladrf, 0);
 361 
 362     /* done changing address */
 363     if (mp->chipid != BROKEN_ADDRCHG_REV)
 364         out_8(&mb->iac, 0);
 365 
 366     if (mp->port_aaui)
 367         out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
 368     else
 369         out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
 370 }
 371 
 372 static void __mace_set_address(struct net_device *dev, void *addr)
 373 {
 374     struct mace_data *mp = netdev_priv(dev);
 375     volatile struct mace __iomem *mb = mp->mace;
 376     unsigned char *p = addr;
 377     int i;
 378 
 379     /* load up the hardware address */
 380     if (mp->chipid == BROKEN_ADDRCHG_REV)
 381         out_8(&mb->iac, PHYADDR);
 382     else {
 383         out_8(&mb->iac, ADDRCHG | PHYADDR);
 384         while ((in_8(&mb->iac) & ADDRCHG) != 0)
 385             ;
 386     }
 387     for (i = 0; i < 6; ++i)
 388         out_8(&mb->padr, dev->dev_addr[i] = p[i]);
 389     if (mp->chipid != BROKEN_ADDRCHG_REV)
 390         out_8(&mb->iac, 0);
 391 }
 392 
 393 static int mace_set_address(struct net_device *dev, void *addr)
 394 {
 395     struct mace_data *mp = netdev_priv(dev);
 396     volatile struct mace __iomem *mb = mp->mace;
 397     unsigned long flags;
 398 
 399     spin_lock_irqsave(&mp->lock, flags);
 400 
 401     __mace_set_address(dev, addr);
 402 
 403     /* note: setting ADDRCHG clears ENRCV */
 404     out_8(&mb->maccc, mp->maccc);
 405 
 406     spin_unlock_irqrestore(&mp->lock, flags);
 407     return 0;
 408 }
 409 
 410 static inline void mace_clean_rings(struct mace_data *mp)
 411 {
 412     int i;
 413 
 414     /* free some skb's */
 415     for (i = 0; i < N_RX_RING; ++i) {
 416         if (mp->rx_bufs[i] != NULL) {
 417             dev_kfree_skb(mp->rx_bufs[i]);
 418             mp->rx_bufs[i] = NULL;
 419         }
 420     }
 421     for (i = mp->tx_empty; i != mp->tx_fill; ) {
 422         dev_kfree_skb(mp->tx_bufs[i]);
 423         if (++i >= N_TX_RING)
 424             i = 0;
 425     }
 426 }
 427 
 428 static int mace_open(struct net_device *dev)
 429 {
 430     struct mace_data *mp = netdev_priv(dev);
 431     volatile struct mace __iomem *mb = mp->mace;
 432     volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
 433     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
 434     volatile struct dbdma_cmd *cp;
 435     int i;
 436     struct sk_buff *skb;
 437     unsigned char *data;
 438 
 439     /* reset the chip */
 440     mace_reset(dev);
 441 
 442     /* initialize list of sk_buffs for receiving and set up recv dma */
 443     mace_clean_rings(mp);
 444     memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
 445     cp = mp->rx_cmds;
 446     for (i = 0; i < N_RX_RING - 1; ++i) {
 447         skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
 448         if (!skb) {
 449             data = dummy_buf;
 450         } else {
 451             skb_reserve(skb, 2);        /* so IP header lands on 4-byte bdry */
 452             data = skb->data;
 453         }
 454         mp->rx_bufs[i] = skb;
 455         cp->req_count = cpu_to_le16(RX_BUFLEN);
 456         cp->command = cpu_to_le16(INPUT_LAST + INTR_ALWAYS);
 457         cp->phy_addr = cpu_to_le32(virt_to_bus(data));
 458         cp->xfer_status = 0;
 459         ++cp;
 460     }
 461     mp->rx_bufs[i] = NULL;
 462     cp->command = cpu_to_le16(DBDMA_STOP);
 463     mp->rx_fill = i;
 464     mp->rx_empty = 0;
 465 
 466     /* Put a branch back to the beginning of the receive command list */
 467     ++cp;
 468     cp->command = cpu_to_le16(DBDMA_NOP + BR_ALWAYS);
 469     cp->cmd_dep = cpu_to_le32(virt_to_bus(mp->rx_cmds));
 470 
 471     /* start rx dma */
 472     out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
 473     out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
 474     out_le32(&rd->control, (RUN << 16) | RUN);
 475 
 476     /* put a branch at the end of the tx command list */
 477     cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
 478     cp->command = cpu_to_le16(DBDMA_NOP + BR_ALWAYS);
 479     cp->cmd_dep = cpu_to_le32(virt_to_bus(mp->tx_cmds));
 480 
 481     /* reset tx dma */
 482     out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
 483     out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
 484     mp->tx_fill = 0;
 485     mp->tx_empty = 0;
 486     mp->tx_fullup = 0;
 487     mp->tx_active = 0;
 488     mp->tx_bad_runt = 0;
 489 
 490     /* turn it on! */
 491     out_8(&mb->maccc, mp->maccc);
 492     /* enable all interrupts except receive interrupts */
 493     out_8(&mb->imr, RCVINT);
 494 
 495     return 0;
 496 }
 497 
 498 static int mace_close(struct net_device *dev)
 499 {
 500     struct mace_data *mp = netdev_priv(dev);
 501     volatile struct mace __iomem *mb = mp->mace;
 502     volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
 503     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
 504 
 505     /* disable rx and tx */
 506     out_8(&mb->maccc, 0);
 507     out_8(&mb->imr, 0xff);              /* disable all intrs */
 508 
 509     /* disable rx and tx dma */
 510     rd->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
 511     td->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
 512 
 513     mace_clean_rings(mp);
 514 
 515     return 0;
 516 }
 517 
 518 static inline void mace_set_timeout(struct net_device *dev)
 519 {
 520     struct mace_data *mp = netdev_priv(dev);
 521 
 522     if (mp->timeout_active)
 523         del_timer(&mp->tx_timeout);
 524     mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
 525     add_timer(&mp->tx_timeout);
 526     mp->timeout_active = 1;
 527 }
 528 
 529 static netdev_tx_t mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
 530 {
 531     struct mace_data *mp = netdev_priv(dev);
 532     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
 533     volatile struct dbdma_cmd *cp, *np;
 534     unsigned long flags;
 535     int fill, next, len;
 536 
 537     /* see if there's a free slot in the tx ring */
 538     spin_lock_irqsave(&mp->lock, flags);
 539     fill = mp->tx_fill;
 540     next = fill + 1;
 541     if (next >= N_TX_RING)
 542         next = 0;
 543     if (next == mp->tx_empty) {
 544         netif_stop_queue(dev);
 545         mp->tx_fullup = 1;
 546         spin_unlock_irqrestore(&mp->lock, flags);
 547         return NETDEV_TX_BUSY;          /* can't take it at the moment */
 548     }
 549     spin_unlock_irqrestore(&mp->lock, flags);
 550 
 551     /* partially fill in the dma command block */
 552     len = skb->len;
 553     if (len > ETH_FRAME_LEN) {
 554         printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
 555         len = ETH_FRAME_LEN;
 556     }
 557     mp->tx_bufs[fill] = skb;
 558     cp = mp->tx_cmds + NCMDS_TX * fill;
 559     cp->req_count = cpu_to_le16(len);
 560     cp->phy_addr = cpu_to_le32(virt_to_bus(skb->data));
 561 
 562     np = mp->tx_cmds + NCMDS_TX * next;
 563     out_le16(&np->command, DBDMA_STOP);
 564 
 565     /* poke the tx dma channel */
 566     spin_lock_irqsave(&mp->lock, flags);
 567     mp->tx_fill = next;
 568     if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
 569         out_le16(&cp->xfer_status, 0);
 570         out_le16(&cp->command, OUTPUT_LAST);
 571         out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
 572         ++mp->tx_active;
 573         mace_set_timeout(dev);
 574     }
 575     if (++next >= N_TX_RING)
 576         next = 0;
 577     if (next == mp->tx_empty)
 578         netif_stop_queue(dev);
 579     spin_unlock_irqrestore(&mp->lock, flags);
 580 
 581     return NETDEV_TX_OK;
 582 }
 583 
 584 static void mace_set_multicast(struct net_device *dev)
 585 {
 586     struct mace_data *mp = netdev_priv(dev);
 587     volatile struct mace __iomem *mb = mp->mace;
 588     int i;
 589     u32 crc;
 590     unsigned long flags;
 591 
 592     spin_lock_irqsave(&mp->lock, flags);
 593     mp->maccc &= ~PROM;
 594     if (dev->flags & IFF_PROMISC) {
 595         mp->maccc |= PROM;
 596     } else {
 597         unsigned char multicast_filter[8];
 598         struct netdev_hw_addr *ha;
 599 
 600         if (dev->flags & IFF_ALLMULTI) {
 601             for (i = 0; i < 8; i++)
 602                 multicast_filter[i] = 0xff;
 603         } else {
 604             for (i = 0; i < 8; i++)
 605                 multicast_filter[i] = 0;
 606             netdev_for_each_mc_addr(ha, dev) {
 607                 crc = ether_crc_le(6, ha->addr);
 608                 i = crc >> 26;  /* bit number in multicast_filter */
 609                 multicast_filter[i >> 3] |= 1 << (i & 7);
 610             }
 611         }
 612 #if 0
 613         printk("Multicast filter :");
 614         for (i = 0; i < 8; i++)
 615             printk("%02x ", multicast_filter[i]);
 616         printk("\n");
 617 #endif
 618 
 619         if (mp->chipid == BROKEN_ADDRCHG_REV)
 620             out_8(&mb->iac, LOGADDR);
 621         else {
 622             out_8(&mb->iac, ADDRCHG | LOGADDR);
 623             while ((in_8(&mb->iac) & ADDRCHG) != 0)
 624                 ;
 625         }
 626         for (i = 0; i < 8; ++i)
 627             out_8(&mb->ladrf, multicast_filter[i]);
 628         if (mp->chipid != BROKEN_ADDRCHG_REV)
 629             out_8(&mb->iac, 0);
 630     }
 631     /* reset maccc */
 632     out_8(&mb->maccc, mp->maccc);
 633     spin_unlock_irqrestore(&mp->lock, flags);
 634 }
 635 
 636 static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev)
 637 {
 638     volatile struct mace __iomem *mb = mp->mace;
 639     static int mace_babbles, mace_jabbers;
 640 
 641     if (intr & MPCO)
 642         dev->stats.rx_missed_errors += 256;
 643     dev->stats.rx_missed_errors += in_8(&mb->mpc);   /* reading clears it */
 644     if (intr & RNTPCO)
 645         dev->stats.rx_length_errors += 256;
 646     dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
 647     if (intr & CERR)
 648         ++dev->stats.tx_heartbeat_errors;
 649     if (intr & BABBLE)
 650         if (mace_babbles++ < 4)
 651             printk(KERN_DEBUG "mace: babbling transmitter\n");
 652     if (intr & JABBER)
 653         if (mace_jabbers++ < 4)
 654             printk(KERN_DEBUG "mace: jabbering transceiver\n");
 655 }
 656 
 657 static irqreturn_t mace_interrupt(int irq, void *dev_id)
 658 {
 659     struct net_device *dev = (struct net_device *) dev_id;
 660     struct mace_data *mp = netdev_priv(dev);
 661     volatile struct mace __iomem *mb = mp->mace;
 662     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
 663     volatile struct dbdma_cmd *cp;
 664     int intr, fs, i, stat, x;
 665     int xcount, dstat;
 666     unsigned long flags;
 667     /* static int mace_last_fs, mace_last_xcount; */
 668 
 669     spin_lock_irqsave(&mp->lock, flags);
 670     intr = in_8(&mb->ir);               /* read interrupt register */
 671     in_8(&mb->xmtrc);                   /* get retries */
 672     mace_handle_misc_intrs(mp, intr, dev);
 673 
 674     i = mp->tx_empty;
 675     while (in_8(&mb->pr) & XMTSV) {
 676         del_timer(&mp->tx_timeout);
 677         mp->timeout_active = 0;
 678         /*
 679          * Clear any interrupt indication associated with this status
 680          * word.  This appears to unlatch any error indication from
 681          * the DMA controller.
 682          */
 683         intr = in_8(&mb->ir);
 684         if (intr != 0)
 685             mace_handle_misc_intrs(mp, intr, dev);
 686         if (mp->tx_bad_runt) {
 687             fs = in_8(&mb->xmtfs);
 688             mp->tx_bad_runt = 0;
 689             out_8(&mb->xmtfc, AUTO_PAD_XMIT);
 690             continue;
 691         }
 692         dstat = le32_to_cpu(td->status);
 693         /* stop DMA controller */
 694         out_le32(&td->control, RUN << 16);
 695         /*
 696          * xcount is the number of complete frames which have been
 697          * written to the fifo but for which status has not been read.
 698          */
 699         xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
 700         if (xcount == 0 || (dstat & DEAD)) {
 701             /*
 702              * If a packet was aborted before the DMA controller has
 703              * finished transferring it, it seems that there are 2 bytes
 704              * which are stuck in some buffer somewhere.  These will get
 705              * transmitted as soon as we read the frame status (which
 706              * reenables the transmit data transfer request).  Turning
 707              * off the DMA controller and/or resetting the MACE doesn't
 708              * help.  So we disable auto-padding and FCS transmission
 709              * so the two bytes will only be a runt packet which should
 710              * be ignored by other stations.
 711              */
 712             out_8(&mb->xmtfc, DXMTFCS);
 713         }
 714         fs = in_8(&mb->xmtfs);
 715         if ((fs & XMTSV) == 0) {
 716             printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
 717                    fs, xcount, dstat);
 718             mace_reset(dev);
 719                 /*
 720                  * XXX mace likes to hang the machine after a xmtfs error.
 721                  * This is hard to reproduce, resetting *may* help
 722                  */
 723         }
 724         cp = mp->tx_cmds + NCMDS_TX * i;
 725         stat = le16_to_cpu(cp->xfer_status);
 726         if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
 727             /*
 728              * Check whether there were in fact 2 bytes written to
 729              * the transmit FIFO.
 730              */
 731             udelay(1);
 732             x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
 733             if (x != 0) {
 734                 /* there were two bytes with an end-of-packet indication */
 735                 mp->tx_bad_runt = 1;
 736                 mace_set_timeout(dev);
 737             } else {
 738                 /*
 739                  * Either there weren't the two bytes buffered up, or they
 740                  * didn't have an end-of-packet indication.
 741                  * We flush the transmit FIFO just in case (by setting the
 742                  * XMTFWU bit with the transmitter disabled).
 743                  */
 744                 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
 745                 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
 746                 udelay(1);
 747                 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
 748                 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
 749             }
 750         }
 751         /* dma should have finished */
 752         if (i == mp->tx_fill) {
 753             printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
 754                    fs, xcount, dstat);
 755             continue;
 756         }
 757         /* Update stats */
 758         if (fs & (UFLO|LCOL|LCAR|RTRY)) {
 759             ++dev->stats.tx_errors;
 760             if (fs & LCAR)
 761                 ++dev->stats.tx_carrier_errors;
 762             if (fs & (UFLO|LCOL|RTRY))
 763                 ++dev->stats.tx_aborted_errors;
 764         } else {
 765             dev->stats.tx_bytes += mp->tx_bufs[i]->len;
 766             ++dev->stats.tx_packets;
 767         }
 768         dev_consume_skb_irq(mp->tx_bufs[i]);
 769         --mp->tx_active;
 770         if (++i >= N_TX_RING)
 771             i = 0;
 772 #if 0
 773         mace_last_fs = fs;
 774         mace_last_xcount = xcount;
 775 #endif
 776     }
 777 
 778     if (i != mp->tx_empty) {
 779         mp->tx_fullup = 0;
 780         netif_wake_queue(dev);
 781     }
 782     mp->tx_empty = i;
 783     i += mp->tx_active;
 784     if (i >= N_TX_RING)
 785         i -= N_TX_RING;
 786     if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
 787         do {
 788             /* set up the next one */
 789             cp = mp->tx_cmds + NCMDS_TX * i;
 790             out_le16(&cp->xfer_status, 0);
 791             out_le16(&cp->command, OUTPUT_LAST);
 792             ++mp->tx_active;
 793             if (++i >= N_TX_RING)
 794                 i = 0;
 795         } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
 796         out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
 797         mace_set_timeout(dev);
 798     }
 799     spin_unlock_irqrestore(&mp->lock, flags);
 800     return IRQ_HANDLED;
 801 }
 802 
 803 static void mace_tx_timeout(struct timer_list *t)
 804 {
 805     struct mace_data *mp = from_timer(mp, t, tx_timeout);
 806     struct net_device *dev = macio_get_drvdata(mp->mdev);
 807     volatile struct mace __iomem *mb = mp->mace;
 808     volatile struct dbdma_regs __iomem *td = mp->tx_dma;
 809     volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
 810     volatile struct dbdma_cmd *cp;
 811     unsigned long flags;
 812     int i;
 813 
 814     spin_lock_irqsave(&mp->lock, flags);
 815     mp->timeout_active = 0;
 816     if (mp->tx_active == 0 && !mp->tx_bad_runt)
 817         goto out;
 818 
 819     /* update various counters */
 820     mace_handle_misc_intrs(mp, in_8(&mb->ir), dev);
 821 
 822     cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
 823 
 824     /* turn off both tx and rx and reset the chip */
 825     out_8(&mb->maccc, 0);
 826     printk(KERN_ERR "mace: transmit timeout - resetting\n");
 827     dbdma_reset(td);
 828     mace_reset(dev);
 829 
 830     /* restart rx dma */
 831     cp = bus_to_virt(le32_to_cpu(rd->cmdptr));
 832     dbdma_reset(rd);
 833     out_le16(&cp->xfer_status, 0);
 834     out_le32(&rd->cmdptr, virt_to_bus(cp));
 835     out_le32(&rd->control, (RUN << 16) | RUN);
 836 
 837     /* fix up the transmit side */
 838     i = mp->tx_empty;
 839     mp->tx_active = 0;
 840     ++dev->stats.tx_errors;
 841     if (mp->tx_bad_runt) {
 842         mp->tx_bad_runt = 0;
 843     } else if (i != mp->tx_fill) {
 844         dev_kfree_skb(mp->tx_bufs[i]);
 845         if (++i >= N_TX_RING)
 846             i = 0;
 847         mp->tx_empty = i;
 848     }
 849     mp->tx_fullup = 0;
 850     netif_wake_queue(dev);
 851     if (i != mp->tx_fill) {
 852         cp = mp->tx_cmds + NCMDS_TX * i;
 853         out_le16(&cp->xfer_status, 0);
 854         out_le16(&cp->command, OUTPUT_LAST);
 855         out_le32(&td->cmdptr, virt_to_bus(cp));
 856         out_le32(&td->control, (RUN << 16) | RUN);
 857         ++mp->tx_active;
 858         mace_set_timeout(dev);
 859     }
 860 
 861     /* turn it back on */
 862     out_8(&mb->imr, RCVINT);
 863     out_8(&mb->maccc, mp->maccc);
 864 
 865 out:
 866     spin_unlock_irqrestore(&mp->lock, flags);
 867 }
 868 
 869 static irqreturn_t mace_txdma_intr(int irq, void *dev_id)
 870 {
 871         return IRQ_HANDLED;
 872 }
 873 
 874 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id)
 875 {
 876     struct net_device *dev = (struct net_device *) dev_id;
 877     struct mace_data *mp = netdev_priv(dev);
 878     volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
 879     volatile struct dbdma_cmd *cp, *np;
 880     int i, nb, stat, next;
 881     struct sk_buff *skb;
 882     unsigned frame_status;
 883     static int mace_lost_status;
 884     unsigned char *data;
 885     unsigned long flags;
 886 
 887     spin_lock_irqsave(&mp->lock, flags);
 888     for (i = mp->rx_empty; i != mp->rx_fill; ) {
 889         cp = mp->rx_cmds + i;
 890         stat = le16_to_cpu(cp->xfer_status);
 891         if ((stat & ACTIVE) == 0) {
 892             next = i + 1;
 893             if (next >= N_RX_RING)
 894                 next = 0;
 895             np = mp->rx_cmds + next;
 896             if (next != mp->rx_fill &&
 897                 (le16_to_cpu(np->xfer_status) & ACTIVE) != 0) {
 898                 printk(KERN_DEBUG "mace: lost a status word\n");
 899                 ++mace_lost_status;
 900             } else
 901                 break;
 902         }
 903         nb = le16_to_cpu(cp->req_count) - le16_to_cpu(cp->res_count);
 904         out_le16(&cp->command, DBDMA_STOP);
 905         /* got a packet, have a look at it */
 906         skb = mp->rx_bufs[i];
 907         if (!skb) {
 908             ++dev->stats.rx_dropped;
 909         } else if (nb > 8) {
 910             data = skb->data;
 911             frame_status = (data[nb-3] << 8) + data[nb-4];
 912             if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
 913                 ++dev->stats.rx_errors;
 914                 if (frame_status & RS_OFLO)
 915                     ++dev->stats.rx_over_errors;
 916                 if (frame_status & RS_FRAMERR)
 917                     ++dev->stats.rx_frame_errors;
 918                 if (frame_status & RS_FCSERR)
 919                     ++dev->stats.rx_crc_errors;
 920             } else {
 921                 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
 922                  * FCS on frames with 802.3 headers. This means that Ethernet
 923                  * frames have 8 extra octets at the end, while 802.3 frames
 924                  * have only 4. We need to correctly account for this. */
 925                 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
 926                     nb -= 4;
 927                 else    /* Ethernet header; mace includes FCS */
 928                     nb -= 8;
 929                 skb_put(skb, nb);
 930                 skb->protocol = eth_type_trans(skb, dev);
 931                 dev->stats.rx_bytes += skb->len;
 932                 netif_rx(skb);
 933                 mp->rx_bufs[i] = NULL;
 934                 ++dev->stats.rx_packets;
 935             }
 936         } else {
 937             ++dev->stats.rx_errors;
 938             ++dev->stats.rx_length_errors;
 939         }
 940 
 941         /* advance to next */
 942         if (++i >= N_RX_RING)
 943             i = 0;
 944     }
 945     mp->rx_empty = i;
 946 
 947     i = mp->rx_fill;
 948     for (;;) {
 949         next = i + 1;
 950         if (next >= N_RX_RING)
 951             next = 0;
 952         if (next == mp->rx_empty)
 953             break;
 954         cp = mp->rx_cmds + i;
 955         skb = mp->rx_bufs[i];
 956         if (!skb) {
 957             skb = netdev_alloc_skb(dev, RX_BUFLEN + 2);
 958             if (skb) {
 959                 skb_reserve(skb, 2);
 960                 mp->rx_bufs[i] = skb;
 961             }
 962         }
 963         cp->req_count = cpu_to_le16(RX_BUFLEN);
 964         data = skb? skb->data: dummy_buf;
 965         cp->phy_addr = cpu_to_le32(virt_to_bus(data));
 966         out_le16(&cp->xfer_status, 0);
 967         out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
 968 #if 0
 969         if ((le32_to_cpu(rd->status) & ACTIVE) != 0) {
 970             out_le32(&rd->control, (PAUSE << 16) | PAUSE);
 971             while ((in_le32(&rd->status) & ACTIVE) != 0)
 972                 ;
 973         }
 974 #endif
 975         i = next;
 976     }
 977     if (i != mp->rx_fill) {
 978         out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
 979         mp->rx_fill = i;
 980     }
 981     spin_unlock_irqrestore(&mp->lock, flags);
 982     return IRQ_HANDLED;
 983 }
 984 
 985 static const struct of_device_id mace_match[] =
 986 {
 987         {
 988         .name           = "mace",
 989         },
 990         {},
 991 };
 992 MODULE_DEVICE_TABLE (of, mace_match);
 993 
 994 static struct macio_driver mace_driver =
 995 {
 996         .driver = {
 997                 .name           = "mace",
 998                 .owner          = THIS_MODULE,
 999                 .of_match_table = mace_match,
1000         },
1001         .probe          = mace_probe,
1002         .remove         = mace_remove,
1003 };
1004 
1005 
1006 static int __init mace_init(void)
1007 {
1008         return macio_register_driver(&mace_driver);
1009 }
1010 
1011 static void __exit mace_cleanup(void)
1012 {
1013         macio_unregister_driver(&mace_driver);
1014 
1015         kfree(dummy_buf);
1016         dummy_buf = NULL;
1017 }
1018 
1019 MODULE_AUTHOR("Paul Mackerras");
1020 MODULE_DESCRIPTION("PowerMac MACE driver.");
1021 module_param(port_aaui, int, 0);
1022 MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
1023 MODULE_LICENSE("GPL");
1024 
1025 module_init(mace_init);
1026 module_exit(mace_cleanup);
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root/drivers/net/ethernet/apple/mace.c

DEFINITIONS
