drivers/net/ethernet/dec/tulip/uli526x.c

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This source file includes following definitions.
srom_clk_write
uli526x_init_one
uli526x_remove_one
uli526x_open
uli526x_init
uli526x_start_xmit
uli526x_stop
uli526x_interrupt
uli526x_poll
uli526x_free_tx_pkt
uli526x_rx_packet
uli526x_set_filter_mode
ULi_ethtool_get_link_ksettings
netdev_get_drvinfo
netdev_get_link_ksettings
netdev_get_link
uli526x_get_wol
uli526x_timer
uli526x_reset_prepare
uli526x_dynamic_reset
uli526x_suspend
uli526x_resume
uli526x_free_rxbuffer
uli526x_reuse_skb
uli526x_descriptor_init
update_cr6
send_filter_frame
allocate_rx_buffer
read_srom_word
uli526x_sense_speed
uli526x_set_phyxcer
uli526x_process_mode
phy_writeby_cr9
phy_readby_cr9
phy_readby_cr10
phy_writeby_cr10
phy_write_1bit
phy_read_1bit
uli526x_init_module
uli526x_cleanup_module
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3 
   4 
   5 */
   6 
   7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   8 
   9 #define DRV_NAME        "uli526x"
  10 #define DRV_VERSION     "0.9.3"
  11 #define DRV_RELDATE     "2005-7-29"
  12 
  13 #include <linux/module.h>
  14 
  15 #include <linux/kernel.h>
  16 #include <linux/string.h>
  17 #include <linux/timer.h>
  18 #include <linux/errno.h>
  19 #include <linux/ioport.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/init.h>
  23 #include <linux/netdevice.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/ethtool.h>
  26 #include <linux/skbuff.h>
  27 #include <linux/delay.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/bitops.h>
  31 
  32 #include <asm/processor.h>
  33 #include <asm/io.h>
  34 #include <asm/dma.h>
  35 #include <linux/uaccess.h>
  36 
  37 #define uw32(reg, val)  iowrite32(val, ioaddr + (reg))
  38 #define ur32(reg)       ioread32(ioaddr + (reg))
  39 
  40 /* Board/System/Debug information/definition ---------------- */
  41 #define PCI_ULI5261_ID  0x526110B9      /* ULi M5261 ID*/
  42 #define PCI_ULI5263_ID  0x526310B9      /* ULi M5263 ID*/
  43 
  44 #define ULI526X_IO_SIZE 0x100
  45 #define TX_DESC_CNT     0x20            /* Allocated Tx descriptors */
  46 #define RX_DESC_CNT     0x30            /* Allocated Rx descriptors */
  47 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2)      /* Max TX packet count */
  48 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3)      /* TX wakeup count */
  49 #define DESC_ALL_CNT    (TX_DESC_CNT + RX_DESC_CNT)
  50 #define TX_BUF_ALLOC    0x600
  51 #define RX_ALLOC_SIZE   0x620
  52 #define ULI526X_RESET    1
  53 #define CR0_DEFAULT     0
  54 #define CR6_DEFAULT     0x22200000
  55 #define CR7_DEFAULT     0x180c1
  56 #define CR15_DEFAULT    0x06            /* TxJabber RxWatchdog */
  57 #define TDES0_ERR_MASK  0x4302          /* TXJT, LC, EC, FUE */
  58 #define MAX_PACKET_SIZE 1514
  59 #define ULI5261_MAX_MULTICAST 14
  60 #define RX_COPY_SIZE    100
  61 #define MAX_CHECK_PACKET 0x8000
  62 
  63 #define ULI526X_10MHF      0
  64 #define ULI526X_100MHF     1
  65 #define ULI526X_10MFD      4
  66 #define ULI526X_100MFD     5
  67 #define ULI526X_AUTO       8
  68 
  69 #define ULI526X_TXTH_72 0x400000        /* TX TH 72 byte */
  70 #define ULI526X_TXTH_96 0x404000        /* TX TH 96 byte */
  71 #define ULI526X_TXTH_128        0x0000          /* TX TH 128 byte */
  72 #define ULI526X_TXTH_256        0x4000          /* TX TH 256 byte */
  73 #define ULI526X_TXTH_512        0x8000          /* TX TH 512 byte */
  74 #define ULI526X_TXTH_1K 0xC000          /* TX TH 1K  byte */
  75 
  76 #define ULI526X_TIMER_WUT  (jiffies + HZ * 1)/* timer wakeup time : 1 second */
  77 #define ULI526X_TX_TIMEOUT ((16*HZ)/2)  /* tx packet time-out time 8 s" */
  78 #define ULI526X_TX_KICK         (4*HZ/2)        /* tx packet Kick-out time 2 s" */
  79 
  80 #define ULI526X_DBUG(dbug_now, msg, value)                      \
  81 do {                                                            \
  82         if (uli526x_debug || (dbug_now))                        \
  83                 pr_err("%s %lx\n", (msg), (long) (value));      \
  84 } while (0)
  85 
  86 #define SHOW_MEDIA_TYPE(mode)                                   \
  87         pr_err("Change Speed to %sMhz %s duplex\n",             \
  88                mode & 1 ? "100" : "10",                         \
  89                mode & 4 ? "full" : "half");
  90 
  91 
  92 /* CR9 definition: SROM/MII */
  93 #define CR9_SROM_READ   0x4800
  94 #define CR9_SRCS        0x1
  95 #define CR9_SRCLK       0x2
  96 #define CR9_CRDOUT      0x8
  97 #define SROM_DATA_0     0x0
  98 #define SROM_DATA_1     0x4
  99 #define PHY_DATA_1      0x20000
 100 #define PHY_DATA_0      0x00000
 101 #define MDCLKH          0x10000
 102 
 103 #define PHY_POWER_DOWN  0x800
 104 
 105 #define SROM_V41_CODE   0x14
 106 
 107 /* Structure/enum declaration ------------------------------- */
 108 struct tx_desc {
 109         __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
 110         char *tx_buf_ptr;               /* Data for us */
 111         struct tx_desc *next_tx_desc;
 112 } __attribute__(( aligned(32) ));
 113 
 114 struct rx_desc {
 115         __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
 116         struct sk_buff *rx_skb_ptr;     /* Data for us */
 117         struct rx_desc *next_rx_desc;
 118 } __attribute__(( aligned(32) ));
 119 
 120 struct uli526x_board_info {
 121         struct uli_phy_ops {
 122                 void (*write)(struct uli526x_board_info *, u8, u8, u16);
 123                 u16 (*read)(struct uli526x_board_info *, u8, u8);
 124         } phy;
 125         struct net_device *next_dev;    /* next device */
 126         struct pci_dev *pdev;           /* PCI device */
 127         spinlock_t lock;
 128 
 129         void __iomem *ioaddr;           /* I/O base address */
 130         u32 cr0_data;
 131         u32 cr5_data;
 132         u32 cr6_data;
 133         u32 cr7_data;
 134         u32 cr15_data;
 135 
 136         /* pointer for memory physical address */
 137         dma_addr_t buf_pool_dma_ptr;    /* Tx buffer pool memory */
 138         dma_addr_t buf_pool_dma_start;  /* Tx buffer pool align dword */
 139         dma_addr_t desc_pool_dma_ptr;   /* descriptor pool memory */
 140         dma_addr_t first_tx_desc_dma;
 141         dma_addr_t first_rx_desc_dma;
 142 
 143         /* descriptor pointer */
 144         unsigned char *buf_pool_ptr;    /* Tx buffer pool memory */
 145         unsigned char *buf_pool_start;  /* Tx buffer pool align dword */
 146         unsigned char *desc_pool_ptr;   /* descriptor pool memory */
 147         struct tx_desc *first_tx_desc;
 148         struct tx_desc *tx_insert_ptr;
 149         struct tx_desc *tx_remove_ptr;
 150         struct rx_desc *first_rx_desc;
 151         struct rx_desc *rx_insert_ptr;
 152         struct rx_desc *rx_ready_ptr;   /* packet come pointer */
 153         unsigned long tx_packet_cnt;    /* transmitted packet count */
 154         unsigned long rx_avail_cnt;     /* available rx descriptor count */
 155         unsigned long interval_rx_cnt;  /* rx packet count a callback time */
 156 
 157         u16 dbug_cnt;
 158         u16 NIC_capability;             /* NIC media capability */
 159         u16 PHY_reg4;                   /* Saved Phyxcer register 4 value */
 160 
 161         u8 media_mode;                  /* user specify media mode */
 162         u8 op_mode;                     /* real work media mode */
 163         u8 phy_addr;
 164         u8 link_failed;                 /* Ever link failed */
 165         u8 wait_reset;                  /* Hardware failed, need to reset */
 166         struct timer_list timer;
 167 
 168         /* Driver defined statistic counter */
 169         unsigned long tx_fifo_underrun;
 170         unsigned long tx_loss_carrier;
 171         unsigned long tx_no_carrier;
 172         unsigned long tx_late_collision;
 173         unsigned long tx_excessive_collision;
 174         unsigned long tx_jabber_timeout;
 175         unsigned long reset_count;
 176         unsigned long reset_cr8;
 177         unsigned long reset_fatal;
 178         unsigned long reset_TXtimeout;
 179 
 180         /* NIC SROM data */
 181         unsigned char srom[128];
 182         u8 init;
 183 };
 184 
 185 enum uli526x_offsets {
 186         DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
 187         DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
 188         DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
 189         DCR15 = 0x78
 190 };
 191 
 192 enum uli526x_CR6_bits {
 193         CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
 194         CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
 195         CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
 196 };
 197 
 198 /* Global variable declaration ----------------------------- */
 199 static int printed_version;
 200 static const char version[] =
 201         "ULi M5261/M5263 net driver, version " DRV_VERSION " (" DRV_RELDATE ")";
 202 
 203 static int uli526x_debug;
 204 static unsigned char uli526x_media_mode = ULI526X_AUTO;
 205 static u32 uli526x_cr6_user_set;
 206 
 207 /* For module input parameter */
 208 static int debug;
 209 static u32 cr6set;
 210 static int mode = 8;
 211 
 212 /* function declaration ------------------------------------- */
 213 static int uli526x_open(struct net_device *);
 214 static netdev_tx_t uli526x_start_xmit(struct sk_buff *,
 215                                             struct net_device *);
 216 static int uli526x_stop(struct net_device *);
 217 static void uli526x_set_filter_mode(struct net_device *);
 218 static const struct ethtool_ops netdev_ethtool_ops;
 219 static u16 read_srom_word(struct uli526x_board_info *, int);
 220 static irqreturn_t uli526x_interrupt(int, void *);
 221 #ifdef CONFIG_NET_POLL_CONTROLLER
 222 static void uli526x_poll(struct net_device *dev);
 223 #endif
 224 static void uli526x_descriptor_init(struct net_device *, void __iomem *);
 225 static void allocate_rx_buffer(struct net_device *);
 226 static void update_cr6(u32, void __iomem *);
 227 static void send_filter_frame(struct net_device *, int);
 228 static u16 phy_readby_cr9(struct uli526x_board_info *, u8, u8);
 229 static u16 phy_readby_cr10(struct uli526x_board_info *, u8, u8);
 230 static void phy_writeby_cr9(struct uli526x_board_info *, u8, u8, u16);
 231 static void phy_writeby_cr10(struct uli526x_board_info *, u8, u8, u16);
 232 static void phy_write_1bit(struct uli526x_board_info *db, u32);
 233 static u16 phy_read_1bit(struct uli526x_board_info *db);
 234 static u8 uli526x_sense_speed(struct uli526x_board_info *);
 235 static void uli526x_process_mode(struct uli526x_board_info *);
 236 static void uli526x_timer(struct timer_list *t);
 237 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
 238 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
 239 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
 240 static void uli526x_dynamic_reset(struct net_device *);
 241 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
 242 static void uli526x_init(struct net_device *);
 243 static void uli526x_set_phyxcer(struct uli526x_board_info *);
 244 
 245 static void srom_clk_write(struct uli526x_board_info *db, u32 data)
 246 {
 247         void __iomem *ioaddr = db->ioaddr;
 248 
 249         uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
 250         udelay(5);
 251         uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
 252         udelay(5);
 253         uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
 254         udelay(5);
 255 }
 256 
 257 /* ULI526X network board routine ---------------------------- */
 258 
 259 static const struct net_device_ops netdev_ops = {
 260         .ndo_open               = uli526x_open,
 261         .ndo_stop               = uli526x_stop,
 262         .ndo_start_xmit         = uli526x_start_xmit,
 263         .ndo_set_rx_mode        = uli526x_set_filter_mode,
 264         .ndo_set_mac_address    = eth_mac_addr,
 265         .ndo_validate_addr      = eth_validate_addr,
 266 #ifdef CONFIG_NET_POLL_CONTROLLER
 267         .ndo_poll_controller    = uli526x_poll,
 268 #endif
 269 };
 270 
 271 /*
 272  *      Search ULI526X board, allocate space and register it
 273  */
 274 
 275 static int uli526x_init_one(struct pci_dev *pdev,
 276                             const struct pci_device_id *ent)
 277 {
 278         struct uli526x_board_info *db;  /* board information structure */
 279         struct net_device *dev;
 280         void __iomem *ioaddr;
 281         int i, err;
 282 
 283         ULI526X_DBUG(0, "uli526x_init_one()", 0);
 284 
 285         if (!printed_version++)
 286                 pr_info("%s\n", version);
 287 
 288         /* Init network device */
 289         dev = alloc_etherdev(sizeof(*db));
 290         if (dev == NULL)
 291                 return -ENOMEM;
 292         SET_NETDEV_DEV(dev, &pdev->dev);
 293 
 294         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
 295                 pr_warn("32-bit PCI DMA not available\n");
 296                 err = -ENODEV;
 297                 goto err_out_free;
 298         }
 299 
 300         /* Enable Master/IO access, Disable memory access */
 301         err = pci_enable_device(pdev);
 302         if (err)
 303                 goto err_out_free;
 304 
 305         if (!pci_resource_start(pdev, 0)) {
 306                 pr_err("I/O base is zero\n");
 307                 err = -ENODEV;
 308                 goto err_out_disable;
 309         }
 310 
 311         if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
 312                 pr_err("Allocated I/O size too small\n");
 313                 err = -ENODEV;
 314                 goto err_out_disable;
 315         }
 316 
 317         err = pci_request_regions(pdev, DRV_NAME);
 318         if (err < 0) {
 319                 pr_err("Failed to request PCI regions\n");
 320                 goto err_out_disable;
 321         }
 322 
 323         /* Init system & device */
 324         db = netdev_priv(dev);
 325 
 326         /* Allocate Tx/Rx descriptor memory */
 327         err = -ENOMEM;
 328 
 329         db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
 330         if (!db->desc_pool_ptr)
 331                 goto err_out_release;
 332 
 333         db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
 334         if (!db->buf_pool_ptr)
 335                 goto err_out_free_tx_desc;
 336 
 337         db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
 338         db->first_tx_desc_dma = db->desc_pool_dma_ptr;
 339         db->buf_pool_start = db->buf_pool_ptr;
 340         db->buf_pool_dma_start = db->buf_pool_dma_ptr;
 341 
 342         switch (ent->driver_data) {
 343         case PCI_ULI5263_ID:
 344                 db->phy.write   = phy_writeby_cr10;
 345                 db->phy.read    = phy_readby_cr10;
 346                 break;
 347         default:
 348                 db->phy.write   = phy_writeby_cr9;
 349                 db->phy.read    = phy_readby_cr9;
 350                 break;
 351         }
 352 
 353         /* IO region. */
 354         ioaddr = pci_iomap(pdev, 0, 0);
 355         if (!ioaddr)
 356                 goto err_out_free_tx_buf;
 357 
 358         db->ioaddr = ioaddr;
 359         db->pdev = pdev;
 360         db->init = 1;
 361 
 362         pci_set_drvdata(pdev, dev);
 363 
 364         /* Register some necessary functions */
 365         dev->netdev_ops = &netdev_ops;
 366         dev->ethtool_ops = &netdev_ethtool_ops;
 367 
 368         spin_lock_init(&db->lock);
 369 
 370 
 371         /* read 64 word srom data */
 372         for (i = 0; i < 64; i++)
 373                 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db, i));
 374 
 375         /* Set Node address */
 376         if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0)               /* SROM absent, so read MAC address from ID Table */
 377         {
 378                 uw32(DCR0, 0x10000);    //Diagnosis mode
 379                 uw32(DCR13, 0x1c0);     //Reset dianostic pointer port
 380                 uw32(DCR14, 0);         //Clear reset port
 381                 uw32(DCR14, 0x10);      //Reset ID Table pointer
 382                 uw32(DCR14, 0);         //Clear reset port
 383                 uw32(DCR13, 0);         //Clear CR13
 384                 uw32(DCR13, 0x1b0);     //Select ID Table access port
 385                 //Read MAC address from CR14
 386                 for (i = 0; i < 6; i++)
 387                         dev->dev_addr[i] = ur32(DCR14);
 388                 //Read end
 389                 uw32(DCR13, 0);         //Clear CR13
 390                 uw32(DCR0, 0);          //Clear CR0
 391                 udelay(10);
 392         }
 393         else            /*Exist SROM*/
 394         {
 395                 for (i = 0; i < 6; i++)
 396                         dev->dev_addr[i] = db->srom[20 + i];
 397         }
 398         err = register_netdev (dev);
 399         if (err)
 400                 goto err_out_unmap;
 401 
 402         netdev_info(dev, "ULi M%04lx at pci%s, %pM, irq %d\n",
 403                     ent->driver_data >> 16, pci_name(pdev),
 404                     dev->dev_addr, pdev->irq);
 405 
 406         pci_set_master(pdev);
 407 
 408         return 0;
 409 
 410 err_out_unmap:
 411         pci_iounmap(pdev, db->ioaddr);
 412 err_out_free_tx_buf:
 413         pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
 414                             db->buf_pool_ptr, db->buf_pool_dma_ptr);
 415 err_out_free_tx_desc:
 416         pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
 417                             db->desc_pool_ptr, db->desc_pool_dma_ptr);
 418 err_out_release:
 419         pci_release_regions(pdev);
 420 err_out_disable:
 421         pci_disable_device(pdev);
 422 err_out_free:
 423         free_netdev(dev);
 424 
 425         return err;
 426 }
 427 
 428 
 429 static void uli526x_remove_one(struct pci_dev *pdev)
 430 {
 431         struct net_device *dev = pci_get_drvdata(pdev);
 432         struct uli526x_board_info *db = netdev_priv(dev);
 433 
 434         unregister_netdev(dev);
 435         pci_iounmap(pdev, db->ioaddr);
 436         pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
 437                                 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
 438                                 db->desc_pool_dma_ptr);
 439         pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
 440                                 db->buf_pool_ptr, db->buf_pool_dma_ptr);
 441         pci_release_regions(pdev);
 442         pci_disable_device(pdev);
 443         free_netdev(dev);
 444 }
 445 
 446 
 447 /*
 448  *      Open the interface.
 449  *      The interface is opened whenever "ifconfig" activates it.
 450  */
 451 
 452 static int uli526x_open(struct net_device *dev)
 453 {
 454         int ret;
 455         struct uli526x_board_info *db = netdev_priv(dev);
 456 
 457         ULI526X_DBUG(0, "uli526x_open", 0);
 458 
 459         /* system variable init */
 460         db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
 461         db->tx_packet_cnt = 0;
 462         db->rx_avail_cnt = 0;
 463         db->link_failed = 1;
 464         netif_carrier_off(dev);
 465         db->wait_reset = 0;
 466 
 467         db->NIC_capability = 0xf;       /* All capability*/
 468         db->PHY_reg4 = 0x1e0;
 469 
 470         /* CR6 operation mode decision */
 471         db->cr6_data |= ULI526X_TXTH_256;
 472         db->cr0_data = CR0_DEFAULT;
 473 
 474         /* Initialize ULI526X board */
 475         uli526x_init(dev);
 476 
 477         ret = request_irq(db->pdev->irq, uli526x_interrupt, IRQF_SHARED,
 478                           dev->name, dev);
 479         if (ret)
 480                 return ret;
 481 
 482         /* Active System Interface */
 483         netif_wake_queue(dev);
 484 
 485         /* set and active a timer process */
 486         timer_setup(&db->timer, uli526x_timer, 0);
 487         db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
 488         add_timer(&db->timer);
 489 
 490         return 0;
 491 }
 492 
 493 
 494 /*      Initialize ULI526X board
 495  *      Reset ULI526X board
 496  *      Initialize TX/Rx descriptor chain structure
 497  *      Send the set-up frame
 498  *      Enable Tx/Rx machine
 499  */
 500 
 501 static void uli526x_init(struct net_device *dev)
 502 {
 503         struct uli526x_board_info *db = netdev_priv(dev);
 504         struct uli_phy_ops *phy = &db->phy;
 505         void __iomem *ioaddr = db->ioaddr;
 506         u8      phy_tmp;
 507         u8      timeout;
 508         u16 phy_reg_reset;
 509 
 510 
 511         ULI526X_DBUG(0, "uli526x_init()", 0);
 512 
 513         /* Reset M526x MAC controller */
 514         uw32(DCR0, ULI526X_RESET);      /* RESET MAC */
 515         udelay(100);
 516         uw32(DCR0, db->cr0_data);
 517         udelay(5);
 518 
 519         /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
 520         db->phy_addr = 1;
 521         for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
 522                 u16 phy_value;
 523 
 524                 phy_value = phy->read(db, phy_tmp, 3);  //peer add
 525                 if (phy_value != 0xffff && phy_value != 0) {
 526                         db->phy_addr = phy_tmp;
 527                         break;
 528                 }
 529         }
 530 
 531         if (phy_tmp == 32)
 532                 pr_warn("Can not find the phy address!!!\n");
 533         /* Parser SROM and media mode */
 534         db->media_mode = uli526x_media_mode;
 535 
 536         /* phyxcer capability setting */
 537         phy_reg_reset = phy->read(db, db->phy_addr, 0);
 538         phy_reg_reset = (phy_reg_reset | 0x8000);
 539         phy->write(db, db->phy_addr, 0, phy_reg_reset);
 540 
 541         /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
 542          * functions") or phy data sheet for details on phy reset
 543          */
 544         udelay(500);
 545         timeout = 10;
 546         while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000)
 547                 udelay(100);
 548 
 549         /* Process Phyxcer Media Mode */
 550         uli526x_set_phyxcer(db);
 551 
 552         /* Media Mode Process */
 553         if ( !(db->media_mode & ULI526X_AUTO) )
 554                 db->op_mode = db->media_mode;           /* Force Mode */
 555 
 556         /* Initialize Transmit/Receive descriptor and CR3/4 */
 557         uli526x_descriptor_init(dev, ioaddr);
 558 
 559         /* Init CR6 to program M526X operation */
 560         update_cr6(db->cr6_data, ioaddr);
 561 
 562         /* Send setup frame */
 563         send_filter_frame(dev, netdev_mc_count(dev));   /* M5261/M5263 */
 564 
 565         /* Init CR7, interrupt active bit */
 566         db->cr7_data = CR7_DEFAULT;
 567         uw32(DCR7, db->cr7_data);
 568 
 569         /* Init CR15, Tx jabber and Rx watchdog timer */
 570         uw32(DCR15, db->cr15_data);
 571 
 572         /* Enable ULI526X Tx/Rx function */
 573         db->cr6_data |= CR6_RXSC | CR6_TXSC;
 574         update_cr6(db->cr6_data, ioaddr);
 575 }
 576 
 577 
 578 /*
 579  *      Hardware start transmission.
 580  *      Send a packet to media from the upper layer.
 581  */
 582 
 583 static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb,
 584                                             struct net_device *dev)
 585 {
 586         struct uli526x_board_info *db = netdev_priv(dev);
 587         void __iomem *ioaddr = db->ioaddr;
 588         struct tx_desc *txptr;
 589         unsigned long flags;
 590 
 591         ULI526X_DBUG(0, "uli526x_start_xmit", 0);
 592 
 593         /* Resource flag check */
 594         netif_stop_queue(dev);
 595 
 596         /* Too large packet check */
 597         if (skb->len > MAX_PACKET_SIZE) {
 598                 netdev_err(dev, "big packet = %d\n", (u16)skb->len);
 599                 dev_kfree_skb_any(skb);
 600                 return NETDEV_TX_OK;
 601         }
 602 
 603         spin_lock_irqsave(&db->lock, flags);
 604 
 605         /* No Tx resource check, it never happen nromally */
 606         if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
 607                 spin_unlock_irqrestore(&db->lock, flags);
 608                 netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt);
 609                 return NETDEV_TX_BUSY;
 610         }
 611 
 612         /* Disable NIC interrupt */
 613         uw32(DCR7, 0);
 614 
 615         /* transmit this packet */
 616         txptr = db->tx_insert_ptr;
 617         skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
 618         txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
 619 
 620         /* Point to next transmit free descriptor */
 621         db->tx_insert_ptr = txptr->next_tx_desc;
 622 
 623         /* Transmit Packet Process */
 624         if (db->tx_packet_cnt < TX_DESC_CNT) {
 625                 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
 626                 db->tx_packet_cnt++;                    /* Ready to send */
 627                 uw32(DCR1, 0x1);                        /* Issue Tx polling */
 628                 netif_trans_update(dev);                /* saved time stamp */
 629         }
 630 
 631         /* Tx resource check */
 632         if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
 633                 netif_wake_queue(dev);
 634 
 635         /* Restore CR7 to enable interrupt */
 636         spin_unlock_irqrestore(&db->lock, flags);
 637         uw32(DCR7, db->cr7_data);
 638 
 639         /* free this SKB */
 640         dev_consume_skb_any(skb);
 641 
 642         return NETDEV_TX_OK;
 643 }
 644 
 645 
 646 /*
 647  *      Stop the interface.
 648  *      The interface is stopped when it is brought.
 649  */
 650 
 651 static int uli526x_stop(struct net_device *dev)
 652 {
 653         struct uli526x_board_info *db = netdev_priv(dev);
 654         void __iomem *ioaddr = db->ioaddr;
 655 
 656         /* disable system */
 657         netif_stop_queue(dev);
 658 
 659         /* deleted timer */
 660         del_timer_sync(&db->timer);
 661 
 662         /* Reset & stop ULI526X board */
 663         uw32(DCR0, ULI526X_RESET);
 664         udelay(5);
 665         db->phy.write(db, db->phy_addr, 0, 0x8000);
 666 
 667         /* free interrupt */
 668         free_irq(db->pdev->irq, dev);
 669 
 670         /* free allocated rx buffer */
 671         uli526x_free_rxbuffer(db);
 672 
 673         return 0;
 674 }
 675 
 676 
 677 /*
 678  *      M5261/M5263 insterrupt handler
 679  *      receive the packet to upper layer, free the transmitted packet
 680  */
 681 
 682 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
 683 {
 684         struct net_device *dev = dev_id;
 685         struct uli526x_board_info *db = netdev_priv(dev);
 686         void __iomem *ioaddr = db->ioaddr;
 687         unsigned long flags;
 688 
 689         spin_lock_irqsave(&db->lock, flags);
 690         uw32(DCR7, 0);
 691 
 692         /* Got ULI526X status */
 693         db->cr5_data = ur32(DCR5);
 694         uw32(DCR5, db->cr5_data);
 695         if ( !(db->cr5_data & 0x180c1) ) {
 696                 /* Restore CR7 to enable interrupt mask */
 697                 uw32(DCR7, db->cr7_data);
 698                 spin_unlock_irqrestore(&db->lock, flags);
 699                 return IRQ_HANDLED;
 700         }
 701 
 702         /* Check system status */
 703         if (db->cr5_data & 0x2000) {
 704                 /* system bus error happen */
 705                 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
 706                 db->reset_fatal++;
 707                 db->wait_reset = 1;     /* Need to RESET */
 708                 spin_unlock_irqrestore(&db->lock, flags);
 709                 return IRQ_HANDLED;
 710         }
 711 
 712          /* Received the coming packet */
 713         if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
 714                 uli526x_rx_packet(dev, db);
 715 
 716         /* reallocate rx descriptor buffer */
 717         if (db->rx_avail_cnt<RX_DESC_CNT)
 718                 allocate_rx_buffer(dev);
 719 
 720         /* Free the transmitted descriptor */
 721         if ( db->cr5_data & 0x01)
 722                 uli526x_free_tx_pkt(dev, db);
 723 
 724         /* Restore CR7 to enable interrupt mask */
 725         uw32(DCR7, db->cr7_data);
 726 
 727         spin_unlock_irqrestore(&db->lock, flags);
 728         return IRQ_HANDLED;
 729 }
 730 
 731 #ifdef CONFIG_NET_POLL_CONTROLLER
 732 static void uli526x_poll(struct net_device *dev)
 733 {
 734         struct uli526x_board_info *db = netdev_priv(dev);
 735 
 736         /* ISR grabs the irqsave lock, so this should be safe */
 737         uli526x_interrupt(db->pdev->irq, dev);
 738 }
 739 #endif
 740 
 741 /*
 742  *      Free TX resource after TX complete
 743  */
 744 
 745 static void uli526x_free_tx_pkt(struct net_device *dev,
 746                                 struct uli526x_board_info * db)
 747 {
 748         struct tx_desc *txptr;
 749         u32 tdes0;
 750 
 751         txptr = db->tx_remove_ptr;
 752         while(db->tx_packet_cnt) {
 753                 tdes0 = le32_to_cpu(txptr->tdes0);
 754                 if (tdes0 & 0x80000000)
 755                         break;
 756 
 757                 /* A packet sent completed */
 758                 db->tx_packet_cnt--;
 759                 dev->stats.tx_packets++;
 760 
 761                 /* Transmit statistic counter */
 762                 if ( tdes0 != 0x7fffffff ) {
 763                         dev->stats.collisions += (tdes0 >> 3) & 0xf;
 764                         dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
 765                         if (tdes0 & TDES0_ERR_MASK) {
 766                                 dev->stats.tx_errors++;
 767                                 if (tdes0 & 0x0002) {   /* UnderRun */
 768                                         db->tx_fifo_underrun++;
 769                                         if ( !(db->cr6_data & CR6_SFT) ) {
 770                                                 db->cr6_data = db->cr6_data | CR6_SFT;
 771                                                 update_cr6(db->cr6_data, db->ioaddr);
 772                                         }
 773                                 }
 774                                 if (tdes0 & 0x0100)
 775                                         db->tx_excessive_collision++;
 776                                 if (tdes0 & 0x0200)
 777                                         db->tx_late_collision++;
 778                                 if (tdes0 & 0x0400)
 779                                         db->tx_no_carrier++;
 780                                 if (tdes0 & 0x0800)
 781                                         db->tx_loss_carrier++;
 782                                 if (tdes0 & 0x4000)
 783                                         db->tx_jabber_timeout++;
 784                         }
 785                 }
 786 
 787                 txptr = txptr->next_tx_desc;
 788         }/* End of while */
 789 
 790         /* Update TX remove pointer to next */
 791         db->tx_remove_ptr = txptr;
 792 
 793         /* Resource available check */
 794         if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
 795                 netif_wake_queue(dev);  /* Active upper layer, send again */
 796 }
 797 
 798 
 799 /*
 800  *      Receive the come packet and pass to upper layer
 801  */
 802 
 803 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
 804 {
 805         struct rx_desc *rxptr;
 806         struct sk_buff *skb;
 807         int rxlen;
 808         u32 rdes0;
 809 
 810         rxptr = db->rx_ready_ptr;
 811 
 812         while(db->rx_avail_cnt) {
 813                 rdes0 = le32_to_cpu(rxptr->rdes0);
 814                 if (rdes0 & 0x80000000) /* packet owner check */
 815                 {
 816                         break;
 817                 }
 818 
 819                 db->rx_avail_cnt--;
 820                 db->interval_rx_cnt++;
 821 
 822                 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
 823                 if ( (rdes0 & 0x300) != 0x300) {
 824                         /* A packet without First/Last flag */
 825                         /* reuse this SKB */
 826                         ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
 827                         uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
 828                 } else {
 829                         /* A packet with First/Last flag */
 830                         rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
 831 
 832                         /* error summary bit check */
 833                         if (rdes0 & 0x8000) {
 834                                 /* This is a error packet */
 835                                 dev->stats.rx_errors++;
 836                                 if (rdes0 & 1)
 837                                         dev->stats.rx_fifo_errors++;
 838                                 if (rdes0 & 2)
 839                                         dev->stats.rx_crc_errors++;
 840                                 if (rdes0 & 0x80)
 841                                         dev->stats.rx_length_errors++;
 842                         }
 843 
 844                         if ( !(rdes0 & 0x8000) ||
 845                                 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
 846                                 struct sk_buff *new_skb = NULL;
 847 
 848                                 skb = rxptr->rx_skb_ptr;
 849 
 850                                 /* Good packet, send to upper layer */
 851                                 /* Shorst packet used new SKB */
 852                                 if ((rxlen < RX_COPY_SIZE) &&
 853                                     (((new_skb = netdev_alloc_skb(dev, rxlen + 2)) != NULL))) {
 854                                         skb = new_skb;
 855                                         /* size less than COPY_SIZE, allocate a rxlen SKB */
 856                                         skb_reserve(skb, 2); /* 16byte align */
 857                                         skb_put_data(skb,
 858                                                      skb_tail_pointer(rxptr->rx_skb_ptr),
 859                                                      rxlen);
 860                                         uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
 861                                 } else
 862                                         skb_put(skb, rxlen);
 863 
 864                                 skb->protocol = eth_type_trans(skb, dev);
 865                                 netif_rx(skb);
 866                                 dev->stats.rx_packets++;
 867                                 dev->stats.rx_bytes += rxlen;
 868 
 869                         } else {
 870                                 /* Reuse SKB buffer when the packet is error */
 871                                 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
 872                                 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
 873                         }
 874                 }
 875 
 876                 rxptr = rxptr->next_rx_desc;
 877         }
 878 
 879         db->rx_ready_ptr = rxptr;
 880 }
 881 
 882 
 883 /*
 884  * Set ULI526X multicast address
 885  */
 886 
 887 static void uli526x_set_filter_mode(struct net_device * dev)
 888 {
 889         struct uli526x_board_info *db = netdev_priv(dev);
 890         unsigned long flags;
 891 
 892         ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
 893         spin_lock_irqsave(&db->lock, flags);
 894 
 895         if (dev->flags & IFF_PROMISC) {
 896                 ULI526X_DBUG(0, "Enable PROM Mode", 0);
 897                 db->cr6_data |= CR6_PM | CR6_PBF;
 898                 update_cr6(db->cr6_data, db->ioaddr);
 899                 spin_unlock_irqrestore(&db->lock, flags);
 900                 return;
 901         }
 902 
 903         if (dev->flags & IFF_ALLMULTI ||
 904             netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) {
 905                 ULI526X_DBUG(0, "Pass all multicast address",
 906                              netdev_mc_count(dev));
 907                 db->cr6_data &= ~(CR6_PM | CR6_PBF);
 908                 db->cr6_data |= CR6_PAM;
 909                 spin_unlock_irqrestore(&db->lock, flags);
 910                 return;
 911         }
 912 
 913         ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev));
 914         send_filter_frame(dev, netdev_mc_count(dev));   /* M5261/M5263 */
 915         spin_unlock_irqrestore(&db->lock, flags);
 916 }
 917 
 918 static void
 919 ULi_ethtool_get_link_ksettings(struct uli526x_board_info *db,
 920                                struct ethtool_link_ksettings *cmd)
 921 {
 922         u32 supported, advertising;
 923 
 924         supported = (SUPPORTED_10baseT_Half |
 925                            SUPPORTED_10baseT_Full |
 926                            SUPPORTED_100baseT_Half |
 927                            SUPPORTED_100baseT_Full |
 928                            SUPPORTED_Autoneg |
 929                            SUPPORTED_MII);
 930 
 931         advertising = (ADVERTISED_10baseT_Half |
 932                            ADVERTISED_10baseT_Full |
 933                            ADVERTISED_100baseT_Half |
 934                            ADVERTISED_100baseT_Full |
 935                            ADVERTISED_Autoneg |
 936                            ADVERTISED_MII);
 937 
 938         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
 939                                                 supported);
 940         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
 941                                                 advertising);
 942 
 943         cmd->base.port = PORT_MII;
 944         cmd->base.phy_address = db->phy_addr;
 945 
 946         cmd->base.speed = SPEED_10;
 947         cmd->base.duplex = DUPLEX_HALF;
 948 
 949         if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
 950         {
 951                 cmd->base.speed = SPEED_100;
 952         }
 953         if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
 954         {
 955                 cmd->base.duplex = DUPLEX_FULL;
 956         }
 957         if(db->link_failed)
 958         {
 959                 cmd->base.speed = SPEED_UNKNOWN;
 960                 cmd->base.duplex = DUPLEX_UNKNOWN;
 961         }
 962 
 963         if (db->media_mode & ULI526X_AUTO)
 964         {
 965                 cmd->base.autoneg = AUTONEG_ENABLE;
 966         }
 967 }
 968 
 969 static void netdev_get_drvinfo(struct net_device *dev,
 970                                struct ethtool_drvinfo *info)
 971 {
 972         struct uli526x_board_info *np = netdev_priv(dev);
 973 
 974         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
 975         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
 976         strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
 977 }
 978 
 979 static int netdev_get_link_ksettings(struct net_device *dev,
 980                                      struct ethtool_link_ksettings *cmd)
 981 {
 982         struct uli526x_board_info *np = netdev_priv(dev);
 983 
 984         ULi_ethtool_get_link_ksettings(np, cmd);
 985 
 986         return 0;
 987 }
 988 
 989 static u32 netdev_get_link(struct net_device *dev) {
 990         struct uli526x_board_info *np = netdev_priv(dev);
 991 
 992         if(np->link_failed)
 993                 return 0;
 994         else
 995                 return 1;
 996 }
 997 
 998 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 999 {
1000         wol->supported = WAKE_PHY | WAKE_MAGIC;
1001         wol->wolopts = 0;
1002 }
1003 
1004 static const struct ethtool_ops netdev_ethtool_ops = {
1005         .get_drvinfo            = netdev_get_drvinfo,
1006         .get_link               = netdev_get_link,
1007         .get_wol                = uli526x_get_wol,
1008         .get_link_ksettings     = netdev_get_link_ksettings,
1009 };
1010 
1011 /*
1012  *      A periodic timer routine
1013  *      Dynamic media sense, allocate Rx buffer...
1014  */
1015 
1016 static void uli526x_timer(struct timer_list *t)
1017 {
1018         struct uli526x_board_info *db = from_timer(db, t, timer);
1019         struct net_device *dev = pci_get_drvdata(db->pdev);
1020         struct uli_phy_ops *phy = &db->phy;
1021         void __iomem *ioaddr = db->ioaddr;
1022         unsigned long flags;
1023         u8 tmp_cr12 = 0;
1024         u32 tmp_cr8;
1025 
1026         //ULI526X_DBUG(0, "uli526x_timer()", 0);
1027         spin_lock_irqsave(&db->lock, flags);
1028 
1029 
1030         /* Dynamic reset ULI526X : system error or transmit time-out */
1031         tmp_cr8 = ur32(DCR8);
1032         if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1033                 db->reset_cr8++;
1034                 db->wait_reset = 1;
1035         }
1036         db->interval_rx_cnt = 0;
1037 
1038         /* TX polling kick monitor */
1039         if ( db->tx_packet_cnt &&
1040              time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) {
1041                 uw32(DCR1, 0x1);   // Tx polling again
1042 
1043                 // TX Timeout
1044                 if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) {
1045                         db->reset_TXtimeout++;
1046                         db->wait_reset = 1;
1047                         netdev_err(dev, " Tx timeout - resetting\n");
1048                 }
1049         }
1050 
1051         if (db->wait_reset) {
1052                 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1053                 db->reset_count++;
1054                 uli526x_dynamic_reset(dev);
1055                 db->timer.expires = ULI526X_TIMER_WUT;
1056                 add_timer(&db->timer);
1057                 spin_unlock_irqrestore(&db->lock, flags);
1058                 return;
1059         }
1060 
1061         /* Link status check, Dynamic media type change */
1062         if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0)
1063                 tmp_cr12 = 3;
1064 
1065         if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1066                 /* Link Failed */
1067                 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1068                 netif_carrier_off(dev);
1069                 netdev_info(dev, "NIC Link is Down\n");
1070                 db->link_failed = 1;
1071 
1072                 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1073                 /* AUTO don't need */
1074                 if ( !(db->media_mode & 0x8) )
1075                         phy->write(db, db->phy_addr, 0, 0x1000);
1076 
1077                 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1078                 if (db->media_mode & ULI526X_AUTO) {
1079                         db->cr6_data&=~0x00000200;      /* bit9=0, HD mode */
1080                         update_cr6(db->cr6_data, db->ioaddr);
1081                 }
1082         } else
1083                 if ((tmp_cr12 & 0x3) && db->link_failed) {
1084                         ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1085                         db->link_failed = 0;
1086 
1087                         /* Auto Sense Speed */
1088                         if ( (db->media_mode & ULI526X_AUTO) &&
1089                                 uli526x_sense_speed(db) )
1090                                 db->link_failed = 1;
1091                         uli526x_process_mode(db);
1092 
1093                         if(db->link_failed==0)
1094                         {
1095                                 netdev_info(dev, "NIC Link is Up %d Mbps %s duplex\n",
1096                                             (db->op_mode == ULI526X_100MHF ||
1097                                              db->op_mode == ULI526X_100MFD)
1098                                             ? 100 : 10,
1099                                             (db->op_mode == ULI526X_10MFD ||
1100                                              db->op_mode == ULI526X_100MFD)
1101                                             ? "Full" : "Half");
1102                                 netif_carrier_on(dev);
1103                         }
1104                         /* SHOW_MEDIA_TYPE(db->op_mode); */
1105                 }
1106                 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1107                 {
1108                         if(db->init==1)
1109                         {
1110                                 netdev_info(dev, "NIC Link is Down\n");
1111                                 netif_carrier_off(dev);
1112                         }
1113                 }
1114         db->init = 0;
1115 
1116         /* Timer active again */
1117         db->timer.expires = ULI526X_TIMER_WUT;
1118         add_timer(&db->timer);
1119         spin_unlock_irqrestore(&db->lock, flags);
1120 }
1121 
1122 
1123 /*
1124  *      Stop ULI526X board
1125  *      Free Tx/Rx allocated memory
1126  *      Init system variable
1127  */
1128 
1129 static void uli526x_reset_prepare(struct net_device *dev)
1130 {
1131         struct uli526x_board_info *db = netdev_priv(dev);
1132         void __iomem *ioaddr = db->ioaddr;
1133 
1134         /* Sopt MAC controller */
1135         db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1136         update_cr6(db->cr6_data, ioaddr);
1137         uw32(DCR7, 0);                          /* Disable Interrupt */
1138         uw32(DCR5, ur32(DCR5));
1139 
1140         /* Disable upper layer interface */
1141         netif_stop_queue(dev);
1142 
1143         /* Free Rx Allocate buffer */
1144         uli526x_free_rxbuffer(db);
1145 
1146         /* system variable init */
1147         db->tx_packet_cnt = 0;
1148         db->rx_avail_cnt = 0;
1149         db->link_failed = 1;
1150         db->init=1;
1151         db->wait_reset = 0;
1152 }
1153 
1154 
1155 /*
1156  *      Dynamic reset the ULI526X board
1157  *      Stop ULI526X board
1158  *      Free Tx/Rx allocated memory
1159  *      Reset ULI526X board
1160  *      Re-initialize ULI526X board
1161  */
1162 
1163 static void uli526x_dynamic_reset(struct net_device *dev)
1164 {
1165         ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1166 
1167         uli526x_reset_prepare(dev);
1168 
1169         /* Re-initialize ULI526X board */
1170         uli526x_init(dev);
1171 
1172         /* Restart upper layer interface */
1173         netif_wake_queue(dev);
1174 }
1175 
1176 
1177 #ifdef CONFIG_PM
1178 
1179 /*
1180  *      Suspend the interface.
1181  */
1182 
1183 static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1184 {
1185         struct net_device *dev = pci_get_drvdata(pdev);
1186         pci_power_t power_state;
1187         int err;
1188 
1189         ULI526X_DBUG(0, "uli526x_suspend", 0);
1190 
1191         pci_save_state(pdev);
1192 
1193         if (!netif_running(dev))
1194                 return 0;
1195 
1196         netif_device_detach(dev);
1197         uli526x_reset_prepare(dev);
1198 
1199         power_state = pci_choose_state(pdev, state);
1200         pci_enable_wake(pdev, power_state, 0);
1201         err = pci_set_power_state(pdev, power_state);
1202         if (err) {
1203                 netif_device_attach(dev);
1204                 /* Re-initialize ULI526X board */
1205                 uli526x_init(dev);
1206                 /* Restart upper layer interface */
1207                 netif_wake_queue(dev);
1208         }
1209 
1210         return err;
1211 }
1212 
1213 /*
1214  *      Resume the interface.
1215  */
1216 
1217 static int uli526x_resume(struct pci_dev *pdev)
1218 {
1219         struct net_device *dev = pci_get_drvdata(pdev);
1220         int err;
1221 
1222         ULI526X_DBUG(0, "uli526x_resume", 0);
1223 
1224         pci_restore_state(pdev);
1225 
1226         if (!netif_running(dev))
1227                 return 0;
1228 
1229         err = pci_set_power_state(pdev, PCI_D0);
1230         if (err) {
1231                 netdev_warn(dev, "Could not put device into D0\n");
1232                 return err;
1233         }
1234 
1235         netif_device_attach(dev);
1236         /* Re-initialize ULI526X board */
1237         uli526x_init(dev);
1238         /* Restart upper layer interface */
1239         netif_wake_queue(dev);
1240 
1241         return 0;
1242 }
1243 
1244 #else /* !CONFIG_PM */
1245 
1246 #define uli526x_suspend NULL
1247 #define uli526x_resume  NULL
1248 
1249 #endif /* !CONFIG_PM */
1250 
1251 
1252 /*
1253  *      free all allocated rx buffer
1254  */
1255 
1256 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1257 {
1258         ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1259 
1260         /* free allocated rx buffer */
1261         while (db->rx_avail_cnt) {
1262                 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1263                 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1264                 db->rx_avail_cnt--;
1265         }
1266 }
1267 
1268 
1269 /*
1270  *      Reuse the SK buffer
1271  */
1272 
1273 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1274 {
1275         struct rx_desc *rxptr = db->rx_insert_ptr;
1276 
1277         if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1278                 rxptr->rx_skb_ptr = skb;
1279                 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1280                                                           skb_tail_pointer(skb),
1281                                                           RX_ALLOC_SIZE,
1282                                                           PCI_DMA_FROMDEVICE));
1283                 wmb();
1284                 rxptr->rdes0 = cpu_to_le32(0x80000000);
1285                 db->rx_avail_cnt++;
1286                 db->rx_insert_ptr = rxptr->next_rx_desc;
1287         } else
1288                 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1289 }
1290 
1291 
1292 /*
1293  *      Initialize transmit/Receive descriptor
1294  *      Using Chain structure, and allocate Tx/Rx buffer
1295  */
1296 
1297 static void uli526x_descriptor_init(struct net_device *dev, void __iomem *ioaddr)
1298 {
1299         struct uli526x_board_info *db = netdev_priv(dev);
1300         struct tx_desc *tmp_tx;
1301         struct rx_desc *tmp_rx;
1302         unsigned char *tmp_buf;
1303         dma_addr_t tmp_tx_dma, tmp_rx_dma;
1304         dma_addr_t tmp_buf_dma;
1305         int i;
1306 
1307         ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1308 
1309         /* tx descriptor start pointer */
1310         db->tx_insert_ptr = db->first_tx_desc;
1311         db->tx_remove_ptr = db->first_tx_desc;
1312         uw32(DCR4, db->first_tx_desc_dma);      /* TX DESC address */
1313 
1314         /* rx descriptor start pointer */
1315         db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1316         db->first_rx_desc_dma =  db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1317         db->rx_insert_ptr = db->first_rx_desc;
1318         db->rx_ready_ptr = db->first_rx_desc;
1319         uw32(DCR3, db->first_rx_desc_dma);      /* RX DESC address */
1320 
1321         /* Init Transmit chain */
1322         tmp_buf = db->buf_pool_start;
1323         tmp_buf_dma = db->buf_pool_dma_start;
1324         tmp_tx_dma = db->first_tx_desc_dma;
1325         for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1326                 tmp_tx->tx_buf_ptr = tmp_buf;
1327                 tmp_tx->tdes0 = cpu_to_le32(0);
1328                 tmp_tx->tdes1 = cpu_to_le32(0x81000000);        /* IC, chain */
1329                 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1330                 tmp_tx_dma += sizeof(struct tx_desc);
1331                 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1332                 tmp_tx->next_tx_desc = tmp_tx + 1;
1333                 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1334                 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1335         }
1336         (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1337         tmp_tx->next_tx_desc = db->first_tx_desc;
1338 
1339          /* Init Receive descriptor chain */
1340         tmp_rx_dma=db->first_rx_desc_dma;
1341         for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1342                 tmp_rx->rdes0 = cpu_to_le32(0);
1343                 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1344                 tmp_rx_dma += sizeof(struct rx_desc);
1345                 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1346                 tmp_rx->next_rx_desc = tmp_rx + 1;
1347         }
1348         (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1349         tmp_rx->next_rx_desc = db->first_rx_desc;
1350 
1351         /* pre-allocate Rx buffer */
1352         allocate_rx_buffer(dev);
1353 }
1354 
1355 
1356 /*
1357  *      Update CR6 value
1358  *      Firstly stop ULI526X, then written value and start
1359  */
1360 static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
1361 {
1362         uw32(DCR6, cr6_data);
1363         udelay(5);
1364 }
1365 
1366 
1367 /*
1368  *      Send a setup frame for M5261/M5263
1369  *      This setup frame initialize ULI526X address filter mode
1370  */
1371 
1372 #ifdef __BIG_ENDIAN
1373 #define FLT_SHIFT 16
1374 #else
1375 #define FLT_SHIFT 0
1376 #endif
1377 
1378 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1379 {
1380         struct uli526x_board_info *db = netdev_priv(dev);
1381         void __iomem *ioaddr = db->ioaddr;
1382         struct netdev_hw_addr *ha;
1383         struct tx_desc *txptr;
1384         u16 * addrptr;
1385         u32 * suptr;
1386         int i;
1387 
1388         ULI526X_DBUG(0, "send_filter_frame()", 0);
1389 
1390         txptr = db->tx_insert_ptr;
1391         suptr = (u32 *) txptr->tx_buf_ptr;
1392 
1393         /* Node address */
1394         addrptr = (u16 *) dev->dev_addr;
1395         *suptr++ = addrptr[0] << FLT_SHIFT;
1396         *suptr++ = addrptr[1] << FLT_SHIFT;
1397         *suptr++ = addrptr[2] << FLT_SHIFT;
1398 
1399         /* broadcast address */
1400         *suptr++ = 0xffff << FLT_SHIFT;
1401         *suptr++ = 0xffff << FLT_SHIFT;
1402         *suptr++ = 0xffff << FLT_SHIFT;
1403 
1404         /* fit the multicast address */
1405         netdev_for_each_mc_addr(ha, dev) {
1406                 addrptr = (u16 *) ha->addr;
1407                 *suptr++ = addrptr[0] << FLT_SHIFT;
1408                 *suptr++ = addrptr[1] << FLT_SHIFT;
1409                 *suptr++ = addrptr[2] << FLT_SHIFT;
1410         }
1411 
1412         for (i = netdev_mc_count(dev); i < 14; i++) {
1413                 *suptr++ = 0xffff << FLT_SHIFT;
1414                 *suptr++ = 0xffff << FLT_SHIFT;
1415                 *suptr++ = 0xffff << FLT_SHIFT;
1416         }
1417 
1418         /* prepare the setup frame */
1419         db->tx_insert_ptr = txptr->next_tx_desc;
1420         txptr->tdes1 = cpu_to_le32(0x890000c0);
1421 
1422         /* Resource Check and Send the setup packet */
1423         if (db->tx_packet_cnt < TX_DESC_CNT) {
1424                 /* Resource Empty */
1425                 db->tx_packet_cnt++;
1426                 txptr->tdes0 = cpu_to_le32(0x80000000);
1427                 update_cr6(db->cr6_data | 0x2000, ioaddr);
1428                 uw32(DCR1, 0x1);        /* Issue Tx polling */
1429                 update_cr6(db->cr6_data, ioaddr);
1430                 netif_trans_update(dev);
1431         } else
1432                 netdev_err(dev, "No Tx resource - Send_filter_frame!\n");
1433 }
1434 
1435 
1436 /*
1437  *      Allocate rx buffer,
1438  *      As possible as allocate maxiumn Rx buffer
1439  */
1440 
1441 static void allocate_rx_buffer(struct net_device *dev)
1442 {
1443         struct uli526x_board_info *db = netdev_priv(dev);
1444         struct rx_desc *rxptr;
1445         struct sk_buff *skb;
1446 
1447         rxptr = db->rx_insert_ptr;
1448 
1449         while(db->rx_avail_cnt < RX_DESC_CNT) {
1450                 skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE);
1451                 if (skb == NULL)
1452                         break;
1453                 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1454                 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1455                                                           skb_tail_pointer(skb),
1456                                                           RX_ALLOC_SIZE,
1457                                                           PCI_DMA_FROMDEVICE));
1458                 wmb();
1459                 rxptr->rdes0 = cpu_to_le32(0x80000000);
1460                 rxptr = rxptr->next_rx_desc;
1461                 db->rx_avail_cnt++;
1462         }
1463 
1464         db->rx_insert_ptr = rxptr;
1465 }
1466 
1467 
1468 /*
1469  *      Read one word data from the serial ROM
1470  */
1471 
1472 static u16 read_srom_word(struct uli526x_board_info *db, int offset)
1473 {
1474         void __iomem *ioaddr = db->ioaddr;
1475         u16 srom_data = 0;
1476         int i;
1477 
1478         uw32(DCR9, CR9_SROM_READ);
1479         uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1480 
1481         /* Send the Read Command 110b */
1482         srom_clk_write(db, SROM_DATA_1);
1483         srom_clk_write(db, SROM_DATA_1);
1484         srom_clk_write(db, SROM_DATA_0);
1485 
1486         /* Send the offset */
1487         for (i = 5; i >= 0; i--) {
1488                 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1489                 srom_clk_write(db, srom_data);
1490         }
1491 
1492         uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1493 
1494         for (i = 16; i > 0; i--) {
1495                 uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
1496                 udelay(5);
1497                 srom_data = (srom_data << 1) |
1498                             ((ur32(DCR9) & CR9_CRDOUT) ? 1 : 0);
1499                 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1500                 udelay(5);
1501         }
1502 
1503         uw32(DCR9, CR9_SROM_READ);
1504         return srom_data;
1505 }
1506 
1507 
1508 /*
1509  *      Auto sense the media mode
1510  */
1511 
1512 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1513 {
1514         struct uli_phy_ops *phy = &db->phy;
1515         u8 ErrFlag = 0;
1516         u16 phy_mode;
1517 
1518         phy_mode = phy->read(db, db->phy_addr, 1);
1519         phy_mode = phy->read(db, db->phy_addr, 1);
1520 
1521         if ( (phy_mode & 0x24) == 0x24 ) {
1522 
1523                 phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7);
1524                 if(phy_mode&0x8000)
1525                         phy_mode = 0x8000;
1526                 else if(phy_mode&0x4000)
1527                         phy_mode = 0x4000;
1528                 else if(phy_mode&0x2000)
1529                         phy_mode = 0x2000;
1530                 else
1531                         phy_mode = 0x1000;
1532 
1533                 switch (phy_mode) {
1534                 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1535                 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1536                 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1537                 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1538                 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1539                 }
1540         } else {
1541                 db->op_mode = ULI526X_10MHF;
1542                 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1543                 ErrFlag = 1;
1544         }
1545 
1546         return ErrFlag;
1547 }
1548 
1549 
1550 /*
1551  *      Set 10/100 phyxcer capability
1552  *      AUTO mode : phyxcer register4 is NIC capability
1553  *      Force mode: phyxcer register4 is the force media
1554  */
1555 
1556 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1557 {
1558         struct uli_phy_ops *phy = &db->phy;
1559         u16 phy_reg;
1560 
1561         /* Phyxcer capability setting */
1562         phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0;
1563 
1564         if (db->media_mode & ULI526X_AUTO) {
1565                 /* AUTO Mode */
1566                 phy_reg |= db->PHY_reg4;
1567         } else {
1568                 /* Force Mode */
1569                 switch(db->media_mode) {
1570                 case ULI526X_10MHF: phy_reg |= 0x20; break;
1571                 case ULI526X_10MFD: phy_reg |= 0x40; break;
1572                 case ULI526X_100MHF: phy_reg |= 0x80; break;
1573                 case ULI526X_100MFD: phy_reg |= 0x100; break;
1574                 }
1575 
1576         }
1577 
1578         /* Write new capability to Phyxcer Reg4 */
1579         if ( !(phy_reg & 0x01e0)) {
1580                 phy_reg|=db->PHY_reg4;
1581                 db->media_mode|=ULI526X_AUTO;
1582         }
1583         phy->write(db, db->phy_addr, 4, phy_reg);
1584 
1585         /* Restart Auto-Negotiation */
1586         phy->write(db, db->phy_addr, 0, 0x1200);
1587         udelay(50);
1588 }
1589 
1590 
1591 /*
1592  *      Process op-mode
1593         AUTO mode : PHY controller in Auto-negotiation Mode
1594  *      Force mode: PHY controller in force mode with HUB
1595  *                      N-way force capability with SWITCH
1596  */
1597 
1598 static void uli526x_process_mode(struct uli526x_board_info *db)
1599 {
1600         struct uli_phy_ops *phy = &db->phy;
1601         u16 phy_reg;
1602 
1603         /* Full Duplex Mode Check */
1604         if (db->op_mode & 0x4)
1605                 db->cr6_data |= CR6_FDM;        /* Set Full Duplex Bit */
1606         else
1607                 db->cr6_data &= ~CR6_FDM;       /* Clear Full Duplex Bit */
1608 
1609         update_cr6(db->cr6_data, db->ioaddr);
1610 
1611         /* 10/100M phyxcer force mode need */
1612         if (!(db->media_mode & 0x8)) {
1613                 /* Forece Mode */
1614                 phy_reg = phy->read(db, db->phy_addr, 6);
1615                 if (!(phy_reg & 0x1)) {
1616                         /* parter without N-Way capability */
1617                         phy_reg = 0x0;
1618                         switch(db->op_mode) {
1619                         case ULI526X_10MHF: phy_reg = 0x0; break;
1620                         case ULI526X_10MFD: phy_reg = 0x100; break;
1621                         case ULI526X_100MHF: phy_reg = 0x2000; break;
1622                         case ULI526X_100MFD: phy_reg = 0x2100; break;
1623                         }
1624                         phy->write(db, db->phy_addr, 0, phy_reg);
1625                 }
1626         }
1627 }
1628 
1629 
1630 /* M5261/M5263 Chip */
1631 static void phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr,
1632                             u8 offset, u16 phy_data)
1633 {
1634         u16 i;
1635 
1636         /* Send 33 synchronization clock to Phy controller */
1637         for (i = 0; i < 35; i++)
1638                 phy_write_1bit(db, PHY_DATA_1);
1639 
1640         /* Send start command(01) to Phy */
1641         phy_write_1bit(db, PHY_DATA_0);
1642         phy_write_1bit(db, PHY_DATA_1);
1643 
1644         /* Send write command(01) to Phy */
1645         phy_write_1bit(db, PHY_DATA_0);
1646         phy_write_1bit(db, PHY_DATA_1);
1647 
1648         /* Send Phy address */
1649         for (i = 0x10; i > 0; i = i >> 1)
1650                 phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1651 
1652         /* Send register address */
1653         for (i = 0x10; i > 0; i = i >> 1)
1654                 phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1655 
1656         /* written trasnition */
1657         phy_write_1bit(db, PHY_DATA_1);
1658         phy_write_1bit(db, PHY_DATA_0);
1659 
1660         /* Write a word data to PHY controller */
1661         for (i = 0x8000; i > 0; i >>= 1)
1662                 phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1663 }
1664 
1665 static u16 phy_readby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset)
1666 {
1667         u16 phy_data;
1668         int i;
1669 
1670         /* Send 33 synchronization clock to Phy controller */
1671         for (i = 0; i < 35; i++)
1672                 phy_write_1bit(db, PHY_DATA_1);
1673 
1674         /* Send start command(01) to Phy */
1675         phy_write_1bit(db, PHY_DATA_0);
1676         phy_write_1bit(db, PHY_DATA_1);
1677 
1678         /* Send read command(10) to Phy */
1679         phy_write_1bit(db, PHY_DATA_1);
1680         phy_write_1bit(db, PHY_DATA_0);
1681 
1682         /* Send Phy address */
1683         for (i = 0x10; i > 0; i = i >> 1)
1684                 phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1685 
1686         /* Send register address */
1687         for (i = 0x10; i > 0; i = i >> 1)
1688                 phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1689 
1690         /* Skip transition state */
1691         phy_read_1bit(db);
1692 
1693         /* read 16bit data */
1694         for (phy_data = 0, i = 0; i < 16; i++) {
1695                 phy_data <<= 1;
1696                 phy_data |= phy_read_1bit(db);
1697         }
1698 
1699         return phy_data;
1700 }
1701 
1702 static u16 phy_readby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1703                            u8 offset)
1704 {
1705         void __iomem *ioaddr = db->ioaddr;
1706         u32 cr10_value = phy_addr;
1707 
1708         cr10_value = (cr10_value <<  5) + offset;
1709         cr10_value = (cr10_value << 16) + 0x08000000;
1710         uw32(DCR10, cr10_value);
1711         udelay(1);
1712         while (1) {
1713                 cr10_value = ur32(DCR10);
1714                 if (cr10_value & 0x10000000)
1715                         break;
1716         }
1717         return cr10_value & 0x0ffff;
1718 }
1719 
1720 static void phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1721                              u8 offset, u16 phy_data)
1722 {
1723         void __iomem *ioaddr = db->ioaddr;
1724         u32 cr10_value = phy_addr;
1725 
1726         cr10_value = (cr10_value <<  5) + offset;
1727         cr10_value = (cr10_value << 16) + 0x04000000 + phy_data;
1728         uw32(DCR10, cr10_value);
1729         udelay(1);
1730 }
1731 /*
1732  *      Write one bit data to Phy Controller
1733  */
1734 
1735 static void phy_write_1bit(struct uli526x_board_info *db, u32 data)
1736 {
1737         void __iomem *ioaddr = db->ioaddr;
1738 
1739         uw32(DCR9, data);               /* MII Clock Low */
1740         udelay(1);
1741         uw32(DCR9, data | MDCLKH);      /* MII Clock High */
1742         udelay(1);
1743         uw32(DCR9, data);               /* MII Clock Low */
1744         udelay(1);
1745 }
1746 
1747 
1748 /*
1749  *      Read one bit phy data from PHY controller
1750  */
1751 
1752 static u16 phy_read_1bit(struct uli526x_board_info *db)
1753 {
1754         void __iomem *ioaddr = db->ioaddr;
1755         u16 phy_data;
1756 
1757         uw32(DCR9, 0x50000);
1758         udelay(1);
1759         phy_data = (ur32(DCR9) >> 19) & 0x1;
1760         uw32(DCR9, 0x40000);
1761         udelay(1);
1762 
1763         return phy_data;
1764 }
1765 
1766 
1767 static const struct pci_device_id uli526x_pci_tbl[] = {
1768         { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1769         { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1770         { 0, }
1771 };
1772 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1773 
1774 
1775 static struct pci_driver uli526x_driver = {
1776         .name           = "uli526x",
1777         .id_table       = uli526x_pci_tbl,
1778         .probe          = uli526x_init_one,
1779         .remove         = uli526x_remove_one,
1780         .suspend        = uli526x_suspend,
1781         .resume         = uli526x_resume,
1782 };
1783 
1784 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1785 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1786 MODULE_LICENSE("GPL");
1787 
1788 module_param(debug, int, 0644);
1789 module_param(mode, int, 0);
1790 module_param(cr6set, int, 0);
1791 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1792 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1793 
1794 /*      Description:
1795  *      when user used insmod to add module, system invoked init_module()
1796  *      to register the services.
1797  */
1798 
1799 static int __init uli526x_init_module(void)
1800 {
1801 
1802         pr_info("%s\n", version);
1803         printed_version = 1;
1804 
1805         ULI526X_DBUG(0, "init_module() ", debug);
1806 
1807         if (debug)
1808                 uli526x_debug = debug;  /* set debug flag */
1809         if (cr6set)
1810                 uli526x_cr6_user_set = cr6set;
1811 
1812         switch (mode) {
1813         case ULI526X_10MHF:
1814         case ULI526X_100MHF:
1815         case ULI526X_10MFD:
1816         case ULI526X_100MFD:
1817                 uli526x_media_mode = mode;
1818                 break;
1819         default:
1820                 uli526x_media_mode = ULI526X_AUTO;
1821                 break;
1822         }
1823 
1824         return pci_register_driver(&uli526x_driver);
1825 }
1826 
1827 
1828 /*
1829  *      Description:
1830  *      when user used rmmod to delete module, system invoked clean_module()
1831  *      to un-register all registered services.
1832  */
1833 
1834 static void __exit uli526x_cleanup_module(void)
1835 {
1836         ULI526X_DBUG(0, "uli526x_cleanup_module() ", debug);
1837         pci_unregister_driver(&uli526x_driver);
1838 }
1839 
1840 module_init(uli526x_init_module);
1841 module_exit(uli526x_cleanup_module);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/dec/tulip/uli526x.c

DEFINITIONS
