This source file includes following definitions.
- ionic_init_devinfo
- ionic_dev_setup
- ionic_dev_teardown
- ionic_dev_cmd_status
- ionic_dev_cmd_done
- ionic_dev_cmd_comp
- ionic_dev_cmd_go
- ionic_dev_cmd_identify
- ionic_dev_cmd_init
- ionic_dev_cmd_reset
- ionic_dev_cmd_port_identify
- ionic_dev_cmd_port_init
- ionic_dev_cmd_port_reset
- ionic_dev_cmd_port_state
- ionic_dev_cmd_port_speed
- ionic_dev_cmd_port_autoneg
- ionic_dev_cmd_port_fec
- ionic_dev_cmd_port_pause
- ionic_dev_cmd_lif_identify
- ionic_dev_cmd_lif_init
- ionic_dev_cmd_lif_reset
- ionic_dev_cmd_adminq_init
- ionic_db_page_num
- ionic_cq_init
- ionic_cq_map
- ionic_cq_bind
- ionic_cq_service
- ionic_q_init
- ionic_q_map
- ionic_q_sg_map
- ionic_q_post
- ionic_q_is_posted
- ionic_q_service
1
2
3
4 #include <linux/kernel.h>
5 #include <linux/types.h>
6 #include <linux/errno.h>
7 #include <linux/io.h>
8 #include <linux/slab.h>
9 #include <linux/etherdevice.h>
10 #include "ionic.h"
11 #include "ionic_dev.h"
12 #include "ionic_lif.h"
13
14 void ionic_init_devinfo(struct ionic *ionic)
15 {
16 struct ionic_dev *idev = &ionic->idev;
17
18 idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type);
19 idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev);
20
21 memcpy_fromio(idev->dev_info.fw_version,
22 idev->dev_info_regs->fw_version,
23 IONIC_DEVINFO_FWVERS_BUFLEN);
24
25 memcpy_fromio(idev->dev_info.serial_num,
26 idev->dev_info_regs->serial_num,
27 IONIC_DEVINFO_SERIAL_BUFLEN);
28
29 idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0;
30 idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0;
31
32 dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version);
33 }
34
35 int ionic_dev_setup(struct ionic *ionic)
36 {
37 struct ionic_dev_bar *bar = ionic->bars;
38 unsigned int num_bars = ionic->num_bars;
39 struct ionic_dev *idev = &ionic->idev;
40 struct device *dev = ionic->dev;
41 u32 sig;
42
43
44 if (num_bars < 1) {
45 dev_err(dev, "No bars found, aborting\n");
46 return -EFAULT;
47 }
48
49 if (bar->len < IONIC_BAR0_SIZE) {
50 dev_err(dev, "Resource bar size %lu too small, aborting\n",
51 bar->len);
52 return -EFAULT;
53 }
54
55 idev->dev_info_regs = bar->vaddr + IONIC_BAR0_DEV_INFO_REGS_OFFSET;
56 idev->dev_cmd_regs = bar->vaddr + IONIC_BAR0_DEV_CMD_REGS_OFFSET;
57 idev->intr_status = bar->vaddr + IONIC_BAR0_INTR_STATUS_OFFSET;
58 idev->intr_ctrl = bar->vaddr + IONIC_BAR0_INTR_CTRL_OFFSET;
59
60 sig = ioread32(&idev->dev_info_regs->signature);
61 if (sig != IONIC_DEV_INFO_SIGNATURE) {
62 dev_err(dev, "Incompatible firmware signature %x", sig);
63 return -EFAULT;
64 }
65
66 ionic_init_devinfo(ionic);
67
68
69 bar++;
70 if (num_bars < 2) {
71 dev_err(dev, "Doorbell bar missing, aborting\n");
72 return -EFAULT;
73 }
74
75 idev->db_pages = bar->vaddr;
76 idev->phy_db_pages = bar->bus_addr;
77
78 return 0;
79 }
80
81 void ionic_dev_teardown(struct ionic *ionic)
82 {
83
84 }
85
86
87 u8 ionic_dev_cmd_status(struct ionic_dev *idev)
88 {
89 return ioread8(&idev->dev_cmd_regs->comp.comp.status);
90 }
91
92 bool ionic_dev_cmd_done(struct ionic_dev *idev)
93 {
94 return ioread32(&idev->dev_cmd_regs->done) & IONIC_DEV_CMD_DONE;
95 }
96
97 void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp)
98 {
99 memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp));
100 }
101
102 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
103 {
104 memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd));
105 iowrite32(0, &idev->dev_cmd_regs->done);
106 iowrite32(1, &idev->dev_cmd_regs->doorbell);
107 }
108
109
110 void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver)
111 {
112 union ionic_dev_cmd cmd = {
113 .identify.opcode = IONIC_CMD_IDENTIFY,
114 .identify.ver = ver,
115 };
116
117 ionic_dev_cmd_go(idev, &cmd);
118 }
119
120 void ionic_dev_cmd_init(struct ionic_dev *idev)
121 {
122 union ionic_dev_cmd cmd = {
123 .init.opcode = IONIC_CMD_INIT,
124 .init.type = 0,
125 };
126
127 ionic_dev_cmd_go(idev, &cmd);
128 }
129
130 void ionic_dev_cmd_reset(struct ionic_dev *idev)
131 {
132 union ionic_dev_cmd cmd = {
133 .reset.opcode = IONIC_CMD_RESET,
134 };
135
136 ionic_dev_cmd_go(idev, &cmd);
137 }
138
139
140 void ionic_dev_cmd_port_identify(struct ionic_dev *idev)
141 {
142 union ionic_dev_cmd cmd = {
143 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY,
144 .port_init.index = 0,
145 };
146
147 ionic_dev_cmd_go(idev, &cmd);
148 }
149
150 void ionic_dev_cmd_port_init(struct ionic_dev *idev)
151 {
152 union ionic_dev_cmd cmd = {
153 .port_init.opcode = IONIC_CMD_PORT_INIT,
154 .port_init.index = 0,
155 .port_init.info_pa = cpu_to_le64(idev->port_info_pa),
156 };
157
158 ionic_dev_cmd_go(idev, &cmd);
159 }
160
161 void ionic_dev_cmd_port_reset(struct ionic_dev *idev)
162 {
163 union ionic_dev_cmd cmd = {
164 .port_reset.opcode = IONIC_CMD_PORT_RESET,
165 .port_reset.index = 0,
166 };
167
168 ionic_dev_cmd_go(idev, &cmd);
169 }
170
171 void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state)
172 {
173 union ionic_dev_cmd cmd = {
174 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
175 .port_setattr.index = 0,
176 .port_setattr.attr = IONIC_PORT_ATTR_STATE,
177 .port_setattr.state = state,
178 };
179
180 ionic_dev_cmd_go(idev, &cmd);
181 }
182
183 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed)
184 {
185 union ionic_dev_cmd cmd = {
186 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
187 .port_setattr.index = 0,
188 .port_setattr.attr = IONIC_PORT_ATTR_SPEED,
189 .port_setattr.speed = cpu_to_le32(speed),
190 };
191
192 ionic_dev_cmd_go(idev, &cmd);
193 }
194
195 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable)
196 {
197 union ionic_dev_cmd cmd = {
198 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
199 .port_setattr.index = 0,
200 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG,
201 .port_setattr.an_enable = an_enable,
202 };
203
204 ionic_dev_cmd_go(idev, &cmd);
205 }
206
207 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type)
208 {
209 union ionic_dev_cmd cmd = {
210 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
211 .port_setattr.index = 0,
212 .port_setattr.attr = IONIC_PORT_ATTR_FEC,
213 .port_setattr.fec_type = fec_type,
214 };
215
216 ionic_dev_cmd_go(idev, &cmd);
217 }
218
219 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type)
220 {
221 union ionic_dev_cmd cmd = {
222 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
223 .port_setattr.index = 0,
224 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE,
225 .port_setattr.pause_type = pause_type,
226 };
227
228 ionic_dev_cmd_go(idev, &cmd);
229 }
230
231
232 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver)
233 {
234 union ionic_dev_cmd cmd = {
235 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY,
236 .lif_identify.type = type,
237 .lif_identify.ver = ver,
238 };
239
240 ionic_dev_cmd_go(idev, &cmd);
241 }
242
243 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
244 dma_addr_t info_pa)
245 {
246 union ionic_dev_cmd cmd = {
247 .lif_init.opcode = IONIC_CMD_LIF_INIT,
248 .lif_init.index = cpu_to_le16(lif_index),
249 .lif_init.info_pa = cpu_to_le64(info_pa),
250 };
251
252 ionic_dev_cmd_go(idev, &cmd);
253 }
254
255 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index)
256 {
257 union ionic_dev_cmd cmd = {
258 .lif_init.opcode = IONIC_CMD_LIF_RESET,
259 .lif_init.index = cpu_to_le16(lif_index),
260 };
261
262 ionic_dev_cmd_go(idev, &cmd);
263 }
264
265 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq,
266 u16 lif_index, u16 intr_index)
267 {
268 struct ionic_queue *q = &qcq->q;
269 struct ionic_cq *cq = &qcq->cq;
270
271 union ionic_dev_cmd cmd = {
272 .q_init.opcode = IONIC_CMD_Q_INIT,
273 .q_init.lif_index = cpu_to_le16(lif_index),
274 .q_init.type = q->type,
275 .q_init.index = cpu_to_le32(q->index),
276 .q_init.flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
277 IONIC_QINIT_F_ENA),
278 .q_init.pid = cpu_to_le16(q->pid),
279 .q_init.intr_index = cpu_to_le16(intr_index),
280 .q_init.ring_size = ilog2(q->num_descs),
281 .q_init.ring_base = cpu_to_le64(q->base_pa),
282 .q_init.cq_ring_base = cpu_to_le64(cq->base_pa),
283 };
284
285 ionic_dev_cmd_go(idev, &cmd);
286 }
287
288 int ionic_db_page_num(struct ionic_lif *lif, int pid)
289 {
290 return (lif->hw_index * lif->dbid_count) + pid;
291 }
292
293 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
294 struct ionic_intr_info *intr,
295 unsigned int num_descs, size_t desc_size)
296 {
297 struct ionic_cq_info *cur;
298 unsigned int ring_size;
299 unsigned int i;
300
301 if (desc_size == 0 || !is_power_of_2(num_descs))
302 return -EINVAL;
303
304 ring_size = ilog2(num_descs);
305 if (ring_size < 2 || ring_size > 16)
306 return -EINVAL;
307
308 cq->lif = lif;
309 cq->bound_intr = intr;
310 cq->num_descs = num_descs;
311 cq->desc_size = desc_size;
312 cq->tail = cq->info;
313 cq->done_color = 1;
314
315 cur = cq->info;
316
317 for (i = 0; i < num_descs; i++) {
318 if (i + 1 == num_descs) {
319 cur->next = cq->info;
320 cur->last = true;
321 } else {
322 cur->next = cur + 1;
323 }
324 cur->index = i;
325 cur++;
326 }
327
328 return 0;
329 }
330
331 void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa)
332 {
333 struct ionic_cq_info *cur;
334 unsigned int i;
335
336 cq->base = base;
337 cq->base_pa = base_pa;
338
339 for (i = 0, cur = cq->info; i < cq->num_descs; i++, cur++)
340 cur->cq_desc = base + (i * cq->desc_size);
341 }
342
343 void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q)
344 {
345 cq->bound_q = q;
346 }
347
348 unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do,
349 ionic_cq_cb cb, ionic_cq_done_cb done_cb,
350 void *done_arg)
351 {
352 unsigned int work_done = 0;
353
354 if (work_to_do == 0)
355 return 0;
356
357 while (cb(cq, cq->tail)) {
358 if (cq->tail->last)
359 cq->done_color = !cq->done_color;
360 cq->tail = cq->tail->next;
361 DEBUG_STATS_CQE_CNT(cq);
362
363 if (++work_done >= work_to_do)
364 break;
365 }
366
367 if (work_done && done_cb)
368 done_cb(done_arg);
369
370 return work_done;
371 }
372
373 int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
374 struct ionic_queue *q, unsigned int index, const char *name,
375 unsigned int num_descs, size_t desc_size,
376 size_t sg_desc_size, unsigned int pid)
377 {
378 struct ionic_desc_info *cur;
379 unsigned int ring_size;
380 unsigned int i;
381
382 if (desc_size == 0 || !is_power_of_2(num_descs))
383 return -EINVAL;
384
385 ring_size = ilog2(num_descs);
386 if (ring_size < 2 || ring_size > 16)
387 return -EINVAL;
388
389 q->lif = lif;
390 q->idev = idev;
391 q->index = index;
392 q->num_descs = num_descs;
393 q->desc_size = desc_size;
394 q->sg_desc_size = sg_desc_size;
395 q->tail = q->info;
396 q->head = q->tail;
397 q->pid = pid;
398
399 snprintf(q->name, sizeof(q->name), "L%d-%s%u", lif->index, name, index);
400
401 cur = q->info;
402
403 for (i = 0; i < num_descs; i++) {
404 if (i + 1 == num_descs)
405 cur->next = q->info;
406 else
407 cur->next = cur + 1;
408 cur->index = i;
409 cur->left = num_descs - i;
410 cur++;
411 }
412
413 return 0;
414 }
415
416 void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa)
417 {
418 struct ionic_desc_info *cur;
419 unsigned int i;
420
421 q->base = base;
422 q->base_pa = base_pa;
423
424 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++)
425 cur->desc = base + (i * q->desc_size);
426 }
427
428 void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa)
429 {
430 struct ionic_desc_info *cur;
431 unsigned int i;
432
433 q->sg_base = base;
434 q->sg_base_pa = base_pa;
435
436 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++)
437 cur->sg_desc = base + (i * q->sg_desc_size);
438 }
439
440 void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb,
441 void *cb_arg)
442 {
443 struct device *dev = q->lif->ionic->dev;
444 struct ionic_lif *lif = q->lif;
445
446 q->head->cb = cb;
447 q->head->cb_arg = cb_arg;
448 q->head = q->head->next;
449
450 dev_dbg(dev, "lif=%d qname=%s qid=%d qtype=%d p_index=%d ringdb=%d\n",
451 q->lif->index, q->name, q->hw_type, q->hw_index,
452 q->head->index, ring_doorbell);
453
454 if (ring_doorbell)
455 ionic_dbell_ring(lif->kern_dbpage, q->hw_type,
456 q->dbval | q->head->index);
457 }
458
459 static bool ionic_q_is_posted(struct ionic_queue *q, unsigned int pos)
460 {
461 unsigned int mask, tail, head;
462
463 mask = q->num_descs - 1;
464 tail = q->tail->index;
465 head = q->head->index;
466
467 return ((pos - tail) & mask) < ((head - tail) & mask);
468 }
469
470 void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info,
471 unsigned int stop_index)
472 {
473 struct ionic_desc_info *desc_info;
474 ionic_desc_cb cb;
475 void *cb_arg;
476
477
478 if (q->tail->index == q->head->index)
479 return;
480
481
482 if (unlikely(!ionic_q_is_posted(q, stop_index)))
483 dev_err(q->lif->ionic->dev,
484 "ionic stop is not posted %s stop %u tail %u head %u\n",
485 q->name, stop_index, q->tail->index, q->head->index);
486
487 do {
488 desc_info = q->tail;
489 q->tail = desc_info->next;
490
491 cb = desc_info->cb;
492 cb_arg = desc_info->cb_arg;
493
494 desc_info->cb = NULL;
495 desc_info->cb_arg = NULL;
496
497 if (cb)
498 cb(q, desc_info, cq_info, cb_arg);
499 } while (desc_info->index != stop_index);
500 }