1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* FDDI network adapter driver for DEC FDDIcontroller 700/700-C devices.
3 *
4 * Copyright (c) 2018 Maciej W. Rozycki
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * References:
12 *
13 * Dave Sawyer & Phil Weeks & Frank Itkowsky,
14 * "DEC FDDIcontroller 700 Port Specification",
15 * Revision 1.1, Digital Equipment Corporation
16 */
17
18 #include <linux/compiler.h>
19 #include <linux/if_fddi.h>
20 #include <linux/spinlock.h>
21 #include <linux/timer.h>
22 #include <linux/types.h>
23
24 /* IOmem register offsets. */
25 #define FZA_REG_BASE 0x100000 /* register base address */
26 #define FZA_REG_RESET 0x100200 /* reset, r/w */
27 #define FZA_REG_INT_EVENT 0x100400 /* interrupt event, r/w1c */
28 #define FZA_REG_STATUS 0x100402 /* status, r/o */
29 #define FZA_REG_INT_MASK 0x100404 /* interrupt mask, r/w */
30 #define FZA_REG_CONTROL_A 0x100500 /* control A, r/w1s */
31 #define FZA_REG_CONTROL_B 0x100502 /* control B, r/w */
32
33 /* Reset register constants. Bits 1:0 are r/w, others are fixed at 0. */
34 #define FZA_RESET_DLU 0x0002 /* OR with INIT to blast flash memory */
35 #define FZA_RESET_INIT 0x0001 /* switch into the reset state */
36 #define FZA_RESET_CLR 0x0000 /* run self-test and return to work */
37
38 /* Interrupt event register constants. All bits are r/w1c. */
39 #define FZA_EVENT_DLU_DONE 0x0800 /* flash memory write complete */
40 #define FZA_EVENT_FLUSH_TX 0x0400 /* transmit ring flush request */
41 #define FZA_EVENT_PM_PARITY_ERR 0x0200 /* onboard packet memory parity err */
42 #define FZA_EVENT_HB_PARITY_ERR 0x0100 /* host bus parity error */
43 #define FZA_EVENT_NXM_ERR 0x0080 /* non-existent memory access error;
44 * also raised for unaligned and
45 * unsupported partial-word accesses
46 */
47 #define FZA_EVENT_LINK_ST_CHG 0x0040 /* link status change */
48 #define FZA_EVENT_STATE_CHG 0x0020 /* adapter state change */
49 #define FZA_EVENT_UNS_POLL 0x0010 /* unsolicited event service request */
50 #define FZA_EVENT_CMD_DONE 0x0008 /* command done ack */
51 #define FZA_EVENT_SMT_TX_POLL 0x0004 /* SMT frame transmit request */
52 #define FZA_EVENT_RX_POLL 0x0002 /* receive request (packet avail.) */
53 #define FZA_EVENT_TX_DONE 0x0001 /* RMC transmit done ack */
54
55 /* Status register constants. All bits are r/o. */
56 #define FZA_STATUS_DLU_SHIFT 0xc /* down line upgrade status bits */
57 #define FZA_STATUS_DLU_MASK 0x03
58 #define FZA_STATUS_LINK_SHIFT 0xb /* link status bits */
59 #define FZA_STATUS_LINK_MASK 0x01
60 #define FZA_STATUS_STATE_SHIFT 0x8 /* adapter state bits */
61 #define FZA_STATUS_STATE_MASK 0x07
62 #define FZA_STATUS_HALT_SHIFT 0x0 /* halt reason bits */
63 #define FZA_STATUS_HALT_MASK 0xff
64 #define FZA_STATUS_TEST_SHIFT 0x0 /* test failure bits */
65 #define FZA_STATUS_TEST_MASK 0xff
66
67 #define FZA_STATUS_GET_DLU(x) (((x) >> FZA_STATUS_DLU_SHIFT) & \
68 FZA_STATUS_DLU_MASK)
69 #define FZA_STATUS_GET_LINK(x) (((x) >> FZA_STATUS_LINK_SHIFT) & \
70 FZA_STATUS_LINK_MASK)
71 #define FZA_STATUS_GET_STATE(x) (((x) >> FZA_STATUS_STATE_SHIFT) & \
72 FZA_STATUS_STATE_MASK)
73 #define FZA_STATUS_GET_HALT(x) (((x) >> FZA_STATUS_HALT_SHIFT) & \
74 FZA_STATUS_HALT_MASK)
75 #define FZA_STATUS_GET_TEST(x) (((x) >> FZA_STATUS_TEST_SHIFT) & \
76 FZA_STATUS_TEST_MASK)
77
78 #define FZA_DLU_FAILURE 0x0 /* DLU catastrophic error; brain dead */
79 #define FZA_DLU_ERROR 0x1 /* DLU error; old firmware intact */
80 #define FZA_DLU_SUCCESS 0x2 /* DLU OK; new firmware loaded */
81
82 #define FZA_LINK_OFF 0x0 /* link unavailable */
83 #define FZA_LINK_ON 0x1 /* link available */
84
85 #define FZA_STATE_RESET 0x0 /* resetting */
86 #define FZA_STATE_UNINITIALIZED 0x1 /* after a reset */
87 #define FZA_STATE_INITIALIZED 0x2 /* initialized */
88 #define FZA_STATE_RUNNING 0x3 /* running (link active) */
89 #define FZA_STATE_MAINTENANCE 0x4 /* running (link looped back) */
90 #define FZA_STATE_HALTED 0x5 /* halted (error condition) */
91
92 #define FZA_HALT_UNKNOWN 0x00 /* unknown reason */
93 #define FZA_HALT_HOST 0x01 /* host-directed HALT */
94 #define FZA_HALT_HB_PARITY 0x02 /* host bus parity error */
95 #define FZA_HALT_NXM 0x03 /* adapter non-existent memory ref. */
96 #define FZA_HALT_SW 0x04 /* adapter software fault */
97 #define FZA_HALT_HW 0x05 /* adapter hardware fault */
98 #define FZA_HALT_PC_TRACE 0x06 /* PC Trace path test */
99 #define FZA_HALT_DLSW 0x07 /* data link software fault */
100 #define FZA_HALT_DLHW 0x08 /* data link hardware fault */
101
102 #define FZA_TEST_FATAL 0x00 /* self-test catastrophic failure */
103 #define FZA_TEST_68K 0x01 /* 68000 CPU */
104 #define FZA_TEST_SRAM_BWADDR 0x02 /* SRAM byte/word address */
105 #define FZA_TEST_SRAM_DBUS 0x03 /* SRAM data bus */
106 #define FZA_TEST_SRAM_STUCK1 0x04 /* SRAM stuck-at range 1 */
107 #define FZA_TEST_SRAM_STUCK2 0x05 /* SRAM stuck-at range 2 */
108 #define FZA_TEST_SRAM_COUPL1 0x06 /* SRAM coupling range 1 */
109 #define FZA_TEST_SRAM_COUPL2 0x07 /* SRAM coupling */
110 #define FZA_TEST_FLASH_CRC 0x08 /* Flash CRC */
111 #define FZA_TEST_ROM 0x09 /* option ROM */
112 #define FZA_TEST_PHY_CSR 0x0a /* PHY CSR */
113 #define FZA_TEST_MAC_BIST 0x0b /* MAC BiST */
114 #define FZA_TEST_MAC_CSR 0x0c /* MAC CSR */
115 #define FZA_TEST_MAC_ADDR_UNIQ 0x0d /* MAC unique address */
116 #define FZA_TEST_ELM_BIST 0x0e /* ELM BiST */
117 #define FZA_TEST_ELM_CSR 0x0f /* ELM CSR */
118 #define FZA_TEST_ELM_ADDR_UNIQ 0x10 /* ELM unique address */
119 #define FZA_TEST_CAM 0x11 /* CAM */
120 #define FZA_TEST_NIROM 0x12 /* NI ROM checksum */
121 #define FZA_TEST_SC_LOOP 0x13 /* SC loopback packet */
122 #define FZA_TEST_LM_LOOP 0x14 /* LM loopback packet */
123 #define FZA_TEST_EB_LOOP 0x15 /* EB loopback packet */
124 #define FZA_TEST_SC_LOOP_BYPS 0x16 /* SC bypass loopback packet */
125 #define FZA_TEST_LM_LOOP_LOCAL 0x17 /* LM local loopback packet */
126 #define FZA_TEST_EB_LOOP_LOCAL 0x18 /* EB local loopback packet */
127 #define FZA_TEST_CDC_LOOP 0x19 /* CDC loopback packet */
128 #define FZA_TEST_FIBER_LOOP 0x1A /* FIBER loopback packet */
129 #define FZA_TEST_CAM_MATCH_LOOP 0x1B /* CAM match packet loopback */
130 #define FZA_TEST_68K_IRQ_STUCK 0x1C /* 68000 interrupt line stuck-at */
131 #define FZA_TEST_IRQ_PRESENT 0x1D /* interrupt present register */
132 #define FZA_TEST_RMC_BIST 0x1E /* RMC BiST */
133 #define FZA_TEST_RMC_CSR 0x1F /* RMC CSR */
134 #define FZA_TEST_RMC_ADDR_UNIQ 0x20 /* RMC unique address */
135 #define FZA_TEST_PM_DPATH 0x21 /* packet memory data path */
136 #define FZA_TEST_PM_ADDR 0x22 /* packet memory address */
137 #define FZA_TEST_RES_23 0x23 /* reserved */
138 #define FZA_TEST_PM_DESC 0x24 /* packet memory descriptor */
139 #define FZA_TEST_PM_OWN 0x25 /* packet memory own bit */
140 #define FZA_TEST_PM_PARITY 0x26 /* packet memory parity */
141 #define FZA_TEST_PM_BSWAP 0x27 /* packet memory byte swap */
142 #define FZA_TEST_PM_WSWAP 0x28 /* packet memory word swap */
143 #define FZA_TEST_PM_REF 0x29 /* packet memory refresh */
144 #define FZA_TEST_PM_CSR 0x2A /* PM CSR */
145 #define FZA_TEST_PORT_STATUS 0x2B /* port status register */
146 #define FZA_TEST_HOST_IRQMASK 0x2C /* host interrupt mask */
147 #define FZA_TEST_TIMER_IRQ1 0x2D /* RTOS timer */
148 #define FZA_TEST_FORCE_IRQ1 0x2E /* force RTOS IRQ1 */
149 #define FZA_TEST_TIMER_IRQ5 0x2F /* IRQ5 backoff timer */
150 #define FZA_TEST_FORCE_IRQ5 0x30 /* force IRQ5 */
151 #define FZA_TEST_RES_31 0x31 /* reserved */
152 #define FZA_TEST_IC_PRIO 0x32 /* interrupt controller priority */
153 #define FZA_TEST_PM_FULL 0x33 /* full packet memory */
154 #define FZA_TEST_PMI_DMA 0x34 /* PMI DMA */
155
156 /* Interrupt mask register constants. All bits are r/w. */
157 #define FZA_MASK_RESERVED 0xf000 /* unused */
158 #define FZA_MASK_DLU_DONE 0x0800 /* flash memory write complete */
159 #define FZA_MASK_FLUSH_TX 0x0400 /* transmit ring flush request */
160 #define FZA_MASK_PM_PARITY_ERR 0x0200 /* onboard packet memory parity error
161 */
162 #define FZA_MASK_HB_PARITY_ERR 0x0100 /* host bus parity error */
163 #define FZA_MASK_NXM_ERR 0x0080 /* adapter non-existent memory
164 * reference
165 */
166 #define FZA_MASK_LINK_ST_CHG 0x0040 /* link status change */
167 #define FZA_MASK_STATE_CHG 0x0020 /* adapter state change */
168 #define FZA_MASK_UNS_POLL 0x0010 /* unsolicited event service request */
169 #define FZA_MASK_CMD_DONE 0x0008 /* command ring entry processed */
170 #define FZA_MASK_SMT_TX_POLL 0x0004 /* SMT frame transmit request */
171 #define FZA_MASK_RCV_POLL 0x0002 /* receive request (packet available)
172 */
173 #define FZA_MASK_TX_DONE 0x0001 /* RMC transmit done acknowledge */
174
175 /* Which interrupts to receive: 0/1 is mask/unmask. */
176 #define FZA_MASK_NONE 0x0000
177 #define FZA_MASK_NORMAL \
178 ((~(FZA_MASK_RESERVED | FZA_MASK_DLU_DONE | \
179 FZA_MASK_PM_PARITY_ERR | FZA_MASK_HB_PARITY_ERR | \
180 FZA_MASK_NXM_ERR)) & 0xffff)
181
182 /* Control A register constants. */
183 #define FZA_CONTROL_A_HB_PARITY_ERR 0x8000 /* host bus parity error */
184 #define FZA_CONTROL_A_NXM_ERR 0x4000 /* adapter non-existent memory
185 * reference
186 */
187 #define FZA_CONTROL_A_SMT_RX_OVFL 0x0040 /* SMT receive overflow */
188 #define FZA_CONTROL_A_FLUSH_DONE 0x0020 /* flush tx request complete */
189 #define FZA_CONTROL_A_SHUT 0x0010 /* turn the interface off */
190 #define FZA_CONTROL_A_HALT 0x0008 /* halt the controller */
191 #define FZA_CONTROL_A_CMD_POLL 0x0004 /* command ring poll */
192 #define FZA_CONTROL_A_SMT_RX_POLL 0x0002 /* SMT receive ring poll */
193 #define FZA_CONTROL_A_TX_POLL 0x0001 /* transmit poll */
194
195 /* Control B register constants. All bits are r/w.
196 *
197 * Possible values:
198 * 0x0000 after booting into REX,
199 * 0x0003 after issuing `boot #/mop'.
200 */
201 #define FZA_CONTROL_B_CONSOLE 0x0002 /* OR with DRIVER for console
202 * (TC firmware) mode
203 */
204 #define FZA_CONTROL_B_DRIVER 0x0001 /* driver mode */
205 #define FZA_CONTROL_B_IDLE 0x0000 /* no driver installed */
206
207 #define FZA_RESET_PAD \
208 (FZA_REG_RESET - FZA_REG_BASE)
209 #define FZA_INT_EVENT_PAD \
210 (FZA_REG_INT_EVENT - FZA_REG_RESET - sizeof(u16))
211 #define FZA_CONTROL_A_PAD \
212 (FZA_REG_CONTROL_A - FZA_REG_INT_MASK - sizeof(u16))
213
214 /* Layout of registers. */
215 struct fza_regs {
216 u8 pad0[FZA_RESET_PAD];
217 u16 reset; /* reset register */
218 u8 pad1[FZA_INT_EVENT_PAD];
219 u16 int_event; /* interrupt event register */
220 u16 status; /* status register */
221 u16 int_mask; /* interrupt mask register */
222 u8 pad2[FZA_CONTROL_A_PAD];
223 u16 control_a; /* control A register */
224 u16 control_b; /* control B register */
225 };
226
227 /* Command descriptor ring entry. */
228 struct fza_ring_cmd {
229 u32 cmd_own; /* bit 31: ownership, bits [30:0]: command */
230 u32 stat; /* command status */
231 u32 buffer; /* address of the buffer in the FZA space */
232 u32 pad0;
233 };
234
235 #define FZA_RING_CMD 0x200400 /* command ring address */
236 #define FZA_RING_CMD_SIZE 0x40 /* command descriptor ring
237 * size
238 */
239 /* Command constants. */
240 #define FZA_RING_CMD_MASK 0x7fffffff
241 #define FZA_RING_CMD_NOP 0x00000000 /* nop */
242 #define FZA_RING_CMD_INIT 0x00000001 /* initialize */
243 #define FZA_RING_CMD_MODCAM 0x00000002 /* modify CAM */
244 #define FZA_RING_CMD_PARAM 0x00000003 /* set system parameters */
245 #define FZA_RING_CMD_MODPROM 0x00000004 /* modify promiscuous mode */
246 #define FZA_RING_CMD_SETCHAR 0x00000005 /* set link characteristics */
247 #define FZA_RING_CMD_RDCNTR 0x00000006 /* read counters */
248 #define FZA_RING_CMD_STATUS 0x00000007 /* get link status */
249 #define FZA_RING_CMD_RDCAM 0x00000008 /* read CAM */
250
251 /* Command status constants. */
252 #define FZA_RING_STAT_SUCCESS 0x00000000
253
254 /* Unsolicited event descriptor ring entry. */
255 struct fza_ring_uns {
256 u32 own; /* bit 31: ownership, bits [30:0]: reserved */
257 u32 id; /* event ID */
258 u32 buffer; /* address of the buffer in the FZA space */
259 u32 pad0; /* reserved */
260 };
261
262 #define FZA_RING_UNS 0x200800 /* unsolicited ring address */
263 #define FZA_RING_UNS_SIZE 0x40 /* unsolicited descriptor ring
264 * size
265 */
266 /* Unsolicited event constants. */
267 #define FZA_RING_UNS_UND 0x00000000 /* undefined event ID */
268 #define FZA_RING_UNS_INIT_IN 0x00000001 /* ring init initiated */
269 #define FZA_RING_UNS_INIT_RX 0x00000002 /* ring init received */
270 #define FZA_RING_UNS_BEAC_IN 0x00000003 /* ring beaconing initiated */
271 #define FZA_RING_UNS_DUP_ADDR 0x00000004 /* duplicate address detected */
272 #define FZA_RING_UNS_DUP_TOK 0x00000005 /* duplicate token detected */
273 #define FZA_RING_UNS_PURG_ERR 0x00000006 /* ring purger error */
274 #define FZA_RING_UNS_STRIP_ERR 0x00000007 /* bridge strip error */
275 #define FZA_RING_UNS_OP_OSC 0x00000008 /* ring op oscillation */
276 #define FZA_RING_UNS_BEAC_RX 0x00000009 /* directed beacon received */
277 #define FZA_RING_UNS_PCT_IN 0x0000000a /* PC trace initiated */
278 #define FZA_RING_UNS_PCT_RX 0x0000000b /* PC trace received */
279 #define FZA_RING_UNS_TX_UNDER 0x0000000c /* transmit underrun */
280 #define FZA_RING_UNS_TX_FAIL 0x0000000d /* transmit failure */
281 #define FZA_RING_UNS_RX_OVER 0x0000000e /* receive overrun */
282
283 /* RMC (Ring Memory Control) transmit descriptor ring entry. */
284 struct fza_ring_rmc_tx {
285 u32 rmc; /* RMC information */
286 u32 avl; /* available for host (unused by RMC) */
287 u32 own; /* bit 31: ownership, bits [30:0]: reserved */
288 u32 pad0; /* reserved */
289 };
290
291 #define FZA_TX_BUFFER_ADDR(x) (0x200000 | (((x) & 0xffff) << 5))
292 #define FZA_TX_BUFFER_SIZE 512
293 struct fza_buffer_tx {
294 u32 data[FZA_TX_BUFFER_SIZE / sizeof(u32)];
295 };
296
297 /* Transmit ring RMC constants. */
298 #define FZA_RING_TX_SOP 0x80000000 /* start of packet */
299 #define FZA_RING_TX_EOP 0x40000000 /* end of packet */
300 #define FZA_RING_TX_DTP 0x20000000 /* discard this packet */
301 #define FZA_RING_TX_VBC 0x10000000 /* valid buffer byte count */
302 #define FZA_RING_TX_DCC_MASK 0x0f000000 /* DMA completion code */
303 #define FZA_RING_TX_DCC_SUCCESS 0x01000000 /* transmit succeeded */
304 #define FZA_RING_TX_DCC_DTP_SOP 0x02000000 /* DTP set at SOP */
305 #define FZA_RING_TX_DCC_DTP 0x04000000 /* DTP set within packet */
306 #define FZA_RING_TX_DCC_ABORT 0x05000000 /* MAC-requested abort */
307 #define FZA_RING_TX_DCC_PARITY 0x06000000 /* xmit data parity error */
308 #define FZA_RING_TX_DCC_UNDRRUN 0x07000000 /* transmit underrun */
309 #define FZA_RING_TX_XPO_MASK 0x003fe000 /* transmit packet offset */
310
311 /* Host receive descriptor ring entry. */
312 struct fza_ring_hst_rx {
313 u32 buf0_own; /* bit 31: ownership, bits [30:23]: unused,
314 * bits [22:0]: right-shifted address of the
315 * buffer in system memory (low buffer)
316 */
317 u32 buffer1; /* bits [31:23]: unused,
318 * bits [22:0]: right-shifted address of the
319 * buffer in system memory (high buffer)
320 */
321 u32 rmc; /* RMC information */
322 u32 pad0;
323 };
324
325 #define FZA_RX_BUFFER_SIZE (4096 + 512) /* buffer length */
326
327 /* Receive ring RMC constants. */
328 #define FZA_RING_RX_SOP 0x80000000 /* start of packet */
329 #define FZA_RING_RX_EOP 0x40000000 /* end of packet */
330 #define FZA_RING_RX_FSC_MASK 0x38000000 /* # of frame status bits */
331 #define FZA_RING_RX_FSB_MASK 0x07c00000 /* frame status bits */
332 #define FZA_RING_RX_FSB_ERR 0x04000000 /* error detected */
333 #define FZA_RING_RX_FSB_ADDR 0x02000000 /* address recognized */
334 #define FZA_RING_RX_FSB_COP 0x01000000 /* frame copied */
335 #define FZA_RING_RX_FSB_F0 0x00800000 /* first additional flag */
336 #define FZA_RING_RX_FSB_F1 0x00400000 /* second additional flag */
337 #define FZA_RING_RX_BAD 0x00200000 /* bad packet */
338 #define FZA_RING_RX_CRC 0x00100000 /* CRC error */
339 #define FZA_RING_RX_RRR_MASK 0x000e0000 /* MAC receive status bits */
340 #define FZA_RING_RX_RRR_OK 0x00000000 /* receive OK */
341 #define FZA_RING_RX_RRR_SADDR 0x00020000 /* source address matched */
342 #define FZA_RING_RX_RRR_DADDR 0x00040000 /* dest address not matched */
343 #define FZA_RING_RX_RRR_ABORT 0x00060000 /* RMC abort */
344 #define FZA_RING_RX_RRR_LENGTH 0x00080000 /* invalid length */
345 #define FZA_RING_RX_RRR_FRAG 0x000a0000 /* fragment */
346 #define FZA_RING_RX_RRR_FORMAT 0x000c0000 /* format error */
347 #define FZA_RING_RX_RRR_RESET 0x000e0000 /* MAC reset */
348 #define FZA_RING_RX_DA_MASK 0x00018000 /* daddr match status bits */
349 #define FZA_RING_RX_DA_NONE 0x00000000 /* no match */
350 #define FZA_RING_RX_DA_PROM 0x00008000 /* promiscuous match */
351 #define FZA_RING_RX_DA_CAM 0x00010000 /* CAM entry match */
352 #define FZA_RING_RX_DA_LOCAL 0x00018000 /* link addr or LLC bcast */
353 #define FZA_RING_RX_SA_MASK 0x00006000 /* saddr match status bits */
354 #define FZA_RING_RX_SA_NONE 0x00000000 /* no match */
355 #define FZA_RING_RX_SA_ALIAS 0x00002000 /* alias address match */
356 #define FZA_RING_RX_SA_CAM 0x00004000 /* CAM entry match */
357 #define FZA_RING_RX_SA_LOCAL 0x00006000 /* link address match */
358
359 /* SMT (Station Management) transmit/receive descriptor ring entry. */
360 struct fza_ring_smt {
361 u32 own; /* bit 31: ownership, bits [30:0]: unused */
362 u32 rmc; /* RMC information */
363 u32 buffer; /* address of the buffer */
364 u32 pad0; /* reserved */
365 };
366
367 /* Ownership constants.
368 *
369 * Only an owner is permitted to process a given ring entry.
370 * RMC transmit ring meanings are reversed.
371 */
372 #define FZA_RING_OWN_MASK 0x80000000
373 #define FZA_RING_OWN_FZA 0x00000000 /* permit FZA, forbid host */
374 #define FZA_RING_OWN_HOST 0x80000000 /* permit host, forbid FZA */
375 #define FZA_RING_TX_OWN_RMC 0x80000000 /* permit RMC, forbid host */
376 #define FZA_RING_TX_OWN_HOST 0x00000000 /* permit host, forbid RMC */
377
378 /* RMC constants. */
379 #define FZA_RING_PBC_MASK 0x00001fff /* frame length */
380
381 /* Layout of counter buffers. */
382
383 struct fza_counter {
384 u32 msw;
385 u32 lsw;
386 };
387
388 struct fza_counters {
389 struct fza_counter sys_buf; /* system buffer unavailable */
390 struct fza_counter tx_under; /* transmit underruns */
391 struct fza_counter tx_fail; /* transmit failures */
392 struct fza_counter rx_over; /* receive data overruns */
393 struct fza_counter frame_cnt; /* frame count */
394 struct fza_counter error_cnt; /* error count */
395 struct fza_counter lost_cnt; /* lost count */
396 struct fza_counter rinit_in; /* ring initialization initiated */
397 struct fza_counter rinit_rx; /* ring initialization received */
398 struct fza_counter beac_in; /* ring beacon initiated */
399 struct fza_counter dup_addr; /* duplicate address test failures */
400 struct fza_counter dup_tok; /* duplicate token detected */
401 struct fza_counter purg_err; /* ring purge errors */
402 struct fza_counter strip_err; /* bridge strip errors */
403 struct fza_counter pct_in; /* traces initiated */
404 struct fza_counter pct_rx; /* traces received */
405 struct fza_counter lem_rej; /* LEM rejects */
406 struct fza_counter tne_rej; /* TNE expiry rejects */
407 struct fza_counter lem_event; /* LEM events */
408 struct fza_counter lct_rej; /* LCT rejects */
409 struct fza_counter conn_cmpl; /* connections completed */
410 struct fza_counter el_buf; /* elasticity buffer errors */
411 };
412
413 /* Layout of command buffers. */
414
415 /* INIT command buffer.
416 *
417 * Values of default link parameters given are as obtained from a
418 * DEFZA-AA rev. C03 board. The board counts time in units of 80ns.
419 */
420 struct fza_cmd_init {
421 u32 tx_mode; /* transmit mode */
422 u32 hst_rx_size; /* host receive ring entries */
423
424 struct fza_counters counters; /* counters */
425
426 u8 rmc_rev[4]; /* RMC revision */
427 u8 rom_rev[4]; /* ROM revision */
428 u8 fw_rev[4]; /* firmware revision */
429
430 u32 mop_type; /* MOP device type */
431
432 u32 hst_rx; /* base of host rx descriptor ring */
433 u32 rmc_tx; /* base of RMC tx descriptor ring */
434 u32 rmc_tx_size; /* size of RMC tx descriptor ring */
435 u32 smt_tx; /* base of SMT tx descriptor ring */
436 u32 smt_tx_size; /* size of SMT tx descriptor ring */
437 u32 smt_rx; /* base of SMT rx descriptor ring */
438 u32 smt_rx_size; /* size of SMT rx descriptor ring */
439
440 u32 hw_addr[2]; /* link address */
441
442 u32 def_t_req; /* default Requested TTRT (T_REQ) --
443 * C03: 100000 [80ns]
444 */
445 u32 def_tvx; /* default Valid Transmission Time
446 * (TVX) -- C03: 32768 [80ns]
447 */
448 u32 def_t_max; /* default Maximum TTRT (T_MAX) --
449 * C03: 2162688 [80ns]
450 */
451 u32 lem_threshold; /* default LEM threshold -- C03: 8 */
452 u32 def_station_id[2]; /* default station ID */
453
454 u32 pmd_type_alt; /* alternative PMD type code */
455
456 u32 smt_ver; /* SMT version */
457
458 u32 rtoken_timeout; /* default restricted token timeout
459 * -- C03: 12500000 [80ns]
460 */
461 u32 ring_purger; /* default ring purger enable --
462 * C03: 1
463 */
464
465 u32 smt_ver_max; /* max SMT version ID */
466 u32 smt_ver_min; /* min SMT version ID */
467 u32 pmd_type; /* PMD type code */
468 };
469
470 /* INIT command PMD type codes. */
471 #define FZA_PMD_TYPE_MMF 0 /* Multimode fiber */
472 #define FZA_PMD_TYPE_TW 101 /* ThinWire */
473 #define FZA_PMD_TYPE_STP 102 /* STP */
474
475 /* MODCAM/RDCAM command buffer. */
476 #define FZA_CMD_CAM_SIZE 64 /* CAM address entry count */
477 struct fza_cmd_cam {
478 u32 hw_addr[FZA_CMD_CAM_SIZE][2]; /* CAM address entries */
479 };
480
481 /* PARAM command buffer.
482 *
483 * Permitted ranges given are as defined by the spec and obtained from a
484 * DEFZA-AA rev. C03 board, respectively. The rtoken_timeout field is
485 * erroneously interpreted in units of ms.
486 */
487 struct fza_cmd_param {
488 u32 loop_mode; /* loopback mode */
489 u32 t_max; /* Maximum TTRT (T_MAX)
490 * def: ??? [80ns]
491 * C03: [t_req+1,4294967295] [80ns]
492 */
493 u32 t_req; /* Requested TTRT (T_REQ)
494 * def: [50000,2097151] [80ns]
495 * C03: [50001,t_max-1] [80ns]
496 */
497 u32 tvx; /* Valid Transmission Time (TVX)
498 * def: [29375,65280] [80ns]
499 * C03: [29376,65279] [80ns]
500 */
501 u32 lem_threshold; /* LEM threshold */
502 u32 station_id[2]; /* station ID */
503 u32 rtoken_timeout; /* restricted token timeout
504 * def: [0,125000000] [80ns]
505 * C03: [0,9999] [ms]
506 */
507 u32 ring_purger; /* ring purger enable: 0|1 */
508 };
509
510 /* Loopback modes for the PARAM command. */
511 #define FZA_LOOP_NORMAL 0
512 #define FZA_LOOP_INTERN 1
513 #define FZA_LOOP_EXTERN 2
514
515 /* MODPROM command buffer. */
516 struct fza_cmd_modprom {
517 u32 llc_prom; /* LLC promiscuous enable */
518 u32 smt_prom; /* SMT promiscuous enable */
519 u32 llc_multi; /* LLC multicast promiscuous enable */
520 u32 llc_bcast; /* LLC broadcast promiscuous enable */
521 };
522
523 /* SETCHAR command buffer.
524 *
525 * Permitted ranges are as for the PARAM command.
526 */
527 struct fza_cmd_setchar {
528 u32 t_max; /* Maximum TTRT (T_MAX) */
529 u32 t_req; /* Requested TTRT (T_REQ) */
530 u32 tvx; /* Valid Transmission Time (TVX) */
531 u32 lem_threshold; /* LEM threshold */
532 u32 rtoken_timeout; /* restricted token timeout */
533 u32 ring_purger; /* ring purger enable */
534 };
535
536 /* RDCNTR command buffer. */
537 struct fza_cmd_rdcntr {
538 struct fza_counters counters; /* counters */
539 };
540
541 /* STATUS command buffer. */
542 struct fza_cmd_status {
543 u32 led_state; /* LED state */
544 u32 rmt_state; /* ring management state */
545 u32 link_state; /* link state */
546 u32 dup_addr; /* duplicate address flag */
547 u32 ring_purger; /* ring purger state */
548 u32 t_neg; /* negotiated TTRT [80ns] */
549 u32 una[2]; /* upstream neighbour address */
550 u32 una_timeout; /* UNA timed out */
551 u32 strip_mode; /* frame strip mode */
552 u32 yield_mode; /* claim token yield mode */
553 u32 phy_state; /* PHY state */
554 u32 neigh_phy; /* neighbour PHY type */
555 u32 reject; /* reject reason */
556 u32 phy_lee; /* PHY link error estimate [-log10] */
557 u32 una_old[2]; /* old upstream neighbour address */
558 u32 rmt_mac; /* remote MAC indicated */
559 u32 ring_err; /* ring error reason */
560 u32 beac_rx[2]; /* sender of last directed beacon */
561 u32 un_dup_addr; /* upstream neighbr dup address flag */
562 u32 dna[2]; /* downstream neighbour address */
563 u32 dna_old[2]; /* old downstream neighbour address */
564 };
565
566 /* Common command buffer. */
567 union fza_cmd_buf {
568 struct fza_cmd_init init;
569 struct fza_cmd_cam cam;
570 struct fza_cmd_param param;
571 struct fza_cmd_modprom modprom;
572 struct fza_cmd_setchar setchar;
573 struct fza_cmd_rdcntr rdcntr;
574 struct fza_cmd_status status;
575 };
576
577 /* MAC (Media Access Controller) chip packet request header constants. */
578
579 /* Packet request header byte #0. */
580 #define FZA_PRH0_FMT_TYPE_MASK 0xc0 /* type of packet, always zero */
581 #define FZA_PRH0_TOK_TYPE_MASK 0x30 /* type of token required
582 * to send this frame
583 */
584 #define FZA_PRH0_TKN_TYPE_ANY 0x30 /* use either token type */
585 #define FZA_PRH0_TKN_TYPE_UNR 0x20 /* use an unrestricted token */
586 #define FZA_PRH0_TKN_TYPE_RST 0x10 /* use a restricted token */
587 #define FZA_PRH0_TKN_TYPE_IMM 0x00 /* send immediately, no token required
588 */
589 #define FZA_PRH0_FRAME_MASK 0x08 /* type of frame to send */
590 #define FZA_PRH0_FRAME_SYNC 0x08 /* send a synchronous frame */
591 #define FZA_PRH0_FRAME_ASYNC 0x00 /* send an asynchronous frame */
592 #define FZA_PRH0_MODE_MASK 0x04 /* send mode */
593 #define FZA_PRH0_MODE_IMMED 0x04 /* an immediate mode, send regardless
594 * of the ring operational state
595 */
596 #define FZA_PRH0_MODE_NORMAL 0x00 /* a normal mode, send only if ring
597 * operational
598 */
599 #define FZA_PRH0_SF_MASK 0x02 /* send frame first */
600 #define FZA_PRH0_SF_FIRST 0x02 /* send this frame first
601 * with this token capture
602 */
603 #define FZA_PRH0_SF_NORMAL 0x00 /* treat this frame normally */
604 #define FZA_PRH0_BCN_MASK 0x01 /* beacon frame */
605 #define FZA_PRH0_BCN_BEACON 0x01 /* send the frame only
606 * if in the beacon state
607 */
608 #define FZA_PRH0_BCN_DATA 0x01 /* send the frame only
609 * if in the data state
610 */
611 /* Packet request header byte #1. */
612 /* bit 7 always zero */
613 #define FZA_PRH1_SL_MASK 0x40 /* send frame last */
614 #define FZA_PRH1_SL_LAST 0x40 /* send this frame last, releasing
615 * the token afterwards
616 */
617 #define FZA_PRH1_SL_NORMAL 0x00 /* treat this frame normally */
618 #define FZA_PRH1_CRC_MASK 0x20 /* CRC append */
619 #define FZA_PRH1_CRC_NORMAL 0x20 /* calculate the CRC and append it
620 * as the FCS field to the frame
621 */
622 #define FZA_PRH1_CRC_SKIP 0x00 /* leave the frame as is */
623 #define FZA_PRH1_TKN_SEND_MASK 0x18 /* type of token to send after the
624 * frame if this is the last frame
625 */
626 #define FZA_PRH1_TKN_SEND_ORIG 0x18 /* send a token of the same type as the
627 * originally captured one
628 */
629 #define FZA_PRH1_TKN_SEND_RST 0x10 /* send a restricted token */
630 #define FZA_PRH1_TKN_SEND_UNR 0x08 /* send an unrestricted token */
631 #define FZA_PRH1_TKN_SEND_NONE 0x00 /* send no token */
632 #define FZA_PRH1_EXTRA_FS_MASK 0x07 /* send extra frame status indicators
633 */
634 #define FZA_PRH1_EXTRA_FS_ST 0x07 /* TR RR ST II */
635 #define FZA_PRH1_EXTRA_FS_SS 0x06 /* TR RR SS II */
636 #define FZA_PRH1_EXTRA_FS_SR 0x05 /* TR RR SR II */
637 #define FZA_PRH1_EXTRA_FS_NONE1 0x04 /* TR RR II II */
638 #define FZA_PRH1_EXTRA_FS_RT 0x03 /* TR RR RT II */
639 #define FZA_PRH1_EXTRA_FS_RS 0x02 /* TR RR RS II */
640 #define FZA_PRH1_EXTRA_FS_RR 0x01 /* TR RR RR II */
641 #define FZA_PRH1_EXTRA_FS_NONE 0x00 /* TR RR II II */
642 /* Packet request header byte #2. */
643 #define FZA_PRH2_NORMAL 0x00 /* always zero */
644
645 /* PRH used for LLC frames. */
646 #define FZA_PRH0_LLC (FZA_PRH0_TKN_TYPE_UNR)
647 #define FZA_PRH1_LLC (FZA_PRH1_CRC_NORMAL | FZA_PRH1_TKN_SEND_UNR)
648 #define FZA_PRH2_LLC (FZA_PRH2_NORMAL)
649
650 /* PRH used for SMT frames. */
651 #define FZA_PRH0_SMT (FZA_PRH0_TKN_TYPE_UNR)
652 #define FZA_PRH1_SMT (FZA_PRH1_CRC_NORMAL | FZA_PRH1_TKN_SEND_UNR)
653 #define FZA_PRH2_SMT (FZA_PRH2_NORMAL)
654
655 #if ((FZA_RING_RX_SIZE) < 2) || ((FZA_RING_RX_SIZE) > 256)
656 # error FZA_RING_RX_SIZE has to be from 2 up to 256
657 #endif
658 #if ((FZA_RING_TX_MODE) != 0) && ((FZA_RING_TX_MODE) != 1)
659 # error FZA_RING_TX_MODE has to be either 0 or 1
660 #endif
661
662 #define FZA_RING_TX_SIZE (512 << (FZA_RING_TX_MODE))
663
664 struct fza_private {
665 struct device *bdev; /* pointer to the bus device */
666 const char *name; /* printable device name */
667 void __iomem *mmio; /* MMIO ioremap cookie */
668 struct fza_regs __iomem *regs; /* pointer to FZA registers */
669
670 struct sk_buff *rx_skbuff[FZA_RING_RX_SIZE];
671 /* all skbs assigned to the host
672 * receive descriptors
673 */
674 dma_addr_t rx_dma[FZA_RING_RX_SIZE];
675 /* their corresponding DMA addresses */
676
677 struct fza_ring_cmd __iomem *ring_cmd;
678 /* pointer to the command descriptor
679 * ring
680 */
681 int ring_cmd_index; /* index to the command descriptor ring
682 * for the next command
683 */
684 struct fza_ring_uns __iomem *ring_uns;
685 /* pointer to the unsolicited
686 * descriptor ring
687 */
688 int ring_uns_index; /* index to the unsolicited descriptor
689 * ring for the next event
690 */
691
692 struct fza_ring_rmc_tx __iomem *ring_rmc_tx;
693 /* pointer to the RMC transmit
694 * descriptor ring (obtained from the
695 * INIT command)
696 */
697 int ring_rmc_tx_size; /* number of entries in the RMC
698 * transmit descriptor ring (obtained
699 * from the INIT command)
700 */
701 int ring_rmc_tx_index; /* index to the RMC transmit descriptor
702 * ring for the next transmission
703 */
704 int ring_rmc_txd_index; /* index to the RMC transmit descriptor
705 * ring for the next transmit done
706 * acknowledge
707 */
708
709 struct fza_ring_hst_rx __iomem *ring_hst_rx;
710 /* pointer to the host receive
711 * descriptor ring (obtained from the
712 * INIT command)
713 */
714 int ring_hst_rx_size; /* number of entries in the host
715 * receive descriptor ring (set by the
716 * INIT command)
717 */
718 int ring_hst_rx_index; /* index to the host receive descriptor
719 * ring for the next transmission
720 */
721
722 struct fza_ring_smt __iomem *ring_smt_tx;
723 /* pointer to the SMT transmit
724 * descriptor ring (obtained from the
725 * INIT command)
726 */
727 int ring_smt_tx_size; /* number of entries in the SMT
728 * transmit descriptor ring (obtained
729 * from the INIT command)
730 */
731 int ring_smt_tx_index; /* index to the SMT transmit descriptor
732 * ring for the next transmission
733 */
734
735 struct fza_ring_smt __iomem *ring_smt_rx;
736 /* pointer to the SMT transmit
737 * descriptor ring (obtained from the
738 * INIT command)
739 */
740 int ring_smt_rx_size; /* number of entries in the SMT
741 * receive descriptor ring (obtained
742 * from the INIT command)
743 */
744 int ring_smt_rx_index; /* index to the SMT receive descriptor
745 * ring for the next transmission
746 */
747
748 struct fza_buffer_tx __iomem *buffer_tx;
749 /* pointer to the RMC transmit buffers
750 */
751
752 uint state; /* adapter expected state */
753
754 spinlock_t lock; /* for device & private data access */
755 uint int_mask; /* interrupt source selector */
756
757 int cmd_done_flag; /* command completion trigger */
758 wait_queue_head_t cmd_done_wait;
759
760 int state_chg_flag; /* state change trigger */
761 wait_queue_head_t state_chg_wait;
762
763 struct timer_list reset_timer; /* RESET time-out trigger */
764 int timer_state; /* RESET trigger state */
765
766 int queue_active; /* whether to enable queueing */
767
768 struct net_device_stats stats;
769
770 uint irq_count_flush_tx; /* transmit flush irqs */
771 uint irq_count_uns_poll; /* unsolicited event irqs */
772 uint irq_count_smt_tx_poll; /* SMT transmit irqs */
773 uint irq_count_rx_poll; /* host receive irqs */
774 uint irq_count_tx_done; /* transmit done irqs */
775 uint irq_count_cmd_done; /* command done irqs */
776 uint irq_count_state_chg; /* state change irqs */
777 uint irq_count_link_st_chg; /* link status change irqs */
778
779 uint t_max; /* T_MAX */
780 uint t_req; /* T_REQ */
781 uint tvx; /* TVX */
782 uint lem_threshold; /* LEM threshold */
783 uint station_id[2]; /* station ID */
784 uint rtoken_timeout; /* restricted token timeout */
785 uint ring_purger; /* ring purger enable flag */
786 };
787
788 struct fza_fddihdr {
789 u8 pa[2]; /* preamble */
790 u8 sd; /* starting delimiter */
791 struct fddihdr hdr;
792 } __packed;